1 /**
2 ******************************************************************************
3 * @file stm32wbaxx_ll_dma.h
4 * @author MCD Application Team
5 * @brief Header file of DMA LL module.
6 ******************************************************************************
7 * @attention
8 *
9 * Copyright (c) 2022 STMicroelectronics.
10 * All rights reserved.
11 *
12 * This software is licensed under terms that can be found in the LICENSE file
13 * in the root directory of this software component.
14 * If no LICENSE file comes with this software, it is provided AS-IS.
15 *
16 ******************************************************************************
17 @verbatim
18 ==============================================================================
19 ##### LL DMA driver acronyms #####
20 ==============================================================================
21 [..] Acronyms table :
22 =========================================
23 || Acronym || ||
24 =========================================
25 || SRC || Source ||
26 || DEST || Destination ||
27 || ADDR || Address ||
28 || ADDRS || Addresses ||
29 || INC || Increment / Incremented ||
30 || DEC || Decrement / Decremented ||
31 || BLK || Block ||
32 || RPT || Repeat / Repeated ||
33 || TRIG || Trigger ||
34 =========================================
35 @endverbatim
36 ******************************************************************************
37 */
38
39 /* Define to prevent recursive inclusion -------------------------------------*/
40 #ifndef STM32WBAxx_LL_DMA_H
41 #define STM32WBAxx_LL_DMA_H
42
43 #ifdef __cplusplus
44 extern "C" {
45 #endif /* __cplusplus */
46
47 /* Includes ------------------------------------------------------------------*/
48 #include "stm32wbaxx.h"
49
50 /** @addtogroup STM32WBAxx_LL_Driver
51 * @{
52 */
53
54 #if defined (GPDMA1)
55
56 /** @defgroup DMA_LL DMA
57 * @{
58 */
59
60 /* Private types -------------------------------------------------------------*/
61 /* Private variables ---------------------------------------------------------*/
62
63 /** @defgroup DMA_LL_Private_Variables DMA Private Variables
64 * @{
65 */
66 #define DMA_CHANNEL0_OFFSET (0x00000050UL)
67 #define DMA_CHANNEL1_OFFSET (0x000000D0UL)
68 #define DMA_CHANNEL2_OFFSET (0x00000150UL)
69 #define DMA_CHANNEL3_OFFSET (0x000001D0UL)
70 #define DMA_CHANNEL4_OFFSET (0x00000250UL)
71 #define DMA_CHANNEL5_OFFSET (0x000002D0UL)
72 #define DMA_CHANNEL6_OFFSET (0x00000350UL)
73 #define DMA_CHANNEL7_OFFSET (0x000003D0UL)
74
75 /* Array used to get the DMA Channel register offset versus Channel index LL_DMA_CHANNEL_x */
76 static const uint32_t LL_DMA_CH_OFFSET_TAB[] =
77 {
78 DMA_CHANNEL0_OFFSET, DMA_CHANNEL1_OFFSET, DMA_CHANNEL2_OFFSET, DMA_CHANNEL3_OFFSET,
79 DMA_CHANNEL4_OFFSET, DMA_CHANNEL5_OFFSET, DMA_CHANNEL6_OFFSET, DMA_CHANNEL7_OFFSET,
80 };
81
82 /**
83 * @}
84 */
85
86 /* Private constants ---------------------------------------------------------*/
87 /* Private macros ------------------------------------------------------------*/
88 /* Exported types ------------------------------------------------------------*/
89
90 #if defined (USE_FULL_LL_DRIVER)
91 /** @defgroup DMA_LL_ES_INIT DMA Exported Init structure
92 * @{
93 */
94
95 /**
96 * @brief LL DMA init structure definition.
97 */
98 typedef struct
99 {
100 uint32_t SrcAddress; /*!< This field specify the data transfer source address.
101 Programming this field is mandatory for all available DMA channels.
102 This parameter must be a value between Min_Data = 0 and Max_Data = 0xFFFFFFFF.
103 This feature can be modified afterwards using unitary function
104 @ref LL_DMA_SetSrcAddress(). */
105
106 uint32_t DestAddress; /*!< This field specify the data transfer destination address.
107 Programming this field is mandatory for all available DMA channels.
108 This parameter must be a value between Min_Data = 0 and Max_Data = 0xFFFFFFFF.
109 This feature can be modified afterwards using unitary function
110 @ref LL_DMA_SetDestAddress(). */
111
112 uint32_t Direction; /*!< This field specify the data transfer direction.
113 Programming this field is mandatory for all available DMA channels.
114 This parameter can be a value of @ref DMA_LL_EC_TRANSFER_DIRECTION.
115 This feature can be modified afterwards using unitary function
116 @ref LL_DMA_SetDataTransferDirection(). */
117
118 uint32_t BlkHWRequest; /*!< This field specify the hardware request unity.
119 Programming this field is mandatory for all available DMA channels.
120 This parameter can be a value of @ref DMA_LL_EC_BLKHW_REQUEST.
121 This feature can be modified afterwards using unitary function
122 @ref LL_DMA_SetBlkHWRequest(). */
123
124 uint32_t DataAlignment; /*!< This field specify the transfer data alignment.
125 Programming this field is mandatory for all available DMA channels.
126 This parameter can be a value of @ref DMA_LL_EC_DATA_ALIGNMENT.
127 This feature can be modified afterwards using unitary function
128 @ref LL_DMA_SetDataAlignment(). */
129
130 uint32_t SrcBurstLength; /*!< This field specify the source burst length of transfer in bytes.
131 Programming this field is mandatory for all available DMA channels.
132 This parameter must be a value between Min_Data = 1 and Max_Data = 64.
133 This feature can be modified afterwards using unitary function
134 @ref LL_DMA_SetSrcBurstLength(). */
135
136 uint32_t DestBurstLength; /*!< This field specify the destination burst length of transfer in bytes.
137 Programming this field is mandatory for all available DMA channels.
138 This parameter must be a value between Min_Data = 1 and Max_Data = 64.
139 This feature can be modified afterwards using unitary function
140 @ref LL_DMA_SetDestBurstLength(). */
141
142 uint32_t SrcDataWidth; /*!< This field specify the source data width.
143 Programming this field is mandatory for all available DMA channels.
144 This parameter can be a value of @ref DMA_LL_EC_SOURCE_DATA_WIDTH.
145 This feature can be modified afterwards using unitary function
146 @ref LL_DMA_SetSrcDataWidth(). */
147
148 uint32_t DestDataWidth; /*!< This field specify the destination data width.
149 Programming this field is mandatory for all available DMA channels.
150 This parameter can be a value of @ref DMA_LL_EC_DESTINATION_DATA_WIDTH.
151 This feature can be modified afterwards using unitary function
152 @ref LL_DMA_SetDestDataWidth(). */
153
154 uint32_t SrcIncMode; /*!< This field specify the source burst increment mode.
155 Programming this field is mandatory for all available DMA channels.
156 This parameter can be a value of @ref DMA_LL_EC_SOURCE_INCREMENT_MODE.
157 This feature can be modified afterwards using unitary function
158 @ref LL_DMA_SetSrcIncMode(). */
159
160 uint32_t DestIncMode; /*!< This field specify the destination burst increment mode.
161 Programming this field is mandatory for all available DMA channels.
162 This parameter can be a value of @ref DMA_LL_EC_DESTINATION_INCREMENT_MODE.
163 This feature can be modified afterwards using unitary function
164 @ref LL_DMA_SetDestIncMode(). */
165
166 uint32_t Priority; /*!< This field specify the channel priority level.
167 Programming this field is mandatory for all available DMA channels.
168 This parameter can be a value of @ref DMA_LL_EC_PRIORITY_LEVEL.
169 This feature can be modified afterwards using unitary function
170 @ref LL_DMA_SetChannelPriorityLevel(). */
171
172 uint32_t BlkDataLength; /*!< This field specify the length of a block transfer in bytes.
173 Programming this field is mandatory for all available DMA channels.
174 This parameter must be a value between Min_Data = 0 and Max_Data = 0x0000FFFF.
175 This feature can be modified afterwards using unitary function
176 @ref LL_DMA_SetBlkDataLength(). */
177
178 uint32_t TriggerMode; /*!< This field specify the trigger mode.
179 Programming this field is mandatory for all available DMA channels.
180 This parameter can be a value of @ref DMA_LL_EC_TRIGGER_MODE.
181 This feature can be modified afterwards using unitary function
182 @ref LL_DMA_SetTriggerMode(). */
183
184 uint32_t TriggerPolarity; /*!< This field specify the trigger event polarity.
185 Programming this field is mandatory for all available DMA channels.
186 This parameter can be a value of @ref DMA_LL_EC_TRIGGER_POLARITY.
187 This feature can be modified afterwards using unitary function
188 @ref LL_DMA_SetTriggerPolarity(). */
189
190 uint32_t TriggerSelection; /*!< This field specify the trigger event selection.
191 Programming this field is mandatory for all available DMA channels.
192 This parameter can be a value of @ref DMA_LL_EC_TRIGGER_SELECTION.
193 This feature can be modified afterwards using unitary function
194 @ref LL_DMA_SetHWTrigger(). */
195
196 uint32_t Request; /*!< This field specify the peripheral request selection.
197 Programming this field is mandatory for all available DMA channels.
198 This parameter can be a value of @ref DMA_LL_EC_REQUEST_SELECTION.
199 This feature can be modified afterwards using unitary function
200 @ref LL_DMA_SetPeriphRequest(). */
201
202 uint32_t TransferEventMode; /*!< This field specify the transfer event mode.
203 Programming this field is mandatory for all available DMA channels.
204 This parameter can be a value of @ref DMA_LL_EC_TRANSFER_EVENT_MODE.
205 This feature can be modified afterwards using unitary function
206 @ref LL_DMA_SetTransferEventMode(). */
207
208 uint32_t DestHWordExchange; /*!< This field specify the destination half word exchange.
209 Programming this field is mandatory for all available DMA channels.
210 This parameter can be a value of @ref DMA_LL_EC_DEST_HALFWORD_EXCHANGE.
211 This feature can be modified afterwards using unitary function
212 @ref LL_DMA_SetDestHWordExchange(). */
213
214 uint32_t DestByteExchange; /*!< This field specify the destination byte exchange.
215 Programming this field is mandatory for all available DMA channels.
216 This parameter can be a value of @ref DMA_LL_EC_DEST_BYTE_EXCHANGE.
217 This feature can be modified afterwards using unitary function
218 @ref LL_DMA_SetDestByteExchange(). */
219
220 uint32_t SrcByteExchange; /*!< This field specify the source byte exchange.
221 Programming this field is mandatory for all available DMA channels.
222 This parameter can be a value of @ref DMA_LL_EC_SRC_BYTE_EXCHANGE.
223 This feature can be modified afterwards using unitary function
224 @ref LL_DMA_SetSrcByteExchange(). */
225
226 uint32_t SrcAllocatedPort; /*!< This field specify the source allocated port.
227 Programming this field is mandatory for all available DMA channels.
228 This parameter can be a value of @ref DMA_LL_EC_SOURCE_ALLOCATED_PORT.
229 This feature can be modified afterwards using unitary function
230 @ref LL_DMA_SetSrcAllocatedPort(). */
231
232 uint32_t DestAllocatedPort; /*!< This field specify the destination allocated port.
233 Programming this field is mandatory for all available DMA channels.
234 This parameter can be a value of @ref DMA_LL_EC_DESTINATION_ALLOCATED_PORT.
235 This feature can be modified afterwards using unitary function
236 @ref LL_DMA_SetDestAllocatedPort(). */
237
238 uint32_t LinkAllocatedPort; /*!< This field specify the linked-list allocated port.
239 Programming this field is mandatory for all available DMA channels.
240 This parameter can be a value of @ref DMA_LL_EC_LINKED_LIST_ALLOCATED_PORT.
241 This feature can be modified afterwards using unitary function
242 @ref LL_DMA_SetLinkAllocatedPort(). */
243
244 uint32_t LinkStepMode; /*!< This field specify the link step mode.
245 Programming this field is mandatory for all available DMA channels.
246 This parameter can be a value of @ref DMA_LL_EC_LINK_STEP_MODE.
247 This feature can be modified afterwards using unitary function
248 @ref LL_DMA_SetLinkStepMode(). */
249
250 uint32_t LinkedListBaseAddr; /*!< This field specify the linked list base address.
251 Programming this field is mandatory for all available DMA channels.
252 This parameter can be a value Between 0 to 0xFFFF0000 (where the 4 first
253 bytes are always forced to 0).
254 This feature can be modified afterwards using unitary function
255 @ref LL_DMA_SetLinkedListBaseAddr(). */
256
257 uint32_t LinkedListAddrOffset; /*!< Specifies the linked list address offset.
258 Programming this field is mandatory for all available DMA channels.
259 This parameter can be a value Between 0 to 0x0000FFFC.
260 This feature can be modified afterwards using unitary function
261 @ref LL_DMA_SetLinkedListAddrOffset(). */
262
263 } LL_DMA_InitTypeDef;
264
265
266 /**
267 * @brief LL DMA init linked list structure definition.
268 */
269 typedef struct
270 {
271 uint32_t Priority; /*!< This field specify the channel priority level.
272 Programming this field is mandatory for all available DMA channels.
273 This parameter can be a value of @ref DMA_LL_EC_PRIORITY_LEVEL.
274 This feature can be modified afterwards using unitary function
275 @ref LL_DMA_SetChannelPriorityLevel(). */
276
277 uint32_t LinkStepMode; /*!< This field specify the link step mode.
278 Programming this field is mandatory for all available DMA channels.
279 This parameter can be a value of @ref DMA_LL_EC_LINK_STEP_MODE.
280 This feature can be modified afterwards using unitary function
281 @ref LL_DMA_SetLinkStepMode(). */
282
283 uint32_t LinkAllocatedPort; /*!< This field specify the linked-list allocated port.
284 Programming this field is mandatory for all available DMA channels.
285 This parameter can be a value of @ref DMA_LL_EC_LINKED_LIST_ALLOCATED_PORT.
286 This feature can be modified afterwards using unitary function
287 @ref LL_DMA_SetLinkAllocatedPort(). */
288
289 uint32_t TransferEventMode; /*!< This field specify the transfer event mode.
290 Programming this field is mandatory for all available DMA channels.
291 This parameter can be a value of @ref DMA_LL_EC_TRANSFER_EVENT_MODE.
292 This feature can be modified afterwards using unitary function
293 @ref LL_DMA_SetTransferEventMode(). */
294 } LL_DMA_InitLinkedListTypeDef;
295
296
297 /**
298 * @brief LL DMA node init structure definition.
299 */
300 typedef struct
301 {
302 /* CTR1 register fields ******************************************************
303 If any CTR1 fields need to be updated comparing to previous node, it is
304 mandatory to update the new value in CTR1 register fields and enable update
305 CTR1 register in UpdateRegisters fields if it is not enabled in the
306 previous node.
307
308 */
309 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
310 uint32_t DestSecure; /*!< This field specify the destination secure.
311 This parameter can be a value of @ref DMA_LL_EC_DESTINATION_SECURITY_ATTRIBUTE. */
312 #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
313
314 uint32_t DestAllocatedPort; /*!< This field specify the destination allocated port.
315 This parameter can be a value of @ref DMA_LL_EC_DESTINATION_ALLOCATED_PORT. */
316
317 uint32_t DestHWordExchange; /*!< This field specify the destination half word exchange.
318 This parameter can be a value of @ref DMA_LL_EC_DEST_HALFWORD_EXCHANGE. */
319
320 uint32_t DestByteExchange; /*!< This field specify the destination byte exchange.
321 This parameter can be a value of @ref DMA_LL_EC_DEST_BYTE_EXCHANGE. */
322
323 uint32_t DestBurstLength; /*!< This field specify the destination burst length of transfer in bytes.
324 This parameter must be a value between Min_Data = 1 and Max_Data = 64. */
325
326 uint32_t DestIncMode; /*!< This field specify the destination increment mode.
327 This parameter can be a value of @ref DMA_LL_EC_DESTINATION_INCREMENT_MODE. */
328
329 uint32_t DestDataWidth; /*!< This field specify the destination data width.
330 This parameter can be a value of @ref DMA_LL_EC_DESTINATION_DATA_WIDTH. */
331
332 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
333 uint32_t SrcSecure; /*!< This field specify the source secure.
334 This parameter can be a value of @ref DMA_LL_EC_SOURCE_SECURITY_ATTRIBUTE. */
335 #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
336
337 uint32_t SrcAllocatedPort; /*!< This field specify the source allocated port.
338 This parameter can be a value of @ref DMA_LL_EC_SOURCE_ALLOCATED_PORT. */
339
340 uint32_t SrcByteExchange; /*!< This field specify the source byte exchange.
341 This parameter can be a value of @ref DMA_LL_EC_SRC_BYTE_EXCHANGE. */
342
343 uint32_t DataAlignment; /*!< This field specify the transfer data alignment.
344 This parameter can be a value of @ref DMA_LL_EC_DATA_ALIGNMENT. */
345
346 uint32_t SrcBurstLength; /*!< This field specify the source burst length of transfer in bytes.
347 This parameter must be a value between Min_Data = 1 and Max_Data = 64. */
348
349 uint32_t SrcIncMode; /*!< This field specify the source increment mode.
350 This parameter can be a value of @ref DMA_LL_EC_SOURCE_INCREMENT_MODE. */
351
352 uint32_t SrcDataWidth; /*!< This field specify the source data width.
353 This parameter can be a value of @ref DMA_LL_EC_SOURCE_DATA_WIDTH. */
354
355
356 /* CTR2 register fields ******************************************************
357 If any CTR2 fields need to be updated comparing to previous node, it is
358 mandatory to update the new value in CTR2 register fields and enable update
359 CTR2 register in UpdateRegisters fields if it is not enabled in the
360 previous node.
361
362 For all node created, filling all fields is mandatory.
363 */
364 uint32_t TransferEventMode; /*!< This field specify the transfer event mode.
365 This parameter can be a value of @ref DMA_LL_EC_TRANSFER_EVENT_MODE. */
366
367 uint32_t TriggerPolarity; /*!< This field specify the trigger event polarity.
368 This parameter can be a value of @ref DMA_LL_EC_TRIGGER_POLARITY. */
369
370 uint32_t TriggerSelection; /*!< This field specify the trigger event selection.
371 This parameter can be a value of @ref DMA_LL_EC_TRIGGER_SELECTION. */
372
373 uint32_t TriggerMode; /*!< This field specify the trigger mode.
374 This parameter can be a value of @ref DMA_LL_EC_TRIGGER_MODE. */
375
376 uint32_t BlkHWRequest; /*!< This field specify the hardware request unity.
377 This parameter can be a value of @ref DMA_LL_EC_BLKHW_REQUEST. */
378
379 uint32_t Direction; /*!< This field specify the transfer direction.
380 This parameter can be a value of @ref DMA_LL_EC_TRANSFER_DIRECTION. */
381
382 uint32_t Request; /*!< This field specify the peripheral request selection.
383 This parameter can be a value of @ref DMA_LL_EC_REQUEST_SELECTION. */
384
385
386 /* CBR1 register fields ******************************************************
387 If any CBR1 fields need to be updated comparing to previous node, it is
388 mandatory to update the new value in CBR1 register fields and enable update
389 CBR1 register in UpdateRegisters fields if it is not enabled in the
390 previous node.
391 */
392
393 uint32_t BlkDataLength; /*!< This field specify the length of a block transfer in bytes.
394 This parameter must be a value between Min_Data = 0
395 and Max_Data = 0x0000FFFF. */
396
397 /* CSAR register fields ******************************************************
398 If any CSAR fields need to be updated comparing to previous node, it is
399 mandatory to update the new value in CSAR register fields and enable update
400 CSAR register in UpdateRegisters fields if it is not enabled in the
401 previous node.
402
403 For all node created, filling all fields is mandatory.
404 */
405 uint32_t SrcAddress; /*!< This field specify the transfer source address.
406 This parameter must be a value between Min_Data = 0
407 and Max_Data = 0xFFFFFFFF. */
408
409
410 /* CDAR register fields ******************************************************
411 If any CDAR fields need to be updated comparing to previous node, it is
412 mandatory to update the new value in CDAR register fields and enable update
413 CDAR register in UpdateRegisters fields if it is not enabled in the
414 previous node.
415
416 For all node created, filling all fields is mandatory.
417 */
418 uint32_t DestAddress; /*!< This field specify the transfer destination address.
419 This parameter must be a value between Min_Data = 0
420 and Max_Data = 0xFFFFFFFF. */
421
422 /* CLLR register fields ******************************************************
423 If any CLLR fields need to be updated comparing to previous node, it is
424 mandatory to update the new value in CLLR register fields and enable update
425 CLLR register in UpdateRegisters fields if it is not enabled in the
426 previous node.
427 */
428 uint32_t UpdateRegisters; /*!< Specifies the linked list register update.
429 This parameter can be a value of @ref DMA_LL_EC_LINKEDLIST_REGISTER_UPDATE. */
430
431 /* DMA Node type field *******************************************************
432 This parameter defines node types as node size and node content varies
433 between channels.
434 Thanks to this fields, linked list queue could be created independently
435 from channel selection. So, one queue could be executed by all DMA channels.
436 */
437 uint32_t NodeType; /*!< Specifies the node type to be created.
438 This parameter can be a value of @ref DMA_LL_EC_LINKEDLIST_NODE_TYPE. */
439 } LL_DMA_InitNodeTypeDef;
440
441 /**
442 * @brief LL DMA linked list node structure definition.
443 * @note For GPDMA linear addressing channels, the maximum node size is :
444 * (4 Bytes * 6 registers = 24 Bytes).
445 */
446 typedef struct
447 {
448 __IO uint32_t LinkRegisters[6U];
449
450 } LL_DMA_LinkNodeTypeDef;
451 /**
452 * @}
453 */
454
455 #endif /* defined (USE_FULL_LL_DRIVER) */
456
457 /* Exported constants --------------------------------------------------------*/
458
459 /** @defgroup DMA_LL_Exported_Constants DMA Exported Constants
460 * @{
461 */
462
463 /** @defgroup DMA_LL_EC_CHANNEL Channel
464 * @{
465 */
466 #define LL_DMA_CHANNEL_0 (0x00U)
467 #define LL_DMA_CHANNEL_1 (0x01U)
468 #define LL_DMA_CHANNEL_2 (0x02U)
469 #define LL_DMA_CHANNEL_3 (0x03U)
470 #define LL_DMA_CHANNEL_4 (0x04U)
471 #define LL_DMA_CHANNEL_5 (0x05U)
472 #define LL_DMA_CHANNEL_6 (0x06U)
473 #define LL_DMA_CHANNEL_7 (0x07U)
474 #define LL_DMA_CHANNEL_8 (0x08U)
475 #define LL_DMA_CHANNEL_9 (0x09U)
476 #define LL_DMA_CHANNEL_10 (0x0AU)
477 #define LL_DMA_CHANNEL_11 (0x0BU)
478 #define LL_DMA_CHANNEL_12 (0x0CU)
479 #define LL_DMA_CHANNEL_13 (0x0DU)
480 #define LL_DMA_CHANNEL_14 (0x0EU)
481 #define LL_DMA_CHANNEL_15 (0x0FU)
482 #if defined (USE_FULL_LL_DRIVER)
483 #define LL_DMA_CHANNEL_ALL (0x10U)
484 #endif /* defined (USE_FULL_LL_DRIVER) */
485 /**
486 * @}
487 */
488
489 #if defined (USE_FULL_LL_DRIVER)
490 /** @defgroup DMA_LL_EC_CLLR_OFFSET CLLR offset
491 * @{
492 */
493 #define LL_DMA_CLLR_OFFSET0 (0x00U)
494 #define LL_DMA_CLLR_OFFSET1 (0x01U)
495 #define LL_DMA_CLLR_OFFSET2 (0x02U)
496 #define LL_DMA_CLLR_OFFSET3 (0x03U)
497 #define LL_DMA_CLLR_OFFSET4 (0x04U)
498 #define LL_DMA_CLLR_OFFSET5 (0x05U)
499 #define LL_DMA_CLLR_OFFSET6 (0x06U)
500 #define LL_DMA_CLLR_OFFSET7 (0x07U)
501 /**
502 * @}
503 */
504 #endif /* defined (USE_FULL_LL_DRIVER) */
505
506 /** @defgroup DMA_LL_EC_PRIORITY_LEVEL Priority Level
507 * @{
508 */
509 #define LL_DMA_LOW_PRIORITY_LOW_WEIGHT 0x00000000U /*!< Priority level : Low Priority, Low Weight */
510 #define LL_DMA_LOW_PRIORITY_MID_WEIGHT DMA_CCR_PRIO_0 /*!< Priority level : Low Priority, Mid Weight */
511 #define LL_DMA_LOW_PRIORITY_HIGH_WEIGHT DMA_CCR_PRIO_1 /*!< Priority level : Low Priority, High Weight */
512 #define LL_DMA_HIGH_PRIORITY DMA_CCR_PRIO /*!< Priority level : High Priority */
513 /**
514 * @}
515 */
516
517 /** @defgroup DMA_LL_EC_LINKED_LIST_ALLOCATED_PORT Linked List Allocated Port
518 * @{
519 */
520 #define LL_DMA_LINK_ALLOCATED_PORT0 0x00000000U /*!< Linked List Allocated Port 0 */
521 #define LL_DMA_LINK_ALLOCATED_PORT1 DMA_CCR_LAP /*!< Linked List Allocated Port 1 */
522 /**
523 * @}
524 */
525
526 /** @defgroup DMA_LL_EC_LINK_STEP_MODE Link Step Mode
527 * @{
528 */
529 #define LL_DMA_LSM_FULL_EXECUTION 0x00000000U /*!< Channel execute the full linked list */
530 #define LL_DMA_LSM_1LINK_EXECUTION DMA_CCR_LSM /*!< Channel execute one node of the linked list */
531 /**
532 * @}
533 */
534
535 /** @defgroup DMA_LL_EC_DEST_HALFWORD_EXCHANGE Destination Half-Word Exchange
536 * @{
537 */
538 #define LL_DMA_DEST_HALFWORD_PRESERVE 0x00000000U /*!< No destination Half-Word exchange when destination data width
539 is word */
540 #define LL_DMA_DEST_HALFWORD_EXCHANGE DMA_CTR1_DHX /*!< Destination Half-Word exchange when destination data width
541 is word */
542 /**
543 * @}
544 */
545
546 /** @defgroup DMA_LL_EC_DEST_BYTE_EXCHANGE Destination Byte Exchange
547 * @{
548 */
549 #define LL_DMA_DEST_BYTE_PRESERVE 0x00000000U /*!< No destination Byte exchange when destination data width > Byte */
550 #define LL_DMA_DEST_BYTE_EXCHANGE DMA_CTR1_DBX /*!< Destination Byte exchange when destination data width > Byte */
551 /**
552 * @}
553 */
554
555 /** @defgroup DMA_LL_EC_SRC_BYTE_EXCHANGE Source Byte Exchange
556 * @{
557 */
558 #define LL_DMA_SRC_BYTE_PRESERVE 0x00000000U /*!< No source Byte exchange when source data width is word */
559 #define LL_DMA_SRC_BYTE_EXCHANGE DMA_CTR1_SBX /*!< Source Byte exchange when source data width is word */
560 /**
561 * @}
562 */
563
564 /** @defgroup DMA_LL_EC_SOURCE_ALLOCATED_PORT Source Allocated Port
565 * @{
566 */
567 #define LL_DMA_SRC_ALLOCATED_PORT0 0x00000000U /*!< Source Allocated Port 0 */
568 #define LL_DMA_SRC_ALLOCATED_PORT1 DMA_CTR1_SAP /*!< Source Allocated Port 1 */
569 /**
570 * @}
571 */
572
573 /** @defgroup DMA_LL_EC_DESTINATION_ALLOCATED_PORT Destination Allocated Port
574 * @{
575 */
576 #define LL_DMA_DEST_ALLOCATED_PORT0 0x00000000U /*!< Destination Allocated Port 0 */
577 #define LL_DMA_DEST_ALLOCATED_PORT1 DMA_CTR1_DAP /*!< Destination Allocated Port 1 */
578 /**
579 * @}
580 */
581
582 /** @defgroup DMA_LL_EC_DESTINATION_INCREMENT_MODE Destination Increment Mode
583 * @{
584 */
585 #define LL_DMA_DEST_FIXED 0x00000000U /*!< Destination fixed single/burst */
586 #define LL_DMA_DEST_INCREMENT DMA_CTR1_DINC /*!< Destination incremented single/burst */
587 /**
588 * @}
589 */
590
591 /** @defgroup DMA_LL_EC_DESTINATION_DATA_WIDTH Destination Data Width
592 * @{
593 */
594 #define LL_DMA_DEST_DATAWIDTH_BYTE 0x00000000U /*!< Destination Data Width : Byte */
595 #define LL_DMA_DEST_DATAWIDTH_HALFWORD DMA_CTR1_DDW_LOG2_0 /*!< Destination Data Width : HalfWord */
596 #define LL_DMA_DEST_DATAWIDTH_WORD DMA_CTR1_DDW_LOG2_1 /*!< Destination Data Width : Word */
597 /**
598 * @}
599 */
600
601 /** @defgroup DMA_LL_EC_DATA_ALIGNMENT Data Alignment
602 * @{
603 */
604 #define LL_DMA_DATA_ALIGN_ZEROPADD 0x00000000U /*!< If src data width < dest data width :
605 => Right Aligned padded with 0 up to destination
606 data width.
607 If src data width > dest data width :
608 => Right Aligned Left Truncated down to destination
609 data width. */
610 #define LL_DMA_DATA_ALIGN_SIGNEXTPADD DMA_CTR1_PAM_0 /*!< If src data width < dest data width :
611 => Right Aligned padded with sign extended up to destination
612 data width.
613 If src data width > dest data width :
614 => Left Aligned Right Truncated down to the destination
615 data width */
616 #define LL_DMA_DATA_PACK_UNPACK DMA_CTR1_PAM_1 /*!< If src data width < dest data width :
617 => Packed at the destination data width
618 If src data width > dest data width :
619 => Unpacked at the destination data width */
620 /**
621 * @}
622 */
623
624 /** @defgroup DMA_LL_EC_SOURCE_INCREMENT_MODE Source Increment Mode
625 * @{
626 */
627 #define LL_DMA_SRC_FIXED 0x00000000U /*!< Source fixed single/burst */
628 #define LL_DMA_SRC_INCREMENT DMA_CTR1_SINC /*!< Source incremented single/burst */
629 /**
630 * @}
631 */
632
633 /** @defgroup DMA_LL_EC_SOURCE_DATA_WIDTH Source Data Width
634 * @{
635 */
636 #define LL_DMA_SRC_DATAWIDTH_BYTE 0x00000000U /*!< Source Data Width : Byte */
637 #define LL_DMA_SRC_DATAWIDTH_HALFWORD DMA_CTR1_SDW_LOG2_0 /*!< Source Data Width : HalfWord */
638 #define LL_DMA_SRC_DATAWIDTH_WORD DMA_CTR1_SDW_LOG2_1 /*!< Source Data Width : Word */
639 /**
640 * @}
641 */
642
643 /** @defgroup DMA_LL_EC_BLKHW_REQUEST Block Hardware Request
644 * @{
645 */
646 #define LL_DMA_HWREQUEST_SINGLEBURST 0x00000000U /*!< Hardware request is driven by a peripheral with a hardware
647 request/acknowledge protocol at a burst level */
648 #define LL_DMA_HWREQUEST_BLK DMA_CTR2_BREQ /*!< Hardware request is driven by a peripheral with a hardware
649 request/acknowledge protocol at a block level */
650 /**
651 * @}
652 */
653
654 /** @defgroup DMA_LL_EC_TRANSFER_EVENT_MODE Transfer Event Mode
655 * @{
656 */
657 #define LL_DMA_TCEM_BLK_TRANSFER 0x00000000U /*!< The TC (and the HT) event is generated at the
658 (respectively half) end of each block */
659 #define LL_DMA_TCEM_RPT_BLK_TRANSFER DMA_CTR2_TCEM_0 /*!< The TC (and the HT) event is generated at the
660 (respectively half) end of the repeated block */
661 #define LL_DMA_TCEM_EACH_LLITEM_TRANSFER DMA_CTR2_TCEM_1 /*!< The TC (and the HT) event is generated at the
662 (respectively half) end of each linked-list item */
663 #define LL_DMA_TCEM_LAST_LLITEM_TRANSFER DMA_CTR2_TCEM /*!< The TC (and the HT) event is generated at the
664 (respectively half) end of the last linked-list item */
665 /**
666 * @}
667 */
668
669 /** @defgroup DMA_LL_EC_TRIGGER_POLARITY Trigger Polarity
670 * @{
671 */
672 #define LL_DMA_TRIG_POLARITY_MASKED 0x00000000U /*!< No trigger of the selected DMA request.
673 Masked trigger event */
674 #define LL_DMA_TRIG_POLARITY_RISING DMA_CTR2_TRIGPOL_0 /*!< Trigger of the selected DMA request on the rising
675 edge of the selected trigger event input */
676 #define LL_DMA_TRIG_POLARITY_FALLING DMA_CTR2_TRIGPOL_1 /*!< Trigger of the selected DMA request on the falling
677 edge of the selected trigger event input */
678 /**
679 * @}
680 */
681
682 /** @defgroup DMA_LL_EC_TRIGGER_MODE Transfer Trigger Mode
683 * @{
684 */
685 #define LL_DMA_TRIGM_BLK_TRANSFER 0x00000000U /*!< A block transfer is conditioned by (at least)
686 one hit trigger */
687 #define LL_DMA_TRIGM_RPT_BLK_TRANSFER DMA_CTR2_TRIGM_0 /*!< A repeated block transfer is conditioned by (at least)
688 one hit trigger */
689 #define LL_DMA_TRIGM_LLI_LINK_TRANSFER DMA_CTR2_TRIGM_1 /*!< A LLI link transfer is conditioned by (at least)
690 one hit trigger */
691 #define LL_DMA_TRIGM_SINGLBURST_TRANSFER DMA_CTR2_TRIGM /*!< A Single/Burst transfer is conditioned by (at least)
692 one hit trigger */
693 /**
694 * @}
695 */
696
697 /** @defgroup DMA_LL_EC_TRANSFER_DIRECTION Transfer Direction
698 * @{
699 */
700 #define LL_DMA_DIRECTION_MEMORY_TO_MEMORY DMA_CTR2_SWREQ /*!< Memory to memory direction */
701 #define LL_DMA_DIRECTION_PERIPH_TO_MEMORY 0x00000000U /*!< Peripheral to memory direction */
702 #define LL_DMA_DIRECTION_MEMORY_TO_PERIPH DMA_CTR2_DREQ /*!< Memory to peripheral direction */
703 /**
704 * @}
705 */
706
707
708 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
709 /** @defgroup DMA_LL_EC_SOURCE_SECURITY_ATTRIBUTE Source Security Attribute
710 * @{
711 */
712 #define LL_DMA_CHANNEL_NSEC 0x00000000U /*!< NSecure channel */
713 #define LL_DMA_CHANNEL_SEC 0x00000001U /*!< Secure channel */
714 /**
715 * @}
716 */
717
718 /** @defgroup DMA_LL_EC_SOURCE_SECURITY_ATTRIBUTE Source Security Attribute
719 * @{
720 */
721 #define LL_DMA_CHANNEL_SRC_NSEC 0x00000000U /*!< NSecure transfer from the source */
722 #define LL_DMA_CHANNEL_SRC_SEC DMA_CTR1_SSEC /*!< Secure transfer from the source */
723 /**
724 * @}
725 */
726
727 /** @defgroup DMA_LL_EC_DESTINATION_SECURITY_ATTRIBUTE Destination Security Attribute
728 * @{
729 */
730 #define LL_DMA_CHANNEL_DEST_NSEC 0x00000000U /*!< NSecure transfer from the destination */
731 #define LL_DMA_CHANNEL_DEST_SEC DMA_CTR1_DSEC /*!< Secure transfer from the destination */
732 /**
733 * @}
734 */
735 #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
736
737 /** @defgroup DMA_LL_EC_LINKEDLIST_NODE_TYPE Linked list node type
738 * @{
739 */
740 #define LL_DMA_GPDMA_LINEAR_NODE 0x01U /*!< GPDMA node : linear addressing node */
741
742 /**
743 * @}
744 */
745
746 /** @defgroup DMA_LL_EC_LINKEDLIST_REGISTER_UPDATE Linked list register update
747 * @{
748 */
749 #define LL_DMA_UPDATE_CTR1 DMA_CLLR_UT1 /*!< Update CTR1 register from memory :
750 available for all DMA channels */
751 #define LL_DMA_UPDATE_CTR2 DMA_CLLR_UT2 /*!< Update CTR2 register from memory :
752 available for all DMA channels */
753 #define LL_DMA_UPDATE_CBR1 DMA_CLLR_UB1 /*!< Update CBR1 register from memory :
754 available for all DMA channels */
755 #define LL_DMA_UPDATE_CSAR DMA_CLLR_USA /*!< Update CSAR register from memory :
756 available for all DMA channels */
757 #define LL_DMA_UPDATE_CDAR DMA_CLLR_UDA /*!< Update CDAR register from memory :
758 available for all DMA channels */
759 #define LL_DMA_UPDATE_CLLR DMA_CLLR_ULL /*!< Update CLLR register from memory :
760 available for all DMA channels */
761 /**
762 * @}
763 */
764
765 /** @defgroup DMA_LL_EC_REQUEST_SELECTION Request Selection
766 * @{
767 */
768 /* GPDMA1 Hardware Requests */
769 #define LL_GPDMA1_REQUEST_ADC4 0U /*!< GPDMA1 HW request is ADC4 */
770 #if defined (SPI1)
771 #define LL_GPDMA1_REQUEST_SPI1_RX 1U /*!< GPDMA1 HW request is SPI1_RX */
772 #define LL_GPDMA1_REQUEST_SPI1_TX 2U /*!< GPDMA1 HW request is SPI1_TX */
773 #endif /* defined (SPI1) */
774 #define LL_GPDMA1_REQUEST_SPI3_RX 3U /*!< GPDMA1 HW request is SPI3_RX */
775 #define LL_GPDMA1_REQUEST_SPI3_TX 4U /*!< GPDMA1 HW request is SPI3_TX */
776 #if defined (I2C1)
777 #define LL_GPDMA1_REQUEST_I2C1_RX 5U /*!< GPDMA1 HW request is I2C1_RX */
778 #define LL_GPDMA1_REQUEST_I2C1_TX 6U /*!< GPDMA1 HW request is I2C1_TX */
779 #define LL_GPDMA1_REQUEST_I2C1_EVC 7U /*!< GPDMA1 HW request is I2C1_EVC */
780 #endif /* defined (I2C1) */
781 #define LL_GPDMA1_REQUEST_I2C3_RX 8U /*!< GPDMA1 HW request is I2C3_RX */
782 #define LL_GPDMA1_REQUEST_I2C3_TX 9U /*!< GPDMA1 HW request is I2C3_TX */
783 #define LL_GPDMA1_REQUEST_I2C3_EVC 10U /*!< GPDMA1 HW request is I2C3_EVC */
784 #define LL_GPDMA1_REQUEST_USART1_RX 11U /*!< GPDMA1 HW request is USART1_RX */
785 #define LL_GPDMA1_REQUEST_USART1_TX 12U /*!< GPDMA1 HW request is USART1_TX */
786 #if defined (USART2)
787 #define LL_GPDMA1_REQUEST_USART2_RX 13U /*!< GPDMA1 HW request is USART2_RX */
788 #define LL_GPDMA1_REQUEST_USART2_TX 14U /*!< GPDMA1 HW request is USART2_TX */
789 #endif /* defined (USART2) */
790 #define LL_GPDMA1_REQUEST_LPUART1_RX 15U /*!< GPDMA1 HW request is LPUART1_RX */
791 #define LL_GPDMA1_REQUEST_LPUART1_TX 16U /*!< GPDMA1 HW request is LPUART1_TX */
792 #if defined (SAI1)
793 #define LL_GPDMA1_REQUEST_SAI1_A 17U /*!< GPDMA1 HW request is SAI1_A */
794 #define LL_GPDMA1_REQUEST_SAI1_B 18U /*!< GPDMA1 HW request is SAI1_B */
795 #endif /* defined (SAI1) */
796 #define LL_GPDMA1_REQUEST_TIM1_CH1 19U /*!< GPDMA1 HW request is TIM1_CH1 */
797 #define LL_GPDMA1_REQUEST_TIM1_CH2 20U /*!< GPDMA1 HW request is TIM1_CH2 */
798 #define LL_GPDMA1_REQUEST_TIM1_CH3 21U /*!< GPDMA1 HW request is TIM1_CH3 */
799 #define LL_GPDMA1_REQUEST_TIM1_CH4 22U /*!< GPDMA1 HW request is TIM1_CH4 */
800 #define LL_GPDMA1_REQUEST_TIM1_UP 23U /*!< GPDMA1 HW request is TIM1_UP */
801 #define LL_GPDMA1_REQUEST_TIM1_TRIG 24U /*!< GPDMA1 HW request is TIM1_TRIG */
802 #define LL_GPDMA1_REQUEST_TIM1_COM 25U /*!< GPDMA1 HW request is TIM1_COM */
803 #define LL_GPDMA1_REQUEST_TIM2_CH1 26U /*!< GPDMA1 HW request is TIM2_CH1 */
804 #define LL_GPDMA1_REQUEST_TIM2_CH2 27U /*!< GPDMA1 HW request is TIM2_CH2 */
805 #define LL_GPDMA1_REQUEST_TIM2_CH3 28U /*!< GPDMA1 HW request is TIM2_CH3 */
806 #define LL_GPDMA1_REQUEST_TIM2_CH4 29U /*!< GPDMA1 HW request is TIM2_CH4 */
807 #define LL_GPDMA1_REQUEST_TIM2_UP 30U /*!< GPDMA1 HW request is TIM2_UP */
808 #if defined (TIM3)
809 #define LL_GPDMA1_REQUEST_TIM3_CH1 31U /*!< GPDMA1 HW request is TIM3_CH1 */
810 #define LL_GPDMA1_REQUEST_TIM3_CH2 32U /*!< GPDMA1 HW request is TIM3_CH2 */
811 #define LL_GPDMA1_REQUEST_TIM3_CH3 33U /*!< GPDMA1 HW request is TIM3_CH3 */
812 #define LL_GPDMA1_REQUEST_TIM3_CH4 34U /*!< GPDMA1 HW request is TIM3_CH4 */
813 #define LL_GPDMA1_REQUEST_TIM3_UP 35U /*!< GPDMA1 HW request is TIM3_UP */
814 #define LL_GPDMA1_REQUEST_TIM3_TRIG 36U /*!< GPDMA1 HW request is TIM3_TRIG */
815 #endif /* defined (TIM3) */
816 #define LL_GPDMA1_REQUEST_TIM16_CH1 37U /*!< GPDMA1 HW request is TIM16_CH1 */
817 #define LL_GPDMA1_REQUEST_TIM16_UP 38U /*!< GPDMA1 HW request is TIM16_UP */
818 #if defined (TIM17)
819 #define LL_GPDMA1_REQUEST_TIM17_CH1 39U /*!< GPDMA1 HW request is TIM17_CH1 */
820 #define LL_GPDMA1_REQUEST_TIM17_UP 40U /*!< GPDMA1 HW request is TIM17_UP */
821 #endif /* defined (TIM17) */
822 #if defined (AES)
823 #define LL_GPDMA1_REQUEST_AES_IN 41U /*!< GPDMA1 HW request is AES_IN */
824 #define LL_GPDMA1_REQUEST_AES_OUT 42U /*!< GPDMA1 HW request is AES_OUT */
825 #endif /* defined (AES) */
826 #define LL_GPDMA1_REQUEST_HASH_IN 43U /*!< GPDMA1 HW request is HASH_IN */
827 #if defined (SAES)
828 #define LL_GPDMA1_REQUEST_SAES_IN 44U /*!< GPDMA1 HW request is SAES_IN */
829 #define LL_GPDMA1_REQUEST_SAES_OUT 45U /*!< GPDMA1 HW request is SAES_OUT */
830 #endif /* defined (SAES) */
831 #define LL_GPDMA1_REQUEST_LPTIM1_IC1 46U /*!< GPDMA1 HW request is LPTIM1_IC1 */
832 #define LL_GPDMA1_REQUEST_LPTIM1_IC2 47U /*!< GPDMA1 HW request is LPTIM1_IC2 */
833 #define LL_GPDMA1_REQUEST_LPTIM1_UE 48U /*!< GPDMA1 HW request is LPTIM1_UE */
834 #if defined (LPTIM2)
835 #define LL_GPDMA1_REQUEST_LPTIM2_IC1 49U /*!< GPDMA1 HW request is LPTIM2_IC1 */
836 #define LL_GPDMA1_REQUEST_LPTIM2_IC2 50U /*!< GPDMA1 HW request is LPTIM2_IC2 */
837 #define LL_GPDMA1_REQUEST_LPTIM2_UE 51U /*!< GPDMA1 HW request is LPTIM2_UE */
838 #endif /* defined (LPTIM2) */
839
840 /**
841 * @}
842 */
843
844 /** @defgroup DMA_LL_EC_TRIGGER_SELECTION Trigger Selection
845 * @{
846 */
847 /* GPDMA1 Hardware Triggers */
848 #define LL_GPDMA1_TRIGGER_EXTI_LINE0 0U /*!< GPDMA1 HW Trigger signal is EXTI_LINE0 */
849 #define LL_GPDMA1_TRIGGER_EXTI_LINE1 1U /*!< GPDMA1 HW Trigger signal is EXTI_LINE1 */
850 #define LL_GPDMA1_TRIGGER_EXTI_LINE2 2U /*!< GPDMA1 HW Trigger signal is EXTI_LINE2 */
851 #define LL_GPDMA1_TRIGGER_EXTI_LINE3 3U /*!< GPDMA1 HW Trigger signal is EXTI_LINE3 */
852 #define LL_GPDMA1_TRIGGER_EXTI_LINE4 4U /*!< GPDMA1 HW Trigger signal is EXTI_LINE4 */
853 #define LL_GPDMA1_TRIGGER_EXTI_LINE5 5U /*!< GPDMA1 HW Trigger signal is EXTI_LINE5 */
854 #define LL_GPDMA1_TRIGGER_EXTI_LINE6 6U /*!< GPDMA1 HW Trigger signal is EXTI_LINE6 */
855 #define LL_GPDMA1_TRIGGER_EXTI_LINE7 7U /*!< GPDMA1 HW Trigger signal is EXTI_LINE7 */
856 #define LL_GPDMA1_TRIGGER_TAMP_TRG1 8U /*!< GPDMA1 HW Trigger signal is TAMP_TRG1 */
857 #define LL_GPDMA1_TRIGGER_TAMP_TRG2 9U /*!< GPDMA1 HW Trigger signal is TAMP_TRG2 */
858 #define LL_GPDMA1_TRIGGER_TAMP_TRG3 10U /*!< GPDMA1 HW Trigger signal is TAMP_TRG3 */
859 #define LL_GPDMA1_TRIGGER_LPTIM1_CH1 11U /*!< GPDMA1 HW Trigger signal is LPTIM1_CH1 */
860 #define LL_GPDMA1_TRIGGER_LPTIM1_CH2 12U /*!< GPDMA1 HW Trigger signal is LPTIM1_CH2 */
861 #if defined (LPTIM2)
862 #define LL_GPDMA1_TRIGGER_LPTIM2_CH1 13U /*!< GPDMA1 HW Trigger signal is LPTIM2_CH1 */
863 #define LL_GPDMA1_TRIGGER_LPTIM2_CH2 14U /*!< GPDMA1 HW Trigger signal is LPTIM2_CH2 */
864 #endif /* defined (LPTIM2) */
865 #if defined (COMP1)
866 #define LL_GPDMA1_TRIGGER_COMP1_OUT 15U /*!< GPDMA1 HW Trigger signal is COMP1_OUT */
867 #endif /* defined (COMP1) */
868 #if defined (COMP2)
869 #define LL_GPDMA1_TRIGGER_COMP2_OUT 16U /*!< GPDMA1 HW Trigger signal is COMP2_OUT */
870 #endif /* defined (COMP2) */
871 #define LL_GPDMA1_TRIGGER_RTC_ALRA_TRG 17U /*!< GPDMA1 HW Trigger signal is RTC_ALRA_TRG */
872 #define LL_GPDMA1_TRIGGER_RTC_ALRB_TRG 18U /*!< GPDMA1 HW Trigger signal is RTC_ALRB_TRG */
873 #define LL_GPDMA1_TRIGGER_RTC_WUT_TRG 19U /*!< GPDMA1 HW Trigger signal is RTC_WUT_TRG */
874 #define LL_GPDMA1_TRIGGER_GPDMA1_CH0_TCF 20U /*!< GPDMA1 HW Trigger signal is GPDMA1_CH0_TCF */
875 #define LL_GPDMA1_TRIGGER_GPDMA1_CH1_TCF 21U /*!< GPDMA1 HW Trigger signal is GPDMA1_CH1_TCF */
876 #define LL_GPDMA1_TRIGGER_GPDMA1_CH2_TCF 22U /*!< GPDMA1 HW Trigger signal is GPDMA1_CH2_TCF */
877 #define LL_GPDMA1_TRIGGER_GPDMA1_CH3_TCF 23U /*!< GPDMA1 HW Trigger signal is GPDMA1_CH3_TCF */
878 #define LL_GPDMA1_TRIGGER_GPDMA1_CH4_TCF 24U /*!< GPDMA1 HW Trigger signal is GPDMA1_CH4_TCF */
879 #define LL_GPDMA1_TRIGGER_GPDMA1_CH5_TCF 25U /*!< GPDMA1 HW Trigger signal is GPDMA1_CH5_TCF */
880 #define LL_GPDMA1_TRIGGER_GPDMA1_CH6_TCF 26U /*!< GPDMA1 HW Trigger signal is GPDMA1_CH6_TCF */
881 #define LL_GPDMA1_TRIGGER_GPDMA1_CH7_TCF 27U /*!< GPDMA1 HW Trigger signal is GPDMA1_CH7_TCF */
882 #define LL_GPDMA1_TRIGGER_TIM2_TRGO 28U /*!< GPDMA1 HW Trigger signal is TIM2_TRGO */
883 #define LL_GPDMA1_TRIGGER_ADC4_AWD1 29U /*!< GPDMA1 HW Trigger signal is ADC4_ADW1 */
884 #if defined (TIM3)
885 #define LL_GPDMA1_TRIGGER_TIM3_TRGO 30U /*!< GPDMA1 HW Trigger signal is TIM3_TRGO */
886 #endif /* defined (TIM3) */
887 /**
888 * @}
889 */
890
891 /**
892 * @}
893 */
894
895 /* Exported macro ------------------------------------------------------------*/
896
897 /** @defgroup DMA_LL_Exported_Macros DMA Exported Macros
898 * @{
899 */
900
901 /** @defgroup DMA_LL_EM_COMMON_WRITE_READ_REGISTERS Common Write and Read Registers macros
902 * @{
903 */
904 /**
905 * @brief Write a value in DMA register.
906 * @param __INSTANCE__ DMA Instance.
907 * @param __REG__ Register to be written.
908 * @param __VALUE__ Value to be written in the register.
909 * @retval None.
910 */
911 #define LL_DMA_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG((__INSTANCE__)->__REG__, (__VALUE__))
912
913 /**
914 * @brief Read a value in DMA register.
915 * @param __INSTANCE__ DMA Instance.
916 * @param __REG__ Register to be read.
917 * @retval Register value.
918 */
919 #define LL_DMA_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
920 /**
921 * @}
922 */
923
924 /** @defgroup DMA_LL_EM_CONVERT_DMAxCHANNELy Convert DMAxChannely
925 * @{
926 */
927 /**
928 * @brief Convert DMAx_Channely into DMAx.
929 * @param __CHANNEL_INSTANCE__ DMAx_Channely.
930 * @retval DMAx.
931 */
932 #define LL_DMA_GET_INSTANCE(__CHANNEL_INSTANCE__) \
933 (GPDMA1)
934
935 /**
936 * @brief Convert DMAx_Channely into LL_DMA_CHANNEL_y.
937 * @param __CHANNEL_INSTANCE__ DMAx_Channely.
938 * @retval LL_DMA_CHANNEL_y.
939 */
940 #define LL_DMA_GET_CHANNEL(__CHANNEL_INSTANCE__) \
941 (((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)GPDMA1_Channel0)) ? LL_DMA_CHANNEL_0 : \
942 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)GPDMA1_Channel1)) ? LL_DMA_CHANNEL_1 : \
943 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)GPDMA1_Channel2)) ? LL_DMA_CHANNEL_2 : \
944 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)GPDMA1_Channel3)) ? LL_DMA_CHANNEL_3 : \
945 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)GPDMA1_Channel4)) ? LL_DMA_CHANNEL_4 : \
946 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)GPDMA1_Channel5)) ? LL_DMA_CHANNEL_5 : \
947 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)GPDMA1_Channel6)) ? LL_DMA_CHANNEL_6 : \
948 LL_DMA_CHANNEL_7)
949
950 /**
951 * @brief Convert DMA Instance DMAx and LL_DMA_CHANNEL_y into DMAx_Channely.
952 * @param __DMA_INSTANCE__ DMAx.
953 * @param __CHANNEL__ LL_DMA_CHANNEL_y.
954 * @retval DMAx_Channely.
955 */
956 #define LL_DMA_GET_CHANNEL_INSTANCE(__DMA_INSTANCE__, __CHANNEL__) \
957 ((((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)GPDMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_0))) \
958 ? GPDMA1_Channel0 : \
959 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)GPDMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) \
960 ? GPDMA1_Channel1 : \
961 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)GPDMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) \
962 ? GPDMA1_Channel2 : \
963 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)GPDMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) \
964 ? GPDMA1_Channel3 : \
965 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)GPDMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) \
966 ? GPDMA1_Channel4 : \
967 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)GPDMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) \
968 ? GPDMA1_Channel5 : \
969 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)GPDMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_6))) \
970 ? GPDMA1_Channel6 : GPDMA1_Channel7)
971
972 /**
973 * @}
974 */
975
976 /**
977 * @}
978 */
979
980 /* Exported functions --------------------------------------------------------*/
981
982 /** @defgroup DMA_LL_Exported_Functions DMA Exported Functions
983 * @{
984 */
985
986 /** @defgroup DMA_LL_EF_Configuration Configuration
987 * @{
988 */
989 /**
990 * @brief Enable channel.
991 * @note This API is used for all available DMA channels.
992 * @rmtoll CCR EN LL_DMA_EnableChannel
993 * @param DMAx DMAx Instance.
994 * @param Channel This parameter can be one of the following values:
995 * @arg @ref LL_DMA_CHANNEL_0
996 * @arg @ref LL_DMA_CHANNEL_1
997 * @arg @ref LL_DMA_CHANNEL_2
998 * @arg @ref LL_DMA_CHANNEL_3
999 * @arg @ref LL_DMA_CHANNEL_4
1000 * @arg @ref LL_DMA_CHANNEL_5
1001 * @arg @ref LL_DMA_CHANNEL_6
1002 * @arg @ref LL_DMA_CHANNEL_7
1003 * @retval None.
1004 */
LL_DMA_EnableChannel(const DMA_TypeDef * DMAx,uint32_t Channel)1005 __STATIC_INLINE void LL_DMA_EnableChannel(const DMA_TypeDef *DMAx, uint32_t Channel)
1006 {
1007 uint32_t dma_base_addr = (uint32_t)DMAx;
1008 SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_EN);
1009 }
1010
1011 /**
1012 * @brief Disable channel.
1013 * @note This API is used for all available DMA channels.
1014 * @rmtoll CCR EN LL_DMA_DisableChannel
1015 * @param DMAx DMAx Instance.
1016 * @param Channel This parameter can be one of the following values:
1017 * @arg @ref LL_DMA_CHANNEL_0
1018 * @arg @ref LL_DMA_CHANNEL_1
1019 * @arg @ref LL_DMA_CHANNEL_2
1020 * @arg @ref LL_DMA_CHANNEL_3
1021 * @arg @ref LL_DMA_CHANNEL_4
1022 * @arg @ref LL_DMA_CHANNEL_5
1023 * @arg @ref LL_DMA_CHANNEL_6
1024 * @arg @ref LL_DMA_CHANNEL_7
1025 * @retval None.
1026 */
LL_DMA_DisableChannel(const DMA_TypeDef * DMAx,uint32_t Channel)1027 __STATIC_INLINE void LL_DMA_DisableChannel(const DMA_TypeDef *DMAx, uint32_t Channel)
1028 {
1029 uint32_t dma_base_addr = (uint32_t)DMAx;
1030 SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR,
1031 (DMA_CCR_SUSP | DMA_CCR_RESET));
1032 }
1033
1034 /**
1035 * @brief Check if channel is enabled or disabled.
1036 * @note This API is used for all available DMA channels.
1037 * @rmtoll CCR EN LL_DMA_IsEnabledChannel
1038 * @param DMAx DMAx Instance
1039 * @param Channel This parameter can be one of the following values:
1040 * @arg @ref LL_DMA_CHANNEL_0
1041 * @arg @ref LL_DMA_CHANNEL_1
1042 * @arg @ref LL_DMA_CHANNEL_2
1043 * @arg @ref LL_DMA_CHANNEL_3
1044 * @arg @ref LL_DMA_CHANNEL_4
1045 * @arg @ref LL_DMA_CHANNEL_5
1046 * @arg @ref LL_DMA_CHANNEL_6
1047 * @arg @ref LL_DMA_CHANNEL_7
1048 * @retval State of bit (1 or 0).
1049 */
LL_DMA_IsEnabledChannel(const DMA_TypeDef * DMAx,uint32_t Channel)1050 __STATIC_INLINE uint32_t LL_DMA_IsEnabledChannel(const DMA_TypeDef *DMAx, uint32_t Channel)
1051 {
1052 uint32_t dma_base_addr = (uint32_t)DMAx;
1053 return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_EN)
1054 == (DMA_CCR_EN)) ? 1UL : 0UL);
1055 }
1056
1057 /**
1058 * @brief Reset channel.
1059 * @note This API is used for all available DMA channels.
1060 * @rmtoll CCR RESET LL_DMA_ResetChannel
1061 * @param DMAx DMAx Instance
1062 * @param Channel This parameter can be one of the following values:
1063 * @arg @ref LL_DMA_CHANNEL_0
1064 * @arg @ref LL_DMA_CHANNEL_1
1065 * @arg @ref LL_DMA_CHANNEL_2
1066 * @arg @ref LL_DMA_CHANNEL_3
1067 * @arg @ref LL_DMA_CHANNEL_4
1068 * @arg @ref LL_DMA_CHANNEL_5
1069 * @arg @ref LL_DMA_CHANNEL_6
1070 * @arg @ref LL_DMA_CHANNEL_7
1071 * @retval None.
1072 */
LL_DMA_ResetChannel(const DMA_TypeDef * DMAx,uint32_t Channel)1073 __STATIC_INLINE void LL_DMA_ResetChannel(const DMA_TypeDef *DMAx, uint32_t Channel)
1074 {
1075 uint32_t dma_base_addr = (uint32_t)DMAx;
1076 SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_RESET);
1077 }
1078
1079 /**
1080 * @brief Suspend channel.
1081 * @note This API is used for all available DMA channels.
1082 * @rmtoll CCR SUSP LL_DMA_SuspendChannel
1083 * @param DMAx DMAx Instance
1084 * @param Channel This parameter can be one of the following values:
1085 * @arg @ref LL_DMA_CHANNEL_0
1086 * @arg @ref LL_DMA_CHANNEL_1
1087 * @arg @ref LL_DMA_CHANNEL_2
1088 * @arg @ref LL_DMA_CHANNEL_3
1089 * @arg @ref LL_DMA_CHANNEL_4
1090 * @arg @ref LL_DMA_CHANNEL_5
1091 * @arg @ref LL_DMA_CHANNEL_6
1092 * @arg @ref LL_DMA_CHANNEL_7
1093 * @retval None.
1094 */
LL_DMA_SuspendChannel(const DMA_TypeDef * DMAx,uint32_t Channel)1095 __STATIC_INLINE void LL_DMA_SuspendChannel(const DMA_TypeDef *DMAx, uint32_t Channel)
1096 {
1097 uint32_t dma_base_addr = (uint32_t)DMAx;
1098 SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_SUSP);
1099 }
1100
1101 /**
1102 * @brief Resume channel.
1103 * @note This API is used for all available DMA channels.
1104 * @rmtoll CCR SUSP LL_DMA_ResumeChannel
1105 * @param DMAx DMAx Instance
1106 * @param Channel This parameter can be one of the following values:
1107 * @arg @ref LL_DMA_CHANNEL_0
1108 * @arg @ref LL_DMA_CHANNEL_1
1109 * @arg @ref LL_DMA_CHANNEL_2
1110 * @arg @ref LL_DMA_CHANNEL_3
1111 * @arg @ref LL_DMA_CHANNEL_4
1112 * @arg @ref LL_DMA_CHANNEL_5
1113 * @arg @ref LL_DMA_CHANNEL_6
1114 * @arg @ref LL_DMA_CHANNEL_7
1115 * @retval None.
1116 */
LL_DMA_ResumeChannel(const DMA_TypeDef * DMAx,uint32_t Channel)1117 __STATIC_INLINE void LL_DMA_ResumeChannel(const DMA_TypeDef *DMAx, uint32_t Channel)
1118 {
1119 uint32_t dma_base_addr = (uint32_t)DMAx;
1120 CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_SUSP);
1121 }
1122
1123 /**
1124 * @brief Check if channel is suspended.
1125 * @note This API is used for all available DMA channels.
1126 * @rmtoll CCR SUSP LL_DMA_IsSuspendedChannel
1127 * @param DMAx DMAx Instance
1128 * @param Channel This parameter can be one of the following values:
1129 * @arg @ref LL_DMA_CHANNEL_0
1130 * @arg @ref LL_DMA_CHANNEL_1
1131 * @arg @ref LL_DMA_CHANNEL_2
1132 * @arg @ref LL_DMA_CHANNEL_3
1133 * @arg @ref LL_DMA_CHANNEL_4
1134 * @arg @ref LL_DMA_CHANNEL_5
1135 * @arg @ref LL_DMA_CHANNEL_6
1136 * @arg @ref LL_DMA_CHANNEL_7
1137 * @retval State of bit (1 or 0).
1138 */
LL_DMA_IsSuspendedChannel(const DMA_TypeDef * DMAx,uint32_t Channel)1139 __STATIC_INLINE uint32_t LL_DMA_IsSuspendedChannel(const DMA_TypeDef *DMAx, uint32_t Channel)
1140 {
1141 uint32_t dma_base_addr = (uint32_t)DMAx;
1142 return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_SUSP)
1143 == (DMA_CCR_SUSP)) ? 1UL : 0UL);
1144 }
1145
1146 /**
1147 * @brief Set linked-list base address.
1148 * @note This API is used for all available DMA channels.
1149 * @rmtoll CLBAR LBA LL_DMA_SetLinkedListBaseAddr
1150 * @param DMAx DMAx Instance
1151 * @param Channel This parameter can be one of the following values:
1152 * @arg @ref LL_DMA_CHANNEL_0
1153 * @arg @ref LL_DMA_CHANNEL_1
1154 * @arg @ref LL_DMA_CHANNEL_2
1155 * @arg @ref LL_DMA_CHANNEL_3
1156 * @arg @ref LL_DMA_CHANNEL_4
1157 * @arg @ref LL_DMA_CHANNEL_5
1158 * @arg @ref LL_DMA_CHANNEL_6
1159 * @arg @ref LL_DMA_CHANNEL_7
1160 * @param LinkedListBaseAddr Between 0 to 0xFFFF0000 (where the 4 LSB bytes
1161 * are always 0)
1162 * @retval None.
1163 */
LL_DMA_SetLinkedListBaseAddr(const DMA_TypeDef * DMAx,uint32_t Channel,uint32_t LinkedListBaseAddr)1164 __STATIC_INLINE void LL_DMA_SetLinkedListBaseAddr(const DMA_TypeDef *DMAx, uint32_t Channel,
1165 uint32_t LinkedListBaseAddr)
1166 {
1167 uint32_t dma_base_addr = (uint32_t)DMAx;
1168 MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLBAR, DMA_CLBAR_LBA,
1169 (LinkedListBaseAddr & DMA_CLBAR_LBA));
1170 }
1171
1172 /**
1173 * @brief Get linked-list base address.
1174 * @note This API is used for all available DMA channels.
1175 * @rmtoll CLBAR LBA LL_DMA_GetLinkedListBaseAddr
1176 * @param DMAx DMAx Instance
1177 * @param Channel This parameter can be one of the following values:
1178 * @arg @ref LL_DMA_CHANNEL_0
1179 * @arg @ref LL_DMA_CHANNEL_1
1180 * @arg @ref LL_DMA_CHANNEL_2
1181 * @arg @ref LL_DMA_CHANNEL_3
1182 * @arg @ref LL_DMA_CHANNEL_4
1183 * @arg @ref LL_DMA_CHANNEL_5
1184 * @arg @ref LL_DMA_CHANNEL_6
1185 * @arg @ref LL_DMA_CHANNEL_7
1186 * @retval Value between 0 to 0xFFFF0000 (where the 4 LSB bytes are always 0)
1187 */
LL_DMA_GetLinkedListBaseAddr(const DMA_TypeDef * DMAx,uint32_t Channel)1188 __STATIC_INLINE uint32_t LL_DMA_GetLinkedListBaseAddr(const DMA_TypeDef *DMAx, uint32_t Channel)
1189 {
1190 uint32_t dma_base_addr = (uint32_t)DMAx;
1191 return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLBAR, DMA_CLBAR_LBA));
1192 }
1193
1194 /**
1195 * @brief Configure all parameters linked to channel control.
1196 * @note This API is used for all available DMA channels.
1197 * @rmtoll CCR PRIO LL_DMA_ConfigControl\n
1198 * CCR LAP LL_DMA_ConfigControl\n
1199 * CCR LSM LL_DMA_ConfigControl
1200 * @param DMAx DMAx Instance
1201 * @param Channel This parameter can be one of the following values:
1202 * @arg @ref LL_DMA_CHANNEL_0
1203 * @arg @ref LL_DMA_CHANNEL_1
1204 * @arg @ref LL_DMA_CHANNEL_2
1205 * @arg @ref LL_DMA_CHANNEL_3
1206 * @arg @ref LL_DMA_CHANNEL_4
1207 * @arg @ref LL_DMA_CHANNEL_5
1208 * @arg @ref LL_DMA_CHANNEL_6
1209 * @arg @ref LL_DMA_CHANNEL_7
1210 * @param Configuration This parameter must be a combination of all the following values:
1211 * @arg @ref LL_DMA_LOW_PRIORITY_LOW_WEIGHT or @ref LL_DMA_LOW_PRIORITY_MID_WEIGHT or
1212 * @ref LL_DMA_LOW_PRIORITY_HIGH_WEIGHT or @ref LL_DMA_HIGH_PRIORITY
1213 * @arg @ref LL_DMA_LINK_ALLOCATED_PORT0 or @ref LL_DMA_LINK_ALLOCATED_PORT1
1214 * @arg @ref LL_DMA_LSM_FULL_EXECUTION or @ref LL_DMA_LSM_1LINK_EXECUTION
1215 *@retval None.
1216 */
LL_DMA_ConfigControl(const DMA_TypeDef * DMAx,uint32_t Channel,uint32_t Configuration)1217 __STATIC_INLINE void LL_DMA_ConfigControl(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Configuration)
1218 {
1219 uint32_t dma_base_addr = (uint32_t)DMAx;
1220 MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR,
1221 (DMA_CCR_PRIO | DMA_CCR_LAP | DMA_CCR_LSM), Configuration);
1222 }
1223
1224 /**
1225 * @brief Set priority level.
1226 * @note This API is used for all available DMA channels.
1227 * @rmtoll CCR PRIO LL_DMA_SetChannelPriorityLevel
1228 * @param DMAx DMAx Instance
1229 * @param Channel This parameter can be one of the following values:
1230 * @arg @ref LL_DMA_CHANNEL_0
1231 * @arg @ref LL_DMA_CHANNEL_1
1232 * @arg @ref LL_DMA_CHANNEL_2
1233 * @arg @ref LL_DMA_CHANNEL_3
1234 * @arg @ref LL_DMA_CHANNEL_4
1235 * @arg @ref LL_DMA_CHANNEL_5
1236 * @arg @ref LL_DMA_CHANNEL_6
1237 * @arg @ref LL_DMA_CHANNEL_7
1238 * @param Priority This parameter can be one of the following values:
1239 * @arg @ref LL_DMA_LOW_PRIORITY_LOW_WEIGHT
1240 * @arg @ref LL_DMA_LOW_PRIORITY_MID_WEIGHT
1241 * @arg @ref LL_DMA_LOW_PRIORITY_HIGH_WEIGHT
1242 * @arg @ref LL_DMA_HIGH_PRIORITY
1243 * @retval None.
1244 */
LL_DMA_SetChannelPriorityLevel(const DMA_TypeDef * DMAx,uint32_t Channel,uint32_t Priority)1245 __STATIC_INLINE void LL_DMA_SetChannelPriorityLevel(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Priority)
1246 {
1247 uint32_t dma_base_addr = (uint32_t)DMAx;
1248 MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_PRIO, Priority);
1249 }
1250
1251 /**
1252 * @brief Get Channel priority level.
1253 * @note This API is used for all available DMA channels.
1254 * @rmtoll CCR PRIO LL_DMA_GetChannelPriorityLevel
1255 * @param DMAx DMAx Instance
1256 * @param Channel This parameter can be one of the following values:
1257 * @arg @ref LL_DMA_CHANNEL_0
1258 * @arg @ref LL_DMA_CHANNEL_1
1259 * @arg @ref LL_DMA_CHANNEL_2
1260 * @arg @ref LL_DMA_CHANNEL_3
1261 * @arg @ref LL_DMA_CHANNEL_4
1262 * @arg @ref LL_DMA_CHANNEL_5
1263 * @arg @ref LL_DMA_CHANNEL_6
1264 * @arg @ref LL_DMA_CHANNEL_7
1265 * @retval Returned value can be one of the following values:
1266 * @arg @ref LL_DMA_LOW_PRIORITY_LOW_WEIGHT
1267 * @arg @ref LL_DMA_LOW_PRIORITY_MID_WEIGHT
1268 * @arg @ref LL_DMA_LOW_PRIORITY_HIGH_WEIGHT
1269 * @arg @ref LL_DMA_HIGH_PRIORITY
1270 */
LL_DMA_GetChannelPriorityLevel(const DMA_TypeDef * DMAx,uint32_t Channel)1271 __STATIC_INLINE uint32_t LL_DMA_GetChannelPriorityLevel(const DMA_TypeDef *DMAx, uint32_t Channel)
1272 {
1273 uint32_t dma_base_addr = (uint32_t)DMAx;
1274 return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_PRIO));
1275 }
1276
1277 /**
1278 * @brief Set linked-list allocated port.
1279 * @rmtoll CCR LAP LL_DMA_SetLinkAllocatedPort
1280 * @param DMAx DMAx Instance
1281 * @param Channel This parameter can be one of the following values:
1282 * @arg @ref LL_DMA_CHANNEL_0
1283 * @arg @ref LL_DMA_CHANNEL_1
1284 * @arg @ref LL_DMA_CHANNEL_2
1285 * @arg @ref LL_DMA_CHANNEL_3
1286 * @arg @ref LL_DMA_CHANNEL_4
1287 * @arg @ref LL_DMA_CHANNEL_5
1288 * @arg @ref LL_DMA_CHANNEL_6
1289 * @arg @ref LL_DMA_CHANNEL_7
1290 * @param LinkAllocatedPort This parameter can be one of the following values:
1291 * @arg @ref LL_DMA_LINK_ALLOCATED_PORT0
1292 * @arg @ref LL_DMA_LINK_ALLOCATED_PORT1
1293 * @retval None.
1294 */
LL_DMA_SetLinkAllocatedPort(const DMA_TypeDef * DMAx,uint32_t Channel,uint32_t LinkAllocatedPort)1295 __STATIC_INLINE void LL_DMA_SetLinkAllocatedPort(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t LinkAllocatedPort)
1296 {
1297 uint32_t dma_base_addr = (uint32_t)DMAx;
1298 MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR,
1299 DMA_CCR_LAP, LinkAllocatedPort);
1300 }
1301
1302 /**
1303 * @brief Get linked-list allocated port.
1304 * @rmtoll CCR LAP LL_DMA_GetLinkAllocatedPort
1305 * @param DMAx DMAx Instance
1306 * @param Channel This parameter can be one of the following values:
1307 * @arg @ref LL_DMA_CHANNEL_0
1308 * @arg @ref LL_DMA_CHANNEL_1
1309 * @arg @ref LL_DMA_CHANNEL_2
1310 * @arg @ref LL_DMA_CHANNEL_3
1311 * @arg @ref LL_DMA_CHANNEL_4
1312 * @arg @ref LL_DMA_CHANNEL_5
1313 * @arg @ref LL_DMA_CHANNEL_6
1314 * @arg @ref LL_DMA_CHANNEL_7
1315 * @retval Returned value can be one of the following values:
1316 * @arg @ref LL_DMA_LINK_ALLOCATED_PORT0
1317 * @arg @ref LL_DMA_LINK_ALLOCATED_PORT1
1318 */
LL_DMA_GetLinkAllocatedPort(const DMA_TypeDef * DMAx,uint32_t Channel)1319 __STATIC_INLINE uint32_t LL_DMA_GetLinkAllocatedPort(const DMA_TypeDef *DMAx, uint32_t Channel)
1320 {
1321 uint32_t dma_base_addr = (uint32_t)DMAx;
1322 return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_LAP));
1323 }
1324
1325 /**
1326 * @brief Set link step mode.
1327 * @note This API is used for all available DMA channels.
1328 * @rmtoll CCR LSM LL_DMA_SetLinkStepMode
1329 * @param DMAx DMAx Instance
1330 * @param Channel This parameter can be one of the following values:
1331 * @arg @ref LL_DMA_CHANNEL_0
1332 * @arg @ref LL_DMA_CHANNEL_1
1333 * @arg @ref LL_DMA_CHANNEL_2
1334 * @arg @ref LL_DMA_CHANNEL_3
1335 * @arg @ref LL_DMA_CHANNEL_4
1336 * @arg @ref LL_DMA_CHANNEL_5
1337 * @arg @ref LL_DMA_CHANNEL_6
1338 * @arg @ref LL_DMA_CHANNEL_7
1339 * @param LinkStepMode This parameter can be one of the following values:
1340 * @arg @ref LL_DMA_LSM_FULL_EXECUTION
1341 * @arg @ref LL_DMA_LSM_1LINK_EXECUTION
1342 * @retval None.
1343 */
LL_DMA_SetLinkStepMode(const DMA_TypeDef * DMAx,uint32_t Channel,uint32_t LinkStepMode)1344 __STATIC_INLINE void LL_DMA_SetLinkStepMode(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t LinkStepMode)
1345 {
1346 uint32_t dma_base_addr = (uint32_t)DMAx;
1347 MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_LSM, LinkStepMode);
1348 }
1349
1350 /**
1351 * @brief Get Link step mode.
1352 * @note This API is used for all available DMA channels.
1353 * @rmtoll CCR LSM LL_DMA_GetLinkStepMode
1354 * @param DMAx DMAx Instance
1355 * @param Channel This parameter can be one of the following values:
1356 * @arg @ref LL_DMA_CHANNEL_0
1357 * @arg @ref LL_DMA_CHANNEL_1
1358 * @arg @ref LL_DMA_CHANNEL_2
1359 * @arg @ref LL_DMA_CHANNEL_3
1360 * @arg @ref LL_DMA_CHANNEL_4
1361 * @arg @ref LL_DMA_CHANNEL_5
1362 * @arg @ref LL_DMA_CHANNEL_6
1363 * @arg @ref LL_DMA_CHANNEL_7
1364 * @retval Returned value can be one of the following values:
1365 * @arg @ref LL_DMA_LSM_FULL_EXECUTION
1366 * @arg @ref LL_DMA_LSM_1LINK_EXECUTION
1367 */
LL_DMA_GetLinkStepMode(const DMA_TypeDef * DMAx,uint32_t Channel)1368 __STATIC_INLINE uint32_t LL_DMA_GetLinkStepMode(const DMA_TypeDef *DMAx, uint32_t Channel)
1369 {
1370 uint32_t dma_base_addr = (uint32_t)DMAx;
1371 return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_LSM));
1372 }
1373
1374 /**
1375 * @brief Configure data transfer.
1376 * @note This API is used for all available DMA channels.
1377 * @rmtoll CTR1 DAP LL_DMA_ConfigTransfer\n
1378 * CTR1 DHX LL_DMA_ConfigTransfer\n
1379 * CTR1 DBX LL_DMA_ConfigTransfer\n
1380 * CTR1 DINC LL_DMA_ConfigTransfer\n
1381 * CTR1 SAP LL_DMA_ConfigTransfer\n
1382 * CTR1 SBX LL_DMA_ConfigTransfer\n
1383 * CTR1 PAM LL_DMA_ConfigTransfer\n
1384 * CTR1 SINC LL_DMA_ConfigTransfer
1385 * @param DMAx DMAx Instance
1386 * @param Channel This parameter can be one of the following values:
1387 * @arg @ref LL_DMA_CHANNEL_0
1388 * @arg @ref LL_DMA_CHANNEL_1
1389 * @arg @ref LL_DMA_CHANNEL_2
1390 * @arg @ref LL_DMA_CHANNEL_3
1391 * @arg @ref LL_DMA_CHANNEL_4
1392 * @arg @ref LL_DMA_CHANNEL_5
1393 * @arg @ref LL_DMA_CHANNEL_6
1394 * @arg @ref LL_DMA_CHANNEL_7
1395 * @param Configuration This parameter must be a combination of all the following values:
1396 * @arg @ref LL_DMA_DEST_ALLOCATED_PORT0 or @ref LL_DMA_DEST_ALLOCATED_PORT1
1397 * @arg @ref LL_DMA_DEST_HALFWORD_PRESERVE or @ref LL_DMA_DEST_HALFWORD_EXCHANGE
1398 * @arg @ref LL_DMA_DEST_BYTE_PRESERVE or @ref LL_DMA_DEST_BYTE_EXCHANGE
1399 * @arg @ref LL_DMA_SRC_BYTE_PRESERVE or @ref LL_DMA_SRC_BYTE_EXCHANGE
1400 * @arg @ref LL_DMA_DEST_FIXED or @ref LL_DMA_DEST_INCREMENT
1401 * @arg @ref LL_DMA_DEST_DATAWIDTH_BYTE or @ref LL_DMA_DEST_DATAWIDTH_HALFWORD or
1402 * @ref LL_DMA_DEST_DATAWIDTH_WORD
1403 * @arg @ref LL_DMA_SRC_ALLOCATED_PORT0 or @ref LL_DMA_SRC_ALLOCATED_PORT1
1404 * @arg @ref LL_DMA_DATA_ALIGN_ZEROPADD or @ref LL_DMA_DATA_ALIGN_SIGNEXTPADD or
1405 * @ref LL_DMA_DATA_PACK_UNPACK
1406 * @arg @ref LL_DMA_SRC_FIXED or @ref LL_DMA_SRC_INCREMENT
1407 * @arg @ref LL_DMA_SRC_DATAWIDTH_BYTE or @ref LL_DMA_SRC_DATAWIDTH_HALFWORD or
1408 * @ref LL_DMA_SRC_DATAWIDTH_WORD
1409 *@retval None.
1410 */
LL_DMA_ConfigTransfer(const DMA_TypeDef * DMAx,uint32_t Channel,uint32_t Configuration)1411 __STATIC_INLINE void LL_DMA_ConfigTransfer(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Configuration)
1412 {
1413 uint32_t dma_base_addr = (uint32_t)DMAx;
1414 MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1,
1415 DMA_CTR1_DAP | DMA_CTR1_DHX | DMA_CTR1_DBX | DMA_CTR1_SBX | DMA_CTR1_DINC | DMA_CTR1_SINC | \
1416 DMA_CTR1_SAP | DMA_CTR1_PAM | DMA_CTR1_DDW_LOG2 | DMA_CTR1_SDW_LOG2, Configuration);
1417 }
1418
1419 /**
1420 * @brief Configure source and destination burst length.
1421 * @rmtoll CTR1 DBL_1 LL_DMA_SetDestBurstLength\n
1422 * @rmtoll CTR1 SBL_1 LL_DMA_SetDestBurstLength
1423 * @param DMAx DMAx Instance
1424 * @param Channel This parameter can be one of the following values:
1425 * @arg @ref LL_DMA_CHANNEL_0
1426 * @arg @ref LL_DMA_CHANNEL_1
1427 * @arg @ref LL_DMA_CHANNEL_2
1428 * @arg @ref LL_DMA_CHANNEL_3
1429 * @arg @ref LL_DMA_CHANNEL_4
1430 * @arg @ref LL_DMA_CHANNEL_5
1431 * @arg @ref LL_DMA_CHANNEL_6
1432 * @arg @ref LL_DMA_CHANNEL_7
1433 * @param SrcBurstLength Between 1 to 64
1434 * @param DestBurstLength Between 1 to 64
1435 * @retval None.
1436 */
LL_DMA_ConfigBurstLength(const DMA_TypeDef * DMAx,uint32_t Channel,uint32_t SrcBurstLength,uint32_t DestBurstLength)1437 __STATIC_INLINE void LL_DMA_ConfigBurstLength(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t SrcBurstLength,
1438 uint32_t DestBurstLength)
1439 {
1440 uint32_t dma_base_addr = (uint32_t)DMAx;
1441 MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1,
1442 (DMA_CTR1_SBL_1 | DMA_CTR1_DBL_1), (((SrcBurstLength - 1U) << DMA_CTR1_SBL_1_Pos) & DMA_CTR1_SBL_1) | \
1443 (((DestBurstLength - 1U) << DMA_CTR1_DBL_1_Pos) & DMA_CTR1_DBL_1));
1444 }
1445
1446 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
1447 /**
1448 * @brief Configure all secure parameters linked to DMA channel.
1449 * @note This API is used for all available DMA channels.
1450 * @rmtoll SECCFGR SEC LL_DMA_ConfigChannelSecure\n
1451 * @rmtoll CTR1 SSEC LL_DMA_ConfigChannelSecure\n
1452 * @rmtoll CTR1 DSEC LL_DMA_ConfigChannelSecure
1453 * @param DMAx DMAx Instance
1454 * @param Channel This parameter can be one of the following values:
1455 * @arg @ref LL_DMA_CHANNEL_0
1456 * @arg @ref LL_DMA_CHANNEL_1
1457 * @arg @ref LL_DMA_CHANNEL_2
1458 * @arg @ref LL_DMA_CHANNEL_3
1459 * @arg @ref LL_DMA_CHANNEL_4
1460 * @arg @ref LL_DMA_CHANNEL_5
1461 * @arg @ref LL_DMA_CHANNEL_6
1462 * @arg @ref LL_DMA_CHANNEL_7
1463 * @param Configuration This parameter must be a combination of all the following values:
1464 * @arg @ref LL_DMA_CHANNEL_NSEC or @ref LL_DMA_CHANNEL_SEC
1465 * @arg @ref LL_DMA_CHANNEL_SRC_NSEC or @ref LL_DMA_CHANNEL_SRC_SEC
1466 * @arg @ref LL_DMA_CHANNEL_DEST_NSEC or @ref LL_DMA_CHANNEL_DEST_SEC
1467 * @retval None.
1468 */
LL_DMA_ConfigChannelSecure(DMA_TypeDef * DMAx,uint32_t Channel,uint32_t Configuration)1469 __STATIC_INLINE void LL_DMA_ConfigChannelSecure(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Configuration)
1470 {
1471 uint32_t dma_base_addr = (uint32_t)DMAx;
1472 MODIFY_REG(DMAx->SECCFGR, (DMA_SECCFGR_SEC0 << Channel), ((Configuration & LL_DMA_CHANNEL_SEC) << Channel));
1473 MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1,
1474 (DMA_CTR1_SSEC | DMA_CTR1_DSEC), (Configuration & (~LL_DMA_CHANNEL_SEC)));
1475 }
1476
1477 /**
1478 * @brief Enable security attribute of the DMA transfer to the destination.
1479 * @note This API is used for all available DMA channels.
1480 * @rmtoll CTR1 DSEC LL_DMA_EnableChannelDestSecure
1481 * @param DMAx DMAx Instance
1482 * @param Channel This parameter can be one of the following values:
1483 * @arg @ref LL_DMA_CHANNEL_0
1484 * @arg @ref LL_DMA_CHANNEL_1
1485 * @arg @ref LL_DMA_CHANNEL_2
1486 * @arg @ref LL_DMA_CHANNEL_3
1487 * @arg @ref LL_DMA_CHANNEL_4
1488 * @arg @ref LL_DMA_CHANNEL_5
1489 * @arg @ref LL_DMA_CHANNEL_6
1490 * @arg @ref LL_DMA_CHANNEL_7
1491 * @retval None.
1492 */
LL_DMA_EnableChannelDestSecure(const DMA_TypeDef * DMAx,uint32_t Channel)1493 __STATIC_INLINE void LL_DMA_EnableChannelDestSecure(const DMA_TypeDef *DMAx, uint32_t Channel)
1494 {
1495 uint32_t dma_base_addr = (uint32_t)DMAx;
1496 SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_DSEC);
1497 }
1498
1499 /**
1500 * @brief Disable security attribute of the DMA transfer to the destination.
1501 * @note This API is used for all available DMA channels.
1502 * @rmtoll CTR1 DSEC LL_DMA_DisableChannelDestSecure
1503 * @param DMAx DMAx Instance
1504 * @param Channel This parameter can be one of the following values:
1505 * @arg @ref LL_DMA_CHANNEL_0
1506 * @arg @ref LL_DMA_CHANNEL_1
1507 * @arg @ref LL_DMA_CHANNEL_2
1508 * @arg @ref LL_DMA_CHANNEL_3
1509 * @arg @ref LL_DMA_CHANNEL_4
1510 * @arg @ref LL_DMA_CHANNEL_5
1511 * @arg @ref LL_DMA_CHANNEL_6
1512 * @arg @ref LL_DMA_CHANNEL_7
1513 * @retval None.
1514 */
LL_DMA_DisableChannelDestSecure(const DMA_TypeDef * DMAx,uint32_t Channel)1515 __STATIC_INLINE void LL_DMA_DisableChannelDestSecure(const DMA_TypeDef *DMAx, uint32_t Channel)
1516 {
1517 uint32_t dma_base_addr = (uint32_t)DMAx;
1518 CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_DSEC);
1519 }
1520
1521 /**
1522 * @brief Check security attribute of the DMA transfer to the destination.
1523 * @note This API is used for all available DMA channels.
1524 * @rmtoll CTR1 DSEC LL_DMA_IsEnabledChannelDestSecure
1525 * @param DMAx DMAx Instance
1526 * @param Channel This parameter can be one of the following values:
1527 * @arg @ref LL_DMA_CHANNEL_0
1528 * @arg @ref LL_DMA_CHANNEL_1
1529 * @arg @ref LL_DMA_CHANNEL_2
1530 * @arg @ref LL_DMA_CHANNEL_3
1531 * @arg @ref LL_DMA_CHANNEL_4
1532 * @arg @ref LL_DMA_CHANNEL_5
1533 * @arg @ref LL_DMA_CHANNEL_6
1534 * @arg @ref LL_DMA_CHANNEL_7
1535 * @retval State of bit (1 or 0).
1536 */
LL_DMA_IsEnabledChannelDestSecure(const DMA_TypeDef * DMAx,uint32_t Channel)1537 __STATIC_INLINE uint32_t LL_DMA_IsEnabledChannelDestSecure(const DMA_TypeDef *DMAx, uint32_t Channel)
1538 {
1539 uint32_t dma_base_addr = (uint32_t)DMAx;
1540 return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_DSEC)
1541 == (DMA_CTR1_DSEC)) ? 1UL : 0UL);
1542 }
1543
1544 /**
1545 * @brief Enable security attribute of the DMA transfer from the source.
1546 * @note This API is used for all available DMA channels.
1547 * @rmtoll CTR1 SSEC LL_DMA_EnableChannelSrcSecure
1548 * @param DMAx DMAx Instance
1549 * @param Channel This parameter can be one of the following values:
1550 * @arg @ref LL_DMA_CHANNEL_0
1551 * @arg @ref LL_DMA_CHANNEL_1
1552 * @arg @ref LL_DMA_CHANNEL_2
1553 * @arg @ref LL_DMA_CHANNEL_3
1554 * @arg @ref LL_DMA_CHANNEL_4
1555 * @arg @ref LL_DMA_CHANNEL_5
1556 * @arg @ref LL_DMA_CHANNEL_6
1557 * @arg @ref LL_DMA_CHANNEL_7
1558 * @retval None.
1559 */
LL_DMA_EnableChannelSrcSecure(const DMA_TypeDef * DMAx,uint32_t Channel)1560 __STATIC_INLINE void LL_DMA_EnableChannelSrcSecure(const DMA_TypeDef *DMAx, uint32_t Channel)
1561 {
1562 uint32_t dma_base_addr = (uint32_t)DMAx;
1563 SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_SSEC);
1564 }
1565
1566 /**
1567 * @brief Disable security attribute of the DMA transfer from the source.
1568 * @note This API is used for all available DMA channels.
1569 * @rmtoll CTR1 SSEC LL_DMA_DisableChannelSrcSecure
1570 * @param DMAx DMAx Instance
1571 * @param Channel This parameter can be one of the following values:
1572 * @arg @ref LL_DMA_CHANNEL_0
1573 * @arg @ref LL_DMA_CHANNEL_1
1574 * @arg @ref LL_DMA_CHANNEL_2
1575 * @arg @ref LL_DMA_CHANNEL_3
1576 * @arg @ref LL_DMA_CHANNEL_4
1577 * @arg @ref LL_DMA_CHANNEL_5
1578 * @arg @ref LL_DMA_CHANNEL_6
1579 * @arg @ref LL_DMA_CHANNEL_7
1580 * @retval None.
1581 */
LL_DMA_DisableChannelSrcSecure(const DMA_TypeDef * DMAx,uint32_t Channel)1582 __STATIC_INLINE void LL_DMA_DisableChannelSrcSecure(const DMA_TypeDef *DMAx, uint32_t Channel)
1583 {
1584 uint32_t dma_base_addr = (uint32_t)DMAx;
1585 CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_SSEC);
1586 }
1587
1588 /**
1589 * @brief Check security attribute of the DMA transfer from the source.
1590 * @note This API is used for all available DMA channels.
1591 * @rmtoll CTR1 SSEC LL_DMA_IsEnabledChannelSrcSecure
1592 * @param DMAx DMAx Instance
1593 * @param Channel This parameter can be one of the following values:
1594 * @arg @ref LL_DMA_CHANNEL_0
1595 * @arg @ref LL_DMA_CHANNEL_1
1596 * @arg @ref LL_DMA_CHANNEL_2
1597 * @arg @ref LL_DMA_CHANNEL_3
1598 * @arg @ref LL_DMA_CHANNEL_4
1599 * @arg @ref LL_DMA_CHANNEL_5
1600 * @arg @ref LL_DMA_CHANNEL_6
1601 * @arg @ref LL_DMA_CHANNEL_7
1602 * @retval State of bit (1 or 0).
1603 */
LL_DMA_IsEnabledChannelSrcSecure(const DMA_TypeDef * DMAx,uint32_t Channel)1604 __STATIC_INLINE uint32_t LL_DMA_IsEnabledChannelSrcSecure(const DMA_TypeDef *DMAx, uint32_t Channel)
1605 {
1606 uint32_t dma_base_addr = (uint32_t)DMAx;
1607 return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_SSEC)
1608 == (DMA_CTR1_SSEC)) ? 1UL : 0UL);
1609 }
1610 #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
1611
1612 /**
1613 * @brief Set destination allocated port.
1614 * @rmtoll CTR1 DAP LL_DMA_SetDestAllocatedPort
1615 * @param DMAx DMAx Instance
1616 * @param Channel This parameter can be one of the following values:
1617 * @arg @ref LL_DMA_CHANNEL_0
1618 * @arg @ref LL_DMA_CHANNEL_1
1619 * @arg @ref LL_DMA_CHANNEL_2
1620 * @arg @ref LL_DMA_CHANNEL_3
1621 * @arg @ref LL_DMA_CHANNEL_4
1622 * @arg @ref LL_DMA_CHANNEL_5
1623 * @arg @ref LL_DMA_CHANNEL_6
1624 * @arg @ref LL_DMA_CHANNEL_7
1625 * @param DestAllocatedPort This parameter can be one of the following values:
1626 * @arg @ref LL_DMA_DEST_ALLOCATED_PORT0
1627 * @arg @ref LL_DMA_DEST_ALLOCATED_PORT1
1628 * @retval None.
1629 */
LL_DMA_SetDestAllocatedPort(const DMA_TypeDef * DMAx,uint32_t Channel,uint32_t DestAllocatedPort)1630 __STATIC_INLINE void LL_DMA_SetDestAllocatedPort(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t DestAllocatedPort)
1631 {
1632 uint32_t dma_base_addr = (uint32_t)DMAx;
1633 MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_DAP,
1634 DestAllocatedPort);
1635 }
1636
1637 /**
1638 * @brief Get destination allocated port.
1639 * @rmtoll CTR1 DAP LL_DMA_GetDestAllocatedPort
1640 * @param DMAx DMAx Instance
1641 * @param Channel This parameter can be one of the following values:
1642 * @arg @ref LL_DMA_CHANNEL_0
1643 * @arg @ref LL_DMA_CHANNEL_1
1644 * @arg @ref LL_DMA_CHANNEL_2
1645 * @arg @ref LL_DMA_CHANNEL_3
1646 * @arg @ref LL_DMA_CHANNEL_4
1647 * @arg @ref LL_DMA_CHANNEL_5
1648 * @arg @ref LL_DMA_CHANNEL_6
1649 * @arg @ref LL_DMA_CHANNEL_7
1650 * @retval Returned value can be one of the following values:
1651 * @arg @ref LL_DMA_DEST_ALLOCATED_PORT0
1652 * @arg @ref LL_DMA_DEST_ALLOCATED_PORT1
1653 */
LL_DMA_GetDestAllocatedPort(const DMA_TypeDef * DMAx,uint32_t Channel)1654 __STATIC_INLINE uint32_t LL_DMA_GetDestAllocatedPort(const DMA_TypeDef *DMAx, uint32_t Channel)
1655 {
1656 uint32_t dma_base_addr = (uint32_t)DMAx;
1657 return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_DAP));
1658 }
1659
1660 /**
1661 * @brief Set destination half-word exchange.
1662 * @rmtoll CTR1 DHX LL_DMA_SetDestHWordExchange
1663 * @param DMAx DMAx Instance
1664 * @param Channel This parameter can be one of the following values:
1665 * @arg @ref LL_DMA_CHANNEL_0
1666 * @arg @ref LL_DMA_CHANNEL_1
1667 * @arg @ref LL_DMA_CHANNEL_2
1668 * @arg @ref LL_DMA_CHANNEL_3
1669 * @arg @ref LL_DMA_CHANNEL_4
1670 * @arg @ref LL_DMA_CHANNEL_5
1671 * @arg @ref LL_DMA_CHANNEL_6
1672 * @arg @ref LL_DMA_CHANNEL_7
1673 * @param DestHWordExchange This parameter can be one of the following values:
1674 * @arg @ref LL_DMA_DEST_HALFWORD_PRESERVE
1675 * @arg @ref LL_DMA_DEST_HALFWORD_EXCHANGE
1676 * @retval None.
1677 */
LL_DMA_SetDestHWordExchange(const DMA_TypeDef * DMAx,uint32_t Channel,uint32_t DestHWordExchange)1678 __STATIC_INLINE void LL_DMA_SetDestHWordExchange(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t DestHWordExchange)
1679 {
1680 uint32_t dma_base_addr = (uint32_t)DMAx;
1681 MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_DHX,
1682 DestHWordExchange);
1683 }
1684
1685 /**
1686 * @brief Get destination half-word exchange.
1687 * @rmtoll CTR1 DHX LL_DMA_GetDestHWordExchange
1688 * @param DMAx DMAx Instance
1689 * @param Channel This parameter can be one of the following values:
1690 * @arg @ref LL_DMA_CHANNEL_0
1691 * @arg @ref LL_DMA_CHANNEL_1
1692 * @arg @ref LL_DMA_CHANNEL_2
1693 * @arg @ref LL_DMA_CHANNEL_3
1694 * @arg @ref LL_DMA_CHANNEL_4
1695 * @arg @ref LL_DMA_CHANNEL_5
1696 * @arg @ref LL_DMA_CHANNEL_6
1697 * @arg @ref LL_DMA_CHANNEL_7
1698 * @retval Returned value can be one of the following values:
1699 * @arg @ref LL_DMA_DEST_HALFWORD_PRESERVE
1700 * @arg @ref LL_DMA_DEST_HALFWORD_EXCHANGE
1701 */
LL_DMA_GetDestHWordExchange(const DMA_TypeDef * DMAx,uint32_t Channel)1702 __STATIC_INLINE uint32_t LL_DMA_GetDestHWordExchange(const DMA_TypeDef *DMAx, uint32_t Channel)
1703 {
1704 uint32_t dma_base_addr = (uint32_t)DMAx;
1705 return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_DHX));
1706 }
1707
1708 /**
1709 * @brief Set destination byte exchange.
1710 * @rmtoll CTR1 DBX LL_DMA_SetDestByteExchange
1711 * @param DMAx DMAx Instance
1712 * @param Channel This parameter can be one of the following values:
1713 * @arg @ref LL_DMA_CHANNEL_0
1714 * @arg @ref LL_DMA_CHANNEL_1
1715 * @arg @ref LL_DMA_CHANNEL_2
1716 * @arg @ref LL_DMA_CHANNEL_3
1717 * @arg @ref LL_DMA_CHANNEL_4
1718 * @arg @ref LL_DMA_CHANNEL_5
1719 * @arg @ref LL_DMA_CHANNEL_6
1720 * @arg @ref LL_DMA_CHANNEL_7
1721 * @param DestByteExchange This parameter can be one of the following values:
1722 * @arg @ref LL_DMA_DEST_BYTE_PRESERVE
1723 * @arg @ref LL_DMA_DEST_BYTE_EXCHANGE
1724 * @retval None.
1725 */
LL_DMA_SetDestByteExchange(const DMA_TypeDef * DMAx,uint32_t Channel,uint32_t DestByteExchange)1726 __STATIC_INLINE void LL_DMA_SetDestByteExchange(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t DestByteExchange)
1727 {
1728 uint32_t dma_base_addr = (uint32_t)DMAx;
1729 MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_DBX,
1730 DestByteExchange);
1731 }
1732
1733 /**
1734 * @brief Get destination byte exchange.
1735 * @rmtoll CTR1 DBX LL_DMA_GetDestByteExchange
1736 * @param DMAx DMAx Instance
1737 * @param Channel This parameter can be one of the following values:
1738 * @arg @ref LL_DMA_CHANNEL_0
1739 * @arg @ref LL_DMA_CHANNEL_1
1740 * @arg @ref LL_DMA_CHANNEL_2
1741 * @arg @ref LL_DMA_CHANNEL_3
1742 * @arg @ref LL_DMA_CHANNEL_4
1743 * @arg @ref LL_DMA_CHANNEL_5
1744 * @arg @ref LL_DMA_CHANNEL_6
1745 * @arg @ref LL_DMA_CHANNEL_7
1746 * @retval Returned value can be one of the following values:
1747 * @arg @ref LL_DMA_DEST_BYTE_PRESERVE
1748 * @arg @ref LL_DMA_DEST_BYTE_EXCHANGE
1749 */
LL_DMA_GetDestByteExchange(const DMA_TypeDef * DMAx,uint32_t Channel)1750 __STATIC_INLINE uint32_t LL_DMA_GetDestByteExchange(const DMA_TypeDef *DMAx, uint32_t Channel)
1751 {
1752 uint32_t dma_base_addr = (uint32_t)DMAx;
1753 return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_DBX));
1754 }
1755
1756 /**
1757 * @brief Set source byte exchange.
1758 * @rmtoll CTR1 SBX LL_DMA_SetSrcByteExchange
1759 * @param DMAx DMAx Instance
1760 * @param Channel This parameter can be one of the following values:
1761 * @arg @ref LL_DMA_CHANNEL_0
1762 * @arg @ref LL_DMA_CHANNEL_1
1763 * @arg @ref LL_DMA_CHANNEL_2
1764 * @arg @ref LL_DMA_CHANNEL_3
1765 * @arg @ref LL_DMA_CHANNEL_4
1766 * @arg @ref LL_DMA_CHANNEL_5
1767 * @arg @ref LL_DMA_CHANNEL_6
1768 * @arg @ref LL_DMA_CHANNEL_7
1769 * @param SrcByteExchange This parameter can be one of the following values:
1770 * @arg @ref LL_DMA_SRC_BYTE_PRESERVE
1771 * @arg @ref LL_DMA_SRC_BYTE_EXCHANGE
1772 * @retval None.
1773 */
LL_DMA_SetSrcByteExchange(const DMA_TypeDef * DMAx,uint32_t Channel,uint32_t SrcByteExchange)1774 __STATIC_INLINE void LL_DMA_SetSrcByteExchange(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t SrcByteExchange)
1775 {
1776 uint32_t dma_base_addr = (uint32_t)DMAx;
1777 MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_SBX,
1778 SrcByteExchange);
1779 }
1780
1781 /**
1782 * @brief Get source byte exchange.
1783 * @rmtoll CTR1 SBX LL_DMA_GetSrcByteExchange
1784 * @param DMAx DMAx Instance
1785 * @param Channel This parameter can be one of the following values:
1786 * @arg @ref LL_DMA_CHANNEL_0
1787 * @arg @ref LL_DMA_CHANNEL_1
1788 * @arg @ref LL_DMA_CHANNEL_2
1789 * @arg @ref LL_DMA_CHANNEL_3
1790 * @arg @ref LL_DMA_CHANNEL_4
1791 * @arg @ref LL_DMA_CHANNEL_5
1792 * @arg @ref LL_DMA_CHANNEL_6
1793 * @arg @ref LL_DMA_CHANNEL_7
1794 * @retval Returned value can be one of the following values:
1795 * @arg @ref LL_DMA_SRC_BYTE_PRESERVE
1796 * @arg @ref LL_DMA_SRC_BYTE_EXCHANGE
1797 */
LL_DMA_GetSrcByteExchange(const DMA_TypeDef * DMAx,uint32_t Channel)1798 __STATIC_INLINE uint32_t LL_DMA_GetSrcByteExchange(const DMA_TypeDef *DMAx, uint32_t Channel)
1799 {
1800 uint32_t dma_base_addr = (uint32_t)DMAx;
1801 return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_SBX));
1802 }
1803
1804 /**
1805 * @brief Set destination burst length.
1806 * @rmtoll CTR1 DBL_1 LL_DMA_SetDestBurstLength
1807 * @param DMAx DMAx Instance
1808 * @param Channel This parameter can be one of the following values:
1809 * @arg @ref LL_DMA_CHANNEL_0
1810 * @arg @ref LL_DMA_CHANNEL_1
1811 * @arg @ref LL_DMA_CHANNEL_2
1812 * @arg @ref LL_DMA_CHANNEL_3
1813 * @arg @ref LL_DMA_CHANNEL_4
1814 * @arg @ref LL_DMA_CHANNEL_5
1815 * @arg @ref LL_DMA_CHANNEL_6
1816 * @arg @ref LL_DMA_CHANNEL_7
1817 * @param DestBurstLength Between 1 to 64
1818 * @retval None.
1819 */
LL_DMA_SetDestBurstLength(const DMA_TypeDef * DMAx,uint32_t Channel,uint32_t DestBurstLength)1820 __STATIC_INLINE void LL_DMA_SetDestBurstLength(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t DestBurstLength)
1821 {
1822 uint32_t dma_base_addr = (uint32_t)DMAx;
1823 MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_DBL_1,
1824 ((DestBurstLength - 1U) << DMA_CTR1_DBL_1_Pos) & DMA_CTR1_DBL_1);
1825 }
1826
1827 /**
1828 * @brief Get destination burst length.
1829 * @rmtoll CTR1 DBL_1 LL_DMA_GetDestBurstLength
1830 * @param DMAx DMAx Instance
1831 * @param Channel This parameter can be one of the following values:
1832 * @arg @ref LL_DMA_CHANNEL_0
1833 * @arg @ref LL_DMA_CHANNEL_1
1834 * @arg @ref LL_DMA_CHANNEL_2
1835 * @arg @ref LL_DMA_CHANNEL_3
1836 * @arg @ref LL_DMA_CHANNEL_4
1837 * @arg @ref LL_DMA_CHANNEL_5
1838 * @arg @ref LL_DMA_CHANNEL_6
1839 * @arg @ref LL_DMA_CHANNEL_7
1840 * @retval Between 1 to 64.
1841 */
LL_DMA_GetDestBurstLength(const DMA_TypeDef * DMAx,uint32_t Channel)1842 __STATIC_INLINE uint32_t LL_DMA_GetDestBurstLength(const DMA_TypeDef *DMAx, uint32_t Channel)
1843 {
1844 uint32_t dma_base_addr = (uint32_t)DMAx;
1845 return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1,
1846 DMA_CTR1_DBL_1) >> DMA_CTR1_DBL_1_Pos) + 1U);
1847 }
1848
1849 /**
1850 * @brief Set destination increment mode.
1851 * @rmtoll CTR1 DINC LL_DMA_SetDestIncMode
1852 * @param DMAx DMAx Instance
1853 * @param Channel This parameter can be one of the following values:
1854 * @arg @ref LL_DMA_CHANNEL_0
1855 * @arg @ref LL_DMA_CHANNEL_1
1856 * @arg @ref LL_DMA_CHANNEL_2
1857 * @arg @ref LL_DMA_CHANNEL_3
1858 * @arg @ref LL_DMA_CHANNEL_4
1859 * @arg @ref LL_DMA_CHANNEL_5
1860 * @arg @ref LL_DMA_CHANNEL_6
1861 * @arg @ref LL_DMA_CHANNEL_7
1862 * @param DestInc This parameter can be one of the following values:
1863 * @arg @ref LL_DMA_DEST_FIXED
1864 * @arg @ref LL_DMA_DEST_INCREMENT
1865 * @retval None.
1866 */
LL_DMA_SetDestIncMode(const DMA_TypeDef * DMAx,uint32_t Channel,uint32_t DestInc)1867 __STATIC_INLINE void LL_DMA_SetDestIncMode(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t DestInc)
1868 {
1869 uint32_t dma_base_addr = (uint32_t)DMAx;
1870 MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_DINC, DestInc);
1871 }
1872
1873 /**
1874 * @brief Get destination increment mode.
1875 * @note This API is used for all available DMA channels.
1876 * @rmtoll CTR1 DINC LL_DMA_GetDestIncMode
1877 * @param DMAx DMAx Instance
1878 * @param Channel This parameter can be one of the following values:
1879 * @arg @ref LL_DMA_CHANNEL_0
1880 * @arg @ref LL_DMA_CHANNEL_1
1881 * @arg @ref LL_DMA_CHANNEL_2
1882 * @arg @ref LL_DMA_CHANNEL_3
1883 * @arg @ref LL_DMA_CHANNEL_4
1884 * @arg @ref LL_DMA_CHANNEL_5
1885 * @arg @ref LL_DMA_CHANNEL_6
1886 * @arg @ref LL_DMA_CHANNEL_7
1887 * @retval Returned value can be one of the following values:
1888 * @arg @ref LL_DMA_DEST_FIXED
1889 * @arg @ref LL_DMA_DEST_INCREMENT
1890 */
LL_DMA_GetDestIncMode(const DMA_TypeDef * DMAx,uint32_t Channel)1891 __STATIC_INLINE uint32_t LL_DMA_GetDestIncMode(const DMA_TypeDef *DMAx, uint32_t Channel)
1892 {
1893 uint32_t dma_base_addr = (uint32_t)DMAx;
1894 return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_DINC));
1895 }
1896
1897 /**
1898 * @brief Set destination data width.
1899 * @note This API is used for all available DMA channels.
1900 * @rmtoll CTR1 DDW_LOG2 LL_DMA_SetDestDataWidth
1901 * @param DMAx DMAx Instance
1902 * @param Channel This parameter can be one of the following values:
1903 * @arg @ref LL_DMA_CHANNEL_0
1904 * @arg @ref LL_DMA_CHANNEL_1
1905 * @arg @ref LL_DMA_CHANNEL_2
1906 * @arg @ref LL_DMA_CHANNEL_3
1907 * @arg @ref LL_DMA_CHANNEL_4
1908 * @arg @ref LL_DMA_CHANNEL_5
1909 * @arg @ref LL_DMA_CHANNEL_6
1910 * @arg @ref LL_DMA_CHANNEL_7
1911 * @param DestDataWidth This parameter can be one of the following values:
1912 * @arg @ref LL_DMA_DEST_DATAWIDTH_BYTE
1913 * @arg @ref LL_DMA_DEST_DATAWIDTH_HALFWORD
1914 * @arg @ref LL_DMA_DEST_DATAWIDTH_WORD
1915 * @retval None.
1916 */
LL_DMA_SetDestDataWidth(const DMA_TypeDef * DMAx,uint32_t Channel,uint32_t DestDataWidth)1917 __STATIC_INLINE void LL_DMA_SetDestDataWidth(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t DestDataWidth)
1918 {
1919 uint32_t dma_base_addr = (uint32_t)DMAx;
1920 MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_DDW_LOG2,
1921 DestDataWidth);
1922 }
1923
1924 /**
1925 * @brief Get destination data width.
1926 * @note This API is used for all available DMA channels.
1927 * @rmtoll CTR1 DDW_LOG2 LL_DMA_GetDestDataWidth
1928 * @param DMAx DMAx Instance
1929 * @param Channel This parameter can be one of the following values:
1930 * @arg @ref LL_DMA_CHANNEL_0
1931 * @arg @ref LL_DMA_CHANNEL_1
1932 * @arg @ref LL_DMA_CHANNEL_2
1933 * @arg @ref LL_DMA_CHANNEL_3
1934 * @arg @ref LL_DMA_CHANNEL_4
1935 * @arg @ref LL_DMA_CHANNEL_5
1936 * @arg @ref LL_DMA_CHANNEL_6
1937 * @arg @ref LL_DMA_CHANNEL_7
1938 * @retval Returned value can be one of the following values:
1939 * @arg @ref LL_DMA_DEST_DATAWIDTH_BYTE
1940 * @arg @ref LL_DMA_DEST_DATAWIDTH_HALFWORD
1941 * @arg @ref LL_DMA_DEST_DATAWIDTH_WORD
1942 */
LL_DMA_GetDestDataWidth(const DMA_TypeDef * DMAx,uint32_t Channel)1943 __STATIC_INLINE uint32_t LL_DMA_GetDestDataWidth(const DMA_TypeDef *DMAx, uint32_t Channel)
1944 {
1945 uint32_t dma_base_addr = (uint32_t)DMAx;
1946 return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_DDW_LOG2));
1947 }
1948
1949 /**
1950 * @brief Set source allocated port.
1951 * @rmtoll CTR1 SAP LL_DMA_SetSrcAllocatedPort
1952 * @param DMAx DMAx Instance
1953 * @param Channel This parameter can be one of the following values:
1954 * @arg @ref LL_DMA_CHANNEL_0
1955 * @arg @ref LL_DMA_CHANNEL_1
1956 * @arg @ref LL_DMA_CHANNEL_2
1957 * @arg @ref LL_DMA_CHANNEL_3
1958 * @arg @ref LL_DMA_CHANNEL_4
1959 * @arg @ref LL_DMA_CHANNEL_5
1960 * @arg @ref LL_DMA_CHANNEL_6
1961 * @arg @ref LL_DMA_CHANNEL_7
1962 * @param SrcAllocatedPort This parameter can be one of the following values:
1963 * @arg @ref LL_DMA_SRC_ALLOCATED_PORT0
1964 * @arg @ref LL_DMA_SRC_ALLOCATED_PORT1
1965 * @retval None.
1966 */
LL_DMA_SetSrcAllocatedPort(const DMA_TypeDef * DMAx,uint32_t Channel,uint32_t SrcAllocatedPort)1967 __STATIC_INLINE void LL_DMA_SetSrcAllocatedPort(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t SrcAllocatedPort)
1968 {
1969 uint32_t dma_base_addr = (uint32_t)DMAx;
1970 MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_SAP,
1971 SrcAllocatedPort);
1972 }
1973
1974 /**
1975 * @brief Get source allocated port.
1976 * @rmtoll CTR1 SAP LL_DMA_GetSrcAllocatedPort
1977 * @param DMAx DMAx Instance
1978 * @param Channel This parameter can be one of the following values:
1979 * @arg @ref LL_DMA_CHANNEL_0
1980 * @arg @ref LL_DMA_CHANNEL_1
1981 * @arg @ref LL_DMA_CHANNEL_2
1982 * @arg @ref LL_DMA_CHANNEL_3
1983 * @arg @ref LL_DMA_CHANNEL_4
1984 * @arg @ref LL_DMA_CHANNEL_5
1985 * @arg @ref LL_DMA_CHANNEL_6
1986 * @arg @ref LL_DMA_CHANNEL_7
1987 * @retval Returned value can be one of the following values:
1988 * @arg @ref LL_DMA_SRC_ALLOCATED_PORT0
1989 * @arg @ref LL_DMA_SRC_ALLOCATED_PORT1
1990 */
LL_DMA_GetSrcAllocatedPort(const DMA_TypeDef * DMAx,uint32_t Channel)1991 __STATIC_INLINE uint32_t LL_DMA_GetSrcAllocatedPort(const DMA_TypeDef *DMAx, uint32_t Channel)
1992 {
1993 uint32_t dma_base_addr = (uint32_t)DMAx;
1994 return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_SAP));
1995 }
1996
1997 /**
1998 * @brief Set data alignment mode.
1999 * @note This API is used for all available DMA channels.
2000 * @rmtoll CTR1 PAM LL_DMA_SetDataAlignment
2001 * @param DMAx DMAx Instance
2002 * @param Channel This parameter can be one of the following values:
2003 * @arg @ref LL_DMA_CHANNEL_0
2004 * @arg @ref LL_DMA_CHANNEL_1
2005 * @arg @ref LL_DMA_CHANNEL_2
2006 * @arg @ref LL_DMA_CHANNEL_3
2007 * @arg @ref LL_DMA_CHANNEL_4
2008 * @arg @ref LL_DMA_CHANNEL_5
2009 * @arg @ref LL_DMA_CHANNEL_6
2010 * @arg @ref LL_DMA_CHANNEL_7
2011 * @param DataAlignment This parameter can be one of the following values:
2012 * @arg @ref LL_DMA_DATA_ALIGN_ZEROPADD
2013 * @arg @ref LL_DMA_DATA_ALIGN_SIGNEXTPADD
2014 * @arg @ref LL_DMA_DATA_PACK_UNPACK
2015 * @retval None.
2016 */
LL_DMA_SetDataAlignment(const DMA_TypeDef * DMAx,uint32_t Channel,uint32_t DataAlignment)2017 __STATIC_INLINE void LL_DMA_SetDataAlignment(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t DataAlignment)
2018 {
2019 uint32_t dma_base_addr = (uint32_t)DMAx;
2020 MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_PAM,
2021 DataAlignment);
2022 }
2023
2024 /**
2025 * @brief Get data alignment mode.
2026 * @note This API is used for all available DMA channels.
2027 * @rmtoll CTR1 PAM LL_DMA_GetDataAlignment
2028 * @param DMAx DMAx Instance
2029 * @param Channel This parameter can be one of the following values:
2030 * @arg @ref LL_DMA_CHANNEL_0
2031 * @arg @ref LL_DMA_CHANNEL_1
2032 * @arg @ref LL_DMA_CHANNEL_2
2033 * @arg @ref LL_DMA_CHANNEL_3
2034 * @arg @ref LL_DMA_CHANNEL_4
2035 * @arg @ref LL_DMA_CHANNEL_5
2036 * @arg @ref LL_DMA_CHANNEL_6
2037 * @arg @ref LL_DMA_CHANNEL_7
2038 * @retval Returned value can be one of the following values:
2039 * @arg @ref LL_DMA_DATA_ALIGN_ZEROPADD
2040 * @arg @ref LL_DMA_DATA_ALIGN_SIGNEXTPADD
2041 * @arg @ref LL_DMA_DATA_PACK_UNPACK
2042 */
LL_DMA_GetDataAlignment(const DMA_TypeDef * DMAx,uint32_t Channel)2043 __STATIC_INLINE uint32_t LL_DMA_GetDataAlignment(const DMA_TypeDef *DMAx, uint32_t Channel)
2044 {
2045 uint32_t dma_base_addr = (uint32_t)DMAx;
2046 return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_PAM));
2047 }
2048
2049 /**
2050 * @brief Set source burst length.
2051 * @rmtoll CTR1 SBL_1 LL_DMA_SetSrcBurstLength
2052 * @param DMAx DMAx Instance
2053 * @param Channel This parameter can be one of the following values:
2054 * @arg @ref LL_DMA_CHANNEL_0
2055 * @arg @ref LL_DMA_CHANNEL_1
2056 * @arg @ref LL_DMA_CHANNEL_2
2057 * @arg @ref LL_DMA_CHANNEL_3
2058 * @arg @ref LL_DMA_CHANNEL_4
2059 * @arg @ref LL_DMA_CHANNEL_5
2060 * @arg @ref LL_DMA_CHANNEL_6
2061 * @arg @ref LL_DMA_CHANNEL_7
2062 * @param SrcBurstLength Between 1 to 64
2063 * @retval None.
2064 */
LL_DMA_SetSrcBurstLength(const DMA_TypeDef * DMAx,uint32_t Channel,uint32_t SrcBurstLength)2065 __STATIC_INLINE void LL_DMA_SetSrcBurstLength(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t SrcBurstLength)
2066 {
2067 uint32_t dma_base_addr = (uint32_t)DMAx;
2068 MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_SBL_1,
2069 ((SrcBurstLength - 1U) << DMA_CTR1_SBL_1_Pos) & DMA_CTR1_SBL_1);
2070 }
2071
2072 /**
2073 * @brief Get source burst length.
2074 * @rmtoll CTR1 SBL_1 LL_DMA_GetSrcBurstLength
2075 * @param DMAx DMAx Instance
2076 * @param Channel This parameter can be one of the following values:
2077 * @arg @ref LL_DMA_CHANNEL_0
2078 * @arg @ref LL_DMA_CHANNEL_1
2079 * @arg @ref LL_DMA_CHANNEL_2
2080 * @arg @ref LL_DMA_CHANNEL_3
2081 * @arg @ref LL_DMA_CHANNEL_4
2082 * @arg @ref LL_DMA_CHANNEL_5
2083 * @arg @ref LL_DMA_CHANNEL_6
2084 * @arg @ref LL_DMA_CHANNEL_7
2085 * @retval Between 1 to 64
2086 * @retval None.
2087 */
LL_DMA_GetSrcBurstLength(const DMA_TypeDef * DMAx,uint32_t Channel)2088 __STATIC_INLINE uint32_t LL_DMA_GetSrcBurstLength(const DMA_TypeDef *DMAx, uint32_t Channel)
2089 {
2090 uint32_t dma_base_addr = (uint32_t)DMAx;
2091 return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1,
2092 DMA_CTR1_SBL_1) >> DMA_CTR1_SBL_1_Pos) + 1U);
2093 }
2094
2095 /**
2096 * @brief Set source increment mode.
2097 * @note This API is used for all available DMA channels.
2098 * @rmtoll CTR1 SINC LL_DMA_SetSrcIncMode
2099 * @param DMAx DMAx Instance
2100 * @param Channel This parameter can be one of the following values:
2101 * @arg @ref LL_DMA_CHANNEL_0
2102 * @arg @ref LL_DMA_CHANNEL_1
2103 * @arg @ref LL_DMA_CHANNEL_2
2104 * @arg @ref LL_DMA_CHANNEL_3
2105 * @arg @ref LL_DMA_CHANNEL_4
2106 * @arg @ref LL_DMA_CHANNEL_5
2107 * @arg @ref LL_DMA_CHANNEL_6
2108 * @arg @ref LL_DMA_CHANNEL_7
2109 * @param SrcInc This parameter can be one of the following values:
2110 * @arg @ref LL_DMA_SRC_FIXED
2111 * @arg @ref LL_DMA_SRC_INCREMENT
2112 * @retval None.
2113 */
LL_DMA_SetSrcIncMode(const DMA_TypeDef * DMAx,uint32_t Channel,uint32_t SrcInc)2114 __STATIC_INLINE void LL_DMA_SetSrcIncMode(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t SrcInc)
2115 {
2116 uint32_t dma_base_addr = (uint32_t)DMAx;
2117 MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_SINC, SrcInc);
2118 }
2119
2120 /**
2121 * @brief Get source increment mode.
2122 * @note This API is used for all available DMA channels.
2123 * @rmtoll CTR1 SINC LL_DMA_GetSrcIncMode
2124 * @param DMAx DMAx Instance
2125 * @param Channel This parameter can be one of the following values:
2126 * @arg @ref LL_DMA_CHANNEL_0
2127 * @arg @ref LL_DMA_CHANNEL_1
2128 * @arg @ref LL_DMA_CHANNEL_2
2129 * @arg @ref LL_DMA_CHANNEL_3
2130 * @arg @ref LL_DMA_CHANNEL_4
2131 * @arg @ref LL_DMA_CHANNEL_5
2132 * @arg @ref LL_DMA_CHANNEL_6
2133 * @arg @ref LL_DMA_CHANNEL_7
2134 * @retval Returned value can be one of the following values:
2135 * @arg @ref LL_DMA_SRC_FIXED
2136 * @arg @ref LL_DMA_SRC_INCREMENT
2137 */
LL_DMA_GetSrcIncMode(const DMA_TypeDef * DMAx,uint32_t Channel)2138 __STATIC_INLINE uint32_t LL_DMA_GetSrcIncMode(const DMA_TypeDef *DMAx, uint32_t Channel)
2139 {
2140 uint32_t dma_base_addr = (uint32_t)DMAx;
2141 return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_SINC));
2142 }
2143
2144 /**
2145 * @brief Set source data width.
2146 * @note This API is used for all available DMA channels.
2147 * @rmtoll CTR1 SDW_LOG2 LL_DMA_SetSrcDataWidth
2148 * @param DMAx DMAx Instance
2149 * @param Channel This parameter can be one of the following values:
2150 * @arg @ref LL_DMA_CHANNEL_0
2151 * @arg @ref LL_DMA_CHANNEL_1
2152 * @arg @ref LL_DMA_CHANNEL_2
2153 * @arg @ref LL_DMA_CHANNEL_3
2154 * @arg @ref LL_DMA_CHANNEL_4
2155 * @arg @ref LL_DMA_CHANNEL_5
2156 * @arg @ref LL_DMA_CHANNEL_6
2157 * @arg @ref LL_DMA_CHANNEL_7
2158 * @param SrcDataWidth This parameter can be one of the following values:
2159 * @arg @ref LL_DMA_SRC_DATAWIDTH_BYTE
2160 * @arg @ref LL_DMA_SRC_DATAWIDTH_HALFWORD
2161 * @arg @ref LL_DMA_SRC_DATAWIDTH_WORD
2162 * @retval None.
2163 */
LL_DMA_SetSrcDataWidth(const DMA_TypeDef * DMAx,uint32_t Channel,uint32_t SrcDataWidth)2164 __STATIC_INLINE void LL_DMA_SetSrcDataWidth(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t SrcDataWidth)
2165 {
2166 uint32_t dma_base_addr = (uint32_t)DMAx;
2167 MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_SDW_LOG2,
2168 SrcDataWidth);
2169 }
2170
2171 /**
2172 * @brief Get Source Data width.
2173 * @note This API is used for all available DMA channels.
2174 * @rmtoll CTR1 SDW_LOG2 LL_DMA_GetSrcDataWidth
2175 * @param DMAx DMAx Instance
2176 * @param Channel This parameter can be one of the following values:
2177 * @arg @ref LL_DMA_CHANNEL_0
2178 * @arg @ref LL_DMA_CHANNEL_1
2179 * @arg @ref LL_DMA_CHANNEL_2
2180 * @arg @ref LL_DMA_CHANNEL_3
2181 * @arg @ref LL_DMA_CHANNEL_4
2182 * @arg @ref LL_DMA_CHANNEL_5
2183 * @arg @ref LL_DMA_CHANNEL_6
2184 * @arg @ref LL_DMA_CHANNEL_7
2185 * @retval Returned value can be one of the following values:
2186 * @arg @ref LL_DMA_SRC_DATAWIDTH_BYTE
2187 * @arg @ref LL_DMA_SRC_DATAWIDTH_HALFWORD
2188 * @arg @ref LL_DMA_SRC_DATAWIDTH_WORD
2189 */
LL_DMA_GetSrcDataWidth(const DMA_TypeDef * DMAx,uint32_t Channel)2190 __STATIC_INLINE uint32_t LL_DMA_GetSrcDataWidth(const DMA_TypeDef *DMAx, uint32_t Channel)
2191 {
2192 uint32_t dma_base_addr = (uint32_t)DMAx;
2193 return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_SDW_LOG2));
2194 }
2195
2196 /**
2197 * @brief Configure channel transfer.
2198 * @note This API is used for all available DMA channels.
2199 * @rmtoll CTR2 TCEM LL_DMA_ConfigChannelTransfer\n
2200 * CTR2 TRIGPOL LL_DMA_ConfigChannelTransfer\n
2201 * CTR2 TRIGM LL_DMA_ConfigChannelTransfer\n
2202 * CTR2 BREQ LL_DMA_ConfigChannelTransfer\n
2203 * CTR2 DREQ LL_DMA_ConfigChannelTransfer\n
2204 * CTR2 SWREQ LL_DMA_ConfigChannelTransfer
2205 * @param DMAx DMAx Instance
2206 * @param Channel This parameter can be one of the following values:
2207 * @arg @ref LL_DMA_CHANNEL_0
2208 * @arg @ref LL_DMA_CHANNEL_1
2209 * @arg @ref LL_DMA_CHANNEL_2
2210 * @arg @ref LL_DMA_CHANNEL_3
2211 * @arg @ref LL_DMA_CHANNEL_4
2212 * @arg @ref LL_DMA_CHANNEL_5
2213 * @arg @ref LL_DMA_CHANNEL_6
2214 * @arg @ref LL_DMA_CHANNEL_7
2215 * @param Configuration This parameter must be a combination of all the following values:
2216 * @arg @ref LL_DMA_TCEM_BLK_TRANSFER or @ref LL_DMA_TCEM_RPT_BLK_TRANSFER or
2217 * @ref LL_DMA_TCEM_EACH_LLITEM_TRANSFER or @ref LL_DMA_TCEM_LAST_LLITEM_TRANSFER
2218 * @arg @ref LL_DMA_HWREQUEST_SINGLEBURST or @ref LL_DMA_HWREQUEST_BLK
2219 * @arg @ref LL_DMA_TRIG_POLARITY_MASKED or @ref LL_DMA_TRIG_POLARITY_RISING or
2220 * @ref LL_DMA_TRIG_POLARITY_FALLING
2221 * @arg @ref LL_DMA_TRIGM_BLK_TRANSFER or @ref LL_DMA_TRIGM_RPT_BLK_TRANSFER or
2222 * @ref LL_DMA_TRIGM_LLI_LINK_TRANSFER or @ref LL_DMA_TRIGM_SINGLBURST_TRANSFER
2223 * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY or @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH or
2224 * @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
2225 *@retval None.
2226 */
LL_DMA_ConfigChannelTransfer(const DMA_TypeDef * DMAx,uint32_t Channel,uint32_t Configuration)2227 __STATIC_INLINE void LL_DMA_ConfigChannelTransfer(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Configuration)
2228 {
2229 uint32_t dma_base_addr = (uint32_t)DMAx;
2230 MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR2,
2231 (DMA_CTR2_TCEM | DMA_CTR2_TRIGPOL | DMA_CTR2_TRIGM | DMA_CTR2_DREQ | DMA_CTR2_SWREQ | DMA_CTR2_BREQ),
2232 Configuration);
2233 }
2234
2235 /**
2236 * @brief Set transfer event mode.
2237 * @note This API is used for all available DMA channels.
2238 * @rmtoll CTR2 TCEM LL_DMA_SetTransferEventMode
2239 * @param DMAx DMAx Instance
2240 * @param Channel This parameter can be one of the following values:
2241 * @arg @ref LL_DMA_CHANNEL_0
2242 * @arg @ref LL_DMA_CHANNEL_1
2243 * @arg @ref LL_DMA_CHANNEL_2
2244 * @arg @ref LL_DMA_CHANNEL_3
2245 * @arg @ref LL_DMA_CHANNEL_4
2246 * @arg @ref LL_DMA_CHANNEL_5
2247 * @arg @ref LL_DMA_CHANNEL_6
2248 * @arg @ref LL_DMA_CHANNEL_7
2249 * @param TransferEventMode This parameter can be one of the following values:
2250 * @arg @ref LL_DMA_TCEM_BLK_TRANSFER
2251 * @arg @ref LL_DMA_TCEM_RPT_BLK_TRANSFER
2252 * @arg @ref LL_DMA_TCEM_EACH_LLITEM_TRANSFER
2253 * @arg @ref LL_DMA_TCEM_LAST_LLITEM_TRANSFER
2254 * @retval None.
2255 */
LL_DMA_SetTransferEventMode(const DMA_TypeDef * DMAx,uint32_t Channel,uint32_t TransferEventMode)2256 __STATIC_INLINE void LL_DMA_SetTransferEventMode(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t TransferEventMode)
2257 {
2258 uint32_t dma_base_addr = (uint32_t)DMAx;
2259 MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR2, DMA_CTR2_TCEM,
2260 TransferEventMode);
2261 }
2262
2263 /**
2264 * @brief Get transfer event mode.
2265 * @note This API is used for all available DMA channels.
2266 * @rmtoll CTR2 TCEM LL_DMA_GetTransferEventMode
2267 * @param DMAx DMAx Instance
2268 * @param Channel This parameter can be one of the following values:
2269 * @arg @ref LL_DMA_CHANNEL_0
2270 * @arg @ref LL_DMA_CHANNEL_1
2271 * @arg @ref LL_DMA_CHANNEL_2
2272 * @arg @ref LL_DMA_CHANNEL_3
2273 * @arg @ref LL_DMA_CHANNEL_4
2274 * @arg @ref LL_DMA_CHANNEL_5
2275 * @arg @ref LL_DMA_CHANNEL_6
2276 * @arg @ref LL_DMA_CHANNEL_7
2277 * @retval Returned value can be one of the following values:
2278 * @arg @ref LL_DMA_TCEM_BLK_TRANSFER
2279 * @arg @ref LL_DMA_TCEM_RPT_BLK_TRANSFER
2280 * @arg @ref LL_DMA_TCEM_EACH_LLITEM_TRANSFER
2281 * @arg @ref LL_DMA_TCEM_LAST_LLITEM_TRANSFER
2282 */
LL_DMA_GetTransferEventMode(const DMA_TypeDef * DMAx,uint32_t Channel)2283 __STATIC_INLINE uint32_t LL_DMA_GetTransferEventMode(const DMA_TypeDef *DMAx, uint32_t Channel)
2284 {
2285 uint32_t dma_base_addr = (uint32_t)DMAx;
2286 return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR2, DMA_CTR2_TCEM));
2287 }
2288
2289 /**
2290 * @brief Set trigger polarity.
2291 * @note This API is used for all available DMA channels.
2292 * @rmtoll CTR2 TRIGPOL LL_DMA_SetTriggerPolarity
2293 * @param DMAx DMAx Instance
2294 * @param Channel This parameter can be one of the following values:
2295 * @arg @ref LL_DMA_CHANNEL_0
2296 * @arg @ref LL_DMA_CHANNEL_1
2297 * @arg @ref LL_DMA_CHANNEL_2
2298 * @arg @ref LL_DMA_CHANNEL_3
2299 * @arg @ref LL_DMA_CHANNEL_4
2300 * @arg @ref LL_DMA_CHANNEL_5
2301 * @arg @ref LL_DMA_CHANNEL_6
2302 * @arg @ref LL_DMA_CHANNEL_7
2303 * @param TriggerPolarity This parameter can be one of the following values:
2304 * @arg @ref LL_DMA_TRIG_POLARITY_MASKED
2305 * @arg @ref LL_DMA_TRIG_POLARITY_RISING
2306 * @arg @ref LL_DMA_TRIG_POLARITY_FALLING
2307 * @retval None.
2308 */
LL_DMA_SetTriggerPolarity(const DMA_TypeDef * DMAx,uint32_t Channel,uint32_t TriggerPolarity)2309 __STATIC_INLINE void LL_DMA_SetTriggerPolarity(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t TriggerPolarity)
2310 {
2311 uint32_t dma_base_addr = (uint32_t)DMAx;
2312 MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR2, DMA_CTR2_TRIGPOL,
2313 TriggerPolarity);
2314 }
2315
2316 /**
2317 * @brief Get trigger polarity.
2318 * @note This API is used for all available DMA channels.
2319 * @rmtoll CTR2 TRIGPOL LL_DMA_GetTriggerPolarity
2320 * @param DMAx DMAx Instance
2321 * @param Channel This parameter can be one of the following values:
2322 * @arg @ref LL_DMA_CHANNEL_0
2323 * @arg @ref LL_DMA_CHANNEL_1
2324 * @arg @ref LL_DMA_CHANNEL_2
2325 * @arg @ref LL_DMA_CHANNEL_3
2326 * @arg @ref LL_DMA_CHANNEL_4
2327 * @arg @ref LL_DMA_CHANNEL_5
2328 * @arg @ref LL_DMA_CHANNEL_6
2329 * @arg @ref LL_DMA_CHANNEL_7
2330 * @retval Returned value can be one of the following values:
2331 * @arg @ref LL_DMA_TRIG_POLARITY_MASKED
2332 * @arg @ref LL_DMA_TRIG_POLARITY_RISING
2333 * @arg @ref LL_DMA_TRIG_POLARITY_FALLING
2334 */
LL_DMA_GetTriggerPolarity(const DMA_TypeDef * DMAx,uint32_t Channel)2335 __STATIC_INLINE uint32_t LL_DMA_GetTriggerPolarity(const DMA_TypeDef *DMAx, uint32_t Channel)
2336 {
2337 uint32_t dma_base_addr = (uint32_t)DMAx;
2338 return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR2, DMA_CTR2_TRIGPOL));
2339 }
2340
2341 /**
2342 * @brief Set trigger Mode.
2343 * @note This API is used for all available DMA channels.
2344 * @rmtoll CTR2 TRIGM LL_DMA_SetTriggerMode
2345 * @param DMAx DMAx Instance
2346 * @param Channel This parameter can be one of the following values:
2347 * @arg @ref LL_DMA_CHANNEL_0
2348 * @arg @ref LL_DMA_CHANNEL_1
2349 * @arg @ref LL_DMA_CHANNEL_2
2350 * @arg @ref LL_DMA_CHANNEL_3
2351 * @arg @ref LL_DMA_CHANNEL_4
2352 * @arg @ref LL_DMA_CHANNEL_5
2353 * @arg @ref LL_DMA_CHANNEL_6
2354 * @arg @ref LL_DMA_CHANNEL_7
2355 * @param TriggerMode This parameter can be one of the following values:
2356 * @arg @ref LL_DMA_TRIGM_BLK_TRANSFER
2357 * @arg @ref LL_DMA_TRIGM_LLI_LINK_TRANSFER
2358 * @arg @ref LL_DMA_TRIGM_SINGLBURST_TRANSFER
2359 * @retval None.
2360 */
LL_DMA_SetTriggerMode(const DMA_TypeDef * DMAx,uint32_t Channel,uint32_t TriggerMode)2361 __STATIC_INLINE void LL_DMA_SetTriggerMode(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t TriggerMode)
2362 {
2363 uint32_t dma_base_addr = (uint32_t)DMAx;
2364 MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR2, DMA_CTR2_TRIGM,
2365 TriggerMode);
2366 }
2367
2368 /**
2369 * @brief Get trigger Mode.
2370 * @note This API is used for all available DMA channels.
2371 * @rmtoll CTR2 TRIGM LL_DMA_GetTriggerMode
2372 * @param DMAx DMAx Instance
2373 * @param Channel This parameter can be one of the following values:
2374 * @arg @ref LL_DMA_CHANNEL_0
2375 * @arg @ref LL_DMA_CHANNEL_1
2376 * @arg @ref LL_DMA_CHANNEL_2
2377 * @arg @ref LL_DMA_CHANNEL_3
2378 * @arg @ref LL_DMA_CHANNEL_4
2379 * @arg @ref LL_DMA_CHANNEL_5
2380 * @arg @ref LL_DMA_CHANNEL_6
2381 * @arg @ref LL_DMA_CHANNEL_7
2382 * @retval Returned value can be one of the following values:
2383 * @arg @ref LL_DMA_TRIGM_BLK_TRANSFER
2384 * @arg @ref LL_DMA_TRIGM_LLI_LINK_TRANSFER
2385 * @arg @ref LL_DMA_TRIGM_SINGLBURST_TRANSFER
2386 */
LL_DMA_GetTriggerMode(const DMA_TypeDef * DMAx,uint32_t Channel)2387 __STATIC_INLINE uint32_t LL_DMA_GetTriggerMode(const DMA_TypeDef *DMAx, uint32_t Channel)
2388 {
2389 uint32_t dma_base_addr = (uint32_t)DMAx;
2390 return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR2, DMA_CTR2_TRIGM));
2391 }
2392
2393 /**
2394 * @brief Set destination hardware and software transfer request.
2395 * @note This API is used for all available DMA channels.
2396 * @rmtoll CTR2 DREQ LL_DMA_SetDataTransferDirection\n
2397 * @rmtoll CTR2 SWREQ LL_DMA_SetDataTransferDirection
2398 * @param DMAx DMAx Instance
2399 * @param Channel This parameter can be one of the following values:
2400 * @arg @ref LL_DMA_CHANNEL_0
2401 * @arg @ref LL_DMA_CHANNEL_1
2402 * @arg @ref LL_DMA_CHANNEL_2
2403 * @arg @ref LL_DMA_CHANNEL_3
2404 * @arg @ref LL_DMA_CHANNEL_4
2405 * @arg @ref LL_DMA_CHANNEL_5
2406 * @arg @ref LL_DMA_CHANNEL_6
2407 * @arg @ref LL_DMA_CHANNEL_7
2408 * @param Direction This parameter can be one of the following values:
2409 * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY
2410 * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH
2411 * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
2412 * @retval None.
2413 */
LL_DMA_SetDataTransferDirection(const DMA_TypeDef * DMAx,uint32_t Channel,uint32_t Direction)2414 __STATIC_INLINE void LL_DMA_SetDataTransferDirection(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Direction)
2415 {
2416 uint32_t dma_base_addr = (uint32_t)DMAx;
2417 MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR2,
2418 DMA_CTR2_DREQ | DMA_CTR2_SWREQ, Direction);
2419 }
2420
2421 /**
2422 * @brief Get destination hardware and software transfer request.
2423 * @note This API is used for all available DMA channels.
2424 * @rmtoll CTR2 DREQ LL_DMA_GetDataTransferDirection\n
2425 * @rmtoll CTR2 SWREQ LL_DMA_GetDataTransferDirection
2426 * @param DMAx DMAx Instance
2427 * @param Channel This parameter can be one of the following values:
2428 * @arg @ref LL_DMA_CHANNEL_0
2429 * @arg @ref LL_DMA_CHANNEL_1
2430 * @arg @ref LL_DMA_CHANNEL_2
2431 * @arg @ref LL_DMA_CHANNEL_3
2432 * @arg @ref LL_DMA_CHANNEL_4
2433 * @arg @ref LL_DMA_CHANNEL_5
2434 * @arg @ref LL_DMA_CHANNEL_6
2435 * @arg @ref LL_DMA_CHANNEL_7
2436 * @retval Returned value can be one of the following values:
2437 * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY
2438 * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH
2439 * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
2440 */
LL_DMA_GetDataTransferDirection(const DMA_TypeDef * DMAx,uint32_t Channel)2441 __STATIC_INLINE uint32_t LL_DMA_GetDataTransferDirection(const DMA_TypeDef *DMAx, uint32_t Channel)
2442 {
2443 uint32_t dma_base_addr = (uint32_t)DMAx;
2444 return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR2,
2445 DMA_CTR2_DREQ | DMA_CTR2_SWREQ));
2446 }
2447
2448 /**
2449 * @brief Set block hardware request.
2450 * @note This API is used for all available DMA channels.
2451 * @rmtoll CTR2 BREQ LL_DMA_SetBlkHWRequest\n
2452 * @param DMAx DMAx Instance
2453 * @param Channel This parameter can be one of the following values:
2454 * @arg @ref LL_DMA_CHANNEL_0
2455 * @arg @ref LL_DMA_CHANNEL_1
2456 * @arg @ref LL_DMA_CHANNEL_2
2457 * @arg @ref LL_DMA_CHANNEL_3
2458 * @arg @ref LL_DMA_CHANNEL_4
2459 * @arg @ref LL_DMA_CHANNEL_5
2460 * @arg @ref LL_DMA_CHANNEL_6
2461 * @arg @ref LL_DMA_CHANNEL_7
2462 * @param BlkHWRequest This parameter can be one of the following values:
2463 * @arg @ref LL_DMA_HWREQUEST_SINGLEBURST
2464 * @arg @ref LL_DMA_HWREQUEST_BLK
2465 * @retval None.
2466 */
LL_DMA_SetBlkHWRequest(const DMA_TypeDef * DMAx,uint32_t Channel,uint32_t BlkHWRequest)2467 __STATIC_INLINE void LL_DMA_SetBlkHWRequest(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t BlkHWRequest)
2468 {
2469 uint32_t dma_base_addr = (uint32_t)DMAx;
2470 MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR2, DMA_CTR2_BREQ,
2471 BlkHWRequest);
2472 }
2473
2474 /**
2475 * @brief Get block hardware request.
2476 * @note This API is used for all available DMA channels.
2477 * @rmtoll CTR2 BREQ LL_DMA_GetBlkHWRequest\n
2478 * @param DMAx DMAx Instance
2479 * @param Channel This parameter can be one of the following values:
2480 * @arg @ref LL_DMA_CHANNEL_0
2481 * @arg @ref LL_DMA_CHANNEL_1
2482 * @arg @ref LL_DMA_CHANNEL_2
2483 * @arg @ref LL_DMA_CHANNEL_3
2484 * @arg @ref LL_DMA_CHANNEL_4
2485 * @arg @ref LL_DMA_CHANNEL_5
2486 * @arg @ref LL_DMA_CHANNEL_6
2487 * @arg @ref LL_DMA_CHANNEL_7
2488 * @retval Returned value can be one of the following values:
2489 * @arg @ref LL_DMA_HWREQUEST_SINGLEBURST
2490 * @arg @ref LL_DMA_HWREQUEST_BLK
2491 */
LL_DMA_GetBlkHWRequest(const DMA_TypeDef * DMAx,uint32_t Channel)2492 __STATIC_INLINE uint32_t LL_DMA_GetBlkHWRequest(const DMA_TypeDef *DMAx, uint32_t Channel)
2493 {
2494 uint32_t dma_base_addr = (uint32_t)DMAx;
2495 return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR2, DMA_CTR2_BREQ));
2496 }
2497
2498 /**
2499 * @brief Set hardware request.
2500 * @note This API is used for all available DMA channels.
2501 * @rmtoll CTR2 REQSEL LL_DMA_SetPeriphRequest
2502 * @param DMAx DMAx Instance
2503 * @param Channel This parameter can be one of the following values:
2504 * @arg @ref LL_DMA_CHANNEL_0
2505 * @arg @ref LL_DMA_CHANNEL_1
2506 * @arg @ref LL_DMA_CHANNEL_2
2507 * @arg @ref LL_DMA_CHANNEL_3
2508 * @arg @ref LL_DMA_CHANNEL_4
2509 * @arg @ref LL_DMA_CHANNEL_5
2510 * @arg @ref LL_DMA_CHANNEL_6
2511 * @arg @ref LL_DMA_CHANNEL_7
2512 * @param Request This parameter can be one of the following values:
2513 * @arg @ref LL_GPDMA1_REQUEST_ADC4
2514 * @arg @ref LL_GPDMA1_REQUEST_SPI1_RX (*)
2515 * @arg @ref LL_GPDMA1_REQUEST_SPI1_TX (*)
2516 * @arg @ref LL_GPDMA1_REQUEST_SPI3_RX
2517 * @arg @ref LL_GPDMA1_REQUEST_SPI3_TX
2518 * @arg @ref LL_GPDMA1_REQUEST_I2C1_RX (*)
2519 * @arg @ref LL_GPDMA1_REQUEST_I2C1_TX (*)
2520 * @arg @ref LL_GPDMA1_REQUEST_I2C1_EVC (*)
2521 * @arg @ref LL_GPDMA1_REQUEST_I2C3_RX
2522 * @arg @ref LL_GPDMA1_REQUEST_I2C3_TX
2523 * @arg @ref LL_GPDMA1_REQUEST_I2C3_EVC
2524 * @arg @ref LL_GPDMA1_REQUEST_USART1_RX
2525 * @arg @ref LL_GPDMA1_REQUEST_USART1_TX
2526 * @arg @ref LL_GPDMA1_REQUEST_USART2_RX (*)
2527 * @arg @ref LL_GPDMA1_REQUEST_USART2_TX (*)
2528 * @arg @ref LL_GPDMA1_REQUEST_LPUART1_RX
2529 * @arg @ref LL_GPDMA1_REQUEST_LPUART1_TX
2530 * @arg @ref LL_GPDMA1_REQUEST_SAI1_A (*)
2531 * @arg @ref LL_GPDMA1_REQUEST_SAI1_B (*)
2532 * @arg @ref LL_GPDMA1_REQUEST_TIM1_CH1
2533 * @arg @ref LL_GPDMA1_REQUEST_TIM1_CH2
2534 * @arg @ref LL_GPDMA1_REQUEST_TIM1_CH3
2535 * @arg @ref LL_GPDMA1_REQUEST_TIM1_CH4
2536 * @arg @ref LL_GPDMA1_REQUEST_TIM1_UP
2537 * @arg @ref LL_GPDMA1_REQUEST_TIM1_TRIG
2538 * @arg @ref LL_GPDMA1_REQUEST_TIM1_COM
2539 * @arg @ref LL_GPDMA1_REQUEST_TIM2_CH1
2540 * @arg @ref LL_GPDMA1_REQUEST_TIM2_CH2
2541 * @arg @ref LL_GPDMA1_REQUEST_TIM2_CH3
2542 * @arg @ref LL_GPDMA1_REQUEST_TIM2_CH4
2543 * @arg @ref LL_GPDMA1_REQUEST_TIM2_UP
2544 * @arg @ref LL_GPDMA1_REQUEST_TIM3_CH1 (*)
2545 * @arg @ref LL_GPDMA1_REQUEST_TIM3_CH2 (*)
2546 * @arg @ref LL_GPDMA1_REQUEST_TIM3_CH3 (*)
2547 * @arg @ref LL_GPDMA1_REQUEST_TIM3_CH4 (*)
2548 * @arg @ref LL_GPDMA1_REQUEST_TIM3_UP (*)
2549 * @arg @ref LL_GPDMA1_REQUEST_TIM3_TRIG (*)
2550 * @arg @ref LL_GPDMA1_REQUEST_TIM16_CH1
2551 * @arg @ref LL_GPDMA1_REQUEST_TIM16_UP
2552 * @arg @ref LL_GPDMA1_REQUEST_TIM17_CH1 (*)
2553 * @arg @ref LL_GPDMA1_REQUEST_TIM17_UP (*)
2554 * @arg @ref LL_GPDMA1_REQUEST_AES_IN (*)
2555 * @arg @ref LL_GPDMA1_REQUEST_AES_OUT (*)
2556 * @arg @ref LL_GPDMA1_REQUEST_HASH_IN
2557 * @arg @ref LL_GPDMA1_REQUEST_SAES_IN (*)
2558 * @arg @ref LL_GPDMA1_REQUEST_SAES_OUT (*)
2559 * @arg @ref LL_GPDMA1_REQUEST_LPTIM1_IC1
2560 * @arg @ref LL_GPDMA1_REQUEST_LPTIM1_IC2
2561 * @arg @ref LL_GPDMA1_REQUEST_LPTIM1_UE
2562 * @arg @ref LL_GPDMA1_REQUEST_LPTIM2_IC1 (*)
2563 * @arg @ref LL_GPDMA1_REQUEST_LPTIM2_IC2 (*)
2564 * @arg @ref LL_GPDMA1_REQUEST_LPTIM2_UE (*)
2565 * @arg @ref LL_GPDMA1_REQUEST_SPI2_RX (*)
2566 * @arg @ref LL_GPDMA1_REQUEST_SPI2_TX (*)
2567 * @arg @ref LL_GPDMA1_REQUEST_I2C2_RX (*)
2568 * @arg @ref LL_GPDMA1_REQUEST_I2C2_TX (*)
2569 * @arg @ref LL_GPDMA1_REQUEST_I2C2_EVC (*)
2570 * @arg @ref LL_GPDMA1_REQUEST_I2C4_RX (*)
2571 * @arg @ref LL_GPDMA1_REQUEST_I2C4_TX (*)
2572 * @arg @ref LL_GPDMA1_REQUEST_I2C4_EVC (*)
2573 * @arg @ref LL_GPDMA1_REQUEST_TIM4_CH1 (*)
2574 * @arg @ref LL_GPDMA1_REQUEST_TIM4_CH2 (*)
2575 * @arg @ref LL_GPDMA1_REQUEST_TIM4_CH3 (*)
2576 * @arg @ref LL_GPDMA1_REQUEST_TIM4_CH4 (*)
2577 * @arg @ref LL_GPDMA1_REQUEST_TIM4_UP (*)
2578 * @arg @ref LL_GPDMA1_REQUEST_USART3_RX (*)
2579 * @arg @ref LL_GPDMA1_REQUEST_USART3_TX (*)
2580 * @note (*) Availability depends on devices.
2581 * @retval None.
2582 */
LL_DMA_SetPeriphRequest(const DMA_TypeDef * DMAx,uint32_t Channel,uint32_t Request)2583 __STATIC_INLINE void LL_DMA_SetPeriphRequest(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Request)
2584 {
2585 uint32_t dma_base_addr = (uint32_t)DMAx;
2586 MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR2, DMA_CTR2_REQSEL, Request);
2587 }
2588
2589 /**
2590 * @brief Get hardware request.
2591 * @note This API is used for all available DMA channels.
2592 * @rmtoll CTR2 REQSEL LL_DMA_GetPeriphRequest
2593 * @param DMAx DMAx Instance
2594 * @param Channel This parameter can be one of the following values:
2595 * @arg @ref LL_DMA_CHANNEL_0
2596 * @arg @ref LL_DMA_CHANNEL_1
2597 * @arg @ref LL_DMA_CHANNEL_2
2598 * @arg @ref LL_DMA_CHANNEL_3
2599 * @arg @ref LL_DMA_CHANNEL_4
2600 * @arg @ref LL_DMA_CHANNEL_5
2601 * @arg @ref LL_DMA_CHANNEL_6
2602 * @arg @ref LL_DMA_CHANNEL_7
2603 * @retval Returned value can be one of the following values:
2604 * @arg @ref LL_GPDMA1_REQUEST_ADC4
2605 * @arg @ref LL_GPDMA1_REQUEST_SPI1_RX (*)
2606 * @arg @ref LL_GPDMA1_REQUEST_SPI1_TX (*)
2607 * @arg @ref LL_GPDMA1_REQUEST_SPI3_RX
2608 * @arg @ref LL_GPDMA1_REQUEST_SPI3_TX
2609 * @arg @ref LL_GPDMA1_REQUEST_I2C1_RX (*)
2610 * @arg @ref LL_GPDMA1_REQUEST_I2C1_TX (*)
2611 * @arg @ref LL_GPDMA1_REQUEST_I2C1_EVC (*)
2612 * @arg @ref LL_GPDMA1_REQUEST_I2C3_RX
2613 * @arg @ref LL_GPDMA1_REQUEST_I2C3_TX
2614 * @arg @ref LL_GPDMA1_REQUEST_I2C3_EVC
2615 * @arg @ref LL_GPDMA1_REQUEST_USART1_RX
2616 * @arg @ref LL_GPDMA1_REQUEST_USART1_TX
2617 * @arg @ref LL_GPDMA1_REQUEST_USART2_RX (*)
2618 * @arg @ref LL_GPDMA1_REQUEST_USART2_TX (*)
2619 * @arg @ref LL_GPDMA1_REQUEST_LPUART1_RX
2620 * @arg @ref LL_GPDMA1_REQUEST_LPUART1_TX
2621 * @arg @ref LL_GPDMA1_REQUEST_SAI1_A (*)
2622 * @arg @ref LL_GPDMA1_REQUEST_SAI1_B (*)
2623 * @arg @ref LL_GPDMA1_REQUEST_TIM1_CH1
2624 * @arg @ref LL_GPDMA1_REQUEST_TIM1_CH2
2625 * @arg @ref LL_GPDMA1_REQUEST_TIM1_CH3
2626 * @arg @ref LL_GPDMA1_REQUEST_TIM1_CH4
2627 * @arg @ref LL_GPDMA1_REQUEST_TIM1_UP
2628 * @arg @ref LL_GPDMA1_REQUEST_TIM1_TRIG
2629 * @arg @ref LL_GPDMA1_REQUEST_TIM1_COM
2630 * @arg @ref LL_GPDMA1_REQUEST_TIM2_CH1
2631 * @arg @ref LL_GPDMA1_REQUEST_TIM2_CH2
2632 * @arg @ref LL_GPDMA1_REQUEST_TIM2_CH3
2633 * @arg @ref LL_GPDMA1_REQUEST_TIM2_CH4
2634 * @arg @ref LL_GPDMA1_REQUEST_TIM2_UP
2635 * @arg @ref LL_GPDMA1_REQUEST_TIM3_CH1 (*)
2636 * @arg @ref LL_GPDMA1_REQUEST_TIM3_CH2 (*)
2637 * @arg @ref LL_GPDMA1_REQUEST_TIM3_CH3 (*)
2638 * @arg @ref LL_GPDMA1_REQUEST_TIM3_CH4 (*)
2639 * @arg @ref LL_GPDMA1_REQUEST_TIM3_UP (*)
2640 * @arg @ref LL_GPDMA1_REQUEST_TIM3_TRIG (*)
2641 * @arg @ref LL_GPDMA1_REQUEST_TIM16_CH1
2642 * @arg @ref LL_GPDMA1_REQUEST_TIM16_UP
2643 * @arg @ref LL_GPDMA1_REQUEST_TIM17_CH1 (*)
2644 * @arg @ref LL_GPDMA1_REQUEST_TIM17_UP (*)
2645 * @arg @ref LL_GPDMA1_REQUEST_AES_IN (*)
2646 * @arg @ref LL_GPDMA1_REQUEST_AES_OUT (*)
2647 * @arg @ref LL_GPDMA1_REQUEST_HASH_IN
2648 * @arg @ref LL_GPDMA1_REQUEST_SAES_IN (*)
2649 * @arg @ref LL_GPDMA1_REQUEST_SAES_OUT (*)
2650 * @arg @ref LL_GPDMA1_REQUEST_LPTIM1_IC1
2651 * @arg @ref LL_GPDMA1_REQUEST_LPTIM1_IC2
2652 * @arg @ref LL_GPDMA1_REQUEST_LPTIM1_UE
2653 * @arg @ref LL_GPDMA1_REQUEST_LPTIM2_IC1 (*)
2654 * @arg @ref LL_GPDMA1_REQUEST_LPTIM2_IC2 (*)
2655 * @arg @ref LL_GPDMA1_REQUEST_LPTIM2_UE (*)
2656 * @arg @ref LL_GPDMA1_REQUEST_SPI2_RX (*)
2657 * @arg @ref LL_GPDMA1_REQUEST_SPI2_TX (*)
2658 * @arg @ref LL_GPDMA1_REQUEST_I2C2_RX (*)
2659 * @arg @ref LL_GPDMA1_REQUEST_I2C2_TX (*)
2660 * @arg @ref LL_GPDMA1_REQUEST_I2C2_EVC (*)
2661 * @arg @ref LL_GPDMA1_REQUEST_I2C4_RX (*)
2662 * @arg @ref LL_GPDMA1_REQUEST_I2C4_TX (*)
2663 * @arg @ref LL_GPDMA1_REQUEST_I2C4_EVC (*)
2664 * @arg @ref LL_GPDMA1_REQUEST_TIM4_CH1 (*)
2665 * @arg @ref LL_GPDMA1_REQUEST_TIM4_CH2 (*)
2666 * @arg @ref LL_GPDMA1_REQUEST_TIM4_CH3 (*)
2667 * @arg @ref LL_GPDMA1_REQUEST_TIM4_CH4 (*)
2668 * @arg @ref LL_GPDMA1_REQUEST_TIM4_UP (*)
2669 * @arg @ref LL_GPDMA1_REQUEST_USART3_RX (*)
2670 * @arg @ref LL_GPDMA1_REQUEST_USART3_TX (*)
2671 * @note (*) Availability depends on devices.
2672 */
LL_DMA_GetPeriphRequest(const DMA_TypeDef * DMAx,uint32_t Channel)2673 __STATIC_INLINE uint32_t LL_DMA_GetPeriphRequest(const DMA_TypeDef *DMAx, uint32_t Channel)
2674 {
2675 uint32_t dma_base_addr = (uint32_t)DMAx;
2676 return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR2, DMA_CTR2_REQSEL));
2677 }
2678
2679 /**
2680 * @brief Set hardware trigger.
2681 * @note This API is used for all available DMA channels.
2682 * @rmtoll CTR2 TRIGSEL LL_DMA_SetHWTrigger
2683 * @param DMAx DMAx Instance
2684 * @param Channel This parameter can be one of the following values:
2685 * @arg @ref LL_DMA_CHANNEL_0
2686 * @arg @ref LL_DMA_CHANNEL_1
2687 * @arg @ref LL_DMA_CHANNEL_2
2688 * @arg @ref LL_DMA_CHANNEL_3
2689 * @arg @ref LL_DMA_CHANNEL_4
2690 * @arg @ref LL_DMA_CHANNEL_5
2691 * @arg @ref LL_DMA_CHANNEL_6
2692 * @arg @ref LL_DMA_CHANNEL_7
2693 * @param Trigger This parameter can be one of the following values:
2694 * @arg @ref LL_GPDMA1_TRIGGER_EXTI_LINE0
2695 * @arg @ref LL_GPDMA1_TRIGGER_EXTI_LINE1
2696 * @arg @ref LL_GPDMA1_TRIGGER_EXTI_LINE2
2697 * @arg @ref LL_GPDMA1_TRIGGER_EXTI_LINE3
2698 * @arg @ref LL_GPDMA1_TRIGGER_EXTI_LINE4
2699 * @arg @ref LL_GPDMA1_TRIGGER_EXTI_LINE5
2700 * @arg @ref LL_GPDMA1_TRIGGER_EXTI_LINE6
2701 * @arg @ref LL_GPDMA1_TRIGGER_EXTI_LINE7
2702 * @arg @ref LL_GPDMA1_TRIGGER_TAMP_TRG1
2703 * @arg @ref LL_GPDMA1_TRIGGER_TAMP_TRG2
2704 * @arg @ref LL_GPDMA1_TRIGGER_TAMP_TRG3
2705 * @arg @ref LL_GPDMA1_TRIGGER_LPTIM1_CH1
2706 * @arg @ref LL_GPDMA1_TRIGGER_LPTIM1_CH2
2707 * @arg @ref LL_GPDMA1_TRIGGER_LPTIM2_CH1 (*)
2708 * @arg @ref LL_GPDMA1_TRIGGER_LPTIM2_CH2 (*)
2709 * @arg @ref LL_GPDMA1_TRIGGER_COMP1_OUT (*)
2710 * @arg @ref LL_GPDMA1_TRIGGER_COMP2_OUT (*)
2711 * @arg @ref LL_GPDMA1_TRIGGER_RTC_ALRA_TRG
2712 * @arg @ref LL_GPDMA1_TRIGGER_RTC_ALRB_TRG
2713 * @arg @ref LL_GPDMA1_TRIGGER_RTC_WUT_TRG
2714 * @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH0_TCF
2715 * @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH1_TCF
2716 * @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH2_TCF
2717 * @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH3_TCF
2718 * @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH4_TCF
2719 * @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH5_TCF
2720 * @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH6_TCF
2721 * @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH7_TCF
2722 * @arg @ref LL_GPDMA1_TRIGGER_TIM2_TRGO
2723 * @arg @ref LL_GPDMA1_TRIGGER_ADC4_AWD1
2724 * @arg @ref LL_GPDMA1_TRIGGER_TIM3_TRGO (*)
2725 * @retval None.
2726 */
LL_DMA_SetHWTrigger(const DMA_TypeDef * DMAx,uint32_t Channel,uint32_t Trigger)2727 __STATIC_INLINE void LL_DMA_SetHWTrigger(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Trigger)
2728 {
2729 uint32_t dma_base_addr = (uint32_t)DMAx;
2730 MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR2, DMA_CTR2_TRIGSEL,
2731 (Trigger << DMA_CTR2_TRIGSEL_Pos) & DMA_CTR2_TRIGSEL);
2732 }
2733
2734 /**
2735 * @brief Get hardware triggers.
2736 * @note This API is used for all available DMA channels.
2737 * @rmtoll CTR2 TRIGSEL LL_DMA_GetHWTrigger
2738 * @param DMAx DMAx Instance
2739 * @param Channel This parameter can be one of the following values:
2740 * @arg @ref LL_DMA_CHANNEL_0
2741 * @arg @ref LL_DMA_CHANNEL_1
2742 * @arg @ref LL_DMA_CHANNEL_2
2743 * @arg @ref LL_DMA_CHANNEL_3
2744 * @arg @ref LL_DMA_CHANNEL_4
2745 * @arg @ref LL_DMA_CHANNEL_5
2746 * @arg @ref LL_DMA_CHANNEL_6
2747 * @arg @ref LL_DMA_CHANNEL_7
2748 * @retval Returned value can be one of the following values:
2749 * @arg @ref LL_GPDMA1_TRIGGER_EXTI_LINE0
2750 * @arg @ref LL_GPDMA1_TRIGGER_EXTI_LINE1
2751 * @arg @ref LL_GPDMA1_TRIGGER_EXTI_LINE2
2752 * @arg @ref LL_GPDMA1_TRIGGER_EXTI_LINE3
2753 * @arg @ref LL_GPDMA1_TRIGGER_EXTI_LINE4
2754 * @arg @ref LL_GPDMA1_TRIGGER_EXTI_LINE5
2755 * @arg @ref LL_GPDMA1_TRIGGER_EXTI_LINE6
2756 * @arg @ref LL_GPDMA1_TRIGGER_EXTI_LINE7
2757 * @arg @ref LL_GPDMA1_TRIGGER_TAMP_TRG1
2758 * @arg @ref LL_GPDMA1_TRIGGER_TAMP_TRG2
2759 * @arg @ref LL_GPDMA1_TRIGGER_TAMP_TRG3
2760 * @arg @ref LL_GPDMA1_TRIGGER_LPTIM1_CH1
2761 * @arg @ref LL_GPDMA1_TRIGGER_LPTIM1_CH2
2762 * @arg @ref LL_GPDMA1_TRIGGER_LPTIM2_CH1 (*)
2763 * @arg @ref LL_GPDMA1_TRIGGER_LPTIM2_CH2 (*)
2764 * @arg @ref LL_GPDMA1_TRIGGER_COMP1_OUT (*)
2765 * @arg @ref LL_GPDMA1_TRIGGER_COMP2_OUT (*)
2766 * @arg @ref LL_GPDMA1_TRIGGER_RTC_ALRA_TRG
2767 * @arg @ref LL_GPDMA1_TRIGGER_RTC_ALRB_TRG
2768 * @arg @ref LL_GPDMA1_TRIGGER_RTC_WUT_TRG
2769 * @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH0_TCF
2770 * @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH1_TCF
2771 * @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH2_TCF
2772 * @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH3_TCF
2773 * @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH4_TCF
2774 * @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH5_TCF
2775 * @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH6_TCF
2776 * @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH7_TCF
2777 * @arg @ref LL_GPDMA1_TRIGGER_TIM2_TRGO
2778 * @arg @ref LL_GPDMA1_TRIGGER_ADC4_AWD1
2779 * @arg @ref LL_GPDMA1_TRIGGER_TIM3_TRGO (*)
2780 */
LL_DMA_GetHWTrigger(const DMA_TypeDef * DMAx,uint32_t Channel)2781 __STATIC_INLINE uint32_t LL_DMA_GetHWTrigger(const DMA_TypeDef *DMAx, uint32_t Channel)
2782 {
2783 uint32_t dma_base_addr = (uint32_t)DMAx;
2784 return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR2,
2785 DMA_CTR2_TRIGSEL) >> DMA_CTR2_TRIGSEL_Pos);
2786 }
2787
2788 /**
2789 * @brief Set block data length in bytes to transfer.
2790 * @note This API is used for all available DMA channels.
2791 * @rmtoll CBR1 BNDT LL_DMA_SetBlkDataLength
2792 * @param DMAx DMAx Instance
2793 * @param Channel This parameter can be one of the following values:
2794 * @arg @ref LL_DMA_CHANNEL_0
2795 * @arg @ref LL_DMA_CHANNEL_1
2796 * @arg @ref LL_DMA_CHANNEL_2
2797 * @arg @ref LL_DMA_CHANNEL_3
2798 * @arg @ref LL_DMA_CHANNEL_4
2799 * @arg @ref LL_DMA_CHANNEL_5
2800 * @arg @ref LL_DMA_CHANNEL_6
2801 * @arg @ref LL_DMA_CHANNEL_7
2802 * @param BlkDataLength Between 0 to 0x0000FFFF
2803 * @retval None.
2804 */
LL_DMA_SetBlkDataLength(const DMA_TypeDef * DMAx,uint32_t Channel,uint32_t BlkDataLength)2805 __STATIC_INLINE void LL_DMA_SetBlkDataLength(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t BlkDataLength)
2806 {
2807 uint32_t dma_base_addr = (uint32_t)DMAx;
2808 MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CBR1, DMA_CBR1_BNDT,
2809 BlkDataLength);
2810 }
2811
2812 /**
2813 * @brief Get block data length in bytes to transfer.
2814 * @note This API is used for all available DMA channels.
2815 * @rmtoll CBR1 BNDT LL_DMA_GetBlkDataLength
2816 * @param DMAx DMAx Instance
2817 * @param Channel This parameter can be one of the following values:
2818 * @arg @ref LL_DMA_CHANNEL_0
2819 * @arg @ref LL_DMA_CHANNEL_1
2820 * @arg @ref LL_DMA_CHANNEL_2
2821 * @arg @ref LL_DMA_CHANNEL_3
2822 * @arg @ref LL_DMA_CHANNEL_4
2823 * @arg @ref LL_DMA_CHANNEL_5
2824 * @arg @ref LL_DMA_CHANNEL_6
2825 * @arg @ref LL_DMA_CHANNEL_7
2826 * @retval Between 0 to 0x0000FFFF
2827 */
LL_DMA_GetBlkDataLength(const DMA_TypeDef * DMAx,uint32_t Channel)2828 __STATIC_INLINE uint32_t LL_DMA_GetBlkDataLength(const DMA_TypeDef *DMAx, uint32_t Channel)
2829 {
2830 uint32_t dma_base_addr = (uint32_t)DMAx;
2831 return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CBR1, DMA_CBR1_BNDT));
2832 }
2833
2834 /**
2835 * @brief Configure the source and destination addresses.
2836 * @note This API is used for all available DMA channels.
2837 * @note This API must not be called when the DMA Channel is enabled.
2838 * @rmtoll CSAR SA LL_DMA_ConfigAddresses\n
2839 * CDAR DA LL_DMA_ConfigAddresses
2840 * @param DMAx DMAx Instance
2841 * @param Channel This parameter can be one of the following values:
2842 * @arg @ref LL_DMA_CHANNEL_0
2843 * @arg @ref LL_DMA_CHANNEL_1
2844 * @arg @ref LL_DMA_CHANNEL_2
2845 * @arg @ref LL_DMA_CHANNEL_3
2846 * @arg @ref LL_DMA_CHANNEL_4
2847 * @arg @ref LL_DMA_CHANNEL_5
2848 * @arg @ref LL_DMA_CHANNEL_6
2849 * @arg @ref LL_DMA_CHANNEL_7
2850 * @param SrcAddress Between 0 to 0xFFFFFFFF
2851 * @param DestAddress Between 0 to 0xFFFFFFFF
2852 * @retval None.
2853 */
LL_DMA_ConfigAddresses(const DMA_TypeDef * DMAx,uint32_t Channel,uint32_t SrcAddress,uint32_t DestAddress)2854 __STATIC_INLINE void LL_DMA_ConfigAddresses(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t SrcAddress, uint32_t
2855 DestAddress)
2856 {
2857 uint32_t dma_base_addr = (uint32_t)DMAx;
2858 WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CSAR, SrcAddress);
2859 WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CDAR, DestAddress);
2860 }
2861
2862 /**
2863 * @brief Set source address.
2864 * @note This API is used for all available DMA channels.
2865 * @rmtoll CSAR SA LL_DMA_SetSrcAddress
2866 * @param DMAx DMAx Instance
2867 * @param Channel This parameter can be one of the following values:
2868 * @arg @ref LL_DMA_CHANNEL_0
2869 * @arg @ref LL_DMA_CHANNEL_1
2870 * @arg @ref LL_DMA_CHANNEL_2
2871 * @arg @ref LL_DMA_CHANNEL_3
2872 * @arg @ref LL_DMA_CHANNEL_4
2873 * @arg @ref LL_DMA_CHANNEL_5
2874 * @arg @ref LL_DMA_CHANNEL_6
2875 * @arg @ref LL_DMA_CHANNEL_7
2876 * @param SrcAddress Between 0 to 0xFFFFFFFF
2877 * @retval None.
2878 */
LL_DMA_SetSrcAddress(const DMA_TypeDef * DMAx,uint32_t Channel,uint32_t SrcAddress)2879 __STATIC_INLINE void LL_DMA_SetSrcAddress(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t SrcAddress)
2880 {
2881 uint32_t dma_base_addr = (uint32_t)DMAx;
2882 WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CSAR, SrcAddress);
2883 }
2884
2885 /**
2886 * @brief Get source address.
2887 * @note This API is used for all available DMA channels.
2888 * @rmtoll CSAR SA LL_DMA_GetSrcAddress
2889 * @param DMAx DMAx Instance
2890 * @param Channel This parameter can be one of the following values:
2891 * @arg @ref LL_DMA_CHANNEL_0
2892 * @arg @ref LL_DMA_CHANNEL_1
2893 * @arg @ref LL_DMA_CHANNEL_2
2894 * @arg @ref LL_DMA_CHANNEL_3
2895 * @arg @ref LL_DMA_CHANNEL_4
2896 * @arg @ref LL_DMA_CHANNEL_5
2897 * @arg @ref LL_DMA_CHANNEL_6
2898 * @arg @ref LL_DMA_CHANNEL_7
2899 * @retval Between 0 to 0xFFFFFFFF
2900 */
LL_DMA_GetSrcAddress(const DMA_TypeDef * DMAx,uint32_t Channel)2901 __STATIC_INLINE uint32_t LL_DMA_GetSrcAddress(const DMA_TypeDef *DMAx, uint32_t Channel)
2902 {
2903 uint32_t dma_base_addr = (uint32_t)DMAx;
2904 return (READ_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CSAR));
2905 }
2906
2907 /**
2908 * @brief Set destination address.
2909 * @note This API is used for all available DMA channels.
2910 * @rmtoll CDAR DA LL_DMA_SetDestAddress
2911 * @param DMAx DMAx Instance
2912 * @param Channel This parameter can be one of the following values:
2913 * @arg @ref LL_DMA_CHANNEL_0
2914 * @arg @ref LL_DMA_CHANNEL_1
2915 * @arg @ref LL_DMA_CHANNEL_2
2916 * @arg @ref LL_DMA_CHANNEL_3
2917 * @arg @ref LL_DMA_CHANNEL_4
2918 * @arg @ref LL_DMA_CHANNEL_5
2919 * @arg @ref LL_DMA_CHANNEL_6
2920 * @arg @ref LL_DMA_CHANNEL_7
2921 * @param DestAddress Between 0 to 0xFFFFFFFF
2922 * @retval None.
2923 */
LL_DMA_SetDestAddress(const DMA_TypeDef * DMAx,uint32_t Channel,uint32_t DestAddress)2924 __STATIC_INLINE void LL_DMA_SetDestAddress(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t DestAddress)
2925 {
2926 uint32_t dma_base_addr = (uint32_t)DMAx;
2927 WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CDAR, DestAddress);
2928 }
2929
2930 /**
2931 * @brief Get destination address.
2932 * @note This API is used for all available DMA channels.
2933 * @rmtoll CDAR DA LL_DMA_GetDestAddress
2934 * @param DMAx DMAx Instance
2935 * @param Channel This parameter can be one of the following values:
2936 * @arg @ref LL_DMA_CHANNEL_0
2937 * @arg @ref LL_DMA_CHANNEL_1
2938 * @arg @ref LL_DMA_CHANNEL_2
2939 * @arg @ref LL_DMA_CHANNEL_3
2940 * @arg @ref LL_DMA_CHANNEL_4
2941 * @arg @ref LL_DMA_CHANNEL_5
2942 * @arg @ref LL_DMA_CHANNEL_6
2943 * @arg @ref LL_DMA_CHANNEL_7
2944 * @retval Between 0 to 0xFFFFFFFF
2945 */
LL_DMA_GetDestAddress(const DMA_TypeDef * DMAx,uint32_t Channel)2946 __STATIC_INLINE uint32_t LL_DMA_GetDestAddress(const DMA_TypeDef *DMAx, uint32_t Channel)
2947 {
2948 uint32_t dma_base_addr = (uint32_t)DMAx;
2949 return (READ_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CDAR));
2950 }
2951
2952
2953 /**
2954 * @brief Configure registers update and node address offset during the link transfer.
2955 * @note This API is used for all available DMA channels.
2956 * @rmtoll CLLR UT1 LL_DMA_ConfigLinkUpdate\n
2957 * @rmtoll CLLR UT2 LL_DMA_ConfigLinkUpdate\n
2958 * @rmtoll CLLR UB1 LL_DMA_ConfigLinkUpdate\n
2959 * @rmtoll CLLR USA LL_DMA_ConfigLinkUpdate\n
2960 * @rmtoll CLLR UDA LL_DMA_ConfigLinkUpdate\n
2961 * @rmtoll CLLR ULL LL_DMA_ConfigLinkUpdate
2962 * @param DMAx DMAx Instance
2963 * @param Channel This parameter can be one of the following values:
2964 * @arg @ref LL_DMA_CHANNEL_0
2965 * @arg @ref LL_DMA_CHANNEL_1
2966 * @arg @ref LL_DMA_CHANNEL_2
2967 * @arg @ref LL_DMA_CHANNEL_3
2968 * @arg @ref LL_DMA_CHANNEL_4
2969 * @arg @ref LL_DMA_CHANNEL_5
2970 * @arg @ref LL_DMA_CHANNEL_6
2971 * @arg @ref LL_DMA_CHANNEL_7
2972 * @param RegistersUpdate This parameter must be a combination of all the following values:
2973 * @arg @ref LL_DMA_UPDATE_CTR1
2974 * @arg @ref LL_DMA_UPDATE_CTR2
2975 * @arg @ref LL_DMA_UPDATE_CBR1
2976 * @arg @ref LL_DMA_UPDATE_CSAR
2977 * @arg @ref LL_DMA_UPDATE_CDAR
2978 * @arg @ref LL_DMA_UPDATE_CLLR
2979 * @param LinkedListAddrOffset Between 0 to 0x0000FFFC by increment of 4 (4 Bytes)
2980 * @retval None.
2981 */
LL_DMA_ConfigLinkUpdate(const DMA_TypeDef * DMAx,uint32_t Channel,uint32_t RegistersUpdate,uint32_t LinkedListAddrOffset)2982 __STATIC_INLINE void LL_DMA_ConfigLinkUpdate(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t RegistersUpdate,
2983 uint32_t LinkedListAddrOffset)
2984 {
2985 uint32_t dma_base_addr = (uint32_t)DMAx;
2986 MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR,
2987 (DMA_CLLR_UT1 | DMA_CLLR_UT2 | DMA_CLLR_UB1 | DMA_CLLR_USA | DMA_CLLR_UDA | \
2988 DMA_CLLR_ULL | DMA_CLLR_LA), (RegistersUpdate | (LinkedListAddrOffset & DMA_CLLR_LA)));
2989 }
2990
2991 /**
2992 * @brief Enable CTR1 update during the link transfer.
2993 * @note This API is used for all available DMA channels.
2994 * @rmtoll CLLR UT1 LL_DMA_EnableCTR1Update
2995 * @param DMAx DMAx Instance
2996 * @param Channel This parameter can be one of the following values:
2997 * @arg @ref LL_DMA_CHANNEL_0
2998 * @arg @ref LL_DMA_CHANNEL_1
2999 * @arg @ref LL_DMA_CHANNEL_2
3000 * @arg @ref LL_DMA_CHANNEL_3
3001 * @arg @ref LL_DMA_CHANNEL_4
3002 * @arg @ref LL_DMA_CHANNEL_5
3003 * @arg @ref LL_DMA_CHANNEL_6
3004 * @arg @ref LL_DMA_CHANNEL_7
3005 * @retval None.
3006 */
LL_DMA_EnableCTR1Update(const DMA_TypeDef * DMAx,uint32_t Channel)3007 __STATIC_INLINE void LL_DMA_EnableCTR1Update(const DMA_TypeDef *DMAx, uint32_t Channel)
3008 {
3009 uint32_t dma_base_addr = (uint32_t)DMAx;
3010 SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_UT1);
3011 }
3012
3013 /**
3014 * @brief Disable CTR1 update during the link transfer.
3015 * @note This API is used for all available DMA channels.
3016 * @rmtoll CLLR UT1 LL_DMA_DisableCTR1Update
3017 * @param DMAx DMAx Instance
3018 * @param Channel This parameter can be one of the following values:
3019 * @arg @ref LL_DMA_CHANNEL_0
3020 * @arg @ref LL_DMA_CHANNEL_1
3021 * @arg @ref LL_DMA_CHANNEL_2
3022 * @arg @ref LL_DMA_CHANNEL_3
3023 * @arg @ref LL_DMA_CHANNEL_4
3024 * @arg @ref LL_DMA_CHANNEL_5
3025 * @arg @ref LL_DMA_CHANNEL_6
3026 * @arg @ref LL_DMA_CHANNEL_7
3027 * @retval None.
3028 */
LL_DMA_DisableCTR1Update(const DMA_TypeDef * DMAx,uint32_t Channel)3029 __STATIC_INLINE void LL_DMA_DisableCTR1Update(const DMA_TypeDef *DMAx, uint32_t Channel)
3030 {
3031 uint32_t dma_base_addr = (uint32_t)DMAx;
3032 CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_UT1);
3033 }
3034
3035 /**
3036 * @brief Check if CTR1 update during the link transfer is enabled.
3037 * @note This API is used for all available DMA channels.
3038 * @rmtoll CLLR UT1 LL_DMA_IsEnabledCTR1Update
3039 * @param DMAx DMAx Instance
3040 * @param Channel This parameter can be one of the following values:
3041 * @arg @ref LL_DMA_CHANNEL_0
3042 * @arg @ref LL_DMA_CHANNEL_1
3043 * @arg @ref LL_DMA_CHANNEL_2
3044 * @arg @ref LL_DMA_CHANNEL_3
3045 * @arg @ref LL_DMA_CHANNEL_4
3046 * @arg @ref LL_DMA_CHANNEL_5
3047 * @arg @ref LL_DMA_CHANNEL_6
3048 * @arg @ref LL_DMA_CHANNEL_7
3049 * @retval State of bit (1 or 0).
3050 */
LL_DMA_IsEnabledCTR1Update(const DMA_TypeDef * DMAx,uint32_t Channel)3051 __STATIC_INLINE uint32_t LL_DMA_IsEnabledCTR1Update(const DMA_TypeDef *DMAx, uint32_t Channel)
3052 {
3053 uint32_t dma_base_addr = (uint32_t)DMAx;
3054 return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_UT1)
3055 == (DMA_CLLR_UT1)) ? 1UL : 0UL);
3056 }
3057
3058 /**
3059 * @brief Enable CTR2 update during the link transfer.
3060 * @note This API is used for all available DMA channels.
3061 * @rmtoll CLLR UT2 LL_DMA_EnableCTR2Update
3062 * @param DMAx DMAx Instance
3063 * @param Channel This parameter can be one of the following values:
3064 * @arg @ref LL_DMA_CHANNEL_0
3065 * @arg @ref LL_DMA_CHANNEL_1
3066 * @arg @ref LL_DMA_CHANNEL_2
3067 * @arg @ref LL_DMA_CHANNEL_3
3068 * @arg @ref LL_DMA_CHANNEL_4
3069 * @arg @ref LL_DMA_CHANNEL_5
3070 * @arg @ref LL_DMA_CHANNEL_6
3071 * @arg @ref LL_DMA_CHANNEL_7
3072 * @retval None.
3073 */
LL_DMA_EnableCTR2Update(const DMA_TypeDef * DMAx,uint32_t Channel)3074 __STATIC_INLINE void LL_DMA_EnableCTR2Update(const DMA_TypeDef *DMAx, uint32_t Channel)
3075 {
3076 uint32_t dma_base_addr = (uint32_t)DMAx;
3077 SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_UT2);
3078 }
3079
3080 /**
3081 * @brief Disable CTR2 update during the link transfer.
3082 * @note This API is used for all available DMA channels.
3083 * @rmtoll CLLR UT2 LL_DMA_DisableCTR2Update
3084 * @param DMAx DMAx Instance
3085 * @param Channel This parameter can be one of the following values:
3086 * @arg @ref LL_DMA_CHANNEL_0
3087 * @arg @ref LL_DMA_CHANNEL_1
3088 * @arg @ref LL_DMA_CHANNEL_2
3089 * @arg @ref LL_DMA_CHANNEL_3
3090 * @arg @ref LL_DMA_CHANNEL_4
3091 * @arg @ref LL_DMA_CHANNEL_5
3092 * @arg @ref LL_DMA_CHANNEL_6
3093 * @arg @ref LL_DMA_CHANNEL_7
3094 * @retval None.
3095 */
LL_DMA_DisableCTR2Update(const DMA_TypeDef * DMAx,uint32_t Channel)3096 __STATIC_INLINE void LL_DMA_DisableCTR2Update(const DMA_TypeDef *DMAx, uint32_t Channel)
3097 {
3098 uint32_t dma_base_addr = (uint32_t)DMAx;
3099 CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_UT2);
3100 }
3101
3102 /**
3103 * @brief Check if CTR2 update during the link transfer is enabled.
3104 * @note This API is used for all available DMA channels.
3105 * @rmtoll CLLR UT2 LL_DMA_IsEnabledCTR2Update
3106 * @param DMAx DMAx Instance
3107 * @param Channel This parameter can be one of the following values:
3108 * @arg @ref LL_DMA_CHANNEL_0
3109 * @arg @ref LL_DMA_CHANNEL_1
3110 * @arg @ref LL_DMA_CHANNEL_2
3111 * @arg @ref LL_DMA_CHANNEL_3
3112 * @arg @ref LL_DMA_CHANNEL_4
3113 * @arg @ref LL_DMA_CHANNEL_5
3114 * @arg @ref LL_DMA_CHANNEL_6
3115 * @arg @ref LL_DMA_CHANNEL_7
3116 * @retval State of bit (1 or 0).
3117 */
LL_DMA_IsEnabledCTR2Update(const DMA_TypeDef * DMAx,uint32_t Channel)3118 __STATIC_INLINE uint32_t LL_DMA_IsEnabledCTR2Update(const DMA_TypeDef *DMAx, uint32_t Channel)
3119 {
3120 uint32_t dma_base_addr = (uint32_t)DMAx;
3121 return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_UT2)
3122 == (DMA_CLLR_UT2)) ? 1UL : 0UL);
3123 }
3124
3125 /**
3126 * @brief Enable CBR1 update during the link transfer.
3127 * @note This API is used for all available DMA channels.
3128 * @rmtoll CLLR UB1 LL_DMA_EnableCBR1Update
3129 * @param DMAx DMAx Instance
3130 * @param Channel This parameter can be one of the following values:
3131 * @arg @ref LL_DMA_CHANNEL_0
3132 * @arg @ref LL_DMA_CHANNEL_1
3133 * @arg @ref LL_DMA_CHANNEL_2
3134 * @arg @ref LL_DMA_CHANNEL_3
3135 * @arg @ref LL_DMA_CHANNEL_4
3136 * @arg @ref LL_DMA_CHANNEL_5
3137 * @arg @ref LL_DMA_CHANNEL_6
3138 * @arg @ref LL_DMA_CHANNEL_7
3139 * @retval None.
3140 */
LL_DMA_EnableCBR1Update(const DMA_TypeDef * DMAx,uint32_t Channel)3141 __STATIC_INLINE void LL_DMA_EnableCBR1Update(const DMA_TypeDef *DMAx, uint32_t Channel)
3142 {
3143 uint32_t dma_base_addr = (uint32_t)DMAx;
3144 SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_UB1);
3145 }
3146
3147 /**
3148 * @brief Disable CBR1 update during the link transfer.
3149 * @note This API is used for all available DMA channels.
3150 * @rmtoll CLLR UB1 LL_DMA_DisableCBR1Update
3151 * @param DMAx DMAx Instance
3152 * @param Channel This parameter can be one of the following values:
3153 * @arg @ref LL_DMA_CHANNEL_0
3154 * @arg @ref LL_DMA_CHANNEL_1
3155 * @arg @ref LL_DMA_CHANNEL_2
3156 * @arg @ref LL_DMA_CHANNEL_3
3157 * @arg @ref LL_DMA_CHANNEL_4
3158 * @arg @ref LL_DMA_CHANNEL_5
3159 * @arg @ref LL_DMA_CHANNEL_6
3160 * @arg @ref LL_DMA_CHANNEL_7
3161 * @retval None.
3162 */
LL_DMA_DisableCBR1Update(const DMA_TypeDef * DMAx,uint32_t Channel)3163 __STATIC_INLINE void LL_DMA_DisableCBR1Update(const DMA_TypeDef *DMAx, uint32_t Channel)
3164 {
3165 uint32_t dma_base_addr = (uint32_t)DMAx;
3166 CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_UB1);
3167 }
3168
3169 /**
3170 * @brief Check if CBR1 update during the link transfer is enabled.
3171 * @note This API is used for all available DMA channels.
3172 * @rmtoll CLLR UB1 LL_DMA_IsEnabledCBR1Update
3173 * @param DMAx DMAx Instance
3174 * @param Channel This parameter can be one of the following values:
3175 * @arg @ref LL_DMA_CHANNEL_0
3176 * @arg @ref LL_DMA_CHANNEL_1
3177 * @arg @ref LL_DMA_CHANNEL_2
3178 * @arg @ref LL_DMA_CHANNEL_3
3179 * @arg @ref LL_DMA_CHANNEL_4
3180 * @arg @ref LL_DMA_CHANNEL_5
3181 * @arg @ref LL_DMA_CHANNEL_6
3182 * @arg @ref LL_DMA_CHANNEL_7
3183 * @retval State of bit (1 or 0).
3184 */
LL_DMA_IsEnabledCBR1Update(const DMA_TypeDef * DMAx,uint32_t Channel)3185 __STATIC_INLINE uint32_t LL_DMA_IsEnabledCBR1Update(const DMA_TypeDef *DMAx, uint32_t Channel)
3186 {
3187 uint32_t dma_base_addr = (uint32_t)DMAx;
3188 return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_UB1)
3189 == (DMA_CLLR_UB1)) ? 1UL : 0UL);
3190 }
3191
3192 /**
3193 * @brief Enable CSAR update during the link transfer.
3194 * @note This API is used for all available DMA channels.
3195 * @rmtoll CLLR USA LL_DMA_EnableCSARUpdate
3196 * @param DMAx DMAx Instance
3197 * @param Channel This parameter can be one of the following values:
3198 * @arg @ref LL_DMA_CHANNEL_0
3199 * @arg @ref LL_DMA_CHANNEL_1
3200 * @arg @ref LL_DMA_CHANNEL_2
3201 * @arg @ref LL_DMA_CHANNEL_3
3202 * @arg @ref LL_DMA_CHANNEL_4
3203 * @arg @ref LL_DMA_CHANNEL_5
3204 * @arg @ref LL_DMA_CHANNEL_6
3205 * @arg @ref LL_DMA_CHANNEL_7
3206 * @retval None.
3207 */
LL_DMA_EnableCSARUpdate(const DMA_TypeDef * DMAx,uint32_t Channel)3208 __STATIC_INLINE void LL_DMA_EnableCSARUpdate(const DMA_TypeDef *DMAx, uint32_t Channel)
3209 {
3210 uint32_t dma_base_addr = (uint32_t)DMAx;
3211 SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_USA);
3212 }
3213
3214 /**
3215 * @brief Disable CSAR update during the link transfer.
3216 * @note This API is used for all available DMA channels.
3217 * @rmtoll CLLR USA LL_DMA_DisableCSARUpdate
3218 * @param DMAx DMAx Instance
3219 * @param Channel This parameter can be one of the following values:
3220 * @arg @ref LL_DMA_CHANNEL_0
3221 * @arg @ref LL_DMA_CHANNEL_1
3222 * @arg @ref LL_DMA_CHANNEL_2
3223 * @arg @ref LL_DMA_CHANNEL_3
3224 * @arg @ref LL_DMA_CHANNEL_4
3225 * @arg @ref LL_DMA_CHANNEL_5
3226 * @arg @ref LL_DMA_CHANNEL_6
3227 * @arg @ref LL_DMA_CHANNEL_7
3228 * @retval None.
3229 */
LL_DMA_DisableCSARUpdate(const DMA_TypeDef * DMAx,uint32_t Channel)3230 __STATIC_INLINE void LL_DMA_DisableCSARUpdate(const DMA_TypeDef *DMAx, uint32_t Channel)
3231 {
3232 uint32_t dma_base_addr = (uint32_t)DMAx;
3233 CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_USA);
3234 }
3235
3236 /**
3237 * @brief Check if CSAR update during the link transfer is enabled.
3238 * @note This API is used for all available DMA channels.
3239 * @rmtoll CLLR USA LL_DMA_IsEnabledCSARUpdate
3240 * @param DMAx DMAx Instance
3241 * @param Channel This parameter can be one of the following values:
3242 * @arg @ref LL_DMA_CHANNEL_0
3243 * @arg @ref LL_DMA_CHANNEL_1
3244 * @arg @ref LL_DMA_CHANNEL_2
3245 * @arg @ref LL_DMA_CHANNEL_3
3246 * @arg @ref LL_DMA_CHANNEL_4
3247 * @arg @ref LL_DMA_CHANNEL_5
3248 * @arg @ref LL_DMA_CHANNEL_6
3249 * @arg @ref LL_DMA_CHANNEL_7
3250 * @retval State of bit (1 or 0).
3251 */
LL_DMA_IsEnabledCSARUpdate(const DMA_TypeDef * DMAx,uint32_t Channel)3252 __STATIC_INLINE uint32_t LL_DMA_IsEnabledCSARUpdate(const DMA_TypeDef *DMAx, uint32_t Channel)
3253 {
3254 uint32_t dma_base_addr = (uint32_t)DMAx;
3255 return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_USA)
3256 == (DMA_CLLR_USA)) ? 1UL : 0UL);
3257 }
3258
3259 /**
3260 * @brief Enable CDAR update during the link transfer.
3261 * @note This API is used for all available DMA channels.
3262 * @rmtoll CLLR UDA LL_DMA_EnableCDARUpdate
3263 * @param DMAx DMAx Instance
3264 * @param Channel This parameter can be one of the following values:
3265 * @arg @ref LL_DMA_CHANNEL_0
3266 * @arg @ref LL_DMA_CHANNEL_1
3267 * @arg @ref LL_DMA_CHANNEL_2
3268 * @arg @ref LL_DMA_CHANNEL_3
3269 * @arg @ref LL_DMA_CHANNEL_4
3270 * @arg @ref LL_DMA_CHANNEL_5
3271 * @arg @ref LL_DMA_CHANNEL_6
3272 * @arg @ref LL_DMA_CHANNEL_7
3273 * @retval None.
3274 */
LL_DMA_EnableCDARUpdate(const DMA_TypeDef * DMAx,uint32_t Channel)3275 __STATIC_INLINE void LL_DMA_EnableCDARUpdate(const DMA_TypeDef *DMAx, uint32_t Channel)
3276 {
3277 uint32_t dma_base_addr = (uint32_t)DMAx;
3278 SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_UDA);
3279 }
3280
3281 /**
3282 * @brief Disable CDAR update during the link transfer.
3283 * @note This API is used for all available DMA channels.
3284 * @rmtoll CLLR UDA LL_DMA_DisableCDARUpdate
3285 * @param DMAx DMAx Instance
3286 * @param Channel This parameter can be one of the following values:
3287 * @arg @ref LL_DMA_CHANNEL_0
3288 * @arg @ref LL_DMA_CHANNEL_1
3289 * @arg @ref LL_DMA_CHANNEL_2
3290 * @arg @ref LL_DMA_CHANNEL_3
3291 * @arg @ref LL_DMA_CHANNEL_4
3292 * @arg @ref LL_DMA_CHANNEL_5
3293 * @arg @ref LL_DMA_CHANNEL_6
3294 * @arg @ref LL_DMA_CHANNEL_7
3295 * @retval None.
3296 */
LL_DMA_DisableCDARUpdate(const DMA_TypeDef * DMAx,uint32_t Channel)3297 __STATIC_INLINE void LL_DMA_DisableCDARUpdate(const DMA_TypeDef *DMAx, uint32_t Channel)
3298 {
3299 uint32_t dma_base_addr = (uint32_t)DMAx;
3300 CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_UDA);
3301 }
3302
3303 /**
3304 * @brief Check if CDAR update during the link transfer is enabled.
3305 * @note This API is used for all available DMA channels.
3306 * @rmtoll CLLR UDA LL_DMA_IsEnabledCDARUpdate
3307 * @param DMAx DMAx Instance
3308 * @param Channel This parameter can be one of the following values:
3309 * @arg @ref LL_DMA_CHANNEL_0
3310 * @arg @ref LL_DMA_CHANNEL_1
3311 * @arg @ref LL_DMA_CHANNEL_2
3312 * @arg @ref LL_DMA_CHANNEL_3
3313 * @arg @ref LL_DMA_CHANNEL_4
3314 * @arg @ref LL_DMA_CHANNEL_5
3315 * @arg @ref LL_DMA_CHANNEL_6
3316 * @arg @ref LL_DMA_CHANNEL_7
3317 * @retval State of bit (1 or 0).
3318 */
LL_DMA_IsEnabledCDARUpdate(const DMA_TypeDef * DMAx,uint32_t Channel)3319 __STATIC_INLINE uint32_t LL_DMA_IsEnabledCDARUpdate(const DMA_TypeDef *DMAx, uint32_t Channel)
3320 {
3321 uint32_t dma_base_addr = (uint32_t)DMAx;
3322 return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_UDA)
3323 == (DMA_CLLR_UDA)) ? 1UL : 0UL);
3324 }
3325
3326
3327 /**
3328 * @brief Enable CLLR update during the link transfer.
3329 * @note This API is used for all available DMA channels.
3330 * @rmtoll CLLR ULL LL_DMA_EnableCLLRUpdate
3331 * @param DMAx DMAx Instance
3332 * @param Channel This parameter can be one of the following values:
3333 * @arg @ref LL_DMA_CHANNEL_0
3334 * @arg @ref LL_DMA_CHANNEL_1
3335 * @arg @ref LL_DMA_CHANNEL_2
3336 * @arg @ref LL_DMA_CHANNEL_3
3337 * @arg @ref LL_DMA_CHANNEL_4
3338 * @arg @ref LL_DMA_CHANNEL_5
3339 * @arg @ref LL_DMA_CHANNEL_6
3340 * @arg @ref LL_DMA_CHANNEL_7
3341 * @retval None.
3342 */
LL_DMA_EnableCLLRUpdate(const DMA_TypeDef * DMAx,uint32_t Channel)3343 __STATIC_INLINE void LL_DMA_EnableCLLRUpdate(const DMA_TypeDef *DMAx, uint32_t Channel)
3344 {
3345 uint32_t dma_base_addr = (uint32_t)DMAx;
3346 SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_ULL);
3347 }
3348
3349 /**
3350 * @brief Disable CLLR update during the link transfer.
3351 * @note This API is used for all available DMA channels.
3352 * @rmtoll CLLR ULL LL_DMA_DisableCLLRUpdate
3353 * @param DMAx DMAx Instance
3354 * @param Channel This parameter can be one of the following values:
3355 * @arg @ref LL_DMA_CHANNEL_0
3356 * @arg @ref LL_DMA_CHANNEL_1
3357 * @arg @ref LL_DMA_CHANNEL_2
3358 * @arg @ref LL_DMA_CHANNEL_3
3359 * @arg @ref LL_DMA_CHANNEL_4
3360 * @arg @ref LL_DMA_CHANNEL_5
3361 * @arg @ref LL_DMA_CHANNEL_6
3362 * @arg @ref LL_DMA_CHANNEL_7
3363 * @retval None.
3364 */
LL_DMA_DisableCLLRUpdate(const DMA_TypeDef * DMAx,uint32_t Channel)3365 __STATIC_INLINE void LL_DMA_DisableCLLRUpdate(const DMA_TypeDef *DMAx, uint32_t Channel)
3366 {
3367 uint32_t dma_base_addr = (uint32_t)DMAx;
3368 CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_ULL);
3369 }
3370
3371 /**
3372 * @brief Check if CLLR update during the link transfer is enabled.
3373 * @note This API is used for all available DMA channels.
3374 * @rmtoll CLLR ULL LL_DMA_IsEnabledCLLRUpdate
3375 * @param DMAx DMAx Instance
3376 * @param Channel This parameter can be one of the following values:
3377 * @arg @ref LL_DMA_CHANNEL_0
3378 * @arg @ref LL_DMA_CHANNEL_1
3379 * @arg @ref LL_DMA_CHANNEL_2
3380 * @arg @ref LL_DMA_CHANNEL_3
3381 * @arg @ref LL_DMA_CHANNEL_4
3382 * @arg @ref LL_DMA_CHANNEL_5
3383 * @arg @ref LL_DMA_CHANNEL_6
3384 * @arg @ref LL_DMA_CHANNEL_7
3385 * @retval State of bit (1 or 0).
3386 */
LL_DMA_IsEnabledCLLRUpdate(const DMA_TypeDef * DMAx,uint32_t Channel)3387 __STATIC_INLINE uint32_t LL_DMA_IsEnabledCLLRUpdate(const DMA_TypeDef *DMAx, uint32_t Channel)
3388 {
3389 uint32_t dma_base_addr = (uint32_t)DMAx;
3390 return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_ULL)
3391 == (DMA_CLLR_ULL)) ? 1UL : 0UL);
3392 }
3393
3394 /**
3395 * @brief Set linked list address offset.
3396 * @note This API is used for all available DMA channels.
3397 * @rmtoll CLLR LA LL_DMA_SetLinkedListAddrOffset
3398 * @param DMAx DMAx Instance
3399 * @param Channel This parameter can be one of the following values:
3400 * @arg @ref LL_DMA_CHANNEL_0
3401 * @arg @ref LL_DMA_CHANNEL_1
3402 * @arg @ref LL_DMA_CHANNEL_2
3403 * @arg @ref LL_DMA_CHANNEL_3
3404 * @arg @ref LL_DMA_CHANNEL_4
3405 * @arg @ref LL_DMA_CHANNEL_5
3406 * @arg @ref LL_DMA_CHANNEL_6
3407 * @arg @ref LL_DMA_CHANNEL_7
3408 * @param LinkedListAddrOffset Between 0 to 0x0000FFFC by increment of 4 (4 Bytes)
3409 * @retval None.
3410 */
LL_DMA_SetLinkedListAddrOffset(const DMA_TypeDef * DMAx,uint32_t Channel,uint32_t LinkedListAddrOffset)3411 __STATIC_INLINE void LL_DMA_SetLinkedListAddrOffset(const DMA_TypeDef *DMAx, uint32_t Channel,
3412 uint32_t LinkedListAddrOffset)
3413 {
3414 uint32_t dma_base_addr = (uint32_t)DMAx;
3415 MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_LA,
3416 (LinkedListAddrOffset & DMA_CLLR_LA));
3417 }
3418
3419 /**
3420 * @brief Get linked list address offset.
3421 * @note This API is used for all available DMA channels.
3422 * @rmtoll CLLR LA LL_DMA_GetLinkedListAddrOffset
3423 * @param DMAx DMAx Instance
3424 * @param Channel This parameter can be one of the following values:
3425 * @arg @ref LL_DMA_CHANNEL_0
3426 * @arg @ref LL_DMA_CHANNEL_1
3427 * @arg @ref LL_DMA_CHANNEL_2
3428 * @arg @ref LL_DMA_CHANNEL_3
3429 * @arg @ref LL_DMA_CHANNEL_4
3430 * @arg @ref LL_DMA_CHANNEL_5
3431 * @arg @ref LL_DMA_CHANNEL_6
3432 * @arg @ref LL_DMA_CHANNEL_7
3433 * @retval Between 0 to 0x0000FFFC.
3434 */
LL_DMA_GetLinkedListAddrOffset(const DMA_TypeDef * DMAx,uint32_t Channel)3435 __STATIC_INLINE uint32_t LL_DMA_GetLinkedListAddrOffset(const DMA_TypeDef *DMAx, uint32_t Channel)
3436 {
3437 uint32_t dma_base_addr = (uint32_t)DMAx;
3438 return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR,
3439 DMA_CLLR_LA) >> DMA_CLLR_LA_Pos);
3440 }
3441
3442 /**
3443 * @brief Get FIFO level.
3444 * @rmtoll CSR FIFOL LL_DMA_GetFIFOLevel
3445 * @param DMAx DMAx Instance
3446 * @param Channel This parameter can be one of the following values:
3447 * @arg @ref LL_DMA_CHANNEL_0
3448 * @arg @ref LL_DMA_CHANNEL_1
3449 * @arg @ref LL_DMA_CHANNEL_2
3450 * @arg @ref LL_DMA_CHANNEL_3
3451 * @arg @ref LL_DMA_CHANNEL_4
3452 * @arg @ref LL_DMA_CHANNEL_5
3453 * @arg @ref LL_DMA_CHANNEL_6
3454 * @arg @ref LL_DMA_CHANNEL_7
3455 * @retval Between 0 to 0x000000FF.
3456 */
LL_DMA_GetFIFOLevel(const DMA_TypeDef * DMAx,uint32_t Channel)3457 __STATIC_INLINE uint32_t LL_DMA_GetFIFOLevel(const DMA_TypeDef *DMAx, uint32_t Channel)
3458 {
3459 uint32_t dma_base_addr = (uint32_t)DMAx;
3460 return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CSR,
3461 DMA_CSR_FIFOL) >> DMA_CSR_FIFOL_Pos);
3462 }
3463
3464 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
3465 /**
3466 * @brief Enable the DMA channel secure attribute.
3467 * @note This API is used for all available DMA channels.
3468 * @rmtoll SECCFGR SECx LL_DMA_EnableChannelSecure
3469 * @param DMAx DMAx Instance
3470 * @param Channel This parameter can be one of the following values:
3471 * @arg @ref LL_DMA_CHANNEL_0
3472 * @arg @ref LL_DMA_CHANNEL_1
3473 * @arg @ref LL_DMA_CHANNEL_2
3474 * @arg @ref LL_DMA_CHANNEL_3
3475 * @arg @ref LL_DMA_CHANNEL_4
3476 * @arg @ref LL_DMA_CHANNEL_5
3477 * @arg @ref LL_DMA_CHANNEL_6
3478 * @arg @ref LL_DMA_CHANNEL_7
3479 * @retval None.
3480 */
LL_DMA_EnableChannelSecure(DMA_TypeDef * DMAx,uint32_t Channel)3481 __STATIC_INLINE void LL_DMA_EnableChannelSecure(DMA_TypeDef *DMAx, uint32_t Channel)
3482 {
3483 SET_BIT(DMAx->SECCFGR, (DMA_SECCFGR_SEC0 << (Channel & 0x0000000FU)));
3484 }
3485
3486 /**
3487 * @brief Disable the DMA channel secure attribute.
3488 * @note This API is used for all available DMA channels.
3489 * @rmtoll SECCFGR SECx LL_DMA_DisableChannelSecure
3490 * @param DMAx DMAx Instance
3491 * @param Channel This parameter can be one of the following values:
3492 * @arg @ref LL_DMA_CHANNEL_0
3493 * @arg @ref LL_DMA_CHANNEL_1
3494 * @arg @ref LL_DMA_CHANNEL_2
3495 * @arg @ref LL_DMA_CHANNEL_3
3496 * @arg @ref LL_DMA_CHANNEL_4
3497 * @arg @ref LL_DMA_CHANNEL_5
3498 * @arg @ref LL_DMA_CHANNEL_6
3499 * @arg @ref LL_DMA_CHANNEL_7
3500 * @retval None.
3501 */
LL_DMA_DisableChannelSecure(DMA_TypeDef * DMAx,uint32_t Channel)3502 __STATIC_INLINE void LL_DMA_DisableChannelSecure(DMA_TypeDef *DMAx, uint32_t Channel)
3503 {
3504 CLEAR_BIT(DMAx->SECCFGR, (DMA_SECCFGR_SEC0 << (Channel & 0x0000000FU)));
3505 }
3506
3507 /**
3508 * @brief Check if DMA channel secure is enabled.
3509 * @note This API is used for all available DMA channels.
3510 * @rmtoll SECCFGR SECx LL_DMA_IsEnabledChannelSecure
3511 * @param DMAx DMAx Instance
3512 * @param Channel This parameter can be one of the following values:
3513 * @arg @ref LL_DMA_CHANNEL_0
3514 * @arg @ref LL_DMA_CHANNEL_1
3515 * @arg @ref LL_DMA_CHANNEL_2
3516 * @arg @ref LL_DMA_CHANNEL_3
3517 * @arg @ref LL_DMA_CHANNEL_4
3518 * @arg @ref LL_DMA_CHANNEL_5
3519 * @arg @ref LL_DMA_CHANNEL_6
3520 * @arg @ref LL_DMA_CHANNEL_7
3521 * @retval State of bit (1 or 0).
3522 */
LL_DMA_IsEnabledChannelSecure(const DMA_TypeDef * DMAx,uint32_t Channel)3523 __STATIC_INLINE uint32_t LL_DMA_IsEnabledChannelSecure(const DMA_TypeDef *DMAx, uint32_t Channel)
3524 {
3525 return ((READ_BIT(DMAx->SECCFGR, (DMA_SECCFGR_SEC0 << (Channel & 0x0000000FU)))
3526 == (DMA_SECCFGR_SEC0 << (Channel & 0x0000000FU))) ? 1UL : 0UL);
3527 }
3528 #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
3529 #if defined (DMA_PRIVCFGR_PRIV0)
3530 /**
3531 * @brief Enable the DMA channel privilege attribute.
3532 * @note This API is used for all available DMA channels.
3533 * @rmtoll PRIVCFGR PRIVx LL_DMA_EnableChannelPrivilege
3534 * @param DMAx DMAx Instance
3535 * @param Channel This parameter can be one of the following values:
3536 * @arg @ref LL_DMA_CHANNEL_0
3537 * @arg @ref LL_DMA_CHANNEL_1
3538 * @arg @ref LL_DMA_CHANNEL_2
3539 * @arg @ref LL_DMA_CHANNEL_3
3540 * @arg @ref LL_DMA_CHANNEL_4
3541 * @arg @ref LL_DMA_CHANNEL_5
3542 * @arg @ref LL_DMA_CHANNEL_6
3543 * @arg @ref LL_DMA_CHANNEL_7
3544 * @retval None.
3545 */
LL_DMA_EnableChannelPrivilege(DMA_TypeDef * DMAx,uint32_t Channel)3546 __STATIC_INLINE void LL_DMA_EnableChannelPrivilege(DMA_TypeDef *DMAx, uint32_t Channel)
3547 {
3548 SET_BIT(DMAx->PRIVCFGR, (DMA_PRIVCFGR_PRIV0 << (Channel & 0x0000000FU)));
3549 }
3550
3551 /**
3552 * @brief Disable the DMA channel privilege attribute.
3553 * @note This API is used for all available DMA channels.
3554 * @rmtoll PRIVCFGR PRIVx LL_DMA_DisableChannelPrivilege
3555 * @param DMAx DMAx Instance
3556 * @param Channel This parameter can be one of the following values:
3557 * @arg @ref LL_DMA_CHANNEL_0
3558 * @arg @ref LL_DMA_CHANNEL_1
3559 * @arg @ref LL_DMA_CHANNEL_2
3560 * @arg @ref LL_DMA_CHANNEL_3
3561 * @arg @ref LL_DMA_CHANNEL_4
3562 * @arg @ref LL_DMA_CHANNEL_5
3563 * @arg @ref LL_DMA_CHANNEL_6
3564 * @arg @ref LL_DMA_CHANNEL_7
3565 * @retval None.
3566 */
LL_DMA_DisableChannelPrivilege(DMA_TypeDef * DMAx,uint32_t Channel)3567 __STATIC_INLINE void LL_DMA_DisableChannelPrivilege(DMA_TypeDef *DMAx, uint32_t Channel)
3568 {
3569 CLEAR_BIT(DMAx->PRIVCFGR, (DMA_PRIVCFGR_PRIV0 << (Channel & 0x0000000FU)));
3570 }
3571
3572 /**
3573 * @brief Check if DMA Channel privilege is enabled.
3574 * @note This API is used for all available DMA channels.
3575 * @rmtoll PRIVCFGR PRIVx LL_DMA_IsEnabledChannelPrivilege
3576 * @param DMAx DMAx Instance
3577 * @param Channel This parameter can be one of the following values:
3578 * @arg @ref LL_DMA_CHANNEL_0
3579 * @arg @ref LL_DMA_CHANNEL_1
3580 * @arg @ref LL_DMA_CHANNEL_2
3581 * @arg @ref LL_DMA_CHANNEL_3
3582 * @arg @ref LL_DMA_CHANNEL_4
3583 * @arg @ref LL_DMA_CHANNEL_5
3584 * @arg @ref LL_DMA_CHANNEL_6
3585 * @arg @ref LL_DMA_CHANNEL_7
3586 * @retval State of bit (1 or 0).
3587 */
LL_DMA_IsEnabledChannelPrivilege(const DMA_TypeDef * DMAx,uint32_t Channel)3588 __STATIC_INLINE uint32_t LL_DMA_IsEnabledChannelPrivilege(const DMA_TypeDef *DMAx, uint32_t Channel)
3589 {
3590 return ((READ_BIT(DMAx->PRIVCFGR, (DMA_PRIVCFGR_PRIV0 << (Channel & 0x0000000FU)))
3591 == (DMA_PRIVCFGR_PRIV0 << (Channel & 0x0000000FU))) ? 1UL : 0UL);
3592 }
3593 #endif /* defined (DMA_PRIVCFGR_PRIV0) */
3594 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
3595 /**
3596 * @brief Enable the DMA channel lock attributes.
3597 * @note This API is used for all available DMA channels.
3598 * @rmtoll RCFGLOCKR LOCKx LL_DMA_EnableChannelLockAttribute
3599 * @param DMAx DMAx Instance
3600 * @param Channel This parameter can be one of the following values:
3601 * @arg @ref LL_DMA_CHANNEL_0
3602 * @arg @ref LL_DMA_CHANNEL_1
3603 * @arg @ref LL_DMA_CHANNEL_2
3604 * @arg @ref LL_DMA_CHANNEL_3
3605 * @arg @ref LL_DMA_CHANNEL_4
3606 * @arg @ref LL_DMA_CHANNEL_5
3607 * @arg @ref LL_DMA_CHANNEL_6
3608 * @arg @ref LL_DMA_CHANNEL_7
3609 * @retval None.
3610 */
LL_DMA_EnableChannelLockAttribute(DMA_TypeDef * DMAx,uint32_t Channel)3611 __STATIC_INLINE void LL_DMA_EnableChannelLockAttribute(DMA_TypeDef *DMAx, uint32_t Channel)
3612 {
3613 SET_BIT(DMAx->RCFGLOCKR, (DMA_RCFGLOCKR_LOCK0 << (Channel & 0x0000000FU)));
3614 }
3615 #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
3616 #if defined (DMA_RCFGLOCKR_LOCK0)
3617 /**
3618 * @brief Check if DMA channel attributes are locked.
3619 * @note This API is used for all available DMA channels.
3620 * @rmtoll SECCFGR LOCKx LL_DMA_IsEnabledChannelLockAttribute
3621 * @param DMAx DMAx Instance
3622 * @param Channel This parameter can be one of the following values:
3623 * @arg @ref LL_DMA_CHANNEL_0
3624 * @arg @ref LL_DMA_CHANNEL_1
3625 * @arg @ref LL_DMA_CHANNEL_2
3626 * @arg @ref LL_DMA_CHANNEL_3
3627 * @arg @ref LL_DMA_CHANNEL_4
3628 * @arg @ref LL_DMA_CHANNEL_5
3629 * @arg @ref LL_DMA_CHANNEL_6
3630 * @arg @ref LL_DMA_CHANNEL_7
3631 * @retval State of bit (1 or 0).
3632 */
LL_DMA_IsEnabledChannelLockAttribute(const DMA_TypeDef * DMAx,uint32_t Channel)3633 __STATIC_INLINE uint32_t LL_DMA_IsEnabledChannelLockAttribute(const DMA_TypeDef *DMAx, uint32_t Channel)
3634 {
3635 return ((READ_BIT(DMAx->RCFGLOCKR, (DMA_RCFGLOCKR_LOCK0 << (Channel & 0x0000000FU)))
3636 == (DMA_RCFGLOCKR_LOCK0 << (Channel & 0x0000000FU))) ? 1UL : 0UL);
3637 }
3638
3639 #endif /* defined (DMA_RCFGLOCKR_LOCK0) */
3640 /**
3641 * @}
3642 */
3643
3644 /** @defgroup DMA_LL_EF_FLAG_Management Flag Management
3645 * @{
3646 */
3647
3648 /**
3649 * @brief Clear trigger overrun flag.
3650 * @note This API is used for all available DMA channels.
3651 * @rmtoll CFCR TOF LL_DMA_ClearFlag_TO
3652 * @param DMAx DMAx Instance
3653 * @param Channel This parameter can be one of the following values:
3654 * @arg @ref LL_DMA_CHANNEL_0
3655 * @arg @ref LL_DMA_CHANNEL_1
3656 * @arg @ref LL_DMA_CHANNEL_2
3657 * @arg @ref LL_DMA_CHANNEL_3
3658 * @arg @ref LL_DMA_CHANNEL_4
3659 * @arg @ref LL_DMA_CHANNEL_5
3660 * @arg @ref LL_DMA_CHANNEL_6
3661 * @arg @ref LL_DMA_CHANNEL_7
3662 * @retval None.
3663 */
LL_DMA_ClearFlag_TO(const DMA_TypeDef * DMAx,uint32_t Channel)3664 __STATIC_INLINE void LL_DMA_ClearFlag_TO(const DMA_TypeDef *DMAx, uint32_t Channel)
3665 {
3666 uint32_t dma_base_addr = (uint32_t)DMAx;
3667 WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CFCR, DMA_CFCR_TOF);
3668 }
3669
3670 /**
3671 * @brief Clear suspension flag.
3672 * @note This API is used for all available DMA channels.
3673 * @rmtoll CFCR SUSPF LL_DMA_ClearFlag_SUSP
3674 * @param DMAx DMAx Instance
3675 * @param Channel This parameter can be one of the following values:
3676 * @arg @ref LL_DMA_CHANNEL_0
3677 * @arg @ref LL_DMA_CHANNEL_1
3678 * @arg @ref LL_DMA_CHANNEL_2
3679 * @arg @ref LL_DMA_CHANNEL_3
3680 * @arg @ref LL_DMA_CHANNEL_4
3681 * @arg @ref LL_DMA_CHANNEL_5
3682 * @arg @ref LL_DMA_CHANNEL_6
3683 * @arg @ref LL_DMA_CHANNEL_7
3684 * @retval None.
3685 */
LL_DMA_ClearFlag_SUSP(const DMA_TypeDef * DMAx,uint32_t Channel)3686 __STATIC_INLINE void LL_DMA_ClearFlag_SUSP(const DMA_TypeDef *DMAx, uint32_t Channel)
3687 {
3688 uint32_t dma_base_addr = (uint32_t)DMAx;
3689 WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CFCR, DMA_CFCR_SUSPF);
3690 }
3691
3692 /**
3693 * @brief Clear user setting error flag.
3694 * @note This API is used for all available DMA channels.
3695 * @rmtoll CFCR USEF LL_DMA_ClearFlag_USE
3696 * @param DMAx DMAx Instance
3697 * @param Channel This parameter can be one of the following values:
3698 * @arg @ref LL_DMA_CHANNEL_0
3699 * @arg @ref LL_DMA_CHANNEL_1
3700 * @arg @ref LL_DMA_CHANNEL_2
3701 * @arg @ref LL_DMA_CHANNEL_3
3702 * @arg @ref LL_DMA_CHANNEL_4
3703 * @arg @ref LL_DMA_CHANNEL_5
3704 * @arg @ref LL_DMA_CHANNEL_6
3705 * @arg @ref LL_DMA_CHANNEL_7
3706 * @retval None.
3707 */
LL_DMA_ClearFlag_USE(const DMA_TypeDef * DMAx,uint32_t Channel)3708 __STATIC_INLINE void LL_DMA_ClearFlag_USE(const DMA_TypeDef *DMAx, uint32_t Channel)
3709 {
3710 uint32_t dma_base_addr = (uint32_t)DMAx;
3711 WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CFCR, DMA_CFCR_USEF);
3712 }
3713
3714 /**
3715 * @brief Clear link transfer error flag.
3716 * @note This API is used for all available DMA channels.
3717 * @rmtoll CFCR ULEF LL_DMA_ClearFlag_ULE
3718 * @param DMAx DMAx Instance
3719 * @param Channel This parameter can be one of the following values:
3720 * @arg @ref LL_DMA_CHANNEL_0
3721 * @arg @ref LL_DMA_CHANNEL_1
3722 * @arg @ref LL_DMA_CHANNEL_2
3723 * @arg @ref LL_DMA_CHANNEL_3
3724 * @arg @ref LL_DMA_CHANNEL_4
3725 * @arg @ref LL_DMA_CHANNEL_5
3726 * @arg @ref LL_DMA_CHANNEL_6
3727 * @arg @ref LL_DMA_CHANNEL_7
3728 * @retval None.
3729 */
LL_DMA_ClearFlag_ULE(const DMA_TypeDef * DMAx,uint32_t Channel)3730 __STATIC_INLINE void LL_DMA_ClearFlag_ULE(const DMA_TypeDef *DMAx, uint32_t Channel)
3731 {
3732 uint32_t dma_base_addr = (uint32_t)DMAx;
3733 WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CFCR, DMA_CFCR_ULEF);
3734 }
3735
3736 /**
3737 * @brief Clear data transfer error flag.
3738 * @note This API is used for all available DMA channels.
3739 * @rmtoll CFCR DTEF LL_DMA_ClearFlag_DTE
3740 * @param DMAx DMAx Instance
3741 * @param Channel This parameter can be one of the following values:
3742 * @arg @ref LL_DMA_CHANNEL_0
3743 * @arg @ref LL_DMA_CHANNEL_1
3744 * @arg @ref LL_DMA_CHANNEL_2
3745 * @arg @ref LL_DMA_CHANNEL_3
3746 * @arg @ref LL_DMA_CHANNEL_4
3747 * @arg @ref LL_DMA_CHANNEL_5
3748 * @arg @ref LL_DMA_CHANNEL_6
3749 * @arg @ref LL_DMA_CHANNEL_7
3750 * @retval None.
3751 */
LL_DMA_ClearFlag_DTE(const DMA_TypeDef * DMAx,uint32_t Channel)3752 __STATIC_INLINE void LL_DMA_ClearFlag_DTE(const DMA_TypeDef *DMAx, uint32_t Channel)
3753 {
3754 uint32_t dma_base_addr = (uint32_t)DMAx;
3755 WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CFCR, DMA_CFCR_DTEF);
3756 }
3757
3758 /**
3759 * @brief Clear half transfer flag.
3760 * @note This API is used for all available DMA channels.
3761 * @rmtoll CFCR HTF LL_DMA_ClearFlag_HT
3762 * @param DMAx DMAx Instance
3763 * @param Channel This parameter can be one of the following values:
3764 * @arg @ref LL_DMA_CHANNEL_0
3765 * @arg @ref LL_DMA_CHANNEL_1
3766 * @arg @ref LL_DMA_CHANNEL_2
3767 * @arg @ref LL_DMA_CHANNEL_3
3768 * @arg @ref LL_DMA_CHANNEL_4
3769 * @arg @ref LL_DMA_CHANNEL_5
3770 * @arg @ref LL_DMA_CHANNEL_6
3771 * @arg @ref LL_DMA_CHANNEL_7
3772 * @retval None.
3773 */
LL_DMA_ClearFlag_HT(const DMA_TypeDef * DMAx,uint32_t Channel)3774 __STATIC_INLINE void LL_DMA_ClearFlag_HT(const DMA_TypeDef *DMAx, uint32_t Channel)
3775 {
3776 uint32_t dma_base_addr = (uint32_t)DMAx;
3777 WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CFCR, DMA_CFCR_HTF);
3778 }
3779
3780 /**
3781 * @brief Clear transfer complete flag.
3782 * @note This API is used for all available DMA channels.
3783 * @rmtoll CFCR TCF LL_DMA_ClearFlag_TC
3784 * @param DMAx DMAx Instance
3785 * @param Channel This parameter can be one of the following values:
3786 * @arg @ref LL_DMA_CHANNEL_0
3787 * @arg @ref LL_DMA_CHANNEL_1
3788 * @arg @ref LL_DMA_CHANNEL_2
3789 * @arg @ref LL_DMA_CHANNEL_3
3790 * @arg @ref LL_DMA_CHANNEL_4
3791 * @arg @ref LL_DMA_CHANNEL_5
3792 * @arg @ref LL_DMA_CHANNEL_6
3793 * @arg @ref LL_DMA_CHANNEL_7
3794 * @retval None.
3795 */
LL_DMA_ClearFlag_TC(const DMA_TypeDef * DMAx,uint32_t Channel)3796 __STATIC_INLINE void LL_DMA_ClearFlag_TC(const DMA_TypeDef *DMAx, uint32_t Channel)
3797 {
3798 uint32_t dma_base_addr = (uint32_t)DMAx;
3799 WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CFCR, DMA_CFCR_TCF);
3800 }
3801
3802 /**
3803 * @brief Get trigger overrun flag.
3804 * @note This API is used for all available DMA channels.
3805 * @rmtoll CSR TOF LL_DMA_IsActiveFlag_TO
3806 * @param DMAx DMAx Instance
3807 * @param Channel This parameter can be one of the following values:
3808 * @arg @ref LL_DMA_CHANNEL_0
3809 * @arg @ref LL_DMA_CHANNEL_1
3810 * @arg @ref LL_DMA_CHANNEL_2
3811 * @arg @ref LL_DMA_CHANNEL_3
3812 * @arg @ref LL_DMA_CHANNEL_4
3813 * @arg @ref LL_DMA_CHANNEL_5
3814 * @arg @ref LL_DMA_CHANNEL_6
3815 * @arg @ref LL_DMA_CHANNEL_7
3816 * @retval State of bit (1 or 0).
3817 */
LL_DMA_IsActiveFlag_TO(const DMA_TypeDef * DMAx,uint32_t Channel)3818 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TO(const DMA_TypeDef *DMAx, uint32_t Channel)
3819 {
3820 uint32_t dma_base_addr = (uint32_t)DMAx;
3821 return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CSR, DMA_CSR_TOF)
3822 == (DMA_CSR_TOF)) ? 1UL : 0UL);
3823 }
3824
3825 /**
3826 * @brief Get suspension flag.
3827 * @note This API is used for all available DMA channels.
3828 * @rmtoll CSR SUSPF LL_DMA_IsActiveFlag_SUSP
3829 * @param DMAx DMAx Instance
3830 * @param Channel This parameter can be one of the following values:
3831 * @arg @ref LL_DMA_CHANNEL_0
3832 * @arg @ref LL_DMA_CHANNEL_1
3833 * @arg @ref LL_DMA_CHANNEL_2
3834 * @arg @ref LL_DMA_CHANNEL_3
3835 * @arg @ref LL_DMA_CHANNEL_4
3836 * @arg @ref LL_DMA_CHANNEL_5
3837 * @arg @ref LL_DMA_CHANNEL_6
3838 * @arg @ref LL_DMA_CHANNEL_7
3839 * @retval State of bit (1 or 0).
3840 */
LL_DMA_IsActiveFlag_SUSP(const DMA_TypeDef * DMAx,uint32_t Channel)3841 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_SUSP(const DMA_TypeDef *DMAx, uint32_t Channel)
3842 {
3843 uint32_t dma_base_addr = (uint32_t)DMAx;
3844 return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CSR, DMA_CSR_SUSPF)
3845 == (DMA_CSR_SUSPF)) ? 1UL : 0UL);
3846 }
3847
3848 /**
3849 * @brief Get user setting error flag.
3850 * @note This API is used for all available DMA channels.
3851 * @rmtoll CSR USEF LL_DMA_IsActiveFlag_USE
3852 * @param DMAx DMAx Instance
3853 * @param Channel This parameter can be one of the following values:
3854 * @arg @ref LL_DMA_CHANNEL_0
3855 * @arg @ref LL_DMA_CHANNEL_1
3856 * @arg @ref LL_DMA_CHANNEL_2
3857 * @arg @ref LL_DMA_CHANNEL_3
3858 * @arg @ref LL_DMA_CHANNEL_4
3859 * @arg @ref LL_DMA_CHANNEL_5
3860 * @arg @ref LL_DMA_CHANNEL_6
3861 * @arg @ref LL_DMA_CHANNEL_7
3862 * @retval State of bit (1 or 0).
3863 */
LL_DMA_IsActiveFlag_USE(const DMA_TypeDef * DMAx,uint32_t Channel)3864 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_USE(const DMA_TypeDef *DMAx, uint32_t Channel)
3865 {
3866 uint32_t dma_base_addr = (uint32_t)DMAx;
3867 return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CSR, DMA_CSR_USEF)
3868 == (DMA_CSR_USEF)) ? 1UL : 0UL);
3869 }
3870
3871 /**
3872 * @brief Get user setting error flag.
3873 * @note This API is used for all available DMA channels.
3874 * @rmtoll CSR ULEF LL_DMA_IsActiveFlag_ULE
3875 * @param DMAx DMAx Instance
3876 * @param Channel This parameter can be one of the following values:
3877 * @arg @ref LL_DMA_CHANNEL_0
3878 * @arg @ref LL_DMA_CHANNEL_1
3879 * @arg @ref LL_DMA_CHANNEL_2
3880 * @arg @ref LL_DMA_CHANNEL_3
3881 * @arg @ref LL_DMA_CHANNEL_4
3882 * @arg @ref LL_DMA_CHANNEL_5
3883 * @arg @ref LL_DMA_CHANNEL_6
3884 * @arg @ref LL_DMA_CHANNEL_7
3885 * @retval State of bit (1 or 0).
3886 */
LL_DMA_IsActiveFlag_ULE(const DMA_TypeDef * DMAx,uint32_t Channel)3887 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_ULE(const DMA_TypeDef *DMAx, uint32_t Channel)
3888 {
3889 uint32_t dma_base_addr = (uint32_t)DMAx;
3890 return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CSR, DMA_CSR_ULEF)
3891 == (DMA_CSR_ULEF)) ? 1UL : 0UL);
3892 }
3893
3894 /**
3895 * @brief Get data transfer error flag.
3896 * @note This API is used for all available DMA channels.
3897 * @rmtoll CSR DTEF LL_DMA_IsActiveFlag_DTE
3898 * @param DMAx DMAx Instance
3899 * @param Channel This parameter can be one of the following values:
3900 * @arg @ref LL_DMA_CHANNEL_0
3901 * @arg @ref LL_DMA_CHANNEL_1
3902 * @arg @ref LL_DMA_CHANNEL_2
3903 * @arg @ref LL_DMA_CHANNEL_3
3904 * @arg @ref LL_DMA_CHANNEL_4
3905 * @arg @ref LL_DMA_CHANNEL_5
3906 * @arg @ref LL_DMA_CHANNEL_6
3907 * @arg @ref LL_DMA_CHANNEL_7
3908 * @retval State of bit (1 or 0).
3909 */
LL_DMA_IsActiveFlag_DTE(const DMA_TypeDef * DMAx,uint32_t Channel)3910 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DTE(const DMA_TypeDef *DMAx, uint32_t Channel)
3911 {
3912 uint32_t dma_base_addr = (uint32_t)DMAx;
3913 return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CSR, DMA_CSR_DTEF)
3914 == (DMA_CSR_DTEF)) ? 1UL : 0UL);
3915 }
3916
3917 /**
3918 * @brief Get half transfer flag.
3919 * @note This API is used for all available DMA channels.
3920 * @rmtoll CSR HTF LL_DMA_IsActiveFlag_HT
3921 * @param DMAx DMAx Instance
3922 * @param Channel This parameter can be one of the following values:
3923 * @arg @ref LL_DMA_CHANNEL_0
3924 * @arg @ref LL_DMA_CHANNEL_1
3925 * @arg @ref LL_DMA_CHANNEL_2
3926 * @arg @ref LL_DMA_CHANNEL_3
3927 * @arg @ref LL_DMA_CHANNEL_4
3928 * @arg @ref LL_DMA_CHANNEL_5
3929 * @arg @ref LL_DMA_CHANNEL_6
3930 * @arg @ref LL_DMA_CHANNEL_7
3931 * @retval State of bit (1 or 0).
3932 */
LL_DMA_IsActiveFlag_HT(const DMA_TypeDef * DMAx,uint32_t Channel)3933 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT(const DMA_TypeDef *DMAx, uint32_t Channel)
3934 {
3935 uint32_t dma_base_addr = (uint32_t)DMAx;
3936 return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CSR, DMA_CSR_HTF)
3937 == (DMA_CSR_HTF)) ? 1UL : 0UL);
3938 }
3939
3940 /**
3941 * @brief Get transfer complete flag.
3942 * @note This API is used for all available DMA channels.
3943 * @rmtoll CSR TCF LL_DMA_IsActiveFlag_TC
3944 * @param DMAx DMAx Instance
3945 * @param Channel This parameter can be one of the following values:
3946 * @arg @ref LL_DMA_CHANNEL_0
3947 * @arg @ref LL_DMA_CHANNEL_1
3948 * @arg @ref LL_DMA_CHANNEL_2
3949 * @arg @ref LL_DMA_CHANNEL_3
3950 * @arg @ref LL_DMA_CHANNEL_4
3951 * @arg @ref LL_DMA_CHANNEL_5
3952 * @arg @ref LL_DMA_CHANNEL_6
3953 * @arg @ref LL_DMA_CHANNEL_7
3954 * @retval State of bit (1 or 0).
3955 */
LL_DMA_IsActiveFlag_TC(const DMA_TypeDef * DMAx,uint32_t Channel)3956 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC(const DMA_TypeDef *DMAx, uint32_t Channel)
3957 {
3958 uint32_t dma_base_addr = (uint32_t)DMAx;
3959 return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CSR, DMA_CSR_TCF)
3960 == (DMA_CSR_TCF)) ? 1UL : 0UL);
3961 }
3962
3963 /**
3964 * @brief Get idle flag.
3965 * @note This API is used for all available DMA channels.
3966 * @rmtoll CSR IDLEF LL_DMA_IsActiveFlag_IDLE
3967 * @param DMAx DMAx Instance
3968 * @param Channel This parameter can be one of the following values:
3969 * @arg @ref LL_DMA_CHANNEL_0
3970 * @arg @ref LL_DMA_CHANNEL_1
3971 * @arg @ref LL_DMA_CHANNEL_2
3972 * @arg @ref LL_DMA_CHANNEL_3
3973 * @arg @ref LL_DMA_CHANNEL_4
3974 * @arg @ref LL_DMA_CHANNEL_5
3975 * @arg @ref LL_DMA_CHANNEL_6
3976 * @arg @ref LL_DMA_CHANNEL_7
3977 * @retval State of bit (1 or 0).
3978 */
LL_DMA_IsActiveFlag_IDLE(const DMA_TypeDef * DMAx,uint32_t Channel)3979 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_IDLE(const DMA_TypeDef *DMAx, uint32_t Channel)
3980 {
3981 uint32_t dma_base_addr = (uint32_t)DMAx;
3982 return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CSR, DMA_CSR_IDLEF)
3983 == (DMA_CSR_IDLEF)) ? 1UL : 0UL);
3984 }
3985
3986 /**
3987 * @brief Check if nsecure masked interrupt is active.
3988 * @note This API is used for all available DMA channels.
3989 * @rmtoll MISR MISx LL_DMA_IsActiveFlag_MIS
3990 * @param DMAx DMAx Instance
3991 * @param Channel This parameter can be one of the following values:
3992 * @arg @ref LL_DMA_CHANNEL_0
3993 * @arg @ref LL_DMA_CHANNEL_1
3994 * @arg @ref LL_DMA_CHANNEL_2
3995 * @arg @ref LL_DMA_CHANNEL_3
3996 * @arg @ref LL_DMA_CHANNEL_4
3997 * @arg @ref LL_DMA_CHANNEL_5
3998 * @arg @ref LL_DMA_CHANNEL_6
3999 * @arg @ref LL_DMA_CHANNEL_7
4000 * @retval State of bit (1 or 0).
4001 */
LL_DMA_IsActiveFlag_MIS(const DMA_TypeDef * DMAx,uint32_t Channel)4002 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_MIS(const DMA_TypeDef *DMAx, uint32_t Channel)
4003 {
4004 return ((READ_BIT(DMAx->MISR, (DMA_MISR_MIS0 << (Channel & 0x0FU)))
4005 == (DMA_MISR_MIS0 << (Channel & 0x0FU))) ? 1UL : 0UL);
4006 }
4007
4008 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
4009 /**
4010 * @brief Check if secure masked interrupt is active.
4011 * @note This API is used for all available DMA channels.
4012 * @rmtoll SMISR MISx LL_DMA_IsActiveFlag_SMIS
4013 * @param DMAx DMAx Instance
4014 * @param Channel This parameter can be one of the following values:
4015 * @arg @ref LL_DMA_CHANNEL_0
4016 * @arg @ref LL_DMA_CHANNEL_1
4017 * @arg @ref LL_DMA_CHANNEL_2
4018 * @arg @ref LL_DMA_CHANNEL_3
4019 * @arg @ref LL_DMA_CHANNEL_4
4020 * @arg @ref LL_DMA_CHANNEL_5
4021 * @arg @ref LL_DMA_CHANNEL_6
4022 * @arg @ref LL_DMA_CHANNEL_7
4023 * @retval State of bit (1 or 0).
4024 */
LL_DMA_IsActiveFlag_SMIS(const DMA_TypeDef * DMAx,uint32_t Channel)4025 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_SMIS(const DMA_TypeDef *DMAx, uint32_t Channel)
4026 {
4027 return ((READ_BIT(DMAx->SMISR, (DMA_SMISR_MIS0 << (Channel & 0x0000000FU)))
4028 == (DMA_SMISR_MIS0 << (Channel & 0x0000000FU))) ? 1UL : 0UL);
4029 }
4030 #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
4031 /**
4032 * @}
4033 */
4034
4035 /** @defgroup DMA_LL_EF_IT_Management Interrupt Management
4036 * @{
4037 */
4038
4039 /**
4040 * @brief Enable trigger overrun interrupt.
4041 * @note This API is used for all available DMA channels.
4042 * @rmtoll CCR TOIE LL_DMA_EnableIT_TO
4043 * @param DMAx DMAx Instance
4044 * @param Channel This parameter can be one of the following values:
4045 * @arg @ref LL_DMA_CHANNEL_0
4046 * @arg @ref LL_DMA_CHANNEL_1
4047 * @arg @ref LL_DMA_CHANNEL_2
4048 * @arg @ref LL_DMA_CHANNEL_3
4049 * @arg @ref LL_DMA_CHANNEL_4
4050 * @arg @ref LL_DMA_CHANNEL_5
4051 * @arg @ref LL_DMA_CHANNEL_6
4052 * @arg @ref LL_DMA_CHANNEL_7
4053 * @retval None.
4054 */
LL_DMA_EnableIT_TO(const DMA_TypeDef * DMAx,uint32_t Channel)4055 __STATIC_INLINE void LL_DMA_EnableIT_TO(const DMA_TypeDef *DMAx, uint32_t Channel)
4056 {
4057 uint32_t dma_base_addr = (uint32_t)DMAx;
4058 SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_TOIE);
4059 }
4060
4061 /**
4062 * @brief Enable suspension interrupt.
4063 * @note This API is used for all available DMA channels.
4064 * @rmtoll CCR SUSPIE LL_DMA_EnableIT_SUSP
4065 * @param DMAx DMAx Instance
4066 * @param Channel This parameter can be one of the following values:
4067 * @arg @ref LL_DMA_CHANNEL_0
4068 * @arg @ref LL_DMA_CHANNEL_1
4069 * @arg @ref LL_DMA_CHANNEL_2
4070 * @arg @ref LL_DMA_CHANNEL_3
4071 * @arg @ref LL_DMA_CHANNEL_4
4072 * @arg @ref LL_DMA_CHANNEL_5
4073 * @arg @ref LL_DMA_CHANNEL_6
4074 * @arg @ref LL_DMA_CHANNEL_7
4075 * @retval None.
4076 */
LL_DMA_EnableIT_SUSP(const DMA_TypeDef * DMAx,uint32_t Channel)4077 __STATIC_INLINE void LL_DMA_EnableIT_SUSP(const DMA_TypeDef *DMAx, uint32_t Channel)
4078 {
4079 uint32_t dma_base_addr = (uint32_t)DMAx;
4080 SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_SUSPIE);
4081 }
4082
4083 /**
4084 * @brief Enable user setting error interrupt.
4085 * @note This API is used for all available DMA channels.
4086 * @rmtoll CCR USEIE LL_DMA_EnableIT_USE
4087 * @param DMAx DMAx Instance
4088 * @param Channel This parameter can be one of the following values:
4089 * @arg @ref LL_DMA_CHANNEL_0
4090 * @arg @ref LL_DMA_CHANNEL_1
4091 * @arg @ref LL_DMA_CHANNEL_2
4092 * @arg @ref LL_DMA_CHANNEL_3
4093 * @arg @ref LL_DMA_CHANNEL_4
4094 * @arg @ref LL_DMA_CHANNEL_5
4095 * @arg @ref LL_DMA_CHANNEL_6
4096 * @arg @ref LL_DMA_CHANNEL_7
4097 * @retval None.
4098 */
LL_DMA_EnableIT_USE(const DMA_TypeDef * DMAx,uint32_t Channel)4099 __STATIC_INLINE void LL_DMA_EnableIT_USE(const DMA_TypeDef *DMAx, uint32_t Channel)
4100 {
4101 uint32_t dma_base_addr = (uint32_t)DMAx;
4102 SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_USEIE);
4103 }
4104
4105 /**
4106 * @brief Enable update link transfer error interrupt.
4107 * @note This API is used for all available DMA channels.
4108 * @rmtoll CCR ULEIE LL_DMA_EnableIT_ULE
4109 * @param DMAx DMAx Instance
4110 * @param Channel This parameter can be one of the following values:
4111 * @arg @ref LL_DMA_CHANNEL_0
4112 * @arg @ref LL_DMA_CHANNEL_1
4113 * @arg @ref LL_DMA_CHANNEL_2
4114 * @arg @ref LL_DMA_CHANNEL_3
4115 * @arg @ref LL_DMA_CHANNEL_4
4116 * @arg @ref LL_DMA_CHANNEL_5
4117 * @arg @ref LL_DMA_CHANNEL_6
4118 * @arg @ref LL_DMA_CHANNEL_7
4119 * @retval None.
4120 */
LL_DMA_EnableIT_ULE(const DMA_TypeDef * DMAx,uint32_t Channel)4121 __STATIC_INLINE void LL_DMA_EnableIT_ULE(const DMA_TypeDef *DMAx, uint32_t Channel)
4122 {
4123 uint32_t dma_base_addr = (uint32_t)DMAx;
4124 SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_ULEIE);
4125 }
4126
4127 /**
4128 * @brief Enable data transfer error interrupt.
4129 * @note This API is used for all available DMA channels.
4130 * @rmtoll CCR DTEIE LL_DMA_EnableIT_DTE
4131 * @param DMAx DMAx Instance
4132 * @param Channel This parameter can be one of the following values:
4133 * @arg @ref LL_DMA_CHANNEL_0
4134 * @arg @ref LL_DMA_CHANNEL_1
4135 * @arg @ref LL_DMA_CHANNEL_2
4136 * @arg @ref LL_DMA_CHANNEL_3
4137 * @arg @ref LL_DMA_CHANNEL_4
4138 * @arg @ref LL_DMA_CHANNEL_5
4139 * @arg @ref LL_DMA_CHANNEL_6
4140 * @arg @ref LL_DMA_CHANNEL_7
4141 * @retval None.
4142 */
LL_DMA_EnableIT_DTE(const DMA_TypeDef * DMAx,uint32_t Channel)4143 __STATIC_INLINE void LL_DMA_EnableIT_DTE(const DMA_TypeDef *DMAx, uint32_t Channel)
4144 {
4145 uint32_t dma_base_addr = (uint32_t)DMAx;
4146 SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_DTEIE);
4147 }
4148
4149 /**
4150 * @brief Enable half transfer complete interrupt.
4151 * @note This API is used for all available DMA channels.
4152 * @rmtoll CCR HTIE LL_DMA_EnableIT_HT
4153 * @param DMAx DMAx Instance
4154 * @param Channel This parameter can be one of the following values:
4155 * @arg @ref LL_DMA_CHANNEL_0
4156 * @arg @ref LL_DMA_CHANNEL_1
4157 * @arg @ref LL_DMA_CHANNEL_2
4158 * @arg @ref LL_DMA_CHANNEL_3
4159 * @arg @ref LL_DMA_CHANNEL_4
4160 * @arg @ref LL_DMA_CHANNEL_5
4161 * @arg @ref LL_DMA_CHANNEL_6
4162 * @arg @ref LL_DMA_CHANNEL_7
4163 * @retval None.
4164 */
LL_DMA_EnableIT_HT(const DMA_TypeDef * DMAx,uint32_t Channel)4165 __STATIC_INLINE void LL_DMA_EnableIT_HT(const DMA_TypeDef *DMAx, uint32_t Channel)
4166 {
4167 uint32_t dma_base_addr = (uint32_t)DMAx;
4168 SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_HTIE);
4169 }
4170
4171 /**
4172 * @brief Enable transfer complete interrupt.
4173 * @note This API is used for all available DMA channels.
4174 * @rmtoll CCR TCIE LL_DMA_EnableIT_TC
4175 * @param DMAx DMAx Instance
4176 * @param Channel This parameter can be one of the following values:
4177 * @arg @ref LL_DMA_CHANNEL_0
4178 * @arg @ref LL_DMA_CHANNEL_1
4179 * @arg @ref LL_DMA_CHANNEL_2
4180 * @arg @ref LL_DMA_CHANNEL_3
4181 * @arg @ref LL_DMA_CHANNEL_4
4182 * @arg @ref LL_DMA_CHANNEL_5
4183 * @arg @ref LL_DMA_CHANNEL_6
4184 * @arg @ref LL_DMA_CHANNEL_7
4185 * @retval None.
4186 */
LL_DMA_EnableIT_TC(const DMA_TypeDef * DMAx,uint32_t Channel)4187 __STATIC_INLINE void LL_DMA_EnableIT_TC(const DMA_TypeDef *DMAx, uint32_t Channel)
4188 {
4189 uint32_t dma_base_addr = (uint32_t)DMAx;
4190 SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_TCIE);
4191 }
4192
4193 /**
4194 * @brief Disable trigger overrun interrupt.
4195 * @note This API is used for all available DMA channels.
4196 * @rmtoll CCR TOIE LL_DMA_DisableIT_TO
4197 * @param DMAx DMAx Instance
4198 * @param Channel This parameter can be one of the following values:
4199 * @arg @ref LL_DMA_CHANNEL_0
4200 * @arg @ref LL_DMA_CHANNEL_1
4201 * @arg @ref LL_DMA_CHANNEL_2
4202 * @arg @ref LL_DMA_CHANNEL_3
4203 * @arg @ref LL_DMA_CHANNEL_4
4204 * @arg @ref LL_DMA_CHANNEL_5
4205 * @arg @ref LL_DMA_CHANNEL_6
4206 * @arg @ref LL_DMA_CHANNEL_7
4207 * @retval None.
4208 */
LL_DMA_DisableIT_TO(const DMA_TypeDef * DMAx,uint32_t Channel)4209 __STATIC_INLINE void LL_DMA_DisableIT_TO(const DMA_TypeDef *DMAx, uint32_t Channel)
4210 {
4211 uint32_t dma_base_addr = (uint32_t)DMAx;
4212 CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_TOIE);
4213 }
4214
4215 /**
4216 * @brief Disable suspension interrupt.
4217 * @note This API is used for all available DMA channels.
4218 * @rmtoll CCR SUSPIE LL_DMA_DisableIT_SUSP
4219 * @param DMAx DMAx Instance
4220 * @param Channel This parameter can be one of the following values:
4221 * @arg @ref LL_DMA_CHANNEL_0
4222 * @arg @ref LL_DMA_CHANNEL_1
4223 * @arg @ref LL_DMA_CHANNEL_2
4224 * @arg @ref LL_DMA_CHANNEL_3
4225 * @arg @ref LL_DMA_CHANNEL_4
4226 * @arg @ref LL_DMA_CHANNEL_5
4227 * @arg @ref LL_DMA_CHANNEL_6
4228 * @arg @ref LL_DMA_CHANNEL_7
4229 * @retval None.
4230 */
LL_DMA_DisableIT_SUSP(const DMA_TypeDef * DMAx,uint32_t Channel)4231 __STATIC_INLINE void LL_DMA_DisableIT_SUSP(const DMA_TypeDef *DMAx, uint32_t Channel)
4232 {
4233 uint32_t dma_base_addr = (uint32_t)DMAx;
4234 CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_SUSPIE);
4235 }
4236
4237 /**
4238 * @brief Disable user setting error interrupt.
4239 * @note This API is used for all available DMA channels.
4240 * @rmtoll CCR USEIE LL_DMA_DisableIT_USE
4241 * @param DMAx DMAx Instance
4242 * @param Channel This parameter can be one of the following values:
4243 * @arg @ref LL_DMA_CHANNEL_0
4244 * @arg @ref LL_DMA_CHANNEL_1
4245 * @arg @ref LL_DMA_CHANNEL_2
4246 * @arg @ref LL_DMA_CHANNEL_3
4247 * @arg @ref LL_DMA_CHANNEL_4
4248 * @arg @ref LL_DMA_CHANNEL_5
4249 * @arg @ref LL_DMA_CHANNEL_6
4250 * @arg @ref LL_DMA_CHANNEL_7
4251 * @retval None.
4252 */
LL_DMA_DisableIT_USE(const DMA_TypeDef * DMAx,uint32_t Channel)4253 __STATIC_INLINE void LL_DMA_DisableIT_USE(const DMA_TypeDef *DMAx, uint32_t Channel)
4254 {
4255 uint32_t dma_base_addr = (uint32_t)DMAx;
4256 CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_USEIE);
4257 }
4258
4259 /**
4260 * @brief Disable update link transfer error interrupt.
4261 * @note This API is used for all available DMA channels.
4262 * @rmtoll CCR ULEIE LL_DMA_DisableIT_ULE
4263 * @param DMAx DMAx Instance
4264 * @param Channel This parameter can be one of the following values:
4265 * @arg @ref LL_DMA_CHANNEL_0
4266 * @arg @ref LL_DMA_CHANNEL_1
4267 * @arg @ref LL_DMA_CHANNEL_2
4268 * @arg @ref LL_DMA_CHANNEL_3
4269 * @arg @ref LL_DMA_CHANNEL_4
4270 * @arg @ref LL_DMA_CHANNEL_5
4271 * @arg @ref LL_DMA_CHANNEL_6
4272 * @arg @ref LL_DMA_CHANNEL_7
4273 * @retval None.
4274 */
LL_DMA_DisableIT_ULE(const DMA_TypeDef * DMAx,uint32_t Channel)4275 __STATIC_INLINE void LL_DMA_DisableIT_ULE(const DMA_TypeDef *DMAx, uint32_t Channel)
4276 {
4277 uint32_t dma_base_addr = (uint32_t)DMAx;
4278 CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_ULEIE);
4279 }
4280
4281 /**
4282 * @brief Disable data transfer error interrupt.
4283 * @note This API is used for all available DMA channels.
4284 * @rmtoll CCR DTEIE LL_DMA_DisableIT_DTE
4285 * @param DMAx DMAx Instance
4286 * @param Channel This parameter can be one of the following values:
4287 * @arg @ref LL_DMA_CHANNEL_0
4288 * @arg @ref LL_DMA_CHANNEL_1
4289 * @arg @ref LL_DMA_CHANNEL_2
4290 * @arg @ref LL_DMA_CHANNEL_3
4291 * @arg @ref LL_DMA_CHANNEL_4
4292 * @arg @ref LL_DMA_CHANNEL_5
4293 * @arg @ref LL_DMA_CHANNEL_6
4294 * @arg @ref LL_DMA_CHANNEL_7
4295 * @retval None.
4296 */
LL_DMA_DisableIT_DTE(const DMA_TypeDef * DMAx,uint32_t Channel)4297 __STATIC_INLINE void LL_DMA_DisableIT_DTE(const DMA_TypeDef *DMAx, uint32_t Channel)
4298 {
4299 uint32_t dma_base_addr = (uint32_t)DMAx;
4300 CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_DTEIE);
4301 }
4302
4303 /**
4304 * @brief Disable half transfer complete interrupt.
4305 * @note This API is used for all available DMA channels.
4306 * @rmtoll CCR HTIE LL_DMA_DisableIT_HT
4307 * @param DMAx DMAx Instance
4308 * @param Channel This parameter can be one of the following values:
4309 * @arg @ref LL_DMA_CHANNEL_0
4310 * @arg @ref LL_DMA_CHANNEL_1
4311 * @arg @ref LL_DMA_CHANNEL_2
4312 * @arg @ref LL_DMA_CHANNEL_3
4313 * @arg @ref LL_DMA_CHANNEL_4
4314 * @arg @ref LL_DMA_CHANNEL_5
4315 * @arg @ref LL_DMA_CHANNEL_6
4316 * @arg @ref LL_DMA_CHANNEL_7
4317 * @retval None.
4318 */
LL_DMA_DisableIT_HT(const DMA_TypeDef * DMAx,uint32_t Channel)4319 __STATIC_INLINE void LL_DMA_DisableIT_HT(const DMA_TypeDef *DMAx, uint32_t Channel)
4320 {
4321 uint32_t dma_base_addr = (uint32_t)DMAx;
4322 CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_HTIE);
4323 }
4324
4325 /**
4326 * @brief Disable transfer complete interrupt.
4327 * @note This API is used for all available DMA channels.
4328 * @rmtoll CCR TCIE LL_DMA_DisableIT_TC
4329 * @param DMAx DMAx Instance
4330 * @param Channel This parameter can be one of the following values:
4331 * @arg @ref LL_DMA_CHANNEL_0
4332 * @arg @ref LL_DMA_CHANNEL_1
4333 * @arg @ref LL_DMA_CHANNEL_2
4334 * @arg @ref LL_DMA_CHANNEL_3
4335 * @arg @ref LL_DMA_CHANNEL_4
4336 * @arg @ref LL_DMA_CHANNEL_5
4337 * @arg @ref LL_DMA_CHANNEL_6
4338 * @arg @ref LL_DMA_CHANNEL_7
4339 * @retval None.
4340 */
LL_DMA_DisableIT_TC(const DMA_TypeDef * DMAx,uint32_t Channel)4341 __STATIC_INLINE void LL_DMA_DisableIT_TC(const DMA_TypeDef *DMAx, uint32_t Channel)
4342 {
4343 uint32_t dma_base_addr = (uint32_t)DMAx;
4344 CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_TCIE);
4345 }
4346
4347 /**
4348 * @brief Check if trigger overrun interrupt is enabled.
4349 * @note This API is used for all available DMA channels.
4350 * @rmtoll CCR TOIE LL_DMA_IsEnabledIT_TO
4351 * @param DMAx DMAx Instance
4352 * @param Channel This parameter can be one of the following values:
4353 * @arg @ref LL_DMA_CHANNEL_0
4354 * @arg @ref LL_DMA_CHANNEL_1
4355 * @arg @ref LL_DMA_CHANNEL_2
4356 * @arg @ref LL_DMA_CHANNEL_3
4357 * @arg @ref LL_DMA_CHANNEL_4
4358 * @arg @ref LL_DMA_CHANNEL_5
4359 * @arg @ref LL_DMA_CHANNEL_6
4360 * @arg @ref LL_DMA_CHANNEL_7
4361 * @retval State of bit (1 or 0).
4362 */
LL_DMA_IsEnabledIT_TO(const DMA_TypeDef * DMAx,uint32_t Channel)4363 __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TO(const DMA_TypeDef *DMAx, uint32_t Channel)
4364 {
4365 uint32_t dma_base_addr = (uint32_t)DMAx;
4366 return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_TOIE)
4367 == DMA_CCR_TOIE) ? 1UL : 0UL);
4368 }
4369
4370 /**
4371 * @brief Check if suspension interrupt is enabled.
4372 * @note This API is used for all available DMA channels.
4373 * @rmtoll CCR SUSPIE LL_DMA_IsEnabledIT_SUSP
4374 * @param DMAx DMAx Instance
4375 * @param Channel This parameter can be one of the following values:
4376 * @arg @ref LL_DMA_CHANNEL_0
4377 * @arg @ref LL_DMA_CHANNEL_1
4378 * @arg @ref LL_DMA_CHANNEL_2
4379 * @arg @ref LL_DMA_CHANNEL_3
4380 * @arg @ref LL_DMA_CHANNEL_4
4381 * @arg @ref LL_DMA_CHANNEL_5
4382 * @arg @ref LL_DMA_CHANNEL_6
4383 * @arg @ref LL_DMA_CHANNEL_7
4384 * @retval State of bit (1 or 0).
4385 */
LL_DMA_IsEnabledIT_SUSP(const DMA_TypeDef * DMAx,uint32_t Channel)4386 __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_SUSP(const DMA_TypeDef *DMAx, uint32_t Channel)
4387 {
4388 uint32_t dma_base_addr = (uint32_t)DMAx;
4389 return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_SUSPIE)
4390 == DMA_CCR_SUSPIE) ? 1UL : 0UL);
4391 }
4392
4393 /**
4394 * @brief Check if user setting error interrupt is enabled.
4395 * @note This API is used for all available DMA channels.
4396 * @rmtoll CCR USEIE LL_DMA_IsEnabledIT_USE
4397 * @param DMAx DMAx Instance
4398 * @param Channel This parameter can be one of the following values:
4399 * @arg @ref LL_DMA_CHANNEL_0
4400 * @arg @ref LL_DMA_CHANNEL_1
4401 * @arg @ref LL_DMA_CHANNEL_2
4402 * @arg @ref LL_DMA_CHANNEL_3
4403 * @arg @ref LL_DMA_CHANNEL_4
4404 * @arg @ref LL_DMA_CHANNEL_5
4405 * @arg @ref LL_DMA_CHANNEL_6
4406 * @arg @ref LL_DMA_CHANNEL_7
4407 * @retval State of bit (1 or 0).
4408 */
LL_DMA_IsEnabledIT_USE(const DMA_TypeDef * DMAx,uint32_t Channel)4409 __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_USE(const DMA_TypeDef *DMAx, uint32_t Channel)
4410 {
4411 uint32_t dma_base_addr = (uint32_t)DMAx;
4412 return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_USEIE)
4413 == DMA_CCR_USEIE) ? 1UL : 0UL);
4414 }
4415
4416 /**
4417 * @brief Check if update link transfer error interrupt is enabled.
4418 * @note This API is used for all available DMA channels.
4419 * @rmtoll CCR ULEIE LL_DMA_IsEnabledIT_ULE
4420 * @param DMAx DMAx Instance
4421 * @param Channel This parameter can be one of the following values:
4422 * @arg @ref LL_DMA_CHANNEL_0
4423 * @arg @ref LL_DMA_CHANNEL_1
4424 * @arg @ref LL_DMA_CHANNEL_2
4425 * @arg @ref LL_DMA_CHANNEL_3
4426 * @arg @ref LL_DMA_CHANNEL_4
4427 * @arg @ref LL_DMA_CHANNEL_5
4428 * @arg @ref LL_DMA_CHANNEL_6
4429 * @arg @ref LL_DMA_CHANNEL_7
4430 * @retval State of bit (1 or 0).
4431 */
LL_DMA_IsEnabledIT_ULE(const DMA_TypeDef * DMAx,uint32_t Channel)4432 __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_ULE(const DMA_TypeDef *DMAx, uint32_t Channel)
4433 {
4434 uint32_t dma_base_addr = (uint32_t)DMAx;
4435 return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_ULEIE)
4436 == DMA_CCR_ULEIE) ? 1UL : 0UL);
4437 }
4438
4439 /**
4440 * @brief Check if data transfer error interrupt is enabled.
4441 * @note This API is used for all available DMA channels.
4442 * @rmtoll CCR DTEIE LL_DMA_IsEnabledIT_DTE
4443 * @param DMAx DMAx Instance
4444 * @param Channel This parameter can be one of the following values:
4445 * @arg @ref LL_DMA_CHANNEL_0
4446 * @arg @ref LL_DMA_CHANNEL_1
4447 * @arg @ref LL_DMA_CHANNEL_2
4448 * @arg @ref LL_DMA_CHANNEL_3
4449 * @arg @ref LL_DMA_CHANNEL_4
4450 * @arg @ref LL_DMA_CHANNEL_5
4451 * @arg @ref LL_DMA_CHANNEL_6
4452 * @arg @ref LL_DMA_CHANNEL_7
4453 * @retval State of bit (1 or 0).
4454 */
LL_DMA_IsEnabledIT_DTE(const DMA_TypeDef * DMAx,uint32_t Channel)4455 __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_DTE(const DMA_TypeDef *DMAx, uint32_t Channel)
4456 {
4457 uint32_t dma_base_addr = (uint32_t)DMAx;
4458 return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_DTEIE)
4459 == DMA_CCR_DTEIE) ? 1UL : 0UL);
4460 }
4461
4462 /**
4463 * @brief Check if half transfer complete interrupt is enabled.
4464 * @note This API is used for all available DMA channels.
4465 * @rmtoll CCR HTIE LL_DMA_IsEnabledIT_HT
4466 * @param DMAx DMAx Instance
4467 * @param Channel This parameter can be one of the following values:
4468 * @arg @ref LL_DMA_CHANNEL_0
4469 * @arg @ref LL_DMA_CHANNEL_1
4470 * @arg @ref LL_DMA_CHANNEL_2
4471 * @arg @ref LL_DMA_CHANNEL_3
4472 * @arg @ref LL_DMA_CHANNEL_4
4473 * @arg @ref LL_DMA_CHANNEL_5
4474 * @arg @ref LL_DMA_CHANNEL_6
4475 * @arg @ref LL_DMA_CHANNEL_7
4476 * @retval State of bit (1 or 0).
4477 */
LL_DMA_IsEnabledIT_HT(const DMA_TypeDef * DMAx,uint32_t Channel)4478 __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_HT(const DMA_TypeDef *DMAx, uint32_t Channel)
4479 {
4480 uint32_t dma_base_addr = (uint32_t)DMAx;
4481 return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_HTIE)
4482 == DMA_CCR_HTIE) ? 1UL : 0UL);
4483 }
4484
4485 /**
4486 * @brief Check if transfer complete interrupt is enabled.
4487 * @note This API is used for all available DMA channels.
4488 * @rmtoll CCR TCIE LL_DMA_IsEnabledIT_TC
4489 * @param DMAx DMAx Instance
4490 * @param Channel This parameter can be one of the following values:
4491 * @arg @ref LL_DMA_CHANNEL_0
4492 * @arg @ref LL_DMA_CHANNEL_1
4493 * @arg @ref LL_DMA_CHANNEL_2
4494 * @arg @ref LL_DMA_CHANNEL_3
4495 * @arg @ref LL_DMA_CHANNEL_4
4496 * @arg @ref LL_DMA_CHANNEL_5
4497 * @arg @ref LL_DMA_CHANNEL_6
4498 * @arg @ref LL_DMA_CHANNEL_7
4499 * @retval State of bit (1 or 0).
4500 */
LL_DMA_IsEnabledIT_TC(const DMA_TypeDef * DMAx,uint32_t Channel)4501 __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TC(const DMA_TypeDef *DMAx, uint32_t Channel)
4502 {
4503 uint32_t dma_base_addr = (uint32_t)DMAx;
4504 return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_TCIE)
4505 == DMA_CCR_TCIE) ? 1UL : 0UL);
4506 }
4507 /**
4508 * @}
4509 */
4510
4511 #if defined (USE_FULL_LL_DRIVER)
4512 /** @defgroup DMA_LL_EF_Init Initialization and de-initialization functions
4513 * @{
4514 */
4515 uint32_t LL_DMA_Init(DMA_TypeDef *DMAx, uint32_t Channel, LL_DMA_InitTypeDef *DMA_InitStruct);
4516 uint32_t LL_DMA_DeInit(DMA_TypeDef *DMAx, uint32_t Channel);
4517
4518 void LL_DMA_StructInit(LL_DMA_InitTypeDef *DMA_InitStruct);
4519 void LL_DMA_ListStructInit(LL_DMA_InitLinkedListTypeDef *DMA_InitLinkedListStruct);
4520 void LL_DMA_NodeStructInit(LL_DMA_InitNodeTypeDef *DMA_InitNodeStruct);
4521
4522 uint32_t LL_DMA_List_Init(DMA_TypeDef *DMAx, uint32_t Channel,
4523 LL_DMA_InitLinkedListTypeDef *DMA_InitLinkedListStruct);
4524 uint32_t LL_DMA_List_DeInit(DMA_TypeDef *DMAx, uint32_t Channel);
4525
4526 uint32_t LL_DMA_CreateLinkNode(LL_DMA_InitNodeTypeDef *DMA_InitNodeStruct, LL_DMA_LinkNodeTypeDef *pNode);
4527 void LL_DMA_ConnectLinkNode(LL_DMA_LinkNodeTypeDef *pPrevLinkNode, uint32_t PrevNodeCLLRIdx,
4528 LL_DMA_LinkNodeTypeDef *pNewLinkNode, uint32_t NewNodeCLLRIdx);
4529 void LL_DMA_DisconnectNextLinkNode(LL_DMA_LinkNodeTypeDef *pLinkNode, uint32_t LinkNodeCLLRIdx);
4530 /**
4531 * @}
4532 */
4533 #endif /* defined (USE_FULL_LL_DRIVER) */
4534
4535 /**
4536 * @}
4537 */
4538
4539 /**
4540 * @}
4541 */
4542
4543 #endif /* defined (GPDMA1) */
4544
4545 /**
4546 * @}
4547 */
4548
4549 #ifdef __cplusplus
4550 }
4551 #endif /* __cplusplus */
4552
4553 #endif /* STM32WBAxx_LL_DMA_H */
4554
4555
