1 /**
2 ******************************************************************************
3 * @file stm32h5xx_ll_dma.h
4 * @author MCD Application Team
5 * @brief Header file of DMA LL module.
6 ******************************************************************************
7 * @attention
8 *
9 * Copyright (c) 2022 STMicroelectronics.
10 * All rights reserved.
11 *
12 * This software is licensed under terms that can be found in the LICENSE file
13 * in the root directory of this software component.
14 * If no LICENSE file comes with this software, it is provided AS-IS.
15 *
16 ******************************************************************************
17 @verbatim
18 ==============================================================================
19 ##### LL DMA driver acronyms #####
20 ==============================================================================
21 [..] Acronyms table :
22 =========================================
23 || Acronym || ||
24 =========================================
25 || SRC || Source ||
26 || DEST || Destination ||
27 || ADDR || Address ||
28 || ADDRS || Addresses ||
29 || INC || Increment / Incremented ||
30 || DEC || Decrement / Decremented ||
31 || BLK || Block ||
32 || RPT || Repeat / Repeated ||
33 || TRIG || Trigger ||
34 =========================================
35 @endverbatim
36 ******************************************************************************
37 */
38
39 /* Define to prevent recursive inclusion -------------------------------------*/
40 #ifndef STM32H5xx_LL_DMA_H
41 #define STM32H5xx_LL_DMA_H
42
43 #ifdef __cplusplus
44 extern "C" {
45 #endif /* __cplusplus */
46
47 /* Includes ------------------------------------------------------------------*/
48 #include "stm32h5xx.h"
49
50 /** @addtogroup STM32H5xx_LL_Driver
51 * @{
52 */
53
54 #if defined (GPDMA1)
55
56 /** @defgroup DMA_LL DMA
57 * @{
58 */
59
60 /* Private types -------------------------------------------------------------*/
61 /* Private variables ---------------------------------------------------------*/
62
63 /** @defgroup DMA_LL_Private_Variables DMA Private Variables
64 * @{
65 */
66 #define DMA_CHANNEL0_OFFSET (0x00000050UL)
67 #define DMA_CHANNEL1_OFFSET (0x000000D0UL)
68 #define DMA_CHANNEL2_OFFSET (0x00000150UL)
69 #define DMA_CHANNEL3_OFFSET (0x000001D0UL)
70 #define DMA_CHANNEL4_OFFSET (0x00000250UL)
71 #define DMA_CHANNEL5_OFFSET (0x000002D0UL)
72 #define DMA_CHANNEL6_OFFSET (0x00000350UL)
73 #define DMA_CHANNEL7_OFFSET (0x000003D0UL)
74 #define DMA_CHANNEL8_OFFSET (0x00000450UL)
75 #define DMA_CHANNEL9_OFFSET (0x000004D0UL)
76 #define DMA_CHANNEL10_OFFSET (0x00000550UL)
77 #define DMA_CHANNEL11_OFFSET (0x000005D0UL)
78 #define DMA_CHANNEL12_OFFSET (0x00000650UL)
79 #define DMA_CHANNEL13_OFFSET (0x000006D0UL)
80 #define DMA_CHANNEL14_OFFSET (0x00000750UL)
81 #define DMA_CHANNEL15_OFFSET (0x000007D0UL)
82
83 /* Array used to get the DMA Channel register offset versus Channel index LL_DMA_CHANNEL_x */
84 static const uint32_t LL_DMA_CH_OFFSET_TAB[] =
85 {
86 DMA_CHANNEL0_OFFSET, DMA_CHANNEL1_OFFSET, DMA_CHANNEL2_OFFSET, DMA_CHANNEL3_OFFSET,
87 DMA_CHANNEL4_OFFSET, DMA_CHANNEL5_OFFSET, DMA_CHANNEL6_OFFSET, DMA_CHANNEL7_OFFSET,
88 DMA_CHANNEL8_OFFSET, DMA_CHANNEL9_OFFSET, DMA_CHANNEL10_OFFSET, DMA_CHANNEL11_OFFSET,
89 DMA_CHANNEL12_OFFSET, DMA_CHANNEL13_OFFSET, DMA_CHANNEL14_OFFSET, DMA_CHANNEL15_OFFSET,
90 };
91 /**
92 * @}
93 */
94
95 /* Private constants ---------------------------------------------------------*/
96 /* Private macros ------------------------------------------------------------*/
97 /* Exported types ------------------------------------------------------------*/
98
99 #if defined (USE_FULL_LL_DRIVER)
100 /** @defgroup DMA_LL_ES_INIT DMA Exported Init structure
101 * @{
102 */
103
104 /**
105 * @brief LL DMA init structure definition.
106 */
107 typedef struct
108 {
109 uint32_t SrcAddress; /*!< This field specify the data transfer source address.
110 Programming this field is mandatory for all available DMA channels.
111 This parameter must be a value between Min_Data = 0 and Max_Data = 0xFFFFFFFF.
112 This feature can be modified afterwards using unitary function
113 @ref LL_DMA_SetSrcAddress(). */
114
115 uint32_t DestAddress; /*!< This field specify the data transfer destination address.
116 Programming this field is mandatory for all available DMA channels.
117 This parameter must be a value between Min_Data = 0 and Max_Data = 0xFFFFFFFF.
118 This feature can be modified afterwards using unitary function
119 @ref LL_DMA_SetDestAddress(). */
120
121 uint32_t Direction; /*!< This field specify the data transfer direction.
122 Programming this field is mandatory for all available DMA channels.
123 This parameter can be a value of @ref DMA_LL_EC_TRANSFER_DIRECTION.
124 This feature can be modified afterwards using unitary function
125 @ref LL_DMA_SetDataTransferDirection(). */
126
127 uint32_t BlkHWRequest; /*!< This field specify the hardware request unity.
128 Programming this field is mandatory for all available DMA channels.
129 This parameter can be a value of @ref DMA_LL_EC_BLKHW_REQUEST.
130 This feature can be modified afterwards using unitary function
131 @ref LL_DMA_SetBlkHWRequest(). */
132
133 uint32_t DataAlignment; /*!< This field specify the transfer data alignment.
134 Programming this field is mandatory for all available DMA channels.
135 This parameter can be a value of @ref DMA_LL_EC_DATA_ALIGNMENT.
136 This feature can be modified afterwards using unitary function
137 @ref LL_DMA_SetDataAlignment(). */
138
139 uint32_t SrcBurstLength; /*!< This field specify the source burst length of transfer in bytes.
140 Programming this field is not mandatory for LPDMA channels.
141 This parameter must be a value between Min_Data = 1 and Max_Data = 64.
142 This feature can be modified afterwards using unitary function
143 @ref LL_DMA_SetSrcBurstLength(). */
144
145 uint32_t DestBurstLength; /*!< This field specify the destination burst length of transfer in bytes.
146 Programming this field is not mandatory for LPDMA channels.
147 This parameter must be a value between Min_Data = 1 and Max_Data = 64.
148 This feature can be modified afterwards using unitary function
149 @ref LL_DMA_SetDestBurstLength(). */
150
151 uint32_t SrcDataWidth; /*!< This field specify the source data width.
152 Programming this field is mandatory for all available DMA channels.
153 This parameter can be a value of @ref DMA_LL_EC_SOURCE_DATA_WIDTH.
154 This feature can be modified afterwards using unitary function
155 @ref LL_DMA_SetSrcDataWidth(). */
156
157 uint32_t DestDataWidth; /*!< This field specify the destination data width.
158 Programming this field is mandatory for all available DMA channels.
159 This parameter can be a value of @ref DMA_LL_EC_DESTINATION_DATA_WIDTH.
160 This feature can be modified afterwards using unitary function
161 @ref LL_DMA_SetDestDataWidth(). */
162
163 uint32_t SrcIncMode; /*!< This field specify the source burst increment mode.
164 Programming this field is mandatory for all available DMA channels.
165 This parameter can be a value of @ref DMA_LL_EC_SOURCE_INCREMENT_MODE.
166 This feature can be modified afterwards using unitary function
167 @ref LL_DMA_SetSrcIncMode(). */
168
169 uint32_t DestIncMode; /*!< This field specify the destination burst increment mode.
170 Programming this field is mandatory for all available DMA channels.
171 This parameter can be a value of @ref DMA_LL_EC_DESTINATION_INCREMENT_MODE.
172 This feature can be modified afterwards using unitary function
173 @ref LL_DMA_SetDestIncMode(). */
174
175 uint32_t Priority; /*!< This field specify the channel priority level.
176 Programming this field is mandatory for all available DMA channels.
177 This parameter can be a value of @ref DMA_LL_EC_PRIORITY_LEVEL.
178 This feature can be modified afterwards using unitary function
179 @ref LL_DMA_SetChannelPriorityLevel(). */
180
181 uint32_t BlkDataLength; /*!< This field specify the length of a block transfer in bytes.
182 Programming this field is mandatory for all available DMA channels.
183 This parameter must be a value between Min_Data = 0 and Max_Data = 0x0000FFFF.
184 This feature can be modified afterwards using unitary function
185 @ref LL_DMA_SetBlkDataLength(). */
186
187 uint32_t BlkRptCount; /*!< This field specify the number of repetitions of the current block.
188 Programming this field is mandatory only for 2D addressing channels.
189 This parameter can be a value between 1 and 2048 Min_Data = 0
190 and Max_Data = 0x000007FF.
191 This feature can be modified afterwards using unitary function
192 @ref LL_DMA_SetBlkRptCount(). */
193
194 uint32_t TriggerMode; /*!< This field specify the trigger mode.
195 Programming this field is mandatory for all available DMA channels.
196 This parameter can be a value of @ref DMA_LL_EC_TRIGGER_MODE.
197 This feature can be modified afterwards using unitary function
198 @ref LL_DMA_SetTriggerMode(). */
199
200 uint32_t TriggerPolarity; /*!< This field specify the trigger event polarity.
201 Programming this field is mandatory for all available DMA channels.
202 This parameter can be a value of @ref DMA_LL_EC_TRIGGER_POLARITY.
203 This feature can be modified afterwards using unitary function
204 @ref LL_DMA_SetTriggerPolarity(). */
205
206 uint32_t TriggerSelection; /*!< This field specify the trigger event selection.
207 Programming this field is mandatory for all available DMA channels.
208 This parameter can be a value of @ref DMA_LL_EC_TRIGGER_SELECTION.
209 This feature can be modified afterwards using unitary function
210 @ref LL_DMA_SetHWTrigger(). */
211
212 uint32_t Request; /*!< This field specify the peripheral request selection.
213 Programming this field is mandatory for all available DMA channels.
214 This parameter can be a value of @ref DMA_LL_EC_REQUEST_SELECTION.
215 This feature can be modified afterwards using unitary function
216 @ref LL_DMA_SetPeriphRequest(). */
217
218 uint32_t TransferEventMode; /*!< This field specify the transfer event mode.
219 Programming this field is mandatory for all available DMA channels.
220 This parameter can be a value of @ref DMA_LL_EC_TRANSFER_EVENT_MODE.
221 This feature can be modified afterwards using unitary function
222 @ref LL_DMA_SetTransferEventMode(). */
223
224 uint32_t DestHWordExchange; /*!< This field specify the destination half word exchange.
225 Programming this field is not mandatory for LPDMA channels.
226 This parameter can be a value of @ref DMA_LL_EC_DEST_HALFWORD_EXCHANGE.
227 This feature can be modified afterwards using unitary function
228 @ref LL_DMA_SetDestHWordExchange(). */
229
230 uint32_t DestByteExchange; /*!< This field specify the destination byte exchange.
231 Programming this field is not mandatory for LPDMA channels.
232 This parameter can be a value of @ref DMA_LL_EC_DEST_BYTE_EXCHANGE.
233 This feature can be modified afterwards using unitary function
234 @ref LL_DMA_SetDestByteExchange(). */
235
236 uint32_t SrcByteExchange; /*!< This field specify the source byte exchange.
237 Programming this field is not mandatory for LPDMA channels.
238 This parameter can be a value of @ref DMA_LL_EC_SRC_BYTE_EXCHANGE.
239 This feature can be modified afterwards using unitary function
240 @ref LL_DMA_SetSrcByteExchange(). */
241
242 uint32_t SrcAllocatedPort; /*!< This field specify the source allocated port.
243 Programming this field is not mandatory for LPDMA channels.
244 This parameter can be a value of @ref DMA_LL_EC_SOURCE_ALLOCATED_PORT.
245 This feature can be modified afterwards using unitary function
246 @ref LL_DMA_SetSrcAllocatedPort(). */
247
248 uint32_t DestAllocatedPort; /*!< This field specify the destination allocated port.
249 Programming this field is not mandatory for LPDMA channels.
250 This parameter can be a value of @ref DMA_LL_EC_DESTINATION_ALLOCATED_PORT.
251 This feature can be modified afterwards using unitary function
252 @ref LL_DMA_SetDestAllocatedPort(). */
253
254 uint32_t LinkAllocatedPort; /*!< This field specify the linked-list allocated port.
255 Programming this field is not mandatory for LPDMA channels.
256 This parameter can be a value of @ref DMA_LL_EC_LINKED_LIST_ALLOCATED_PORT.
257 This feature can be modified afterwards using unitary function
258 @ref LL_DMA_SetLinkAllocatedPort(). */
259
260 uint32_t LinkStepMode; /*!< This field specify the link step mode.
261 Programming this field is mandatory for all available DMA channels.
262 This parameter can be a value of @ref DMA_LL_EC_LINK_STEP_MODE.
263 This feature can be modified afterwards using unitary function
264 @ref LL_DMA_SetLinkStepMode(). */
265
266 uint32_t SrcAddrUpdateMode; /*!< This field specify the source address update mode.
267 Programming this field is mandatory only for 2D addressing channels.
268 This parameter can be a value of @ref DMA_LL_EC_SRC_ADDR_UPDATE_MODE.
269 This feature can be modified afterwards using unitary function
270 @ref LL_DMA_SetSrcAddrUpdate(). */
271
272 uint32_t DestAddrUpdateMode; /*!< This field specify the destination address update mode.
273 Programming this field is mandatory only for 2D addressing channels.
274 This parameter can be a value of @ref DMA_LL_EC_DEST_ADDR_UPDATE_MODE.
275 This feature can be modified afterwards using unitary function
276 @ref LL_DMA_SetDestAddrUpdate(). */
277
278 uint32_t SrcAddrOffset; /*!< This field specifies the source address offset.
279 Programming this field is mandatory only for 2D addressing channels.
280 This parameter can be a value Between 0 to 0x00001FFF.
281 This feature can be modified afterwards using unitary function
282 @ref LL_DMA_SetSrcAddrUpdateValue(). */
283
284 uint32_t DestAddrOffset; /*!< This field specifies the destination address offset.
285 Programming this field is mandatory only for 2D addressing channels.
286 This parameter can be a value Between 0 to 0x00001FFF.
287 This feature can be modified afterwards using unitary function
288 @ref LL_DMA_SetDestAddrUpdateValue(). */
289
290 uint32_t BlkRptSrcAddrUpdateMode; /*!< This field specifies the block repeat source address update mode.
291 Programming this field is mandatory only for 2D addressing channels.
292 This parameter can be a value of @ref DMA_LL_EC_BLK_RPT_SRC_ADDR_UPDATE_MODE.
293 This feature can be modified afterwards using unitary function
294 @ref LL_DMA_SetBlkRptSrcAddrUpdate(). */
295
296 uint32_t BlkRptDestAddrUpdateMode; /*!< This field specifies the block repeat destination address update mode.
297 Programming this field is mandatory only for 2D addressing channels.
298 This parameter can be a value of @ref DMA_LL_EC_BLK_RPT_DEST_ADDR_UPDATE_MODE.
299 This feature can be modified afterwards using unitary function
300 @ref LL_DMA_SetBlkRptDestAddrUpdate(). */
301
302 uint32_t BlkRptSrcAddrOffset; /*!< This field specifies the block repeat source address offset.
303 Programming this field is mandatory only for 2D addressing channels.
304 This parameter can be a value Between 0 to 0x0000FFFF.
305 This feature can be modified afterwards using unitary function
306 @ref LL_DMA_SetBlkRptSrcAddrUpdateValue(). */
307
308 uint32_t BlkRptDestAddrOffset; /*!< This field specifies the block repeat destination address offset.
309 Programming this field is mandatory only for 2D addressing channels.
310 This parameter can be a value Between 0 to 0x0000FFFF.
311 This feature can be modified afterwards using unitary function
312 @ref LL_DMA_SetBlkRptDestAddrUpdateValue(). */
313
314 uint32_t LinkedListBaseAddr; /*!< This field specify the linked list base address.
315 Programming this field is mandatory for all available DMA channels.
316 This parameter can be a value Between 0 to 0xFFFF0000 (where the 4 first
317 bytes are always forced to 0).
318 This feature can be modified afterwards using unitary function
319 @ref LL_DMA_SetLinkedListBaseAddr(). */
320
321 uint32_t LinkedListAddrOffset; /*!< Specifies the linked list address offset.
322 Programming this field is mandatory for all available DMA channels.
323 This parameter can be a value Between 0 to 0x0000FFFC.
324 This feature can be modified afterwards using unitary function
325 @ref LL_DMA_SetLinkedListAddrOffset(). */
326 } LL_DMA_InitTypeDef;
327
328
329 /**
330 * @brief LL DMA init linked list structure definition.
331 */
332 typedef struct
333 {
334 uint32_t Priority; /*!< This field specify the channel priority level.
335 Programming this field is mandatory for all available DMA channels.
336 This parameter can be a value of @ref DMA_LL_EC_PRIORITY_LEVEL.
337 This feature can be modified afterwards using unitary function
338 @ref LL_DMA_SetChannelPriorityLevel(). */
339
340 uint32_t LinkStepMode; /*!< This field specify the link step mode.
341 Programming this field is mandatory for all available DMA channels.
342 This parameter can be a value of @ref DMA_LL_EC_LINK_STEP_MODE.
343 This feature can be modified afterwards using unitary function
344 @ref LL_DMA_SetLinkStepMode(). */
345
346 uint32_t LinkAllocatedPort; /*!< This field specify the linked-list allocated port.
347 Programming this field is not mandatory for LPDMA channels.
348 This parameter can be a value of @ref DMA_LL_EC_LINKED_LIST_ALLOCATED_PORT.
349 This feature can be modified afterwards using unitary function
350 @ref LL_DMA_SetLinkAllocatedPort(). */
351
352 uint32_t TransferEventMode; /*!< This field specify the transfer event mode.
353 Programming this field is mandatory for all available DMA channels.
354 This parameter can be a value of @ref DMA_LL_EC_TRANSFER_EVENT_MODE.
355 This feature can be modified afterwards using unitary function
356 @ref LL_DMA_SetTransferEventMode(). */
357 } LL_DMA_InitLinkedListTypeDef;
358
359
360 /**
361 * @brief LL DMA node init structure definition.
362 */
363 typedef struct
364 {
365 /* CTR1 register fields ******************************************************
366 If any CTR1 fields need to be updated comparing to previous node, it is
367 mandatory to update the new value in CTR1 register fields and enable update
368 CTR1 register in UpdateRegisters fields if it is not enabled in the
369 previous node.
370
371 If the node to be created is for LPDMA channels, there is no need to fill
372 the following fields for CTR1 register :
373 - DestAllocatedPort.
374 - DestHWordExchange.
375 - DestByteExchange.
376 - DestBurstLength.
377 - SrcAllocatedPort.
378 - SrcByteExchange.
379 - SrcBurstLength.
380 */
381 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
382 uint32_t DestSecure; /*!< This field specify the destination secure.
383 This parameter can be a value of @ref DMA_LL_EC_DESTINATION_SECURITY_ATTRIBUTE. */
384 #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
385
386 uint32_t DestAllocatedPort; /*!< This field specify the destination allocated port.
387 This parameter can be a value of @ref DMA_LL_EC_DESTINATION_ALLOCATED_PORT. */
388
389 uint32_t DestHWordExchange; /*!< This field specify the destination half word exchange.
390 This parameter can be a value of @ref DMA_LL_EC_DEST_HALFWORD_EXCHANGE. */
391
392 uint32_t DestByteExchange; /*!< This field specify the destination byte exchange.
393 This parameter can be a value of @ref DMA_LL_EC_DEST_BYTE_EXCHANGE. */
394
395 uint32_t DestBurstLength; /*!< This field specify the destination burst length of transfer in bytes.
396 This parameter must be a value between Min_Data = 1 and Max_Data = 64. */
397
398 uint32_t DestIncMode; /*!< This field specify the destination increment mode.
399 This parameter can be a value of @ref DMA_LL_EC_DESTINATION_INCREMENT_MODE. */
400
401 uint32_t DestDataWidth; /*!< This field specify the destination data width.
402 This parameter can be a value of @ref DMA_LL_EC_DESTINATION_DATA_WIDTH. */
403
404 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
405 uint32_t SrcSecure; /*!< This field specify the source secure.
406 This parameter can be a value of @ref DMA_LL_EC_SOURCE_SECURITY_ATTRIBUTE. */
407 #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
408
409 uint32_t SrcAllocatedPort; /*!< This field specify the source allocated port.
410 This parameter can be a value of @ref DMA_LL_EC_SOURCE_ALLOCATED_PORT. */
411
412 uint32_t SrcByteExchange; /*!< This field specify the source byte exchange.
413 This parameter can be a value of @ref DMA_LL_EC_SRC_BYTE_EXCHANGE. */
414
415 uint32_t DataAlignment; /*!< This field specify the transfer data alignment.
416 This parameter can be a value of @ref DMA_LL_EC_DATA_ALIGNMENT. */
417
418 uint32_t SrcBurstLength; /*!< This field specify the source burst length of transfer in bytes.
419 This parameter must be a value between Min_Data = 1 and Max_Data = 64. */
420
421 uint32_t SrcIncMode; /*!< This field specify the source increment mode.
422 This parameter can be a value of @ref DMA_LL_EC_SOURCE_INCREMENT_MODE. */
423
424 uint32_t SrcDataWidth; /*!< This field specify the source data width.
425 This parameter can be a value of @ref DMA_LL_EC_SOURCE_DATA_WIDTH. */
426
427
428 /* CTR2 register fields ******************************************************
429 If any CTR2 fields need to be updated comparing to previous node, it is
430 mandatory to update the new value in CTR2 register fields and enable update
431 CTR2 register in UpdateRegisters fields if it is not enabled in the
432 previous node.
433
434 For all node created, filling all fields is mandatory.
435 */
436 uint32_t TransferEventMode; /*!< This field specify the transfer event mode.
437 This parameter can be a value of @ref DMA_LL_EC_TRANSFER_EVENT_MODE. */
438
439 uint32_t TriggerPolarity; /*!< This field specify the trigger event polarity.
440 This parameter can be a value of @ref DMA_LL_EC_TRIGGER_POLARITY. */
441
442 uint32_t TriggerSelection; /*!< This field specify the trigger event selection.
443 This parameter can be a value of @ref DMA_LL_EC_TRIGGER_SELECTION. */
444
445 uint32_t TriggerMode; /*!< This field specify the trigger mode.
446 This parameter can be a value of @ref DMA_LL_EC_TRIGGER_MODE. */
447
448 uint32_t BlkHWRequest; /*!< This field specify the hardware request unity.
449 This parameter can be a value of @ref DMA_LL_EC_BLKHW_REQUEST. */
450
451 uint32_t Direction; /*!< This field specify the transfer direction.
452 This parameter can be a value of @ref DMA_LL_EC_TRANSFER_DIRECTION. */
453
454 uint32_t Request; /*!< This field specify the peripheral request selection.
455 This parameter can be a value of @ref DMA_LL_EC_REQUEST_SELECTION. */
456
457
458 /* CBR1 register fields ******************************************************
459 If any CBR1 fields need to be updated comparing to previous node, it is
460 mandatory to update the new value in CBR1 register fields and enable update
461 CBR1 register in UpdateRegisters fields if it is not enabled in the
462 previous node.
463
464 If the node to be created is not for 2D addressing channels, there is no
465 need to fill the following fields for CBR1 register :
466 - BlkReptDestAddrUpdate.
467 - BlkRptSrcAddrUpdate.
468 - DestAddrUpdate.
469 - SrcAddrUpdate.
470 - BlkRptCount.
471 */
472 uint32_t BlkRptDestAddrUpdateMode; /*!< This field specifies the block repeat destination address update mode.
473 This parameter can be a value of
474 @ref DMA_LL_EC_BLK_RPT_DEST_ADDR_UPDATE_MODE. */
475
476 uint32_t BlkRptSrcAddrUpdateMode; /*!< This field specifies the block repeat source address update mode.
477 This parameter can be a value of
478 @ref DMA_LL_EC_BLK_RPT_SRC_ADDR_UPDATE_MODE. */
479
480 uint32_t DestAddrUpdateMode; /*!< This field specify the Destination address update mode.
481 This parameter can be a value of @ref DMA_LL_EC_DEST_ADDR_UPDATE_MODE. */
482
483 uint32_t SrcAddrUpdateMode; /*!< This field specify the Source address update mode.
484 This parameter can be a value of @ref DMA_LL_EC_SRC_ADDR_UPDATE_MODE. */
485
486 uint32_t BlkRptCount; /*!< This field specify the number of repetitions of the current block.
487 This parameter can be a value between 1 and 2048 Min_Data = 0
488 and Max_Data = 0x000007FF. */
489
490 uint32_t BlkDataLength; /*!< This field specify the length of a block transfer in bytes.
491 This parameter must be a value between Min_Data = 0
492 and Max_Data = 0x0000FFFF. */
493
494
495 /* CSAR register fields ******************************************************
496 If any CSAR fields need to be updated comparing to previous node, it is
497 mandatory to update the new value in CSAR register fields and enable update
498 CSAR register in UpdateRegisters fields if it is not enabled in the
499 previous node.
500
501 For all node created, filling all fields is mandatory.
502 */
503 uint32_t SrcAddress; /*!< This field specify the transfer source address.
504 This parameter must be a value between Min_Data = 0
505 and Max_Data = 0xFFFFFFFF. */
506
507
508 /* CDAR register fields ******************************************************
509 If any CDAR fields need to be updated comparing to previous node, it is
510 mandatory to update the new value in CDAR register fields and enable update
511 CDAR register in UpdateRegisters fields if it is not enabled in the
512 previous node.
513
514 For all node created, filling all fields is mandatory.
515 */
516 uint32_t DestAddress; /*!< This field specify the transfer destination address.
517 This parameter must be a value between Min_Data = 0
518 and Max_Data = 0xFFFFFFFF. */
519
520
521 /* CTR3 register fields ******************************************************
522 If any CTR3 fields need to be updated comparing to previous node, it is
523 mandatory to update the new value in CTR3 register fields and enable update
524 CTR3 register in UpdateRegisters fields if it is not enabled in the
525 previous node.
526
527 This register is used only for 2D addressing channels.
528 If used channel is linear addressing, this register will be overwritten by
529 CLLR register in memory.
530 When this register is enabled on UpdateRegisters and the selected channel
531 is linear addressing, LL APIs will discard this register update in memory.
532 */
533 uint32_t DestAddrOffset; /*!< This field specifies the destination address offset.
534 This parameter can be a value Between 0 to 0x00001FFF. */
535
536 uint32_t SrcAddrOffset; /*!< This field specifies the source address offset.
537 This parameter can be a value Between 0 to 0x00001FFF. */
538
539
540 /* CBR2 register fields ******************************************************
541 If any CBR2 fields need to be updated comparing to previous node, it is
542 mandatory to update the new value in CBR2 register fields and enable update
543 CBR2 register in UpdateRegisters fields if it is not enabled in the
544 previous node.
545
546 This register is used only for 2D addressing channels.
547 If used channel is linear addressing, this register will be discarded in
548 memory. When this register is enabled on UpdateRegisters and the selected
549 channel is linear addressing, LL APIs will discard this register update in
550 memory.
551 */
552 uint32_t BlkRptDestAddrOffset; /*!< This field specifies the block repeat destination address offset.
553 This parameter can be a value Between 0 to 0x0000FFFF. */
554
555 uint32_t BlkRptSrcAddrOffset; /*!< This field specifies the block repeat source address offset.
556 This parameter can be a value Between 0 to 0x0000FFFF. */
557
558
559 /* CLLR register fields ******************************************************
560 If any CLLR fields need to be updated comparing to previous node, it is
561 mandatory to update the new value in CLLR register fields and enable update
562 CLLR register in UpdateRegisters fields if it is not enabled in the
563 previous node.
564
565 If used channel is linear addressing, there is no need to enable/disable
566 CTR3 and CBR2 register in UpdateRegisters fields as they will be discarded
567 by LL APIs.
568 */
569 uint32_t UpdateRegisters; /*!< Specifies the linked list register update.
570 This parameter can be a value of @ref DMA_LL_EC_LINKEDLIST_REGISTER_UPDATE. */
571
572 /* DMA Node type field *******************************************************
573 This parameter defines node types as node size and node content varies
574 between channels.
575 Thanks to this fields, linked list queue could be created independently
576 from channel selection. So, one queue could be executed by all DMA channels.
577 */
578 uint32_t NodeType; /*!< Specifies the node type to be created.
579 This parameter can be a value of @ref DMA_LL_EC_LINKEDLIST_NODE_TYPE. */
580 } LL_DMA_InitNodeTypeDef;
581
582 /**
583 * @brief LL DMA linked list node structure definition.
584 * @note For 2D addressing channels, the maximum node size is :
585 * (4 Bytes * 8 registers = 32 Bytes).
586 * For GPDMA linear addressing channels, the maximum node size is :
587 * (4 Bytes * 6 registers = 24 Bytes).
588 * For LPDMA linear addressing channels, the maximum node size is :
589 * (4 Bytes * 6 registers = 24 Bytes).
590 */
591 typedef struct
592 {
593 __IO uint32_t LinkRegisters[8];
594
595 } LL_DMA_LinkNodeTypeDef;
596 /**
597 * @}
598 */
599
600 #endif /* defined (USE_FULL_LL_DRIVER) */
601
602 /* Exported constants --------------------------------------------------------*/
603
604 /** @defgroup DMA_LL_Exported_Constants DMA Exported Constants
605 * @{
606 */
607
608 /** @defgroup DMA_LL_EC_CHANNEL Channel
609 * @{
610 */
611 #define LL_DMA_CHANNEL_0 (0x00U)
612 #define LL_DMA_CHANNEL_1 (0x01U)
613 #define LL_DMA_CHANNEL_2 (0x02U)
614 #define LL_DMA_CHANNEL_3 (0x03U)
615 #define LL_DMA_CHANNEL_4 (0x04U)
616 #define LL_DMA_CHANNEL_5 (0x05U)
617 #define LL_DMA_CHANNEL_6 (0x06U)
618 #define LL_DMA_CHANNEL_7 (0x07U)
619 #define LL_DMA_CHANNEL_8 (0x08U)
620 #define LL_DMA_CHANNEL_9 (0x09U)
621 #define LL_DMA_CHANNEL_10 (0x0AU)
622 #define LL_DMA_CHANNEL_11 (0x0BU)
623 #define LL_DMA_CHANNEL_12 (0x0CU)
624 #define LL_DMA_CHANNEL_13 (0x0DU)
625 #define LL_DMA_CHANNEL_14 (0x0EU)
626 #define LL_DMA_CHANNEL_15 (0x0FU)
627 #if defined (USE_FULL_LL_DRIVER)
628 #define LL_DMA_CHANNEL_ALL (0x10U)
629 #endif /* defined (USE_FULL_LL_DRIVER) */
630 /**
631 * @}
632 */
633
634 #if defined (USE_FULL_LL_DRIVER)
635 /** @defgroup DMA_LL_EC_CLLR_OFFSET CLLR offset
636 * @{
637 */
638 #define LL_DMA_CLLR_OFFSET0 (0x00U)
639 #define LL_DMA_CLLR_OFFSET1 (0x01U)
640 #define LL_DMA_CLLR_OFFSET2 (0x02U)
641 #define LL_DMA_CLLR_OFFSET3 (0x03U)
642 #define LL_DMA_CLLR_OFFSET4 (0x04U)
643 #define LL_DMA_CLLR_OFFSET5 (0x05U)
644 #define LL_DMA_CLLR_OFFSET6 (0x06U)
645 #define LL_DMA_CLLR_OFFSET7 (0x07U)
646 /**
647 * @}
648 */
649 #endif /* defined (USE_FULL_LL_DRIVER) */
650
651 /** @defgroup DMA_LL_EC_PRIORITY_LEVEL Priority Level
652 * @{
653 */
654 #define LL_DMA_LOW_PRIORITY_LOW_WEIGHT 0x00000000U /*!< Priority level : Low Priority, Low Weight */
655 #define LL_DMA_LOW_PRIORITY_MID_WEIGHT DMA_CCR_PRIO_0 /*!< Priority level : Low Priority, Mid Weight */
656 #define LL_DMA_LOW_PRIORITY_HIGH_WEIGHT DMA_CCR_PRIO_1 /*!< Priority level : Low Priority, High Weight */
657 #define LL_DMA_HIGH_PRIORITY DMA_CCR_PRIO /*!< Priority level : High Priority */
658 /**
659 * @}
660 */
661
662 /** @defgroup DMA_LL_EC_LINKED_LIST_ALLOCATED_PORT Linked List Allocated Port
663 * @{
664 */
665 #define LL_DMA_LINK_ALLOCATED_PORT0 0x00000000U /*!< Linked List Allocated Port 0 */
666 #define LL_DMA_LINK_ALLOCATED_PORT1 DMA_CCR_LAP /*!< Linked List Allocated Port 1 */
667 /**
668 * @}
669 */
670
671 /** @defgroup DMA_LL_EC_LINK_STEP_MODE Link Step Mode
672 * @{
673 */
674 #define LL_DMA_LSM_FULL_EXECUTION 0x00000000U /*!< Channel execute the full linked list */
675 #define LL_DMA_LSM_1LINK_EXECUTION DMA_CCR_LSM /*!< Channel execute one node of the linked list */
676 /**
677 * @}
678 */
679
680 /** @defgroup DMA_LL_EC_DEST_HALFWORD_EXCHANGE Destination Half-Word Exchange
681 * @{
682 */
683 #define LL_DMA_DEST_HALFWORD_PRESERVE 0x00000000U /*!< No destinatiion Half-Word exchange when destination data width
684 is word */
685 #define LL_DMA_DEST_HALFWORD_EXCHANGE DMA_CTR1_DHX /*!< Destinatiion Half-Word exchange when destination data width
686 is word */
687 /**
688 * @}
689 */
690
691 /** @defgroup DMA_LL_EC_DEST_BYTE_EXCHANGE Destination Byte Exchange
692 * @{
693 */
694 #define LL_DMA_DEST_BYTE_PRESERVE 0x00000000U /*!< No destination Byte exchange when destination data width > Byte */
695 #define LL_DMA_DEST_BYTE_EXCHANGE DMA_CTR1_DBX /*!< Destination Byte exchange when destination data width > Byte */
696 /**
697 * @}
698 */
699
700 /** @defgroup DMA_LL_EC_SRC_BYTE_EXCHANGE Source Byte Exchange
701 * @{
702 */
703 #define LL_DMA_SRC_BYTE_PRESERVE 0x00000000U /*!< No source Byte exchange when source data width is word */
704 #define LL_DMA_SRC_BYTE_EXCHANGE DMA_CTR1_SBX /*!< Source Byte exchange when source data width is word */
705 /**
706 * @}
707 */
708
709 /** @defgroup DMA_LL_EC_SOURCE_ALLOCATED_PORT Source Allocated Port
710 * @{
711 */
712 #define LL_DMA_SRC_ALLOCATED_PORT0 0x00000000U /*!< Source Allocated Port 0 */
713 #define LL_DMA_SRC_ALLOCATED_PORT1 DMA_CTR1_SAP /*!< Source Allocated Port 1 */
714 /**
715 * @}
716 */
717
718 /** @defgroup DMA_LL_EC_DESTINATION_ALLOCATED_PORT Destination Allocated Port
719 * @{
720 */
721 #define LL_DMA_DEST_ALLOCATED_PORT0 0x00000000U /*!< Destination Allocated Port 0 */
722 #define LL_DMA_DEST_ALLOCATED_PORT1 DMA_CTR1_DAP /*!< Destination Allocated Port 1 */
723 /**
724 * @}
725 */
726
727 /** @defgroup DMA_LL_EC_DESTINATION_INCREMENT_MODE Destination Increment Mode
728 * @{
729 */
730 #define LL_DMA_DEST_FIXED 0x00000000U /*!< Destination fixed single/burst */
731 #define LL_DMA_DEST_INCREMENT DMA_CTR1_DINC /*!< Destination incremented single/burst */
732 /**
733 * @}
734 */
735
736 /** @defgroup DMA_LL_EC_DESTINATION_DATA_WIDTH Destination Data Width
737 * @{
738 */
739 #define LL_DMA_DEST_DATAWIDTH_BYTE 0x00000000U /*!< Destination Data Width : Byte */
740 #define LL_DMA_DEST_DATAWIDTH_HALFWORD DMA_CTR1_DDW_LOG2_0 /*!< Destination Data Width : HalfWord */
741 #define LL_DMA_DEST_DATAWIDTH_WORD DMA_CTR1_DDW_LOG2_1 /*!< Destination Data Width : Word */
742 /**
743 * @}
744 */
745
746 /** @defgroup DMA_LL_EC_DATA_ALIGNMENT Data Alignment
747 * @{
748 */
749 #define LL_DMA_DATA_ALIGN_ZEROPADD 0x00000000U /*!< If src data width < dest data width :
750 => Right Aligned padded with 0 up to destination
751 data width.
752 If src data width > dest data width :
753 => Right Aligned Left Truncated down to destination
754 data width. */
755 #define LL_DMA_DATA_ALIGN_SIGNEXTPADD DMA_CTR1_PAM_0 /*!< If src data width < dest data width :
756 => Right Aligned padded with sign extended up to destination
757 data width.
758 If src data width > dest data width :
759 => Left Aligned Right Truncated down to the destination
760 data width */
761 #define LL_DMA_DATA_PACK_UNPACK DMA_CTR1_PAM_1 /*!< If src data width < dest data width :
762 => Packed at the destination data width (Not Available
763 for LPDMA)
764 If src data width > dest data width :
765 => Unpacked at the destination data width (Not Available
766 for LPDMA) */
767 /**
768 * @}
769 */
770
771 /** @defgroup DMA_LL_EC_SOURCE_INCREMENT_MODE Source Increment Mode
772 * @{
773 */
774 #define LL_DMA_SRC_FIXED 0x00000000U /*!< Source fixed single/burst */
775 #define LL_DMA_SRC_INCREMENT DMA_CTR1_SINC /*!< Source incremented single/burst */
776 /**
777 * @}
778 */
779
780 /** @defgroup DMA_LL_EC_SOURCE_DATA_WIDTH Source Data Width
781 * @{
782 */
783 #define LL_DMA_SRC_DATAWIDTH_BYTE 0x00000000U /*!< Source Data Width : Byte */
784 #define LL_DMA_SRC_DATAWIDTH_HALFWORD DMA_CTR1_SDW_LOG2_0 /*!< Source Data Width : HalfWord */
785 #define LL_DMA_SRC_DATAWIDTH_WORD DMA_CTR1_SDW_LOG2_1 /*!< Source Data Width : Word */
786 /**
787 * @}
788 */
789
790 /** @defgroup DMA_LL_EC_BLKHW_REQUEST Block Hardware Request
791 * @{
792 */
793 #define LL_DMA_HWREQUEST_SINGLEBURST 0x00000000U /*!< Hardware request is driven by a peripheral with a hardware
794 request/acknowledge protocol at a burst level */
795 #define LL_DMA_HWREQUEST_BLK DMA_CTR2_BREQ /*!< Hardware request is driven by a peripheral with a hardware
796 request/acknowledge protocol at a block level */
797 /**
798 * @}
799 */
800
801 /** @defgroup DMA_LL_EC_TRANSFER_EVENT_MODE Transfer Event Mode
802 * @{
803 */
804 #define LL_DMA_TCEM_BLK_TRANSFER 0x00000000U /*!< The TC (and the HT) event is generated at the
805 (respectively half) end of each block */
806 #define LL_DMA_TCEM_RPT_BLK_TRANSFER DMA_CTR2_TCEM_0 /*!< The TC (and the HT) event is generated at the
807 (respectively half) end of the repeated block */
808 #define LL_DMA_TCEM_EACH_LLITEM_TRANSFER DMA_CTR2_TCEM_1 /*!< The TC (and the HT) event is generated at the
809 (respectively half) end of each linked-list item */
810 #define LL_DMA_TCEM_LAST_LLITEM_TRANSFER DMA_CTR2_TCEM /*!< The TC (and the HT) event is generated at the
811 (respectively half) end of the last linked-list item */
812 /**
813 * @}
814 */
815
816 /** @defgroup DMA_LL_EC_TRIGGER_POLARITY Trigger Polarity
817 * @{
818 */
819 #define LL_DMA_TRIG_POLARITY_MASKED 0x00000000U /*!< No trigger of the selected DMA request.
820 Masked trigger event */
821 #define LL_DMA_TRIG_POLARITY_RISING DMA_CTR2_TRIGPOL_0 /*!< Trigger of the selected DMA request on the rising
822 edge of the selected trigger event input */
823 #define LL_DMA_TRIG_POLARITY_FALLING DMA_CTR2_TRIGPOL_1 /*!< Trigger of the selected DMA request on the falling
824 edge of the selected trigger event input */
825 /**
826 * @}
827 */
828
829 /** @defgroup DMA_LL_EC_TRIGGER_MODE Transfer Trigger Mode
830 * @{
831 */
832 #define LL_DMA_TRIGM_BLK_TRANSFER 0x00000000U /*!< A block transfer is conditioned by (at least)
833 one hit trigger */
834 #define LL_DMA_TRIGM_RPT_BLK_TRANSFER DMA_CTR2_TRIGM_0 /*!< A repeated block transfer is conditioned by (at least)
835 one hit trigger */
836 #define LL_DMA_TRIGM_LLI_LINK_TRANSFER DMA_CTR2_TRIGM_1 /*!< A LLI link transfer is conditioned by (at least)
837 one hit trigger */
838 #define LL_DMA_TRIGM_SINGLBURST_TRANSFER DMA_CTR2_TRIGM /*!< A Single/Burst transfer is conditioned by (at least)
839 one hit trigger */
840 /**
841 * @}
842 */
843
844 /** @defgroup DMA_LL_EC_TRANSFER_DIRECTION Transfer Direction
845 * @{
846 */
847 #define LL_DMA_DIRECTION_MEMORY_TO_MEMORY DMA_CTR2_SWREQ /*!< Memory to memory direction */
848 #define LL_DMA_DIRECTION_PERIPH_TO_MEMORY 0x00000000U /*!< Peripheral to memory direction */
849 #define LL_DMA_DIRECTION_MEMORY_TO_PERIPH DMA_CTR2_DREQ /*!< Memory to peripheral direction */
850 /**
851 * @}
852 */
853
854 /** @defgroup DMA_LL_EC_BLK_RPT_SRC_ADDR_UPDATE_MODE Block Repeat Source Address Update Mode
855 * @{
856 */
857 #define LL_DMA_BLKRPT_SRC_ADDR_INCREMENT 0x00000000U /*!< Source address pointer is incremented after each block
858 transfer by source update value */
859 #define LL_DMA_BLKRPT_SRC_ADDR_DECREMENT DMA_CBR1_BRSDEC /*!< Source address pointer is decremented after each block
860 transfer by source update value */
861 /**
862 * @}
863 */
864
865 /** @defgroup DMA_LL_EC_BLK_RPT_DEST_ADDR_UPDATE_MODE Block Repeat Destination Address Update Mode
866 * @{
867 */
868 #define LL_DMA_BLKRPT_DEST_ADDR_INCREMENT 0x00000000U /*!< Destination address is incremented after each block
869 transfer by destination update value */
870 #define LL_DMA_BLKRPT_DEST_ADDR_DECREMENT DMA_CBR1_BRDDEC /*!< Destination address is decremented after each block
871 transfer by destination update value */
872 /**
873 * @}
874 */
875
876 /** @defgroup DMA_LL_EC_SRC_ADDR_UPDATE_MODE Burst Source Address Update Mode
877 * @{
878 */
879 #define LL_DMA_BURST_SRC_ADDR_INCREMENT 0x00000000U /*!< Source address pointer is incremented after each burst
880 transfer by source update value */
881 #define LL_DMA_BURST_SRC_ADDR_DECREMENT DMA_CBR1_SDEC /*!< Source address pointer is decremented after each burst
882 transfer by source update value */
883 /**
884 * @}
885 */
886
887 /** @defgroup DMA_LL_EC_DEST_ADDR_UPDATE_MODE Burst Destination Address Update Mode
888 * @{
889 */
890 #define LL_DMA_BURST_DEST_ADDR_INCREMENT 0x00000000U /*!< Destination address pointer is incremented after each
891 burst transfer by destination update value */
892 #define LL_DMA_BURST_DEST_ADDR_DECREMENT DMA_CBR1_DDEC /*!< Destination address pointer is decremented after each
893 burst transfer by destination update value */
894 /**
895 * @}
896 */
897
898 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
899 /** @defgroup DMA_LL_EC_SOURCE_SECURITY_ATTRIBUTE Source Security Attribute
900 * @{
901 */
902 #define LL_DMA_CHANNEL_NSEC 0x00000000U /*!< NSecure channel */
903 #define LL_DMA_CHANNEL_SEC 0x00000001U /*!< Secure channel */
904 /**
905 * @}
906 */
907
908 /** @defgroup DMA_LL_EC_SOURCE_SECURITY_ATTRIBUTE Source Security Attribute
909 * @{
910 */
911 #define LL_DMA_CHANNEL_SRC_NSEC 0x00000000U /*!< NSecure transfer from the source */
912 #define LL_DMA_CHANNEL_SRC_SEC DMA_CTR1_SSEC /*!< Secure transfer from the source */
913 /**
914 * @}
915 */
916
917 /** @defgroup DMA_LL_EC_DESTINATION_SECURITY_ATTRIBUTE Destination Security Attribute
918 * @{
919 */
920 #define LL_DMA_CHANNEL_DEST_NSEC 0x00000000U /*!< NSecure transfer from the destination */
921 #define LL_DMA_CHANNEL_DEST_SEC DMA_CTR1_DSEC /*!< Secure transfer from the destination */
922 /**
923 * @}
924 */
925 #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
926
927 /** @defgroup DMA_LL_EC_LINKEDLIST_NODE_TYPE Linked list node type
928 * @{
929 */
930 #define LL_DMA_GPDMA_LINEAR_NODE 0x01U /*!< GPDMA node : linear addressing node */
931 #define LL_DMA_GPDMA_2D_NODE 0x02U /*!< GPDMA node : 2 dimension addressing node */
932
933 /**
934 * @}
935 */
936
937 /** @defgroup DMA_LL_EC_LINKEDLIST_REGISTER_UPDATE Linked list register update
938 * @{
939 */
940 #define LL_DMA_UPDATE_CTR1 DMA_CLLR_UT1 /*!< Update CTR1 register from memory :
941 available for all DMA channels */
942 #define LL_DMA_UPDATE_CTR2 DMA_CLLR_UT2 /*!< Update CTR2 register from memory :
943 available for all DMA channels */
944 #define LL_DMA_UPDATE_CBR1 DMA_CLLR_UB1 /*!< Update CBR1 register from memory :
945 available for all DMA channels */
946 #define LL_DMA_UPDATE_CSAR DMA_CLLR_USA /*!< Update CSAR register from memory :
947 available for all DMA channels */
948 #define LL_DMA_UPDATE_CDAR DMA_CLLR_UDA /*!< Update CDAR register from memory :
949 available for all DMA channels */
950 #define LL_DMA_UPDATE_CTR3 DMA_CLLR_UT3 /*!< Update CTR3 register from memory :
951 available only for 2D addressing DMA channels */
952 #define LL_DMA_UPDATE_CBR2 DMA_CLLR_UB2 /*!< Update CBR2 register from memory :
953 available only for 2D addressing DMA channels */
954 #define LL_DMA_UPDATE_CLLR DMA_CLLR_ULL /*!< Update CLLR register from memory :
955 available for all DMA channels */
956 /**
957 * @}
958 */
959
960 /** @defgroup DMA_LL_EC_REQUEST_SELECTION Request Selection
961 * @{
962 */
963 /* GPDMA1 Hardware Requests */
964 #define LL_GPDMA1_REQUEST_ADC1 0U /*!< GPDMA1 HW request is ADC1 */
965 #if defined (ADC2)
966 #define LL_GPDMA1_REQUEST_ADC2 1U /*!< GPDMA1 HW request is ADC2 */
967 #endif /* ADC2 */
968 #define LL_GPDMA1_REQUEST_DAC1_CH1 2U /*!< GPDMA1 HW request is DAC1_CH1 */
969 #define LL_GPDMA1_REQUEST_DAC1_CH2 3U /*!< GPDMA1 HW request is DAC1_CH2 */
970 #define LL_GPDMA1_REQUEST_TIM6_UP 4U /*!< GPDMA1 HW request is TIM6_UP */
971 #define LL_GPDMA1_REQUEST_TIM7_UP 5U /*!< GPDMA1 HW request is TIM7_UP */
972 #define LL_GPDMA1_REQUEST_SPI1_RX 6U /*!< GPDMA1 HW request is SPI1_RX */
973 #define LL_GPDMA1_REQUEST_SPI1_TX 7U /*!< GPDMA1 HW request is SPI1_TX */
974 #define LL_GPDMA1_REQUEST_SPI2_RX 8U /*!< GPDMA1 HW request is SPI2_RX */
975 #define LL_GPDMA1_REQUEST_SPI2_TX 9U /*!< GPDMA1 HW request is SPI2_TX */
976 #define LL_GPDMA1_REQUEST_SPI3_RX 10U /*!< GPDMA1 HW request is SPI3_RX */
977 #define LL_GPDMA1_REQUEST_SPI3_TX 11U /*!< GPDMA1 HW request is SPI3_TX */
978 #define LL_GPDMA1_REQUEST_I2C1_RX 12U /*!< GPDMA1 HW request is I2C1_RX */
979 #define LL_GPDMA1_REQUEST_I2C1_TX 13U /*!< GPDMA1 HW request is I2C1_TX */
980 #define LL_GPDMA1_REQUEST_I2C2_RX 15U /*!< GPDMA1 HW request is I2C2_RX */
981 #define LL_GPDMA1_REQUEST_I2C2_TX 16U /*!< GPDMA1 HW request is I2C2_TX */
982 #if defined (I2C3)
983 #define LL_GPDMA1_REQUEST_I2C3_RX 18U /*!< GPDMA1 HW request is I2C3_RX */
984 #define LL_GPDMA1_REQUEST_I2C3_TX 19U /*!< GPDMA1 HW request is I2C3_TX */
985 #endif /* I2C3 */
986 #define LL_GPDMA1_REQUEST_USART1_RX 21U /*!< GPDMA1 HW request is USART1_RX */
987 #define LL_GPDMA1_REQUEST_USART1_TX 22U /*!< GPDMA1 HW request is USART1_TX */
988 #define LL_GPDMA1_REQUEST_USART2_RX 23U /*!< GPDMA1 HW request is USART2_RX */
989 #define LL_GPDMA1_REQUEST_USART2_TX 24U /*!< GPDMA1 HW request is USART2_TX */
990 #define LL_GPDMA1_REQUEST_USART3_RX 25U /*!< GPDMA1 HW request is USART3_RX */
991 #define LL_GPDMA1_REQUEST_USART3_TX 26U /*!< GPDMA1 HW request is USART3_TX */
992 #if defined (UART4)
993 #define LL_GPDMA1_REQUEST_UART4_RX 27U /*!< GPDMA1 HW request is UART4_RX */
994 #define LL_GPDMA1_REQUEST_UART4_TX 28U /*!< GPDMA1 HW request is UART4_TX */
995 #endif /* UART4 */
996 #if defined (UART4)
997 #define LL_GPDMA1_REQUEST_UART5_RX 29U /*!< GPDMA1 HW request is UART5_RX */
998 #define LL_GPDMA1_REQUEST_UART5_TX 30U /*!< GPDMA1 HW request is UART5_TX */
999 #endif /* UART5 */
1000 #if defined (UART4)
1001 #define LL_GPDMA1_REQUEST_USART6_RX 31U /*!< GPDMA1 HW request is USART6_RX */
1002 #define LL_GPDMA1_REQUEST_USART6_TX 32U /*!< GPDMA1 HW request is USART6_TX */
1003 #endif /* USART6 */
1004 #if defined (UART7)
1005 #define LL_GPDMA1_REQUEST_UART7_RX 33U /*!< GPDMA1 HW request is UART7_RX */
1006 #define LL_GPDMA1_REQUEST_UART7_TX 34U /*!< GPDMA1 HW request is UART7_TX */
1007 #endif /* UART7 */
1008 #if defined (UART8)
1009 #define LL_GPDMA1_REQUEST_UART8_RX 35U /*!< GPDMA1 HW request is UART8_RX */
1010 #define LL_GPDMA1_REQUEST_UART8_TX 36U /*!< GPDMA1 HW request is UART8_TX */
1011 #endif /* UART8 */
1012 #if defined (UART9)
1013 #define LL_GPDMA1_REQUEST_UART9_RX 37U /*!< GPDMA1 HW request is UART9_RX */
1014 #define LL_GPDMA1_REQUEST_UART9_TX 38U /*!< GPDMA1 HW request is UART9_TX */
1015 #endif /* UART9 */
1016 #if defined (USART10)
1017 #define LL_GPDMA1_REQUEST_USART10_RX 39U /*!< GPDMA1 HW request is USART10_RX */
1018 #define LL_GPDMA1_REQUEST_USART10_TX 40U /*!< GPDMA1 HW request is USART10_TX */
1019 #endif /* USART10 */
1020 #if defined (USART11)
1021 #define LL_GPDMA1_REQUEST_USART11_RX 41U /*!< GPDMA1 HW request is USART11_RX */
1022 #define LL_GPDMA1_REQUEST_USART11_TX 42U /*!< GPDMA1 HW request is USART11_TX */
1023 #endif /* USART11 */
1024 #if defined (UART12)
1025 #define LL_GPDMA1_REQUEST_UART12_RX 43U /*!< GPDMA1 HW request is UART12_RX */
1026 #define LL_GPDMA1_REQUEST_UART12_TX 44U /*!< GPDMA1 HW request is UART12_TX */
1027 #endif /* UART12 */
1028 #define LL_GPDMA1_REQUEST_LPUART1_RX 45U /*!< GPDMA1 HW request is LPUART1_RX */
1029 #define LL_GPDMA1_REQUEST_LPUART1_TX 46U /*!< GPDMA1 HW request is LPUART1_TX */
1030 #if defined (SPI4)
1031 #define LL_GPDMA1_REQUEST_SPI4_RX 47U /*!< GPDMA1 HW request is SPI4_RX */
1032 #define LL_GPDMA1_REQUEST_SPI4_TX 48U /*!< GPDMA1 HW request is SPI4_TX */
1033 #endif /* SPI4 */
1034 #if defined (SPI5)
1035 #define LL_GPDMA1_REQUEST_SPI5_RX 49U /*!< GPDMA1 HW request is SPI5_RX */
1036 #define LL_GPDMA1_REQUEST_SPI5_TX 50U /*!< GPDMA1 HW request is SPI5_TX */
1037 #endif /* SPI5 */
1038 #if defined (SPI6)
1039 #define LL_GPDMA1_REQUEST_SPI6_RX 51U /*!< GPDMA1 HW request is SPI6_RX */
1040 #define LL_GPDMA1_REQUEST_SPI6_TX 52U /*!< GPDMA1 HW request is SPI6_TX */
1041 #endif /* SPI6 */
1042 #if defined (SAI1)
1043 #define LL_GPDMA1_REQUEST_SAI1_A 53U /*!< GPDMA1 HW request is SAI1_A */
1044 #define LL_GPDMA1_REQUEST_SAI1_B 54U /*!< GPDMA1 HW request is SAI1_B */
1045 #endif /* SAI1 */
1046 #if defined (SAI2)
1047 #define LL_GPDMA1_REQUEST_SAI2_A 55U /*!< GPDMA1 HW request is SAI2_A */
1048 #define LL_GPDMA1_REQUEST_SAI2_B 56U /*!< GPDMA1 HW request is SAI2_B */
1049 #endif /* SAI2 */
1050 #if defined (OCTOSPI1)
1051 #define LL_GPDMA1_REQUEST_OCTOSPI1 57U /*!< GPDMA1 HW request is OCTOSPI1 */
1052 #endif /* OCTOSPI1 */
1053 #define LL_GPDMA1_REQUEST_TIM1_CH1 58U /*!< GPDMA1 HW request is TIM1_CH1 */
1054 #define LL_GPDMA1_REQUEST_TIM1_CH2 59U /*!< GPDMA1 HW request is TIM1_CH2 */
1055 #define LL_GPDMA1_REQUEST_TIM1_CH3 60U /*!< GPDMA1 HW request is TIM1_CH3 */
1056 #define LL_GPDMA1_REQUEST_TIM1_CH4 61U /*!< GPDMA1 HW request is TIM1_CH4 */
1057 #define LL_GPDMA1_REQUEST_TIM1_UP 62U /*!< GPDMA1 HW request is TIM1_UP */
1058 #define LL_GPDMA1_REQUEST_TIM1_TRIG 63U /*!< GPDMA1 HW request is TIM1_TRIG */
1059 #define LL_GPDMA1_REQUEST_TIM1_COM 64U /*!< GPDMA1 HW request is TIM1_COM */
1060 #if defined (TIM8)
1061 #define LL_GPDMA1_REQUEST_TIM8_CH1 65U /*!< GPDMA1 HW request is TIM8_CH1 */
1062 #define LL_GPDMA1_REQUEST_TIM8_CH2 66U /*!< GPDMA1 HW request is TIM8_CH2 */
1063 #define LL_GPDMA1_REQUEST_TIM8_CH3 67U /*!< GPDMA1 HW request is TIM8_CH3 */
1064 #define LL_GPDMA1_REQUEST_TIM8_CH4 68U /*!< GPDMA1 HW request is TIM8_CH4 */
1065 #define LL_GPDMA1_REQUEST_TIM8_UP 69U /*!< GPDMA1 HW request is TIM8_UP */
1066 #define LL_GPDMA1_REQUEST_TIM8_TRIG 70U /*!< GPDMA1 HW request is TIM8_TRIG */
1067 #define LL_GPDMA1_REQUEST_TIM8_COM 71U /*!< GPDMA1 HW request is TIM8_COM */
1068 #endif /* TIM8 */
1069 #define LL_GPDMA1_REQUEST_TIM2_CH1 72U /*!< GPDMA1 HW request is TIM2_CH1 */
1070 #define LL_GPDMA1_REQUEST_TIM2_CH2 73U /*!< GPDMA1 HW request is TIM2_CH2 */
1071 #define LL_GPDMA1_REQUEST_TIM2_CH3 74U /*!< GPDMA1 HW request is TIM2_CH3 */
1072 #define LL_GPDMA1_REQUEST_TIM2_CH4 75U /*!< GPDMA1 HW request is TIM2_CH4 */
1073 #define LL_GPDMA1_REQUEST_TIM2_UP 76U /*!< GPDMA1 HW request is TIM2_UP */
1074 #define LL_GPDMA1_REQUEST_TIM3_CH1 77U /*!< GPDMA1 HW request is TIM3_CH1 */
1075 #define LL_GPDMA1_REQUEST_TIM3_CH2 78U /*!< GPDMA1 HW request is TIM3_CH2 */
1076 #define LL_GPDMA1_REQUEST_TIM3_CH3 79U /*!< GPDMA1 HW request is TIM3_CH3 */
1077 #define LL_GPDMA1_REQUEST_TIM3_CH4 80U /*!< GPDMA1 HW request is TIM3_CH4 */
1078 #define LL_GPDMA1_REQUEST_TIM3_UP 81U /*!< GPDMA1 HW request is TIM3_UP */
1079 #define LL_GPDMA1_REQUEST_TIM3_TRIG 82U /*!< GPDMA1 HW request is TIM3_TRIG */
1080 #if defined (TIM4)
1081 #define LL_GPDMA1_REQUEST_TIM4_CH1 83U /*!< GPDMA1 HW request is TIM4_CH1 */
1082 #define LL_GPDMA1_REQUEST_TIM4_CH2 84U /*!< GPDMA1 HW request is TIM4_CH2 */
1083 #define LL_GPDMA1_REQUEST_TIM4_CH3 85U /*!< GPDMA1 HW request is TIM4_CH3 */
1084 #define LL_GPDMA1_REQUEST_TIM4_CH4 86U /*!< GPDMA1 HW request is TIM4_CH4 */
1085 #define LL_GPDMA1_REQUEST_TIM4_UP 87U /*!< GPDMA1 HW request is TIM4_UP */
1086 #endif /* TIM4 */
1087 #if defined (TIM5)
1088 #define LL_GPDMA1_REQUEST_TIM5_CH1 88U /*!< GPDMA1 HW request is TIM5_CH1 */
1089 #define LL_GPDMA1_REQUEST_TIM5_CH2 89U /*!< GPDMA1 HW request is TIM5_CH2 */
1090 #define LL_GPDMA1_REQUEST_TIM5_CH3 90U /*!< GPDMA1 HW request is TIM5_CH3 */
1091 #define LL_GPDMA1_REQUEST_TIM5_CH4 91U /*!< GPDMA1 HW request is TIM5_CH4 */
1092 #define LL_GPDMA1_REQUEST_TIM5_UP 92U /*!< GPDMA1 HW request is TIM5_UP */
1093 #define LL_GPDMA1_REQUEST_TIM5_TRIG 93U /*!< GPDMA1 HW request is TIM5_TRIG */
1094 #endif /* TIM5 */
1095 #if defined (TIM15)
1096 #define LL_GPDMA1_REQUEST_TIM15_CH1 94U /*!< GPDMA1 HW request is TIM15_CH1 */
1097 #define LL_GPDMA1_REQUEST_TIM15_UP 95U /*!< GPDMA1 HW request is TIM15_UP */
1098 #define LL_GPDMA1_REQUEST_TIM15_TRIG 96U /*!< GPDMA1 HW request is TIM15_TRIG */
1099 #define LL_GPDMA1_REQUEST_TIM15_COM 97U /*!< GPDMA1 HW request is TIM15_COM */
1100 #endif /* TIM15 */
1101 #if defined (TIM16)
1102 #define LL_GPDMA1_REQUEST_TIM16_CH1 98U /*!< GPDMA1 HW request is TIM16_CH1 */
1103 #define LL_GPDMA1_REQUEST_TIM16_UP 99U /*!< GPDMA1 HW request is TIM16_UP */
1104 #endif /* TIM16 */
1105 #if defined (TIM17)
1106 #define LL_GPDMA1_REQUEST_TIM17_CH1 100U /*!< GPDMA1 HW request is TIM17_CH1 */
1107 #define LL_GPDMA1_REQUEST_TIM17_UP 101U /*!< GPDMA1 HW request is TIM17_UP */
1108 #endif /* TIM17 */
1109 #define LL_GPDMA1_REQUEST_LPTIM1_IC1 102U /*!< GPDMA1 HW request is LPTIM1_IC1 */
1110 #define LL_GPDMA1_REQUEST_LPTIM1_IC2 103U /*!< GPDMA1 HW request is LPTIM1_IC2 */
1111 #define LL_GPDMA1_REQUEST_LPTIM1_UE 104U /*!< GPDMA1 HW request is LPTIM1_UE */
1112 #define LL_GPDMA1_REQUEST_LPTIM2_IC1 105U /*!< GPDMA1 HW request is LPTIM2_IC1 */
1113 #define LL_GPDMA1_REQUEST_LPTIM2_IC2 106U /*!< GPDMA1 HW request is LPTIM2_IC2 */
1114 #define LL_GPDMA1_REQUEST_LPTIM2_UE 107U /*!< GPDMA1 HW request is LPTIM2_UE */
1115 #if defined (DCMI)
1116 #define LL_GPDMA1_REQUEST_DCMI 108U /*!< GPDMA1 HW request is DCMI */
1117 #endif /* DCMI */
1118 #if defined (AES)
1119 #define LL_GPDMA1_REQUEST_AES_OUT 109U /*!< GPDMA1 HW request is AES_OUT */
1120 #define LL_GPDMA1_REQUEST_AES_IN 110U /*!< GPDMA1 HW request is AES_IN */
1121 #endif /* AES */
1122 #define LL_GPDMA1_REQUEST_HASH_IN 111U /*!< GPDMA1 HW request is HASH_IN */
1123 #if defined (UCPD1)
1124 #define LL_GPDMA1_REQUEST_UCPD1_RX 112U /*!< GPDMA1 HW request is UCPD1_RX */
1125 #define LL_GPDMA1_REQUEST_UCPD1_TX 113U /*!< GPDMA1 HW request is UCPD1_TX */
1126 #endif /* UCPD1 */
1127 #if defined (CORDIC)
1128 #define LL_GPDMA1_REQUEST_CORDIC_READ 114U /*!< GPDMA1 HW request is CORDIC_READ */
1129 #define LL_GPDMA1_REQUEST_CORDIC_WRITE 115U /*!< GPDMA1 HW request is CORDIC_WRITE */
1130 #endif /* CORDIC */
1131 #if defined (FMAC)
1132 #define LL_GPDMA1_REQUEST_FMAC_READ 116U /*!< GPDMA1 HW request is FMAC_READ */
1133 #define LL_GPDMA1_REQUEST_FMAC_WRITE 117U /*!< GPDMA1 HW request is FMAC_WRITE */
1134 #endif /* FMAC */
1135 #if defined (SAES)
1136 #define LL_GPDMA1_REQUEST_SAES_OUT 118U /*!< GPDMA1 HW request is SAES_OUT */
1137 #define LL_GPDMA1_REQUEST_SAES_IN 119U /*!< GPDMA1 HW request is SAES_IN */
1138 #endif /* SAES */
1139 #define LL_GPDMA1_REQUEST_I3C1_RX 120U /*!< GPDMA1 HW request is I3C1_RX */
1140 #define LL_GPDMA1_REQUEST_I3C1_TX 121U /*!< GPDMA1 HW request is I3C1_TX */
1141 #define LL_GPDMA1_REQUEST_I3C1_TC 122U /*!< GPDMA1 HW request is I3C1_TC */
1142 #define LL_GPDMA1_REQUEST_I3C1_RS 123U /*!< GPDMA1 HW request is I3C1_RS */
1143 #if defined (I2C4)
1144 #define LL_GPDMA1_REQUEST_I2C4_RX 124U /*!< GPDMA1 HW request is I2C4_RX */
1145 #define LL_GPDMA1_REQUEST_I2C4_TX 125U /*!< GPDMA1 HW request is I2C4_TX */
1146 #endif /* I2C4 */
1147 #if defined (LPTIM3)
1148 #define LL_GPDMA1_REQUEST_LPTIM3_IC1 127U /*!< GPDMA1 HW request is LPTIM3_IC1 */
1149 #define LL_GPDMA1_REQUEST_LPTIM3_IC2 128U /*!< GPDMA1 HW request is LPTIM3_IC2 */
1150 #define LL_GPDMA1_REQUEST_LPTIM3_UE 129U /*!< GPDMA1 HW request is LPTIM3_UE */
1151 #endif /* LPTIM3 */
1152 #if defined (LPTIM5)
1153 #define LL_GPDMA1_REQUEST_LPTIM5_IC1 130U /*!< GPDMA1 HW request is LPTIM5_IC1 */
1154 #define LL_GPDMA1_REQUEST_LPTIM5_IC2 131U /*!< GPDMA1 HW request is LPTIM5_IC2 */
1155 #define LL_GPDMA1_REQUEST_LPTIM5_UE 132U /*!< GPDMA1 HW request is LPTIM5_UE */
1156 #endif /* LPTIM5 */
1157 #if defined (LPTIM6)
1158 #define LL_GPDMA1_REQUEST_LPTIM6_IC1 133U /*!< GPDMA1 HW request is LPTIM6_IC1 */
1159 #define LL_GPDMA1_REQUEST_LPTIM6_IC2 134U /*!< GPDMA1 HW request is LPTIM6_IC2 */
1160 #define LL_GPDMA1_REQUEST_LPTIM6_UE 135U /*!< GPDMA1 HW request is LPTIM6_UE */
1161 #endif /* LPTIM6 */
1162 #if defined (I3C2)
1163 #define LL_GPDMA1_REQUEST_I3C2_RX 136U /*!< GPDMA1 HW request is I3C2_RX */
1164 #define LL_GPDMA1_REQUEST_I3C2_TX 137U /*!< GPDMA1 HW request is I3C2_TX */
1165 #define LL_GPDMA1_REQUEST_I3C2_TC 138U /*!< GPDMA1 HW request is I3C2_TC */
1166 #define LL_GPDMA1_REQUEST_I3C2_RS 139U /*!< GPDMA1 HW request is I3C2_RS */
1167 #endif /* I3C2 */
1168
1169 /* GPDMA2 Hardware Requests */
1170 #define LL_GPDMA2_REQUEST_ADC1 0U /*!< GPDMA2 HW request is ADC1 */
1171 #if defined (ADC2)
1172 #define LL_GPDMA2_REQUEST_ADC2 1U /*!< GPDMA2 HW request is ADC2 */
1173 #endif /* ADC2 */
1174 #define LL_GPDMA2_REQUEST_DAC1_CH1 2U /*!< GPDMA2 HW request is DAC1_CH1 */
1175 #define LL_GPDMA2_REQUEST_DAC1_CH2 3U /*!< GPDMA2 HW request is DAC1_CH2 */
1176 #define LL_GPDMA2_REQUEST_TIM6_UP 4U /*!< GPDMA2 HW request is TIM6_UP */
1177 #define LL_GPDMA2_REQUEST_TIM7_UP 5U /*!< GPDMA2 HW request is TIM7_UP */
1178 #define LL_GPDMA2_REQUEST_SPI1_RX 6U /*!< GPDMA2 HW request is SPI1_RX */
1179 #define LL_GPDMA2_REQUEST_SPI1_TX 7U /*!< GPDMA2 HW request is SPI1_TX */
1180 #define LL_GPDMA2_REQUEST_SPI2_RX 8U /*!< GPDMA2 HW request is SPI2_RX */
1181 #define LL_GPDMA2_REQUEST_SPI2_TX 9U /*!< GPDMA2 HW request is SPI2_TX */
1182 #define LL_GPDMA2_REQUEST_SPI3_RX 10U /*!< GPDMA2 HW request is SPI3_RX */
1183 #define LL_GPDMA2_REQUEST_SPI3_TX 11U /*!< GPDMA2 HW request is SPI3_TX */
1184 #define LL_GPDMA2_REQUEST_I2C1_RX 12U /*!< GPDMA2 HW request is I2C1_RX */
1185 #define LL_GPDMA2_REQUEST_I2C1_TX 13U /*!< GPDMA2 HW request is I2C1_TX */
1186 #define LL_GPDMA2_REQUEST_I2C2_RX 15U /*!< GPDMA2 HW request is I2C2_RX */
1187 #define LL_GPDMA2_REQUEST_I2C2_TX 16U /*!< GPDMA2 HW request is I2C2_TX */
1188 #if defined (I2C3)
1189 #define LL_GPDMA2_REQUEST_I2C3_RX 18U /*!< GPDMA2 HW request is I2C3_RX */
1190 #define LL_GPDMA2_REQUEST_I2C3_TX 19U /*!< GPDMA2 HW request is I2C3_TX */
1191 #endif /* I2C3 */
1192 #define LL_GPDMA2_REQUEST_USART1_RX 21U /*!< GPDMA2 HW request is USART1_RX */
1193 #define LL_GPDMA2_REQUEST_USART1_TX 22U /*!< GPDMA2 HW request is USART1_TX */
1194 #define LL_GPDMA2_REQUEST_USART2_RX 23U /*!< GPDMA2 HW request is USART2_RX */
1195 #define LL_GPDMA2_REQUEST_USART2_TX 24U /*!< GPDMA2 HW request is USART2_TX */
1196 #define LL_GPDMA2_REQUEST_USART3_RX 25U /*!< GPDMA2 HW request is USART3_RX */
1197 #define LL_GPDMA2_REQUEST_USART3_TX 26U /*!< GPDMA2 HW request is USART3_TX */
1198 #if defined (UART4)
1199 #define LL_GPDMA2_REQUEST_UART4_RX 27U /*!< GPDMA2 HW request is UART4_RX */
1200 #define LL_GPDMA2_REQUEST_UART4_TX 28U /*!< GPDMA2 HW request is UART4_TX */
1201 #endif /* UART4 */
1202 #if defined (UART4)
1203 #define LL_GPDMA2_REQUEST_UART5_RX 29U /*!< GPDMA2 HW request is UART5_RX */
1204 #define LL_GPDMA2_REQUEST_UART5_TX 30U /*!< GPDMA2 HW request is UART5_TX */
1205 #endif /* UART5 */
1206 #if defined (UART4)
1207 #define LL_GPDMA2_REQUEST_USART6_RX 31U /*!< GPDMA2 HW request is USART6_RX */
1208 #define LL_GPDMA2_REQUEST_USART6_TX 32U /*!< GPDMA2 HW request is USART6_TX */
1209 #endif /* USART6 */
1210 #if defined (UART7)
1211 #define LL_GPDMA2_REQUEST_UART7_RX 33U /*!< GPDMA2 HW request is UART7_RX */
1212 #define LL_GPDMA2_REQUEST_UART7_TX 34U /*!< GPDMA2 HW request is UART7_TX */
1213 #endif /* UART7 */
1214 #if defined (UART8)
1215 #define LL_GPDMA2_REQUEST_UART8_RX 35U /*!< GPDMA2 HW request is UART8_RX */
1216 #define LL_GPDMA2_REQUEST_UART8_TX 36U /*!< GPDMA2 HW request is UART8_TX */
1217 #endif /* UART8 */
1218 #if defined (UART9)
1219 #define LL_GPDMA2_REQUEST_UART9_RX 37U /*!< GPDMA2 HW request is UART9_RX */
1220 #define LL_GPDMA2_REQUEST_UART9_TX 38U /*!< GPDMA2 HW request is UART9_TX */
1221 #endif /* UART9 */
1222 #if defined (USART10)
1223 #define LL_GPDMA2_REQUEST_USART10_RX 39U /*!< GPDMA2 HW request is USART10_RX */
1224 #define LL_GPDMA2_REQUEST_USART10_TX 40U /*!< GPDMA2 HW request is USART10_TX */
1225 #endif /* USART10 */
1226 #if defined (USART11)
1227 #define LL_GPDMA2_REQUEST_USART11_RX 41U /*!< GPDMA2 HW request is USART11_RX */
1228 #define LL_GPDMA2_REQUEST_USART11_TX 42U /*!< GPDMA2 HW request is USART11_TX */
1229 #endif /* USART11 */
1230 #if defined (UART12)
1231 #define LL_GPDMA2_REQUEST_UART12_RX 43U /*!< GPDMA2 HW request is UART12_RX */
1232 #define LL_GPDMA2_REQUEST_UART12_TX 44U /*!< GPDMA2 HW request is UART12_TX */
1233 #endif /* UART12 */
1234 #define LL_GPDMA2_REQUEST_LPUART1_RX 45U /*!< GPDMA2 HW request is LPUART1_RX */
1235 #define LL_GPDMA2_REQUEST_LPUART1_TX 46U /*!< GPDMA2 HW request is LPUART1_TX */
1236 #if defined (SPI4)
1237 #define LL_GPDMA2_REQUEST_SPI4_RX 47U /*!< GPDMA2 HW request is SPI4_RX */
1238 #define LL_GPDMA2_REQUEST_SPI4_TX 48U /*!< GPDMA2 HW request is SPI4_TX */
1239 #endif /* SPI4 */
1240 #if defined (SPI5)
1241 #define LL_GPDMA2_REQUEST_SPI5_RX 49U /*!< GPDMA2 HW request is SPI5_RX */
1242 #define LL_GPDMA2_REQUEST_SPI5_TX 50U /*!< GPDMA2 HW request is SPI5_TX */
1243 #endif /* SPI5 */
1244 #if defined (SPI6)
1245 #define LL_GPDMA2_REQUEST_SPI6_RX 51U /*!< GPDMA2 HW request is SPI6_RX */
1246 #define LL_GPDMA2_REQUEST_SPI6_TX 52U /*!< GPDMA2 HW request is SPI6_TX */
1247 #endif /* SPI6 */
1248 #if defined (SAI1)
1249 #define LL_GPDMA2_REQUEST_SAI1_A 53U /*!< GPDMA2 HW request is SAI1_A */
1250 #define LL_GPDMA2_REQUEST_SAI1_B 54U /*!< GPDMA2 HW request is SAI1_B */
1251 #endif /* SAI1 */
1252 #if defined (SAI2)
1253 #define LL_GPDMA2_REQUEST_SAI2_A 55U /*!< GPDMA2 HW request is SAI2_A */
1254 #define LL_GPDMA2_REQUEST_SAI2_B 56U /*!< GPDMA2 HW request is SAI2_B */
1255 #endif /* SAI2 */
1256 #if defined (OCTOSPI1)
1257 #define LL_GPDMA2_REQUEST_OCTOSPI1 57U /*!< GPDMA2 HW request is OCTOSPI1 */
1258 #endif /* OCTOSPI1 */
1259 #define LL_GPDMA2_REQUEST_TIM1_CH1 58U /*!< GPDMA2 HW request is TIM1_CH1 */
1260 #define LL_GPDMA2_REQUEST_TIM1_CH2 59U /*!< GPDMA2 HW request is TIM1_CH2 */
1261 #define LL_GPDMA2_REQUEST_TIM1_CH3 60U /*!< GPDMA2 HW request is TIM1_CH3 */
1262 #define LL_GPDMA2_REQUEST_TIM1_CH4 61U /*!< GPDMA2 HW request is TIM1_CH4 */
1263 #define LL_GPDMA2_REQUEST_TIM1_UP 62U /*!< GPDMA2 HW request is TIM1_UP */
1264 #define LL_GPDMA2_REQUEST_TIM1_TRIG 63U /*!< GPDMA2 HW request is TIM1_TRIG */
1265 #define LL_GPDMA2_REQUEST_TIM1_COM 64U /*!< GPDMA2 HW request is TIM1_COM */
1266 #if defined (TIM8)
1267 #define LL_GPDMA2_REQUEST_TIM8_CH1 65U /*!< GPDMA2 HW request is TIM8_CH1 */
1268 #define LL_GPDMA2_REQUEST_TIM8_CH2 66U /*!< GPDMA2 HW request is TIM8_CH2 */
1269 #define LL_GPDMA2_REQUEST_TIM8_CH3 67U /*!< GPDMA2 HW request is TIM8_CH3 */
1270 #define LL_GPDMA2_REQUEST_TIM8_CH4 68U /*!< GPDMA2 HW request is TIM8_CH4 */
1271 #define LL_GPDMA2_REQUEST_TIM8_UP 69U /*!< GPDMA2 HW request is TIM8_UP */
1272 #define LL_GPDMA2_REQUEST_TIM8_TRIG 70U /*!< GPDMA2 HW request is TIM8_TRIG */
1273 #define LL_GPDMA2_REQUEST_TIM8_COM 71U /*!< GPDMA2 HW request is TIM8_COM */
1274 #endif /* TIM8 */
1275 #define LL_GPDMA2_REQUEST_TIM2_CH1 72U /*!< GPDMA2 HW request is TIM2_CH1 */
1276 #define LL_GPDMA2_REQUEST_TIM2_CH2 73U /*!< GPDMA2 HW request is TIM2_CH2 */
1277 #define LL_GPDMA2_REQUEST_TIM2_CH3 74U /*!< GPDMA2 HW request is TIM2_CH3 */
1278 #define LL_GPDMA2_REQUEST_TIM2_CH4 75U /*!< GPDMA2 HW request is TIM2_CH4 */
1279 #define LL_GPDMA2_REQUEST_TIM2_UP 76U /*!< GPDMA2 HW request is TIM2_UP */
1280 #define LL_GPDMA2_REQUEST_TIM3_CH1 77U /*!< GPDMA2 HW request is TIM3_CH1 */
1281 #define LL_GPDMA2_REQUEST_TIM3_CH2 78U /*!< GPDMA2 HW request is TIM3_CH2 */
1282 #define LL_GPDMA2_REQUEST_TIM3_CH3 79U /*!< GPDMA2 HW request is TIM3_CH3 */
1283 #define LL_GPDMA2_REQUEST_TIM3_CH4 80U /*!< GPDMA2 HW request is TIM3_CH4 */
1284 #define LL_GPDMA2_REQUEST_TIM3_UP 81U /*!< GPDMA2 HW request is TIM3_UP */
1285 #define LL_GPDMA2_REQUEST_TIM3_TRIG 82U /*!< GPDMA2 HW request is TIM3_TRIG */
1286 #if defined (TIM4)
1287 #define LL_GPDMA2_REQUEST_TIM4_CH1 83U /*!< GPDMA2 HW request is TIM4_CH1 */
1288 #define LL_GPDMA2_REQUEST_TIM4_CH2 84U /*!< GPDMA2 HW request is TIM4_CH2 */
1289 #define LL_GPDMA2_REQUEST_TIM4_CH3 85U /*!< GPDMA2 HW request is TIM4_CH3 */
1290 #define LL_GPDMA2_REQUEST_TIM4_CH4 86U /*!< GPDMA2 HW request is TIM4_CH4 */
1291 #define LL_GPDMA2_REQUEST_TIM4_UP 87U /*!< GPDMA2 HW request is TIM4_UP */
1292 #endif /* TIM4 */
1293 #if defined (TIM5)
1294 #define LL_GPDMA2_REQUEST_TIM5_CH1 88U /*!< GPDMA2 HW request is TIM5_CH1 */
1295 #define LL_GPDMA2_REQUEST_TIM5_CH2 89U /*!< GPDMA2 HW request is TIM5_CH2 */
1296 #define LL_GPDMA2_REQUEST_TIM5_CH3 90U /*!< GPDMA2 HW request is TIM5_CH3 */
1297 #define LL_GPDMA2_REQUEST_TIM5_CH4 91U /*!< GPDMA2 HW request is TIM5_CH4 */
1298 #define LL_GPDMA2_REQUEST_TIM5_UP 92U /*!< GPDMA2 HW request is TIM5_UP */
1299 #define LL_GPDMA2_REQUEST_TIM5_TRIG 93U /*!< GPDMA2 HW request is TIM5_TRIG */
1300 #endif /* TIM5 */
1301 #if defined (TIM15)
1302 #define LL_GPDMA2_REQUEST_TIM15_CH1 94U /*!< GPDMA2 HW request is TIM15_CH1 */
1303 #define LL_GPDMA2_REQUEST_TIM15_UP 95U /*!< GPDMA2 HW request is TIM15_UP */
1304 #define LL_GPDMA2_REQUEST_TIM15_TRIG 96U /*!< GPDMA2 HW request is TIM15_TRIG */
1305 #define LL_GPDMA2_REQUEST_TIM15_COM 97U /*!< GPDMA2 HW request is TIM15_COM */
1306 #endif /* TIM15 */
1307 #if defined (TIM16)
1308 #define LL_GPDMA2_REQUEST_TIM16_CH1 98U /*!< GPDMA2 HW request is TIM16_CH1 */
1309 #define LL_GPDMA2_REQUEST_TIM16_UP 99U /*!< GPDMA2 HW request is TIM16_UP */
1310 #endif /* TIM16 */
1311 #if defined (TIM17)
1312 #define LL_GPDMA2_REQUEST_TIM17_CH1 100U /*!< GPDMA2 HW request is TIM17_CH1 */
1313 #define LL_GPDMA2_REQUEST_TIM17_UP 101U /*!< GPDMA2 HW request is TIM17_UP */
1314 #endif /* TIM17 */
1315 #define LL_GPDMA2_REQUEST_LPTIM1_IC1 102U /*!< GPDMA2 HW request is LPTIM1_IC1 */
1316 #define LL_GPDMA2_REQUEST_LPTIM1_IC2 103U /*!< GPDMA2 HW request is LPTIM1_IC2 */
1317 #define LL_GPDMA2_REQUEST_LPTIM1_UE 104U /*!< GPDMA2 HW request is LPTIM1_UE */
1318 #define LL_GPDMA2_REQUEST_LPTIM2_IC1 105U /*!< GPDMA2 HW request is LPTIM2_IC1 */
1319 #define LL_GPDMA2_REQUEST_LPTIM2_IC2 106U /*!< GPDMA2 HW request is LPTIM2_IC2 */
1320 #define LL_GPDMA2_REQUEST_LPTIM2_UE 107U /*!< GPDMA2 HW request is LPTIM2_UE */
1321 #if defined (DCMI)
1322 #define LL_GPDMA2_REQUEST_DCMI 108U /*!< GPDMA2 HW request is DCMI */
1323 #endif /* DCMI */
1324 #if defined (AES)
1325 #define LL_GPDMA2_REQUEST_AES_OUT 109U /*!< GPDMA2 HW request is AES_OUT */
1326 #define LL_GPDMA2_REQUEST_AES_IN 110U /*!< GPDMA2 HW request is AES_IN */
1327 #endif /* AES */
1328 #define LL_GPDMA2_REQUEST_HASH_IN 111U /*!< GPDMA2 HW request is HASH_IN */
1329 #if defined (UCPD1)
1330 #define LL_GPDMA2_REQUEST_UCPD1_RX 112U /*!< GPDMA2 HW request is UCPD1_RX */
1331 #define LL_GPDMA2_REQUEST_UCPD1_TX 113U /*!< GPDMA2 HW request is UCPD1_TX */
1332 #endif /* UCPD1 */
1333 #if defined (CORDIC)
1334 #define LL_GPDMA2_REQUEST_CORDIC_READ 114U /*!< GPDMA2 HW request is CORDIC_READ */
1335 #define LL_GPDMA2_REQUEST_CORDIC_WRITE 115U /*!< GPDMA2 HW request is CORDIC_WRITE */
1336 #endif /* CORDIC */
1337 #if defined (FMAC)
1338 #define LL_GPDMA2_REQUEST_FMAC_READ 116U /*!< GPDMA2 HW request is FMAC_READ */
1339 #define LL_GPDMA2_REQUEST_FMAC_WRITE 117U /*!< GPDMA2 HW request is FMAC_WRITE */
1340 #endif /* FMAC */
1341 #if defined (SAES)
1342 #define LL_GPDMA2_REQUEST_SAES_OUT 118U /*!< GPDMA2 HW request is SAES_OUT */
1343 #define LL_GPDMA2_REQUEST_SAES_IN 119U /*!< GPDMA2 HW request is SAES_IN */
1344 #endif /* SAES */
1345 #define LL_GPDMA2_REQUEST_I3C1_RX 120U /*!< GPDMA2 HW request is I3C1_RX */
1346 #define LL_GPDMA2_REQUEST_I3C1_TX 121U /*!< GPDMA2 HW request is I3C1_TX */
1347 #define LL_GPDMA2_REQUEST_I3C1_TC 122U /*!< GPDMA2 HW request is I3C1_TC */
1348 #define LL_GPDMA2_REQUEST_I3C1_RS 123U /*!< GPDMA2 HW request is I3C1_RS */
1349 #if defined (I2C4)
1350 #define LL_GPDMA2_REQUEST_I2C4_RX 124U /*!< GPDMA2 HW request is I2C4_RX */
1351 #define LL_GPDMA2_REQUEST_I2C4_TX 125U /*!< GPDMA2 HW request is I2C4_TX */
1352 #endif /* I2C4 */
1353 #if defined (LPTIM3)
1354 #define LL_GPDMA2_REQUEST_LPTIM3_IC1 127U /*!< GPDMA2 HW request is LPTIM3_IC1 */
1355 #define LL_GPDMA2_REQUEST_LPTIM3_IC2 128U /*!< GPDMA2 HW request is LPTIM3_IC2 */
1356 #define LL_GPDMA2_REQUEST_LPTIM3_UE 129U /*!< GPDMA2 HW request is LPTIM3_UE */
1357 #endif /* LPTIM3 */
1358 #if defined (LPTIM5)
1359 #define LL_GPDMA2_REQUEST_LPTIM5_IC1 130U /*!< GPDMA2 HW request is LPTIM5_IC1 */
1360 #define LL_GPDMA2_REQUEST_LPTIM5_IC2 131U /*!< GPDMA2 HW request is LPTIM5_IC2 */
1361 #define LL_GPDMA2_REQUEST_LPTIM5_UE 132U /*!< GPDMA2 HW request is LPTIM5_UE */
1362 #endif /* LPTIM5 */
1363 #if defined (LPTIM6)
1364 #define LL_GPDMA2_REQUEST_LPTIM6_IC1 133U /*!< GPDMA2 HW request is LPTIM6_IC1 */
1365 #define LL_GPDMA2_REQUEST_LPTIM6_IC2 134U /*!< GPDMA2 HW request is LPTIM6_IC2 */
1366 #define LL_GPDMA2_REQUEST_LPTIM6_UE 135U /*!< GPDMA2 HW request is LPTIM6_UE */
1367 #endif /* LPTIM6 */
1368 #if defined (I3C2)
1369 #define LL_GPDMA2_REQUEST_I3C2_RX 136U /*!< GPDMA2 HW request is I3C2_RX */
1370 #define LL_GPDMA2_REQUEST_I3C2_TX 137U /*!< GPDMA2 HW request is I3C2_TX */
1371 #define LL_GPDMA2_REQUEST_I3C2_TC 138U /*!< GPDMA2 HW request is I3C2_TC */
1372 #define LL_GPDMA2_REQUEST_I3C2_RS 139U /*!< GPDMA2 HW request is I3C2_RS */
1373 #endif /* I3C2 */
1374
1375 /**
1376 * @}
1377 */
1378
1379 /** @defgroup DMA_LL_EC_TRIGGER_SELECTION Trigger Selection
1380 * @{
1381 */
1382 /* GPDMA1 Hardware Triggers */
1383 #define LL_GPDMA1_TRIGGER_EXTI_LINE0 0U /*!< GPDMA1 HW Trigger signal is EXTI_LINE0 */
1384 #define LL_GPDMA1_TRIGGER_EXTI_LINE1 1U /*!< GPDMA1 HW Trigger signal is EXTI_LINE1 */
1385 #define LL_GPDMA1_TRIGGER_EXTI_LINE2 2U /*!< GPDMA1 HW Trigger signal is EXTI_LINE2 */
1386 #define LL_GPDMA1_TRIGGER_EXTI_LINE3 3U /*!< GPDMA1 HW Trigger signal is EXTI_LINE3 */
1387 #define LL_GPDMA1_TRIGGER_EXTI_LINE4 4U /*!< GPDMA1 HW Trigger signal is EXTI_LINE4 */
1388 #define LL_GPDMA1_TRIGGER_EXTI_LINE5 5U /*!< GPDMA1 HW Trigger signal is EXTI_LINE5 */
1389 #define LL_GPDMA1_TRIGGER_EXTI_LINE6 6U /*!< GPDMA1 HW Trigger signal is EXTI_LINE6 */
1390 #define LL_GPDMA1_TRIGGER_EXTI_LINE7 7U /*!< GPDMA1 HW Trigger signal is EXTI_LINE7 */
1391 #define LL_GPDMA1_TRIGGER_TAMP_TRG1 8U /*!< GPDMA1 HW Trigger signal is TAMP_TRG1 */
1392 #define LL_GPDMA1_TRIGGER_TAMP_TRG2 9U /*!< GPDMA1 HW Trigger signal is TAMP_TRG2 */
1393 #if defined (TAMP_CR1_TAMP3E)
1394 #define LL_GPDMA1_TRIGGER_TAMP_TRG3 10U /*!< GPDMA1 HW Trigger signal is TAMP_TRG3 */
1395 #endif /* TAMP_CR1_TAMP3E */
1396 #define LL_GPDMA1_TRIGGER_LPTIM1_CH1 11U /*!< GPDMA1 HW Trigger signal is LPTIM1_CH1 */
1397 #define LL_GPDMA1_TRIGGER_LPTIM1_CH2 12U /*!< GPDMA1 HW Trigger signal is LPTIM1_CH2 */
1398 #define LL_GPDMA1_TRIGGER_LPTIM2_CH1 13U /*!< GPDMA1 HW Trigger signal is LPTIM2_CH1 */
1399 #define LL_GPDMA1_TRIGGER_LPTIM2_CH2 14U /*!< GPDMA1 HW Trigger signal is LPTIM2_CH2 */
1400 #define LL_GPDMA1_TRIGGER_RTC_ALRA_TRG 15U /*!< GPDMA1 HW Trigger signal is RTC_ALRA_TRG */
1401 #define LL_GPDMA1_TRIGGER_RTC_ALRB_TRG 16U /*!< GPDMA1 HW Trigger signal is RTC_ALRB_TRG */
1402 #define LL_GPDMA1_TRIGGER_RTC_WUT_TRG 17U /*!< GPDMA1 HW Trigger signal is RTC_WUT_TRG */
1403 #define LL_GPDMA1_TRIGGER_GPDMA1_CH0_TCF 18U /*!< GPDMA1 HW Trigger signal is GPDMA1_CH0_TCF */
1404 #define LL_GPDMA1_TRIGGER_GPDMA1_CH1_TCF 19U /*!< GPDMA1 HW Trigger signal is GPDMA1_CH1_TCF */
1405 #define LL_GPDMA1_TRIGGER_GPDMA1_CH2_TCF 20U /*!< GPDMA1 HW Trigger signal is GPDMA1_CH2_TCF */
1406 #define LL_GPDMA1_TRIGGER_GPDMA1_CH3_TCF 21U /*!< GPDMA1 HW Trigger signal is GPDMA1_CH3_TCF */
1407 #define LL_GPDMA1_TRIGGER_GPDMA1_CH4_TCF 22U /*!< GPDMA1 HW Trigger signal is GPDMA1_CH4_TCF */
1408 #define LL_GPDMA1_TRIGGER_GPDMA1_CH5_TCF 23U /*!< GPDMA1 HW Trigger signal is GPDMA1_CH5_TCF */
1409 #define LL_GPDMA1_TRIGGER_GPDMA1_CH6_TCF 24U /*!< GPDMA1 HW Trigger signal is GPDMA1_CH6_TCF */
1410 #define LL_GPDMA1_TRIGGER_GPDMA1_CH7_TCF 25U /*!< GPDMA1 HW Trigger signal is GPDMA1_CH7_TCF */
1411 #define LL_GPDMA1_TRIGGER_GPDMA2_CH0_TCF 26U /*!< GPDMA1 HW Trigger signal is GPDMA2_CH0_TCF */
1412 #define LL_GPDMA1_TRIGGER_GPDMA2_CH1_TCF 27U /*!< GPDMA1 HW Trigger signal is GPDMA2_CH1_TCF */
1413 #define LL_GPDMA1_TRIGGER_GPDMA2_CH2_TCF 28U /*!< GPDMA1 HW Trigger signal is GPDMA2_CH2_TCF */
1414 #define LL_GPDMA1_TRIGGER_GPDMA2_CH3_TCF 29U /*!< GPDMA1 HW Trigger signal is GPDMA2_CH3_TCF */
1415 #define LL_GPDMA1_TRIGGER_GPDMA2_CH4_TCF 30U /*!< GPDMA1 HW Trigger signal is GPDMA2_CH4_TCF */
1416 #define LL_GPDMA1_TRIGGER_GPDMA2_CH5_TCF 31U /*!< GPDMA1 HW Trigger signal is GPDMA2_CH5_TCF */
1417 #define LL_GPDMA1_TRIGGER_GPDMA2_CH6_TCF 32U /*!< GPDMA1 HW Trigger signal is GPDMA2_CH6_TCF */
1418 #define LL_GPDMA1_TRIGGER_GPDMA2_CH7_TCF 33U /*!< GPDMA1 HW Trigger signal is GPDMA2_CH7_TCF */
1419 #define LL_GPDMA1_TRIGGER_TIM2_TRGO 34U /*!< GPDMA1 HW Trigger signal is TIM2_TRGO */
1420 #if defined (TIM15)
1421 #define LL_GPDMA1_TRIGGER_TIM15_TRGO 35U /*!< GPDMA1 HW Trigger signal is TIM15_TRGO */
1422 #endif /* TIM15 */
1423 #if defined (TIM12)
1424 #define LL_GPDMA1_TRIGGER_TIM12_TRGO 36U /*!< GPDMA1 HW Trigger signal is TIM12_TRGO */
1425 #endif /* TIM12 */
1426 #if defined (LPTIM3)
1427 #define LL_GPDMA1_TRIGGER_LPTIM3_CH1 37U /*!< GPDMA1 HW Trigger signal is LPTIM3_CH1 */
1428 #define LL_GPDMA1_TRIGGER_LPTIM3_CH2 38U /*!< GPDMA1 HW Trigger signal is LPTIM3_CH2 */
1429 #endif /* LPTIM3 */
1430 #if defined (LPTIM4)
1431 #define LL_GPDMA1_TRIGGER_LPTIM4_AIT 39U /*!< GPDMA1 HW Trigger signal is LPTIM4_AIT */
1432 #endif /* LPTIM4 */
1433 #if defined (LPTIM5)
1434 #define LL_GPDMA1_TRIGGER_LPTIM5_CH1 40U /*!< GPDMA1 HW Trigger signal is LPTIM5_CH1 */
1435 #define LL_GPDMA1_TRIGGER_LPTIM5_CH2 41U /*!< GPDMA1 HW Trigger signal is LPTIM5_CH2 */
1436 #endif /* LPTIM5 */
1437 #if defined (LPTIM6)
1438 #define LL_GPDMA1_TRIGGER_LPTIM6_CH1 42U /*!< GPDMA1 HW Trigger signal is LPTIM6_CH1 */
1439 #define LL_GPDMA1_TRIGGER_LPTIM6_CH2 43U /*!< GPDMA1 HW Trigger signal is LPTIM6_CH2 */
1440 #endif /* LPTIM6 */
1441 #if defined (COMP1)
1442 #define LL_GPDMA1_TRIGGER_COMP1_OUT 44U /*!< GPDMA1 HW Trigger signal is COMP1_OUT */
1443 #endif /* COMP1 */
1444 #if defined (STM32H503xx)
1445 #define LL_GPDMA1_TRIGGER_EVENTOUT 45U /*!< GPDMA1 HW Trigger signal is COMP1_OUT */
1446 #endif /* STM32H503xx */
1447
1448 /* GPDMA2 Hardware Triggers */
1449 #define LL_GPDMA2_TRIGGER_EXTI_LINE0 0U /*!< GPDMA2 HW Trigger signal is EXTI_LINE0 */
1450 #define LL_GPDMA2_TRIGGER_EXTI_LINE1 1U /*!< GPDMA2 HW Trigger signal is EXTI_LINE1 */
1451 #define LL_GPDMA2_TRIGGER_EXTI_LINE2 2U /*!< GPDMA2 HW Trigger signal is EXTI_LINE2 */
1452 #define LL_GPDMA2_TRIGGER_EXTI_LINE3 3U /*!< GPDMA2 HW Trigger signal is EXTI_LINE3 */
1453 #define LL_GPDMA2_TRIGGER_EXTI_LINE4 4U /*!< GPDMA2 HW Trigger signal is EXTI_LINE4 */
1454 #define LL_GPDMA2_TRIGGER_EXTI_LINE5 5U /*!< GPDMA2 HW Trigger signal is EXTI_LINE5 */
1455 #define LL_GPDMA2_TRIGGER_EXTI_LINE6 6U /*!< GPDMA2 HW Trigger signal is EXTI_LINE6 */
1456 #define LL_GPDMA2_TRIGGER_EXTI_LINE7 7U /*!< GPDMA2 HW Trigger signal is EXTI_LINE7 */
1457 #define LL_GPDMA2_TRIGGER_TAMP_TRG1 8U /*!< GPDMA2 HW Trigger signal is TAMP_TRG1 */
1458 #define LL_GPDMA2_TRIGGER_TAMP_TRG2 9U /*!< GPDMA2 HW Trigger signal is TAMP_TRG2 */
1459 #define LL_GPDMA2_TRIGGER_TAMP_TRG3 10U /*!< GPDMA2 HW Trigger signal is TAMP_TRG3 */
1460 #define LL_GPDMA2_TRIGGER_LPTIM1_CH1 11U /*!< GPDMA2 HW Trigger signal is LPTIM1_CH1 */
1461 #define LL_GPDMA2_TRIGGER_LPTIM1_CH2 12U /*!< GPDMA2 HW Trigger signal is LPTIM1_CH2 */
1462 #define LL_GPDMA2_TRIGGER_LPTIM2_CH1 13U /*!< GPDMA2 HW Trigger signal is LPTIM2_CH1 */
1463 #define LL_GPDMA2_TRIGGER_LPTIM2_CH2 14U /*!< GPDMA2 HW Trigger signal is LPTIM2_CH2 */
1464 #define LL_GPDMA2_TRIGGER_RTC_ALRA_TRG 15U /*!< GPDMA2 HW Trigger signal is RTC_ALRA_TRG */
1465 #define LL_GPDMA2_TRIGGER_RTC_ALRB_TRG 16U /*!< GPDMA2 HW Trigger signal is RTC_ALRB_TRG */
1466 #define LL_GPDMA2_TRIGGER_RTC_WUT_TRG 17U /*!< GPDMA2 HW Trigger signal is RTC_WUT_TRG */
1467 #define LL_GPDMA2_TRIGGER_GPDMA1_CH0_TCF 18U /*!< GPDMA2 HW Trigger signal is GPDMA1_CH0_TCF */
1468 #define LL_GPDMA2_TRIGGER_GPDMA1_CH1_TCF 19U /*!< GPDMA2 HW Trigger signal is GPDMA1_CH1_TCF */
1469 #define LL_GPDMA2_TRIGGER_GPDMA1_CH2_TCF 20U /*!< GPDMA2 HW Trigger signal is GPDMA1_CH2_TCF */
1470 #define LL_GPDMA2_TRIGGER_GPDMA1_CH3_TCF 21U /*!< GPDMA2 HW Trigger signal is GPDMA1_CH3_TCF */
1471 #define LL_GPDMA2_TRIGGER_GPDMA1_CH4_TCF 22U /*!< GPDMA2 HW Trigger signal is GPDMA1_CH4_TCF */
1472 #define LL_GPDMA2_TRIGGER_GPDMA1_CH5_TCF 23U /*!< GPDMA2 HW Trigger signal is GPDMA1_CH5_TCF */
1473 #define LL_GPDMA2_TRIGGER_GPDMA1_CH6_TCF 24U /*!< GPDMA2 HW Trigger signal is GPDMA1_CH6_TCF */
1474 #define LL_GPDMA2_TRIGGER_GPDMA1_CH7_TCF 25U /*!< GPDMA2 HW Trigger signal is GPDMA1_CH7_TCF */
1475 #define LL_GPDMA2_TRIGGER_GPDMA2_CH0_TCF 26U /*!< GPDMA2 HW Trigger signal is GPDMA2_CH0_TCF */
1476 #define LL_GPDMA2_TRIGGER_GPDMA2_CH1_TCF 27U /*!< GPDMA2 HW Trigger signal is GPDMA2_CH1_TCF */
1477 #define LL_GPDMA2_TRIGGER_GPDMA2_CH2_TCF 28U /*!< GPDMA2 HW Trigger signal is GPDMA2_CH2_TCF */
1478 #define LL_GPDMA2_TRIGGER_GPDMA2_CH3_TCF 29U /*!< GPDMA2 HW Trigger signal is GPDMA2_CH3_TCF */
1479 #define LL_GPDMA2_TRIGGER_GPDMA2_CH4_TCF 30U /*!< GPDMA2 HW Trigger signal is GPDMA2_CH4_TCF */
1480 #define LL_GPDMA2_TRIGGER_GPDMA2_CH5_TCF 31U /*!< GPDMA2 HW Trigger signal is GPDMA2_CH5_TCF */
1481 #define LL_GPDMA2_TRIGGER_GPDMA2_CH6_TCF 32U /*!< GPDMA2 HW Trigger signal is GPDMA2_CH6_TCF */
1482 #define LL_GPDMA2_TRIGGER_GPDMA2_CH7_TCF 33U /*!< GPDMA2 HW Trigger signal is GPDMA2_CH7_TCF */
1483 #define LL_GPDMA2_TRIGGER_TIM2_TRGO 34U /*!< GPDMA2 HW Trigger signal is TIM2_TRGO */
1484 #if defined (TIM15)
1485 #define LL_GPDMA2_TRIGGER_TIM15_TRGO 35U /*!< GPDMA2 HW Trigger signal is TIM15_TRGO */
1486 #endif /* TIM15 */
1487 #if defined (TIM12)
1488 #define LL_GPDMA2_TRIGGER_TIM12_TRGO 36U /*!< GPDMA2 HW Trigger signal is TIM12_TRGO */
1489 #endif /* TIM12 */
1490 #if defined (LPTIM3)
1491 #define LL_GPDMA2_TRIGGER_LPTIM3_CH1 37U /*!< GPDMA2 HW Trigger signal is LPTIM3_CH1 */
1492 #define LL_GPDMA2_TRIGGER_LPTIM3_CH2 38U /*!< GPDMA2 HW Trigger signal is LPTIM3_CH2 */
1493 #endif /* LPTIM3 */
1494 #if defined (LPTIM4)
1495 #define LL_GPDMA2_TRIGGER_LPTIM4_AIT 39U /*!< GPDMA2 HW Trigger signal is LPTIM4_AIT */
1496 #endif /* LPTIM4 */
1497 #if defined (LPTIM5)
1498 #define LL_GPDMA2_TRIGGER_LPTIM5_CH1 40U /*!< GPDMA2 HW Trigger signal is LPTIM5_CH1 */
1499 #define LL_GPDMA2_TRIGGER_LPTIM5_CH2 41U /*!< GPDMA2 HW Trigger signal is LPTIM5_CH2 */
1500 #endif /* LPTIM5 */
1501 #if defined (LPTIM6)
1502 #define LL_GPDMA2_TRIGGER_LPTIM6_CH1 42U /*!< GPDMA2 HW Trigger signal is LPTIM6_CH1 */
1503 #define LL_GPDMA2_TRIGGER_LPTIM6_CH2 43U /*!< GPDMA2 HW Trigger signal is LPTIM6_CH2 */
1504 #endif /* LPTIM6 */
1505 #if defined (COMP1)
1506 #define LL_GPDMA2_TRIGGER_COMP1_OUT 44U /*!< GPDMA2 HW Trigger signal is COMP1_OUT */
1507 #endif /* COMP1 */
1508 #if defined (STM32H503xx)
1509 #define LL_GPDMA2_TRIGGER_EVENTOUT 45U /*!< GPDMA2 HW Trigger signal is COMP1_OUT */
1510 #endif /* STM32H503xx */
1511 /**
1512 * @}
1513 */
1514
1515 /**
1516 * @}
1517 */
1518
1519 /* Exported macro ------------------------------------------------------------*/
1520
1521 /** @defgroup DMA_LL_Exported_Macros DMA Exported Macros
1522 * @{
1523 */
1524
1525 /** @defgroup DMA_LL_EM_COMMON_WRITE_READ_REGISTERS Common Write and Read Registers macros
1526 * @{
1527 */
1528 /**
1529 * @brief Write a value in DMA register.
1530 * @param __INSTANCE__ DMA Instance.
1531 * @param __REG__ Register to be written.
1532 * @param __VALUE__ Value to be written in the register.
1533 * @retval None.
1534 */
1535 #define LL_DMA_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG((__INSTANCE__)->__REG__, (__VALUE__))
1536
1537 /**
1538 * @brief Read a value in DMA register.
1539 * @param __INSTANCE__ DMA Instance.
1540 * @param __REG__ Register to be read.
1541 * @retval Register value.
1542 */
1543 #define LL_DMA_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
1544 /**
1545 * @}
1546 */
1547
1548 /** @defgroup DMA_LL_EM_CONVERT_DMAxCHANNELy Convert DMAxChannely
1549 * @{
1550 */
1551 /**
1552 * @brief Convert DMAx_Channely into DMAx.
1553 * @param __CHANNEL_INSTANCE__ DMAx_Channely.
1554 * @retval DMAx.
1555 */
1556 #define LL_DMA_GET_INSTANCE(__CHANNEL_INSTANCE__) \
1557 (((uint32_t)(__CHANNEL_INSTANCE__) > ((uint32_t)GPDMA1_Channel7)) ? GPDMA2 : GPDMA1)
1558
1559 /**
1560 * @brief Convert DMAx_Channely into LL_DMA_CHANNEL_y.
1561 * @param __CHANNEL_INSTANCE__ DMAx_Channely.
1562 * @retval LL_DMA_CHANNEL_y.
1563 */
1564 #define LL_DMA_GET_CHANNEL(__CHANNEL_INSTANCE__) \
1565 (((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)GPDMA1_Channel0)) ? LL_DMA_CHANNEL_0 : \
1566 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)GPDMA2_Channel0)) ? LL_DMA_CHANNEL_0 : \
1567 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)GPDMA1_Channel1)) ? LL_DMA_CHANNEL_1 : \
1568 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)GPDMA2_Channel1)) ? LL_DMA_CHANNEL_1 : \
1569 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)GPDMA1_Channel2)) ? LL_DMA_CHANNEL_2 : \
1570 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)GPDMA2_Channel2)) ? LL_DMA_CHANNEL_2 : \
1571 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)GPDMA1_Channel3)) ? LL_DMA_CHANNEL_3 : \
1572 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)GPDMA2_Channel3)) ? LL_DMA_CHANNEL_3 : \
1573 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)GPDMA1_Channel4)) ? LL_DMA_CHANNEL_4 : \
1574 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)GPDMA2_Channel4)) ? LL_DMA_CHANNEL_4 : \
1575 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)GPDMA1_Channel5)) ? LL_DMA_CHANNEL_5 : \
1576 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)GPDMA2_Channel5)) ? LL_DMA_CHANNEL_5 : \
1577 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)GPDMA1_Channel6)) ? LL_DMA_CHANNEL_6 : \
1578 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)GPDMA2_Channel6)) ? LL_DMA_CHANNEL_6 : \
1579 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)GPDMA1_Channel7)) ? LL_DMA_CHANNEL_7 : \
1580 LL_DMA_CHANNEL_7)
1581
1582 /**
1583 * @brief Convert DMA Instance DMAx and LL_DMA_CHANNEL_y into DMAx_Channely.
1584 * @param __DMA_INSTANCE__ DMAx.
1585 * @param __CHANNEL__ LL_DMA_CHANNEL_y.
1586 * @retval DMAx_Channely.
1587 */
1588 #define LL_DMA_GET_CHANNEL_INSTANCE(__DMA_INSTANCE__, __CHANNEL__) \
1589 ((((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)GPDMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_0))) \
1590 ? GPDMA1_Channel0 : \
1591 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)GPDMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) \
1592 ? GPDMA1_Channel1 : \
1593 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)GPDMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) \
1594 ? GPDMA1_Channel2 : \
1595 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)GPDMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) \
1596 ? GPDMA1_Channel3 : \
1597 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)GPDMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) \
1598 ? GPDMA1_Channel4 : \
1599 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)GPDMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) \
1600 ? GPDMA1_Channel5 : \
1601 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)GPDMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_6))) \
1602 ? GPDMA1_Channel6 : \
1603 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)GPDMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_7))) \
1604 ? GPDMA1_Channel7 : \
1605 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)GPDMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_0))) \
1606 ? GPDMA2_Channel0 : \
1607 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)GPDMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) \
1608 ? GPDMA2_Channel1 : \
1609 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)GPDMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2)))\
1610 ? GPDMA2_Channel2 : \
1611 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)GPDMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3)))\
1612 ? GPDMA2_Channel3 : \
1613 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)GPDMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4)))\
1614 ? GPDMA2_Channel4 : \
1615 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)GPDMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5)))\
1616 ? GPDMA2_Channel5 : \
1617 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)GPDMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_6)))\
1618 ? GPDMA2_Channel6 : GPDMA2_Channel7)
1619
1620 /**
1621 * @}
1622 */
1623
1624 /**
1625 * @}
1626 */
1627
1628 /* Exported functions --------------------------------------------------------*/
1629
1630 /** @defgroup DMA_LL_Exported_Functions DMA Exported Functions
1631 * @{
1632 */
1633
1634 /** @defgroup DMA_LL_EF_Configuration Configuration
1635 * @{
1636 */
1637 /**
1638 * @brief Enable channel.
1639 * @note This API is used for all available DMA channels.
1640 * @rmtoll CCR EN LL_DMA_EnableChannel
1641 * @param DMAx DMAx Instance.
1642 * @param Channel This parameter can be one of the following values:
1643 * @arg @ref LL_DMA_CHANNEL_0
1644 * @arg @ref LL_DMA_CHANNEL_1
1645 * @arg @ref LL_DMA_CHANNEL_2
1646 * @arg @ref LL_DMA_CHANNEL_3
1647 * @arg @ref LL_DMA_CHANNEL_4
1648 * @arg @ref LL_DMA_CHANNEL_5
1649 * @arg @ref LL_DMA_CHANNEL_6
1650 * @arg @ref LL_DMA_CHANNEL_7
1651 * @arg @ref LL_DMA_CHANNEL_8
1652 * @arg @ref LL_DMA_CHANNEL_9
1653 * @arg @ref LL_DMA_CHANNEL_10
1654 * @arg @ref LL_DMA_CHANNEL_11
1655 * @arg @ref LL_DMA_CHANNEL_12
1656 * @arg @ref LL_DMA_CHANNEL_13
1657 * @arg @ref LL_DMA_CHANNEL_14
1658 * @arg @ref LL_DMA_CHANNEL_15
1659 * @retval None.
1660 */
LL_DMA_EnableChannel(DMA_TypeDef * DMAx,uint32_t Channel)1661 __STATIC_INLINE void LL_DMA_EnableChannel(DMA_TypeDef *DMAx, uint32_t Channel)
1662 {
1663 uint32_t dma_base_addr = (uint32_t)DMAx;
1664 SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_EN);
1665 }
1666
1667 /**
1668 * @brief Disable channel.
1669 * @note This API is used for all available DMA channels.
1670 * @rmtoll CCR EN LL_DMA_DisableChannel
1671 * @param DMAx DMAx Instance.
1672 * @param Channel This parameter can be one of the following values:
1673 * @arg @ref LL_DMA_CHANNEL_0
1674 * @arg @ref LL_DMA_CHANNEL_1
1675 * @arg @ref LL_DMA_CHANNEL_2
1676 * @arg @ref LL_DMA_CHANNEL_3
1677 * @arg @ref LL_DMA_CHANNEL_4
1678 * @arg @ref LL_DMA_CHANNEL_5
1679 * @arg @ref LL_DMA_CHANNEL_6
1680 * @arg @ref LL_DMA_CHANNEL_7
1681 * @arg @ref LL_DMA_CHANNEL_8
1682 * @arg @ref LL_DMA_CHANNEL_9
1683 * @arg @ref LL_DMA_CHANNEL_10
1684 * @arg @ref LL_DMA_CHANNEL_11
1685 * @arg @ref LL_DMA_CHANNEL_12
1686 * @arg @ref LL_DMA_CHANNEL_13
1687 * @arg @ref LL_DMA_CHANNEL_14
1688 * @arg @ref LL_DMA_CHANNEL_15
1689 * @retval None.
1690 */
LL_DMA_DisableChannel(DMA_TypeDef * DMAx,uint32_t Channel)1691 __STATIC_INLINE void LL_DMA_DisableChannel(DMA_TypeDef *DMAx, uint32_t Channel)
1692 {
1693 uint32_t dma_base_addr = (uint32_t)DMAx;
1694 SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR,
1695 (DMA_CCR_SUSP | DMA_CCR_RESET));
1696 }
1697
1698 /**
1699 * @brief Check if channel is enabled or disabled.
1700 * @note This API is used for all available DMA channels.
1701 * @rmtoll CCR EN LL_DMA_IsEnabledChannel
1702 * @param DMAx DMAx Instance
1703 * @param Channel This parameter can be one of the following values:
1704 * @arg @ref LL_DMA_CHANNEL_0
1705 * @arg @ref LL_DMA_CHANNEL_1
1706 * @arg @ref LL_DMA_CHANNEL_2
1707 * @arg @ref LL_DMA_CHANNEL_3
1708 * @arg @ref LL_DMA_CHANNEL_4
1709 * @arg @ref LL_DMA_CHANNEL_5
1710 * @arg @ref LL_DMA_CHANNEL_6
1711 * @arg @ref LL_DMA_CHANNEL_7
1712 * @arg @ref LL_DMA_CHANNEL_8
1713 * @arg @ref LL_DMA_CHANNEL_9
1714 * @arg @ref LL_DMA_CHANNEL_10
1715 * @arg @ref LL_DMA_CHANNEL_11
1716 * @arg @ref LL_DMA_CHANNEL_12
1717 * @arg @ref LL_DMA_CHANNEL_13
1718 * @arg @ref LL_DMA_CHANNEL_14
1719 * @arg @ref LL_DMA_CHANNEL_15
1720 * @retval State of bit (1 or 0).
1721 */
LL_DMA_IsEnabledChannel(DMA_TypeDef * DMAx,uint32_t Channel)1722 __STATIC_INLINE uint32_t LL_DMA_IsEnabledChannel(DMA_TypeDef *DMAx, uint32_t Channel)
1723 {
1724 uint32_t dma_base_addr = (uint32_t)DMAx;
1725 return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_EN)
1726 == (DMA_CCR_EN)) ? 1UL : 0UL);
1727 }
1728
1729 /**
1730 * @brief Reset channel.
1731 * @note This API is used for all available DMA channels.
1732 * @rmtoll CCR RESET LL_DMA_ResetChannel
1733 * @param DMAx DMAx Instance
1734 * @param Channel This parameter can be one of the following values:
1735 * @arg @ref LL_DMA_CHANNEL_0
1736 * @arg @ref LL_DMA_CHANNEL_1
1737 * @arg @ref LL_DMA_CHANNEL_2
1738 * @arg @ref LL_DMA_CHANNEL_3
1739 * @arg @ref LL_DMA_CHANNEL_4
1740 * @arg @ref LL_DMA_CHANNEL_5
1741 * @arg @ref LL_DMA_CHANNEL_6
1742 * @arg @ref LL_DMA_CHANNEL_7
1743 * @arg @ref LL_DMA_CHANNEL_8
1744 * @arg @ref LL_DMA_CHANNEL_9
1745 * @arg @ref LL_DMA_CHANNEL_10
1746 * @arg @ref LL_DMA_CHANNEL_11
1747 * @arg @ref LL_DMA_CHANNEL_12
1748 * @arg @ref LL_DMA_CHANNEL_13
1749 * @arg @ref LL_DMA_CHANNEL_14
1750 * @arg @ref LL_DMA_CHANNEL_15
1751 * @retval None.
1752 */
LL_DMA_ResetChannel(DMA_TypeDef * DMAx,uint32_t Channel)1753 __STATIC_INLINE void LL_DMA_ResetChannel(DMA_TypeDef *DMAx, uint32_t Channel)
1754 {
1755 uint32_t dma_base_addr = (uint32_t)DMAx;
1756 SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_RESET);
1757 }
1758
1759 /**
1760 * @brief Suspend channel.
1761 * @note This API is used for all available DMA channels.
1762 * @rmtoll CCR SUSP LL_DMA_SuspendChannel
1763 * @param DMAx DMAx Instance
1764 * @param Channel This parameter can be one of the following values:
1765 * @arg @ref LL_DMA_CHANNEL_0
1766 * @arg @ref LL_DMA_CHANNEL_1
1767 * @arg @ref LL_DMA_CHANNEL_2
1768 * @arg @ref LL_DMA_CHANNEL_3
1769 * @arg @ref LL_DMA_CHANNEL_4
1770 * @arg @ref LL_DMA_CHANNEL_5
1771 * @arg @ref LL_DMA_CHANNEL_6
1772 * @arg @ref LL_DMA_CHANNEL_7
1773 * @arg @ref LL_DMA_CHANNEL_8
1774 * @arg @ref LL_DMA_CHANNEL_9
1775 * @arg @ref LL_DMA_CHANNEL_10
1776 * @arg @ref LL_DMA_CHANNEL_11
1777 * @arg @ref LL_DMA_CHANNEL_12
1778 * @arg @ref LL_DMA_CHANNEL_13
1779 * @arg @ref LL_DMA_CHANNEL_14
1780 * @arg @ref LL_DMA_CHANNEL_15
1781 * @retval None.
1782 */
LL_DMA_SuspendChannel(DMA_TypeDef * DMAx,uint32_t Channel)1783 __STATIC_INLINE void LL_DMA_SuspendChannel(DMA_TypeDef *DMAx, uint32_t Channel)
1784 {
1785 uint32_t dma_base_addr = (uint32_t)DMAx;
1786 SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_SUSP);
1787 }
1788
1789 /**
1790 * @brief Resume channel.
1791 * @note This API is used for all available DMA channels.
1792 * @rmtoll CCR SUSP LL_DMA_ResumeChannel
1793 * @param DMAx DMAx Instance
1794 * @param Channel This parameter can be one of the following values:
1795 * @arg @ref LL_DMA_CHANNEL_0
1796 * @arg @ref LL_DMA_CHANNEL_1
1797 * @arg @ref LL_DMA_CHANNEL_2
1798 * @arg @ref LL_DMA_CHANNEL_3
1799 * @arg @ref LL_DMA_CHANNEL_4
1800 * @arg @ref LL_DMA_CHANNEL_5
1801 * @arg @ref LL_DMA_CHANNEL_6
1802 * @arg @ref LL_DMA_CHANNEL_7
1803 * @arg @ref LL_DMA_CHANNEL_8
1804 * @arg @ref LL_DMA_CHANNEL_9
1805 * @arg @ref LL_DMA_CHANNEL_10
1806 * @arg @ref LL_DMA_CHANNEL_11
1807 * @arg @ref LL_DMA_CHANNEL_12
1808 * @arg @ref LL_DMA_CHANNEL_13
1809 * @arg @ref LL_DMA_CHANNEL_14
1810 * @arg @ref LL_DMA_CHANNEL_15
1811 * @retval None.
1812 */
LL_DMA_ResumeChannel(DMA_TypeDef * DMAx,uint32_t Channel)1813 __STATIC_INLINE void LL_DMA_ResumeChannel(DMA_TypeDef *DMAx, uint32_t Channel)
1814 {
1815 uint32_t dma_base_addr = (uint32_t)DMAx;
1816 CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_SUSP);
1817 }
1818
1819 /**
1820 * @brief Check if channel is suspended.
1821 * @note This API is used for all available DMA channels.
1822 * @rmtoll CCR SUSP LL_DMA_IsSuspendedChannel
1823 * @param DMAx DMAx Instance
1824 * @param Channel This parameter can be one of the following values:
1825 * @arg @ref LL_DMA_CHANNEL_0
1826 * @arg @ref LL_DMA_CHANNEL_1
1827 * @arg @ref LL_DMA_CHANNEL_2
1828 * @arg @ref LL_DMA_CHANNEL_3
1829 * @arg @ref LL_DMA_CHANNEL_4
1830 * @arg @ref LL_DMA_CHANNEL_5
1831 * @arg @ref LL_DMA_CHANNEL_6
1832 * @arg @ref LL_DMA_CHANNEL_7
1833 * @arg @ref LL_DMA_CHANNEL_8
1834 * @arg @ref LL_DMA_CHANNEL_9
1835 * @arg @ref LL_DMA_CHANNEL_10
1836 * @arg @ref LL_DMA_CHANNEL_11
1837 * @arg @ref LL_DMA_CHANNEL_12
1838 * @arg @ref LL_DMA_CHANNEL_13
1839 * @arg @ref LL_DMA_CHANNEL_14
1840 * @arg @ref LL_DMA_CHANNEL_15
1841 * @retval State of bit (1 or 0).
1842 */
LL_DMA_IsSuspendedChannel(DMA_TypeDef * DMAx,uint32_t Channel)1843 __STATIC_INLINE uint32_t LL_DMA_IsSuspendedChannel(DMA_TypeDef *DMAx, uint32_t Channel)
1844 {
1845 uint32_t dma_base_addr = (uint32_t)DMAx;
1846 return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_SUSP)
1847 == (DMA_CCR_SUSP)) ? 1UL : 0UL);
1848 }
1849
1850 /**
1851 * @brief Set linked-list base address.
1852 * @note This API is used for all available DMA channels.
1853 * @rmtoll CLBAR LBA LL_DMA_SetLinkedListBaseAddr
1854 * @param DMAx DMAx Instance
1855 * @param Channel This parameter can be one of the following values:
1856 * @arg @ref LL_DMA_CHANNEL_0
1857 * @arg @ref LL_DMA_CHANNEL_1
1858 * @arg @ref LL_DMA_CHANNEL_2
1859 * @arg @ref LL_DMA_CHANNEL_3
1860 * @arg @ref LL_DMA_CHANNEL_4
1861 * @arg @ref LL_DMA_CHANNEL_5
1862 * @arg @ref LL_DMA_CHANNEL_6
1863 * @arg @ref LL_DMA_CHANNEL_7
1864 * @arg @ref LL_DMA_CHANNEL_8
1865 * @arg @ref LL_DMA_CHANNEL_9
1866 * @arg @ref LL_DMA_CHANNEL_10
1867 * @arg @ref LL_DMA_CHANNEL_11
1868 * @arg @ref LL_DMA_CHANNEL_12
1869 * @arg @ref LL_DMA_CHANNEL_13
1870 * @arg @ref LL_DMA_CHANNEL_14
1871 * @arg @ref LL_DMA_CHANNEL_15
1872 * @param LinkedListBaseAddr Between 0 to 0xFFFF0000 (where the 4 LSB bytes
1873 * are always 0)
1874 * @retval None.
1875 */
LL_DMA_SetLinkedListBaseAddr(DMA_TypeDef * DMAx,uint32_t Channel,uint32_t LinkedListBaseAddr)1876 __STATIC_INLINE void LL_DMA_SetLinkedListBaseAddr(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t LinkedListBaseAddr)
1877 {
1878 uint32_t dma_base_addr = (uint32_t)DMAx;
1879 MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLBAR, DMA_CLBAR_LBA,
1880 (LinkedListBaseAddr & DMA_CLBAR_LBA));
1881 }
1882
1883 /**
1884 * @brief Get linked-list base address.
1885 * @note This API is used for all available DMA channels.
1886 * @rmtoll CLBAR LBA LL_DMA_GetLinkedListBaseAddr
1887 * @param DMAx DMAx Instance
1888 * @param Channel This parameter can be one of the following values:
1889 * @arg @ref LL_DMA_CHANNEL_0
1890 * @arg @ref LL_DMA_CHANNEL_1
1891 * @arg @ref LL_DMA_CHANNEL_2
1892 * @arg @ref LL_DMA_CHANNEL_3
1893 * @arg @ref LL_DMA_CHANNEL_4
1894 * @arg @ref LL_DMA_CHANNEL_5
1895 * @arg @ref LL_DMA_CHANNEL_6
1896 * @arg @ref LL_DMA_CHANNEL_7
1897 * @arg @ref LL_DMA_CHANNEL_8
1898 * @arg @ref LL_DMA_CHANNEL_9
1899 * @arg @ref LL_DMA_CHANNEL_10
1900 * @arg @ref LL_DMA_CHANNEL_11
1901 * @arg @ref LL_DMA_CHANNEL_12
1902 * @arg @ref LL_DMA_CHANNEL_13
1903 * @arg @ref LL_DMA_CHANNEL_14
1904 * @arg @ref LL_DMA_CHANNEL_15
1905 * @retval Value between 0 to 0xFFFF0000 (where the 4 LSB bytes are always 0)
1906 */
LL_DMA_GetLinkedListBaseAddr(DMA_TypeDef * DMAx,uint32_t Channel)1907 __STATIC_INLINE uint32_t LL_DMA_GetLinkedListBaseAddr(DMA_TypeDef *DMAx, uint32_t Channel)
1908 {
1909 uint32_t dma_base_addr = (uint32_t)DMAx;
1910 return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLBAR, DMA_CLBAR_LBA));
1911 }
1912
1913 /**
1914 * @brief Configure all parameters linked to channel control.
1915 * @note This API is used for all available DMA channels.
1916 * For LPDMA channels, LAP field programming is discarded.
1917 * @rmtoll CCR PRIO LL_DMA_ConfigControl\n
1918 * CCR LAP LL_DMA_ConfigControl\n
1919 * CCR LSM LL_DMA_ConfigControl
1920 * @param DMAx DMAx Instance
1921 * @param Channel This parameter can be one of the following values:
1922 * @arg @ref LL_DMA_CHANNEL_0
1923 * @arg @ref LL_DMA_CHANNEL_1
1924 * @arg @ref LL_DMA_CHANNEL_2
1925 * @arg @ref LL_DMA_CHANNEL_3
1926 * @arg @ref LL_DMA_CHANNEL_4
1927 * @arg @ref LL_DMA_CHANNEL_5
1928 * @arg @ref LL_DMA_CHANNEL_6
1929 * @arg @ref LL_DMA_CHANNEL_7
1930 * @arg @ref LL_DMA_CHANNEL_8
1931 * @arg @ref LL_DMA_CHANNEL_9
1932 * @arg @ref LL_DMA_CHANNEL_10
1933 * @arg @ref LL_DMA_CHANNEL_11
1934 * @arg @ref LL_DMA_CHANNEL_12
1935 * @arg @ref LL_DMA_CHANNEL_13
1936 * @arg @ref LL_DMA_CHANNEL_14
1937 * @arg @ref LL_DMA_CHANNEL_15
1938 * @param Configuration This parameter must be a combination of all the following values:
1939 * @arg @ref LL_DMA_LOW_PRIORITY_LOW_WEIGHT or @ref LL_DMA_LOW_PRIORITY_MID_WEIGHT or
1940 * @ref LL_DMA_LOW_PRIORITY_HIGH_WEIGHT or @ref LL_DMA_HIGH_PRIORITY
1941 * @arg @ref LL_DMA_LINK_ALLOCATED_PORT0 or @ref LL_DMA_LINK_ALLOCATED_PORT1
1942 * @arg @ref LL_DMA_LSM_FULL_EXECUTION or @ref LL_DMA_LSM_1LINK_EXECUTION
1943 *@retval None.
1944 */
LL_DMA_ConfigControl(DMA_TypeDef * DMAx,uint32_t Channel,uint32_t Configuration)1945 __STATIC_INLINE void LL_DMA_ConfigControl(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Configuration)
1946 {
1947 uint32_t dma_base_addr = (uint32_t)DMAx;
1948 MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR,
1949 (DMA_CCR_PRIO | DMA_CCR_LAP | DMA_CCR_LSM), Configuration);
1950 }
1951
1952 /**
1953 * @brief Set priority level.
1954 * @note This API is used for all available DMA channels.
1955 * @rmtoll CCR PRIO LL_DMA_SetChannelPriorityLevel
1956 * @param DMAx DMAx Instance
1957 * @param Channel This parameter can be one of the following values:
1958 * @arg @ref LL_DMA_CHANNEL_0
1959 * @arg @ref LL_DMA_CHANNEL_1
1960 * @arg @ref LL_DMA_CHANNEL_2
1961 * @arg @ref LL_DMA_CHANNEL_3
1962 * @arg @ref LL_DMA_CHANNEL_4
1963 * @arg @ref LL_DMA_CHANNEL_5
1964 * @arg @ref LL_DMA_CHANNEL_6
1965 * @arg @ref LL_DMA_CHANNEL_7
1966 * @arg @ref LL_DMA_CHANNEL_8
1967 * @arg @ref LL_DMA_CHANNEL_9
1968 * @arg @ref LL_DMA_CHANNEL_10
1969 * @arg @ref LL_DMA_CHANNEL_11
1970 * @arg @ref LL_DMA_CHANNEL_12
1971 * @arg @ref LL_DMA_CHANNEL_13
1972 * @arg @ref LL_DMA_CHANNEL_14
1973 * @arg @ref LL_DMA_CHANNEL_15
1974 * @param Priority This parameter can be one of the following values:
1975 * @arg @ref LL_DMA_LOW_PRIORITY_LOW_WEIGHT
1976 * @arg @ref LL_DMA_LOW_PRIORITY_MID_WEIGHT
1977 * @arg @ref LL_DMA_LOW_PRIORITY_HIGH_WEIGHT
1978 * @arg @ref LL_DMA_HIGH_PRIORITY
1979 * @retval None.
1980 */
LL_DMA_SetChannelPriorityLevel(DMA_TypeDef * DMAx,uint32_t Channel,uint32_t Priority)1981 __STATIC_INLINE void LL_DMA_SetChannelPriorityLevel(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Priority)
1982 {
1983 uint32_t dma_base_addr = (uint32_t)DMAx;
1984 MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_PRIO, Priority);
1985 }
1986
1987 /**
1988 * @brief Get Channel priority level.
1989 * @note This API is used for all available DMA channels.
1990 * @rmtoll CCR PRIO LL_DMA_GetChannelPriorityLevel
1991 * @param DMAx DMAx Instance
1992 * @param Channel This parameter can be one of the following values:
1993 * @arg @ref LL_DMA_CHANNEL_0
1994 * @arg @ref LL_DMA_CHANNEL_1
1995 * @arg @ref LL_DMA_CHANNEL_2
1996 * @arg @ref LL_DMA_CHANNEL_3
1997 * @arg @ref LL_DMA_CHANNEL_4
1998 * @arg @ref LL_DMA_CHANNEL_5
1999 * @arg @ref LL_DMA_CHANNEL_6
2000 * @arg @ref LL_DMA_CHANNEL_7
2001 * @arg @ref LL_DMA_CHANNEL_8
2002 * @arg @ref LL_DMA_CHANNEL_9
2003 * @arg @ref LL_DMA_CHANNEL_10
2004 * @arg @ref LL_DMA_CHANNEL_11
2005 * @arg @ref LL_DMA_CHANNEL_12
2006 * @arg @ref LL_DMA_CHANNEL_13
2007 * @arg @ref LL_DMA_CHANNEL_14
2008 * @arg @ref LL_DMA_CHANNEL_15
2009 * @retval Returned value can be one of the following values:
2010 * @arg @ref LL_DMA_LOW_PRIORITY_LOW_WEIGHT
2011 * @arg @ref LL_DMA_LOW_PRIORITY_MID_WEIGHT
2012 * @arg @ref LL_DMA_LOW_PRIORITY_HIGH_WEIGHT
2013 * @arg @ref LL_DMA_HIGH_PRIORITY
2014 */
LL_DMA_GetChannelPriorityLevel(DMA_TypeDef * DMAx,uint32_t Channel)2015 __STATIC_INLINE uint32_t LL_DMA_GetChannelPriorityLevel(DMA_TypeDef *DMAx, uint32_t Channel)
2016 {
2017 uint32_t dma_base_addr = (uint32_t)DMAx;
2018 return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_PRIO));
2019 }
2020
2021 /**
2022 * @brief Set linked-list allocated port.
2023 * @note This API is not used for LPDMA channels.
2024 * @rmtoll CCR LAP LL_DMA_SetLinkAllocatedPort
2025 * @param DMAx DMAx Instance
2026 * @param Channel This parameter can be one of the following values:
2027 * @arg @ref LL_DMA_CHANNEL_0
2028 * @arg @ref LL_DMA_CHANNEL_1
2029 * @arg @ref LL_DMA_CHANNEL_2
2030 * @arg @ref LL_DMA_CHANNEL_3
2031 * @arg @ref LL_DMA_CHANNEL_4
2032 * @arg @ref LL_DMA_CHANNEL_5
2033 * @arg @ref LL_DMA_CHANNEL_6
2034 * @arg @ref LL_DMA_CHANNEL_7
2035 * @arg @ref LL_DMA_CHANNEL_8
2036 * @arg @ref LL_DMA_CHANNEL_9
2037 * @arg @ref LL_DMA_CHANNEL_10
2038 * @arg @ref LL_DMA_CHANNEL_11
2039 * @arg @ref LL_DMA_CHANNEL_12
2040 * @arg @ref LL_DMA_CHANNEL_13
2041 * @arg @ref LL_DMA_CHANNEL_14
2042 * @arg @ref LL_DMA_CHANNEL_15
2043 * @param LinkAllocatedPort This parameter can be one of the following values:
2044 * @arg @ref LL_DMA_LINK_ALLOCATED_PORT0
2045 * @arg @ref LL_DMA_LINK_ALLOCATED_PORT1
2046 * @retval None.
2047 */
LL_DMA_SetLinkAllocatedPort(DMA_TypeDef * DMAx,uint32_t Channel,uint32_t LinkAllocatedPort)2048 __STATIC_INLINE void LL_DMA_SetLinkAllocatedPort(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t LinkAllocatedPort)
2049 {
2050 uint32_t dma_base_addr = (uint32_t)DMAx;
2051 MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR,
2052 DMA_CCR_LAP, LinkAllocatedPort);
2053 }
2054
2055 /**
2056 * @brief Get linked-list allocated port.
2057 * @note This API is not used for LPDMA channels.
2058 * @rmtoll CCR LAP LL_DMA_GetLinkAllocatedPort
2059 * @param DMAx DMAx Instance
2060 * @param Channel This parameter can be one of the following values:
2061 * @arg @ref LL_DMA_CHANNEL_0
2062 * @arg @ref LL_DMA_CHANNEL_1
2063 * @arg @ref LL_DMA_CHANNEL_2
2064 * @arg @ref LL_DMA_CHANNEL_3
2065 * @arg @ref LL_DMA_CHANNEL_4
2066 * @arg @ref LL_DMA_CHANNEL_5
2067 * @arg @ref LL_DMA_CHANNEL_6
2068 * @arg @ref LL_DMA_CHANNEL_7
2069 * @arg @ref LL_DMA_CHANNEL_8
2070 * @arg @ref LL_DMA_CHANNEL_9
2071 * @arg @ref LL_DMA_CHANNEL_10
2072 * @arg @ref LL_DMA_CHANNEL_11
2073 * @arg @ref LL_DMA_CHANNEL_12
2074 * @arg @ref LL_DMA_CHANNEL_13
2075 * @arg @ref LL_DMA_CHANNEL_14
2076 * @arg @ref LL_DMA_CHANNEL_15
2077 * @retval Returned value can be one of the following values:
2078 * @arg @ref LL_DMA_LINK_ALLOCATED_PORT0
2079 * @arg @ref LL_DMA_LINK_ALLOCATED_PORT1
2080 */
LL_DMA_GetLinkAllocatedPort(DMA_TypeDef * DMAx,uint32_t Channel)2081 __STATIC_INLINE uint32_t LL_DMA_GetLinkAllocatedPort(DMA_TypeDef *DMAx, uint32_t Channel)
2082 {
2083 uint32_t dma_base_addr = (uint32_t)DMAx;
2084 return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_LAP));
2085 }
2086
2087 /**
2088 * @brief Set link step mode.
2089 * @note This API is used for all available DMA channels.
2090 * @rmtoll CCR LSM LL_DMA_SetLinkStepMode
2091 * @param DMAx DMAx Instance
2092 * @param Channel This parameter can be one of the following values:
2093 * @arg @ref LL_DMA_CHANNEL_0
2094 * @arg @ref LL_DMA_CHANNEL_1
2095 * @arg @ref LL_DMA_CHANNEL_2
2096 * @arg @ref LL_DMA_CHANNEL_3
2097 * @arg @ref LL_DMA_CHANNEL_4
2098 * @arg @ref LL_DMA_CHANNEL_5
2099 * @arg @ref LL_DMA_CHANNEL_6
2100 * @arg @ref LL_DMA_CHANNEL_7
2101 * @arg @ref LL_DMA_CHANNEL_8
2102 * @arg @ref LL_DMA_CHANNEL_9
2103 * @arg @ref LL_DMA_CHANNEL_10
2104 * @arg @ref LL_DMA_CHANNEL_11
2105 * @arg @ref LL_DMA_CHANNEL_12
2106 * @arg @ref LL_DMA_CHANNEL_13
2107 * @arg @ref LL_DMA_CHANNEL_14
2108 * @arg @ref LL_DMA_CHANNEL_15
2109 * @param LinkStepMode This parameter can be one of the following values:
2110 * @arg @ref LL_DMA_LSM_FULL_EXECUTION
2111 * @arg @ref LL_DMA_LSM_1LINK_EXECUTION
2112 * @retval None.
2113 */
LL_DMA_SetLinkStepMode(DMA_TypeDef * DMAx,uint32_t Channel,uint32_t LinkStepMode)2114 __STATIC_INLINE void LL_DMA_SetLinkStepMode(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t LinkStepMode)
2115 {
2116 uint32_t dma_base_addr = (uint32_t)DMAx;
2117 MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_LSM, LinkStepMode);
2118 }
2119
2120 /**
2121 * @brief Get Link step mode.
2122 * @note This API is used for all available DMA channels.
2123 * @rmtoll CCR LSM LL_DMA_GetLinkStepMode
2124 * @param DMAx DMAx Instance
2125 * @param Channel This parameter can be one of the following values:
2126 * @arg @ref LL_DMA_CHANNEL_0
2127 * @arg @ref LL_DMA_CHANNEL_1
2128 * @arg @ref LL_DMA_CHANNEL_2
2129 * @arg @ref LL_DMA_CHANNEL_3
2130 * @arg @ref LL_DMA_CHANNEL_4
2131 * @arg @ref LL_DMA_CHANNEL_5
2132 * @arg @ref LL_DMA_CHANNEL_6
2133 * @arg @ref LL_DMA_CHANNEL_7
2134 * @arg @ref LL_DMA_CHANNEL_8
2135 * @arg @ref LL_DMA_CHANNEL_9
2136 * @arg @ref LL_DMA_CHANNEL_10
2137 * @arg @ref LL_DMA_CHANNEL_11
2138 * @arg @ref LL_DMA_CHANNEL_12
2139 * @arg @ref LL_DMA_CHANNEL_13
2140 * @arg @ref LL_DMA_CHANNEL_14
2141 * @arg @ref LL_DMA_CHANNEL_15
2142 * @retval Returned value can be one of the following values:
2143 * @arg @ref LL_DMA_LSM_FULL_EXECUTION
2144 * @arg @ref LL_DMA_LSM_1LINK_EXECUTION
2145 */
LL_DMA_GetLinkStepMode(DMA_TypeDef * DMAx,uint32_t Channel)2146 __STATIC_INLINE uint32_t LL_DMA_GetLinkStepMode(DMA_TypeDef *DMAx, uint32_t Channel)
2147 {
2148 uint32_t dma_base_addr = (uint32_t)DMAx;
2149 return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_LSM));
2150 }
2151
2152 /**
2153 * @brief Configure data transfer.
2154 * @note This API is used for all available DMA channels.
2155 * For LPDMA channels DAP, DHX, DBX, SAP, SBX fields programming is
2156 * discarded.
2157 * @rmtoll CTR1 DAP LL_DMA_ConfigTransfer\n
2158 * CTR1 DHX LL_DMA_ConfigTransfer\n
2159 * CTR1 DBX LL_DMA_ConfigTransfer\n
2160 * CTR1 DINC LL_DMA_ConfigTransfer\n
2161 * CTR1 SAP LL_DMA_ConfigTransfer\n
2162 * CTR1 SBX LL_DMA_ConfigTransfer\n
2163 * CTR1 PAM LL_DMA_ConfigTransfer\n
2164 * CTR1 SINC LL_DMA_ConfigTransfer
2165 * @param DMAx DMAx Instance
2166 * @param Channel This parameter can be one of the following values:
2167 * @arg @ref LL_DMA_CHANNEL_0
2168 * @arg @ref LL_DMA_CHANNEL_1
2169 * @arg @ref LL_DMA_CHANNEL_2
2170 * @arg @ref LL_DMA_CHANNEL_3
2171 * @arg @ref LL_DMA_CHANNEL_4
2172 * @arg @ref LL_DMA_CHANNEL_5
2173 * @arg @ref LL_DMA_CHANNEL_6
2174 * @arg @ref LL_DMA_CHANNEL_7
2175 * @arg @ref LL_DMA_CHANNEL_8
2176 * @arg @ref LL_DMA_CHANNEL_9
2177 * @arg @ref LL_DMA_CHANNEL_10
2178 * @arg @ref LL_DMA_CHANNEL_11
2179 * @arg @ref LL_DMA_CHANNEL_12
2180 * @arg @ref LL_DMA_CHANNEL_13
2181 * @arg @ref LL_DMA_CHANNEL_14
2182 * @arg @ref LL_DMA_CHANNEL_15
2183 * @param Configuration This parameter must be a combination of all the following values:
2184 * @arg @ref LL_DMA_DEST_ALLOCATED_PORT0 or @ref LL_DMA_DEST_ALLOCATED_PORT1
2185 * @arg @ref LL_DMA_DEST_HALFWORD_PRESERVE or @ref LL_DMA_DEST_HALFWORD_EXCHANGE
2186 * @arg @ref LL_DMA_DEST_BYTE_PRESERVE or @ref LL_DMA_DEST_BYTE_EXCHANGE
2187 * @arg @ref LL_DMA_SRC_BYTE_PRESERVE or @ref LL_DMA_SRC_BYTE_EXCHANGE
2188 * @arg @ref LL_DMA_DEST_FIXED or @ref LL_DMA_DEST_INCREMENT
2189 * @arg @ref LL_DMA_DEST_DATAWIDTH_BYTE or @ref LL_DMA_DEST_DATAWIDTH_HALFWORD or
2190 * @ref LL_DMA_DEST_DATAWIDTH_WORD
2191 * @arg @ref LL_DMA_SRC_ALLOCATED_PORT0 or @ref LL_DMA_SRC_ALLOCATED_PORT1
2192 * @arg @ref LL_DMA_DATA_ALIGN_ZEROPADD or @ref LL_DMA_DATA_ALIGN_SIGNEXTPADD or
2193 * @ref LL_DMA_DATA_PACK_UNPACK
2194 * @arg @ref LL_DMA_SRC_FIXED or @ref LL_DMA_SRC_INCREMENT
2195 * @arg @ref LL_DMA_SRC_DATAWIDTH_BYTE or @ref LL_DMA_SRC_DATAWIDTH_HALFWORD or
2196 * @ref LL_DMA_SRC_DATAWIDTH_WORD
2197 *@retval None.
2198 */
LL_DMA_ConfigTransfer(DMA_TypeDef * DMAx,uint32_t Channel,uint32_t Configuration)2199 __STATIC_INLINE void LL_DMA_ConfigTransfer(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Configuration)
2200 {
2201 uint32_t dma_base_addr = (uint32_t)DMAx;
2202 MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1,
2203 DMA_CTR1_DAP | DMA_CTR1_DHX | DMA_CTR1_DBX | DMA_CTR1_SBX | DMA_CTR1_DINC | DMA_CTR1_SINC | \
2204 DMA_CTR1_SAP | DMA_CTR1_PAM | DMA_CTR1_DDW_LOG2 | DMA_CTR1_SDW_LOG2, Configuration);
2205 }
2206
2207 /**
2208 * @brief Configure source and destination burst length.
2209 * @note This API is not used for LPDMA channels.
2210 * @rmtoll CTR1 DBL_1 LL_DMA_SetDestBurstLength\n
2211 * @rmtoll CTR1 SBL_1 LL_DMA_SetDestBurstLength
2212 * @param DMAx DMAx Instance
2213 * @param Channel This parameter can be one of the following values:
2214 * @arg @ref LL_DMA_CHANNEL_0
2215 * @arg @ref LL_DMA_CHANNEL_1
2216 * @arg @ref LL_DMA_CHANNEL_2
2217 * @arg @ref LL_DMA_CHANNEL_3
2218 * @arg @ref LL_DMA_CHANNEL_4
2219 * @arg @ref LL_DMA_CHANNEL_5
2220 * @arg @ref LL_DMA_CHANNEL_6
2221 * @arg @ref LL_DMA_CHANNEL_7
2222 * @arg @ref LL_DMA_CHANNEL_8
2223 * @arg @ref LL_DMA_CHANNEL_9
2224 * @arg @ref LL_DMA_CHANNEL_10
2225 * @arg @ref LL_DMA_CHANNEL_11
2226 * @arg @ref LL_DMA_CHANNEL_12
2227 * @arg @ref LL_DMA_CHANNEL_13
2228 * @arg @ref LL_DMA_CHANNEL_14
2229 * @arg @ref LL_DMA_CHANNEL_15
2230 * @param SrcBurstLength Between 1 to 64
2231 * @param DestBurstLength Between 1 to 64
2232 * @retval None.
2233 */
LL_DMA_ConfigBurstLength(DMA_TypeDef * DMAx,uint32_t Channel,uint32_t SrcBurstLength,uint32_t DestBurstLength)2234 __STATIC_INLINE void LL_DMA_ConfigBurstLength(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t SrcBurstLength,
2235 uint32_t DestBurstLength)
2236 {
2237 uint32_t dma_base_addr = (uint32_t)DMAx;
2238 MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1,
2239 (DMA_CTR1_SBL_1 | DMA_CTR1_DBL_1), (((SrcBurstLength - 1U) << DMA_CTR1_SBL_1_Pos) & DMA_CTR1_SBL_1) | \
2240 (((DestBurstLength - 1U) << DMA_CTR1_DBL_1_Pos) & DMA_CTR1_DBL_1));
2241 }
2242
2243 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
2244 /**
2245 * @brief Configure all secure parameters linked to DMA channel.
2246 * @note This API is used for all available DMA channels.
2247 * @rmtoll SECCFGR SEC LL_DMA_ConfigChannelSecure\n
2248 * @rmtoll CTR1 SSEC LL_DMA_ConfigChannelSecure\n
2249 * @rmtoll CTR1 DSEC LL_DMA_ConfigChannelSecure
2250 * @param DMAx DMAx Instance
2251 * @param Channel This parameter can be one of the following values:
2252 * @arg @ref LL_DMA_CHANNEL_0
2253 * @arg @ref LL_DMA_CHANNEL_1
2254 * @arg @ref LL_DMA_CHANNEL_2
2255 * @arg @ref LL_DMA_CHANNEL_3
2256 * @arg @ref LL_DMA_CHANNEL_4
2257 * @arg @ref LL_DMA_CHANNEL_5
2258 * @arg @ref LL_DMA_CHANNEL_6
2259 * @arg @ref LL_DMA_CHANNEL_7
2260 * @arg @ref LL_DMA_CHANNEL_8
2261 * @arg @ref LL_DMA_CHANNEL_9
2262 * @arg @ref LL_DMA_CHANNEL_10
2263 * @arg @ref LL_DMA_CHANNEL_11
2264 * @arg @ref LL_DMA_CHANNEL_12
2265 * @arg @ref LL_DMA_CHANNEL_13
2266 * @arg @ref LL_DMA_CHANNEL_14
2267 * @arg @ref LL_DMA_CHANNEL_15
2268 * @param Configuration This parameter must be a combination of all the following values:
2269 * @arg @ref LL_DMA_CHANNEL_NSEC or @ref LL_DMA_CHANNEL_SEC
2270 * @arg @ref LL_DMA_CHANNEL_SRC_NSEC or @ref LL_DMA_CHANNEL_SRC_SEC
2271 * @arg @ref LL_DMA_CHANNEL_DEST_NSEC or @ref LL_DMA_CHANNEL_DEST_SEC
2272 * @retval None.
2273 */
LL_DMA_ConfigChannelSecure(DMA_TypeDef * DMAx,uint32_t Channel,uint32_t Configuration)2274 __STATIC_INLINE void LL_DMA_ConfigChannelSecure(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Configuration)
2275 {
2276 uint32_t dma_base_addr = (uint32_t)DMAx;
2277 MODIFY_REG(DMAx->SECCFGR, (DMA_SECCFGR_SEC0 << Channel), ((Configuration & LL_DMA_CHANNEL_SEC) << Channel));
2278 MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1,
2279 (DMA_CTR1_DSEC | DMA_CTR1_DSEC), (Configuration & (~LL_DMA_CHANNEL_SEC)));
2280 }
2281
2282 /**
2283 * @brief Enable security attribute of the DMA transfer to the destination.
2284 * @note This API is used for all available DMA channels.
2285 * @rmtoll CTR1 DSEC LL_DMA_EnableChannelDestSecure
2286 * @param DMAx DMAx Instance
2287 * @param Channel This parameter can be one of the following values:
2288 * @arg @ref LL_DMA_CHANNEL_0
2289 * @arg @ref LL_DMA_CHANNEL_1
2290 * @arg @ref LL_DMA_CHANNEL_2
2291 * @arg @ref LL_DMA_CHANNEL_3
2292 * @arg @ref LL_DMA_CHANNEL_4
2293 * @arg @ref LL_DMA_CHANNEL_5
2294 * @arg @ref LL_DMA_CHANNEL_6
2295 * @arg @ref LL_DMA_CHANNEL_7
2296 * @arg @ref LL_DMA_CHANNEL_8
2297 * @arg @ref LL_DMA_CHANNEL_9
2298 * @arg @ref LL_DMA_CHANNEL_10
2299 * @arg @ref LL_DMA_CHANNEL_11
2300 * @arg @ref LL_DMA_CHANNEL_12
2301 * @arg @ref LL_DMA_CHANNEL_13
2302 * @arg @ref LL_DMA_CHANNEL_14
2303 * @arg @ref LL_DMA_CHANNEL_15
2304 * @retval None.
2305 */
LL_DMA_EnableChannelDestSecure(DMA_TypeDef * DMAx,uint32_t Channel)2306 __STATIC_INLINE void LL_DMA_EnableChannelDestSecure(DMA_TypeDef *DMAx, uint32_t Channel)
2307 {
2308 uint32_t dma_base_addr = (uint32_t)DMAx;
2309 SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_DSEC);
2310 }
2311
2312 /**
2313 * @brief Disable security attribute of the DMA transfer to the destination.
2314 * @note This API is used for all available DMA channels.
2315 * @rmtoll CTR1 DSEC LL_DMA_DisableChannelDestSecure
2316 * @param DMAx DMAx Instance
2317 * @param Channel This parameter can be one of the following values:
2318 * @arg @ref LL_DMA_CHANNEL_0
2319 * @arg @ref LL_DMA_CHANNEL_1
2320 * @arg @ref LL_DMA_CHANNEL_2
2321 * @arg @ref LL_DMA_CHANNEL_3
2322 * @arg @ref LL_DMA_CHANNEL_4
2323 * @arg @ref LL_DMA_CHANNEL_5
2324 * @arg @ref LL_DMA_CHANNEL_6
2325 * @arg @ref LL_DMA_CHANNEL_7
2326 * @arg @ref LL_DMA_CHANNEL_8
2327 * @arg @ref LL_DMA_CHANNEL_9
2328 * @arg @ref LL_DMA_CHANNEL_10
2329 * @arg @ref LL_DMA_CHANNEL_11
2330 * @arg @ref LL_DMA_CHANNEL_12
2331 * @arg @ref LL_DMA_CHANNEL_13
2332 * @arg @ref LL_DMA_CHANNEL_14
2333 * @arg @ref LL_DMA_CHANNEL_15
2334 * @retval None.
2335 */
LL_DMA_DisableChannelDestSecure(DMA_TypeDef * DMAx,uint32_t Channel)2336 __STATIC_INLINE void LL_DMA_DisableChannelDestSecure(DMA_TypeDef *DMAx, uint32_t Channel)
2337 {
2338 uint32_t dma_base_addr = (uint32_t)DMAx;
2339 CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_DSEC);
2340 }
2341
2342 /**
2343 * @brief Check security attribute of the DMA transfer to the destination.
2344 * @note This API is used for all available DMA channels.
2345 * @rmtoll CTR1 DSEC LL_DMA_IsEnabledChannelDestSecure
2346 * @param DMAx DMAx Instance
2347 * @param Channel This parameter can be one of the following values:
2348 * @arg @ref LL_DMA_CHANNEL_0
2349 * @arg @ref LL_DMA_CHANNEL_1
2350 * @arg @ref LL_DMA_CHANNEL_2
2351 * @arg @ref LL_DMA_CHANNEL_3
2352 * @arg @ref LL_DMA_CHANNEL_4
2353 * @arg @ref LL_DMA_CHANNEL_5
2354 * @arg @ref LL_DMA_CHANNEL_6
2355 * @arg @ref LL_DMA_CHANNEL_7
2356 * @arg @ref LL_DMA_CHANNEL_8
2357 * @arg @ref LL_DMA_CHANNEL_9
2358 * @arg @ref LL_DMA_CHANNEL_10
2359 * @arg @ref LL_DMA_CHANNEL_11
2360 * @arg @ref LL_DMA_CHANNEL_12
2361 * @arg @ref LL_DMA_CHANNEL_13
2362 * @arg @ref LL_DMA_CHANNEL_14
2363 * @arg @ref LL_DMA_CHANNEL_15
2364 * @retval State of bit (1 or 0).
2365 */
LL_DMA_IsEnabledChannelDestSecure(DMA_TypeDef * DMAx,uint32_t Channel)2366 __STATIC_INLINE uint32_t LL_DMA_IsEnabledChannelDestSecure(DMA_TypeDef *DMAx, uint32_t Channel)
2367 {
2368 uint32_t dma_base_addr = (uint32_t)DMAx;
2369 return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_DSEC)
2370 == (DMA_CTR1_DSEC)) ? 1UL : 0UL);
2371 }
2372
2373 /**
2374 * @brief Enable security attribute of the DMA transfer from the source.
2375 * @note This API is used for all available DMA channels.
2376 * @rmtoll CTR1 SSEC LL_DMA_EnableChannelSrcSecure
2377 * @param DMAx DMAx Instance
2378 * @param Channel This parameter can be one of the following values:
2379 * @arg @ref LL_DMA_CHANNEL_0
2380 * @arg @ref LL_DMA_CHANNEL_1
2381 * @arg @ref LL_DMA_CHANNEL_2
2382 * @arg @ref LL_DMA_CHANNEL_3
2383 * @arg @ref LL_DMA_CHANNEL_4
2384 * @arg @ref LL_DMA_CHANNEL_5
2385 * @arg @ref LL_DMA_CHANNEL_6
2386 * @arg @ref LL_DMA_CHANNEL_7
2387 * @arg @ref LL_DMA_CHANNEL_8
2388 * @arg @ref LL_DMA_CHANNEL_9
2389 * @arg @ref LL_DMA_CHANNEL_10
2390 * @arg @ref LL_DMA_CHANNEL_11
2391 * @arg @ref LL_DMA_CHANNEL_12
2392 * @arg @ref LL_DMA_CHANNEL_13
2393 * @arg @ref LL_DMA_CHANNEL_14
2394 * @arg @ref LL_DMA_CHANNEL_15
2395 * @retval None.
2396 */
LL_DMA_EnableChannelSrcSecure(DMA_TypeDef * DMAx,uint32_t Channel)2397 __STATIC_INLINE void LL_DMA_EnableChannelSrcSecure(DMA_TypeDef *DMAx, uint32_t Channel)
2398 {
2399 uint32_t dma_base_addr = (uint32_t)DMAx;
2400 SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_SSEC);
2401 }
2402
2403 /**
2404 * @brief Disable security attribute of the DMA transfer from the source.
2405 * @note This API is used for all available DMA channels.
2406 * @rmtoll CTR1 SSEC LL_DMA_DisableChannelSrcSecure
2407 * @param DMAx DMAx Instance
2408 * @param Channel This parameter can be one of the following values:
2409 * @arg @ref LL_DMA_CHANNEL_0
2410 * @arg @ref LL_DMA_CHANNEL_1
2411 * @arg @ref LL_DMA_CHANNEL_2
2412 * @arg @ref LL_DMA_CHANNEL_3
2413 * @arg @ref LL_DMA_CHANNEL_4
2414 * @arg @ref LL_DMA_CHANNEL_5
2415 * @arg @ref LL_DMA_CHANNEL_6
2416 * @arg @ref LL_DMA_CHANNEL_7
2417 * @arg @ref LL_DMA_CHANNEL_8
2418 * @arg @ref LL_DMA_CHANNEL_9
2419 * @arg @ref LL_DMA_CHANNEL_10
2420 * @arg @ref LL_DMA_CHANNEL_11
2421 * @arg @ref LL_DMA_CHANNEL_12
2422 * @arg @ref LL_DMA_CHANNEL_13
2423 * @arg @ref LL_DMA_CHANNEL_14
2424 * @arg @ref LL_DMA_CHANNEL_15
2425 * @retval None.
2426 */
LL_DMA_DisableChannelSrcSecure(DMA_TypeDef * DMAx,uint32_t Channel)2427 __STATIC_INLINE void LL_DMA_DisableChannelSrcSecure(DMA_TypeDef *DMAx, uint32_t Channel)
2428 {
2429 uint32_t dma_base_addr = (uint32_t)DMAx;
2430 CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_SSEC);
2431 }
2432
2433 /**
2434 * @brief Check security attribute of the DMA transfer from the source.
2435 * @note This API is used for all available DMA channels.
2436 * @rmtoll CTR1 SSEC LL_DMA_IsEnabledChannelSrcSecure
2437 * @param DMAx DMAx Instance
2438 * @param Channel This parameter can be one of the following values:
2439 * @arg @ref LL_DMA_CHANNEL_0
2440 * @arg @ref LL_DMA_CHANNEL_1
2441 * @arg @ref LL_DMA_CHANNEL_2
2442 * @arg @ref LL_DMA_CHANNEL_3
2443 * @arg @ref LL_DMA_CHANNEL_4
2444 * @arg @ref LL_DMA_CHANNEL_5
2445 * @arg @ref LL_DMA_CHANNEL_6
2446 * @arg @ref LL_DMA_CHANNEL_7
2447 * @arg @ref LL_DMA_CHANNEL_8
2448 * @arg @ref LL_DMA_CHANNEL_9
2449 * @arg @ref LL_DMA_CHANNEL_10
2450 * @arg @ref LL_DMA_CHANNEL_11
2451 * @arg @ref LL_DMA_CHANNEL_12
2452 * @arg @ref LL_DMA_CHANNEL_13
2453 * @arg @ref LL_DMA_CHANNEL_14
2454 * @arg @ref LL_DMA_CHANNEL_15
2455 * @retval State of bit (1 or 0).
2456 */
LL_DMA_IsEnabledChannelSrcSecure(DMA_TypeDef * DMAx,uint32_t Channel)2457 __STATIC_INLINE uint32_t LL_DMA_IsEnabledChannelSrcSecure(DMA_TypeDef *DMAx, uint32_t Channel)
2458 {
2459 uint32_t dma_base_addr = (uint32_t)DMAx;
2460 return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_SSEC)
2461 == (DMA_CTR1_SSEC)) ? 1UL : 0UL);
2462 }
2463 #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
2464
2465 /**
2466 * @brief Set destination allocated port.
2467 * @note This API is not used for LPDMA channels.
2468 * @rmtoll CTR1 DAP LL_DMA_SetDestAllocatedPort
2469 * @param DMAx DMAx Instance
2470 * @param Channel This parameter can be one of the following values:
2471 * @arg @ref LL_DMA_CHANNEL_0
2472 * @arg @ref LL_DMA_CHANNEL_1
2473 * @arg @ref LL_DMA_CHANNEL_2
2474 * @arg @ref LL_DMA_CHANNEL_3
2475 * @arg @ref LL_DMA_CHANNEL_4
2476 * @arg @ref LL_DMA_CHANNEL_5
2477 * @arg @ref LL_DMA_CHANNEL_6
2478 * @arg @ref LL_DMA_CHANNEL_7
2479 * @arg @ref LL_DMA_CHANNEL_8
2480 * @arg @ref LL_DMA_CHANNEL_9
2481 * @arg @ref LL_DMA_CHANNEL_10
2482 * @arg @ref LL_DMA_CHANNEL_11
2483 * @arg @ref LL_DMA_CHANNEL_12
2484 * @arg @ref LL_DMA_CHANNEL_13
2485 * @arg @ref LL_DMA_CHANNEL_14
2486 * @arg @ref LL_DMA_CHANNEL_15
2487 * @param DestAllocatedPort This parameter can be one of the following values:
2488 * @arg @ref LL_DMA_DEST_ALLOCATED_PORT0
2489 * @arg @ref LL_DMA_DEST_ALLOCATED_PORT1
2490 * @retval None.
2491 */
LL_DMA_SetDestAllocatedPort(DMA_TypeDef * DMAx,uint32_t Channel,uint32_t DestAllocatedPort)2492 __STATIC_INLINE void LL_DMA_SetDestAllocatedPort(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t DestAllocatedPort)
2493 {
2494 uint32_t dma_base_addr = (uint32_t)DMAx;
2495 MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_DAP,
2496 DestAllocatedPort);
2497 }
2498
2499 /**
2500 * @brief Get destination allocated port.
2501 * @note This API is not used for LPDMA channels.
2502 * @rmtoll CTR1 DAP LL_DMA_GetDestAllocatedPort
2503 * @param DMAx DMAx Instance
2504 * @param Channel This parameter can be one of the following values:
2505 * @arg @ref LL_DMA_CHANNEL_0
2506 * @arg @ref LL_DMA_CHANNEL_1
2507 * @arg @ref LL_DMA_CHANNEL_2
2508 * @arg @ref LL_DMA_CHANNEL_3
2509 * @arg @ref LL_DMA_CHANNEL_4
2510 * @arg @ref LL_DMA_CHANNEL_5
2511 * @arg @ref LL_DMA_CHANNEL_6
2512 * @arg @ref LL_DMA_CHANNEL_7
2513 * @arg @ref LL_DMA_CHANNEL_8
2514 * @arg @ref LL_DMA_CHANNEL_9
2515 * @arg @ref LL_DMA_CHANNEL_10
2516 * @arg @ref LL_DMA_CHANNEL_11
2517 * @arg @ref LL_DMA_CHANNEL_12
2518 * @arg @ref LL_DMA_CHANNEL_13
2519 * @arg @ref LL_DMA_CHANNEL_14
2520 * @arg @ref LL_DMA_CHANNEL_15
2521 * @retval Returned value can be one of the following values:
2522 * @arg @ref LL_DMA_DEST_ALLOCATED_PORT0
2523 * @arg @ref LL_DMA_DEST_ALLOCATED_PORT1
2524 */
LL_DMA_GetDestAllocatedPort(DMA_TypeDef * DMAx,uint32_t Channel)2525 __STATIC_INLINE uint32_t LL_DMA_GetDestAllocatedPort(DMA_TypeDef *DMAx, uint32_t Channel)
2526 {
2527 uint32_t dma_base_addr = (uint32_t)DMAx;
2528 return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_DAP));
2529 }
2530
2531 /**
2532 * @brief Set destination half-word exchange.
2533 * @note This API is not used for LPDMA channels.
2534 * @rmtoll CTR1 DHX LL_DMA_SetDestHWordExchange
2535 * @param DMAx DMAx Instance
2536 * @param Channel This parameter can be one of the following values:
2537 * @arg @ref LL_DMA_CHANNEL_0
2538 * @arg @ref LL_DMA_CHANNEL_1
2539 * @arg @ref LL_DMA_CHANNEL_2
2540 * @arg @ref LL_DMA_CHANNEL_3
2541 * @arg @ref LL_DMA_CHANNEL_4
2542 * @arg @ref LL_DMA_CHANNEL_5
2543 * @arg @ref LL_DMA_CHANNEL_6
2544 * @arg @ref LL_DMA_CHANNEL_7
2545 * @arg @ref LL_DMA_CHANNEL_8
2546 * @arg @ref LL_DMA_CHANNEL_9
2547 * @arg @ref LL_DMA_CHANNEL_10
2548 * @arg @ref LL_DMA_CHANNEL_11
2549 * @arg @ref LL_DMA_CHANNEL_12
2550 * @arg @ref LL_DMA_CHANNEL_13
2551 * @arg @ref LL_DMA_CHANNEL_14
2552 * @arg @ref LL_DMA_CHANNEL_15
2553 * @param DestHWordExchange This parameter can be one of the following values:
2554 * @arg @ref LL_DMA_DEST_HALFWORD_PRESERVE
2555 * @arg @ref LL_DMA_DEST_HALFWORD_EXCHANGE
2556 * @retval None.
2557 */
LL_DMA_SetDestHWordExchange(DMA_TypeDef * DMAx,uint32_t Channel,uint32_t DestHWordExchange)2558 __STATIC_INLINE void LL_DMA_SetDestHWordExchange(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t DestHWordExchange)
2559 {
2560 uint32_t dma_base_addr = (uint32_t)DMAx;
2561 MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_DHX,
2562 DestHWordExchange);
2563 }
2564
2565 /**
2566 * @brief Get destination half-word exchange.
2567 * @note This API is not used for LPDMA channels.
2568 * @rmtoll CTR1 DHX LL_DMA_GetDestHWordExchange
2569 * @param DMAx DMAx Instance
2570 * @param Channel This parameter can be one of the following values:
2571 * @arg @ref LL_DMA_CHANNEL_0
2572 * @arg @ref LL_DMA_CHANNEL_1
2573 * @arg @ref LL_DMA_CHANNEL_2
2574 * @arg @ref LL_DMA_CHANNEL_3
2575 * @arg @ref LL_DMA_CHANNEL_4
2576 * @arg @ref LL_DMA_CHANNEL_5
2577 * @arg @ref LL_DMA_CHANNEL_6
2578 * @arg @ref LL_DMA_CHANNEL_7
2579 * @arg @ref LL_DMA_CHANNEL_8
2580 * @arg @ref LL_DMA_CHANNEL_9
2581 * @arg @ref LL_DMA_CHANNEL_10
2582 * @arg @ref LL_DMA_CHANNEL_11
2583 * @arg @ref LL_DMA_CHANNEL_12
2584 * @arg @ref LL_DMA_CHANNEL_13
2585 * @arg @ref LL_DMA_CHANNEL_14
2586 * @arg @ref LL_DMA_CHANNEL_15
2587 * @retval Returned value can be one of the following values:
2588 * @arg @ref LL_DMA_DEST_HALFWORD_PRESERVE
2589 * @arg @ref LL_DMA_DEST_HALFWORD_EXCHANGE
2590 */
LL_DMA_GetDestHWordExchange(DMA_TypeDef * DMAx,uint32_t Channel)2591 __STATIC_INLINE uint32_t LL_DMA_GetDestHWordExchange(DMA_TypeDef *DMAx, uint32_t Channel)
2592 {
2593 uint32_t dma_base_addr = (uint32_t)DMAx;
2594 return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_DHX));
2595 }
2596
2597 /**
2598 * @brief Set destination byte exchange.
2599 * @note This API is not used for LPDMA channels.
2600 * @rmtoll CTR1 DBX LL_DMA_SetDestByteExchange
2601 * @param DMAx DMAx Instance
2602 * @param Channel This parameter can be one of the following values:
2603 * @arg @ref LL_DMA_CHANNEL_0
2604 * @arg @ref LL_DMA_CHANNEL_1
2605 * @arg @ref LL_DMA_CHANNEL_2
2606 * @arg @ref LL_DMA_CHANNEL_3
2607 * @arg @ref LL_DMA_CHANNEL_4
2608 * @arg @ref LL_DMA_CHANNEL_5
2609 * @arg @ref LL_DMA_CHANNEL_6
2610 * @arg @ref LL_DMA_CHANNEL_7
2611 * @arg @ref LL_DMA_CHANNEL_8
2612 * @arg @ref LL_DMA_CHANNEL_9
2613 * @arg @ref LL_DMA_CHANNEL_10
2614 * @arg @ref LL_DMA_CHANNEL_11
2615 * @arg @ref LL_DMA_CHANNEL_12
2616 * @arg @ref LL_DMA_CHANNEL_13
2617 * @arg @ref LL_DMA_CHANNEL_14
2618 * @arg @ref LL_DMA_CHANNEL_15
2619 * @param DestByteExchange This parameter can be one of the following values:
2620 * @arg @ref LL_DMA_DEST_BYTE_PRESERVE
2621 * @arg @ref LL_DMA_DEST_BYTE_EXCHANGE
2622 * @retval None.
2623 */
LL_DMA_SetDestByteExchange(DMA_TypeDef * DMAx,uint32_t Channel,uint32_t DestByteExchange)2624 __STATIC_INLINE void LL_DMA_SetDestByteExchange(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t DestByteExchange)
2625 {
2626 uint32_t dma_base_addr = (uint32_t)DMAx;
2627 MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_DBX,
2628 DestByteExchange);
2629 }
2630
2631 /**
2632 * @brief Get destination byte exchange.
2633 * @note This API is not used for LPDMA channels.
2634 * @rmtoll CTR1 DBX LL_DMA_GetDestByteExchange
2635 * @param DMAx DMAx Instance
2636 * @param Channel This parameter can be one of the following values:
2637 * @arg @ref LL_DMA_CHANNEL_0
2638 * @arg @ref LL_DMA_CHANNEL_1
2639 * @arg @ref LL_DMA_CHANNEL_2
2640 * @arg @ref LL_DMA_CHANNEL_3
2641 * @arg @ref LL_DMA_CHANNEL_4
2642 * @arg @ref LL_DMA_CHANNEL_5
2643 * @arg @ref LL_DMA_CHANNEL_6
2644 * @arg @ref LL_DMA_CHANNEL_7
2645 * @arg @ref LL_DMA_CHANNEL_8
2646 * @arg @ref LL_DMA_CHANNEL_9
2647 * @arg @ref LL_DMA_CHANNEL_10
2648 * @arg @ref LL_DMA_CHANNEL_11
2649 * @arg @ref LL_DMA_CHANNEL_12
2650 * @arg @ref LL_DMA_CHANNEL_13
2651 * @arg @ref LL_DMA_CHANNEL_14
2652 * @arg @ref LL_DMA_CHANNEL_15
2653 * @retval Returned value can be one of the following values:
2654 * @arg @ref LL_DMA_DEST_BYTE_PRESERVE
2655 * @arg @ref LL_DMA_DEST_BYTE_EXCHANGE
2656 */
LL_DMA_GetDestByteExchange(DMA_TypeDef * DMAx,uint32_t Channel)2657 __STATIC_INLINE uint32_t LL_DMA_GetDestByteExchange(DMA_TypeDef *DMAx, uint32_t Channel)
2658 {
2659 uint32_t dma_base_addr = (uint32_t)DMAx;
2660 return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_DBX));
2661 }
2662
2663 /**
2664 * @brief Set source byte exchange.
2665 * @note This API is not used for LPDMA channels.
2666 * @rmtoll CTR1 SBX LL_DMA_SetSrcByteExchange
2667 * @param DMAx DMAx Instance
2668 * @param Channel This parameter can be one of the following values:
2669 * @arg @ref LL_DMA_CHANNEL_0
2670 * @arg @ref LL_DMA_CHANNEL_1
2671 * @arg @ref LL_DMA_CHANNEL_2
2672 * @arg @ref LL_DMA_CHANNEL_3
2673 * @arg @ref LL_DMA_CHANNEL_4
2674 * @arg @ref LL_DMA_CHANNEL_5
2675 * @arg @ref LL_DMA_CHANNEL_6
2676 * @arg @ref LL_DMA_CHANNEL_7
2677 * @arg @ref LL_DMA_CHANNEL_8
2678 * @arg @ref LL_DMA_CHANNEL_9
2679 * @arg @ref LL_DMA_CHANNEL_10
2680 * @arg @ref LL_DMA_CHANNEL_11
2681 * @arg @ref LL_DMA_CHANNEL_12
2682 * @arg @ref LL_DMA_CHANNEL_13
2683 * @arg @ref LL_DMA_CHANNEL_14
2684 * @arg @ref LL_DMA_CHANNEL_15
2685 * @param SrcByteExchange This parameter can be one of the following values:
2686 * @arg @ref LL_DMA_SRC_BYTE_PRESERVE
2687 * @arg @ref LL_DMA_SRC_BYTE_EXCHANGE
2688 * @retval None.
2689 */
LL_DMA_SetSrcByteExchange(DMA_TypeDef * DMAx,uint32_t Channel,uint32_t SrcByteExchange)2690 __STATIC_INLINE void LL_DMA_SetSrcByteExchange(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t SrcByteExchange)
2691 {
2692 uint32_t dma_base_addr = (uint32_t)DMAx;
2693 MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_SBX,
2694 SrcByteExchange);
2695 }
2696
2697 /**
2698 * @brief Get source byte exchange.
2699 * @note This API is not used for LPDMA channels.
2700 * @rmtoll CTR1 SBX LL_DMA_GetSrcByteExchange
2701 * @param DMAx DMAx Instance
2702 * @param Channel This parameter can be one of the following values:
2703 * @arg @ref LL_DMA_CHANNEL_0
2704 * @arg @ref LL_DMA_CHANNEL_1
2705 * @arg @ref LL_DMA_CHANNEL_2
2706 * @arg @ref LL_DMA_CHANNEL_3
2707 * @arg @ref LL_DMA_CHANNEL_4
2708 * @arg @ref LL_DMA_CHANNEL_5
2709 * @arg @ref LL_DMA_CHANNEL_6
2710 * @arg @ref LL_DMA_CHANNEL_7
2711 * @arg @ref LL_DMA_CHANNEL_8
2712 * @arg @ref LL_DMA_CHANNEL_9
2713 * @arg @ref LL_DMA_CHANNEL_10
2714 * @arg @ref LL_DMA_CHANNEL_11
2715 * @arg @ref LL_DMA_CHANNEL_12
2716 * @arg @ref LL_DMA_CHANNEL_13
2717 * @arg @ref LL_DMA_CHANNEL_14
2718 * @arg @ref LL_DMA_CHANNEL_15
2719 * @retval Returned value can be one of the following values:
2720 * @arg @ref LL_DMA_SRC_BYTE_PRESERVE
2721 * @arg @ref LL_DMA_SRC_BYTE_EXCHANGE
2722 */
LL_DMA_GetSrcByteExchange(DMA_TypeDef * DMAx,uint32_t Channel)2723 __STATIC_INLINE uint32_t LL_DMA_GetSrcByteExchange(DMA_TypeDef *DMAx, uint32_t Channel)
2724 {
2725 uint32_t dma_base_addr = (uint32_t)DMAx;
2726 return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_SBX));
2727 }
2728
2729 /**
2730 * @brief Set destination burst length.
2731 * @note This API is not used for LPDMA channels.
2732 * @rmtoll CTR1 DBL_1 LL_DMA_SetDestBurstLength
2733 * @param DMAx DMAx Instance
2734 * @param Channel This parameter can be one of the following values:
2735 * @arg @ref LL_DMA_CHANNEL_0
2736 * @arg @ref LL_DMA_CHANNEL_1
2737 * @arg @ref LL_DMA_CHANNEL_2
2738 * @arg @ref LL_DMA_CHANNEL_3
2739 * @arg @ref LL_DMA_CHANNEL_4
2740 * @arg @ref LL_DMA_CHANNEL_5
2741 * @arg @ref LL_DMA_CHANNEL_6
2742 * @arg @ref LL_DMA_CHANNEL_7
2743 * @arg @ref LL_DMA_CHANNEL_8
2744 * @arg @ref LL_DMA_CHANNEL_9
2745 * @arg @ref LL_DMA_CHANNEL_10
2746 * @arg @ref LL_DMA_CHANNEL_11
2747 * @arg @ref LL_DMA_CHANNEL_12
2748 * @arg @ref LL_DMA_CHANNEL_13
2749 * @arg @ref LL_DMA_CHANNEL_14
2750 * @arg @ref LL_DMA_CHANNEL_15
2751 * @param DestBurstLength Between 1 to 64
2752 * @retval None.
2753 */
LL_DMA_SetDestBurstLength(DMA_TypeDef * DMAx,uint32_t Channel,uint32_t DestBurstLength)2754 __STATIC_INLINE void LL_DMA_SetDestBurstLength(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t DestBurstLength)
2755 {
2756 uint32_t dma_base_addr = (uint32_t)DMAx;
2757 MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_DBL_1,
2758 ((DestBurstLength - 1U) << DMA_CTR1_DBL_1_Pos) & DMA_CTR1_DBL_1);
2759 }
2760
2761 /**
2762 * @brief Get destination burst length.
2763 * @note This API is not used for LPDMA channels.
2764 * @rmtoll CTR1 DBL_1 LL_DMA_GetDestBurstLength
2765 * @param DMAx DMAx Instance
2766 * @param Channel This parameter can be one of the following values:
2767 * @arg @ref LL_DMA_CHANNEL_0
2768 * @arg @ref LL_DMA_CHANNEL_1
2769 * @arg @ref LL_DMA_CHANNEL_2
2770 * @arg @ref LL_DMA_CHANNEL_3
2771 * @arg @ref LL_DMA_CHANNEL_4
2772 * @arg @ref LL_DMA_CHANNEL_5
2773 * @arg @ref LL_DMA_CHANNEL_6
2774 * @arg @ref LL_DMA_CHANNEL_7
2775 * @arg @ref LL_DMA_CHANNEL_8
2776 * @arg @ref LL_DMA_CHANNEL_9
2777 * @arg @ref LL_DMA_CHANNEL_10
2778 * @arg @ref LL_DMA_CHANNEL_11
2779 * @arg @ref LL_DMA_CHANNEL_12
2780 * @arg @ref LL_DMA_CHANNEL_13
2781 * @arg @ref LL_DMA_CHANNEL_14
2782 * @arg @ref LL_DMA_CHANNEL_15
2783 * @retval Between 1 to 64.
2784 */
LL_DMA_GetDestBurstLength(DMA_TypeDef * DMAx,uint32_t Channel)2785 __STATIC_INLINE uint32_t LL_DMA_GetDestBurstLength(DMA_TypeDef *DMAx, uint32_t Channel)
2786 {
2787 uint32_t dma_base_addr = (uint32_t)DMAx;
2788 return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1,
2789 DMA_CTR1_DBL_1) >> DMA_CTR1_DBL_1_Pos) + 1U);
2790 }
2791
2792 /**
2793 * @brief Set destination increment mode.
2794 * @note This API is not used for LPDMA channels.
2795 * @rmtoll CTR1 DINC LL_DMA_SetDestIncMode
2796 * @param DMAx DMAx Instance
2797 * @param Channel This parameter can be one of the following values:
2798 * @arg @ref LL_DMA_CHANNEL_0
2799 * @arg @ref LL_DMA_CHANNEL_1
2800 * @arg @ref LL_DMA_CHANNEL_2
2801 * @arg @ref LL_DMA_CHANNEL_3
2802 * @arg @ref LL_DMA_CHANNEL_4
2803 * @arg @ref LL_DMA_CHANNEL_5
2804 * @arg @ref LL_DMA_CHANNEL_6
2805 * @arg @ref LL_DMA_CHANNEL_7
2806 * @arg @ref LL_DMA_CHANNEL_8
2807 * @arg @ref LL_DMA_CHANNEL_9
2808 * @arg @ref LL_DMA_CHANNEL_10
2809 * @arg @ref LL_DMA_CHANNEL_11
2810 * @arg @ref LL_DMA_CHANNEL_12
2811 * @arg @ref LL_DMA_CHANNEL_13
2812 * @arg @ref LL_DMA_CHANNEL_14
2813 * @arg @ref LL_DMA_CHANNEL_15
2814 * @param DestInc This parameter can be one of the following values:
2815 * @arg @ref LL_DMA_DEST_FIXED
2816 * @arg @ref LL_DMA_DEST_INCREMENT
2817 * @retval None.
2818 */
LL_DMA_SetDestIncMode(DMA_TypeDef * DMAx,uint32_t Channel,uint32_t DestInc)2819 __STATIC_INLINE void LL_DMA_SetDestIncMode(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t DestInc)
2820 {
2821 uint32_t dma_base_addr = (uint32_t)DMAx;
2822 MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_DINC, DestInc);
2823 }
2824
2825 /**
2826 * @brief Get destination increment mode.
2827 * @note This API is used for all available DMA channels.
2828 * @rmtoll CTR1 DINC LL_DMA_GetDestIncMode
2829 * @param DMAx DMAx Instance
2830 * @param Channel This parameter can be one of the following values:
2831 * @arg @ref LL_DMA_CHANNEL_0
2832 * @arg @ref LL_DMA_CHANNEL_1
2833 * @arg @ref LL_DMA_CHANNEL_2
2834 * @arg @ref LL_DMA_CHANNEL_3
2835 * @arg @ref LL_DMA_CHANNEL_4
2836 * @arg @ref LL_DMA_CHANNEL_5
2837 * @arg @ref LL_DMA_CHANNEL_6
2838 * @arg @ref LL_DMA_CHANNEL_7
2839 * @arg @ref LL_DMA_CHANNEL_8
2840 * @arg @ref LL_DMA_CHANNEL_9
2841 * @arg @ref LL_DMA_CHANNEL_10
2842 * @arg @ref LL_DMA_CHANNEL_11
2843 * @arg @ref LL_DMA_CHANNEL_12
2844 * @arg @ref LL_DMA_CHANNEL_13
2845 * @arg @ref LL_DMA_CHANNEL_14
2846 * @arg @ref LL_DMA_CHANNEL_15
2847 * @retval Returned value can be one of the following values:
2848 * @arg @ref LL_DMA_DEST_FIXED
2849 * @arg @ref LL_DMA_DEST_INCREMENT
2850 */
LL_DMA_GetDestIncMode(DMA_TypeDef * DMAx,uint32_t Channel)2851 __STATIC_INLINE uint32_t LL_DMA_GetDestIncMode(DMA_TypeDef *DMAx, uint32_t Channel)
2852 {
2853 uint32_t dma_base_addr = (uint32_t)DMAx;
2854 return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_DINC));
2855 }
2856
2857 /**
2858 * @brief Set destination data width.
2859 * @note This API is used for all available DMA channels.
2860 * @rmtoll CTR1 DDW_LOG2 LL_DMA_SetDestDataWidth
2861 * @param DMAx DMAx Instance
2862 * @param Channel This parameter can be one of the following values:
2863 * @arg @ref LL_DMA_CHANNEL_0
2864 * @arg @ref LL_DMA_CHANNEL_1
2865 * @arg @ref LL_DMA_CHANNEL_2
2866 * @arg @ref LL_DMA_CHANNEL_3
2867 * @arg @ref LL_DMA_CHANNEL_4
2868 * @arg @ref LL_DMA_CHANNEL_5
2869 * @arg @ref LL_DMA_CHANNEL_6
2870 * @arg @ref LL_DMA_CHANNEL_7
2871 * @arg @ref LL_DMA_CHANNEL_8
2872 * @arg @ref LL_DMA_CHANNEL_9
2873 * @arg @ref LL_DMA_CHANNEL_10
2874 * @arg @ref LL_DMA_CHANNEL_11
2875 * @arg @ref LL_DMA_CHANNEL_12
2876 * @arg @ref LL_DMA_CHANNEL_13
2877 * @arg @ref LL_DMA_CHANNEL_14
2878 * @arg @ref LL_DMA_CHANNEL_15
2879 * @param DestDataWidth This parameter can be one of the following values:
2880 * @arg @ref LL_DMA_DEST_DATAWIDTH_BYTE
2881 * @arg @ref LL_DMA_DEST_DATAWIDTH_HALFWORD
2882 * @arg @ref LL_DMA_DEST_DATAWIDTH_WORD
2883 * @retval None.
2884 */
LL_DMA_SetDestDataWidth(DMA_TypeDef * DMAx,uint32_t Channel,uint32_t DestDataWidth)2885 __STATIC_INLINE void LL_DMA_SetDestDataWidth(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t DestDataWidth)
2886 {
2887 uint32_t dma_base_addr = (uint32_t)DMAx;
2888 MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_DDW_LOG2,
2889 DestDataWidth);
2890 }
2891
2892 /**
2893 * @brief Get destination data width.
2894 * @note This API is used for all available DMA channels.
2895 * @rmtoll CTR1 DDW_LOG2 LL_DMA_GetDestDataWidth
2896 * @param DMAx DMAx Instance
2897 * @param Channel This parameter can be one of the following values:
2898 * @arg @ref LL_DMA_CHANNEL_0
2899 * @arg @ref LL_DMA_CHANNEL_1
2900 * @arg @ref LL_DMA_CHANNEL_2
2901 * @arg @ref LL_DMA_CHANNEL_3
2902 * @arg @ref LL_DMA_CHANNEL_4
2903 * @arg @ref LL_DMA_CHANNEL_5
2904 * @arg @ref LL_DMA_CHANNEL_6
2905 * @arg @ref LL_DMA_CHANNEL_7
2906 * @arg @ref LL_DMA_CHANNEL_8
2907 * @arg @ref LL_DMA_CHANNEL_9
2908 * @arg @ref LL_DMA_CHANNEL_10
2909 * @arg @ref LL_DMA_CHANNEL_11
2910 * @arg @ref LL_DMA_CHANNEL_12
2911 * @arg @ref LL_DMA_CHANNEL_13
2912 * @arg @ref LL_DMA_CHANNEL_14
2913 * @arg @ref LL_DMA_CHANNEL_15
2914 * @retval Returned value can be one of the following values:
2915 * @arg @ref LL_DMA_DEST_DATAWIDTH_BYTE
2916 * @arg @ref LL_DMA_DEST_DATAWIDTH_HALFWORD
2917 * @arg @ref LL_DMA_DEST_DATAWIDTH_WORD
2918 */
LL_DMA_GetDestDataWidth(DMA_TypeDef * DMAx,uint32_t Channel)2919 __STATIC_INLINE uint32_t LL_DMA_GetDestDataWidth(DMA_TypeDef *DMAx, uint32_t Channel)
2920 {
2921 uint32_t dma_base_addr = (uint32_t)DMAx;
2922 return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_DDW_LOG2));
2923 }
2924
2925 /**
2926 * @brief Set source allocated port.
2927 * @note This API is not used for LPDMA channels.
2928 * @rmtoll CTR1 SAP LL_DMA_SetSrcAllocatedPort
2929 * @param DMAx DMAx Instance
2930 * @param Channel This parameter can be one of the following values:
2931 * @arg @ref LL_DMA_CHANNEL_0
2932 * @arg @ref LL_DMA_CHANNEL_1
2933 * @arg @ref LL_DMA_CHANNEL_2
2934 * @arg @ref LL_DMA_CHANNEL_3
2935 * @arg @ref LL_DMA_CHANNEL_4
2936 * @arg @ref LL_DMA_CHANNEL_5
2937 * @arg @ref LL_DMA_CHANNEL_6
2938 * @arg @ref LL_DMA_CHANNEL_7
2939 * @arg @ref LL_DMA_CHANNEL_8
2940 * @arg @ref LL_DMA_CHANNEL_9
2941 * @arg @ref LL_DMA_CHANNEL_10
2942 * @arg @ref LL_DMA_CHANNEL_11
2943 * @arg @ref LL_DMA_CHANNEL_12
2944 * @arg @ref LL_DMA_CHANNEL_13
2945 * @arg @ref LL_DMA_CHANNEL_14
2946 * @arg @ref LL_DMA_CHANNEL_15
2947 * @param SrcAllocatedPort This parameter can be one of the following values:
2948 * @arg @ref LL_DMA_SRC_ALLOCATED_PORT0
2949 * @arg @ref LL_DMA_SRC_ALLOCATED_PORT1
2950 * @retval None.
2951 */
LL_DMA_SetSrcAllocatedPort(DMA_TypeDef * DMAx,uint32_t Channel,uint32_t SrcAllocatedPort)2952 __STATIC_INLINE void LL_DMA_SetSrcAllocatedPort(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t SrcAllocatedPort)
2953 {
2954 uint32_t dma_base_addr = (uint32_t)DMAx;
2955 MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_SAP,
2956 SrcAllocatedPort);
2957 }
2958
2959 /**
2960 * @brief Get source allocated port.
2961 * @note This API is not used for LPDMA channels.
2962 * @rmtoll CTR1 SAP LL_DMA_GetSrcAllocatedPort
2963 * @param DMAx DMAx Instance
2964 * @param Channel This parameter can be one of the following values:
2965 * @arg @ref LL_DMA_CHANNEL_0
2966 * @arg @ref LL_DMA_CHANNEL_1
2967 * @arg @ref LL_DMA_CHANNEL_2
2968 * @arg @ref LL_DMA_CHANNEL_3
2969 * @arg @ref LL_DMA_CHANNEL_4
2970 * @arg @ref LL_DMA_CHANNEL_5
2971 * @arg @ref LL_DMA_CHANNEL_6
2972 * @arg @ref LL_DMA_CHANNEL_7
2973 * @arg @ref LL_DMA_CHANNEL_8
2974 * @arg @ref LL_DMA_CHANNEL_9
2975 * @arg @ref LL_DMA_CHANNEL_10
2976 * @arg @ref LL_DMA_CHANNEL_11
2977 * @arg @ref LL_DMA_CHANNEL_12
2978 * @arg @ref LL_DMA_CHANNEL_13
2979 * @arg @ref LL_DMA_CHANNEL_14
2980 * @arg @ref LL_DMA_CHANNEL_15
2981 * @retval Returned value can be one of the following values:
2982 * @arg @ref LL_DMA_SRC_ALLOCATED_PORT0
2983 * @arg @ref LL_DMA_SRC_ALLOCATED_PORT1
2984 */
LL_DMA_GetSrcAllocatedPort(DMA_TypeDef * DMAx,uint32_t Channel)2985 __STATIC_INLINE uint32_t LL_DMA_GetSrcAllocatedPort(DMA_TypeDef *DMAx, uint32_t Channel)
2986 {
2987 uint32_t dma_base_addr = (uint32_t)DMAx;
2988 return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_SAP));
2989 }
2990
2991 /**
2992 * @brief Set data alignment mode.
2993 * @note This API is used for all available DMA channels.
2994 * For LPDMA channels, PAM field is reduced to one bit.
2995 * @rmtoll CTR1 PAM LL_DMA_SetDataAlignment
2996 * @param DMAx DMAx Instance
2997 * @param Channel This parameter can be one of the following values:
2998 * @arg @ref LL_DMA_CHANNEL_0
2999 * @arg @ref LL_DMA_CHANNEL_1
3000 * @arg @ref LL_DMA_CHANNEL_2
3001 * @arg @ref LL_DMA_CHANNEL_3
3002 * @arg @ref LL_DMA_CHANNEL_4
3003 * @arg @ref LL_DMA_CHANNEL_5
3004 * @arg @ref LL_DMA_CHANNEL_6
3005 * @arg @ref LL_DMA_CHANNEL_7
3006 * @arg @ref LL_DMA_CHANNEL_8
3007 * @arg @ref LL_DMA_CHANNEL_9
3008 * @arg @ref LL_DMA_CHANNEL_10
3009 * @arg @ref LL_DMA_CHANNEL_11
3010 * @arg @ref LL_DMA_CHANNEL_12
3011 * @arg @ref LL_DMA_CHANNEL_13
3012 * @arg @ref LL_DMA_CHANNEL_14
3013 * @arg @ref LL_DMA_CHANNEL_15
3014 * @param DataAlignment This parameter can be one of the following values:
3015 * @arg @ref LL_DMA_DATA_ALIGN_ZEROPADD
3016 * @arg @ref LL_DMA_DATA_ALIGN_SIGNEXTPADD
3017 * @arg @ref LL_DMA_DATA_PACK_UNPACK (This value is not allowed for LPDMA channels)
3018 * @retval None.
3019 */
LL_DMA_SetDataAlignment(DMA_TypeDef * DMAx,uint32_t Channel,uint32_t DataAlignment)3020 __STATIC_INLINE void LL_DMA_SetDataAlignment(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t DataAlignment)
3021 {
3022 uint32_t dma_base_addr = (uint32_t)DMAx;
3023 MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_PAM,
3024 DataAlignment);
3025 }
3026
3027 /**
3028 * @brief Get data alignment mode.
3029 * @note This API is used for all available DMA channels.
3030 * For LPDMA channels, PAM field is reduced to one bit.
3031 * @rmtoll CTR1 PAM LL_DMA_GetDataAlignment
3032 * @param DMAx DMAx Instance
3033 * @param Channel This parameter can be one of the following values:
3034 * @arg @ref LL_DMA_CHANNEL_0
3035 * @arg @ref LL_DMA_CHANNEL_1
3036 * @arg @ref LL_DMA_CHANNEL_2
3037 * @arg @ref LL_DMA_CHANNEL_3
3038 * @arg @ref LL_DMA_CHANNEL_4
3039 * @arg @ref LL_DMA_CHANNEL_5
3040 * @arg @ref LL_DMA_CHANNEL_6
3041 * @arg @ref LL_DMA_CHANNEL_7
3042 * @arg @ref LL_DMA_CHANNEL_8
3043 * @arg @ref LL_DMA_CHANNEL_9
3044 * @arg @ref LL_DMA_CHANNEL_10
3045 * @arg @ref LL_DMA_CHANNEL_11
3046 * @arg @ref LL_DMA_CHANNEL_12
3047 * @arg @ref LL_DMA_CHANNEL_13
3048 * @arg @ref LL_DMA_CHANNEL_14
3049 * @arg @ref LL_DMA_CHANNEL_15
3050 * @retval Returned value can be one of the following values:
3051 * @arg @ref LL_DMA_DATA_ALIGN_ZEROPADD
3052 * @arg @ref LL_DMA_DATA_ALIGN_SIGNEXTPADD
3053 * @arg @ref LL_DMA_DATA_PACK_UNPACK (This value is not allowed for LPDMA channels)
3054 */
LL_DMA_GetDataAlignment(DMA_TypeDef * DMAx,uint32_t Channel)3055 __STATIC_INLINE uint32_t LL_DMA_GetDataAlignment(DMA_TypeDef *DMAx, uint32_t Channel)
3056 {
3057 uint32_t dma_base_addr = (uint32_t)DMAx;
3058 return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_PAM));
3059 }
3060
3061 /**
3062 * @brief Set source burst length.
3063 * @note This API is not used for LPDMA channels.
3064 * @rmtoll CTR1 SBL_1 LL_DMA_SetSrcBurstLength
3065 * @param DMAx DMAx Instance
3066 * @param Channel This parameter can be one of the following values:
3067 * @arg @ref LL_DMA_CHANNEL_0
3068 * @arg @ref LL_DMA_CHANNEL_1
3069 * @arg @ref LL_DMA_CHANNEL_2
3070 * @arg @ref LL_DMA_CHANNEL_3
3071 * @arg @ref LL_DMA_CHANNEL_4
3072 * @arg @ref LL_DMA_CHANNEL_5
3073 * @arg @ref LL_DMA_CHANNEL_6
3074 * @arg @ref LL_DMA_CHANNEL_7
3075 * @arg @ref LL_DMA_CHANNEL_8
3076 * @arg @ref LL_DMA_CHANNEL_9
3077 * @arg @ref LL_DMA_CHANNEL_10
3078 * @arg @ref LL_DMA_CHANNEL_11
3079 * @arg @ref LL_DMA_CHANNEL_12
3080 * @arg @ref LL_DMA_CHANNEL_13
3081 * @arg @ref LL_DMA_CHANNEL_14
3082 * @arg @ref LL_DMA_CHANNEL_15
3083 * @param SrcBurstLength Between 1 to 64
3084 * @retval None.
3085 */
LL_DMA_SetSrcBurstLength(DMA_TypeDef * DMAx,uint32_t Channel,uint32_t SrcBurstLength)3086 __STATIC_INLINE void LL_DMA_SetSrcBurstLength(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t SrcBurstLength)
3087 {
3088 uint32_t dma_base_addr = (uint32_t)DMAx;
3089 MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_SBL_1,
3090 ((SrcBurstLength - 1U) << DMA_CTR1_SBL_1_Pos) & DMA_CTR1_SBL_1);
3091 }
3092
3093 /**
3094 * @brief Get source burst length.
3095 * @note This API is not used for LPDMA channels.
3096 * @rmtoll CTR1 SBL_1 LL_DMA_GetSrcBurstLength
3097 * @param DMAx DMAx Instance
3098 * @param Channel This parameter can be one of the following values:
3099 * @arg @ref LL_DMA_CHANNEL_0
3100 * @arg @ref LL_DMA_CHANNEL_1
3101 * @arg @ref LL_DMA_CHANNEL_2
3102 * @arg @ref LL_DMA_CHANNEL_3
3103 * @arg @ref LL_DMA_CHANNEL_4
3104 * @arg @ref LL_DMA_CHANNEL_5
3105 * @arg @ref LL_DMA_CHANNEL_6
3106 * @arg @ref LL_DMA_CHANNEL_7
3107 * @arg @ref LL_DMA_CHANNEL_8
3108 * @arg @ref LL_DMA_CHANNEL_9
3109 * @arg @ref LL_DMA_CHANNEL_10
3110 * @arg @ref LL_DMA_CHANNEL_11
3111 * @arg @ref LL_DMA_CHANNEL_12
3112 * @arg @ref LL_DMA_CHANNEL_13
3113 * @arg @ref LL_DMA_CHANNEL_14
3114 * @arg @ref LL_DMA_CHANNEL_15
3115 * @retval Between 1 to 64
3116 * @retval None.
3117 */
LL_DMA_GetSrcBurstLength(DMA_TypeDef * DMAx,uint32_t Channel)3118 __STATIC_INLINE uint32_t LL_DMA_GetSrcBurstLength(DMA_TypeDef *DMAx, uint32_t Channel)
3119 {
3120 uint32_t dma_base_addr = (uint32_t)DMAx;
3121 return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1,
3122 DMA_CTR1_SBL_1) >> DMA_CTR1_SBL_1_Pos) + 1U);
3123 }
3124
3125 /**
3126 * @brief Set source increment mode.
3127 * @note This API is used for all available DMA channels.
3128 * @rmtoll CTR1 SINC LL_DMA_SetSrcIncMode
3129 * @param DMAx DMAx Instance
3130 * @param Channel This parameter can be one of the following values:
3131 * @arg @ref LL_DMA_CHANNEL_0
3132 * @arg @ref LL_DMA_CHANNEL_1
3133 * @arg @ref LL_DMA_CHANNEL_2
3134 * @arg @ref LL_DMA_CHANNEL_3
3135 * @arg @ref LL_DMA_CHANNEL_4
3136 * @arg @ref LL_DMA_CHANNEL_5
3137 * @arg @ref LL_DMA_CHANNEL_6
3138 * @arg @ref LL_DMA_CHANNEL_7
3139 * @arg @ref LL_DMA_CHANNEL_8
3140 * @arg @ref LL_DMA_CHANNEL_9
3141 * @arg @ref LL_DMA_CHANNEL_10
3142 * @arg @ref LL_DMA_CHANNEL_11
3143 * @arg @ref LL_DMA_CHANNEL_12
3144 * @arg @ref LL_DMA_CHANNEL_13
3145 * @arg @ref LL_DMA_CHANNEL_14
3146 * @arg @ref LL_DMA_CHANNEL_15
3147 * @param SrcInc This parameter can be one of the following values:
3148 * @arg @ref LL_DMA_SRC_FIXED
3149 * @arg @ref LL_DMA_SRC_INCREMENT
3150 * @retval None.
3151 */
LL_DMA_SetSrcIncMode(DMA_TypeDef * DMAx,uint32_t Channel,uint32_t SrcInc)3152 __STATIC_INLINE void LL_DMA_SetSrcIncMode(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t SrcInc)
3153 {
3154 uint32_t dma_base_addr = (uint32_t)DMAx;
3155 MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_SINC, SrcInc);
3156 }
3157
3158 /**
3159 * @brief Get source increment mode.
3160 * @note This API is used for all available DMA channels.
3161 * @rmtoll CTR1 SINC LL_DMA_GetSrcIncMode
3162 * @param DMAx DMAx Instance
3163 * @param Channel This parameter can be one of the following values:
3164 * @arg @ref LL_DMA_CHANNEL_0
3165 * @arg @ref LL_DMA_CHANNEL_1
3166 * @arg @ref LL_DMA_CHANNEL_2
3167 * @arg @ref LL_DMA_CHANNEL_3
3168 * @arg @ref LL_DMA_CHANNEL_4
3169 * @arg @ref LL_DMA_CHANNEL_5
3170 * @arg @ref LL_DMA_CHANNEL_6
3171 * @arg @ref LL_DMA_CHANNEL_7
3172 * @arg @ref LL_DMA_CHANNEL_8
3173 * @arg @ref LL_DMA_CHANNEL_9
3174 * @arg @ref LL_DMA_CHANNEL_10
3175 * @arg @ref LL_DMA_CHANNEL_11
3176 * @arg @ref LL_DMA_CHANNEL_12
3177 * @arg @ref LL_DMA_CHANNEL_13
3178 * @arg @ref LL_DMA_CHANNEL_14
3179 * @arg @ref LL_DMA_CHANNEL_15
3180 * @retval Returned value can be one of the following values:
3181 * @arg @ref LL_DMA_SRC_FIXED
3182 * @arg @ref LL_DMA_SRC_INCREMENT
3183 */
LL_DMA_GetSrcIncMode(DMA_TypeDef * DMAx,uint32_t Channel)3184 __STATIC_INLINE uint32_t LL_DMA_GetSrcIncMode(DMA_TypeDef *DMAx, uint32_t Channel)
3185 {
3186 uint32_t dma_base_addr = (uint32_t)DMAx;
3187 return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_SINC));
3188 }
3189
3190 /**
3191 * @brief Set source data width.
3192 * @note This API is used for all available DMA channels.
3193 * @rmtoll CTR1 SDW_LOG2 LL_DMA_SetSrcDataWidth
3194 * @param DMAx DMAx Instance
3195 * @param Channel This parameter can be one of the following values:
3196 * @arg @ref LL_DMA_CHANNEL_0
3197 * @arg @ref LL_DMA_CHANNEL_1
3198 * @arg @ref LL_DMA_CHANNEL_2
3199 * @arg @ref LL_DMA_CHANNEL_3
3200 * @arg @ref LL_DMA_CHANNEL_4
3201 * @arg @ref LL_DMA_CHANNEL_5
3202 * @arg @ref LL_DMA_CHANNEL_6
3203 * @arg @ref LL_DMA_CHANNEL_7
3204 * @arg @ref LL_DMA_CHANNEL_8
3205 * @arg @ref LL_DMA_CHANNEL_9
3206 * @arg @ref LL_DMA_CHANNEL_10
3207 * @arg @ref LL_DMA_CHANNEL_11
3208 * @arg @ref LL_DMA_CHANNEL_12
3209 * @arg @ref LL_DMA_CHANNEL_13
3210 * @arg @ref LL_DMA_CHANNEL_14
3211 * @arg @ref LL_DMA_CHANNEL_15
3212 * @param SrcDataWidth This parameter can be one of the following values:
3213 * @arg @ref LL_DMA_SRC_DATAWIDTH_BYTE
3214 * @arg @ref LL_DMA_SRC_DATAWIDTH_HALFWORD
3215 * @arg @ref LL_DMA_SRC_DATAWIDTH_WORD
3216 * @retval None.
3217 */
LL_DMA_SetSrcDataWidth(DMA_TypeDef * DMAx,uint32_t Channel,uint32_t SrcDataWidth)3218 __STATIC_INLINE void LL_DMA_SetSrcDataWidth(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t SrcDataWidth)
3219 {
3220 uint32_t dma_base_addr = (uint32_t)DMAx;
3221 MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_SDW_LOG2,
3222 SrcDataWidth);
3223 }
3224
3225 /**
3226 * @brief Get Source Data width.
3227 * @note This API is used for all available DMA channels.
3228 * @rmtoll CTR1 SDW_LOG2 LL_DMA_GetSrcDataWidth
3229 * @param DMAx DMAx Instance
3230 * @param Channel This parameter can be one of the following values:
3231 * @arg @ref LL_DMA_CHANNEL_0
3232 * @arg @ref LL_DMA_CHANNEL_1
3233 * @arg @ref LL_DMA_CHANNEL_2
3234 * @arg @ref LL_DMA_CHANNEL_3
3235 * @arg @ref LL_DMA_CHANNEL_4
3236 * @arg @ref LL_DMA_CHANNEL_5
3237 * @arg @ref LL_DMA_CHANNEL_6
3238 * @arg @ref LL_DMA_CHANNEL_7
3239 * @arg @ref LL_DMA_CHANNEL_8
3240 * @arg @ref LL_DMA_CHANNEL_9
3241 * @arg @ref LL_DMA_CHANNEL_10
3242 * @arg @ref LL_DMA_CHANNEL_11
3243 * @arg @ref LL_DMA_CHANNEL_12
3244 * @arg @ref LL_DMA_CHANNEL_13
3245 * @arg @ref LL_DMA_CHANNEL_14
3246 * @arg @ref LL_DMA_CHANNEL_15
3247 * @retval Returned value can be one of the following values:
3248 * @arg @ref LL_DMA_SRC_DATAWIDTH_BYTE
3249 * @arg @ref LL_DMA_SRC_DATAWIDTH_HALFWORD
3250 * @arg @ref LL_DMA_SRC_DATAWIDTH_WORD
3251 */
LL_DMA_GetSrcDataWidth(DMA_TypeDef * DMAx,uint32_t Channel)3252 __STATIC_INLINE uint32_t LL_DMA_GetSrcDataWidth(DMA_TypeDef *DMAx, uint32_t Channel)
3253 {
3254 uint32_t dma_base_addr = (uint32_t)DMAx;
3255 return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_SDW_LOG2));
3256 }
3257
3258 /**
3259 * @brief Configure channel transfer.
3260 * @note This API is used for all available DMA channels.
3261 * @rmtoll CTR2 TCEM LL_DMA_ConfigChannelTransfer\n
3262 * CTR2 TRIGPOL LL_DMA_ConfigChannelTransfer\n
3263 * CTR2 TRIGM LL_DMA_ConfigChannelTransfer\n
3264 * CTR2 BREQ LL_DMA_ConfigChannelTransfer\n
3265 * CTR2 DREQ LL_DMA_ConfigChannelTransfer\n
3266 * CTR2 SWREQ LL_DMA_ConfigChannelTransfer
3267 * @param DMAx DMAx Instance
3268 * @param Channel This parameter can be one of the following values:
3269 * @arg @ref LL_DMA_CHANNEL_0
3270 * @arg @ref LL_DMA_CHANNEL_1
3271 * @arg @ref LL_DMA_CHANNEL_2
3272 * @arg @ref LL_DMA_CHANNEL_3
3273 * @arg @ref LL_DMA_CHANNEL_4
3274 * @arg @ref LL_DMA_CHANNEL_5
3275 * @arg @ref LL_DMA_CHANNEL_6
3276 * @arg @ref LL_DMA_CHANNEL_7
3277 * @arg @ref LL_DMA_CHANNEL_8
3278 * @arg @ref LL_DMA_CHANNEL_9
3279 * @arg @ref LL_DMA_CHANNEL_10
3280 * @arg @ref LL_DMA_CHANNEL_11
3281 * @arg @ref LL_DMA_CHANNEL_12
3282 * @arg @ref LL_DMA_CHANNEL_13
3283 * @arg @ref LL_DMA_CHANNEL_14
3284 * @arg @ref LL_DMA_CHANNEL_15
3285 * @param Configuration This parameter must be a combination of all the following values:
3286 * @arg @ref LL_DMA_TCEM_BLK_TRANSFER or @ref LL_DMA_TCEM_RPT_BLK_TRANSFER or
3287 * @ref LL_DMA_TCEM_EACH_LLITEM_TRANSFER or @ref LL_DMA_TCEM_LAST_LLITEM_TRANSFER
3288 * @arg @ref LL_DMA_TRIG_POLARITY_MASKED or @ref LL_DMA_HWREQUEST_BLK
3289 * @arg @ref LL_DMA_HWREQUEST_SINGLEBURST or @ref LL_DMA_TRIG_POLARITY_RISING or
3290 * @ref LL_DMA_TRIG_POLARITY_FALLING
3291 * @arg @ref LL_DMA_TRIGM_BLK_TRANSFER or @ref LL_DMA_TRIGM_RPT_BLK_TRANSFER or
3292 * @ref LL_DMA_TRIGM_LLI_LINK_TRANSFER or @ref LL_DMA_TRIGM_SINGLBURST_TRANSFER
3293 * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY or @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH or
3294 * @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
3295 *@retval None.
3296 */
LL_DMA_ConfigChannelTransfer(DMA_TypeDef * DMAx,uint32_t Channel,uint32_t Configuration)3297 __STATIC_INLINE void LL_DMA_ConfigChannelTransfer(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Configuration)
3298 {
3299 uint32_t dma_base_addr = (uint32_t)DMAx;
3300 MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR2,
3301 (DMA_CTR2_TCEM | DMA_CTR2_TRIGPOL | DMA_CTR2_TRIGM | DMA_CTR2_DREQ | DMA_CTR2_SWREQ | DMA_CTR2_BREQ),
3302 Configuration);
3303 }
3304
3305 /**
3306 * @brief Set transfer event mode.
3307 * @note This API is used for all available DMA channels.
3308 * @rmtoll CTR2 TCEM LL_DMA_SetTransferEventMode
3309 * @param DMAx DMAx Instance
3310 * @param Channel This parameter can be one of the following values:
3311 * @arg @ref LL_DMA_CHANNEL_0
3312 * @arg @ref LL_DMA_CHANNEL_1
3313 * @arg @ref LL_DMA_CHANNEL_2
3314 * @arg @ref LL_DMA_CHANNEL_3
3315 * @arg @ref LL_DMA_CHANNEL_4
3316 * @arg @ref LL_DMA_CHANNEL_5
3317 * @arg @ref LL_DMA_CHANNEL_6
3318 * @arg @ref LL_DMA_CHANNEL_7
3319 * @arg @ref LL_DMA_CHANNEL_8
3320 * @arg @ref LL_DMA_CHANNEL_9
3321 * @arg @ref LL_DMA_CHANNEL_10
3322 * @arg @ref LL_DMA_CHANNEL_11
3323 * @arg @ref LL_DMA_CHANNEL_12
3324 * @arg @ref LL_DMA_CHANNEL_13
3325 * @arg @ref LL_DMA_CHANNEL_14
3326 * @arg @ref LL_DMA_CHANNEL_15
3327 * @param TransferEventMode This parameter can be one of the following values:
3328 * @arg @ref LL_DMA_TCEM_BLK_TRANSFER
3329 * @arg @ref LL_DMA_TCEM_RPT_BLK_TRANSFER
3330 * @arg @ref LL_DMA_TCEM_EACH_LLITEM_TRANSFER
3331 * @arg @ref LL_DMA_TCEM_LAST_LLITEM_TRANSFER
3332 * @retval None.
3333 */
LL_DMA_SetTransferEventMode(DMA_TypeDef * DMAx,uint32_t Channel,uint32_t TransferEventMode)3334 __STATIC_INLINE void LL_DMA_SetTransferEventMode(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t TransferEventMode)
3335 {
3336 uint32_t dma_base_addr = (uint32_t)DMAx;
3337 MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR2, DMA_CTR2_TCEM,
3338 TransferEventMode);
3339 }
3340
3341 /**
3342 * @brief Get transfer event mode.
3343 * @note This API is used for all available DMA channels.
3344 * @rmtoll CTR2 TCEM LL_DMA_GetTransferEventMode
3345 * @param DMAx DMAx Instance
3346 * @param Channel This parameter can be one of the following values:
3347 * @arg @ref LL_DMA_CHANNEL_0
3348 * @arg @ref LL_DMA_CHANNEL_1
3349 * @arg @ref LL_DMA_CHANNEL_2
3350 * @arg @ref LL_DMA_CHANNEL_3
3351 * @arg @ref LL_DMA_CHANNEL_4
3352 * @arg @ref LL_DMA_CHANNEL_5
3353 * @arg @ref LL_DMA_CHANNEL_6
3354 * @arg @ref LL_DMA_CHANNEL_7
3355 * @arg @ref LL_DMA_CHANNEL_8
3356 * @arg @ref LL_DMA_CHANNEL_9
3357 * @arg @ref LL_DMA_CHANNEL_10
3358 * @arg @ref LL_DMA_CHANNEL_11
3359 * @arg @ref LL_DMA_CHANNEL_12
3360 * @arg @ref LL_DMA_CHANNEL_13
3361 * @arg @ref LL_DMA_CHANNEL_14
3362 * @arg @ref LL_DMA_CHANNEL_15
3363 * @retval Returned value can be one of the following values:
3364 * @arg @ref LL_DMA_TCEM_BLK_TRANSFER
3365 * @arg @ref LL_DMA_TCEM_RPT_BLK_TRANSFER
3366 * @arg @ref LL_DMA_TCEM_EACH_LLITEM_TRANSFER
3367 * @arg @ref LL_DMA_TCEM_LAST_LLITEM_TRANSFER
3368 */
LL_DMA_GetTransferEventMode(DMA_TypeDef * DMAx,uint32_t Channel)3369 __STATIC_INLINE uint32_t LL_DMA_GetTransferEventMode(DMA_TypeDef *DMAx, uint32_t Channel)
3370 {
3371 uint32_t dma_base_addr = (uint32_t)DMAx;
3372 return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR2, DMA_CTR2_TCEM));
3373 }
3374
3375 /**
3376 * @brief Set trigger polarity.
3377 * @note This API is used for all available DMA channels.
3378 * @rmtoll CTR2 TRIGPOL LL_DMA_SetTriggerPolarity
3379 * @param DMAx DMAx Instance
3380 * @param Channel This parameter can be one of the following values:
3381 * @arg @ref LL_DMA_CHANNEL_0
3382 * @arg @ref LL_DMA_CHANNEL_1
3383 * @arg @ref LL_DMA_CHANNEL_2
3384 * @arg @ref LL_DMA_CHANNEL_3
3385 * @arg @ref LL_DMA_CHANNEL_4
3386 * @arg @ref LL_DMA_CHANNEL_5
3387 * @arg @ref LL_DMA_CHANNEL_6
3388 * @arg @ref LL_DMA_CHANNEL_7
3389 * @arg @ref LL_DMA_CHANNEL_8
3390 * @arg @ref LL_DMA_CHANNEL_9
3391 * @arg @ref LL_DMA_CHANNEL_10
3392 * @arg @ref LL_DMA_CHANNEL_11
3393 * @arg @ref LL_DMA_CHANNEL_12
3394 * @arg @ref LL_DMA_CHANNEL_13
3395 * @arg @ref LL_DMA_CHANNEL_14
3396 * @arg @ref LL_DMA_CHANNEL_15
3397 * @param TriggerPolarity This parameter can be one of the following values:
3398 * @arg @ref LL_DMA_TRIG_POLARITY_MASKED
3399 * @arg @ref LL_DMA_TRIG_POLARITY_RISING
3400 * @arg @ref LL_DMA_TRIG_POLARITY_FALLING
3401 * @retval None.
3402 */
LL_DMA_SetTriggerPolarity(DMA_TypeDef * DMAx,uint32_t Channel,uint32_t TriggerPolarity)3403 __STATIC_INLINE void LL_DMA_SetTriggerPolarity(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t TriggerPolarity)
3404 {
3405 uint32_t dma_base_addr = (uint32_t)DMAx;
3406 MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR2, DMA_CTR2_TRIGPOL,
3407 TriggerPolarity);
3408 }
3409
3410 /**
3411 * @brief Get trigger polarity.
3412 * @note This API is used for all available DMA channels.
3413 * @rmtoll CTR2 TRIGPOL LL_DMA_GetTriggerPolarity
3414 * @param DMAx DMAx Instance
3415 * @param Channel This parameter can be one of the following values:
3416 * @arg @ref LL_DMA_CHANNEL_0
3417 * @arg @ref LL_DMA_CHANNEL_1
3418 * @arg @ref LL_DMA_CHANNEL_2
3419 * @arg @ref LL_DMA_CHANNEL_3
3420 * @arg @ref LL_DMA_CHANNEL_4
3421 * @arg @ref LL_DMA_CHANNEL_5
3422 * @arg @ref LL_DMA_CHANNEL_6
3423 * @arg @ref LL_DMA_CHANNEL_7
3424 * @arg @ref LL_DMA_CHANNEL_8
3425 * @arg @ref LL_DMA_CHANNEL_9
3426 * @arg @ref LL_DMA_CHANNEL_10
3427 * @arg @ref LL_DMA_CHANNEL_11
3428 * @arg @ref LL_DMA_CHANNEL_12
3429 * @arg @ref LL_DMA_CHANNEL_13
3430 * @arg @ref LL_DMA_CHANNEL_14
3431 * @arg @ref LL_DMA_CHANNEL_15
3432 * @retval Returned value can be one of the following values:
3433 * @arg @ref LL_DMA_TRIG_POLARITY_MASKED
3434 * @arg @ref LL_DMA_TRIG_POLARITY_RISING
3435 * @arg @ref LL_DMA_TRIG_POLARITY_FALLING
3436 */
LL_DMA_GetTriggerPolarity(DMA_TypeDef * DMAx,uint32_t Channel)3437 __STATIC_INLINE uint32_t LL_DMA_GetTriggerPolarity(DMA_TypeDef *DMAx, uint32_t Channel)
3438 {
3439 uint32_t dma_base_addr = (uint32_t)DMAx;
3440 return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR2, DMA_CTR2_TRIGPOL));
3441 }
3442
3443 /**
3444 * @brief Set trigger Mode.
3445 * @note This API is used for all available DMA channels.
3446 * @rmtoll CTR2 TRIGM LL_DMA_SetTriggerMode
3447 * @param DMAx DMAx Instance
3448 * @param Channel This parameter can be one of the following values:
3449 * @arg @ref LL_DMA_CHANNEL_0
3450 * @arg @ref LL_DMA_CHANNEL_1
3451 * @arg @ref LL_DMA_CHANNEL_2
3452 * @arg @ref LL_DMA_CHANNEL_3
3453 * @arg @ref LL_DMA_CHANNEL_4
3454 * @arg @ref LL_DMA_CHANNEL_5
3455 * @arg @ref LL_DMA_CHANNEL_6
3456 * @arg @ref LL_DMA_CHANNEL_7
3457 * @arg @ref LL_DMA_CHANNEL_8
3458 * @arg @ref LL_DMA_CHANNEL_9
3459 * @arg @ref LL_DMA_CHANNEL_10
3460 * @arg @ref LL_DMA_CHANNEL_11
3461 * @arg @ref LL_DMA_CHANNEL_12
3462 * @arg @ref LL_DMA_CHANNEL_13
3463 * @arg @ref LL_DMA_CHANNEL_14
3464 * @arg @ref LL_DMA_CHANNEL_15
3465 * @param TriggerMode This parameter can be one of the following values:
3466 * @arg @ref LL_DMA_TRIGM_BLK_TRANSFER
3467 * @arg @ref LL_DMA_TRIGM_RPT_BLK_TRANSFER (This value is allowed only for 2D addressing channels)
3468 * @arg @ref LL_DMA_TRIGM_LLI_LINK_TRANSFER
3469 * @arg @ref LL_DMA_TRIGM_SINGLBURST_TRANSFER
3470 * @retval None.
3471 */
LL_DMA_SetTriggerMode(DMA_TypeDef * DMAx,uint32_t Channel,uint32_t TriggerMode)3472 __STATIC_INLINE void LL_DMA_SetTriggerMode(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t TriggerMode)
3473 {
3474 uint32_t dma_base_addr = (uint32_t)DMAx;
3475 MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR2, DMA_CTR2_TRIGM,
3476 TriggerMode);
3477 }
3478
3479 /**
3480 * @brief Get trigger Mode.
3481 * @note This API is used for all available DMA channels.
3482 * @rmtoll CTR2 TRIGM LL_DMA_GetTriggerMode
3483 * @param DMAx DMAx Instance
3484 * @param Channel This parameter can be one of the following values:
3485 * @arg @ref LL_DMA_CHANNEL_0
3486 * @arg @ref LL_DMA_CHANNEL_1
3487 * @arg @ref LL_DMA_CHANNEL_2
3488 * @arg @ref LL_DMA_CHANNEL_3
3489 * @arg @ref LL_DMA_CHANNEL_4
3490 * @arg @ref LL_DMA_CHANNEL_5
3491 * @arg @ref LL_DMA_CHANNEL_6
3492 * @arg @ref LL_DMA_CHANNEL_7
3493 * @arg @ref LL_DMA_CHANNEL_8
3494 * @arg @ref LL_DMA_CHANNEL_9
3495 * @arg @ref LL_DMA_CHANNEL_10
3496 * @arg @ref LL_DMA_CHANNEL_11
3497 * @arg @ref LL_DMA_CHANNEL_12
3498 * @arg @ref LL_DMA_CHANNEL_13
3499 * @arg @ref LL_DMA_CHANNEL_14
3500 * @arg @ref LL_DMA_CHANNEL_15
3501 * @retval Returned value can be one of the following values:
3502 * @arg @ref LL_DMA_TRIGM_BLK_TRANSFER
3503 * @arg @ref LL_DMA_TRIGM_RPT_BLK_TRANSFER (This value is allowed only for 2D addressing channels)
3504 * @arg @ref LL_DMA_TRIGM_LLI_LINK_TRANSFER
3505 * @arg @ref LL_DMA_TRIGM_SINGLBURST_TRANSFER
3506 */
LL_DMA_GetTriggerMode(DMA_TypeDef * DMAx,uint32_t Channel)3507 __STATIC_INLINE uint32_t LL_DMA_GetTriggerMode(DMA_TypeDef *DMAx, uint32_t Channel)
3508 {
3509 uint32_t dma_base_addr = (uint32_t)DMAx;
3510 return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR2, DMA_CTR2_TRIGM));
3511 }
3512
3513 /**
3514 * @brief Set destination hardware and software transfer request.
3515 * @note This API is used for all available DMA channels.
3516 * @rmtoll CTR2 DREQ LL_DMA_SetDataTransferDirection\n
3517 * @rmtoll CTR2 SWREQ LL_DMA_SetDataTransferDirection
3518 * @param DMAx DMAx Instance
3519 * @param Channel This parameter can be one of the following values:
3520 * @arg @ref LL_DMA_CHANNEL_0
3521 * @arg @ref LL_DMA_CHANNEL_1
3522 * @arg @ref LL_DMA_CHANNEL_2
3523 * @arg @ref LL_DMA_CHANNEL_3
3524 * @arg @ref LL_DMA_CHANNEL_4
3525 * @arg @ref LL_DMA_CHANNEL_5
3526 * @arg @ref LL_DMA_CHANNEL_6
3527 * @arg @ref LL_DMA_CHANNEL_7
3528 * @arg @ref LL_DMA_CHANNEL_8
3529 * @arg @ref LL_DMA_CHANNEL_9
3530 * @arg @ref LL_DMA_CHANNEL_10
3531 * @arg @ref LL_DMA_CHANNEL_11
3532 * @arg @ref LL_DMA_CHANNEL_12
3533 * @arg @ref LL_DMA_CHANNEL_13
3534 * @arg @ref LL_DMA_CHANNEL_14
3535 * @arg @ref LL_DMA_CHANNEL_15
3536 * @param Direction This parameter can be one of the following values:
3537 * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY
3538 * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH (This value is not allowed for LPDMA channels)
3539 * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY (This value is not allowed for LPDMA channels)
3540 * @retval None.
3541 */
LL_DMA_SetDataTransferDirection(DMA_TypeDef * DMAx,uint32_t Channel,uint32_t Direction)3542 __STATIC_INLINE void LL_DMA_SetDataTransferDirection(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Direction)
3543 {
3544 uint32_t dma_base_addr = (uint32_t)DMAx;
3545 MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR2,
3546 DMA_CTR2_DREQ | DMA_CTR2_SWREQ, Direction);
3547 }
3548
3549 /**
3550 * @brief Get destination hardware and software transfer request.
3551 * @note This API is used for all available DMA channels.
3552 * For LPDMA channels, DREQ fields programming is discarded.
3553 * @rmtoll CTR2 DREQ LL_DMA_GetDataTransferDirection\n
3554 * @rmtoll CTR2 SWREQ LL_DMA_GetDataTransferDirection
3555 * @param DMAx DMAx Instance
3556 * @param Channel This parameter can be one of the following values:
3557 * @arg @ref LL_DMA_CHANNEL_0
3558 * @arg @ref LL_DMA_CHANNEL_1
3559 * @arg @ref LL_DMA_CHANNEL_2
3560 * @arg @ref LL_DMA_CHANNEL_3
3561 * @arg @ref LL_DMA_CHANNEL_4
3562 * @arg @ref LL_DMA_CHANNEL_5
3563 * @arg @ref LL_DMA_CHANNEL_6
3564 * @arg @ref LL_DMA_CHANNEL_7
3565 * @arg @ref LL_DMA_CHANNEL_8
3566 * @arg @ref LL_DMA_CHANNEL_9
3567 * @arg @ref LL_DMA_CHANNEL_10
3568 * @arg @ref LL_DMA_CHANNEL_11
3569 * @arg @ref LL_DMA_CHANNEL_12
3570 * @arg @ref LL_DMA_CHANNEL_13
3571 * @arg @ref LL_DMA_CHANNEL_14
3572 * @arg @ref LL_DMA_CHANNEL_15
3573 * @retval Returned value can be one of the following values:
3574 * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY
3575 * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH (This value is not allowed for LPDMA channels)
3576 * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY (This value is not allowed for LPDMA channels)
3577 */
LL_DMA_GetDataTransferDirection(DMA_TypeDef * DMAx,uint32_t Channel)3578 __STATIC_INLINE uint32_t LL_DMA_GetDataTransferDirection(DMA_TypeDef *DMAx, uint32_t Channel)
3579 {
3580 uint32_t dma_base_addr = (uint32_t)DMAx;
3581 return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR2,
3582 DMA_CTR2_DREQ | DMA_CTR2_SWREQ));
3583 }
3584
3585 /**
3586 * @brief Set block hardware request.
3587 * @note This API is used for all available DMA channels.
3588 * @rmtoll CTR2 BREQ LL_DMA_SetBlkHWRequest\n
3589 * @param DMAx DMAx Instance
3590 * @param Channel This parameter can be one of the following values:
3591 * @arg @ref LL_DMA_CHANNEL_0
3592 * @arg @ref LL_DMA_CHANNEL_1
3593 * @arg @ref LL_DMA_CHANNEL_2
3594 * @arg @ref LL_DMA_CHANNEL_3
3595 * @arg @ref LL_DMA_CHANNEL_4
3596 * @arg @ref LL_DMA_CHANNEL_5
3597 * @arg @ref LL_DMA_CHANNEL_6
3598 * @arg @ref LL_DMA_CHANNEL_7
3599 * @arg @ref LL_DMA_CHANNEL_8
3600 * @arg @ref LL_DMA_CHANNEL_9
3601 * @arg @ref LL_DMA_CHANNEL_10
3602 * @arg @ref LL_DMA_CHANNEL_11
3603 * @arg @ref LL_DMA_CHANNEL_12
3604 * @arg @ref LL_DMA_CHANNEL_13
3605 * @arg @ref LL_DMA_CHANNEL_14
3606 * @arg @ref LL_DMA_CHANNEL_15
3607 * @param BlkHWRequest This parameter can be one of the following values:
3608 * @arg @ref LL_DMA_HWREQUEST_SINGLEBURST
3609 * @arg @ref LL_DMA_HWREQUEST_BLK
3610 * @retval None.
3611 */
LL_DMA_SetBlkHWRequest(DMA_TypeDef * DMAx,uint32_t Channel,uint32_t BlkHWRequest)3612 __STATIC_INLINE void LL_DMA_SetBlkHWRequest(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t BlkHWRequest)
3613 {
3614 uint32_t dma_base_addr = (uint32_t)DMAx;
3615 MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR2, DMA_CTR2_BREQ,
3616 BlkHWRequest);
3617 }
3618
3619 /**
3620 * @brief Get block hardware request.
3621 * @note This API is used for all available DMA channels.
3622 * @rmtoll CTR2 BREQ LL_DMA_GetBlkHWRequest\n
3623 * @param DMAx DMAx Instance
3624 * @param Channel This parameter can be one of the following values:
3625 * @arg @ref LL_DMA_CHANNEL_0
3626 * @arg @ref LL_DMA_CHANNEL_1
3627 * @arg @ref LL_DMA_CHANNEL_2
3628 * @arg @ref LL_DMA_CHANNEL_3
3629 * @arg @ref LL_DMA_CHANNEL_4
3630 * @arg @ref LL_DMA_CHANNEL_5
3631 * @arg @ref LL_DMA_CHANNEL_6
3632 * @arg @ref LL_DMA_CHANNEL_7
3633 * @arg @ref LL_DMA_CHANNEL_8
3634 * @arg @ref LL_DMA_CHANNEL_9
3635 * @arg @ref LL_DMA_CHANNEL_10
3636 * @arg @ref LL_DMA_CHANNEL_11
3637 * @arg @ref LL_DMA_CHANNEL_12
3638 * @arg @ref LL_DMA_CHANNEL_13
3639 * @arg @ref LL_DMA_CHANNEL_14
3640 * @arg @ref LL_DMA_CHANNEL_15
3641 * @retval Returned value can be one of the following values:
3642 * @arg @ref LL_DMA_HWREQUEST_SINGLEBURST
3643 * @arg @ref LL_DMA_HWREQUEST_BLK
3644 */
LL_DMA_GetBlkHWRequest(DMA_TypeDef * DMAx,uint32_t Channel)3645 __STATIC_INLINE uint32_t LL_DMA_GetBlkHWRequest(DMA_TypeDef *DMAx, uint32_t Channel)
3646 {
3647 uint32_t dma_base_addr = (uint32_t)DMAx;
3648 return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR2, DMA_CTR2_BREQ));
3649 }
3650
3651 /**
3652 * @brief Set hardware request.
3653 * @note This API is used for all available DMA channels.
3654 * For LPDMA channels, REQSEL fields is reduced to 5 bits.
3655 * @rmtoll CTR2 REQSEL LL_DMA_SetPeriphRequest
3656 * @param DMAx DMAx Instance
3657 * @param Channel This parameter can be one of the following values:
3658 * @arg @ref LL_DMA_CHANNEL_0
3659 * @arg @ref LL_DMA_CHANNEL_1
3660 * @arg @ref LL_DMA_CHANNEL_2
3661 * @arg @ref LL_DMA_CHANNEL_3
3662 * @arg @ref LL_DMA_CHANNEL_4
3663 * @arg @ref LL_DMA_CHANNEL_5
3664 * @arg @ref LL_DMA_CHANNEL_6
3665 * @arg @ref LL_DMA_CHANNEL_7
3666 * @arg @ref LL_DMA_CHANNEL_8
3667 * @arg @ref LL_DMA_CHANNEL_9
3668 * @arg @ref LL_DMA_CHANNEL_10
3669 * @arg @ref LL_DMA_CHANNEL_11
3670 * @arg @ref LL_DMA_CHANNEL_12
3671 * @arg @ref LL_DMA_CHANNEL_13
3672 * @arg @ref LL_DMA_CHANNEL_14
3673 * @arg @ref LL_DMA_CHANNEL_15
3674 * @param Request This parameter can be one of the following values:
3675 * @arg @ref LL_GPDMA1_REQUEST_ADC1
3676 * @arg @ref LL_GPDMA1_REQUEST_ADC2 (*)
3677 * @arg @ref LL_GPDMA1_REQUEST_DAC1_CH1
3678 * @arg @ref LL_GPDMA1_REQUEST_DAC1_CH2
3679 * @arg @ref LL_GPDMA1_REQUEST_TIM6_UP
3680 * @arg @ref LL_GPDMA1_REQUEST_TIM7_UP
3681 * @arg @ref LL_GPDMA1_REQUEST_SPI1_RX
3682 * @arg @ref LL_GPDMA1_REQUEST_SPI1_TX
3683 * @arg @ref LL_GPDMA1_REQUEST_SPI2_RX
3684 * @arg @ref LL_GPDMA1_REQUEST_SPI2_TX
3685 * @arg @ref LL_GPDMA1_REQUEST_SPI3_RX
3686 * @arg @ref LL_GPDMA1_REQUEST_SPI3_TX
3687 * @arg @ref LL_GPDMA1_REQUEST_I2C1_RX
3688 * @arg @ref LL_GPDMA1_REQUEST_I2C1_TX
3689 * @arg @ref LL_GPDMA1_REQUEST_I2C2_RX
3690 * @arg @ref LL_GPDMA1_REQUEST_I2C2_TX
3691 * @arg @ref LL_GPDMA1_REQUEST_I2C3_RX (*)
3692 * @arg @ref LL_GPDMA1_REQUEST_I2C3_TX (*)
3693 * @arg @ref LL_GPDMA1_REQUEST_USART1_RX
3694 * @arg @ref LL_GPDMA1_REQUEST_USART1_TX
3695 * @arg @ref LL_GPDMA1_REQUEST_USART2_RX
3696 * @arg @ref LL_GPDMA1_REQUEST_USART2_TX
3697 * @arg @ref LL_GPDMA1_REQUEST_USART3_RX
3698 * @arg @ref LL_GPDMA1_REQUEST_USART3_TX
3699 * @arg @ref LL_GPDMA1_REQUEST_UART4_RX (*)
3700 * @arg @ref LL_GPDMA1_REQUEST_UART4_TX (*)
3701 * @arg @ref LL_GPDMA1_REQUEST_UART5_RX (*)
3702 * @arg @ref LL_GPDMA1_REQUEST_UART5_TX (*)
3703 * @arg @ref LL_GPDMA1_REQUEST_USART6_RX (*)
3704 * @arg @ref LL_GPDMA1_REQUEST_USART6_TX (*)
3705 * @arg @ref LL_GPDMA1_REQUEST_UART7_RX (*)
3706 * @arg @ref LL_GPDMA1_REQUEST_UART7_TX (*)
3707 * @arg @ref LL_GPDMA1_REQUEST_UART8_RX (*)
3708 * @arg @ref LL_GPDMA1_REQUEST_UART8_TX (*)
3709 * @arg @ref LL_GPDMA1_REQUEST_UART9_RX (*)
3710 * @arg @ref LL_GPDMA1_REQUEST_UART9_TX (*)
3711 * @arg @ref LL_GPDMA1_REQUEST_USART10_RX (*)
3712 * @arg @ref LL_GPDMA1_REQUEST_USART10_TX (*)
3713 * @arg @ref LL_GPDMA1_REQUEST_USART11_RX (*)
3714 * @arg @ref LL_GPDMA1_REQUEST_USART11_TX (*)
3715 * @arg @ref LL_GPDMA1_REQUEST_UART12_RX (*)
3716 * @arg @ref LL_GPDMA1_REQUEST_UART12_TX (*)
3717 * @arg @ref LL_GPDMA1_REQUEST_LPUART1_RX
3718 * @arg @ref LL_GPDMA1_REQUEST_LPUART1_TX
3719 * @arg @ref LL_GPDMA1_REQUEST_SPI4_RX (*)
3720 * @arg @ref LL_GPDMA1_REQUEST_SPI4_TX (*)
3721 * @arg @ref LL_GPDMA1_REQUEST_SPI5_RX (*)
3722 * @arg @ref LL_GPDMA1_REQUEST_SPI5_TX (*)
3723 * @arg @ref LL_GPDMA1_REQUEST_SPI6_RX (*)
3724 * @arg @ref LL_GPDMA1_REQUEST_SPI6_TX (*)
3725 * @arg @ref LL_GPDMA1_REQUEST_SAI1_A (*)
3726 * @arg @ref LL_GPDMA1_REQUEST_SAI1_B (*)
3727 * @arg @ref LL_GPDMA1_REQUEST_SAI2_A (*)
3728 * @arg @ref LL_GPDMA1_REQUEST_SAI2_B (*)
3729 * @arg @ref LL_GPDMA1_REQUEST_OCTOSPI1 (*)
3730 * @arg @ref LL_GPDMA1_REQUEST_TIM1_CH1
3731 * @arg @ref LL_GPDMA1_REQUEST_TIM1_CH2
3732 * @arg @ref LL_GPDMA1_REQUEST_TIM1_CH3
3733 * @arg @ref LL_GPDMA1_REQUEST_TIM1_CH4
3734 * @arg @ref LL_GPDMA1_REQUEST_TIM1_UP
3735 * @arg @ref LL_GPDMA1_REQUEST_TIM1_TRIG
3736 * @arg @ref LL_GPDMA1_REQUEST_TIM1_COM
3737 * @arg @ref LL_GPDMA1_REQUEST_TIM8_CH1 (*)
3738 * @arg @ref LL_GPDMA1_REQUEST_TIM8_CH2 (*)
3739 * @arg @ref LL_GPDMA1_REQUEST_TIM8_CH3 (*)
3740 * @arg @ref LL_GPDMA1_REQUEST_TIM8_CH4 (*)
3741 * @arg @ref LL_GPDMA1_REQUEST_TIM8_UP (*)
3742 * @arg @ref LL_GPDMA1_REQUEST_TIM8_TRIG (*)
3743 * @arg @ref LL_GPDMA1_REQUEST_TIM8_COM (*)
3744 * @arg @ref LL_GPDMA1_REQUEST_TIM2_CH1
3745 * @arg @ref LL_GPDMA1_REQUEST_TIM2_CH2
3746 * @arg @ref LL_GPDMA1_REQUEST_TIM2_CH3
3747 * @arg @ref LL_GPDMA1_REQUEST_TIM2_CH4
3748 * @arg @ref LL_GPDMA1_REQUEST_TIM2_UP
3749 * @arg @ref LL_GPDMA1_REQUEST_TIM3_CH1
3750 * @arg @ref LL_GPDMA1_REQUEST_TIM3_CH2
3751 * @arg @ref LL_GPDMA1_REQUEST_TIM3_CH3
3752 * @arg @ref LL_GPDMA1_REQUEST_TIM3_CH4
3753 * @arg @ref LL_GPDMA1_REQUEST_TIM3_UP
3754 * @arg @ref LL_GPDMA1_REQUEST_TIM3_TRIG
3755 * @arg @ref LL_GPDMA1_REQUEST_TIM4_CH1 (*)
3756 * @arg @ref LL_GPDMA1_REQUEST_TIM4_CH2 (*)
3757 * @arg @ref LL_GPDMA1_REQUEST_TIM4_CH3 (*)
3758 * @arg @ref LL_GPDMA1_REQUEST_TIM4_CH4 (*)
3759 * @arg @ref LL_GPDMA1_REQUEST_TIM4_UP (*)
3760 * @arg @ref LL_GPDMA1_REQUEST_TIM5_CH1 (*)
3761 * @arg @ref LL_GPDMA1_REQUEST_TIM5_CH2 (*)
3762 * @arg @ref LL_GPDMA1_REQUEST_TIM5_CH3 (*)
3763 * @arg @ref LL_GPDMA1_REQUEST_TIM5_CH4 (*)
3764 * @arg @ref LL_GPDMA1_REQUEST_TIM5_UP (*)
3765 * @arg @ref LL_GPDMA1_REQUEST_TIM5_TRIG (*)
3766 * @arg @ref LL_GPDMA1_REQUEST_TIM15_CH1 (*)
3767 * @arg @ref LL_GPDMA1_REQUEST_TIM15_UP (*)
3768 * @arg @ref LL_GPDMA1_REQUEST_TIM15_TRIG (*)
3769 * @arg @ref LL_GPDMA1_REQUEST_TIM15_COM (*)
3770 * @arg @ref LL_GPDMA1_REQUEST_TIM16_CH1 (*)
3771 * @arg @ref LL_GPDMA1_REQUEST_TIM16_UP (*)
3772 * @arg @ref LL_GPDMA1_REQUEST_TIM17_CH1 (*)
3773 * @arg @ref LL_GPDMA1_REQUEST_TIM17_UP (*)
3774 * @arg @ref LL_GPDMA1_REQUEST_LPTIM1_IC1
3775 * @arg @ref LL_GPDMA1_REQUEST_LPTIM1_IC2
3776 * @arg @ref LL_GPDMA1_REQUEST_LPTIM1_UE
3777 * @arg @ref LL_GPDMA1_REQUEST_LPTIM2_IC1
3778 * @arg @ref LL_GPDMA1_REQUEST_LPTIM2_IC2
3779 * @arg @ref LL_GPDMA1_REQUEST_LPTIM2_UE
3780 * @arg @ref LL_GPDMA1_REQUEST_DCMI (*)
3781 * @arg @ref LL_GPDMA1_REQUEST_AES_OUT (*)
3782 * @arg @ref LL_GPDMA1_REQUEST_AES_IN (*)
3783 * @arg @ref LL_GPDMA1_REQUEST_HASH_IN
3784 * @arg @ref LL_GPDMA1_REQUEST_UCPD1_RX (*)
3785 * @arg @ref LL_GPDMA1_REQUEST_UCPD1_TX (*)
3786 * @arg @ref LL_GPDMA1_REQUEST_CORDIC_READ (*)
3787 * @arg @ref LL_GPDMA1_REQUEST_CORDIC_WRITE (*)
3788 * @arg @ref LL_GPDMA1_REQUEST_FMAC_READ (*)
3789 * @arg @ref LL_GPDMA1_REQUEST_FMAC_WRITE (*)
3790 * @arg @ref LL_GPDMA1_REQUEST_SAES_OUT (*)
3791 * @arg @ref LL_GPDMA1_REQUEST_SAES_IN (*)
3792 * @arg @ref LL_GPDMA1_REQUEST_I3C1_RX
3793 * @arg @ref LL_GPDMA1_REQUEST_I3C1_TX
3794 * @arg @ref LL_GPDMA1_REQUEST_I3C1_TC
3795 * @arg @ref LL_GPDMA1_REQUEST_I3C1_RS
3796 * @arg @ref LL_GPDMA1_REQUEST_I2C4_RX (*)
3797 * @arg @ref LL_GPDMA1_REQUEST_I2C4_TX (*)
3798 * @arg @ref LL_GPDMA1_REQUEST_LPTIM3_IC1 (*)
3799 * @arg @ref LL_GPDMA1_REQUEST_LPTIM3_IC2 (*)
3800 * @arg @ref LL_GPDMA1_REQUEST_LPTIM3_UE (*)
3801 * @arg @ref LL_GPDMA1_REQUEST_LPTIM5_IC1 (*)
3802 * @arg @ref LL_GPDMA1_REQUEST_LPTIM5_IC2 (*)
3803 * @arg @ref LL_GPDMA1_REQUEST_LPTIM5_UE (*)
3804 * @arg @ref LL_GPDMA1_REQUEST_LPTIM6_IC1 (*)
3805 * @arg @ref LL_GPDMA1_REQUEST_LPTIM6_IC2 (*)
3806 * @arg @ref LL_GPDMA1_REQUEST_LPTIM6_UE (*)
3807 * @arg @ref LL_GPDMA1_REQUEST_I3C2_RX (*)
3808 * @arg @ref LL_GPDMA1_REQUEST_I3C2_TX (*)
3809 * @arg @ref LL_GPDMA1_REQUEST_I3C2_TC (*)
3810 * @arg @ref LL_GPDMA1_REQUEST_I3C2_RS (*)
3811 *
3812 * @arg @ref LL_GPDMA2_REQUEST_ADC1
3813 * @arg @ref LL_GPDMA2_REQUEST_ADC2 (*)
3814 * @arg @ref LL_GPDMA2_REQUEST_DAC1_CH1
3815 * @arg @ref LL_GPDMA2_REQUEST_DAC1_CH2
3816 * @arg @ref LL_GPDMA2_REQUEST_TIM6_UP
3817 * @arg @ref LL_GPDMA2_REQUEST_TIM7_UP
3818 * @arg @ref LL_GPDMA2_REQUEST_SPI1_RX
3819 * @arg @ref LL_GPDMA2_REQUEST_SPI1_TX
3820 * @arg @ref LL_GPDMA2_REQUEST_SPI2_RX
3821 * @arg @ref LL_GPDMA2_REQUEST_SPI2_TX
3822 * @arg @ref LL_GPDMA2_REQUEST_SPI3_RX
3823 * @arg @ref LL_GPDMA2_REQUEST_SPI3_TX
3824 * @arg @ref LL_GPDMA2_REQUEST_I2C1_RX
3825 * @arg @ref LL_GPDMA2_REQUEST_I2C1_TX
3826 * @arg @ref LL_GPDMA2_REQUEST_I2C2_RX
3827 * @arg @ref LL_GPDMA2_REQUEST_I2C2_TX
3828 * @arg @ref LL_GPDMA2_REQUEST_I2C3_RX (*)
3829 * @arg @ref LL_GPDMA2_REQUEST_I2C3_TX (*)
3830 * @arg @ref LL_GPDMA2_REQUEST_USART1_RX
3831 * @arg @ref LL_GPDMA2_REQUEST_USART1_TX
3832 * @arg @ref LL_GPDMA2_REQUEST_USART2_RX
3833 * @arg @ref LL_GPDMA2_REQUEST_USART2_TX
3834 * @arg @ref LL_GPDMA2_REQUEST_USART3_RX
3835 * @arg @ref LL_GPDMA2_REQUEST_USART3_TX
3836 * @arg @ref LL_GPDMA2_REQUEST_UART4_RX (*)
3837 * @arg @ref LL_GPDMA2_REQUEST_UART4_TX (*)
3838 * @arg @ref LL_GPDMA2_REQUEST_UART5_RX (*)
3839 * @arg @ref LL_GPDMA2_REQUEST_UART5_TX (*)
3840 * @arg @ref LL_GPDMA2_REQUEST_USART6_RX (*)
3841 * @arg @ref LL_GPDMA2_REQUEST_USART6_TX (*)
3842 * @arg @ref LL_GPDMA2_REQUEST_UART7_RX (*)
3843 * @arg @ref LL_GPDMA2_REQUEST_UART7_TX (*)
3844 * @arg @ref LL_GPDMA2_REQUEST_UART8_RX (*)
3845 * @arg @ref LL_GPDMA2_REQUEST_UART8_TX (*)
3846 * @arg @ref LL_GPDMA2_REQUEST_UART9_RX (*)
3847 * @arg @ref LL_GPDMA2_REQUEST_UART9_TX (*)
3848 * @arg @ref LL_GPDMA2_REQUEST_USART10_RX (*)
3849 * @arg @ref LL_GPDMA2_REQUEST_USART10_TX (*)
3850 * @arg @ref LL_GPDMA2_REQUEST_USART11_RX (*)
3851 * @arg @ref LL_GPDMA2_REQUEST_USART11_TX (*)
3852 * @arg @ref LL_GPDMA2_REQUEST_UART12_RX (*)
3853 * @arg @ref LL_GPDMA2_REQUEST_UART12_TX (*)
3854 * @arg @ref LL_GPDMA2_REQUEST_LPUART1_RX
3855 * @arg @ref LL_GPDMA2_REQUEST_LPUART1_TX
3856 * @arg @ref LL_GPDMA2_REQUEST_SPI4_RX (*)
3857 * @arg @ref LL_GPDMA2_REQUEST_SPI4_TX (*)
3858 * @arg @ref LL_GPDMA2_REQUEST_SPI5_RX (*)
3859 * @arg @ref LL_GPDMA2_REQUEST_SPI5_TX (*)
3860 * @arg @ref LL_GPDMA2_REQUEST_SPI6_RX (*)
3861 * @arg @ref LL_GPDMA2_REQUEST_SPI6_TX (*)
3862 * @arg @ref LL_GPDMA2_REQUEST_SAI1_A (*)
3863 * @arg @ref LL_GPDMA2_REQUEST_SAI1_B (*)
3864 * @arg @ref LL_GPDMA2_REQUEST_SAI2_A (*)
3865 * @arg @ref LL_GPDMA2_REQUEST_SAI2_B (*)
3866 * @arg @ref LL_GPDMA2_REQUEST_OCTOSPI1 (*)
3867 * @arg @ref LL_GPDMA2_REQUEST_TIM1_CH1
3868 * @arg @ref LL_GPDMA2_REQUEST_TIM1_CH2
3869 * @arg @ref LL_GPDMA2_REQUEST_TIM1_CH3
3870 * @arg @ref LL_GPDMA2_REQUEST_TIM1_CH4
3871 * @arg @ref LL_GPDMA2_REQUEST_TIM1_UP
3872 * @arg @ref LL_GPDMA2_REQUEST_TIM1_TRIG
3873 * @arg @ref LL_GPDMA2_REQUEST_TIM1_COM
3874 * @arg @ref LL_GPDMA2_REQUEST_TIM8_CH1 (*)
3875 * @arg @ref LL_GPDMA2_REQUEST_TIM8_CH2 (*)
3876 * @arg @ref LL_GPDMA2_REQUEST_TIM8_CH3 (*)
3877 * @arg @ref LL_GPDMA2_REQUEST_TIM8_CH4 (*)
3878 * @arg @ref LL_GPDMA2_REQUEST_TIM8_UP (*)
3879 * @arg @ref LL_GPDMA2_REQUEST_TIM8_TRIG (*)
3880 * @arg @ref LL_GPDMA2_REQUEST_TIM8_COM (*)
3881 * @arg @ref LL_GPDMA2_REQUEST_TIM2_CH1
3882 * @arg @ref LL_GPDMA2_REQUEST_TIM2_CH2
3883 * @arg @ref LL_GPDMA2_REQUEST_TIM2_CH3
3884 * @arg @ref LL_GPDMA2_REQUEST_TIM2_CH4
3885 * @arg @ref LL_GPDMA2_REQUEST_TIM2_UP
3886 * @arg @ref LL_GPDMA2_REQUEST_TIM3_CH1
3887 * @arg @ref LL_GPDMA2_REQUEST_TIM3_CH2
3888 * @arg @ref LL_GPDMA2_REQUEST_TIM3_CH3
3889 * @arg @ref LL_GPDMA2_REQUEST_TIM3_CH4
3890 * @arg @ref LL_GPDMA2_REQUEST_TIM3_UP
3891 * @arg @ref LL_GPDMA2_REQUEST_TIM3_TRIG
3892 * @arg @ref LL_GPDMA2_REQUEST_TIM4_CH1 (*)
3893 * @arg @ref LL_GPDMA2_REQUEST_TIM4_CH2 (*)
3894 * @arg @ref LL_GPDMA2_REQUEST_TIM4_CH3 (*)
3895 * @arg @ref LL_GPDMA2_REQUEST_TIM4_CH4 (*)
3896 * @arg @ref LL_GPDMA2_REQUEST_TIM4_UP (*)
3897 * @arg @ref LL_GPDMA2_REQUEST_TIM5_CH1 (*)
3898 * @arg @ref LL_GPDMA2_REQUEST_TIM5_CH2 (*)
3899 * @arg @ref LL_GPDMA2_REQUEST_TIM5_CH3 (*)
3900 * @arg @ref LL_GPDMA2_REQUEST_TIM5_CH4 (*)
3901 * @arg @ref LL_GPDMA2_REQUEST_TIM5_UP (*)
3902 * @arg @ref LL_GPDMA2_REQUEST_TIM5_TRIG (*)
3903 * @arg @ref LL_GPDMA2_REQUEST_TIM15_CH1 (*)
3904 * @arg @ref LL_GPDMA2_REQUEST_TIM15_UP (*)
3905 * @arg @ref LL_GPDMA2_REQUEST_TIM15_TRIG (*)
3906 * @arg @ref LL_GPDMA2_REQUEST_TIM15_COM (*)
3907 * @arg @ref LL_GPDMA2_REQUEST_TIM16_CH1 (*)
3908 * @arg @ref LL_GPDMA2_REQUEST_TIM16_UP (*)
3909 * @arg @ref LL_GPDMA2_REQUEST_TIM17_CH1 (*)
3910 * @arg @ref LL_GPDMA2_REQUEST_TIM17_UP (*)
3911 * @arg @ref LL_GPDMA2_REQUEST_LPTIM1_IC1
3912 * @arg @ref LL_GPDMA2_REQUEST_LPTIM1_IC2
3913 * @arg @ref LL_GPDMA2_REQUEST_LPTIM1_UE
3914 * @arg @ref LL_GPDMA2_REQUEST_LPTIM2_IC1
3915 * @arg @ref LL_GPDMA2_REQUEST_LPTIM2_IC2
3916 * @arg @ref LL_GPDMA2_REQUEST_LPTIM2_UE
3917 * @arg @ref LL_GPDMA2_REQUEST_DCMI (*)
3918 * @arg @ref LL_GPDMA2_REQUEST_AES_OUT (*)
3919 * @arg @ref LL_GPDMA2_REQUEST_AES_IN (*)
3920 * @arg @ref LL_GPDMA2_REQUEST_HASH_IN
3921 * @arg @ref LL_GPDMA2_REQUEST_UCPD1_RX (*)
3922 * @arg @ref LL_GPDMA2_REQUEST_UCPD1_TX (*)
3923 * @arg @ref LL_GPDMA2_REQUEST_CORDIC_READ (*)
3924 * @arg @ref LL_GPDMA2_REQUEST_CORDIC_WRITE (*)
3925 * @arg @ref LL_GPDMA2_REQUEST_FMAC_READ (*)
3926 * @arg @ref LL_GPDMA2_REQUEST_FMAC_WRITE (*)
3927 * @arg @ref LL_GPDMA2_REQUEST_SAES_OUT (*)
3928 * @arg @ref LL_GPDMA2_REQUEST_SAES_IN (*)
3929 * @arg @ref LL_GPDMA2_REQUEST_I3C1_RX
3930 * @arg @ref LL_GPDMA2_REQUEST_I3C1_TX
3931 * @arg @ref LL_GPDMA2_REQUEST_I3C1_TC
3932 * @arg @ref LL_GPDMA2_REQUEST_I3C1_RS
3933 * @arg @ref LL_GPDMA2_REQUEST_I2C4_RX (*)
3934 * @arg @ref LL_GPDMA2_REQUEST_I2C4_TX (*)
3935 * @arg @ref LL_GPDMA2_REQUEST_LPTIM3_IC1 (*)
3936 * @arg @ref LL_GPDMA2_REQUEST_LPTIM3_IC2 (*)
3937 * @arg @ref LL_GPDMA2_REQUEST_LPTIM3_UE (*)
3938 * @arg @ref LL_GPDMA2_REQUEST_LPTIM5_IC1 (*)
3939 * @arg @ref LL_GPDMA2_REQUEST_LPTIM5_IC2 (*)
3940 * @arg @ref LL_GPDMA2_REQUEST_LPTIM5_UE (*)
3941 * @arg @ref LL_GPDMA2_REQUEST_LPTIM6_IC1 (*)
3942 * @arg @ref LL_GPDMA2_REQUEST_LPTIM6_IC2 (*)
3943 * @arg @ref LL_GPDMA2_REQUEST_LPTIM6_UE (*)
3944 * @arg @ref LL_GPDMA2_REQUEST_I3C2_RX (*)
3945 * @arg @ref LL_GPDMA2_REQUEST_I3C2_TX (*)
3946 * @arg @ref LL_GPDMA2_REQUEST_I3C2_TC (*)
3947 * @arg @ref LL_GPDMA2_REQUEST_I3C2_RS (*)
3948 *
3949 * @note (*) Availability depends on devices.
3950 * @retval None.
3951 */
LL_DMA_SetPeriphRequest(DMA_TypeDef * DMAx,uint32_t Channel,uint32_t Request)3952 __STATIC_INLINE void LL_DMA_SetPeriphRequest(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Request)
3953 {
3954 uint32_t dma_base_addr = (uint32_t)DMAx;
3955 MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR2, DMA_CTR2_REQSEL, Request);
3956 }
3957
3958 /**
3959 * @brief Get hardware request.
3960 * @note This API is used for all available DMA channels.
3961 * For LPDMA channels, REQSEL fields is reduced to 5 bits.
3962 * @rmtoll CTR2 REQSEL LL_DMA_GetPeriphRequest
3963 * @param DMAx DMAx Instance
3964 * @param Channel This parameter can be one of the following values:
3965 * @arg @ref LL_DMA_CHANNEL_0
3966 * @arg @ref LL_DMA_CHANNEL_1
3967 * @arg @ref LL_DMA_CHANNEL_2
3968 * @arg @ref LL_DMA_CHANNEL_3
3969 * @arg @ref LL_DMA_CHANNEL_4
3970 * @arg @ref LL_DMA_CHANNEL_5
3971 * @arg @ref LL_DMA_CHANNEL_6
3972 * @arg @ref LL_DMA_CHANNEL_7
3973 * @arg @ref LL_DMA_CHANNEL_8
3974 * @arg @ref LL_DMA_CHANNEL_9
3975 * @arg @ref LL_DMA_CHANNEL_10
3976 * @arg @ref LL_DMA_CHANNEL_11
3977 * @arg @ref LL_DMA_CHANNEL_12
3978 * @arg @ref LL_DMA_CHANNEL_13
3979 * @arg @ref LL_DMA_CHANNEL_14
3980 * @arg @ref LL_DMA_CHANNEL_15
3981 * @retval Returned value can be one of the following values:
3982 * @arg @ref LL_GPDMA1_REQUEST_ADC1
3983 * @arg @ref LL_GPDMA1_REQUEST_ADC2 (*)
3984 * @arg @ref LL_GPDMA1_REQUEST_DAC1_CH1
3985 * @arg @ref LL_GPDMA1_REQUEST_DAC1_CH2
3986 * @arg @ref LL_GPDMA1_REQUEST_TIM6_UP
3987 * @arg @ref LL_GPDMA1_REQUEST_TIM7_UP
3988 * @arg @ref LL_GPDMA1_REQUEST_SPI1_RX
3989 * @arg @ref LL_GPDMA1_REQUEST_SPI1_TX
3990 * @arg @ref LL_GPDMA1_REQUEST_SPI2_RX
3991 * @arg @ref LL_GPDMA1_REQUEST_SPI2_TX
3992 * @arg @ref LL_GPDMA1_REQUEST_SPI3_RX
3993 * @arg @ref LL_GPDMA1_REQUEST_SPI3_TX
3994 * @arg @ref LL_GPDMA1_REQUEST_I2C1_RX
3995 * @arg @ref LL_GPDMA1_REQUEST_I2C1_TX
3996 * @arg @ref LL_GPDMA1_REQUEST_I2C2_RX
3997 * @arg @ref LL_GPDMA1_REQUEST_I2C2_TX
3998 * @arg @ref LL_GPDMA1_REQUEST_I2C3_RX (*)
3999 * @arg @ref LL_GPDMA1_REQUEST_I2C3_TX (*)
4000 * @arg @ref LL_GPDMA1_REQUEST_USART1_RX
4001 * @arg @ref LL_GPDMA1_REQUEST_USART1_TX
4002 * @arg @ref LL_GPDMA1_REQUEST_USART2_RX
4003 * @arg @ref LL_GPDMA1_REQUEST_USART2_TX
4004 * @arg @ref LL_GPDMA1_REQUEST_USART3_RX
4005 * @arg @ref LL_GPDMA1_REQUEST_USART3_TX
4006 * @arg @ref LL_GPDMA1_REQUEST_UART4_RX (*)
4007 * @arg @ref LL_GPDMA1_REQUEST_UART4_TX (*)
4008 * @arg @ref LL_GPDMA1_REQUEST_UART5_RX (*)
4009 * @arg @ref LL_GPDMA1_REQUEST_UART5_TX (*)
4010 * @arg @ref LL_GPDMA1_REQUEST_USART6_RX (*)
4011 * @arg @ref LL_GPDMA1_REQUEST_USART6_TX (*)
4012 * @arg @ref LL_GPDMA1_REQUEST_UART7_RX (*)
4013 * @arg @ref LL_GPDMA1_REQUEST_UART7_TX (*)
4014 * @arg @ref LL_GPDMA1_REQUEST_UART8_RX (*)
4015 * @arg @ref LL_GPDMA1_REQUEST_UART8_TX (*)
4016 * @arg @ref LL_GPDMA1_REQUEST_UART9_RX (*)
4017 * @arg @ref LL_GPDMA1_REQUEST_UART9_TX (*)
4018 * @arg @ref LL_GPDMA1_REQUEST_USART10_RX (*)
4019 * @arg @ref LL_GPDMA1_REQUEST_USART10_TX (*)
4020 * @arg @ref LL_GPDMA1_REQUEST_USART11_RX (*)
4021 * @arg @ref LL_GPDMA1_REQUEST_USART11_TX (*)
4022 * @arg @ref LL_GPDMA1_REQUEST_UART12_RX (*)
4023 * @arg @ref LL_GPDMA1_REQUEST_UART12_TX (*)
4024 * @arg @ref LL_GPDMA1_REQUEST_LPUART1_RX
4025 * @arg @ref LL_GPDMA1_REQUEST_LPUART1_TX
4026 * @arg @ref LL_GPDMA1_REQUEST_SPI4_RX (*)
4027 * @arg @ref LL_GPDMA1_REQUEST_SPI4_TX (*)
4028 * @arg @ref LL_GPDMA1_REQUEST_SPI5_RX (*)
4029 * @arg @ref LL_GPDMA1_REQUEST_SPI5_TX (*)
4030 * @arg @ref LL_GPDMA1_REQUEST_SPI6_RX (*)
4031 * @arg @ref LL_GPDMA1_REQUEST_SPI6_TX (*)
4032 * @arg @ref LL_GPDMA1_REQUEST_SAI1_A (*)
4033 * @arg @ref LL_GPDMA1_REQUEST_SAI1_B (*)
4034 * @arg @ref LL_GPDMA1_REQUEST_SAI2_A (*)
4035 * @arg @ref LL_GPDMA1_REQUEST_SAI2_B (*)
4036 * @arg @ref LL_GPDMA1_REQUEST_OCTOSPI1 (*)
4037 * @arg @ref LL_GPDMA1_REQUEST_TIM1_CH1
4038 * @arg @ref LL_GPDMA1_REQUEST_TIM1_CH2
4039 * @arg @ref LL_GPDMA1_REQUEST_TIM1_CH3
4040 * @arg @ref LL_GPDMA1_REQUEST_TIM1_CH4
4041 * @arg @ref LL_GPDMA1_REQUEST_TIM1_UP
4042 * @arg @ref LL_GPDMA1_REQUEST_TIM1_TRIG
4043 * @arg @ref LL_GPDMA1_REQUEST_TIM1_COM
4044 * @arg @ref LL_GPDMA1_REQUEST_TIM8_CH1 (*)
4045 * @arg @ref LL_GPDMA1_REQUEST_TIM8_CH2 (*)
4046 * @arg @ref LL_GPDMA1_REQUEST_TIM8_CH3 (*)
4047 * @arg @ref LL_GPDMA1_REQUEST_TIM8_CH4 (*)
4048 * @arg @ref LL_GPDMA1_REQUEST_TIM8_UP (*)
4049 * @arg @ref LL_GPDMA1_REQUEST_TIM8_TRIG (*)
4050 * @arg @ref LL_GPDMA1_REQUEST_TIM8_COM (*)
4051 * @arg @ref LL_GPDMA1_REQUEST_TIM2_CH1
4052 * @arg @ref LL_GPDMA1_REQUEST_TIM2_CH2
4053 * @arg @ref LL_GPDMA1_REQUEST_TIM2_CH3
4054 * @arg @ref LL_GPDMA1_REQUEST_TIM2_CH4
4055 * @arg @ref LL_GPDMA1_REQUEST_TIM2_UP
4056 * @arg @ref LL_GPDMA1_REQUEST_TIM3_CH1
4057 * @arg @ref LL_GPDMA1_REQUEST_TIM3_CH2
4058 * @arg @ref LL_GPDMA1_REQUEST_TIM3_CH3
4059 * @arg @ref LL_GPDMA1_REQUEST_TIM3_CH4
4060 * @arg @ref LL_GPDMA1_REQUEST_TIM3_UP
4061 * @arg @ref LL_GPDMA1_REQUEST_TIM3_TRIG
4062 * @arg @ref LL_GPDMA1_REQUEST_TIM4_CH1 (*)
4063 * @arg @ref LL_GPDMA1_REQUEST_TIM4_CH2 (*)
4064 * @arg @ref LL_GPDMA1_REQUEST_TIM4_CH3 (*)
4065 * @arg @ref LL_GPDMA1_REQUEST_TIM4_CH4 (*)
4066 * @arg @ref LL_GPDMA1_REQUEST_TIM4_UP (*)
4067 * @arg @ref LL_GPDMA1_REQUEST_TIM5_CH1 (*)
4068 * @arg @ref LL_GPDMA1_REQUEST_TIM5_CH2 (*)
4069 * @arg @ref LL_GPDMA1_REQUEST_TIM5_CH3 (*)
4070 * @arg @ref LL_GPDMA1_REQUEST_TIM5_CH4 (*)
4071 * @arg @ref LL_GPDMA1_REQUEST_TIM5_UP (*)
4072 * @arg @ref LL_GPDMA1_REQUEST_TIM5_TRIG (*)
4073 * @arg @ref LL_GPDMA1_REQUEST_TIM15_CH1 (*)
4074 * @arg @ref LL_GPDMA1_REQUEST_TIM15_UP (*)
4075 * @arg @ref LL_GPDMA1_REQUEST_TIM15_TRIG (*)
4076 * @arg @ref LL_GPDMA1_REQUEST_TIM15_COM (*)
4077 * @arg @ref LL_GPDMA1_REQUEST_TIM16_CH1 (*)
4078 * @arg @ref LL_GPDMA1_REQUEST_TIM16_UP (*)
4079 * @arg @ref LL_GPDMA1_REQUEST_TIM17_CH1 (*)
4080 * @arg @ref LL_GPDMA1_REQUEST_TIM17_UP (*)
4081 * @arg @ref LL_GPDMA1_REQUEST_LPTIM1_IC1
4082 * @arg @ref LL_GPDMA1_REQUEST_LPTIM1_IC2
4083 * @arg @ref LL_GPDMA1_REQUEST_LPTIM1_UE
4084 * @arg @ref LL_GPDMA1_REQUEST_LPTIM2_IC1
4085 * @arg @ref LL_GPDMA1_REQUEST_LPTIM2_IC2
4086 * @arg @ref LL_GPDMA1_REQUEST_LPTIM2_UE
4087 * @arg @ref LL_GPDMA1_REQUEST_DCMI (*)
4088 * @arg @ref LL_GPDMA1_REQUEST_AES_OUT (*)
4089 * @arg @ref LL_GPDMA1_REQUEST_AES_IN (*)
4090 * @arg @ref LL_GPDMA1_REQUEST_HASH_IN
4091 * @arg @ref LL_GPDMA1_REQUEST_UCPD1_RX (*)
4092 * @arg @ref LL_GPDMA1_REQUEST_UCPD1_TX (*)
4093 * @arg @ref LL_GPDMA1_REQUEST_CORDIC_READ (*)
4094 * @arg @ref LL_GPDMA1_REQUEST_CORDIC_WRITE (*)
4095 * @arg @ref LL_GPDMA1_REQUEST_FMAC_READ (*)
4096 * @arg @ref LL_GPDMA1_REQUEST_FMAC_WRITE (*)
4097 * @arg @ref LL_GPDMA1_REQUEST_SAES_OUT (*)
4098 * @arg @ref LL_GPDMA1_REQUEST_SAES_IN (*)
4099 * @arg @ref LL_GPDMA1_REQUEST_I3C1_RX
4100 * @arg @ref LL_GPDMA1_REQUEST_I3C1_TX
4101 * @arg @ref LL_GPDMA1_REQUEST_I3C1_TC
4102 * @arg @ref LL_GPDMA1_REQUEST_I3C1_RS
4103 * @arg @ref LL_GPDMA1_REQUEST_I2C4_RX (*)
4104 * @arg @ref LL_GPDMA1_REQUEST_I2C4_TX (*)
4105 * @arg @ref LL_GPDMA1_REQUEST_LPTIM3_IC1 (*)
4106 * @arg @ref LL_GPDMA1_REQUEST_LPTIM3_IC2 (*)
4107 * @arg @ref LL_GPDMA1_REQUEST_LPTIM3_UE (*)
4108 * @arg @ref LL_GPDMA1_REQUEST_LPTIM5_IC1 (*)
4109 * @arg @ref LL_GPDMA1_REQUEST_LPTIM5_IC2 (*)
4110 * @arg @ref LL_GPDMA1_REQUEST_LPTIM5_UE (*)
4111 * @arg @ref LL_GPDMA1_REQUEST_LPTIM6_IC1 (*)
4112 * @arg @ref LL_GPDMA1_REQUEST_LPTIM6_IC2 (*)
4113 * @arg @ref LL_GPDMA1_REQUEST_LPTIM6_UE (*)
4114 * @arg @ref LL_GPDMA1_REQUEST_I3C2_RX (*)
4115 * @arg @ref LL_GPDMA1_REQUEST_I3C2_TX (*)
4116 * @arg @ref LL_GPDMA1_REQUEST_I3C2_TC (*)
4117 * @arg @ref LL_GPDMA1_REQUEST_I3C2_RS (*)
4118 *
4119 * @arg @ref LL_GPDMA2_REQUEST_ADC1
4120 * @arg @ref LL_GPDMA2_REQUEST_ADC2 (*)
4121 * @arg @ref LL_GPDMA2_REQUEST_DAC1_CH1
4122 * @arg @ref LL_GPDMA2_REQUEST_DAC1_CH2
4123 * @arg @ref LL_GPDMA2_REQUEST_TIM6_UP
4124 * @arg @ref LL_GPDMA2_REQUEST_TIM7_UP
4125 * @arg @ref LL_GPDMA2_REQUEST_SPI1_RX
4126 * @arg @ref LL_GPDMA2_REQUEST_SPI1_TX
4127 * @arg @ref LL_GPDMA2_REQUEST_SPI2_RX
4128 * @arg @ref LL_GPDMA2_REQUEST_SPI2_TX
4129 * @arg @ref LL_GPDMA2_REQUEST_SPI3_RX
4130 * @arg @ref LL_GPDMA2_REQUEST_SPI3_TX
4131 * @arg @ref LL_GPDMA2_REQUEST_I2C1_RX
4132 * @arg @ref LL_GPDMA2_REQUEST_I2C1_TX
4133 * @arg @ref LL_GPDMA2_REQUEST_I2C2_RX
4134 * @arg @ref LL_GPDMA2_REQUEST_I2C2_TX
4135 * @arg @ref LL_GPDMA2_REQUEST_I2C3_RX (*)
4136 * @arg @ref LL_GPDMA2_REQUEST_I2C3_TX (*)
4137 * @arg @ref LL_GPDMA2_REQUEST_USART1_RX
4138 * @arg @ref LL_GPDMA2_REQUEST_USART1_TX
4139 * @arg @ref LL_GPDMA2_REQUEST_USART2_RX
4140 * @arg @ref LL_GPDMA2_REQUEST_USART2_TX
4141 * @arg @ref LL_GPDMA2_REQUEST_USART3_RX
4142 * @arg @ref LL_GPDMA2_REQUEST_USART3_TX
4143 * @arg @ref LL_GPDMA2_REQUEST_UART4_RX (*)
4144 * @arg @ref LL_GPDMA2_REQUEST_UART4_TX (*)
4145 * @arg @ref LL_GPDMA2_REQUEST_UART5_RX (*)
4146 * @arg @ref LL_GPDMA2_REQUEST_UART5_TX (*)
4147 * @arg @ref LL_GPDMA2_REQUEST_USART6_RX (*)
4148 * @arg @ref LL_GPDMA2_REQUEST_USART6_TX (*)
4149 * @arg @ref LL_GPDMA2_REQUEST_UART7_RX (*)
4150 * @arg @ref LL_GPDMA2_REQUEST_UART7_TX (*)
4151 * @arg @ref LL_GPDMA2_REQUEST_UART8_RX (*)
4152 * @arg @ref LL_GPDMA2_REQUEST_UART8_TX (*)
4153 * @arg @ref LL_GPDMA2_REQUEST_UART9_RX (*)
4154 * @arg @ref LL_GPDMA2_REQUEST_UART9_TX (*)
4155 * @arg @ref LL_GPDMA2_REQUEST_USART10_RX (*)
4156 * @arg @ref LL_GPDMA2_REQUEST_USART10_TX (*)
4157 * @arg @ref LL_GPDMA2_REQUEST_USART11_RX (*)
4158 * @arg @ref LL_GPDMA2_REQUEST_USART11_TX (*)
4159 * @arg @ref LL_GPDMA2_REQUEST_UART12_RX (*)
4160 * @arg @ref LL_GPDMA2_REQUEST_UART12_TX (*)
4161 * @arg @ref LL_GPDMA2_REQUEST_LPUART1_RX
4162 * @arg @ref LL_GPDMA2_REQUEST_LPUART1_TX
4163 * @arg @ref LL_GPDMA2_REQUEST_SPI4_RX (*)
4164 * @arg @ref LL_GPDMA2_REQUEST_SPI4_TX (*)
4165 * @arg @ref LL_GPDMA2_REQUEST_SPI5_RX (*)
4166 * @arg @ref LL_GPDMA2_REQUEST_SPI5_TX (*)
4167 * @arg @ref LL_GPDMA2_REQUEST_SPI6_RX (*)
4168 * @arg @ref LL_GPDMA2_REQUEST_SPI6_TX (*)
4169 * @arg @ref LL_GPDMA2_REQUEST_SAI1_A (*)
4170 * @arg @ref LL_GPDMA2_REQUEST_SAI1_B (*)
4171 * @arg @ref LL_GPDMA2_REQUEST_SAI2_A (*)
4172 * @arg @ref LL_GPDMA2_REQUEST_SAI2_B (*)
4173 * @arg @ref LL_GPDMA2_REQUEST_OCTOSPI1 (*)
4174 * @arg @ref LL_GPDMA2_REQUEST_TIM1_CH1
4175 * @arg @ref LL_GPDMA2_REQUEST_TIM1_CH2
4176 * @arg @ref LL_GPDMA2_REQUEST_TIM1_CH3
4177 * @arg @ref LL_GPDMA2_REQUEST_TIM1_CH4
4178 * @arg @ref LL_GPDMA2_REQUEST_TIM1_UP
4179 * @arg @ref LL_GPDMA2_REQUEST_TIM1_TRIG
4180 * @arg @ref LL_GPDMA2_REQUEST_TIM1_COM
4181 * @arg @ref LL_GPDMA2_REQUEST_TIM8_CH1 (*)
4182 * @arg @ref LL_GPDMA2_REQUEST_TIM8_CH2 (*)
4183 * @arg @ref LL_GPDMA2_REQUEST_TIM8_CH3 (*)
4184 * @arg @ref LL_GPDMA2_REQUEST_TIM8_CH4 (*)
4185 * @arg @ref LL_GPDMA2_REQUEST_TIM8_UP (*)
4186 * @arg @ref LL_GPDMA2_REQUEST_TIM8_TRIG (*)
4187 * @arg @ref LL_GPDMA2_REQUEST_TIM8_COM (*)
4188 * @arg @ref LL_GPDMA2_REQUEST_TIM2_CH1
4189 * @arg @ref LL_GPDMA2_REQUEST_TIM2_CH2
4190 * @arg @ref LL_GPDMA2_REQUEST_TIM2_CH3
4191 * @arg @ref LL_GPDMA2_REQUEST_TIM2_CH4
4192 * @arg @ref LL_GPDMA2_REQUEST_TIM2_UP
4193 * @arg @ref LL_GPDMA2_REQUEST_TIM3_CH1
4194 * @arg @ref LL_GPDMA2_REQUEST_TIM3_CH2
4195 * @arg @ref LL_GPDMA2_REQUEST_TIM3_CH3
4196 * @arg @ref LL_GPDMA2_REQUEST_TIM3_CH4
4197 * @arg @ref LL_GPDMA2_REQUEST_TIM3_UP
4198 * @arg @ref LL_GPDMA2_REQUEST_TIM3_TRIG
4199 * @arg @ref LL_GPDMA2_REQUEST_TIM4_CH1 (*)
4200 * @arg @ref LL_GPDMA2_REQUEST_TIM4_CH2 (*)
4201 * @arg @ref LL_GPDMA2_REQUEST_TIM4_CH3 (*)
4202 * @arg @ref LL_GPDMA2_REQUEST_TIM4_CH4 (*)
4203 * @arg @ref LL_GPDMA2_REQUEST_TIM4_UP (*)
4204 * @arg @ref LL_GPDMA2_REQUEST_TIM5_CH1 (*)
4205 * @arg @ref LL_GPDMA2_REQUEST_TIM5_CH2 (*)
4206 * @arg @ref LL_GPDMA2_REQUEST_TIM5_CH3 (*)
4207 * @arg @ref LL_GPDMA2_REQUEST_TIM5_CH4 (*)
4208 * @arg @ref LL_GPDMA2_REQUEST_TIM5_UP (*)
4209 * @arg @ref LL_GPDMA2_REQUEST_TIM5_TRIG (*)
4210 * @arg @ref LL_GPDMA2_REQUEST_TIM15_CH1 (*)
4211 * @arg @ref LL_GPDMA2_REQUEST_TIM15_UP (*)
4212 * @arg @ref LL_GPDMA2_REQUEST_TIM15_TRIG (*)
4213 * @arg @ref LL_GPDMA2_REQUEST_TIM15_COM (*)
4214 * @arg @ref LL_GPDMA2_REQUEST_TIM16_CH1 (*)
4215 * @arg @ref LL_GPDMA2_REQUEST_TIM16_UP (*)
4216 * @arg @ref LL_GPDMA2_REQUEST_TIM17_CH1 (*)
4217 * @arg @ref LL_GPDMA2_REQUEST_TIM17_UP (*)
4218 * @arg @ref LL_GPDMA2_REQUEST_LPTIM1_IC1
4219 * @arg @ref LL_GPDMA2_REQUEST_LPTIM1_IC2
4220 * @arg @ref LL_GPDMA2_REQUEST_LPTIM1_UE
4221 * @arg @ref LL_GPDMA2_REQUEST_LPTIM2_IC1
4222 * @arg @ref LL_GPDMA2_REQUEST_LPTIM2_IC2
4223 * @arg @ref LL_GPDMA2_REQUEST_LPTIM2_UE
4224 * @arg @ref LL_GPDMA2_REQUEST_DCMI (*)
4225 * @arg @ref LL_GPDMA2_REQUEST_AES_OUT (*)
4226 * @arg @ref LL_GPDMA2_REQUEST_AES_IN (*)
4227 * @arg @ref LL_GPDMA2_REQUEST_HASH_IN
4228 * @arg @ref LL_GPDMA2_REQUEST_UCPD1_RX (*)
4229 * @arg @ref LL_GPDMA2_REQUEST_UCPD1_TX (*)
4230 * @arg @ref LL_GPDMA2_REQUEST_CORDIC_READ (*)
4231 * @arg @ref LL_GPDMA2_REQUEST_CORDIC_WRITE (*)
4232 * @arg @ref LL_GPDMA2_REQUEST_FMAC_READ (*)
4233 * @arg @ref LL_GPDMA2_REQUEST_FMAC_WRITE (*)
4234 * @arg @ref LL_GPDMA2_REQUEST_SAES_OUT (*)
4235 * @arg @ref LL_GPDMA2_REQUEST_SAES_IN (*)
4236 * @arg @ref LL_GPDMA2_REQUEST_I3C1_RX
4237 * @arg @ref LL_GPDMA2_REQUEST_I3C1_TX
4238 * @arg @ref LL_GPDMA2_REQUEST_I3C1_TC
4239 * @arg @ref LL_GPDMA2_REQUEST_I3C1_RS
4240 * @arg @ref LL_GPDMA2_REQUEST_I2C4_RX (*)
4241 * @arg @ref LL_GPDMA2_REQUEST_I2C4_TX (*)
4242 * @arg @ref LL_GPDMA2_REQUEST_LPTIM3_IC1 (*)
4243 * @arg @ref LL_GPDMA2_REQUEST_LPTIM3_IC2 (*)
4244 * @arg @ref LL_GPDMA2_REQUEST_LPTIM3_UE (*)
4245 * @arg @ref LL_GPDMA2_REQUEST_LPTIM5_IC1 (*)
4246 * @arg @ref LL_GPDMA2_REQUEST_LPTIM5_IC2 (*)
4247 * @arg @ref LL_GPDMA2_REQUEST_LPTIM5_UE (*)
4248 * @arg @ref LL_GPDMA2_REQUEST_LPTIM6_IC1 (*)
4249 * @arg @ref LL_GPDMA2_REQUEST_LPTIM6_IC2 (*)
4250 * @arg @ref LL_GPDMA2_REQUEST_LPTIM6_UE (*)
4251 * @arg @ref LL_GPDMA2_REQUEST_I3C2_RX (*)
4252 * @arg @ref LL_GPDMA2_REQUEST_I3C2_TX (*)
4253 * @arg @ref LL_GPDMA2_REQUEST_I3C2_TC (*)
4254 * @arg @ref LL_GPDMA2_REQUEST_I3C2_RS (*)
4255 *
4256 * @note (*) Availability depends on devices.
4257 */
LL_DMA_GetPeriphRequest(DMA_TypeDef * DMAx,uint32_t Channel)4258 __STATIC_INLINE uint32_t LL_DMA_GetPeriphRequest(DMA_TypeDef *DMAx, uint32_t Channel)
4259 {
4260 uint32_t dma_base_addr = (uint32_t)DMAx;
4261 return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR2, DMA_CTR2_REQSEL));
4262 }
4263
4264 /**
4265 * @brief Set hardware trigger.
4266 * @note This API is used for all available DMA channels.
4267 * For LPDMA channels, TRIGSEL fields is reduced to 5 bits.
4268 * @rmtoll CTR2 TRIGSEL LL_DMA_SetHWTrigger
4269 * @param DMAx DMAx Instance
4270 * @param Channel This parameter can be one of the following values:
4271 * @arg @ref LL_DMA_CHANNEL_0
4272 * @arg @ref LL_DMA_CHANNEL_1
4273 * @arg @ref LL_DMA_CHANNEL_2
4274 * @arg @ref LL_DMA_CHANNEL_3
4275 * @arg @ref LL_DMA_CHANNEL_4
4276 * @arg @ref LL_DMA_CHANNEL_5
4277 * @arg @ref LL_DMA_CHANNEL_6
4278 * @arg @ref LL_DMA_CHANNEL_7
4279 * @arg @ref LL_DMA_CHANNEL_8
4280 * @arg @ref LL_DMA_CHANNEL_9
4281 * @arg @ref LL_DMA_CHANNEL_10
4282 * @arg @ref LL_DMA_CHANNEL_11
4283 * @arg @ref LL_DMA_CHANNEL_12
4284 * @arg @ref LL_DMA_CHANNEL_13
4285 * @arg @ref LL_DMA_CHANNEL_14
4286 * @arg @ref LL_DMA_CHANNEL_15
4287 * @param Trigger This parameter can be one of the following values:
4288 * @arg @ref LL_GPDMA1_TRIGGER_EXTI_LINE0
4289 * @arg @ref LL_GPDMA1_TRIGGER_EXTI_LINE1
4290 * @arg @ref LL_GPDMA1_TRIGGER_EXTI_LINE2
4291 * @arg @ref LL_GPDMA1_TRIGGER_EXTI_LINE3
4292 * @arg @ref LL_GPDMA1_TRIGGER_EXTI_LINE4
4293 * @arg @ref LL_GPDMA1_TRIGGER_EXTI_LINE5
4294 * @arg @ref LL_GPDMA1_TRIGGER_EXTI_LINE6
4295 * @arg @ref LL_GPDMA1_TRIGGER_EXTI_LINE7
4296 * @arg @ref LL_GPDMA1_TRIGGER_TAMP_TRG1
4297 * @arg @ref LL_GPDMA1_TRIGGER_TAMP_TRG2
4298 * @arg @ref LL_GPDMA1_TRIGGER_TAMP_TRG3 (*)
4299 * @arg @ref LL_GPDMA1_TRIGGER_LPTIM1_CH1
4300 * @arg @ref LL_GPDMA1_TRIGGER_LPTIM1_CH2
4301 * @arg @ref LL_GPDMA1_TRIGGER_LPTIM2_CH1
4302 * @arg @ref LL_GPDMA1_TRIGGER_LPTIM2_CH2
4303 * @arg @ref LL_GPDMA1_TRIGGER_RTC_ALRA_TRG
4304 * @arg @ref LL_GPDMA1_TRIGGER_RTC_ALRB_TRG
4305 * @arg @ref LL_GPDMA1_TRIGGER_RTC_WUT_TRG
4306 * @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH0_TCF
4307 * @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH1_TCF
4308 * @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH2_TCF
4309 * @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH3_TCF
4310 * @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH4_TCF
4311 * @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH5_TCF
4312 * @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH6_TCF
4313 * @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH7_TCF
4314 * @arg @ref LL_GPDMA1_TRIGGER_GPDMA2_CH0_TCF
4315 * @arg @ref LL_GPDMA1_TRIGGER_GPDMA2_CH1_TCF
4316 * @arg @ref LL_GPDMA1_TRIGGER_GPDMA2_CH2_TCF
4317 * @arg @ref LL_GPDMA1_TRIGGER_GPDMA2_CH3_TCF
4318 * @arg @ref LL_GPDMA1_TRIGGER_GPDMA2_CH4_TCF
4319 * @arg @ref LL_GPDMA1_TRIGGER_GPDMA2_CH5_TCF
4320 * @arg @ref LL_GPDMA1_TRIGGER_GPDMA2_CH6_TCF
4321 * @arg @ref LL_GPDMA1_TRIGGER_GPDMA2_CH7_TCF
4322 * @arg @ref LL_GPDMA1_TRIGGER_TIM2_TRGO
4323 * @arg @ref LL_GPDMA1_TRIGGER_TIM15_TRGO
4324 * @arg @ref LL_GPDMA1_TRIGGER_TIM12_TRGO
4325 * @arg @ref LL_GPDMA1_TRIGGER_LPTIM3_CH1
4326 * @arg @ref LL_GPDMA1_TRIGGER_LPTIM3_CH2
4327 * @arg @ref LL_GPDMA1_TRIGGER_LPTIM4_AIT
4328 * @arg @ref LL_GPDMA1_TRIGGER_LPTIM5_CH1
4329 * @arg @ref LL_GPDMA1_TRIGGER_LPTIM5_CH2
4330 * @arg @ref LL_GPDMA1_TRIGGER_LPTIM6_CH1
4331 * @arg @ref LL_GPDMA1_TRIGGER_LPTIM6_CH2
4332 * @arg @ref LL_GPDMA1_TRIGGER_TIM15_TRGO (*)
4333 * @arg @ref LL_GPDMA1_TRIGGER_TIM12_TRGO (*)
4334 * @arg @ref LL_GPDMA1_TRIGGER_LPTIM3_CH1 (*)
4335 * @arg @ref LL_GPDMA1_TRIGGER_LPTIM3_CH2 (*)
4336 * @arg @ref LL_GPDMA1_TRIGGER_LPTIM4_AIT (*)
4337 * @arg @ref LL_GPDMA1_TRIGGER_LPTIM5_CH1 (*)
4338 * @arg @ref LL_GPDMA1_TRIGGER_LPTIM5_CH2 (*)
4339 * @arg @ref LL_GPDMA1_TRIGGER_LPTIM6_CH1 (*)
4340 * @arg @ref LL_GPDMA1_TRIGGER_LPTIM6_CH2 (*)
4341 * @arg @ref LL_GPDMA1_TRIGGER_COMP1_OUT (*)
4342 * @arg @ref LL_GPDMA1_TRIGGER_EVENTOUT (*)
4343 *
4344 * @arg @ref LL_GPDMA2_TRIGGER_EXTI_LINE0
4345 * @arg @ref LL_GPDMA2_TRIGGER_EXTI_LINE1
4346 * @arg @ref LL_GPDMA2_TRIGGER_EXTI_LINE2
4347 * @arg @ref LL_GPDMA2_TRIGGER_EXTI_LINE3
4348 * @arg @ref LL_GPDMA2_TRIGGER_EXTI_LINE4
4349 * @arg @ref LL_GPDMA2_TRIGGER_EXTI_LINE5
4350 * @arg @ref LL_GPDMA2_TRIGGER_EXTI_LINE6
4351 * @arg @ref LL_GPDMA2_TRIGGER_EXTI_LINE7
4352 * @arg @ref LL_GPDMA2_TRIGGER_TAMP_TRG1
4353 * @arg @ref LL_GPDMA2_TRIGGER_TAMP_TRG2
4354 * @arg @ref LL_GPDMA2_TRIGGER_TAMP_TRG3 (*)
4355 * @arg @ref LL_GPDMA2_TRIGGER_LPTIM1_CH1
4356 * @arg @ref LL_GPDMA2_TRIGGER_LPTIM1_CH2
4357 * @arg @ref LL_GPDMA2_TRIGGER_LPTIM2_CH1
4358 * @arg @ref LL_GPDMA2_TRIGGER_LPTIM2_CH2
4359 * @arg @ref LL_GPDMA2_TRIGGER_RTC_ALRA_TRG
4360 * @arg @ref LL_GPDMA2_TRIGGER_RTC_ALRB_TRG
4361 * @arg @ref LL_GPDMA2_TRIGGER_RTC_WUT_TRG
4362 * @arg @ref LL_GPDMA2_TRIGGER_GPDMA1_CH0_TCF
4363 * @arg @ref LL_GPDMA2_TRIGGER_GPDMA1_CH1_TCF
4364 * @arg @ref LL_GPDMA2_TRIGGER_GPDMA1_CH2_TCF
4365 * @arg @ref LL_GPDMA2_TRIGGER_GPDMA1_CH3_TCF
4366 * @arg @ref LL_GPDMA2_TRIGGER_GPDMA1_CH4_TCF
4367 * @arg @ref LL_GPDMA2_TRIGGER_GPDMA1_CH5_TCF
4368 * @arg @ref LL_GPDMA2_TRIGGER_GPDMA1_CH6_TCF
4369 * @arg @ref LL_GPDMA2_TRIGGER_GPDMA1_CH7_TCF
4370 * @arg @ref LL_GPDMA2_TRIGGER_GPDMA2_CH0_TCF
4371 * @arg @ref LL_GPDMA2_TRIGGER_GPDMA2_CH1_TCF
4372 * @arg @ref LL_GPDMA2_TRIGGER_GPDMA2_CH2_TCF
4373 * @arg @ref LL_GPDMA2_TRIGGER_GPDMA2_CH3_TCF
4374 * @arg @ref LL_GPDMA2_TRIGGER_GPDMA2_CH4_TCF
4375 * @arg @ref LL_GPDMA2_TRIGGER_GPDMA2_CH5_TCF
4376 * @arg @ref LL_GPDMA2_TRIGGER_GPDMA2_CH6_TCF
4377 * @arg @ref LL_GPDMA2_TRIGGER_GPDMA2_CH7_TCF
4378 * @arg @ref LL_GPDMA2_TRIGGER_TIM2_TRGO
4379 * @arg @ref LL_GPDMA2_TRIGGER_TIM15_TRGO
4380 * @arg @ref LL_GPDMA2_TRIGGER_TIM12_TRGO
4381 * @arg @ref LL_GPDMA2_TRIGGER_LPTIM3_CH1
4382 * @arg @ref LL_GPDMA2_TRIGGER_LPTIM3_CH2
4383 * @arg @ref LL_GPDMA2_TRIGGER_LPTIM4_AIT
4384 * @arg @ref LL_GPDMA2_TRIGGER_LPTIM5_CH1
4385 * @arg @ref LL_GPDMA2_TRIGGER_LPTIM5_CH2
4386 * @arg @ref LL_GPDMA2_TRIGGER_LPTIM6_CH1
4387 * @arg @ref LL_GPDMA2_TRIGGER_LPTIM6_CH2
4388 * @arg @ref LL_GPDMA2_TRIGGER_TIM15_TRGO (*)
4389 * @arg @ref LL_GPDMA2_TRIGGER_TIM12_TRGO (*)
4390 * @arg @ref LL_GPDMA2_TRIGGER_LPTIM3_CH1 (*)
4391 * @arg @ref LL_GPDMA2_TRIGGER_LPTIM3_CH2 (*)
4392 * @arg @ref LL_GPDMA2_TRIGGER_LPTIM4_AIT (*)
4393 * @arg @ref LL_GPDMA2_TRIGGER_LPTIM5_CH1 (*)
4394 * @arg @ref LL_GPDMA2_TRIGGER_LPTIM5_CH2 (*)
4395 * @arg @ref LL_GPDMA2_TRIGGER_LPTIM6_CH1 (*)
4396 * @arg @ref LL_GPDMA2_TRIGGER_LPTIM6_CH2 (*)
4397 * @arg @ref LL_GPDMA2_TRIGGER_COMP1_OUT (*)
4398 * @arg @ref LL_GPDMA2_TRIGGER_EVENTOUT (*)
4399 *
4400 * @note (*) Availability depends on devices.
4401 * @retval None.
4402 */
LL_DMA_SetHWTrigger(DMA_TypeDef * DMAx,uint32_t Channel,uint32_t Trigger)4403 __STATIC_INLINE void LL_DMA_SetHWTrigger(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Trigger)
4404 {
4405 uint32_t dma_base_addr = (uint32_t)DMAx;
4406 MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR2, DMA_CTR2_TRIGSEL,
4407 (Trigger << DMA_CTR2_TRIGSEL_Pos) & DMA_CTR2_TRIGSEL);
4408 }
4409
4410 /**
4411 * @brief Get hardware triggers.
4412 * @note This API is used for all available DMA channels.
4413 * For LPDMA channels, TRIGSEL fields is reduced to 5 bits.
4414 * @rmtoll CTR2 TRIGSEL LL_DMA_GetHWTrigger
4415 * @param DMAx DMAx Instance
4416 * @param Channel This parameter can be one of the following values:
4417 * @arg @ref LL_DMA_CHANNEL_0
4418 * @arg @ref LL_DMA_CHANNEL_1
4419 * @arg @ref LL_DMA_CHANNEL_2
4420 * @arg @ref LL_DMA_CHANNEL_3
4421 * @arg @ref LL_DMA_CHANNEL_4
4422 * @arg @ref LL_DMA_CHANNEL_5
4423 * @arg @ref LL_DMA_CHANNEL_6
4424 * @arg @ref LL_DMA_CHANNEL_7
4425 * @arg @ref LL_DMA_CHANNEL_8
4426 * @arg @ref LL_DMA_CHANNEL_9
4427 * @arg @ref LL_DMA_CHANNEL_10
4428 * @arg @ref LL_DMA_CHANNEL_11
4429 * @arg @ref LL_DMA_CHANNEL_12
4430 * @arg @ref LL_DMA_CHANNEL_13
4431 * @arg @ref LL_DMA_CHANNEL_14
4432 * @arg @ref LL_DMA_CHANNEL_15
4433 * @retval Returned value can be one of the following values:
4434 * @arg @ref LL_GPDMA1_TRIGGER_EXTI_LINE0
4435 * @arg @ref LL_GPDMA1_TRIGGER_EXTI_LINE1
4436 * @arg @ref LL_GPDMA1_TRIGGER_EXTI_LINE2
4437 * @arg @ref LL_GPDMA1_TRIGGER_EXTI_LINE3
4438 * @arg @ref LL_GPDMA1_TRIGGER_EXTI_LINE4
4439 * @arg @ref LL_GPDMA1_TRIGGER_EXTI_LINE5
4440 * @arg @ref LL_GPDMA1_TRIGGER_EXTI_LINE6
4441 * @arg @ref LL_GPDMA1_TRIGGER_EXTI_LINE7
4442 * @arg @ref LL_GPDMA1_TRIGGER_TAMP_TRG1
4443 * @arg @ref LL_GPDMA1_TRIGGER_TAMP_TRG2
4444 * @arg @ref LL_GPDMA1_TRIGGER_TAMP_TRG3 (*)
4445 * @arg @ref LL_GPDMA1_TRIGGER_LPTIM1_CH1
4446 * @arg @ref LL_GPDMA1_TRIGGER_LPTIM1_CH2
4447 * @arg @ref LL_GPDMA1_TRIGGER_LPTIM2_CH1
4448 * @arg @ref LL_GPDMA1_TRIGGER_LPTIM2_CH2
4449 * @arg @ref LL_GPDMA1_TRIGGER_RTC_ALRA_TRG
4450 * @arg @ref LL_GPDMA1_TRIGGER_RTC_ALRB_TRG
4451 * @arg @ref LL_GPDMA1_TRIGGER_RTC_WUT_TRG
4452 * @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH0_TCF
4453 * @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH1_TCF
4454 * @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH2_TCF
4455 * @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH3_TCF
4456 * @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH4_TCF
4457 * @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH5_TCF
4458 * @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH6_TCF
4459 * @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH7_TCF
4460 * @arg @ref LL_GPDMA1_TRIGGER_GPDMA2_CH0_TCF
4461 * @arg @ref LL_GPDMA1_TRIGGER_GPDMA2_CH1_TCF
4462 * @arg @ref LL_GPDMA1_TRIGGER_GPDMA2_CH2_TCF
4463 * @arg @ref LL_GPDMA1_TRIGGER_GPDMA2_CH3_TCF
4464 * @arg @ref LL_GPDMA1_TRIGGER_GPDMA2_CH4_TCF
4465 * @arg @ref LL_GPDMA1_TRIGGER_GPDMA2_CH5_TCF
4466 * @arg @ref LL_GPDMA1_TRIGGER_GPDMA2_CH6_TCF
4467 * @arg @ref LL_GPDMA1_TRIGGER_GPDMA2_CH7_TCF
4468 * @arg @ref LL_GPDMA1_TRIGGER_TIM2_TRGO
4469 * @arg @ref LL_GPDMA1_TRIGGER_TIM15_TRGO
4470 * @arg @ref LL_GPDMA1_TRIGGER_TIM12_TRGO
4471 * @arg @ref LL_GPDMA1_TRIGGER_LPTIM3_CH1
4472 * @arg @ref LL_GPDMA1_TRIGGER_LPTIM3_CH2
4473 * @arg @ref LL_GPDMA1_TRIGGER_LPTIM4_AIT
4474 * @arg @ref LL_GPDMA1_TRIGGER_LPTIM5_CH1
4475 * @arg @ref LL_GPDMA1_TRIGGER_LPTIM5_CH2
4476 * @arg @ref LL_GPDMA1_TRIGGER_LPTIM6_CH1
4477 * @arg @ref LL_GPDMA1_TRIGGER_LPTIM6_CH2
4478 * @arg @ref LL_GPDMA1_TRIGGER_TIM15_TRGO (*)
4479 * @arg @ref LL_GPDMA1_TRIGGER_TIM12_TRGO (*)
4480 * @arg @ref LL_GPDMA1_TRIGGER_LPTIM3_CH1 (*)
4481 * @arg @ref LL_GPDMA1_TRIGGER_LPTIM3_CH2 (*)
4482 * @arg @ref LL_GPDMA1_TRIGGER_LPTIM4_AIT (*)
4483 * @arg @ref LL_GPDMA1_TRIGGER_LPTIM5_CH1 (*)
4484 * @arg @ref LL_GPDMA1_TRIGGER_LPTIM5_CH2 (*)
4485 * @arg @ref LL_GPDMA1_TRIGGER_LPTIM6_CH1 (*)
4486 * @arg @ref LL_GPDMA1_TRIGGER_LPTIM6_CH2 (*)
4487 * @arg @ref LL_GPDMA1_TRIGGER_COMP1_OUT (*)
4488 * @arg @ref LL_GPDMA1_TRIGGER_EVENTOUT (*)
4489 *
4490 * @arg @ref LL_GPDMA2_TRIGGER_EXTI_LINE0
4491 * @arg @ref LL_GPDMA2_TRIGGER_EXTI_LINE1
4492 * @arg @ref LL_GPDMA2_TRIGGER_EXTI_LINE2
4493 * @arg @ref LL_GPDMA2_TRIGGER_EXTI_LINE3
4494 * @arg @ref LL_GPDMA2_TRIGGER_EXTI_LINE4
4495 * @arg @ref LL_GPDMA2_TRIGGER_EXTI_LINE5
4496 * @arg @ref LL_GPDMA2_TRIGGER_EXTI_LINE6
4497 * @arg @ref LL_GPDMA2_TRIGGER_EXTI_LINE7
4498 * @arg @ref LL_GPDMA2_TRIGGER_TAMP_TRG1
4499 * @arg @ref LL_GPDMA2_TRIGGER_TAMP_TRG2
4500 * @arg @ref LL_GPDMA2_TRIGGER_TAMP_TRG3 (*)
4501 * @arg @ref LL_GPDMA2_TRIGGER_LPTIM1_CH1
4502 * @arg @ref LL_GPDMA2_TRIGGER_LPTIM1_CH2
4503 * @arg @ref LL_GPDMA2_TRIGGER_LPTIM2_CH1
4504 * @arg @ref LL_GPDMA2_TRIGGER_LPTIM2_CH2
4505 * @arg @ref LL_GPDMA2_TRIGGER_RTC_ALRA_TRG
4506 * @arg @ref LL_GPDMA2_TRIGGER_RTC_ALRB_TRG
4507 * @arg @ref LL_GPDMA2_TRIGGER_RTC_WUT_TRG
4508 * @arg @ref LL_GPDMA2_TRIGGER_GPDMA1_CH0_TCF
4509 * @arg @ref LL_GPDMA2_TRIGGER_GPDMA1_CH1_TCF
4510 * @arg @ref LL_GPDMA2_TRIGGER_GPDMA1_CH2_TCF
4511 * @arg @ref LL_GPDMA2_TRIGGER_GPDMA1_CH3_TCF
4512 * @arg @ref LL_GPDMA2_TRIGGER_GPDMA1_CH4_TCF
4513 * @arg @ref LL_GPDMA2_TRIGGER_GPDMA1_CH5_TCF
4514 * @arg @ref LL_GPDMA2_TRIGGER_GPDMA1_CH6_TCF
4515 * @arg @ref LL_GPDMA2_TRIGGER_GPDMA1_CH7_TCF
4516 * @arg @ref LL_GPDMA2_TRIGGER_GPDMA2_CH0_TCF
4517 * @arg @ref LL_GPDMA2_TRIGGER_GPDMA2_CH1_TCF
4518 * @arg @ref LL_GPDMA2_TRIGGER_GPDMA2_CH2_TCF
4519 * @arg @ref LL_GPDMA2_TRIGGER_GPDMA2_CH3_TCF
4520 * @arg @ref LL_GPDMA2_TRIGGER_GPDMA2_CH4_TCF
4521 * @arg @ref LL_GPDMA2_TRIGGER_GPDMA2_CH5_TCF
4522 * @arg @ref LL_GPDMA2_TRIGGER_GPDMA2_CH6_TCF
4523 * @arg @ref LL_GPDMA2_TRIGGER_GPDMA2_CH7_TCF
4524 * @arg @ref LL_GPDMA2_TRIGGER_TIM2_TRGO
4525 * @arg @ref LL_GPDMA2_TRIGGER_TIM15_TRGO
4526 * @arg @ref LL_GPDMA2_TRIGGER_TIM12_TRGO
4527 * @arg @ref LL_GPDMA2_TRIGGER_LPTIM3_CH1
4528 * @arg @ref LL_GPDMA2_TRIGGER_LPTIM3_CH2
4529 * @arg @ref LL_GPDMA2_TRIGGER_LPTIM4_AIT
4530 * @arg @ref LL_GPDMA2_TRIGGER_LPTIM5_CH1
4531 * @arg @ref LL_GPDMA2_TRIGGER_LPTIM5_CH2
4532 * @arg @ref LL_GPDMA2_TRIGGER_LPTIM6_CH1
4533 * @arg @ref LL_GPDMA2_TRIGGER_LPTIM6_CH2
4534 * @arg @ref LL_GPDMA2_TRIGGER_TIM15_TRGO (*)
4535 * @arg @ref LL_GPDMA2_TRIGGER_TIM12_TRGO (*)
4536 * @arg @ref LL_GPDMA2_TRIGGER_LPTIM3_CH1 (*)
4537 * @arg @ref LL_GPDMA2_TRIGGER_LPTIM3_CH2 (*)
4538 * @arg @ref LL_GPDMA2_TRIGGER_LPTIM4_AIT (*)
4539 * @arg @ref LL_GPDMA2_TRIGGER_LPTIM5_CH1 (*)
4540 * @arg @ref LL_GPDMA2_TRIGGER_LPTIM5_CH2 (*)
4541 * @arg @ref LL_GPDMA2_TRIGGER_LPTIM6_CH1 (*)
4542 * @arg @ref LL_GPDMA2_TRIGGER_LPTIM6_CH2 (*)
4543 * @arg @ref LL_GPDMA2_TRIGGER_COMP1_OUT (*)
4544 * @arg @ref LL_GPDMA2_TRIGGER_EVENTOUT (*)
4545 *
4546 * @note (*) Availability depends on devices.
4547 */
LL_DMA_GetHWTrigger(DMA_TypeDef * DMAx,uint32_t Channel)4548 __STATIC_INLINE uint32_t LL_DMA_GetHWTrigger(DMA_TypeDef *DMAx, uint32_t Channel)
4549 {
4550 uint32_t dma_base_addr = (uint32_t)DMAx;
4551 return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR2,
4552 DMA_CTR2_TRIGSEL) >> DMA_CTR2_TRIGSEL_Pos);
4553 }
4554
4555 /**
4556 * @brief Configure addresses update.
4557 * @note This API is used only for 2D addressing channels.
4558 * @rmtoll CBR1 BRDDEC LL_DMA_ConfigBlkRptAddrUpdate\n
4559 * CBR1 BRSDEC LL_DMA_ConfigBlkRptAddrUpdate\n
4560 * CBR1 DDEC LL_DMA_ConfigBlkRptAddrUpdate\n
4561 * CBR1 SDEC LL_DMA_ConfigBlkRptAddrUpdate
4562 * @param DMAx DMAx Instance
4563 * @param Channel This parameter can be one of the following values:
4564 * @arg @ref LL_DMA_CHANNEL_12
4565 * @arg @ref LL_DMA_CHANNEL_13
4566 * @arg @ref LL_DMA_CHANNEL_14
4567 * @arg @ref LL_DMA_CHANNEL_15
4568 * @param Configuration This parameter must be a combination of all the following values:
4569 * @arg @ref LL_DMA_BLKRPT_DEST_ADDR_INCREMENT or @ref LL_DMA_BLKRPT_DEST_ADDR_DECREMENT
4570 * @arg @ref LL_DMA_BLKRPT_SRC_ADDR_INCREMENT or @ref LL_DMA_BLKRPT_SRC_ADDR_DECREMENT
4571 * @arg @ref LL_DMA_BURST_DEST_ADDR_INCREMENT or @ref LL_DMA_BURST_DEST_ADDR_DECREMENT
4572 * @arg @ref LL_DMA_BURST_SRC_ADDR_INCREMENT or @ref LL_DMA_BURST_SRC_ADDR_DECREMENT
4573 *@retval None.
4574 */
LL_DMA_ConfigBlkRptAddrUpdate(DMA_TypeDef * DMAx,uint32_t Channel,uint32_t Configuration)4575 __STATIC_INLINE void LL_DMA_ConfigBlkRptAddrUpdate(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Configuration)
4576 {
4577 uint32_t dma_base_addr = (uint32_t)DMAx;
4578 MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CBR1,
4579 DMA_CBR1_BRDDEC | DMA_CBR1_BRSDEC | DMA_CBR1_DDEC | DMA_CBR1_SDEC, Configuration);
4580 }
4581
4582 /**
4583 * @brief Configure DMA Block number of data and repeat Count.
4584 * @note This API is used only for 2D addressing channels.
4585 * @rmtoll CBR1 BNDT LL_DMA_ConfigBlkCounters\n
4586 * CBR1 BRC LL_DMA_ConfigBlkCounters
4587 * @param DMAx DMAx Instance
4588 * @param Channel This parameter can be one of the following values:
4589 * @arg @ref LL_DMA_CHANNEL_12
4590 * @arg @ref LL_DMA_CHANNEL_13
4591 * @arg @ref LL_DMA_CHANNEL_14
4592 * @arg @ref LL_DMA_CHANNEL_15
4593 * @param BlkDataLength Between 0 to 0x0000FFFF
4594 * @param BlkRptCount Between 0 to 0x00000EFF
4595 *@retval None.
4596 */
LL_DMA_ConfigBlkCounters(DMA_TypeDef * DMAx,uint32_t Channel,uint32_t BlkDataLength,uint32_t BlkRptCount)4597 __STATIC_INLINE void LL_DMA_ConfigBlkCounters(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t BlkDataLength,
4598 uint32_t BlkRptCount)
4599 {
4600 uint32_t dma_base_addr = (uint32_t)DMAx;
4601 MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CBR1,
4602 (DMA_CBR1_BNDT | DMA_CBR1_BRC), (BlkDataLength | (BlkRptCount << DMA_CBR1_BRC_Pos)));
4603 }
4604
4605 /**
4606 * @brief Set block repeat destination address update.
4607 * @note This API is used only for 2D addressing channels.
4608 * @rmtoll CBR1 BRDDEC LL_DMA_SetBlkRptDestAddrUpdate
4609 * @param DMAx DMAx Instance
4610 * @param Channel This parameter can be one of the following values:
4611 * @arg @ref LL_DMA_CHANNEL_12
4612 * @arg @ref LL_DMA_CHANNEL_13
4613 * @arg @ref LL_DMA_CHANNEL_14
4614 * @arg @ref LL_DMA_CHANNEL_15
4615 * @param BlkRptDestAddrUpdate This parameter can be one of the following values:
4616 * @arg @ref LL_DMA_BLKRPT_DEST_ADDR_INCREMENT
4617 * @arg @ref LL_DMA_BLKRPT_DEST_ADDR_DECREMENT
4618 * @retval None.
4619 */
LL_DMA_SetBlkRptDestAddrUpdate(DMA_TypeDef * DMAx,uint32_t Channel,uint32_t BlkRptDestAddrUpdate)4620 __STATIC_INLINE void LL_DMA_SetBlkRptDestAddrUpdate(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t BlkRptDestAddrUpdate)
4621 {
4622 uint32_t dma_base_addr = (uint32_t)DMAx;
4623 MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CBR1, DMA_CBR1_BRDDEC,
4624 BlkRptDestAddrUpdate);
4625 }
4626
4627 /**
4628 * @brief Get block repeat destination address update.
4629 * @note This API is used only for 2D addressing channels.
4630 * @rmtoll CBR1 BRDDEC LL_DMA_GetBlkRptDestAddrUpdate
4631 * @param DMAx DMAx Instance
4632 * @param Channel This parameter can be one of the following values:
4633 * @arg @ref LL_DMA_CHANNEL_12
4634 * @arg @ref LL_DMA_CHANNEL_13
4635 * @arg @ref LL_DMA_CHANNEL_14
4636 * @arg @ref LL_DMA_CHANNEL_15
4637 * @retval Returned value can be one of the following values:
4638 * @arg @ref LL_DMA_BLKRPT_DEST_ADDR_INCREMENT
4639 * @arg @ref LL_DMA_BLKRPT_DEST_ADDR_DECREMENT
4640 */
LL_DMA_GetBlkRptDestAddrUpdate(DMA_TypeDef * DMAx,uint32_t Channel)4641 __STATIC_INLINE uint32_t LL_DMA_GetBlkRptDestAddrUpdate(DMA_TypeDef *DMAx, uint32_t Channel)
4642 {
4643 uint32_t dma_base_addr = (uint32_t)DMAx;
4644 return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CBR1, DMA_CBR1_BRDDEC));
4645 }
4646
4647 /**
4648 * @brief Set block repeat source address update.
4649 * @note This API is used only for 2D addressing channels.
4650 * @rmtoll CBR1 BRSDEC LL_DMA_SetBlkRptSrcAddrUpdate
4651 * @param DMAx DMAx Instance
4652 * @param Channel This parameter can be one of the following values:
4653 * @arg @ref LL_DMA_CHANNEL_12
4654 * @arg @ref LL_DMA_CHANNEL_13
4655 * @arg @ref LL_DMA_CHANNEL_14
4656 * @arg @ref LL_DMA_CHANNEL_15
4657 * @param BlkRptSrcAddrUpdate This parameter can be one of the following values:
4658 * @arg @ref LL_DMA_BLKRPT_SRC_ADDR_INCREMENT
4659 * @arg @ref LL_DMA_BLKRPT_SRC_ADDR_DECREMENT
4660 * @retval None.
4661 */
LL_DMA_SetBlkRptSrcAddrUpdate(DMA_TypeDef * DMAx,uint32_t Channel,uint32_t BlkRptSrcAddrUpdate)4662 __STATIC_INLINE void LL_DMA_SetBlkRptSrcAddrUpdate(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t BlkRptSrcAddrUpdate)
4663 {
4664 uint32_t dma_base_addr = (uint32_t)DMAx;
4665 MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CBR1, DMA_CBR1_BRSDEC,
4666 BlkRptSrcAddrUpdate);
4667 }
4668
4669 /**
4670 * @brief Get block repeat source address update.
4671 * @note This API is used only for 2D addressing channels.
4672 * @rmtoll CBR1 BRSDEC LL_DMA_GetBlkRptSrcAddrUpdate
4673 * @param DMAx DMAx Instance
4674 * @param Channel This parameter can be one of the following values:
4675 * @arg @ref LL_DMA_CHANNEL_12
4676 * @arg @ref LL_DMA_CHANNEL_13
4677 * @arg @ref LL_DMA_CHANNEL_14
4678 * @arg @ref LL_DMA_CHANNEL_15
4679 * @retval Returned value can be one of the following values:
4680 * @arg @ref LL_DMA_BLKRPT_SRC_ADDR_INCREMENT
4681 * @arg @ref LL_DMA_BLKRPT_SRC_ADDR_DECREMENT
4682 */
LL_DMA_GetBlkRptSrcAddrUpdate(DMA_TypeDef * DMAx,uint32_t Channel)4683 __STATIC_INLINE uint32_t LL_DMA_GetBlkRptSrcAddrUpdate(DMA_TypeDef *DMAx, uint32_t Channel)
4684 {
4685 uint32_t dma_base_addr = (uint32_t)DMAx;
4686 return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CBR1, DMA_CBR1_BRSDEC));
4687 }
4688
4689 /**
4690 * @brief Set destination address update.
4691 * @note This API is used only for 2D addressing channels.
4692 * @rmtoll CBR1 DDEC LL_DMA_SetDestAddrUpdate
4693 * @param DMAx DMAx Instance
4694 * @param Channel This parameter can be one of the following values:
4695 * @arg @ref LL_DMA_CHANNEL_12
4696 * @arg @ref LL_DMA_CHANNEL_13
4697 * @arg @ref LL_DMA_CHANNEL_14
4698 * @arg @ref LL_DMA_CHANNEL_15
4699 * @param DestAddrUpdate This parameter can be one of the following values:
4700 * @arg @ref LL_DMA_BURST_DEST_ADDR_INCREMENT
4701 * @arg @ref LL_DMA_BURST_DEST_ADDR_DECREMENT
4702 * @retval None.
4703 */
LL_DMA_SetDestAddrUpdate(DMA_TypeDef * DMAx,uint32_t Channel,uint32_t DestAddrUpdate)4704 __STATIC_INLINE void LL_DMA_SetDestAddrUpdate(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t DestAddrUpdate)
4705 {
4706 uint32_t dma_base_addr = (uint32_t)DMAx;
4707 MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CBR1, DMA_CBR1_DDEC,
4708 DestAddrUpdate);
4709 }
4710
4711 /**
4712 * @brief Get destination address update.
4713 * @note This API is used only for 2D addressing channels.
4714 * @rmtoll CBR1 DDEC LL_DMA_GetDestAddrUpdate
4715 * @param DMAx DMAx Instance
4716 * @param Channel This parameter can be one of the following values:
4717 * @arg @ref LL_DMA_CHANNEL_12
4718 * @arg @ref LL_DMA_CHANNEL_13
4719 * @arg @ref LL_DMA_CHANNEL_14
4720 * @arg @ref LL_DMA_CHANNEL_15
4721 * @retval Returned value can be one of the following values:
4722 * @arg @ref LL_DMA_BURST_DEST_ADDR_INCREMENT
4723 * @arg @ref LL_DMA_BURST_DEST_ADDR_DECREMENT
4724 */
LL_DMA_GetDestAddrUpdate(DMA_TypeDef * DMAx,uint32_t Channel)4725 __STATIC_INLINE uint32_t LL_DMA_GetDestAddrUpdate(DMA_TypeDef *DMAx, uint32_t Channel)
4726 {
4727 uint32_t dma_base_addr = (uint32_t)DMAx;
4728 return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CBR1, DMA_CBR1_DDEC));
4729 }
4730
4731 /**
4732 * @brief Set source address update.
4733 * @note This API is used only for 2D addressing channels.
4734 * @rmtoll CBR1 SDEC LL_DMA_SetSrcAddrUpdate
4735 * @param DMAx DMAx Instance
4736 * @param Channel This parameter can be one of the following values:
4737 * @arg @ref LL_DMA_CHANNEL_12
4738 * @arg @ref LL_DMA_CHANNEL_13
4739 * @arg @ref LL_DMA_CHANNEL_14
4740 * @arg @ref LL_DMA_CHANNEL_15
4741 * @param SrcAddrUpdate This parameter can be one of the following values:
4742 * @arg @ref LL_DMA_BURST_SRC_ADDR_INCREMENT
4743 * @arg @ref LL_DMA_BURST_SRC_ADDR_DECREMENT
4744 * @retval None.
4745 */
LL_DMA_SetSrcAddrUpdate(DMA_TypeDef * DMAx,uint32_t Channel,uint32_t SrcAddrUpdate)4746 __STATIC_INLINE void LL_DMA_SetSrcAddrUpdate(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t SrcAddrUpdate)
4747 {
4748 uint32_t dma_base_addr = (uint32_t)DMAx;
4749 MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CBR1, DMA_CBR1_SDEC,
4750 SrcAddrUpdate);
4751 }
4752
4753 /**
4754 * @brief Get source address update.
4755 * @note This API is used only for 2D addressing channels.
4756 * @rmtoll CBR1 SDEC LL_DMA_GetSrcAddrUpdate
4757 * @param DMAx DMAx Instance
4758 * @param Channel This parameter can be one of the following values:
4759 * @arg @ref LL_DMA_CHANNEL_12
4760 * @arg @ref LL_DMA_CHANNEL_13
4761 * @arg @ref LL_DMA_CHANNEL_14
4762 * @arg @ref LL_DMA_CHANNEL_15
4763 * @retval Returned value can be one of the following values:
4764 * @arg @ref LL_DMA_BURST_SRC_ADDR_INCREMENT
4765 * @arg @ref LL_DMA_BURST_SRC_ADDR_DECREMENT
4766 */
LL_DMA_GetSrcAddrUpdate(DMA_TypeDef * DMAx,uint32_t Channel)4767 __STATIC_INLINE uint32_t LL_DMA_GetSrcAddrUpdate(DMA_TypeDef *DMAx, uint32_t Channel)
4768 {
4769 uint32_t dma_base_addr = (uint32_t)DMAx;
4770 return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CBR1, DMA_CBR1_SDEC));
4771 }
4772
4773 /**
4774 * @brief Set block repeat count.
4775 * @note This API is used only for 2D addressing channels.
4776 * @rmtoll CBR1 BRC LL_DMA_SetBlkRptCount
4777 * @param DMAx DMAx Instance
4778 * @param Channel This parameter can be one of the following values:
4779 * @arg @ref LL_DMA_CHANNEL_12
4780 * @arg @ref LL_DMA_CHANNEL_13
4781 * @arg @ref LL_DMA_CHANNEL_14
4782 * @arg @ref LL_DMA_CHANNEL_15
4783 * @param BlkRptCount Between 0 to 0x00000EFF
4784 * @retval None.
4785 */
LL_DMA_SetBlkRptCount(DMA_TypeDef * DMAx,uint32_t Channel,uint32_t BlkRptCount)4786 __STATIC_INLINE void LL_DMA_SetBlkRptCount(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t BlkRptCount)
4787 {
4788 uint32_t dma_base_addr = (uint32_t)DMAx;
4789 MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CBR1, DMA_CBR1_BRC,
4790 (BlkRptCount << DMA_CBR1_BRC_Pos) & DMA_CBR1_BRC);
4791 }
4792
4793 /**
4794 * @brief Get block repeat count.
4795 * @note This API is used only for 2D addressing channels.
4796 * @rmtoll CBR1 BRC LL_DMA_GetBlkRptCount
4797 * @param DMAx DMAx Instance
4798 * @param Channel This parameter can be one of the following values:
4799 * @arg @ref LL_DMA_CHANNEL_12
4800 * @arg @ref LL_DMA_CHANNEL_13
4801 * @arg @ref LL_DMA_CHANNEL_14
4802 * @arg @ref LL_DMA_CHANNEL_15
4803 * @retval Between 0 to 0x00000EFF
4804 */
LL_DMA_GetBlkRptCount(DMA_TypeDef * DMAx,uint32_t Channel)4805 __STATIC_INLINE uint32_t LL_DMA_GetBlkRptCount(DMA_TypeDef *DMAx, uint32_t Channel)
4806 {
4807 uint32_t dma_base_addr = (uint32_t)DMAx;
4808 return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CBR1,
4809 DMA_CBR1_BRC) >> DMA_CBR1_BRC_Pos);
4810 }
4811
4812 /**
4813 * @brief Set block data length in bytes to transfer.
4814 * @note This API is used for all available DMA channels.
4815 * @rmtoll CBR1 BNDT LL_DMA_SetBlkDataLength
4816 * @param DMAx DMAx Instance
4817 * @param Channel This parameter can be one of the following values:
4818 * @arg @ref LL_DMA_CHANNEL_0
4819 * @arg @ref LL_DMA_CHANNEL_1
4820 * @arg @ref LL_DMA_CHANNEL_2
4821 * @arg @ref LL_DMA_CHANNEL_3
4822 * @arg @ref LL_DMA_CHANNEL_4
4823 * @arg @ref LL_DMA_CHANNEL_5
4824 * @arg @ref LL_DMA_CHANNEL_6
4825 * @arg @ref LL_DMA_CHANNEL_7
4826 * @arg @ref LL_DMA_CHANNEL_8
4827 * @arg @ref LL_DMA_CHANNEL_9
4828 * @arg @ref LL_DMA_CHANNEL_10
4829 * @arg @ref LL_DMA_CHANNEL_11
4830 * @arg @ref LL_DMA_CHANNEL_12
4831 * @arg @ref LL_DMA_CHANNEL_13
4832 * @arg @ref LL_DMA_CHANNEL_14
4833 * @arg @ref LL_DMA_CHANNEL_15
4834 * @param BlkDataLength Between 0 to 0x0000FFFF
4835 * @retval None.
4836 */
LL_DMA_SetBlkDataLength(DMA_TypeDef * DMAx,uint32_t Channel,uint32_t BlkDataLength)4837 __STATIC_INLINE void LL_DMA_SetBlkDataLength(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t BlkDataLength)
4838 {
4839 uint32_t dma_base_addr = (uint32_t)DMAx;
4840 MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CBR1, DMA_CBR1_BNDT,
4841 BlkDataLength);
4842 }
4843
4844 /**
4845 * @brief Get block data length in bytes to transfer.
4846 * @note This API is used for all available DMA channels.
4847 * @rmtoll CBR1 BNDT LL_DMA_GetBlkDataLength
4848 * @param DMAx DMAx Instance
4849 * @param Channel This parameter can be one of the following values:
4850 * @arg @ref LL_DMA_CHANNEL_0
4851 * @arg @ref LL_DMA_CHANNEL_1
4852 * @arg @ref LL_DMA_CHANNEL_2
4853 * @arg @ref LL_DMA_CHANNEL_3
4854 * @arg @ref LL_DMA_CHANNEL_4
4855 * @arg @ref LL_DMA_CHANNEL_5
4856 * @arg @ref LL_DMA_CHANNEL_6
4857 * @arg @ref LL_DMA_CHANNEL_7
4858 * @arg @ref LL_DMA_CHANNEL_8
4859 * @arg @ref LL_DMA_CHANNEL_9
4860 * @arg @ref LL_DMA_CHANNEL_10
4861 * @arg @ref LL_DMA_CHANNEL_11
4862 * @arg @ref LL_DMA_CHANNEL_12
4863 * @arg @ref LL_DMA_CHANNEL_13
4864 * @arg @ref LL_DMA_CHANNEL_14
4865 * @arg @ref LL_DMA_CHANNEL_15
4866 * @retval Between 0 to 0x0000FFFF
4867 */
LL_DMA_GetBlkDataLength(DMA_TypeDef * DMAx,uint32_t Channel)4868 __STATIC_INLINE uint32_t LL_DMA_GetBlkDataLength(DMA_TypeDef *DMAx, uint32_t Channel)
4869 {
4870 uint32_t dma_base_addr = (uint32_t)DMAx;
4871 return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CBR1, DMA_CBR1_BNDT));
4872 }
4873
4874 /**
4875 * @brief Configure the source and destination addresses.
4876 * @note This API is used for all available DMA channels.
4877 * @note This API must not be called when the DMA Channel is enabled.
4878 * @rmtoll CSAR SA LL_DMA_ConfigAddresses\n
4879 * CDAR DA LL_DMA_ConfigAddresses
4880 * @param DMAx DMAx Instance
4881 * @param Channel This parameter can be one of the following values:
4882 * @arg @ref LL_DMA_CHANNEL_0
4883 * @arg @ref LL_DMA_CHANNEL_1
4884 * @arg @ref LL_DMA_CHANNEL_2
4885 * @arg @ref LL_DMA_CHANNEL_3
4886 * @arg @ref LL_DMA_CHANNEL_4
4887 * @arg @ref LL_DMA_CHANNEL_5
4888 * @arg @ref LL_DMA_CHANNEL_6
4889 * @arg @ref LL_DMA_CHANNEL_7
4890 * @arg @ref LL_DMA_CHANNEL_8
4891 * @arg @ref LL_DMA_CHANNEL_9
4892 * @arg @ref LL_DMA_CHANNEL_10
4893 * @arg @ref LL_DMA_CHANNEL_11
4894 * @arg @ref LL_DMA_CHANNEL_12
4895 * @arg @ref LL_DMA_CHANNEL_13
4896 * @arg @ref LL_DMA_CHANNEL_14
4897 * @arg @ref LL_DMA_CHANNEL_15
4898 * @param SrcAddress Between 0 to 0xFFFFFFFF
4899 * @param DestAddress Between 0 to 0xFFFFFFFF
4900 * @retval None.
4901 */
LL_DMA_ConfigAddresses(DMA_TypeDef * DMAx,uint32_t Channel,uint32_t SrcAddress,uint32_t DestAddress)4902 __STATIC_INLINE void LL_DMA_ConfigAddresses(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t SrcAddress, uint32_t
4903 DestAddress)
4904 {
4905 uint32_t dma_base_addr = (uint32_t)DMAx;
4906 WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CSAR, SrcAddress);
4907 WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CDAR, DestAddress);
4908 }
4909
4910 /**
4911 * @brief Set source address.
4912 * @note This API is used for all available DMA channels.
4913 * @rmtoll CSAR SA LL_DMA_SetSrcAddress
4914 * @param DMAx DMAx Instance
4915 * @param Channel This parameter can be one of the following values:
4916 * @arg @ref LL_DMA_CHANNEL_0
4917 * @arg @ref LL_DMA_CHANNEL_1
4918 * @arg @ref LL_DMA_CHANNEL_2
4919 * @arg @ref LL_DMA_CHANNEL_3
4920 * @arg @ref LL_DMA_CHANNEL_4
4921 * @arg @ref LL_DMA_CHANNEL_5
4922 * @arg @ref LL_DMA_CHANNEL_6
4923 * @arg @ref LL_DMA_CHANNEL_7
4924 * @arg @ref LL_DMA_CHANNEL_8
4925 * @arg @ref LL_DMA_CHANNEL_9
4926 * @arg @ref LL_DMA_CHANNEL_10
4927 * @arg @ref LL_DMA_CHANNEL_11
4928 * @arg @ref LL_DMA_CHANNEL_12
4929 * @arg @ref LL_DMA_CHANNEL_13
4930 * @arg @ref LL_DMA_CHANNEL_14
4931 * @arg @ref LL_DMA_CHANNEL_15
4932 * @param SrcAddress Between 0 to 0xFFFFFFFF
4933 * @retval None.
4934 */
LL_DMA_SetSrcAddress(DMA_TypeDef * DMAx,uint32_t Channel,uint32_t SrcAddress)4935 __STATIC_INLINE void LL_DMA_SetSrcAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t SrcAddress)
4936 {
4937 uint32_t dma_base_addr = (uint32_t)DMAx;
4938 WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CSAR, SrcAddress);
4939 }
4940
4941 /**
4942 * @brief Get source address.
4943 * @note This API is used for all available DMA channels.
4944 * @rmtoll CSAR SA LL_DMA_GetSrcAddress
4945 * @param DMAx DMAx Instance
4946 * @param Channel This parameter can be one of the following values:
4947 * @arg @ref LL_DMA_CHANNEL_0
4948 * @arg @ref LL_DMA_CHANNEL_1
4949 * @arg @ref LL_DMA_CHANNEL_2
4950 * @arg @ref LL_DMA_CHANNEL_3
4951 * @arg @ref LL_DMA_CHANNEL_4
4952 * @arg @ref LL_DMA_CHANNEL_5
4953 * @arg @ref LL_DMA_CHANNEL_6
4954 * @arg @ref LL_DMA_CHANNEL_7
4955 * @arg @ref LL_DMA_CHANNEL_8
4956 * @arg @ref LL_DMA_CHANNEL_9
4957 * @arg @ref LL_DMA_CHANNEL_10
4958 * @arg @ref LL_DMA_CHANNEL_11
4959 * @arg @ref LL_DMA_CHANNEL_12
4960 * @arg @ref LL_DMA_CHANNEL_13
4961 * @arg @ref LL_DMA_CHANNEL_14
4962 * @arg @ref LL_DMA_CHANNEL_15
4963 * @retval Between 0 to 0xFFFFFFFF
4964 */
LL_DMA_GetSrcAddress(DMA_TypeDef * DMAx,uint32_t Channel)4965 __STATIC_INLINE uint32_t LL_DMA_GetSrcAddress(DMA_TypeDef *DMAx, uint32_t Channel)
4966 {
4967 uint32_t dma_base_addr = (uint32_t)DMAx;
4968 return (READ_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CSAR));
4969 }
4970
4971 /**
4972 * @brief Set destination address.
4973 * @note This API is used for all available DMA channels.
4974 * @rmtoll CDAR DA LL_DMA_SetDestAddress
4975 * @param DMAx DMAx Instance
4976 * @param Channel This parameter can be one of the following values:
4977 * @arg @ref LL_DMA_CHANNEL_0
4978 * @arg @ref LL_DMA_CHANNEL_1
4979 * @arg @ref LL_DMA_CHANNEL_2
4980 * @arg @ref LL_DMA_CHANNEL_3
4981 * @arg @ref LL_DMA_CHANNEL_4
4982 * @arg @ref LL_DMA_CHANNEL_5
4983 * @arg @ref LL_DMA_CHANNEL_6
4984 * @arg @ref LL_DMA_CHANNEL_7
4985 * @arg @ref LL_DMA_CHANNEL_8
4986 * @arg @ref LL_DMA_CHANNEL_9
4987 * @arg @ref LL_DMA_CHANNEL_10
4988 * @arg @ref LL_DMA_CHANNEL_11
4989 * @arg @ref LL_DMA_CHANNEL_12
4990 * @arg @ref LL_DMA_CHANNEL_13
4991 * @arg @ref LL_DMA_CHANNEL_14
4992 * @arg @ref LL_DMA_CHANNEL_15
4993 * @param DestAddress Between 0 to 0xFFFFFFFF
4994 * @retval None.
4995 */
LL_DMA_SetDestAddress(DMA_TypeDef * DMAx,uint32_t Channel,uint32_t DestAddress)4996 __STATIC_INLINE void LL_DMA_SetDestAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t DestAddress)
4997 {
4998 uint32_t dma_base_addr = (uint32_t)DMAx;
4999 WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CDAR, DestAddress);
5000 }
5001
5002 /**
5003 * @brief Get destination address.
5004 * @note This API is used for all available DMA channels.
5005 * @rmtoll CDAR DA LL_DMA_GetDestAddress
5006 * @param DMAx DMAx Instance
5007 * @param Channel This parameter can be one of the following values:
5008 * @arg @ref LL_DMA_CHANNEL_0
5009 * @arg @ref LL_DMA_CHANNEL_1
5010 * @arg @ref LL_DMA_CHANNEL_2
5011 * @arg @ref LL_DMA_CHANNEL_3
5012 * @arg @ref LL_DMA_CHANNEL_4
5013 * @arg @ref LL_DMA_CHANNEL_5
5014 * @arg @ref LL_DMA_CHANNEL_6
5015 * @arg @ref LL_DMA_CHANNEL_7
5016 * @arg @ref LL_DMA_CHANNEL_8
5017 * @arg @ref LL_DMA_CHANNEL_9
5018 * @arg @ref LL_DMA_CHANNEL_10
5019 * @arg @ref LL_DMA_CHANNEL_11
5020 * @arg @ref LL_DMA_CHANNEL_12
5021 * @arg @ref LL_DMA_CHANNEL_13
5022 * @arg @ref LL_DMA_CHANNEL_14
5023 * @arg @ref LL_DMA_CHANNEL_15
5024 * @retval Between 0 to 0xFFFFFFFF
5025 */
LL_DMA_GetDestAddress(DMA_TypeDef * DMAx,uint32_t Channel)5026 __STATIC_INLINE uint32_t LL_DMA_GetDestAddress(DMA_TypeDef *DMAx, uint32_t Channel)
5027 {
5028 uint32_t dma_base_addr = (uint32_t)DMAx;
5029 return (READ_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CDAR));
5030 }
5031
5032 /**
5033 * @brief Configure source and destination addresses offset.
5034 * @note This API is used only for 2D addressing channels.
5035 * @note This API must not be called when the DMA Channel is enabled.
5036 * @rmtoll CTR3 DAO LL_DMA_ConfigAddrUpdateValue\n
5037 * CTR3 SAO LL_DMA_ConfigAddrUpdateValue
5038 * @param DMAx DMAx Instance
5039 * @param Channel This parameter can be one of the following values:
5040 * @arg @ref LL_DMA_CHANNEL_12
5041 * @arg @ref LL_DMA_CHANNEL_13
5042 * @arg @ref LL_DMA_CHANNEL_14
5043 * @arg @ref LL_DMA_CHANNEL_15
5044 * @param DestAddrOffset Between 0 to 0x00001FFF
5045 * @param SrcAddrOffset Between 0 to 0x00001FFF
5046 * @retval None.
5047 */
LL_DMA_ConfigAddrUpdateValue(DMA_TypeDef * DMAx,uint32_t Channel,uint32_t SrcAddrOffset,uint32_t DestAddrOffset)5048 __STATIC_INLINE void LL_DMA_ConfigAddrUpdateValue(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t SrcAddrOffset,
5049 uint32_t DestAddrOffset)
5050 {
5051 uint32_t dma_base_addr = (uint32_t)DMAx;
5052 WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR3,
5053 (SrcAddrOffset & DMA_CTR3_SAO) | ((DestAddrOffset << DMA_CTR3_DAO_Pos) & DMA_CTR3_DAO));
5054 }
5055
5056 /**
5057 * @brief Set destination address offset.
5058 * @note This API is used only for 2D addressing channels.
5059 * @rmtoll CTR3 DAO LL_DMA_SetDestAddrUpdateValue
5060 * @param DMAx DMAx Instance
5061 * @param Channel This parameter can be one of the following values:
5062 * @arg @ref LL_DMA_CHANNEL_12
5063 * @arg @ref LL_DMA_CHANNEL_13
5064 * @arg @ref LL_DMA_CHANNEL_14
5065 * @arg @ref LL_DMA_CHANNEL_15
5066 * @param DestAddrOffset Between 0 to 0x00001FFF
5067 * @retval None.
5068 */
LL_DMA_SetDestAddrUpdateValue(DMA_TypeDef * DMAx,uint32_t Channel,uint32_t DestAddrOffset)5069 __STATIC_INLINE void LL_DMA_SetDestAddrUpdateValue(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t DestAddrOffset)
5070 {
5071 uint32_t dma_base_addr = (uint32_t)DMAx;
5072 MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR3, DMA_CTR3_DAO,
5073 ((DestAddrOffset << DMA_CTR3_DAO_Pos) & DMA_CTR3_DAO));
5074 }
5075
5076 /**
5077 * @brief Get destination address offset.
5078 * @note This API is used only for 2D addressing channels.
5079 * @rmtoll CDAR DAO LL_DMA_GetDestAddrUpdateValue
5080 * @param DMAx DMAx Instance
5081 * @param Channel This parameter can be one of the following values:
5082 * @arg @ref LL_DMA_CHANNEL_12
5083 * @arg @ref LL_DMA_CHANNEL_13
5084 * @arg @ref LL_DMA_CHANNEL_14
5085 * @arg @ref LL_DMA_CHANNEL_15
5086 * @retval Between 0 to 0x00001FFF
5087 */
LL_DMA_GetDestAddrUpdateValue(DMA_TypeDef * DMAx,uint32_t Channel)5088 __STATIC_INLINE uint32_t LL_DMA_GetDestAddrUpdateValue(DMA_TypeDef *DMAx, uint32_t Channel)
5089 {
5090 uint32_t dma_base_addr = (uint32_t)DMAx;
5091 return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR3,
5092 DMA_CTR3_DAO) >> DMA_CTR3_DAO_Pos);
5093 }
5094
5095 /**
5096 * @brief Set source address offset.
5097 * @note This API is used only for 2D addressing channels.
5098 * @rmtoll CTR3 SAO LL_DMA_SetSrcAddrUpdateValue
5099 * @param DMAx DMAx Instance
5100 * @param Channel This parameter can be one of the following values:
5101 * @arg @ref LL_DMA_CHANNEL_12
5102 * @arg @ref LL_DMA_CHANNEL_13
5103 * @arg @ref LL_DMA_CHANNEL_14
5104 * @arg @ref LL_DMA_CHANNEL_15
5105 * @param SrcAddrOffset Between 0 to 0x00001FFF
5106 * @retval None.
5107 */
LL_DMA_SetSrcAddrUpdateValue(DMA_TypeDef * DMAx,uint32_t Channel,uint32_t SrcAddrOffset)5108 __STATIC_INLINE void LL_DMA_SetSrcAddrUpdateValue(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t SrcAddrOffset)
5109 {
5110 uint32_t dma_base_addr = (uint32_t)DMAx;
5111 MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR3, DMA_CTR3_SAO,
5112 SrcAddrOffset & DMA_CTR3_SAO);
5113 }
5114
5115 /**
5116 * @brief Get source address offset.
5117 * @note This API is used only for 2D addressing channels.
5118 * @rmtoll CTR3 SAO LL_DMA_GetSrcAddrUpdateValue
5119 * @param DMAx DMAx Instance
5120 * @param Channel This parameter can be one of the following values:
5121 * @arg @ref LL_DMA_CHANNEL_12
5122 * @arg @ref LL_DMA_CHANNEL_13
5123 * @arg @ref LL_DMA_CHANNEL_14
5124 * @arg @ref LL_DMA_CHANNEL_15
5125 * @retval Between 0 to 0x00001FFF
5126 */
LL_DMA_GetSrcAddrUpdateValue(DMA_TypeDef * DMAx,uint32_t Channel)5127 __STATIC_INLINE uint32_t LL_DMA_GetSrcAddrUpdateValue(DMA_TypeDef *DMAx, uint32_t Channel)
5128 {
5129 uint32_t dma_base_addr = (uint32_t)DMAx;
5130 return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR3, DMA_CTR3_SAO));
5131 }
5132
5133 /**
5134 * @brief Configure the block repeated source and destination addresses offset.
5135 * @note This API is used only for 2D addressing channels.
5136 * @note This API must not be called when the DMA Channel is enabled.
5137 * @rmtoll CBR2 BRDAO LL_DMA_ConfigBlkRptAddrUpdateValue\n
5138 * CBR2 BRSAO LL_DMA_ConfigBlkRptAddrUpdateValue
5139 * @param DMAx DMAx Instance
5140 * @param Channel This parameter can be one of the following values:
5141 * @arg @ref LL_DMA_CHANNEL_12
5142 * @arg @ref LL_DMA_CHANNEL_13
5143 * @arg @ref LL_DMA_CHANNEL_14
5144 * @arg @ref LL_DMA_CHANNEL_15
5145 * @param BlkRptDestAddrOffset Between 0 to 0x0000FFFF
5146 * @param BlkRptSrcAddrOffset Between 0 to 0x0000FFFF
5147 * @retval None.
5148 */
LL_DMA_ConfigBlkRptAddrUpdateValue(DMA_TypeDef * DMAx,uint32_t Channel,uint32_t BlkRptSrcAddrOffset,uint32_t BlkRptDestAddrOffset)5149 __STATIC_INLINE void LL_DMA_ConfigBlkRptAddrUpdateValue(DMA_TypeDef *DMAx, uint32_t Channel,
5150 uint32_t BlkRptSrcAddrOffset, uint32_t BlkRptDestAddrOffset)
5151 {
5152 uint32_t dma_base_addr = (uint32_t)DMAx;
5153 WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CBR2,
5154 ((BlkRptDestAddrOffset << DMA_CBR2_BRDAO_Pos) & DMA_CBR2_BRDAO) | (BlkRptSrcAddrOffset & DMA_CBR2_BRSAO));
5155 }
5156
5157 /**
5158 * @brief Set block repeated destination address offset.
5159 * @note This API is used only for 2D addressing channels.
5160 * @rmtoll CBR2 BRDAO LL_DMA_SetBlkRptDestAddrUpdateValue
5161 * @param DMAx DMAx Instance
5162 * @param Channel This parameter can be one of the following values:
5163 * @arg @ref LL_DMA_CHANNEL_12
5164 * @arg @ref LL_DMA_CHANNEL_13
5165 * @arg @ref LL_DMA_CHANNEL_14
5166 * @arg @ref LL_DMA_CHANNEL_15
5167 * @param BlkRptDestAddrOffset Between 0 to 0x0000FFFF
5168 * @retval None.
5169 */
LL_DMA_SetBlkRptDestAddrUpdateValue(DMA_TypeDef * DMAx,uint32_t Channel,uint32_t BlkRptDestAddrOffset)5170 __STATIC_INLINE void LL_DMA_SetBlkRptDestAddrUpdateValue(DMA_TypeDef *DMAx, uint32_t Channel,
5171 uint32_t BlkRptDestAddrOffset)
5172 {
5173 uint32_t dma_base_addr = (uint32_t)DMAx;
5174 MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CBR2, DMA_CBR2_BRDAO,
5175 ((BlkRptDestAddrOffset << DMA_CBR2_BRDAO_Pos) & DMA_CBR2_BRDAO));
5176 }
5177
5178 /**
5179 * @brief Get block repeated destination address offset.
5180 * @note This API is used only for 2D addressing channels.
5181 * @rmtoll CBR2 BRDAO LL_DMA_GetBlkRptDestAddrUpdateValue
5182 * @param DMAx DMAx Instance
5183 * @param Channel This parameter can be one of the following values:
5184 * @arg @ref LL_DMA_CHANNEL_12
5185 * @arg @ref LL_DMA_CHANNEL_13
5186 * @arg @ref LL_DMA_CHANNEL_14
5187 * @arg @ref LL_DMA_CHANNEL_15
5188 * @retval Between 0 to 0x0000FFFF.
5189 */
LL_DMA_GetBlkRptDestAddrUpdateValue(DMA_TypeDef * DMAx,uint32_t Channel)5190 __STATIC_INLINE uint32_t LL_DMA_GetBlkRptDestAddrUpdateValue(DMA_TypeDef *DMAx, uint32_t Channel)
5191 {
5192 uint32_t dma_base_addr = (uint32_t)DMAx;
5193 return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CBR2,
5194 DMA_CBR2_BRDAO) >> DMA_CBR2_BRDAO_Pos);
5195 }
5196
5197 /**
5198 * @brief Set block repeated source address offset.
5199 * @note This API is used only for 2D addressing channels.
5200 * @rmtoll CBR2 BRSAO LL_DMA_SetBlkRptSrcAddrUpdateValue
5201 * @param DMAx DMAx Instance
5202 * @param Channel This parameter can be one of the following values:
5203 * @arg @ref LL_DMA_CHANNEL_12
5204 * @arg @ref LL_DMA_CHANNEL_13
5205 * @arg @ref LL_DMA_CHANNEL_14
5206 * @arg @ref LL_DMA_CHANNEL_15
5207 * @param BlkRptSrcAddrOffset Between 0 to 0x0000FFFF
5208 * @retval None.
5209 */
LL_DMA_SetBlkRptSrcAddrUpdateValue(DMA_TypeDef * DMAx,uint32_t Channel,uint32_t BlkRptSrcAddrOffset)5210 __STATIC_INLINE void LL_DMA_SetBlkRptSrcAddrUpdateValue(DMA_TypeDef *DMAx, uint32_t Channel,
5211 uint32_t BlkRptSrcAddrOffset)
5212 {
5213 uint32_t dma_base_addr = (uint32_t)DMAx;
5214 MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CBR2, DMA_CBR2_BRSAO,
5215 BlkRptSrcAddrOffset);
5216 }
5217
5218 /**
5219 * @brief Get block repeated source address offset.
5220 * @note This API is used only for 2D addressing channels.
5221 * @rmtoll CBR2 BRSAO LL_DMA_GetBlkRptSrcAddrUpdateValue
5222 * @param DMAx DMAx Instance
5223 * @param Channel This parameter can be one of the following values:
5224 * @arg @ref LL_DMA_CHANNEL_12
5225 * @arg @ref LL_DMA_CHANNEL_13
5226 * @arg @ref LL_DMA_CHANNEL_14
5227 * @arg @ref LL_DMA_CHANNEL_15
5228 * @retval Between 0 to 0x0000FFFF
5229 */
LL_DMA_GetBlkRptSrcAddrUpdateValue(DMA_TypeDef * DMAx,uint32_t Channel)5230 __STATIC_INLINE uint32_t LL_DMA_GetBlkRptSrcAddrUpdateValue(DMA_TypeDef *DMAx, uint32_t Channel)
5231 {
5232 uint32_t dma_base_addr = (uint32_t)DMAx;
5233 return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CBR2, DMA_CBR2_BRSAO));
5234 }
5235
5236 /**
5237 * @brief Configure registers update and node address offset during the link transfer.
5238 * @note This API is used for all available DMA channels.
5239 * For linear addressing channels, UT3 and UB2 fields are discarded.
5240 * @rmtoll CLLR UT1 LL_DMA_ConfigLinkUpdate\n
5241 * @rmtoll CLLR UT2 LL_DMA_ConfigLinkUpdate\n
5242 * @rmtoll CLLR UB1 LL_DMA_ConfigLinkUpdate\n
5243 * @rmtoll CLLR USA LL_DMA_ConfigLinkUpdate\n
5244 * @rmtoll CLLR UDA LL_DMA_ConfigLinkUpdate\n
5245 * @rmtoll CLLR UT3 LL_DMA_ConfigLinkUpdate\n
5246 * @rmtoll CLLR UB2 LL_DMA_ConfigLinkUpdate\n
5247 * @rmtoll CLLR ULL LL_DMA_ConfigLinkUpdate
5248 * @param DMAx DMAx Instance
5249 * @param Channel This parameter can be one of the following values:
5250 * @arg @ref LL_DMA_CHANNEL_0
5251 * @arg @ref LL_DMA_CHANNEL_1
5252 * @arg @ref LL_DMA_CHANNEL_2
5253 * @arg @ref LL_DMA_CHANNEL_3
5254 * @arg @ref LL_DMA_CHANNEL_4
5255 * @arg @ref LL_DMA_CHANNEL_5
5256 * @arg @ref LL_DMA_CHANNEL_6
5257 * @arg @ref LL_DMA_CHANNEL_7
5258 * @arg @ref LL_DMA_CHANNEL_8
5259 * @arg @ref LL_DMA_CHANNEL_9
5260 * @arg @ref LL_DMA_CHANNEL_10
5261 * @arg @ref LL_DMA_CHANNEL_11
5262 * @arg @ref LL_DMA_CHANNEL_12
5263 * @arg @ref LL_DMA_CHANNEL_13
5264 * @arg @ref LL_DMA_CHANNEL_14
5265 * @arg @ref LL_DMA_CHANNEL_15
5266 * @param RegistersUpdate This parameter must be a combination of all the following values:
5267 * @arg @ref LL_DMA_UPDATE_CTR1
5268 * @arg @ref LL_DMA_UPDATE_CTR2
5269 * @arg @ref LL_DMA_UPDATE_CBR1
5270 * @arg @ref LL_DMA_UPDATE_CSAR
5271 * @arg @ref LL_DMA_UPDATE_CDAR
5272 * @arg @ref LL_DMA_UPDATE_CTR3 (This value is allowed only for 2D addressing channels)
5273 * @arg @ref LL_DMA_UPDATE_CBR2 (This value is allowed only for 2D addressing channels)
5274 * @arg @ref LL_DMA_UPDATE_CLLR
5275 * @param LinkedListAddrOffset Between 0 to 0x0000FFFC
5276 * @retval None.
5277 */
LL_DMA_ConfigLinkUpdate(DMA_TypeDef * DMAx,uint32_t Channel,uint32_t RegistersUpdate,uint32_t LinkedListAddrOffset)5278 __STATIC_INLINE void LL_DMA_ConfigLinkUpdate(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t RegistersUpdate,
5279 uint32_t LinkedListAddrOffset)
5280 {
5281 uint32_t dma_base_addr = (uint32_t)DMAx;
5282 MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR,
5283 (DMA_CLLR_UT1 | DMA_CLLR_UT2 | DMA_CLLR_UB1 | DMA_CLLR_USA | DMA_CLLR_UDA | DMA_CLLR_UT3 | \
5284 DMA_CLLR_UB2 | DMA_CLLR_ULL | DMA_CLLR_LA), (RegistersUpdate | (LinkedListAddrOffset & DMA_CLLR_LA)));
5285 }
5286
5287 /**
5288 * @brief Enable CTR1 update during the link transfer.
5289 * @note This API is used for all available DMA channels.
5290 * @rmtoll CLLR UT1 LL_DMA_EnableCTR1Update
5291 * @param DMAx DMAx Instance
5292 * @param Channel This parameter can be one of the following values:
5293 * @arg @ref LL_DMA_CHANNEL_0
5294 * @arg @ref LL_DMA_CHANNEL_1
5295 * @arg @ref LL_DMA_CHANNEL_2
5296 * @arg @ref LL_DMA_CHANNEL_3
5297 * @arg @ref LL_DMA_CHANNEL_4
5298 * @arg @ref LL_DMA_CHANNEL_5
5299 * @arg @ref LL_DMA_CHANNEL_6
5300 * @arg @ref LL_DMA_CHANNEL_7
5301 * @arg @ref LL_DMA_CHANNEL_8
5302 * @arg @ref LL_DMA_CHANNEL_9
5303 * @arg @ref LL_DMA_CHANNEL_10
5304 * @arg @ref LL_DMA_CHANNEL_11
5305 * @arg @ref LL_DMA_CHANNEL_12
5306 * @arg @ref LL_DMA_CHANNEL_13
5307 * @arg @ref LL_DMA_CHANNEL_14
5308 * @arg @ref LL_DMA_CHANNEL_15
5309 * @retval None.
5310 */
LL_DMA_EnableCTR1Update(DMA_TypeDef * DMAx,uint32_t Channel)5311 __STATIC_INLINE void LL_DMA_EnableCTR1Update(DMA_TypeDef *DMAx, uint32_t Channel)
5312 {
5313 uint32_t dma_base_addr = (uint32_t)DMAx;
5314 SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_UT1);
5315 }
5316
5317 /**
5318 * @brief Disable CTR1 update during the link transfer.
5319 * @note This API is used for all available DMA channels.
5320 * @rmtoll CLLR UT1 LL_DMA_DisableCTR1Update
5321 * @param DMAx DMAx Instance
5322 * @param Channel This parameter can be one of the following values:
5323 * @arg @ref LL_DMA_CHANNEL_0
5324 * @arg @ref LL_DMA_CHANNEL_1
5325 * @arg @ref LL_DMA_CHANNEL_2
5326 * @arg @ref LL_DMA_CHANNEL_3
5327 * @arg @ref LL_DMA_CHANNEL_4
5328 * @arg @ref LL_DMA_CHANNEL_5
5329 * @arg @ref LL_DMA_CHANNEL_6
5330 * @arg @ref LL_DMA_CHANNEL_7
5331 * @arg @ref LL_DMA_CHANNEL_8
5332 * @arg @ref LL_DMA_CHANNEL_9
5333 * @arg @ref LL_DMA_CHANNEL_10
5334 * @arg @ref LL_DMA_CHANNEL_11
5335 * @arg @ref LL_DMA_CHANNEL_12
5336 * @arg @ref LL_DMA_CHANNEL_13
5337 * @arg @ref LL_DMA_CHANNEL_14
5338 * @arg @ref LL_DMA_CHANNEL_15
5339 * @retval None.
5340 */
LL_DMA_DisableCTR1Update(DMA_TypeDef * DMAx,uint32_t Channel)5341 __STATIC_INLINE void LL_DMA_DisableCTR1Update(DMA_TypeDef *DMAx, uint32_t Channel)
5342 {
5343 uint32_t dma_base_addr = (uint32_t)DMAx;
5344 CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_UT1);
5345 }
5346
5347 /**
5348 * @brief Check if CTR1 update during the link transfer is enabled.
5349 * @note This API is used for all available DMA channels.
5350 * @rmtoll CLLR UT1 LL_DMA_IsEnabledCTR1Update
5351 * @param DMAx DMAx Instance
5352 * @param Channel This parameter can be one of the following values:
5353 * @arg @ref LL_DMA_CHANNEL_0
5354 * @arg @ref LL_DMA_CHANNEL_1
5355 * @arg @ref LL_DMA_CHANNEL_2
5356 * @arg @ref LL_DMA_CHANNEL_3
5357 * @arg @ref LL_DMA_CHANNEL_4
5358 * @arg @ref LL_DMA_CHANNEL_5
5359 * @arg @ref LL_DMA_CHANNEL_6
5360 * @arg @ref LL_DMA_CHANNEL_7
5361 * @arg @ref LL_DMA_CHANNEL_8
5362 * @arg @ref LL_DMA_CHANNEL_9
5363 * @arg @ref LL_DMA_CHANNEL_10
5364 * @arg @ref LL_DMA_CHANNEL_11
5365 * @arg @ref LL_DMA_CHANNEL_12
5366 * @arg @ref LL_DMA_CHANNEL_13
5367 * @arg @ref LL_DMA_CHANNEL_14
5368 * @arg @ref LL_DMA_CHANNEL_15
5369 * @retval State of bit (1 or 0).
5370 */
LL_DMA_IsEnabledCTR1Update(DMA_TypeDef * DMAx,uint32_t Channel)5371 __STATIC_INLINE uint32_t LL_DMA_IsEnabledCTR1Update(DMA_TypeDef *DMAx, uint32_t Channel)
5372 {
5373 uint32_t dma_base_addr = (uint32_t)DMAx;
5374 return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_UT1)
5375 == (DMA_CLLR_UT1)) ? 1UL : 0UL);
5376 }
5377
5378 /**
5379 * @brief Enable CTR2 update during the link transfer.
5380 * @note This API is used for all available DMA channels.
5381 * @rmtoll CLLR UT2 LL_DMA_EnableCTR2Update
5382 * @param DMAx DMAx Instance
5383 * @param Channel This parameter can be one of the following values:
5384 * @arg @ref LL_DMA_CHANNEL_0
5385 * @arg @ref LL_DMA_CHANNEL_1
5386 * @arg @ref LL_DMA_CHANNEL_2
5387 * @arg @ref LL_DMA_CHANNEL_3
5388 * @arg @ref LL_DMA_CHANNEL_4
5389 * @arg @ref LL_DMA_CHANNEL_5
5390 * @arg @ref LL_DMA_CHANNEL_6
5391 * @arg @ref LL_DMA_CHANNEL_7
5392 * @arg @ref LL_DMA_CHANNEL_8
5393 * @arg @ref LL_DMA_CHANNEL_9
5394 * @arg @ref LL_DMA_CHANNEL_10
5395 * @arg @ref LL_DMA_CHANNEL_11
5396 * @arg @ref LL_DMA_CHANNEL_12
5397 * @arg @ref LL_DMA_CHANNEL_13
5398 * @arg @ref LL_DMA_CHANNEL_14
5399 * @arg @ref LL_DMA_CHANNEL_15
5400 * @retval None.
5401 */
LL_DMA_EnableCTR2Update(DMA_TypeDef * DMAx,uint32_t Channel)5402 __STATIC_INLINE void LL_DMA_EnableCTR2Update(DMA_TypeDef *DMAx, uint32_t Channel)
5403 {
5404 uint32_t dma_base_addr = (uint32_t)DMAx;
5405 SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_UT2);
5406 }
5407
5408 /**
5409 * @brief Disable CTR2 update during the link transfer.
5410 * @note This API is used for all available DMA channels.
5411 * @rmtoll CLLR UT2 LL_DMA_DisableCTR2Update
5412 * @param DMAx DMAx Instance
5413 * @param Channel This parameter can be one of the following values:
5414 * @arg @ref LL_DMA_CHANNEL_0
5415 * @arg @ref LL_DMA_CHANNEL_1
5416 * @arg @ref LL_DMA_CHANNEL_2
5417 * @arg @ref LL_DMA_CHANNEL_3
5418 * @arg @ref LL_DMA_CHANNEL_4
5419 * @arg @ref LL_DMA_CHANNEL_5
5420 * @arg @ref LL_DMA_CHANNEL_6
5421 * @arg @ref LL_DMA_CHANNEL_7
5422 * @arg @ref LL_DMA_CHANNEL_8
5423 * @arg @ref LL_DMA_CHANNEL_9
5424 * @arg @ref LL_DMA_CHANNEL_10
5425 * @arg @ref LL_DMA_CHANNEL_11
5426 * @arg @ref LL_DMA_CHANNEL_12
5427 * @arg @ref LL_DMA_CHANNEL_13
5428 * @arg @ref LL_DMA_CHANNEL_14
5429 * @arg @ref LL_DMA_CHANNEL_15
5430 * @retval None.
5431 */
LL_DMA_DisableCTR2Update(DMA_TypeDef * DMAx,uint32_t Channel)5432 __STATIC_INLINE void LL_DMA_DisableCTR2Update(DMA_TypeDef *DMAx, uint32_t Channel)
5433 {
5434 uint32_t dma_base_addr = (uint32_t)DMAx;
5435 CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_UT2);
5436 }
5437
5438 /**
5439 * @brief Check if CTR2 update during the link transfer is enabled.
5440 * @note This API is used for all available DMA channels.
5441 * @rmtoll CLLR UT2 LL_DMA_IsEnabledCTR2Update
5442 * @param DMAx DMAx Instance
5443 * @param Channel This parameter can be one of the following values:
5444 * @arg @ref LL_DMA_CHANNEL_0
5445 * @arg @ref LL_DMA_CHANNEL_1
5446 * @arg @ref LL_DMA_CHANNEL_2
5447 * @arg @ref LL_DMA_CHANNEL_3
5448 * @arg @ref LL_DMA_CHANNEL_4
5449 * @arg @ref LL_DMA_CHANNEL_5
5450 * @arg @ref LL_DMA_CHANNEL_6
5451 * @arg @ref LL_DMA_CHANNEL_7
5452 * @arg @ref LL_DMA_CHANNEL_8
5453 * @arg @ref LL_DMA_CHANNEL_9
5454 * @arg @ref LL_DMA_CHANNEL_10
5455 * @arg @ref LL_DMA_CHANNEL_11
5456 * @arg @ref LL_DMA_CHANNEL_12
5457 * @arg @ref LL_DMA_CHANNEL_13
5458 * @arg @ref LL_DMA_CHANNEL_14
5459 * @arg @ref LL_DMA_CHANNEL_15
5460 * @retval State of bit (1 or 0).
5461 */
LL_DMA_IsEnabledCTR2Update(DMA_TypeDef * DMAx,uint32_t Channel)5462 __STATIC_INLINE uint32_t LL_DMA_IsEnabledCTR2Update(DMA_TypeDef *DMAx, uint32_t Channel)
5463 {
5464 uint32_t dma_base_addr = (uint32_t)DMAx;
5465 return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_UT2)
5466 == (DMA_CLLR_UT2)) ? 1UL : 0UL);
5467 }
5468
5469 /**
5470 * @brief Enable CBR1 update during the link transfer.
5471 * @note This API is used for all available DMA channels.
5472 * @rmtoll CLLR UB1 LL_DMA_EnableCBR1Update
5473 * @param DMAx DMAx Instance
5474 * @param Channel This parameter can be one of the following values:
5475 * @arg @ref LL_DMA_CHANNEL_0
5476 * @arg @ref LL_DMA_CHANNEL_1
5477 * @arg @ref LL_DMA_CHANNEL_2
5478 * @arg @ref LL_DMA_CHANNEL_3
5479 * @arg @ref LL_DMA_CHANNEL_4
5480 * @arg @ref LL_DMA_CHANNEL_5
5481 * @arg @ref LL_DMA_CHANNEL_6
5482 * @arg @ref LL_DMA_CHANNEL_7
5483 * @arg @ref LL_DMA_CHANNEL_8
5484 * @arg @ref LL_DMA_CHANNEL_9
5485 * @arg @ref LL_DMA_CHANNEL_10
5486 * @arg @ref LL_DMA_CHANNEL_11
5487 * @arg @ref LL_DMA_CHANNEL_12
5488 * @arg @ref LL_DMA_CHANNEL_13
5489 * @arg @ref LL_DMA_CHANNEL_14
5490 * @arg @ref LL_DMA_CHANNEL_15
5491 * @retval None.
5492 */
LL_DMA_EnableCBR1Update(DMA_TypeDef * DMAx,uint32_t Channel)5493 __STATIC_INLINE void LL_DMA_EnableCBR1Update(DMA_TypeDef *DMAx, uint32_t Channel)
5494 {
5495 uint32_t dma_base_addr = (uint32_t)DMAx;
5496 SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_UB1);
5497 }
5498
5499 /**
5500 * @brief Disable CBR1 update during the link transfer.
5501 * @note This API is used for all available DMA channels.
5502 * @rmtoll CLLR UB1 LL_DMA_DisableCBR1Update
5503 * @param DMAx DMAx Instance
5504 * @param Channel This parameter can be one of the following values:
5505 * @arg @ref LL_DMA_CHANNEL_0
5506 * @arg @ref LL_DMA_CHANNEL_1
5507 * @arg @ref LL_DMA_CHANNEL_2
5508 * @arg @ref LL_DMA_CHANNEL_3
5509 * @arg @ref LL_DMA_CHANNEL_4
5510 * @arg @ref LL_DMA_CHANNEL_5
5511 * @arg @ref LL_DMA_CHANNEL_6
5512 * @arg @ref LL_DMA_CHANNEL_7
5513 * @arg @ref LL_DMA_CHANNEL_8
5514 * @arg @ref LL_DMA_CHANNEL_9
5515 * @arg @ref LL_DMA_CHANNEL_10
5516 * @arg @ref LL_DMA_CHANNEL_11
5517 * @arg @ref LL_DMA_CHANNEL_12
5518 * @arg @ref LL_DMA_CHANNEL_13
5519 * @arg @ref LL_DMA_CHANNEL_14
5520 * @arg @ref LL_DMA_CHANNEL_15
5521 * @retval None.
5522 */
LL_DMA_DisableCBR1Update(DMA_TypeDef * DMAx,uint32_t Channel)5523 __STATIC_INLINE void LL_DMA_DisableCBR1Update(DMA_TypeDef *DMAx, uint32_t Channel)
5524 {
5525 uint32_t dma_base_addr = (uint32_t)DMAx;
5526 CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_UB1);
5527 }
5528
5529 /**
5530 * @brief Check if CBR1 update during the link transfer is enabled.
5531 * @note This API is used for all available DMA channels.
5532 * @rmtoll CLLR UB1 LL_DMA_IsEnabledCBR1Update
5533 * @param DMAx DMAx Instance
5534 * @param Channel This parameter can be one of the following values:
5535 * @arg @ref LL_DMA_CHANNEL_0
5536 * @arg @ref LL_DMA_CHANNEL_1
5537 * @arg @ref LL_DMA_CHANNEL_2
5538 * @arg @ref LL_DMA_CHANNEL_3
5539 * @arg @ref LL_DMA_CHANNEL_4
5540 * @arg @ref LL_DMA_CHANNEL_5
5541 * @arg @ref LL_DMA_CHANNEL_6
5542 * @arg @ref LL_DMA_CHANNEL_7
5543 * @arg @ref LL_DMA_CHANNEL_8
5544 * @arg @ref LL_DMA_CHANNEL_9
5545 * @arg @ref LL_DMA_CHANNEL_10
5546 * @arg @ref LL_DMA_CHANNEL_11
5547 * @arg @ref LL_DMA_CHANNEL_12
5548 * @arg @ref LL_DMA_CHANNEL_13
5549 * @arg @ref LL_DMA_CHANNEL_14
5550 * @arg @ref LL_DMA_CHANNEL_15
5551 * @retval State of bit (1 or 0).
5552 */
LL_DMA_IsEnabledCBR1Update(DMA_TypeDef * DMAx,uint32_t Channel)5553 __STATIC_INLINE uint32_t LL_DMA_IsEnabledCBR1Update(DMA_TypeDef *DMAx, uint32_t Channel)
5554 {
5555 uint32_t dma_base_addr = (uint32_t)DMAx;
5556 return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_UB1)
5557 == (DMA_CLLR_UB1)) ? 1UL : 0UL);
5558 }
5559
5560 /**
5561 * @brief Enable CSAR update during the link transfer.
5562 * @note This API is used for all available DMA channels.
5563 * @rmtoll CLLR USA LL_DMA_EnableCSARUpdate
5564 * @param DMAx DMAx Instance
5565 * @param Channel This parameter can be one of the following values:
5566 * @arg @ref LL_DMA_CHANNEL_0
5567 * @arg @ref LL_DMA_CHANNEL_1
5568 * @arg @ref LL_DMA_CHANNEL_2
5569 * @arg @ref LL_DMA_CHANNEL_3
5570 * @arg @ref LL_DMA_CHANNEL_4
5571 * @arg @ref LL_DMA_CHANNEL_5
5572 * @arg @ref LL_DMA_CHANNEL_6
5573 * @arg @ref LL_DMA_CHANNEL_7
5574 * @arg @ref LL_DMA_CHANNEL_8
5575 * @arg @ref LL_DMA_CHANNEL_9
5576 * @arg @ref LL_DMA_CHANNEL_10
5577 * @arg @ref LL_DMA_CHANNEL_11
5578 * @arg @ref LL_DMA_CHANNEL_12
5579 * @arg @ref LL_DMA_CHANNEL_13
5580 * @arg @ref LL_DMA_CHANNEL_14
5581 * @arg @ref LL_DMA_CHANNEL_15
5582 * @retval None.
5583 */
LL_DMA_EnableCSARUpdate(DMA_TypeDef * DMAx,uint32_t Channel)5584 __STATIC_INLINE void LL_DMA_EnableCSARUpdate(DMA_TypeDef *DMAx, uint32_t Channel)
5585 {
5586 uint32_t dma_base_addr = (uint32_t)DMAx;
5587 SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_USA);
5588 }
5589
5590 /**
5591 * @brief Disable CSAR update during the link transfer.
5592 * @note This API is used for all available DMA channels.
5593 * @rmtoll CLLR USA LL_DMA_DisableCSARUpdate
5594 * @param DMAx DMAx Instance
5595 * @param Channel This parameter can be one of the following values:
5596 * @arg @ref LL_DMA_CHANNEL_0
5597 * @arg @ref LL_DMA_CHANNEL_1
5598 * @arg @ref LL_DMA_CHANNEL_2
5599 * @arg @ref LL_DMA_CHANNEL_3
5600 * @arg @ref LL_DMA_CHANNEL_4
5601 * @arg @ref LL_DMA_CHANNEL_5
5602 * @arg @ref LL_DMA_CHANNEL_6
5603 * @arg @ref LL_DMA_CHANNEL_7
5604 * @arg @ref LL_DMA_CHANNEL_8
5605 * @arg @ref LL_DMA_CHANNEL_9
5606 * @arg @ref LL_DMA_CHANNEL_10
5607 * @arg @ref LL_DMA_CHANNEL_11
5608 * @arg @ref LL_DMA_CHANNEL_12
5609 * @arg @ref LL_DMA_CHANNEL_13
5610 * @arg @ref LL_DMA_CHANNEL_14
5611 * @arg @ref LL_DMA_CHANNEL_15
5612 * @retval None.
5613 */
LL_DMA_DisableCSARUpdate(DMA_TypeDef * DMAx,uint32_t Channel)5614 __STATIC_INLINE void LL_DMA_DisableCSARUpdate(DMA_TypeDef *DMAx, uint32_t Channel)
5615 {
5616 uint32_t dma_base_addr = (uint32_t)DMAx;
5617 CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_USA);
5618 }
5619
5620 /**
5621 * @brief Check if CSAR update during the link transfer is enabled.
5622 * @note This API is used for all available DMA channels.
5623 * @rmtoll CLLR USA LL_DMA_IsEnabledCSARUpdate
5624 * @param DMAx DMAx Instance
5625 * @param Channel This parameter can be one of the following values:
5626 * @arg @ref LL_DMA_CHANNEL_0
5627 * @arg @ref LL_DMA_CHANNEL_1
5628 * @arg @ref LL_DMA_CHANNEL_2
5629 * @arg @ref LL_DMA_CHANNEL_3
5630 * @arg @ref LL_DMA_CHANNEL_4
5631 * @arg @ref LL_DMA_CHANNEL_5
5632 * @arg @ref LL_DMA_CHANNEL_6
5633 * @arg @ref LL_DMA_CHANNEL_7
5634 * @arg @ref LL_DMA_CHANNEL_8
5635 * @arg @ref LL_DMA_CHANNEL_9
5636 * @arg @ref LL_DMA_CHANNEL_10
5637 * @arg @ref LL_DMA_CHANNEL_11
5638 * @arg @ref LL_DMA_CHANNEL_12
5639 * @arg @ref LL_DMA_CHANNEL_13
5640 * @arg @ref LL_DMA_CHANNEL_14
5641 * @arg @ref LL_DMA_CHANNEL_15
5642 * @retval State of bit (1 or 0).
5643 */
LL_DMA_IsEnabledCSARUpdate(DMA_TypeDef * DMAx,uint32_t Channel)5644 __STATIC_INLINE uint32_t LL_DMA_IsEnabledCSARUpdate(DMA_TypeDef *DMAx, uint32_t Channel)
5645 {
5646 uint32_t dma_base_addr = (uint32_t)DMAx;
5647 return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_USA)
5648 == (DMA_CLLR_USA)) ? 1UL : 0UL);
5649 }
5650
5651 /**
5652 * @brief Enable CDAR update during the link transfer.
5653 * @note This API is used for all available DMA channels.
5654 * @rmtoll CLLR UDA LL_DMA_EnableCDARUpdate
5655 * @param DMAx DMAx Instance
5656 * @param Channel This parameter can be one of the following values:
5657 * @arg @ref LL_DMA_CHANNEL_0
5658 * @arg @ref LL_DMA_CHANNEL_1
5659 * @arg @ref LL_DMA_CHANNEL_2
5660 * @arg @ref LL_DMA_CHANNEL_3
5661 * @arg @ref LL_DMA_CHANNEL_4
5662 * @arg @ref LL_DMA_CHANNEL_5
5663 * @arg @ref LL_DMA_CHANNEL_6
5664 * @arg @ref LL_DMA_CHANNEL_7
5665 * @arg @ref LL_DMA_CHANNEL_8
5666 * @arg @ref LL_DMA_CHANNEL_9
5667 * @arg @ref LL_DMA_CHANNEL_10
5668 * @arg @ref LL_DMA_CHANNEL_11
5669 * @arg @ref LL_DMA_CHANNEL_12
5670 * @arg @ref LL_DMA_CHANNEL_13
5671 * @arg @ref LL_DMA_CHANNEL_14
5672 * @arg @ref LL_DMA_CHANNEL_15
5673 * @retval None.
5674 */
LL_DMA_EnableCDARUpdate(DMA_TypeDef * DMAx,uint32_t Channel)5675 __STATIC_INLINE void LL_DMA_EnableCDARUpdate(DMA_TypeDef *DMAx, uint32_t Channel)
5676 {
5677 uint32_t dma_base_addr = (uint32_t)DMAx;
5678 SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_UDA);
5679 }
5680
5681 /**
5682 * @brief Disable CDAR update during the link transfer.
5683 * @note This API is used for all available DMA channels.
5684 * @rmtoll CLLR UDA LL_DMA_DisableCDARUpdate
5685 * @param DMAx DMAx Instance
5686 * @param Channel This parameter can be one of the following values:
5687 * @arg @ref LL_DMA_CHANNEL_0
5688 * @arg @ref LL_DMA_CHANNEL_1
5689 * @arg @ref LL_DMA_CHANNEL_2
5690 * @arg @ref LL_DMA_CHANNEL_3
5691 * @arg @ref LL_DMA_CHANNEL_4
5692 * @arg @ref LL_DMA_CHANNEL_5
5693 * @arg @ref LL_DMA_CHANNEL_6
5694 * @arg @ref LL_DMA_CHANNEL_7
5695 * @arg @ref LL_DMA_CHANNEL_8
5696 * @arg @ref LL_DMA_CHANNEL_9
5697 * @arg @ref LL_DMA_CHANNEL_10
5698 * @arg @ref LL_DMA_CHANNEL_11
5699 * @arg @ref LL_DMA_CHANNEL_12
5700 * @arg @ref LL_DMA_CHANNEL_13
5701 * @arg @ref LL_DMA_CHANNEL_14
5702 * @arg @ref LL_DMA_CHANNEL_15
5703 * @retval None.
5704 */
LL_DMA_DisableCDARUpdate(DMA_TypeDef * DMAx,uint32_t Channel)5705 __STATIC_INLINE void LL_DMA_DisableCDARUpdate(DMA_TypeDef *DMAx, uint32_t Channel)
5706 {
5707 uint32_t dma_base_addr = (uint32_t)DMAx;
5708 CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_UDA);
5709 }
5710
5711 /**
5712 * @brief Check if CDAR update during the link transfer is enabled.
5713 * @note This API is used for all available DMA channels.
5714 * @rmtoll CLLR UDA LL_DMA_IsEnabledCDARUpdate
5715 * @param DMAx DMAx Instance
5716 * @param Channel This parameter can be one of the following values:
5717 * @arg @ref LL_DMA_CHANNEL_0
5718 * @arg @ref LL_DMA_CHANNEL_1
5719 * @arg @ref LL_DMA_CHANNEL_2
5720 * @arg @ref LL_DMA_CHANNEL_3
5721 * @arg @ref LL_DMA_CHANNEL_4
5722 * @arg @ref LL_DMA_CHANNEL_5
5723 * @arg @ref LL_DMA_CHANNEL_6
5724 * @arg @ref LL_DMA_CHANNEL_7
5725 * @arg @ref LL_DMA_CHANNEL_8
5726 * @arg @ref LL_DMA_CHANNEL_9
5727 * @arg @ref LL_DMA_CHANNEL_10
5728 * @arg @ref LL_DMA_CHANNEL_11
5729 * @arg @ref LL_DMA_CHANNEL_12
5730 * @arg @ref LL_DMA_CHANNEL_13
5731 * @arg @ref LL_DMA_CHANNEL_14
5732 * @arg @ref LL_DMA_CHANNEL_15
5733 * @retval State of bit (1 or 0).
5734 */
LL_DMA_IsEnabledCDARUpdate(DMA_TypeDef * DMAx,uint32_t Channel)5735 __STATIC_INLINE uint32_t LL_DMA_IsEnabledCDARUpdate(DMA_TypeDef *DMAx, uint32_t Channel)
5736 {
5737 uint32_t dma_base_addr = (uint32_t)DMAx;
5738 return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_UDA)
5739 == (DMA_CLLR_UDA)) ? 1UL : 0UL);
5740 }
5741
5742 /**
5743 * @brief Enable CTR3 update during the link transfer.
5744 * @note This API is used only for 2D addressing channels.
5745 * @rmtoll CLLR UT3 LL_DMA_EnableCTR3Update
5746 * @param DMAx DMAx Instance
5747 * @param Channel This parameter can be one of the following values:
5748 * @arg @ref LL_DMA_CHANNEL_12
5749 * @arg @ref LL_DMA_CHANNEL_13
5750 * @arg @ref LL_DMA_CHANNEL_14
5751 * @arg @ref LL_DMA_CHANNEL_15
5752 * @retval None.
5753 */
LL_DMA_EnableCTR3Update(DMA_TypeDef * DMAx,uint32_t Channel)5754 __STATIC_INLINE void LL_DMA_EnableCTR3Update(DMA_TypeDef *DMAx, uint32_t Channel)
5755 {
5756 uint32_t dma_base_addr = (uint32_t)DMAx;
5757 SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_UT3);
5758 }
5759
5760 /**
5761 * @brief Disable CTR3 update during the link transfer.
5762 * @note This API is used only for 2D addressing channels.
5763 * @rmtoll CLLR UT3 LL_DMA_DisableCTR3Update
5764 * @param DMAx DMAx Instance
5765 * @param Channel This parameter can be one of the following values:
5766 * @arg @ref LL_DMA_CHANNEL_12
5767 * @arg @ref LL_DMA_CHANNEL_13
5768 * @arg @ref LL_DMA_CHANNEL_14
5769 * @arg @ref LL_DMA_CHANNEL_15
5770 * @retval None.
5771 */
LL_DMA_DisableCTR3Update(DMA_TypeDef * DMAx,uint32_t Channel)5772 __STATIC_INLINE void LL_DMA_DisableCTR3Update(DMA_TypeDef *DMAx, uint32_t Channel)
5773 {
5774 uint32_t dma_base_addr = (uint32_t)DMAx;
5775 CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_UT3);
5776 }
5777
5778 /**
5779 * @brief Check if CTR3 update during the link transfer is enabled.
5780 * @note This API is used only for 2D addressing channels.
5781 * @rmtoll CLLR UT3 LL_DMA_IsEnabledCTR3Update
5782 * @param DMAx DMAx Instance
5783 * @param Channel This parameter can be one of the following values:
5784 * @arg @ref LL_DMA_CHANNEL_12
5785 * @arg @ref LL_DMA_CHANNEL_13
5786 * @arg @ref LL_DMA_CHANNEL_14
5787 * @arg @ref LL_DMA_CHANNEL_15
5788 * @retval State of bit (1 or 0).
5789 */
LL_DMA_IsEnabledCTR3Update(DMA_TypeDef * DMAx,uint32_t Channel)5790 __STATIC_INLINE uint32_t LL_DMA_IsEnabledCTR3Update(DMA_TypeDef *DMAx, uint32_t Channel)
5791 {
5792 uint32_t dma_base_addr = (uint32_t)DMAx;
5793 return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_UT3)
5794 == (DMA_CLLR_UT3)) ? 1UL : 0UL);
5795 }
5796
5797 /**
5798 * @brief Enable CBR2 update during the link transfer.
5799 * @note This API is used only for 2D addressing channels.
5800 * @rmtoll CLLR UB2 LL_DMA_EnableCBR2Update
5801 * @param DMAx DMAx Instance
5802 * @param Channel This parameter can be one of the following values:
5803 * @arg @ref LL_DMA_CHANNEL_12
5804 * @arg @ref LL_DMA_CHANNEL_13
5805 * @arg @ref LL_DMA_CHANNEL_14
5806 * @arg @ref LL_DMA_CHANNEL_15
5807 * @retval None.
5808 */
LL_DMA_EnableCBR2Update(DMA_TypeDef * DMAx,uint32_t Channel)5809 __STATIC_INLINE void LL_DMA_EnableCBR2Update(DMA_TypeDef *DMAx, uint32_t Channel)
5810 {
5811 uint32_t dma_base_addr = (uint32_t)DMAx;
5812 SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_UB2);
5813 }
5814
5815 /**
5816 * @brief Disable CBR2 update during the link transfer.
5817 * @note This API is used only for 2D addressing channels.
5818 * @rmtoll CLLR UB2 LL_DMA_DisableCBR2Update
5819 * @param DMAx DMAx Instance
5820 * @param Channel This parameter can be one of the following values:
5821 * @arg @ref LL_DMA_CHANNEL_12
5822 * @arg @ref LL_DMA_CHANNEL_13
5823 * @arg @ref LL_DMA_CHANNEL_14
5824 * @arg @ref LL_DMA_CHANNEL_15
5825 * @retval None.
5826 */
LL_DMA_DisableCBR2Update(DMA_TypeDef * DMAx,uint32_t Channel)5827 __STATIC_INLINE void LL_DMA_DisableCBR2Update(DMA_TypeDef *DMAx, uint32_t Channel)
5828 {
5829 uint32_t dma_base_addr = (uint32_t)DMAx;
5830 CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_UB2);
5831 }
5832
5833 /**
5834 * @brief Check if CBR2 update during the link transfer is enabled.
5835 * @note This API is used only for 2D addressing channels.
5836 * @rmtoll CLLR UB2 LL_DMA_IsEnabledCBR2Update
5837 * @param DMAx DMAx Instance
5838 * @param Channel This parameter can be one of the following values:
5839 * @arg @ref LL_DMA_CHANNEL_12
5840 * @arg @ref LL_DMA_CHANNEL_13
5841 * @arg @ref LL_DMA_CHANNEL_14
5842 * @arg @ref LL_DMA_CHANNEL_15
5843 * @retval State of bit (1 or 0).
5844 */
LL_DMA_IsEnabledCBR2Update(DMA_TypeDef * DMAx,uint32_t Channel)5845 __STATIC_INLINE uint32_t LL_DMA_IsEnabledCBR2Update(DMA_TypeDef *DMAx, uint32_t Channel)
5846 {
5847 uint32_t dma_base_addr = (uint32_t)DMAx;
5848 return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_UB2)
5849 == (DMA_CLLR_UB2)) ? 1UL : 0UL);
5850 }
5851
5852 /**
5853 * @brief Enable CLLR update during the link transfer.
5854 * @note This API is used for all available DMA channels.
5855 * @rmtoll CLLR ULL LL_DMA_EnableCLLRUpdate
5856 * @param DMAx DMAx Instance
5857 * @param Channel This parameter can be one of the following values:
5858 * @arg @ref LL_DMA_CHANNEL_0
5859 * @arg @ref LL_DMA_CHANNEL_1
5860 * @arg @ref LL_DMA_CHANNEL_2
5861 * @arg @ref LL_DMA_CHANNEL_3
5862 * @arg @ref LL_DMA_CHANNEL_4
5863 * @arg @ref LL_DMA_CHANNEL_5
5864 * @arg @ref LL_DMA_CHANNEL_6
5865 * @arg @ref LL_DMA_CHANNEL_7
5866 * @arg @ref LL_DMA_CHANNEL_8
5867 * @arg @ref LL_DMA_CHANNEL_9
5868 * @arg @ref LL_DMA_CHANNEL_10
5869 * @arg @ref LL_DMA_CHANNEL_11
5870 * @arg @ref LL_DMA_CHANNEL_12
5871 * @arg @ref LL_DMA_CHANNEL_13
5872 * @arg @ref LL_DMA_CHANNEL_14
5873 * @arg @ref LL_DMA_CHANNEL_15
5874 * @retval None.
5875 */
LL_DMA_EnableCLLRUpdate(DMA_TypeDef * DMAx,uint32_t Channel)5876 __STATIC_INLINE void LL_DMA_EnableCLLRUpdate(DMA_TypeDef *DMAx, uint32_t Channel)
5877 {
5878 uint32_t dma_base_addr = (uint32_t)DMAx;
5879 SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_ULL);
5880 }
5881
5882 /**
5883 * @brief Disable CLLR update during the link transfer.
5884 * @note This API is used for all available DMA channels.
5885 * @rmtoll CLLR ULL LL_DMA_DisableCLLRUpdate
5886 * @param DMAx DMAx Instance
5887 * @param Channel This parameter can be one of the following values:
5888 * @arg @ref LL_DMA_CHANNEL_0
5889 * @arg @ref LL_DMA_CHANNEL_1
5890 * @arg @ref LL_DMA_CHANNEL_2
5891 * @arg @ref LL_DMA_CHANNEL_3
5892 * @arg @ref LL_DMA_CHANNEL_4
5893 * @arg @ref LL_DMA_CHANNEL_5
5894 * @arg @ref LL_DMA_CHANNEL_6
5895 * @arg @ref LL_DMA_CHANNEL_7
5896 * @arg @ref LL_DMA_CHANNEL_8
5897 * @arg @ref LL_DMA_CHANNEL_9
5898 * @arg @ref LL_DMA_CHANNEL_10
5899 * @arg @ref LL_DMA_CHANNEL_11
5900 * @arg @ref LL_DMA_CHANNEL_12
5901 * @arg @ref LL_DMA_CHANNEL_13
5902 * @arg @ref LL_DMA_CHANNEL_14
5903 * @arg @ref LL_DMA_CHANNEL_15
5904 * @retval None.
5905 */
LL_DMA_DisableCLLRUpdate(DMA_TypeDef * DMAx,uint32_t Channel)5906 __STATIC_INLINE void LL_DMA_DisableCLLRUpdate(DMA_TypeDef *DMAx, uint32_t Channel)
5907 {
5908 uint32_t dma_base_addr = (uint32_t)DMAx;
5909 CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_ULL);
5910 }
5911
5912 /**
5913 * @brief Check if CLLR update during the link transfer is enabled.
5914 * @note This API is used for all available DMA channels.
5915 * @rmtoll CLLR ULL LL_DMA_IsEnabledCLLRUpdate
5916 * @param DMAx DMAx Instance
5917 * @param Channel This parameter can be one of the following values:
5918 * @arg @ref LL_DMA_CHANNEL_0
5919 * @arg @ref LL_DMA_CHANNEL_1
5920 * @arg @ref LL_DMA_CHANNEL_2
5921 * @arg @ref LL_DMA_CHANNEL_3
5922 * @arg @ref LL_DMA_CHANNEL_4
5923 * @arg @ref LL_DMA_CHANNEL_5
5924 * @arg @ref LL_DMA_CHANNEL_6
5925 * @arg @ref LL_DMA_CHANNEL_7
5926 * @arg @ref LL_DMA_CHANNEL_8
5927 * @arg @ref LL_DMA_CHANNEL_9
5928 * @arg @ref LL_DMA_CHANNEL_10
5929 * @arg @ref LL_DMA_CHANNEL_11
5930 * @arg @ref LL_DMA_CHANNEL_12
5931 * @arg @ref LL_DMA_CHANNEL_13
5932 * @arg @ref LL_DMA_CHANNEL_14
5933 * @arg @ref LL_DMA_CHANNEL_15
5934 * @retval State of bit (1 or 0).
5935 */
LL_DMA_IsEnabledCLLRUpdate(DMA_TypeDef * DMAx,uint32_t Channel)5936 __STATIC_INLINE uint32_t LL_DMA_IsEnabledCLLRUpdate(DMA_TypeDef *DMAx, uint32_t Channel)
5937 {
5938 uint32_t dma_base_addr = (uint32_t)DMAx;
5939 return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_ULL)
5940 == (DMA_CLLR_ULL)) ? 1UL : 0UL);
5941 }
5942
5943 /**
5944 * @brief Set linked list address offset.
5945 * @note This API is used for all available DMA channels.
5946 * @rmtoll CLLR LA LL_DMA_SetLinkedListAddrOffset
5947 * @param DMAx DMAx Instance
5948 * @param Channel This parameter can be one of the following values:
5949 * @arg @ref LL_DMA_CHANNEL_0
5950 * @arg @ref LL_DMA_CHANNEL_1
5951 * @arg @ref LL_DMA_CHANNEL_2
5952 * @arg @ref LL_DMA_CHANNEL_3
5953 * @arg @ref LL_DMA_CHANNEL_4
5954 * @arg @ref LL_DMA_CHANNEL_5
5955 * @arg @ref LL_DMA_CHANNEL_6
5956 * @arg @ref LL_DMA_CHANNEL_7
5957 * @arg @ref LL_DMA_CHANNEL_8
5958 * @arg @ref LL_DMA_CHANNEL_9
5959 * @arg @ref LL_DMA_CHANNEL_10
5960 * @arg @ref LL_DMA_CHANNEL_11
5961 * @arg @ref LL_DMA_CHANNEL_12
5962 * @arg @ref LL_DMA_CHANNEL_13
5963 * @arg @ref LL_DMA_CHANNEL_14
5964 * @arg @ref LL_DMA_CHANNEL_15
5965 * @param LinkedListAddrOffset Between 0 to 0x0000FFFC
5966 * @retval None.
5967 */
LL_DMA_SetLinkedListAddrOffset(DMA_TypeDef * DMAx,uint32_t Channel,uint32_t LinkedListAddrOffset)5968 __STATIC_INLINE void LL_DMA_SetLinkedListAddrOffset(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t LinkedListAddrOffset)
5969 {
5970 uint32_t dma_base_addr = (uint32_t)DMAx;
5971 MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_LA,
5972 (LinkedListAddrOffset & DMA_CLLR_LA));
5973 }
5974
5975 /**
5976 * @brief Get linked list address offset.
5977 * @note This API is used for all available DMA channels.
5978 * @rmtoll CLLR LA LL_DMA_GetLinkedListAddrOffset
5979 * @param DMAx DMAx Instance
5980 * @param Channel This parameter can be one of the following values:
5981 * @arg @ref LL_DMA_CHANNEL_0
5982 * @arg @ref LL_DMA_CHANNEL_1
5983 * @arg @ref LL_DMA_CHANNEL_2
5984 * @arg @ref LL_DMA_CHANNEL_3
5985 * @arg @ref LL_DMA_CHANNEL_4
5986 * @arg @ref LL_DMA_CHANNEL_5
5987 * @arg @ref LL_DMA_CHANNEL_6
5988 * @arg @ref LL_DMA_CHANNEL_7
5989 * @arg @ref LL_DMA_CHANNEL_8
5990 * @arg @ref LL_DMA_CHANNEL_9
5991 * @arg @ref LL_DMA_CHANNEL_10
5992 * @arg @ref LL_DMA_CHANNEL_11
5993 * @arg @ref LL_DMA_CHANNEL_12
5994 * @arg @ref LL_DMA_CHANNEL_13
5995 * @arg @ref LL_DMA_CHANNEL_14
5996 * @arg @ref LL_DMA_CHANNEL_15
5997 * @retval Between 0 to 0x0000FFFC.
5998 */
LL_DMA_GetLinkedListAddrOffset(DMA_TypeDef * DMAx,uint32_t Channel)5999 __STATIC_INLINE uint32_t LL_DMA_GetLinkedListAddrOffset(DMA_TypeDef *DMAx, uint32_t Channel)
6000 {
6001 uint32_t dma_base_addr = (uint32_t)DMAx;
6002 return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR,
6003 DMA_CLLR_LA) >> DMA_CLLR_LA_Pos);
6004 }
6005
6006 /**
6007 * @brief Get FIFO level.
6008 * @note This API is not used for LPDMA channels.
6009 * @rmtoll CSR FIFOL LL_DMA_GetFIFOLevel
6010 * @param DMAx DMAx Instance
6011 * @param Channel This parameter can be one of the following values:
6012 * @arg @ref LL_DMA_CHANNEL_0
6013 * @arg @ref LL_DMA_CHANNEL_1
6014 * @arg @ref LL_DMA_CHANNEL_2
6015 * @arg @ref LL_DMA_CHANNEL_3
6016 * @arg @ref LL_DMA_CHANNEL_4
6017 * @arg @ref LL_DMA_CHANNEL_5
6018 * @arg @ref LL_DMA_CHANNEL_6
6019 * @arg @ref LL_DMA_CHANNEL_7
6020 * @arg @ref LL_DMA_CHANNEL_8
6021 * @arg @ref LL_DMA_CHANNEL_9
6022 * @arg @ref LL_DMA_CHANNEL_10
6023 * @arg @ref LL_DMA_CHANNEL_11
6024 * @arg @ref LL_DMA_CHANNEL_12
6025 * @arg @ref LL_DMA_CHANNEL_13
6026 * @arg @ref LL_DMA_CHANNEL_14
6027 * @arg @ref LL_DMA_CHANNEL_15
6028 * @retval Between 0 to 0x000000FF.
6029 */
LL_DMA_GetFIFOLevel(DMA_TypeDef * DMAx,uint32_t Channel)6030 __STATIC_INLINE uint32_t LL_DMA_GetFIFOLevel(DMA_TypeDef *DMAx, uint32_t Channel)
6031 {
6032 uint32_t dma_base_addr = (uint32_t)DMAx;
6033 return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CSR,
6034 DMA_CSR_FIFOL) >> DMA_CSR_FIFOL_Pos);
6035 }
6036
6037 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
6038 /**
6039 * @brief Enable the DMA channel secure attribute.
6040 * @note This API is used for all available DMA channels.
6041 * @rmtoll SECCFGR SECx LL_DMA_EnableChannelSecure
6042 * @param DMAx DMAx Instance
6043 * @param Channel This parameter can be one of the following values:
6044 * @arg @ref LL_DMA_CHANNEL_0
6045 * @arg @ref LL_DMA_CHANNEL_1
6046 * @arg @ref LL_DMA_CHANNEL_2
6047 * @arg @ref LL_DMA_CHANNEL_3
6048 * @arg @ref LL_DMA_CHANNEL_4
6049 * @arg @ref LL_DMA_CHANNEL_5
6050 * @arg @ref LL_DMA_CHANNEL_6
6051 * @arg @ref LL_DMA_CHANNEL_7
6052 * @arg @ref LL_DMA_CHANNEL_8
6053 * @arg @ref LL_DMA_CHANNEL_9
6054 * @arg @ref LL_DMA_CHANNEL_10
6055 * @arg @ref LL_DMA_CHANNEL_11
6056 * @arg @ref LL_DMA_CHANNEL_12
6057 * @arg @ref LL_DMA_CHANNEL_13
6058 * @arg @ref LL_DMA_CHANNEL_14
6059 * @arg @ref LL_DMA_CHANNEL_15
6060 * @retval None.
6061 */
LL_DMA_EnableChannelSecure(DMA_TypeDef * DMAx,uint32_t Channel)6062 __STATIC_INLINE void LL_DMA_EnableChannelSecure(DMA_TypeDef *DMAx, uint32_t Channel)
6063 {
6064 SET_BIT(DMAx->SECCFGR, (DMA_SECCFGR_SEC0 << (Channel & 0x0000000FU)));
6065 }
6066
6067 /**
6068 * @brief Disable the DMA channel secure attribute.
6069 * @note This API is used for all available DMA channels.
6070 * @rmtoll SECCFGR SECx LL_DMA_DisableChannelSecure
6071 * @param DMAx DMAx Instance
6072 * @param Channel This parameter can be one of the following values:
6073 * @arg @ref LL_DMA_CHANNEL_0
6074 * @arg @ref LL_DMA_CHANNEL_1
6075 * @arg @ref LL_DMA_CHANNEL_2
6076 * @arg @ref LL_DMA_CHANNEL_3
6077 * @arg @ref LL_DMA_CHANNEL_4
6078 * @arg @ref LL_DMA_CHANNEL_5
6079 * @arg @ref LL_DMA_CHANNEL_6
6080 * @arg @ref LL_DMA_CHANNEL_7
6081 * @arg @ref LL_DMA_CHANNEL_8
6082 * @arg @ref LL_DMA_CHANNEL_9
6083 * @arg @ref LL_DMA_CHANNEL_10
6084 * @arg @ref LL_DMA_CHANNEL_11
6085 * @arg @ref LL_DMA_CHANNEL_12
6086 * @arg @ref LL_DMA_CHANNEL_13
6087 * @arg @ref LL_DMA_CHANNEL_14
6088 * @arg @ref LL_DMA_CHANNEL_15
6089 * @retval None.
6090 */
LL_DMA_DisableChannelSecure(DMA_TypeDef * DMAx,uint32_t Channel)6091 __STATIC_INLINE void LL_DMA_DisableChannelSecure(DMA_TypeDef *DMAx, uint32_t Channel)
6092 {
6093 CLEAR_BIT(DMAx->SECCFGR, (DMA_SECCFGR_SEC0 << (Channel & 0x0000000FU)));
6094 }
6095
6096 /**
6097 * @brief Check if DMA channel secure is enabled.
6098 * @note This API is used for all available DMA channels.
6099 * @rmtoll SECCFGR SECx LL_DMA_IsEnabledChannelSecure
6100 * @param DMAx DMAx Instance
6101 * @param Channel This parameter can be one of the following values:
6102 * @arg @ref LL_DMA_CHANNEL_0
6103 * @arg @ref LL_DMA_CHANNEL_1
6104 * @arg @ref LL_DMA_CHANNEL_2
6105 * @arg @ref LL_DMA_CHANNEL_3
6106 * @arg @ref LL_DMA_CHANNEL_4
6107 * @arg @ref LL_DMA_CHANNEL_5
6108 * @arg @ref LL_DMA_CHANNEL_6
6109 * @arg @ref LL_DMA_CHANNEL_7
6110 * @arg @ref LL_DMA_CHANNEL_8
6111 * @arg @ref LL_DMA_CHANNEL_9
6112 * @arg @ref LL_DMA_CHANNEL_10
6113 * @arg @ref LL_DMA_CHANNEL_11
6114 * @arg @ref LL_DMA_CHANNEL_12
6115 * @arg @ref LL_DMA_CHANNEL_13
6116 * @arg @ref LL_DMA_CHANNEL_14
6117 * @arg @ref LL_DMA_CHANNEL_15
6118 * @retval State of bit (1 or 0).
6119 */
LL_DMA_IsEnabledChannelSecure(DMA_TypeDef * DMAx,uint32_t Channel)6120 __STATIC_INLINE uint32_t LL_DMA_IsEnabledChannelSecure(DMA_TypeDef *DMAx, uint32_t Channel)
6121 {
6122 return ((READ_BIT(DMAx->SECCFGR, (DMA_SECCFGR_SEC0 << (Channel & 0x0000000FU)))
6123 == (DMA_SECCFGR_SEC0 << (Channel & 0x0000000FU))) ? 1UL : 0UL);
6124 }
6125 #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
6126
6127 /**
6128 * @brief Enable the DMA channel privilege attribute.
6129 * @note This API is used for all available DMA channels.
6130 * @rmtoll PRIVCFGR PRIVx LL_DMA_EnableChannelPrivilege
6131 * @param DMAx DMAx Instance
6132 * @param Channel This parameter can be one of the following values:
6133 * @arg @ref LL_DMA_CHANNEL_0
6134 * @arg @ref LL_DMA_CHANNEL_1
6135 * @arg @ref LL_DMA_CHANNEL_2
6136 * @arg @ref LL_DMA_CHANNEL_3
6137 * @arg @ref LL_DMA_CHANNEL_4
6138 * @arg @ref LL_DMA_CHANNEL_5
6139 * @arg @ref LL_DMA_CHANNEL_6
6140 * @arg @ref LL_DMA_CHANNEL_7
6141 * @arg @ref LL_DMA_CHANNEL_8
6142 * @arg @ref LL_DMA_CHANNEL_9
6143 * @arg @ref LL_DMA_CHANNEL_10
6144 * @arg @ref LL_DMA_CHANNEL_11
6145 * @arg @ref LL_DMA_CHANNEL_12
6146 * @arg @ref LL_DMA_CHANNEL_13
6147 * @arg @ref LL_DMA_CHANNEL_14
6148 * @arg @ref LL_DMA_CHANNEL_15
6149 * @retval None.
6150 */
LL_DMA_EnableChannelPrivilege(DMA_TypeDef * DMAx,uint32_t Channel)6151 __STATIC_INLINE void LL_DMA_EnableChannelPrivilege(DMA_TypeDef *DMAx, uint32_t Channel)
6152 {
6153 SET_BIT(DMAx->PRIVCFGR, (DMA_PRIVCFGR_PRIV0 << (Channel & 0x0000000FU)));
6154 }
6155
6156 /**
6157 * @brief Disable the DMA channel privilege attribute.
6158 * @note This API is used for all available DMA channels.
6159 * @rmtoll PRIVCFGR PRIVx LL_DMA_DisableChannelPrivilege
6160 * @param DMAx DMAx Instance
6161 * @param Channel This parameter can be one of the following values:
6162 * @arg @ref LL_DMA_CHANNEL_0
6163 * @arg @ref LL_DMA_CHANNEL_1
6164 * @arg @ref LL_DMA_CHANNEL_2
6165 * @arg @ref LL_DMA_CHANNEL_3
6166 * @arg @ref LL_DMA_CHANNEL_4
6167 * @arg @ref LL_DMA_CHANNEL_5
6168 * @arg @ref LL_DMA_CHANNEL_6
6169 * @arg @ref LL_DMA_CHANNEL_7
6170 * @arg @ref LL_DMA_CHANNEL_8
6171 * @arg @ref LL_DMA_CHANNEL_9
6172 * @arg @ref LL_DMA_CHANNEL_10
6173 * @arg @ref LL_DMA_CHANNEL_11
6174 * @arg @ref LL_DMA_CHANNEL_12
6175 * @arg @ref LL_DMA_CHANNEL_13
6176 * @arg @ref LL_DMA_CHANNEL_14
6177 * @arg @ref LL_DMA_CHANNEL_15
6178 * @retval None.
6179 */
LL_DMA_DisableChannelPrivilege(DMA_TypeDef * DMAx,uint32_t Channel)6180 __STATIC_INLINE void LL_DMA_DisableChannelPrivilege(DMA_TypeDef *DMAx, uint32_t Channel)
6181 {
6182 CLEAR_BIT(DMAx->PRIVCFGR, (DMA_PRIVCFGR_PRIV0 << (Channel & 0x0000000FU)));
6183 }
6184
6185 /**
6186 * @brief Check if DMA Channel privilege is enabled.
6187 * @note This API is used for all available DMA channels.
6188 * @rmtoll PRIVCFGR PRIVx LL_DMA_IsEnabledChannelPrivilege
6189 * @param DMAx DMAx Instance
6190 * @param Channel This parameter can be one of the following values:
6191 * @arg @ref LL_DMA_CHANNEL_0
6192 * @arg @ref LL_DMA_CHANNEL_1
6193 * @arg @ref LL_DMA_CHANNEL_2
6194 * @arg @ref LL_DMA_CHANNEL_3
6195 * @arg @ref LL_DMA_CHANNEL_4
6196 * @arg @ref LL_DMA_CHANNEL_5
6197 * @arg @ref LL_DMA_CHANNEL_6
6198 * @arg @ref LL_DMA_CHANNEL_7
6199 * @arg @ref LL_DMA_CHANNEL_8
6200 * @arg @ref LL_DMA_CHANNEL_9
6201 * @arg @ref LL_DMA_CHANNEL_10
6202 * @arg @ref LL_DMA_CHANNEL_11
6203 * @arg @ref LL_DMA_CHANNEL_12
6204 * @arg @ref LL_DMA_CHANNEL_13
6205 * @arg @ref LL_DMA_CHANNEL_14
6206 * @arg @ref LL_DMA_CHANNEL_15
6207 * @retval State of bit (1 or 0).
6208 */
LL_DMA_IsEnabledChannelPrivilege(DMA_TypeDef * DMAx,uint32_t Channel)6209 __STATIC_INLINE uint32_t LL_DMA_IsEnabledChannelPrivilege(DMA_TypeDef *DMAx, uint32_t Channel)
6210 {
6211 return ((READ_BIT(DMAx->PRIVCFGR, (DMA_PRIVCFGR_PRIV0 << (Channel & 0x0000000FU)))
6212 == (DMA_PRIVCFGR_PRIV0 << (Channel & 0x0000000FU))) ? 1UL : 0UL);
6213 }
6214
6215 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
6216 /**
6217 * @brief Enable the DMA channel lock attributes.
6218 * @note This API is used for all available DMA channels.
6219 * @rmtoll RCFGLOCKR LOCKx LL_DMA_EnableChannelLockAttribute
6220 * @param DMAx DMAx Instance
6221 * @param Channel This parameter can be one of the following values:
6222 * @arg @ref LL_DMA_CHANNEL_0
6223 * @arg @ref LL_DMA_CHANNEL_1
6224 * @arg @ref LL_DMA_CHANNEL_2
6225 * @arg @ref LL_DMA_CHANNEL_3
6226 * @arg @ref LL_DMA_CHANNEL_4
6227 * @arg @ref LL_DMA_CHANNEL_5
6228 * @arg @ref LL_DMA_CHANNEL_6
6229 * @arg @ref LL_DMA_CHANNEL_7
6230 * @arg @ref LL_DMA_CHANNEL_8
6231 * @arg @ref LL_DMA_CHANNEL_9
6232 * @arg @ref LL_DMA_CHANNEL_10
6233 * @arg @ref LL_DMA_CHANNEL_11
6234 * @arg @ref LL_DMA_CHANNEL_12
6235 * @arg @ref LL_DMA_CHANNEL_13
6236 * @arg @ref LL_DMA_CHANNEL_14
6237 * @arg @ref LL_DMA_CHANNEL_15
6238 * @retval None.
6239 */
LL_DMA_EnableChannelLockAttribute(DMA_TypeDef * DMAx,uint32_t Channel)6240 __STATIC_INLINE void LL_DMA_EnableChannelLockAttribute(DMA_TypeDef *DMAx, uint32_t Channel)
6241 {
6242 SET_BIT(DMAx->RCFGLOCKR, (DMA_RCFGLOCKR_LOCK0 << (Channel & 0x0000000FU)));
6243 }
6244
6245 /**
6246 * @brief Check if DMA channel attributes are locked.
6247 * @note This API is used for all available DMA channels.
6248 * @rmtoll SECCFGR LOCKx LL_DMA_IsEnabledChannelLockAttribute
6249 * @param DMAx DMAx Instance
6250 * @param Channel This parameter can be one of the following values:
6251 * @arg @ref LL_DMA_CHANNEL_0
6252 * @arg @ref LL_DMA_CHANNEL_1
6253 * @arg @ref LL_DMA_CHANNEL_2
6254 * @arg @ref LL_DMA_CHANNEL_3
6255 * @arg @ref LL_DMA_CHANNEL_4
6256 * @arg @ref LL_DMA_CHANNEL_5
6257 * @arg @ref LL_DMA_CHANNEL_6
6258 * @arg @ref LL_DMA_CHANNEL_7
6259 * @arg @ref LL_DMA_CHANNEL_8
6260 * @arg @ref LL_DMA_CHANNEL_9
6261 * @arg @ref LL_DMA_CHANNEL_10
6262 * @arg @ref LL_DMA_CHANNEL_11
6263 * @arg @ref LL_DMA_CHANNEL_12
6264 * @arg @ref LL_DMA_CHANNEL_13
6265 * @arg @ref LL_DMA_CHANNEL_14
6266 * @arg @ref LL_DMA_CHANNEL_15
6267 * @retval State of bit (1 or 0).
6268 */
LL_DMA_IsEnabledChannelLockAttribute(DMA_TypeDef * DMAx,uint32_t Channel)6269 __STATIC_INLINE uint32_t LL_DMA_IsEnabledChannelLockAttribute(DMA_TypeDef *DMAx, uint32_t Channel)
6270 {
6271 return ((READ_BIT(DMAx->RCFGLOCKR, (DMA_RCFGLOCKR_LOCK0 << (Channel & 0x0000000FU)))
6272 == (DMA_RCFGLOCKR_LOCK0 << (Channel & 0x0000000FU))) ? 1UL : 0UL);
6273 }
6274 #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
6275 /**
6276 * @}
6277 */
6278
6279 /** @defgroup DMA_LL_EF_FLAG_Management Flag Management
6280 * @{
6281 */
6282
6283 /**
6284 * @brief Clear trigger overrun flag.
6285 * @note This API is used for all available DMA channels.
6286 * @rmtoll CFCR TOF LL_DMA_ClearFlag_TO
6287 * @param DMAx DMAx Instance
6288 * @param Channel This parameter can be one of the following values:
6289 * @arg @ref LL_DMA_CHANNEL_0
6290 * @arg @ref LL_DMA_CHANNEL_1
6291 * @arg @ref LL_DMA_CHANNEL_2
6292 * @arg @ref LL_DMA_CHANNEL_3
6293 * @arg @ref LL_DMA_CHANNEL_4
6294 * @arg @ref LL_DMA_CHANNEL_5
6295 * @arg @ref LL_DMA_CHANNEL_6
6296 * @arg @ref LL_DMA_CHANNEL_7
6297 * @arg @ref LL_DMA_CHANNEL_8
6298 * @arg @ref LL_DMA_CHANNEL_9
6299 * @arg @ref LL_DMA_CHANNEL_10
6300 * @arg @ref LL_DMA_CHANNEL_11
6301 * @arg @ref LL_DMA_CHANNEL_12
6302 * @arg @ref LL_DMA_CHANNEL_13
6303 * @arg @ref LL_DMA_CHANNEL_14
6304 * @arg @ref LL_DMA_CHANNEL_15
6305 * @retval None.
6306 */
LL_DMA_ClearFlag_TO(DMA_TypeDef * DMAx,uint32_t Channel)6307 __STATIC_INLINE void LL_DMA_ClearFlag_TO(DMA_TypeDef *DMAx, uint32_t Channel)
6308 {
6309 uint32_t dma_base_addr = (uint32_t)DMAx;
6310 WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CFCR, DMA_CFCR_TOF);
6311 }
6312
6313 /**
6314 * @brief Clear suspension flag.
6315 * @note This API is used for all available DMA channels.
6316 * @rmtoll CFCR SUSPF LL_DMA_ClearFlag_SUSP
6317 * @param DMAx DMAx Instance
6318 * @param Channel This parameter can be one of the following values:
6319 * @arg @ref LL_DMA_CHANNEL_0
6320 * @arg @ref LL_DMA_CHANNEL_1
6321 * @arg @ref LL_DMA_CHANNEL_2
6322 * @arg @ref LL_DMA_CHANNEL_3
6323 * @arg @ref LL_DMA_CHANNEL_4
6324 * @arg @ref LL_DMA_CHANNEL_5
6325 * @arg @ref LL_DMA_CHANNEL_6
6326 * @arg @ref LL_DMA_CHANNEL_7
6327 * @arg @ref LL_DMA_CHANNEL_8
6328 * @arg @ref LL_DMA_CHANNEL_9
6329 * @arg @ref LL_DMA_CHANNEL_10
6330 * @arg @ref LL_DMA_CHANNEL_11
6331 * @arg @ref LL_DMA_CHANNEL_12
6332 * @arg @ref LL_DMA_CHANNEL_13
6333 * @arg @ref LL_DMA_CHANNEL_14
6334 * @arg @ref LL_DMA_CHANNEL_15
6335 * @retval None.
6336 */
LL_DMA_ClearFlag_SUSP(DMA_TypeDef * DMAx,uint32_t Channel)6337 __STATIC_INLINE void LL_DMA_ClearFlag_SUSP(DMA_TypeDef *DMAx, uint32_t Channel)
6338 {
6339 uint32_t dma_base_addr = (uint32_t)DMAx;
6340 WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CFCR, DMA_CFCR_SUSPF);
6341 }
6342
6343 /**
6344 * @brief Clear user setting error flag.
6345 * @note This API is used for all available DMA channels.
6346 * @rmtoll CFCR USEF LL_DMA_ClearFlag_USE
6347 * @param DMAx DMAx Instance
6348 * @param Channel This parameter can be one of the following values:
6349 * @arg @ref LL_DMA_CHANNEL_0
6350 * @arg @ref LL_DMA_CHANNEL_1
6351 * @arg @ref LL_DMA_CHANNEL_2
6352 * @arg @ref LL_DMA_CHANNEL_3
6353 * @arg @ref LL_DMA_CHANNEL_4
6354 * @arg @ref LL_DMA_CHANNEL_5
6355 * @arg @ref LL_DMA_CHANNEL_6
6356 * @arg @ref LL_DMA_CHANNEL_7
6357 * @arg @ref LL_DMA_CHANNEL_8
6358 * @arg @ref LL_DMA_CHANNEL_9
6359 * @arg @ref LL_DMA_CHANNEL_10
6360 * @arg @ref LL_DMA_CHANNEL_11
6361 * @arg @ref LL_DMA_CHANNEL_12
6362 * @arg @ref LL_DMA_CHANNEL_13
6363 * @arg @ref LL_DMA_CHANNEL_14
6364 * @arg @ref LL_DMA_CHANNEL_15
6365 * @retval None.
6366 */
LL_DMA_ClearFlag_USE(DMA_TypeDef * DMAx,uint32_t Channel)6367 __STATIC_INLINE void LL_DMA_ClearFlag_USE(DMA_TypeDef *DMAx, uint32_t Channel)
6368 {
6369 uint32_t dma_base_addr = (uint32_t)DMAx;
6370 WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CFCR, DMA_CFCR_USEF);
6371 }
6372
6373 /**
6374 * @brief Clear link transfer error flag.
6375 * @note This API is used for all available DMA channels.
6376 * @rmtoll CFCR ULEF LL_DMA_ClearFlag_ULE
6377 * @param DMAx DMAx Instance
6378 * @param Channel This parameter can be one of the following values:
6379 * @arg @ref LL_DMA_CHANNEL_0
6380 * @arg @ref LL_DMA_CHANNEL_1
6381 * @arg @ref LL_DMA_CHANNEL_2
6382 * @arg @ref LL_DMA_CHANNEL_3
6383 * @arg @ref LL_DMA_CHANNEL_4
6384 * @arg @ref LL_DMA_CHANNEL_5
6385 * @arg @ref LL_DMA_CHANNEL_6
6386 * @arg @ref LL_DMA_CHANNEL_7
6387 * @arg @ref LL_DMA_CHANNEL_8
6388 * @arg @ref LL_DMA_CHANNEL_9
6389 * @arg @ref LL_DMA_CHANNEL_10
6390 * @arg @ref LL_DMA_CHANNEL_11
6391 * @arg @ref LL_DMA_CHANNEL_12
6392 * @arg @ref LL_DMA_CHANNEL_13
6393 * @arg @ref LL_DMA_CHANNEL_14
6394 * @arg @ref LL_DMA_CHANNEL_15
6395 * @retval None.
6396 */
LL_DMA_ClearFlag_ULE(DMA_TypeDef * DMAx,uint32_t Channel)6397 __STATIC_INLINE void LL_DMA_ClearFlag_ULE(DMA_TypeDef *DMAx, uint32_t Channel)
6398 {
6399 uint32_t dma_base_addr = (uint32_t)DMAx;
6400 WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CFCR, DMA_CFCR_ULEF);
6401 }
6402
6403 /**
6404 * @brief Clear data transfer error flag.
6405 * @note This API is used for all available DMA channels.
6406 * @rmtoll CFCR DTEF LL_DMA_ClearFlag_DTE
6407 * @param DMAx DMAx Instance
6408 * @param Channel This parameter can be one of the following values:
6409 * @arg @ref LL_DMA_CHANNEL_0
6410 * @arg @ref LL_DMA_CHANNEL_1
6411 * @arg @ref LL_DMA_CHANNEL_2
6412 * @arg @ref LL_DMA_CHANNEL_3
6413 * @arg @ref LL_DMA_CHANNEL_4
6414 * @arg @ref LL_DMA_CHANNEL_5
6415 * @arg @ref LL_DMA_CHANNEL_6
6416 * @arg @ref LL_DMA_CHANNEL_7
6417 * @arg @ref LL_DMA_CHANNEL_8
6418 * @arg @ref LL_DMA_CHANNEL_9
6419 * @arg @ref LL_DMA_CHANNEL_10
6420 * @arg @ref LL_DMA_CHANNEL_11
6421 * @arg @ref LL_DMA_CHANNEL_12
6422 * @arg @ref LL_DMA_CHANNEL_13
6423 * @arg @ref LL_DMA_CHANNEL_14
6424 * @arg @ref LL_DMA_CHANNEL_15
6425 * @retval None.
6426 */
LL_DMA_ClearFlag_DTE(DMA_TypeDef * DMAx,uint32_t Channel)6427 __STATIC_INLINE void LL_DMA_ClearFlag_DTE(DMA_TypeDef *DMAx, uint32_t Channel)
6428 {
6429 uint32_t dma_base_addr = (uint32_t)DMAx;
6430 WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CFCR, DMA_CFCR_DTEF);
6431 }
6432
6433 /**
6434 * @brief Clear half transfer flag.
6435 * @note This API is used for all available DMA channels.
6436 * @rmtoll CFCR HTF LL_DMA_ClearFlag_HT
6437 * @param DMAx DMAx Instance
6438 * @param Channel This parameter can be one of the following values:
6439 * @arg @ref LL_DMA_CHANNEL_0
6440 * @arg @ref LL_DMA_CHANNEL_1
6441 * @arg @ref LL_DMA_CHANNEL_2
6442 * @arg @ref LL_DMA_CHANNEL_3
6443 * @arg @ref LL_DMA_CHANNEL_4
6444 * @arg @ref LL_DMA_CHANNEL_5
6445 * @arg @ref LL_DMA_CHANNEL_6
6446 * @arg @ref LL_DMA_CHANNEL_7
6447 * @arg @ref LL_DMA_CHANNEL_8
6448 * @arg @ref LL_DMA_CHANNEL_9
6449 * @arg @ref LL_DMA_CHANNEL_10
6450 * @arg @ref LL_DMA_CHANNEL_11
6451 * @arg @ref LL_DMA_CHANNEL_12
6452 * @arg @ref LL_DMA_CHANNEL_13
6453 * @arg @ref LL_DMA_CHANNEL_14
6454 * @arg @ref LL_DMA_CHANNEL_15
6455 * @retval None.
6456 */
LL_DMA_ClearFlag_HT(DMA_TypeDef * DMAx,uint32_t Channel)6457 __STATIC_INLINE void LL_DMA_ClearFlag_HT(DMA_TypeDef *DMAx, uint32_t Channel)
6458 {
6459 uint32_t dma_base_addr = (uint32_t)DMAx;
6460 WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CFCR, DMA_CFCR_HTF);
6461 }
6462
6463 /**
6464 * @brief Clear transfer complete flag.
6465 * @note This API is used for all available DMA channels.
6466 * @rmtoll CFCR TCF LL_DMA_ClearFlag_TC
6467 * @param DMAx DMAx Instance
6468 * @param Channel This parameter can be one of the following values:
6469 * @arg @ref LL_DMA_CHANNEL_0
6470 * @arg @ref LL_DMA_CHANNEL_1
6471 * @arg @ref LL_DMA_CHANNEL_2
6472 * @arg @ref LL_DMA_CHANNEL_3
6473 * @arg @ref LL_DMA_CHANNEL_4
6474 * @arg @ref LL_DMA_CHANNEL_5
6475 * @arg @ref LL_DMA_CHANNEL_6
6476 * @arg @ref LL_DMA_CHANNEL_7
6477 * @arg @ref LL_DMA_CHANNEL_8
6478 * @arg @ref LL_DMA_CHANNEL_9
6479 * @arg @ref LL_DMA_CHANNEL_10
6480 * @arg @ref LL_DMA_CHANNEL_11
6481 * @arg @ref LL_DMA_CHANNEL_12
6482 * @arg @ref LL_DMA_CHANNEL_13
6483 * @arg @ref LL_DMA_CHANNEL_14
6484 * @arg @ref LL_DMA_CHANNEL_15
6485 * @retval None.
6486 */
LL_DMA_ClearFlag_TC(DMA_TypeDef * DMAx,uint32_t Channel)6487 __STATIC_INLINE void LL_DMA_ClearFlag_TC(DMA_TypeDef *DMAx, uint32_t Channel)
6488 {
6489 uint32_t dma_base_addr = (uint32_t)DMAx;
6490 WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CFCR, DMA_CFCR_TCF);
6491 }
6492
6493 /**
6494 * @brief Get trigger overrun flag.
6495 * @note This API is used for all available DMA channels.
6496 * @rmtoll CSR TOF LL_DMA_IsActiveFlag_TO
6497 * @param DMAx DMAx Instance
6498 * @param Channel This parameter can be one of the following values:
6499 * @arg @ref LL_DMA_CHANNEL_0
6500 * @arg @ref LL_DMA_CHANNEL_1
6501 * @arg @ref LL_DMA_CHANNEL_2
6502 * @arg @ref LL_DMA_CHANNEL_3
6503 * @arg @ref LL_DMA_CHANNEL_4
6504 * @arg @ref LL_DMA_CHANNEL_5
6505 * @arg @ref LL_DMA_CHANNEL_6
6506 * @arg @ref LL_DMA_CHANNEL_7
6507 * @arg @ref LL_DMA_CHANNEL_8
6508 * @arg @ref LL_DMA_CHANNEL_9
6509 * @arg @ref LL_DMA_CHANNEL_10
6510 * @arg @ref LL_DMA_CHANNEL_11
6511 * @arg @ref LL_DMA_CHANNEL_12
6512 * @arg @ref LL_DMA_CHANNEL_13
6513 * @arg @ref LL_DMA_CHANNEL_14
6514 * @arg @ref LL_DMA_CHANNEL_15
6515 * @retval State of bit (1 or 0).
6516 */
LL_DMA_IsActiveFlag_TO(DMA_TypeDef * DMAx,uint32_t Channel)6517 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TO(DMA_TypeDef *DMAx, uint32_t Channel)
6518 {
6519 uint32_t dma_base_addr = (uint32_t)DMAx;
6520 return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CSR, DMA_CSR_TOF)
6521 == (DMA_CSR_TOF)) ? 1UL : 0UL);
6522 }
6523
6524 /**
6525 * @brief Get suspension flag.
6526 * @note This API is used for all available DMA channels.
6527 * @rmtoll CSR SUSPF LL_DMA_IsActiveFlag_SUSP
6528 * @param DMAx DMAx Instance
6529 * @param Channel This parameter can be one of the following values:
6530 * @arg @ref LL_DMA_CHANNEL_0
6531 * @arg @ref LL_DMA_CHANNEL_1
6532 * @arg @ref LL_DMA_CHANNEL_2
6533 * @arg @ref LL_DMA_CHANNEL_3
6534 * @arg @ref LL_DMA_CHANNEL_4
6535 * @arg @ref LL_DMA_CHANNEL_5
6536 * @arg @ref LL_DMA_CHANNEL_6
6537 * @arg @ref LL_DMA_CHANNEL_7
6538 * @arg @ref LL_DMA_CHANNEL_8
6539 * @arg @ref LL_DMA_CHANNEL_9
6540 * @arg @ref LL_DMA_CHANNEL_10
6541 * @arg @ref LL_DMA_CHANNEL_11
6542 * @arg @ref LL_DMA_CHANNEL_12
6543 * @arg @ref LL_DMA_CHANNEL_13
6544 * @arg @ref LL_DMA_CHANNEL_14
6545 * @arg @ref LL_DMA_CHANNEL_15
6546 * @retval State of bit (1 or 0).
6547 */
LL_DMA_IsActiveFlag_SUSP(DMA_TypeDef * DMAx,uint32_t Channel)6548 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_SUSP(DMA_TypeDef *DMAx, uint32_t Channel)
6549 {
6550 uint32_t dma_base_addr = (uint32_t)DMAx;
6551 return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CSR, DMA_CSR_SUSPF)
6552 == (DMA_CSR_SUSPF)) ? 1UL : 0UL);
6553 }
6554
6555 /**
6556 * @brief Get user setting error flag.
6557 * @note This API is used for all available DMA channels.
6558 * @rmtoll CSR USEF LL_DMA_IsActiveFlag_USE
6559 * @param DMAx DMAx Instance
6560 * @param Channel This parameter can be one of the following values:
6561 * @arg @ref LL_DMA_CHANNEL_0
6562 * @arg @ref LL_DMA_CHANNEL_1
6563 * @arg @ref LL_DMA_CHANNEL_2
6564 * @arg @ref LL_DMA_CHANNEL_3
6565 * @arg @ref LL_DMA_CHANNEL_4
6566 * @arg @ref LL_DMA_CHANNEL_5
6567 * @arg @ref LL_DMA_CHANNEL_6
6568 * @arg @ref LL_DMA_CHANNEL_7
6569 * @arg @ref LL_DMA_CHANNEL_8
6570 * @arg @ref LL_DMA_CHANNEL_9
6571 * @arg @ref LL_DMA_CHANNEL_10
6572 * @arg @ref LL_DMA_CHANNEL_11
6573 * @arg @ref LL_DMA_CHANNEL_12
6574 * @arg @ref LL_DMA_CHANNEL_13
6575 * @arg @ref LL_DMA_CHANNEL_14
6576 * @arg @ref LL_DMA_CHANNEL_15
6577 * @retval State of bit (1 or 0).
6578 */
LL_DMA_IsActiveFlag_USE(DMA_TypeDef * DMAx,uint32_t Channel)6579 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_USE(DMA_TypeDef *DMAx, uint32_t Channel)
6580 {
6581 uint32_t dma_base_addr = (uint32_t)DMAx;
6582 return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CSR, DMA_CSR_USEF)
6583 == (DMA_CSR_USEF)) ? 1UL : 0UL);
6584 }
6585
6586 /**
6587 * @brief Get user setting error flag.
6588 * @note This API is used for all available DMA channels.
6589 * @rmtoll CSR ULEF LL_DMA_IsActiveFlag_ULE
6590 * @param DMAx DMAx Instance
6591 * @param Channel This parameter can be one of the following values:
6592 * @arg @ref LL_DMA_CHANNEL_0
6593 * @arg @ref LL_DMA_CHANNEL_1
6594 * @arg @ref LL_DMA_CHANNEL_2
6595 * @arg @ref LL_DMA_CHANNEL_3
6596 * @arg @ref LL_DMA_CHANNEL_4
6597 * @arg @ref LL_DMA_CHANNEL_5
6598 * @arg @ref LL_DMA_CHANNEL_6
6599 * @arg @ref LL_DMA_CHANNEL_7
6600 * @arg @ref LL_DMA_CHANNEL_8
6601 * @arg @ref LL_DMA_CHANNEL_9
6602 * @arg @ref LL_DMA_CHANNEL_10
6603 * @arg @ref LL_DMA_CHANNEL_11
6604 * @arg @ref LL_DMA_CHANNEL_12
6605 * @arg @ref LL_DMA_CHANNEL_13
6606 * @arg @ref LL_DMA_CHANNEL_14
6607 * @arg @ref LL_DMA_CHANNEL_15
6608 * @retval State of bit (1 or 0).
6609 */
LL_DMA_IsActiveFlag_ULE(DMA_TypeDef * DMAx,uint32_t Channel)6610 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_ULE(DMA_TypeDef *DMAx, uint32_t Channel)
6611 {
6612 uint32_t dma_base_addr = (uint32_t)DMAx;
6613 return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CSR, DMA_CSR_ULEF)
6614 == (DMA_CSR_ULEF)) ? 1UL : 0UL);
6615 }
6616
6617 /**
6618 * @brief Get data transfer error flag.
6619 * @note This API is used for all available DMA channels.
6620 * @rmtoll CSR DTEF LL_DMA_IsActiveFlag_DTE
6621 * @param DMAx DMAx Instance
6622 * @param DMAx DMAx Instance
6623 * @param Channel This parameter can be one of the following values:
6624 * @arg @ref LL_DMA_CHANNEL_0
6625 * @arg @ref LL_DMA_CHANNEL_1
6626 * @arg @ref LL_DMA_CHANNEL_2
6627 * @arg @ref LL_DMA_CHANNEL_3
6628 * @arg @ref LL_DMA_CHANNEL_4
6629 * @arg @ref LL_DMA_CHANNEL_5
6630 * @arg @ref LL_DMA_CHANNEL_6
6631 * @arg @ref LL_DMA_CHANNEL_7
6632 * @arg @ref LL_DMA_CHANNEL_8
6633 * @arg @ref LL_DMA_CHANNEL_9
6634 * @arg @ref LL_DMA_CHANNEL_10
6635 * @arg @ref LL_DMA_CHANNEL_11
6636 * @arg @ref LL_DMA_CHANNEL_12
6637 * @arg @ref LL_DMA_CHANNEL_13
6638 * @arg @ref LL_DMA_CHANNEL_14
6639 * @arg @ref LL_DMA_CHANNEL_15
6640 * @retval State of bit (1 or 0).
6641 */
LL_DMA_IsActiveFlag_DTE(DMA_TypeDef * DMAx,uint32_t Channel)6642 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DTE(DMA_TypeDef *DMAx, uint32_t Channel)
6643 {
6644 uint32_t dma_base_addr = (uint32_t)DMAx;
6645 return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CSR, DMA_CSR_DTEF)
6646 == (DMA_CSR_DTEF)) ? 1UL : 0UL);
6647 }
6648
6649 /**
6650 * @brief Get half transfer flag.
6651 * @note This API is used for all available DMA channels.
6652 * @rmtoll CSR HTF LL_DMA_IsActiveFlag_HT
6653 * @param DMAx DMAx Instance
6654 * @param Channel This parameter can be one of the following values:
6655 * @arg @ref LL_DMA_CHANNEL_0
6656 * @arg @ref LL_DMA_CHANNEL_1
6657 * @arg @ref LL_DMA_CHANNEL_2
6658 * @arg @ref LL_DMA_CHANNEL_3
6659 * @arg @ref LL_DMA_CHANNEL_4
6660 * @arg @ref LL_DMA_CHANNEL_5
6661 * @arg @ref LL_DMA_CHANNEL_6
6662 * @arg @ref LL_DMA_CHANNEL_7
6663 * @arg @ref LL_DMA_CHANNEL_8
6664 * @arg @ref LL_DMA_CHANNEL_9
6665 * @arg @ref LL_DMA_CHANNEL_10
6666 * @arg @ref LL_DMA_CHANNEL_11
6667 * @arg @ref LL_DMA_CHANNEL_12
6668 * @arg @ref LL_DMA_CHANNEL_13
6669 * @arg @ref LL_DMA_CHANNEL_14
6670 * @arg @ref LL_DMA_CHANNEL_15
6671 * @retval State of bit (1 or 0).
6672 */
LL_DMA_IsActiveFlag_HT(DMA_TypeDef * DMAx,uint32_t Channel)6673 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT(DMA_TypeDef *DMAx, uint32_t Channel)
6674 {
6675 uint32_t dma_base_addr = (uint32_t)DMAx;
6676 return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CSR, DMA_CSR_HTF)
6677 == (DMA_CSR_HTF)) ? 1UL : 0UL);
6678 }
6679
6680 /**
6681 * @brief Get transfer complete flag.
6682 * @note This API is used for all available DMA channels.
6683 * @rmtoll CSR TCF LL_DMA_IsActiveFlag_TC
6684 * @param DMAx DMAx Instance
6685 * @param Channel This parameter can be one of the following values:
6686 * @arg @ref LL_DMA_CHANNEL_0
6687 * @arg @ref LL_DMA_CHANNEL_1
6688 * @arg @ref LL_DMA_CHANNEL_2
6689 * @arg @ref LL_DMA_CHANNEL_3
6690 * @arg @ref LL_DMA_CHANNEL_4
6691 * @arg @ref LL_DMA_CHANNEL_5
6692 * @arg @ref LL_DMA_CHANNEL_6
6693 * @arg @ref LL_DMA_CHANNEL_7
6694 * @arg @ref LL_DMA_CHANNEL_8
6695 * @arg @ref LL_DMA_CHANNEL_9
6696 * @arg @ref LL_DMA_CHANNEL_10
6697 * @arg @ref LL_DMA_CHANNEL_11
6698 * @arg @ref LL_DMA_CHANNEL_12
6699 * @arg @ref LL_DMA_CHANNEL_13
6700 * @arg @ref LL_DMA_CHANNEL_14
6701 * @arg @ref LL_DMA_CHANNEL_15
6702 * @retval State of bit (1 or 0).
6703 */
LL_DMA_IsActiveFlag_TC(DMA_TypeDef * DMAx,uint32_t Channel)6704 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC(DMA_TypeDef *DMAx, uint32_t Channel)
6705 {
6706 uint32_t dma_base_addr = (uint32_t)DMAx;
6707 return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CSR, DMA_CSR_TCF)
6708 == (DMA_CSR_TCF)) ? 1UL : 0UL);
6709 }
6710
6711 /**
6712 * @brief Get idle flag.
6713 * @note This API is used for all available DMA channels.
6714 * @rmtoll CSR IDLEF LL_DMA_IsActiveFlag_IDLE
6715 * @param DMAx DMAx Instance
6716 * @param Channel This parameter can be one of the following values:
6717 * @arg @ref LL_DMA_CHANNEL_0
6718 * @arg @ref LL_DMA_CHANNEL_1
6719 * @arg @ref LL_DMA_CHANNEL_2
6720 * @arg @ref LL_DMA_CHANNEL_3
6721 * @arg @ref LL_DMA_CHANNEL_4
6722 * @arg @ref LL_DMA_CHANNEL_5
6723 * @arg @ref LL_DMA_CHANNEL_6
6724 * @arg @ref LL_DMA_CHANNEL_7
6725 * @arg @ref LL_DMA_CHANNEL_8
6726 * @arg @ref LL_DMA_CHANNEL_9
6727 * @arg @ref LL_DMA_CHANNEL_10
6728 * @arg @ref LL_DMA_CHANNEL_11
6729 * @arg @ref LL_DMA_CHANNEL_12
6730 * @arg @ref LL_DMA_CHANNEL_13
6731 * @arg @ref LL_DMA_CHANNEL_14
6732 * @arg @ref LL_DMA_CHANNEL_15
6733 * @retval State of bit (1 or 0).
6734 */
LL_DMA_IsActiveFlag_IDLE(DMA_TypeDef * DMAx,uint32_t Channel)6735 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_IDLE(DMA_TypeDef *DMAx, uint32_t Channel)
6736 {
6737 uint32_t dma_base_addr = (uint32_t)DMAx;
6738 return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CSR, DMA_CSR_IDLEF)
6739 == (DMA_CSR_IDLEF)) ? 1UL : 0UL);
6740 }
6741
6742 /**
6743 * @brief Check if nsecure masked interrupt is active.
6744 * @note This API is used for all available DMA channels.
6745 * @rmtoll MISR MISx LL_DMA_IsActiveFlag_MIS
6746 * @param DMAx DMAx Instance
6747 * @param Channel This parameter can be one of the following values:
6748 * @arg @ref LL_DMA_CHANNEL_0
6749 * @arg @ref LL_DMA_CHANNEL_1
6750 * @arg @ref LL_DMA_CHANNEL_2
6751 * @arg @ref LL_DMA_CHANNEL_3
6752 * @arg @ref LL_DMA_CHANNEL_4
6753 * @arg @ref LL_DMA_CHANNEL_5
6754 * @arg @ref LL_DMA_CHANNEL_6
6755 * @arg @ref LL_DMA_CHANNEL_7
6756 * @arg @ref LL_DMA_CHANNEL_8
6757 * @arg @ref LL_DMA_CHANNEL_9
6758 * @arg @ref LL_DMA_CHANNEL_10
6759 * @arg @ref LL_DMA_CHANNEL_11
6760 * @arg @ref LL_DMA_CHANNEL_12
6761 * @arg @ref LL_DMA_CHANNEL_13
6762 * @arg @ref LL_DMA_CHANNEL_14
6763 * @arg @ref LL_DMA_CHANNEL_15
6764 * @retval State of bit (1 or 0).
6765 */
LL_DMA_IsActiveFlag_MIS(DMA_TypeDef * DMAx,uint32_t Channel)6766 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_MIS(DMA_TypeDef *DMAx, uint32_t Channel)
6767 {
6768 return ((READ_BIT(DMAx->MISR, (DMA_MISR_MIS0 << (Channel & 0x0FU)))
6769 == (DMA_MISR_MIS0 << (Channel & 0x0FU))) ? 1UL : 0UL);
6770 }
6771
6772 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
6773 /**
6774 * @brief Check if secure masked interrupt is active.
6775 * @note This API is used for all available DMA channels.
6776 * @rmtoll SMISR MISx LL_DMA_IsActiveFlag_SMIS
6777 * @param DMAx DMAx Instance
6778 * @param Channel This parameter can be one of the following values:
6779 * @arg @ref LL_DMA_CHANNEL_0
6780 * @arg @ref LL_DMA_CHANNEL_1
6781 * @arg @ref LL_DMA_CHANNEL_2
6782 * @arg @ref LL_DMA_CHANNEL_3
6783 * @arg @ref LL_DMA_CHANNEL_4
6784 * @arg @ref LL_DMA_CHANNEL_5
6785 * @arg @ref LL_DMA_CHANNEL_6
6786 * @arg @ref LL_DMA_CHANNEL_7
6787 * @arg @ref LL_DMA_CHANNEL_8
6788 * @arg @ref LL_DMA_CHANNEL_9
6789 * @arg @ref LL_DMA_CHANNEL_10
6790 * @arg @ref LL_DMA_CHANNEL_11
6791 * @arg @ref LL_DMA_CHANNEL_12
6792 * @arg @ref LL_DMA_CHANNEL_13
6793 * @arg @ref LL_DMA_CHANNEL_14
6794 * @arg @ref LL_DMA_CHANNEL_15
6795 * @retval State of bit (1 or 0).
6796 */
LL_DMA_IsActiveFlag_SMIS(DMA_TypeDef * DMAx,uint32_t Channel)6797 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_SMIS(DMA_TypeDef *DMAx, uint32_t Channel)
6798 {
6799 return ((READ_BIT(DMAx->SMISR, (DMA_SMISR_MIS0 << (Channel & 0x0000000FU)))
6800 == (DMA_SMISR_MIS0 << (Channel & 0x0000000FU))) ? 1UL : 0UL);
6801 }
6802 #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
6803 /**
6804 * @}
6805 */
6806
6807 /** @defgroup DMA_LL_EF_IT_Management Interrupt Management
6808 * @{
6809 */
6810
6811 /**
6812 * @brief Enable trigger overrun interrupt.
6813 * @note This API is used for all available DMA channels.
6814 * @rmtoll CCR TOIE LL_DMA_EnableIT_TO
6815 * @param DMAx DMAx Instance
6816 * @param Channel This parameter can be one of the following values:
6817 * @arg @ref LL_DMA_CHANNEL_0
6818 * @arg @ref LL_DMA_CHANNEL_1
6819 * @arg @ref LL_DMA_CHANNEL_2
6820 * @arg @ref LL_DMA_CHANNEL_3
6821 * @arg @ref LL_DMA_CHANNEL_4
6822 * @arg @ref LL_DMA_CHANNEL_5
6823 * @arg @ref LL_DMA_CHANNEL_6
6824 * @arg @ref LL_DMA_CHANNEL_7
6825 * @arg @ref LL_DMA_CHANNEL_8
6826 * @arg @ref LL_DMA_CHANNEL_9
6827 * @arg @ref LL_DMA_CHANNEL_10
6828 * @arg @ref LL_DMA_CHANNEL_11
6829 * @arg @ref LL_DMA_CHANNEL_12
6830 * @arg @ref LL_DMA_CHANNEL_13
6831 * @arg @ref LL_DMA_CHANNEL_14
6832 * @arg @ref LL_DMA_CHANNEL_15
6833 * @retval None.
6834 */
LL_DMA_EnableIT_TO(DMA_TypeDef * DMAx,uint32_t Channel)6835 __STATIC_INLINE void LL_DMA_EnableIT_TO(DMA_TypeDef *DMAx, uint32_t Channel)
6836 {
6837 uint32_t dma_base_addr = (uint32_t)DMAx;
6838 SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_TOIE);
6839 }
6840
6841 /**
6842 * @brief Enable suspension interrupt.
6843 * @note This API is used for all available DMA channels.
6844 * @rmtoll CCR SUSPIE LL_DMA_EnableIT_SUSP
6845 * @param DMAx DMAx Instance
6846 * @param Channel This parameter can be one of the following values:
6847 * @arg @ref LL_DMA_CHANNEL_0
6848 * @arg @ref LL_DMA_CHANNEL_1
6849 * @arg @ref LL_DMA_CHANNEL_2
6850 * @arg @ref LL_DMA_CHANNEL_3
6851 * @arg @ref LL_DMA_CHANNEL_4
6852 * @arg @ref LL_DMA_CHANNEL_5
6853 * @arg @ref LL_DMA_CHANNEL_6
6854 * @arg @ref LL_DMA_CHANNEL_7
6855 * @arg @ref LL_DMA_CHANNEL_8
6856 * @arg @ref LL_DMA_CHANNEL_9
6857 * @arg @ref LL_DMA_CHANNEL_10
6858 * @arg @ref LL_DMA_CHANNEL_11
6859 * @arg @ref LL_DMA_CHANNEL_12
6860 * @arg @ref LL_DMA_CHANNEL_13
6861 * @arg @ref LL_DMA_CHANNEL_14
6862 * @arg @ref LL_DMA_CHANNEL_15
6863 * @retval None.
6864 */
LL_DMA_EnableIT_SUSP(DMA_TypeDef * DMAx,uint32_t Channel)6865 __STATIC_INLINE void LL_DMA_EnableIT_SUSP(DMA_TypeDef *DMAx, uint32_t Channel)
6866 {
6867 uint32_t dma_base_addr = (uint32_t)DMAx;
6868 SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_SUSPIE);
6869 }
6870
6871 /**
6872 * @brief Enable user setting error interrupt.
6873 * @note This API is used for all available DMA channels.
6874 * @rmtoll CCR USEIE LL_DMA_EnableIT_USE
6875 * @param DMAx DMAx Instance
6876 * @param Channel This parameter can be one of the following values:
6877 * @arg @ref LL_DMA_CHANNEL_0
6878 * @arg @ref LL_DMA_CHANNEL_1
6879 * @arg @ref LL_DMA_CHANNEL_2
6880 * @arg @ref LL_DMA_CHANNEL_3
6881 * @arg @ref LL_DMA_CHANNEL_4
6882 * @arg @ref LL_DMA_CHANNEL_5
6883 * @arg @ref LL_DMA_CHANNEL_6
6884 * @arg @ref LL_DMA_CHANNEL_7
6885 * @arg @ref LL_DMA_CHANNEL_8
6886 * @arg @ref LL_DMA_CHANNEL_9
6887 * @arg @ref LL_DMA_CHANNEL_10
6888 * @arg @ref LL_DMA_CHANNEL_11
6889 * @arg @ref LL_DMA_CHANNEL_12
6890 * @arg @ref LL_DMA_CHANNEL_13
6891 * @arg @ref LL_DMA_CHANNEL_14
6892 * @arg @ref LL_DMA_CHANNEL_15
6893 * @retval None.
6894 */
LL_DMA_EnableIT_USE(DMA_TypeDef * DMAx,uint32_t Channel)6895 __STATIC_INLINE void LL_DMA_EnableIT_USE(DMA_TypeDef *DMAx, uint32_t Channel)
6896 {
6897 uint32_t dma_base_addr = (uint32_t)DMAx;
6898 SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_USEIE);
6899 }
6900
6901 /**
6902 * @brief Enable update link transfer error interrupt.
6903 * @note This API is used for all available DMA channels.
6904 * @rmtoll CCR ULEIE LL_DMA_EnableIT_ULE
6905 * @param DMAx DMAx Instance
6906 * @param Channel This parameter can be one of the following values:
6907 * @arg @ref LL_DMA_CHANNEL_0
6908 * @arg @ref LL_DMA_CHANNEL_1
6909 * @arg @ref LL_DMA_CHANNEL_2
6910 * @arg @ref LL_DMA_CHANNEL_3
6911 * @arg @ref LL_DMA_CHANNEL_4
6912 * @arg @ref LL_DMA_CHANNEL_5
6913 * @arg @ref LL_DMA_CHANNEL_6
6914 * @arg @ref LL_DMA_CHANNEL_7
6915 * @arg @ref LL_DMA_CHANNEL_8
6916 * @arg @ref LL_DMA_CHANNEL_9
6917 * @arg @ref LL_DMA_CHANNEL_10
6918 * @arg @ref LL_DMA_CHANNEL_11
6919 * @arg @ref LL_DMA_CHANNEL_12
6920 * @arg @ref LL_DMA_CHANNEL_13
6921 * @arg @ref LL_DMA_CHANNEL_14
6922 * @arg @ref LL_DMA_CHANNEL_15
6923 * @retval None.
6924 */
LL_DMA_EnableIT_ULE(DMA_TypeDef * DMAx,uint32_t Channel)6925 __STATIC_INLINE void LL_DMA_EnableIT_ULE(DMA_TypeDef *DMAx, uint32_t Channel)
6926 {
6927 uint32_t dma_base_addr = (uint32_t)DMAx;
6928 SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_ULEIE);
6929 }
6930
6931 /**
6932 * @brief Enable data transfer error interrupt.
6933 * @note This API is used for all available DMA channels.
6934 * @rmtoll CCR DTEIE LL_DMA_EnableIT_DTE
6935 * @param DMAx DMAx Instance
6936 * @param Channel This parameter can be one of the following values:
6937 * @arg @ref LL_DMA_CHANNEL_0
6938 * @arg @ref LL_DMA_CHANNEL_1
6939 * @arg @ref LL_DMA_CHANNEL_2
6940 * @arg @ref LL_DMA_CHANNEL_3
6941 * @arg @ref LL_DMA_CHANNEL_4
6942 * @arg @ref LL_DMA_CHANNEL_5
6943 * @arg @ref LL_DMA_CHANNEL_6
6944 * @arg @ref LL_DMA_CHANNEL_7
6945 * @arg @ref LL_DMA_CHANNEL_8
6946 * @arg @ref LL_DMA_CHANNEL_9
6947 * @arg @ref LL_DMA_CHANNEL_10
6948 * @arg @ref LL_DMA_CHANNEL_11
6949 * @arg @ref LL_DMA_CHANNEL_12
6950 * @arg @ref LL_DMA_CHANNEL_13
6951 * @arg @ref LL_DMA_CHANNEL_14
6952 * @arg @ref LL_DMA_CHANNEL_15
6953 * @retval None.
6954 */
LL_DMA_EnableIT_DTE(DMA_TypeDef * DMAx,uint32_t Channel)6955 __STATIC_INLINE void LL_DMA_EnableIT_DTE(DMA_TypeDef *DMAx, uint32_t Channel)
6956 {
6957 uint32_t dma_base_addr = (uint32_t)DMAx;
6958 SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_DTEIE);
6959 }
6960
6961 /**
6962 * @brief Enable half transfer complete interrupt.
6963 * @note This API is used for all available DMA channels.
6964 * @rmtoll CCR HTIE LL_DMA_EnableIT_HT
6965 * @param DMAx DMAx Instance
6966 * @param Channel This parameter can be one of the following values:
6967 * @arg @ref LL_DMA_CHANNEL_0
6968 * @arg @ref LL_DMA_CHANNEL_1
6969 * @arg @ref LL_DMA_CHANNEL_2
6970 * @arg @ref LL_DMA_CHANNEL_3
6971 * @arg @ref LL_DMA_CHANNEL_4
6972 * @arg @ref LL_DMA_CHANNEL_5
6973 * @arg @ref LL_DMA_CHANNEL_6
6974 * @arg @ref LL_DMA_CHANNEL_7
6975 * @arg @ref LL_DMA_CHANNEL_8
6976 * @arg @ref LL_DMA_CHANNEL_9
6977 * @arg @ref LL_DMA_CHANNEL_10
6978 * @arg @ref LL_DMA_CHANNEL_11
6979 * @arg @ref LL_DMA_CHANNEL_12
6980 * @arg @ref LL_DMA_CHANNEL_13
6981 * @arg @ref LL_DMA_CHANNEL_14
6982 * @arg @ref LL_DMA_CHANNEL_15
6983 * @retval None.
6984 */
LL_DMA_EnableIT_HT(DMA_TypeDef * DMAx,uint32_t Channel)6985 __STATIC_INLINE void LL_DMA_EnableIT_HT(DMA_TypeDef *DMAx, uint32_t Channel)
6986 {
6987 uint32_t dma_base_addr = (uint32_t)DMAx;
6988 SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_HTIE);
6989 }
6990
6991 /**
6992 * @brief Enable transfer complete interrupt.
6993 * @note This API is used for all available DMA channels.
6994 * @rmtoll CCR TCIE LL_DMA_EnableIT_TC
6995 * @param DMAx DMAx Instance
6996 * @param Channel This parameter can be one of the following values:
6997 * @arg @ref LL_DMA_CHANNEL_0
6998 * @arg @ref LL_DMA_CHANNEL_1
6999 * @arg @ref LL_DMA_CHANNEL_2
7000 * @arg @ref LL_DMA_CHANNEL_3
7001 * @arg @ref LL_DMA_CHANNEL_4
7002 * @arg @ref LL_DMA_CHANNEL_5
7003 * @arg @ref LL_DMA_CHANNEL_6
7004 * @arg @ref LL_DMA_CHANNEL_7
7005 * @arg @ref LL_DMA_CHANNEL_8
7006 * @arg @ref LL_DMA_CHANNEL_9
7007 * @arg @ref LL_DMA_CHANNEL_10
7008 * @arg @ref LL_DMA_CHANNEL_11
7009 * @arg @ref LL_DMA_CHANNEL_12
7010 * @arg @ref LL_DMA_CHANNEL_13
7011 * @arg @ref LL_DMA_CHANNEL_14
7012 * @arg @ref LL_DMA_CHANNEL_15
7013 * @retval None.
7014 */
LL_DMA_EnableIT_TC(DMA_TypeDef * DMAx,uint32_t Channel)7015 __STATIC_INLINE void LL_DMA_EnableIT_TC(DMA_TypeDef *DMAx, uint32_t Channel)
7016 {
7017 uint32_t dma_base_addr = (uint32_t)DMAx;
7018 SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_TCIE);
7019 }
7020
7021 /**
7022 * @brief Disable trigger overrun interrupt.
7023 * @note This API is used for all available DMA channels.
7024 * @rmtoll CCR TOIE LL_DMA_DisableIT_TO
7025 * @param DMAx DMAx Instance
7026 * @param Channel This parameter can be one of the following values:
7027 * @arg @ref LL_DMA_CHANNEL_0
7028 * @arg @ref LL_DMA_CHANNEL_1
7029 * @arg @ref LL_DMA_CHANNEL_2
7030 * @arg @ref LL_DMA_CHANNEL_3
7031 * @arg @ref LL_DMA_CHANNEL_4
7032 * @arg @ref LL_DMA_CHANNEL_5
7033 * @arg @ref LL_DMA_CHANNEL_6
7034 * @arg @ref LL_DMA_CHANNEL_7
7035 * @arg @ref LL_DMA_CHANNEL_8
7036 * @arg @ref LL_DMA_CHANNEL_9
7037 * @arg @ref LL_DMA_CHANNEL_10
7038 * @arg @ref LL_DMA_CHANNEL_11
7039 * @arg @ref LL_DMA_CHANNEL_12
7040 * @arg @ref LL_DMA_CHANNEL_13
7041 * @arg @ref LL_DMA_CHANNEL_14
7042 * @arg @ref LL_DMA_CHANNEL_15
7043 * @retval None.
7044 */
LL_DMA_DisableIT_TO(DMA_TypeDef * DMAx,uint32_t Channel)7045 __STATIC_INLINE void LL_DMA_DisableIT_TO(DMA_TypeDef *DMAx, uint32_t Channel)
7046 {
7047 uint32_t dma_base_addr = (uint32_t)DMAx;
7048 CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_TOIE);
7049 }
7050
7051 /**
7052 * @brief Disable suspension interrupt.
7053 * @note This API is used for all available DMA channels.
7054 * @rmtoll CCR SUSPIE LL_DMA_DisableIT_SUSP
7055 * @param DMAx DMAx Instance
7056 * @param Channel This parameter can be one of the following values:
7057 * @arg @ref LL_DMA_CHANNEL_0
7058 * @arg @ref LL_DMA_CHANNEL_1
7059 * @arg @ref LL_DMA_CHANNEL_2
7060 * @arg @ref LL_DMA_CHANNEL_3
7061 * @arg @ref LL_DMA_CHANNEL_4
7062 * @arg @ref LL_DMA_CHANNEL_5
7063 * @arg @ref LL_DMA_CHANNEL_6
7064 * @arg @ref LL_DMA_CHANNEL_7
7065 * @arg @ref LL_DMA_CHANNEL_8
7066 * @arg @ref LL_DMA_CHANNEL_9
7067 * @arg @ref LL_DMA_CHANNEL_10
7068 * @arg @ref LL_DMA_CHANNEL_11
7069 * @arg @ref LL_DMA_CHANNEL_12
7070 * @arg @ref LL_DMA_CHANNEL_13
7071 * @arg @ref LL_DMA_CHANNEL_14
7072 * @arg @ref LL_DMA_CHANNEL_15
7073 * @retval None.
7074 */
LL_DMA_DisableIT_SUSP(DMA_TypeDef * DMAx,uint32_t Channel)7075 __STATIC_INLINE void LL_DMA_DisableIT_SUSP(DMA_TypeDef *DMAx, uint32_t Channel)
7076 {
7077 uint32_t dma_base_addr = (uint32_t)DMAx;
7078 CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_SUSPIE);
7079 }
7080
7081 /**
7082 * @brief Disable user setting error interrupt.
7083 * @note This API is used for all available DMA channels.
7084 * @rmtoll CCR USEIE LL_DMA_DisableIT_USE
7085 * @param DMAx DMAx Instance
7086 * @param Channel This parameter can be one of the following values:
7087 * @arg @ref LL_DMA_CHANNEL_0
7088 * @arg @ref LL_DMA_CHANNEL_1
7089 * @arg @ref LL_DMA_CHANNEL_2
7090 * @arg @ref LL_DMA_CHANNEL_3
7091 * @arg @ref LL_DMA_CHANNEL_4
7092 * @arg @ref LL_DMA_CHANNEL_5
7093 * @arg @ref LL_DMA_CHANNEL_6
7094 * @arg @ref LL_DMA_CHANNEL_7
7095 * @arg @ref LL_DMA_CHANNEL_8
7096 * @arg @ref LL_DMA_CHANNEL_9
7097 * @arg @ref LL_DMA_CHANNEL_10
7098 * @arg @ref LL_DMA_CHANNEL_11
7099 * @arg @ref LL_DMA_CHANNEL_12
7100 * @arg @ref LL_DMA_CHANNEL_13
7101 * @arg @ref LL_DMA_CHANNEL_14
7102 * @arg @ref LL_DMA_CHANNEL_15
7103 * @retval None.
7104 */
LL_DMA_DisableIT_USE(DMA_TypeDef * DMAx,uint32_t Channel)7105 __STATIC_INLINE void LL_DMA_DisableIT_USE(DMA_TypeDef *DMAx, uint32_t Channel)
7106 {
7107 uint32_t dma_base_addr = (uint32_t)DMAx;
7108 CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_USEIE);
7109 }
7110
7111 /**
7112 * @brief Disable update link transfer error interrupt.
7113 * @note This API is used for all available DMA channels.
7114 * @rmtoll CCR ULEIE LL_DMA_DisableIT_ULE
7115 * @param DMAx DMAx Instance
7116 * @param Channel This parameter can be one of the following values:
7117 * @arg @ref LL_DMA_CHANNEL_0
7118 * @arg @ref LL_DMA_CHANNEL_1
7119 * @arg @ref LL_DMA_CHANNEL_2
7120 * @arg @ref LL_DMA_CHANNEL_3
7121 * @arg @ref LL_DMA_CHANNEL_4
7122 * @arg @ref LL_DMA_CHANNEL_5
7123 * @arg @ref LL_DMA_CHANNEL_6
7124 * @arg @ref LL_DMA_CHANNEL_7
7125 * @arg @ref LL_DMA_CHANNEL_8
7126 * @arg @ref LL_DMA_CHANNEL_9
7127 * @arg @ref LL_DMA_CHANNEL_10
7128 * @arg @ref LL_DMA_CHANNEL_11
7129 * @arg @ref LL_DMA_CHANNEL_12
7130 * @arg @ref LL_DMA_CHANNEL_13
7131 * @arg @ref LL_DMA_CHANNEL_14
7132 * @arg @ref LL_DMA_CHANNEL_15
7133 * @retval None.
7134 */
LL_DMA_DisableIT_ULE(DMA_TypeDef * DMAx,uint32_t Channel)7135 __STATIC_INLINE void LL_DMA_DisableIT_ULE(DMA_TypeDef *DMAx, uint32_t Channel)
7136 {
7137 uint32_t dma_base_addr = (uint32_t)DMAx;
7138 CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_ULEIE);
7139 }
7140
7141 /**
7142 * @brief Disable data transfer error interrupt.
7143 * @note This API is used for all available DMA channels.
7144 * @rmtoll CCR DTEIE LL_DMA_DisableIT_DTE
7145 * @param DMAx DMAx Instance
7146 * @param Channel This parameter can be one of the following values:
7147 * @arg @ref LL_DMA_CHANNEL_0
7148 * @arg @ref LL_DMA_CHANNEL_1
7149 * @arg @ref LL_DMA_CHANNEL_2
7150 * @arg @ref LL_DMA_CHANNEL_3
7151 * @arg @ref LL_DMA_CHANNEL_4
7152 * @arg @ref LL_DMA_CHANNEL_5
7153 * @arg @ref LL_DMA_CHANNEL_6
7154 * @arg @ref LL_DMA_CHANNEL_7
7155 * @arg @ref LL_DMA_CHANNEL_8
7156 * @arg @ref LL_DMA_CHANNEL_9
7157 * @arg @ref LL_DMA_CHANNEL_10
7158 * @arg @ref LL_DMA_CHANNEL_11
7159 * @arg @ref LL_DMA_CHANNEL_12
7160 * @arg @ref LL_DMA_CHANNEL_13
7161 * @arg @ref LL_DMA_CHANNEL_14
7162 * @arg @ref LL_DMA_CHANNEL_15
7163 * @retval None.
7164 */
LL_DMA_DisableIT_DTE(DMA_TypeDef * DMAx,uint32_t Channel)7165 __STATIC_INLINE void LL_DMA_DisableIT_DTE(DMA_TypeDef *DMAx, uint32_t Channel)
7166 {
7167 uint32_t dma_base_addr = (uint32_t)DMAx;
7168 CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_DTEIE);
7169 }
7170
7171 /**
7172 * @brief Disable half transfer complete interrupt.
7173 * @note This API is used for all available DMA channels.
7174 * @rmtoll CCR HTIE LL_DMA_DisableIT_HT
7175 * @param DMAx DMAx Instance
7176 * @param Channel This parameter can be one of the following values:
7177 * @arg @ref LL_DMA_CHANNEL_0
7178 * @arg @ref LL_DMA_CHANNEL_1
7179 * @arg @ref LL_DMA_CHANNEL_2
7180 * @arg @ref LL_DMA_CHANNEL_3
7181 * @arg @ref LL_DMA_CHANNEL_4
7182 * @arg @ref LL_DMA_CHANNEL_5
7183 * @arg @ref LL_DMA_CHANNEL_6
7184 * @arg @ref LL_DMA_CHANNEL_7
7185 * @arg @ref LL_DMA_CHANNEL_8
7186 * @arg @ref LL_DMA_CHANNEL_9
7187 * @arg @ref LL_DMA_CHANNEL_10
7188 * @arg @ref LL_DMA_CHANNEL_11
7189 * @arg @ref LL_DMA_CHANNEL_12
7190 * @arg @ref LL_DMA_CHANNEL_13
7191 * @arg @ref LL_DMA_CHANNEL_14
7192 * @arg @ref LL_DMA_CHANNEL_15
7193 * @retval None.
7194 */
LL_DMA_DisableIT_HT(DMA_TypeDef * DMAx,uint32_t Channel)7195 __STATIC_INLINE void LL_DMA_DisableIT_HT(DMA_TypeDef *DMAx, uint32_t Channel)
7196 {
7197 uint32_t dma_base_addr = (uint32_t)DMAx;
7198 CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_HTIE);
7199 }
7200
7201 /**
7202 * @brief Disable transfer complete interrupt.
7203 * @note This API is used for all available DMA channels.
7204 * @rmtoll CCR TCIE LL_DMA_DisableIT_TC
7205 * @param DMAx DMAx Instance
7206 * @param Channel This parameter can be one of the following values:
7207 * @arg @ref LL_DMA_CHANNEL_0
7208 * @arg @ref LL_DMA_CHANNEL_1
7209 * @arg @ref LL_DMA_CHANNEL_2
7210 * @arg @ref LL_DMA_CHANNEL_3
7211 * @arg @ref LL_DMA_CHANNEL_4
7212 * @arg @ref LL_DMA_CHANNEL_5
7213 * @arg @ref LL_DMA_CHANNEL_6
7214 * @arg @ref LL_DMA_CHANNEL_7
7215 * @arg @ref LL_DMA_CHANNEL_8
7216 * @arg @ref LL_DMA_CHANNEL_9
7217 * @arg @ref LL_DMA_CHANNEL_10
7218 * @arg @ref LL_DMA_CHANNEL_11
7219 * @arg @ref LL_DMA_CHANNEL_12
7220 * @arg @ref LL_DMA_CHANNEL_13
7221 * @arg @ref LL_DMA_CHANNEL_14
7222 * @arg @ref LL_DMA_CHANNEL_15
7223 * @retval None.
7224 */
LL_DMA_DisableIT_TC(DMA_TypeDef * DMAx,uint32_t Channel)7225 __STATIC_INLINE void LL_DMA_DisableIT_TC(DMA_TypeDef *DMAx, uint32_t Channel)
7226 {
7227 uint32_t dma_base_addr = (uint32_t)DMAx;
7228 CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_TCIE);
7229 }
7230
7231 /**
7232 * @brief Check if trigger overrun interrupt is enabled.
7233 * @note This API is used for all available DMA channels.
7234 * @rmtoll CCR TOIE LL_DMA_IsEnabledIT_TO
7235 * @param DMAx DMAx Instance
7236 * @param Channel This parameter can be one of the following values:
7237 * @arg @ref LL_DMA_CHANNEL_0
7238 * @arg @ref LL_DMA_CHANNEL_1
7239 * @arg @ref LL_DMA_CHANNEL_2
7240 * @arg @ref LL_DMA_CHANNEL_3
7241 * @arg @ref LL_DMA_CHANNEL_4
7242 * @arg @ref LL_DMA_CHANNEL_5
7243 * @arg @ref LL_DMA_CHANNEL_6
7244 * @arg @ref LL_DMA_CHANNEL_7
7245 * @arg @ref LL_DMA_CHANNEL_8
7246 * @arg @ref LL_DMA_CHANNEL_9
7247 * @arg @ref LL_DMA_CHANNEL_10
7248 * @arg @ref LL_DMA_CHANNEL_11
7249 * @arg @ref LL_DMA_CHANNEL_12
7250 * @arg @ref LL_DMA_CHANNEL_13
7251 * @arg @ref LL_DMA_CHANNEL_14
7252 * @arg @ref LL_DMA_CHANNEL_15
7253 * @retval State of bit (1 or 0).
7254 */
LL_DMA_IsEnabledIT_TO(DMA_TypeDef * DMAx,uint32_t Channel)7255 __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TO(DMA_TypeDef *DMAx, uint32_t Channel)
7256 {
7257 uint32_t dma_base_addr = (uint32_t)DMAx;
7258 return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_TOIE)
7259 == DMA_CCR_TOIE) ? 1UL : 0UL);
7260 }
7261
7262 /**
7263 * @brief Check if suspension interrupt is enabled.
7264 * @note This API is used for all available DMA channels.
7265 * @rmtoll CCR SUSPIE LL_DMA_IsEnabledIT_SUSP
7266 * @param DMAx DMAx Instance
7267 * @param Channel This parameter can be one of the following values:
7268 * @arg @ref LL_DMA_CHANNEL_0
7269 * @arg @ref LL_DMA_CHANNEL_1
7270 * @arg @ref LL_DMA_CHANNEL_2
7271 * @arg @ref LL_DMA_CHANNEL_3
7272 * @arg @ref LL_DMA_CHANNEL_4
7273 * @arg @ref LL_DMA_CHANNEL_5
7274 * @arg @ref LL_DMA_CHANNEL_6
7275 * @arg @ref LL_DMA_CHANNEL_7
7276 * @arg @ref LL_DMA_CHANNEL_8
7277 * @arg @ref LL_DMA_CHANNEL_9
7278 * @arg @ref LL_DMA_CHANNEL_10
7279 * @arg @ref LL_DMA_CHANNEL_11
7280 * @arg @ref LL_DMA_CHANNEL_12
7281 * @arg @ref LL_DMA_CHANNEL_13
7282 * @arg @ref LL_DMA_CHANNEL_14
7283 * @arg @ref LL_DMA_CHANNEL_15
7284 * @retval State of bit (1 or 0).
7285 */
LL_DMA_IsEnabledIT_SUSP(DMA_TypeDef * DMAx,uint32_t Channel)7286 __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_SUSP(DMA_TypeDef *DMAx, uint32_t Channel)
7287 {
7288 uint32_t dma_base_addr = (uint32_t)DMAx;
7289 return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_SUSPIE)
7290 == DMA_CCR_SUSPIE) ? 1UL : 0UL);
7291 }
7292
7293 /**
7294 * @brief Check if user setting error interrupt is enabled.
7295 * @note This API is used for all available DMA channels.
7296 * @rmtoll CCR USEIE LL_DMA_IsEnabledIT_USE
7297 * @param DMAx DMAx Instance
7298 * @param Channel This parameter can be one of the following values:
7299 * @arg @ref LL_DMA_CHANNEL_0
7300 * @arg @ref LL_DMA_CHANNEL_1
7301 * @arg @ref LL_DMA_CHANNEL_2
7302 * @arg @ref LL_DMA_CHANNEL_3
7303 * @arg @ref LL_DMA_CHANNEL_4
7304 * @arg @ref LL_DMA_CHANNEL_5
7305 * @arg @ref LL_DMA_CHANNEL_6
7306 * @arg @ref LL_DMA_CHANNEL_7
7307 * @arg @ref LL_DMA_CHANNEL_8
7308 * @arg @ref LL_DMA_CHANNEL_9
7309 * @arg @ref LL_DMA_CHANNEL_10
7310 * @arg @ref LL_DMA_CHANNEL_11
7311 * @arg @ref LL_DMA_CHANNEL_12
7312 * @arg @ref LL_DMA_CHANNEL_13
7313 * @arg @ref LL_DMA_CHANNEL_14
7314 * @arg @ref LL_DMA_CHANNEL_15
7315 * @retval State of bit (1 or 0).
7316 */
LL_DMA_IsEnabledIT_USE(DMA_TypeDef * DMAx,uint32_t Channel)7317 __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_USE(DMA_TypeDef *DMAx, uint32_t Channel)
7318 {
7319 uint32_t dma_base_addr = (uint32_t)DMAx;
7320 return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_USEIE)
7321 == DMA_CCR_USEIE) ? 1UL : 0UL);
7322 }
7323
7324 /**
7325 * @brief Check if update link transfer error interrupt is enabled.
7326 * @note This API is used for all available DMA channels.
7327 * @rmtoll CCR ULEIE LL_DMA_IsEnabledIT_ULE
7328 * @param DMAx DMAx Instance
7329 * @param Channel This parameter can be one of the following values:
7330 * @arg @ref LL_DMA_CHANNEL_0
7331 * @arg @ref LL_DMA_CHANNEL_1
7332 * @arg @ref LL_DMA_CHANNEL_2
7333 * @arg @ref LL_DMA_CHANNEL_3
7334 * @arg @ref LL_DMA_CHANNEL_4
7335 * @arg @ref LL_DMA_CHANNEL_5
7336 * @arg @ref LL_DMA_CHANNEL_6
7337 * @arg @ref LL_DMA_CHANNEL_7
7338 * @arg @ref LL_DMA_CHANNEL_8
7339 * @arg @ref LL_DMA_CHANNEL_9
7340 * @arg @ref LL_DMA_CHANNEL_10
7341 * @arg @ref LL_DMA_CHANNEL_11
7342 * @arg @ref LL_DMA_CHANNEL_12
7343 * @arg @ref LL_DMA_CHANNEL_13
7344 * @arg @ref LL_DMA_CHANNEL_14
7345 * @arg @ref LL_DMA_CHANNEL_15
7346 * @retval State of bit (1 or 0).
7347 */
LL_DMA_IsEnabledIT_ULE(DMA_TypeDef * DMAx,uint32_t Channel)7348 __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_ULE(DMA_TypeDef *DMAx, uint32_t Channel)
7349 {
7350 uint32_t dma_base_addr = (uint32_t)DMAx;
7351 return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_ULEIE)
7352 == DMA_CCR_ULEIE) ? 1UL : 0UL);
7353 }
7354
7355 /**
7356 * @brief Check if data transfer error interrupt is enabled.
7357 * @note This API is used for all available DMA channels.
7358 * @rmtoll CCR DTEIE LL_DMA_IsEnabledIT_DTE
7359 * @param DMAx DMAx Instance
7360 * @param Channel This parameter can be one of the following values:
7361 * @arg @ref LL_DMA_CHANNEL_0
7362 * @arg @ref LL_DMA_CHANNEL_1
7363 * @arg @ref LL_DMA_CHANNEL_2
7364 * @arg @ref LL_DMA_CHANNEL_3
7365 * @arg @ref LL_DMA_CHANNEL_4
7366 * @arg @ref LL_DMA_CHANNEL_5
7367 * @arg @ref LL_DMA_CHANNEL_6
7368 * @arg @ref LL_DMA_CHANNEL_7
7369 * @arg @ref LL_DMA_CHANNEL_8
7370 * @arg @ref LL_DMA_CHANNEL_9
7371 * @arg @ref LL_DMA_CHANNEL_10
7372 * @arg @ref LL_DMA_CHANNEL_11
7373 * @arg @ref LL_DMA_CHANNEL_12
7374 * @arg @ref LL_DMA_CHANNEL_13
7375 * @arg @ref LL_DMA_CHANNEL_14
7376 * @arg @ref LL_DMA_CHANNEL_15
7377 * @retval State of bit (1 or 0).
7378 */
LL_DMA_IsEnabledIT_DTE(DMA_TypeDef * DMAx,uint32_t Channel)7379 __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_DTE(DMA_TypeDef *DMAx, uint32_t Channel)
7380 {
7381 uint32_t dma_base_addr = (uint32_t)DMAx;
7382 return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_DTEIE)
7383 == DMA_CCR_DTEIE) ? 1UL : 0UL);
7384 }
7385
7386 /**
7387 * @brief Check if half transfer complete interrupt is enabled.
7388 * @note This API is used for all available DMA channels.
7389 * @rmtoll CCR HTIE LL_DMA_IsEnabledIT_HT
7390 * @param DMAx DMAx Instance
7391 * @param Channel This parameter can be one of the following values:
7392 * @arg @ref LL_DMA_CHANNEL_0
7393 * @arg @ref LL_DMA_CHANNEL_1
7394 * @arg @ref LL_DMA_CHANNEL_2
7395 * @arg @ref LL_DMA_CHANNEL_3
7396 * @arg @ref LL_DMA_CHANNEL_4
7397 * @arg @ref LL_DMA_CHANNEL_5
7398 * @arg @ref LL_DMA_CHANNEL_6
7399 * @arg @ref LL_DMA_CHANNEL_7
7400 * @arg @ref LL_DMA_CHANNEL_8
7401 * @arg @ref LL_DMA_CHANNEL_9
7402 * @arg @ref LL_DMA_CHANNEL_10
7403 * @arg @ref LL_DMA_CHANNEL_11
7404 * @arg @ref LL_DMA_CHANNEL_12
7405 * @arg @ref LL_DMA_CHANNEL_13
7406 * @arg @ref LL_DMA_CHANNEL_14
7407 * @arg @ref LL_DMA_CHANNEL_15
7408 * @retval State of bit (1 or 0).
7409 */
LL_DMA_IsEnabledIT_HT(DMA_TypeDef * DMAx,uint32_t Channel)7410 __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_HT(DMA_TypeDef *DMAx, uint32_t Channel)
7411 {
7412 uint32_t dma_base_addr = (uint32_t)DMAx;
7413 return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_HTIE)
7414 == DMA_CCR_HTIE) ? 1UL : 0UL);
7415 }
7416
7417 /**
7418 * @brief Check if transfer complete interrupt is enabled.
7419 * @note This API is used for all available DMA channels.
7420 * @rmtoll CCR TCIE LL_DMA_IsEnabledIT_TC
7421 * @param DMAx DMAx Instance
7422 * @param Channel This parameter can be one of the following values:
7423 * @arg @ref LL_DMA_CHANNEL_0
7424 * @arg @ref LL_DMA_CHANNEL_1
7425 * @arg @ref LL_DMA_CHANNEL_2
7426 * @arg @ref LL_DMA_CHANNEL_3
7427 * @arg @ref LL_DMA_CHANNEL_4
7428 * @arg @ref LL_DMA_CHANNEL_5
7429 * @arg @ref LL_DMA_CHANNEL_6
7430 * @arg @ref LL_DMA_CHANNEL_7
7431 * @arg @ref LL_DMA_CHANNEL_8
7432 * @arg @ref LL_DMA_CHANNEL_9
7433 * @arg @ref LL_DMA_CHANNEL_10
7434 * @arg @ref LL_DMA_CHANNEL_11
7435 * @arg @ref LL_DMA_CHANNEL_12
7436 * @arg @ref LL_DMA_CHANNEL_13
7437 * @arg @ref LL_DMA_CHANNEL_14
7438 * @arg @ref LL_DMA_CHANNEL_15
7439 * @retval State of bit (1 or 0).
7440 */
LL_DMA_IsEnabledIT_TC(DMA_TypeDef * DMAx,uint32_t Channel)7441 __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TC(DMA_TypeDef *DMAx, uint32_t Channel)
7442 {
7443 uint32_t dma_base_addr = (uint32_t)DMAx;
7444 return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_TCIE)
7445 == DMA_CCR_TCIE) ? 1UL : 0UL);
7446 }
7447 /**
7448 * @}
7449 */
7450
7451 #if defined (USE_FULL_LL_DRIVER)
7452 /** @defgroup DMA_LL_EF_Init Initialization and de-initialization functions
7453 * @{
7454 */
7455 uint32_t LL_DMA_Init(DMA_TypeDef *DMAx, uint32_t Channel, LL_DMA_InitTypeDef *DMA_InitStruct);
7456 uint32_t LL_DMA_DeInit(DMA_TypeDef *DMAx, uint32_t Channel);
7457
7458 void LL_DMA_StructInit(LL_DMA_InitTypeDef *DMA_InitStruct);
7459 void LL_DMA_ListStructInit(LL_DMA_InitLinkedListTypeDef *DMA_InitLinkedListStruct);
7460 void LL_DMA_NodeStructInit(LL_DMA_InitNodeTypeDef *DMA_InitNodeStruct);
7461
7462 uint32_t LL_DMA_List_Init(DMA_TypeDef *DMAx, uint32_t Channel,
7463 LL_DMA_InitLinkedListTypeDef *DMA_InitLinkedListStruct);
7464 uint32_t LL_DMA_List_DeInit(DMA_TypeDef *DMAx, uint32_t Channel);
7465
7466 uint32_t LL_DMA_CreateLinkNode(LL_DMA_InitNodeTypeDef *DMA_InitNodeStruct, LL_DMA_LinkNodeTypeDef *pNode);
7467 void LL_DMA_ConnectLinkNode(LL_DMA_LinkNodeTypeDef *pPrevLinkNode, uint32_t PrevNodeCLLRIdx,
7468 LL_DMA_LinkNodeTypeDef *pNewLinkNode, uint32_t NewNodeCLLRIdx);
7469 void LL_DMA_DisconnectNextLinkNode(LL_DMA_LinkNodeTypeDef *pLinkNode, uint32_t LinkNodeCLLRIdx);
7470 /**
7471 * @}
7472 */
7473 #endif /* defined (USE_FULL_LL_DRIVER) */
7474
7475 /**
7476 * @}
7477 */
7478
7479 /**
7480 * @}
7481 */
7482
7483 #endif /* defined (GPDMA1) */
7484
7485 /**
7486 * @}
7487 */
7488
7489 #ifdef __cplusplus
7490 }
7491 #endif /* __cplusplus */
7492
7493 #endif /* STM32H5xx_LL_DMA_H */
7494
