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Searched refs:ctrl (Results 1 – 25 of 42) sorted by relevance

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/hal_rpi_pico-latest/src/rp2_common/hardware_interp/include/hardware/
Dinterp.h59 uint32_t ctrl; member
128 c->ctrl = (c->ctrl & ~SIO_INTERP0_CTRL_LANE0_SHIFT_BITS) | in interp_config_set_shift()
144 …c->ctrl = (c->ctrl & ~(SIO_INTERP0_CTRL_LANE0_MASK_LSB_BITS | SIO_INTERP0_CTRL_LANE0_MASK_MSB_BITS… in interp_config_set_mask()
160 c->ctrl = (c->ctrl & ~SIO_INTERP0_CTRL_LANE0_CROSS_INPUT_BITS) | in interp_config_set_cross_input()
173 c->ctrl = (c->ctrl & ~SIO_INTERP0_CTRL_LANE0_CROSS_RESULT_BITS) | in interp_config_set_cross_result()
187 c->ctrl = (c->ctrl & ~SIO_INTERP0_CTRL_LANE0_SIGNED_BITS) | in interp_config_set_signed()
200 c->ctrl = (c->ctrl & ~SIO_INTERP0_CTRL_LANE0_ADD_RAW_BITS) | in interp_config_set_add_raw()
220 c->ctrl = (c->ctrl & ~SIO_INTERP0_CTRL_LANE0_BLEND_BITS) | in interp_config_set_blend()
235 c->ctrl = (c->ctrl & ~SIO_INTERP1_CTRL_LANE0_CLAMP_BITS) | in interp_config_set_clamp()
253 c->ctrl = (c->ctrl & ~SIO_INTERP0_CTRL_LANE0_FORCE_MSB_BITS) | in interp_config_set_force_bits()
[all …]
/hal_rpi_pico-latest/src/rp2_common/hardware_dma/
Ddma.c89 uint32_t ctrl = channel->ctrl_trig; in print_dma_ctrl() local
90 int rgsz = (ctrl & DMA_CH0_CTRL_TRIG_RING_SIZE_BITS) >> DMA_CH0_CTRL_TRIG_RING_SIZE_LSB; in print_dma_ctrl()
92 (uint) ctrl, in print_dma_ctrl()
93 ctrl & DMA_CH0_CTRL_TRIG_AHB_ERROR_BITS ? 1 : 0, in print_dma_ctrl()
94 ctrl & DMA_CH0_CTRL_TRIG_READ_ERROR_BITS ? 1 : 0, in print_dma_ctrl()
95 ctrl & DMA_CH0_CTRL_TRIG_WRITE_ERROR_BITS ? 1 : 0, in print_dma_ctrl()
96 ctrl & DMA_CH0_CTRL_TRIG_BUSY_BITS ? 1 : 0, in print_dma_ctrl()
97 (int) ((ctrl & DMA_CH0_CTRL_TRIG_TREQ_SEL_BITS) >> DMA_CH0_CTRL_TRIG_TREQ_SEL_LSB), in print_dma_ctrl()
98 (int) ((ctrl & DMA_CH0_CTRL_TRIG_CHAIN_TO_BITS) >> DMA_CH0_CTRL_TRIG_CHAIN_TO_LSB), in print_dma_ctrl()
99 ctrl & DMA_CH0_CTRL_TRIG_RING_SEL_BITS ? 1 : 0, in print_dma_ctrl()
[all …]
/hal_rpi_pico-latest/src/rp2_common/hardware_dma/include/hardware/
Ddma.h150 uint32_t ctrl; member
161 …c->ctrl = incr ? (c->ctrl | DMA_CH0_CTRL_TRIG_INCR_READ_BITS) : (c->ctrl & ~DMA_CH0_CTRL_TRIG_INCR… in channel_config_set_read_increment()
172 …c->ctrl = incr ? (c->ctrl | DMA_CH0_CTRL_TRIG_INCR_WRITE_BITS) : (c->ctrl & ~DMA_CH0_CTRL_TRIG_INC… in channel_config_set_write_increment()
192 … c->ctrl = (c->ctrl & ~DMA_CH0_CTRL_TRIG_TREQ_SEL_BITS) | (dreq << DMA_CH0_CTRL_TRIG_TREQ_SEL_LSB); in channel_config_set_dreq()
206 …c->ctrl = (c->ctrl & ~DMA_CH0_CTRL_TRIG_CHAIN_TO_BITS) | (chain_to << DMA_CH0_CTRL_TRIG_CHAIN_TO_L… in channel_config_set_chain_to()
220 …c->ctrl = (c->ctrl & ~DMA_CH0_CTRL_TRIG_DATA_SIZE_BITS) | (((uint)size) << DMA_CH0_CTRL_TRIG_DATA_… in channel_config_set_transfer_data_size()
240 c->ctrl = (c->ctrl & ~(DMA_CH0_CTRL_TRIG_RING_SIZE_BITS | DMA_CH0_CTRL_TRIG_RING_SEL_BITS)) | in channel_config_set_ring()
255 …c->ctrl = bswap ? (c->ctrl | DMA_CH0_CTRL_TRIG_BSWAP_BITS) : (c->ctrl & ~DMA_CH0_CTRL_TRIG_BSWAP_B… in channel_config_set_bswap()
269 …c->ctrl = irq_quiet ? (c->ctrl | DMA_CH0_CTRL_TRIG_IRQ_QUIET_BITS) : (c->ctrl & ~DMA_CH0_CTRL_TRIG… in channel_config_set_irq_quiet()
287 …c->ctrl = high_priority ? (c->ctrl | DMA_CH0_CTRL_TRIG_HIGH_PRIORITY_BITS) : (c->ctrl & ~DMA_CH0_C… in channel_config_set_high_priority()
[all …]
/hal_rpi_pico-latest/src/rp2_common/hardware_watchdog/
Dwatchdog.c32 return watchdog_hw->ctrl & WATCHDOG_CTRL_TIME_BITS; in watchdog_get_time_remaining_ms()
45 hw_clear_bits(&watchdog_hw->ctrl, WATCHDOG_CTRL_ENABLE_BITS); in _watchdog_enable()
55 hw_set_bits(&watchdog_hw->ctrl, dbg_bits); in _watchdog_enable()
57 hw_clear_bits(&watchdog_hw->ctrl, dbg_bits); in _watchdog_enable()
61 hw_set_bits(&watchdog_hw->ctrl, WATCHDOG_CTRL_TRIGGER_BITS); in _watchdog_enable()
72 hw_set_bits(&watchdog_hw->ctrl, WATCHDOG_CTRL_ENABLE_BITS); in _watchdog_enable()
87 hw_clear_bits(&watchdog_hw->ctrl, WATCHDOG_CTRL_ENABLE_BITS); in watchdog_disable()
94 hw_clear_bits(&watchdog_hw->ctrl, WATCHDOG_CTRL_ENABLE_BITS); in watchdog_reboot()
/hal_rpi_pico-latest/src/rp2_common/hardware_interp/
Dinterp.c54 saver->ctrl[0] = interp->ctrl[0]; in interp_save()
55 saver->ctrl[1] = interp->ctrl[1]; in interp_save()
64 interp->ctrl[0] = saver->ctrl[0]; in interp_restore()
65 interp->ctrl[1] = saver->ctrl[1]; in interp_restore()
/hal_rpi_pico-latest/src/rp2_common/hardware_xosc/
Dxosc.c31 xosc_hw->ctrl = XOSC_CTRL_FREQ_RANGE_VALUE_1_15MHZ; in xosc_init()
37 hw_set_bits(&xosc_hw->ctrl, XOSC_CTRL_ENABLE_VALUE_ENABLE << XOSC_CTRL_ENABLE_LSB); in xosc_init()
46 uint32_t tmp = xosc_hw->ctrl; in xosc_disable()
49 xosc_hw->ctrl = tmp; in xosc_disable()
/hal_rpi_pico-latest/src/rp2_common/hardware_ticks/
Dticks.c22 ticks_hw->ticks[tick].ctrl = TICKS_WATCHDOG_CTRL_ENABLE_BITS; in tick_start()
32 hw_clear_bits(&ticks_hw->ticks[tick].ctrl, TICKS_WATCHDOG_CTRL_ENABLE_BITS); in tick_stop()
43 return ticks_hw->ticks[tick].ctrl & TICKS_WATCHDOG_CTRL_RUNNING_BITS; in tick_is_running()
/hal_rpi_pico-latest/src/rp2_common/hardware_clocks/
Dclocks.c35 hw_clear_bits(&clock_hw->ctrl, CLOCKS_CLK_USB_CTRL_ENABLE_BITS); in clock_stop()
53 hw_clear_bits(&clock_hw->ctrl, CLOCKS_CLK_REF_CTRL_SRC_BITS); in clock_configure_internal()
63 hw_clear_bits(&clock_hw->ctrl, CLOCKS_CLK_GPOUT0_CTRL_ENABLE_BITS); in clock_configure_internal()
74 hw_write_masked(&clock_hw->ctrl, in clock_configure_internal()
80 hw_write_masked(&clock_hw->ctrl, in clock_configure_internal()
90 hw_set_bits(&clock_hw->ctrl, CLOCKS_CLK_GPOUT0_CTRL_ENABLE_BITS); in clock_configure_internal()
178 hw_set_bits(&clocks_hw->resus.ctrl, CLOCKS_CLK_SYS_RESUS_CTRL_CLEAR_BITS); in clocks_handle_resus()
179 hw_clear_bits(&clocks_hw->resus.ctrl, CLOCKS_CLK_SYS_RESUS_CTRL_CLEAR_BITS); in clocks_handle_resus()
228 clocks_hw->resus.ctrl = CLOCKS_CLK_SYS_RESUS_CTRL_ENABLE_BITS | timeout; in clocks_enable_resus()
250 clocks_hw->clk[gpclk].ctrl = (src << CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_LSB) | in clock_gpio_init_int_frac16()
/hal_rpi_pico-latest/src/rp2_common/pico_runtime_init/
Druntime_init_clocks.c52 clocks_hw->resus.ctrl = 0; in runtime_init_clocks()
58 hw_clear_bits(&clocks_hw->clk[clk_sys].ctrl, CLOCKS_CLK_SYS_CTRL_SRC_BITS); in runtime_init_clocks()
61 hw_clear_bits(&clocks_hw->clk[clk_ref].ctrl, CLOCKS_CLK_REF_CTRL_SRC_BITS); in runtime_init_clocks()
Druntime_init_stack_guard.c21 if (mpu_hw->ctrl) { in runtime_init_per_core_install_stack_guard()
27 mpu_hw->ctrl = 5; // enable mpu with background default map in runtime_init_per_core_install_stack_guard()
/hal_rpi_pico-latest/src/rp2_common/pico_fix/rp2040_usb_device_enumeration/
Drp2040_usb_device_enumeration.c95 gpio_ctrl_prev = io_bank0_hw->io[dp].ctrl; in hw_enumeration_fix_force_ls_j()
104 hw_write_masked(&io_bank0_hw->io[dp].ctrl, in hw_enumeration_fix_force_ls_j()
145 io_bank0_hw->io[dp].ctrl = gpio_ctrl_prev; in hw_enumeration_fix_finish()
/hal_rpi_pico-latest/src/rp2_common/hardware_rtc/
Drtc.c19 return (rtc_hw->ctrl & RTC_CTRL_RTC_ACTIVE_BITS); in rtc_running()
60 rtc_hw->ctrl = 0; in rtc_set_datetime()
76 rtc_hw->ctrl = RTC_CTRL_LOAD_BITS; in rtc_set_datetime()
79 rtc_hw->ctrl = RTC_CTRL_RTC_ENABLE_BITS; in rtc_set_datetime()
/hal_rpi_pico-latest/src/rp2_common/hardware_gpio/
Dgpio.c48 io_bank0_hw->io[gpio].ctrl = fn << IO_BANK0_GPIO0_CTRL_FUNCSEL_LSB; in gpio_set_function()
58 …return (gpio_function_t) ((io_bank0_hw->io[gpio].ctrl & IO_BANK0_GPIO0_CTRL_FUNCSEL_BITS) >> IO_BA… in gpio_get_function()
75 hw_write_masked(&io_bank0_hw->io[gpio].ctrl, in gpio_set_irqover()
84 hw_write_masked(&io_bank0_hw->io[gpio].ctrl, in gpio_set_inover()
92 hw_write_masked(&io_bank0_hw->io[gpio].ctrl, in gpio_set_outover()
100 hw_write_masked(&io_bank0_hw->io[gpio].ctrl, in gpio_set_oeover()
/hal_rpi_pico-latest/src/rp2040/hardware_structs/include/hardware/structs/
Dusb_dpram.h99 io_rw_32 ctrl; member
108 io_rw_32 ctrl; member
Dwatchdog.h35 io_rw_32 ctrl;
Dmpu.h39 io_rw_32 ctrl;
Dxosc.h32 io_rw_32 ctrl;
Dclocks.h109 io_rw_32 ctrl;
130 io_rw_32 ctrl;
/hal_rpi_pico-latest/src/rp2350/hardware_structs/include/hardware/structs/
Dusb_dpram.h99 io_rw_32 ctrl; member
108 io_rw_32 ctrl; member
Dwatchdog.h35 io_rw_32 ctrl;
Dxosc.h32 io_rw_32 ctrl;
Dticks.h44 io_rw_32 ctrl;
Dsau.h35 io_rw_32 ctrl;
Dxip.h40 io_rw_32 ctrl;
/hal_rpi_pico-latest/src/rp2_common/hardware_pio/include/hardware/
Dpio.h1012 pio->ctrl = (pio->ctrl & ~(1u << sm)) | (bool_to_bit(enabled) << sm); in pio_sm_set_enabled()
1031 pio->ctrl = (pio->ctrl & ~mask) | (enabled ? mask : 0u); in pio_set_sm_mask_enabled()
1053 pio->ctrl = (pio->ctrl & ~(mask << PIO_CTRL_SM_ENABLE_LSB)) | in pio_set_sm_multi_mask_enabled()
1074 hw_set_bits(&pio->ctrl, 1u << (PIO_CTRL_SM_RESTART_LSB + sm)); in pio_sm_restart()
1089 hw_set_bits(&pio->ctrl, (mask << PIO_CTRL_SM_RESTART_LSB) & PIO_CTRL_SM_RESTART_BITS); in pio_restart_sm_mask()
1116 hw_set_bits(&pio->ctrl, 1u << (PIO_CTRL_CLKDIV_RESTART_LSB + sm)); in pio_sm_clkdiv_restart()
1151 hw_set_bits(&pio->ctrl, (mask << PIO_CTRL_CLKDIV_RESTART_LSB) & PIO_CTRL_CLKDIV_RESTART_BITS); in pio_clkdiv_restart_sm_mask()
1189 hw_set_bits(&pio->ctrl, ((mask << PIO_CTRL_CLKDIV_RESTART_LSB) & PIO_CTRL_CLKDIV_RESTART_BITS) | in pio_clkdiv_restart_sm_multi_mask()
1210 hw_set_bits(&pio->ctrl, in pio_enable_sm_mask_in_sync()
1234 hw_set_bits(&pio->ctrl, ((mask << PIO_CTRL_CLKDIV_RESTART_LSB) & PIO_CTRL_CLKDIV_RESTART_BITS) | in pio_enable_sm_multi_mask_in_sync()

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