1 // THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT 2 3 /** 4 * Copyright (c) 2024 Raspberry Pi Ltd. 5 * 6 * SPDX-License-Identifier: BSD-3-Clause 7 */ 8 #ifndef _HARDWARE_STRUCTS_WATCHDOG_H 9 #define _HARDWARE_STRUCTS_WATCHDOG_H 10 11 /** 12 * \file rp2040/watchdog.h 13 */ 14 15 #include "hardware/address_mapped.h" 16 #include "hardware/regs/watchdog.h" 17 18 // Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_watchdog 19 // 20 // The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature) 21 // _REG_(x) will link to the corresponding register in hardware/regs/watchdog.h. 22 // 23 // Bit-field descriptions are of the form: 24 // BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION 25 26 typedef struct { 27 _REG_(WATCHDOG_CTRL_OFFSET) // WATCHDOG_CTRL 28 // Watchdog control 29 // 0x80000000 [31] TRIGGER (0) Trigger a watchdog reset 30 // 0x40000000 [30] ENABLE (0) When not enabled the watchdog timer is paused 31 // 0x04000000 [26] PAUSE_DBG1 (1) Pause the watchdog timer when processor 1 is in debug mode 32 // 0x02000000 [25] PAUSE_DBG0 (1) Pause the watchdog timer when processor 0 is in debug mode 33 // 0x01000000 [24] PAUSE_JTAG (1) Pause the watchdog timer when JTAG is accessing the bus fabric 34 // 0x00ffffff [23:0] TIME (0x000000) Indicates the number of ticks / 2 (see errata RP2040-E1)... 35 io_rw_32 ctrl; 36 37 _REG_(WATCHDOG_LOAD_OFFSET) // WATCHDOG_LOAD 38 // Load the watchdog timer. 39 // 0x00ffffff [23:0] LOAD (0x000000) 40 io_wo_32 load; 41 42 _REG_(WATCHDOG_REASON_OFFSET) // WATCHDOG_REASON 43 // Logs the reason for the last reset. 44 // 0x00000002 [1] FORCE (0) 45 // 0x00000001 [0] TIMER (0) 46 io_ro_32 reason; 47 48 // (Description copied from array index 0 register WATCHDOG_SCRATCH0 applies similarly to other array indexes) 49 _REG_(WATCHDOG_SCRATCH0_OFFSET) // WATCHDOG_SCRATCH0 50 // Scratch register 51 // 0xffffffff [31:0] SCRATCH0 (0x00000000) 52 io_rw_32 scratch[8]; 53 54 _REG_(WATCHDOG_TICK_OFFSET) // WATCHDOG_TICK 55 // Controls the tick generator 56 // 0x000ff800 [19:11] COUNT (-) Count down timer: the remaining number clk_tick cycles... 57 // 0x00000400 [10] RUNNING (-) Is the tick generator running? 58 // 0x00000200 [9] ENABLE (1) start / stop tick generation 59 // 0x000001ff [8:0] CYCLES (0x000) Total number of clk_tick cycles before the next tick 60 io_rw_32 tick; 61 } watchdog_hw_t; 62 63 #define watchdog_hw ((watchdog_hw_t *)WATCHDOG_BASE) 64 static_assert(sizeof (watchdog_hw_t) == 0x0030, ""); 65 66 #endif // _HARDWARE_STRUCTS_WATCHDOG_H 67 68
