1 // THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT 2 3 /** 4 * Copyright (c) 2024 Raspberry Pi Ltd. 5 * 6 * SPDX-License-Identifier: BSD-3-Clause 7 */ 8 #ifndef _HARDWARE_STRUCTS_XIP_H 9 #define _HARDWARE_STRUCTS_XIP_H 10 11 /** 12 * \file rp2350/xip.h 13 */ 14 15 #include "hardware/address_mapped.h" 16 #include "hardware/regs/xip.h" 17 18 // Reference to datasheet: https://datasheets.raspberrypi.com/rp2350/rp2350-datasheet.pdf#tab-registerlist_xip 19 // 20 // The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature) 21 // _REG_(x) will link to the corresponding register in hardware/regs/xip.h. 22 // 23 // Bit-field descriptions are of the form: 24 // BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION 25 26 typedef struct { 27 _REG_(XIP_CTRL_OFFSET) // XIP_CTRL 28 // Cache control register 29 // 0x00000800 [11] WRITABLE_M1 (0) If 1, enable writes to XIP memory window 1 (addresses... 30 // 0x00000400 [10] WRITABLE_M0 (0) If 1, enable writes to XIP memory window 0 (addresses... 31 // 0x00000200 [9] SPLIT_WAYS (0) When 1, route all cached+Secure accesses to way 0 of the... 32 // 0x00000100 [8] MAINT_NONSEC (0) When 0, Non-secure accesses to the cache maintenance... 33 // 0x00000080 [7] NO_UNTRANSLATED_NONSEC (1) When 1, Non-secure accesses to the uncached,... 34 // 0x00000040 [6] NO_UNTRANSLATED_SEC (0) When 1, Secure accesses to the uncached, untranslated... 35 // 0x00000020 [5] NO_UNCACHED_NONSEC (0) When 1, Non-secure accesses to the uncached window... 36 // 0x00000010 [4] NO_UNCACHED_SEC (0) When 1, Secure accesses to the uncached window... 37 // 0x00000008 [3] POWER_DOWN (0) When 1, the cache memories are powered down 38 // 0x00000002 [1] EN_NONSECURE (1) When 1, enable the cache for Non-secure accesses 39 // 0x00000001 [0] EN_SECURE (1) When 1, enable the cache for Secure accesses 40 io_rw_32 ctrl; 41 42 uint32_t _pad0; 43 44 _REG_(XIP_STAT_OFFSET) // XIP_STAT 45 // 0x00000004 [2] FIFO_FULL (0) When 1, indicates the XIP streaming FIFO is completely full 46 // 0x00000002 [1] FIFO_EMPTY (1) When 1, indicates the XIP streaming FIFO is completely empty 47 io_ro_32 stat; 48 49 _REG_(XIP_CTR_HIT_OFFSET) // XIP_CTR_HIT 50 // Cache Hit counter 51 // 0xffffffff [31:0] CTR_HIT (0x00000000) A 32 bit saturating counter that increments upon each... 52 io_rw_32 ctr_hit; 53 54 _REG_(XIP_CTR_ACC_OFFSET) // XIP_CTR_ACC 55 // Cache Access counter 56 // 0xffffffff [31:0] CTR_ACC (0x00000000) A 32 bit saturating counter that increments upon each... 57 io_rw_32 ctr_acc; 58 59 _REG_(XIP_STREAM_ADDR_OFFSET) // XIP_STREAM_ADDR 60 // FIFO stream address 61 // 0xfffffffc [31:2] STREAM_ADDR (0x00000000) The address of the next word to be streamed from flash... 62 io_rw_32 stream_addr; 63 64 _REG_(XIP_STREAM_CTR_OFFSET) // XIP_STREAM_CTR 65 // FIFO stream control 66 // 0x003fffff [21:0] STREAM_CTR (0x000000) Write a nonzero value to start a streaming read 67 io_rw_32 stream_ctr; 68 69 _REG_(XIP_STREAM_FIFO_OFFSET) // XIP_STREAM_FIFO 70 // FIFO stream data 71 // 0xffffffff [31:0] STREAM_FIFO (0x00000000) Streamed data is buffered here, for retrieval by the system DMA 72 io_ro_32 stream_fifo; 73 } xip_ctrl_hw_t; 74 75 #define xip_ctrl_hw ((xip_ctrl_hw_t *)XIP_CTRL_BASE) 76 static_assert(sizeof (xip_ctrl_hw_t) == 0x0020, ""); 77 78 #endif // _HARDWARE_STRUCTS_XIP_H 79 80
