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Searched refs:ctrl (Results 1 – 25 of 26) sorted by relevance

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/hal_rpi_pico-3.4.0/src/rp2_common/hardware_interp/include/hardware/
Dinterp.h54 uint32_t ctrl; member
123 c->ctrl = (c->ctrl & ~SIO_INTERP0_CTRL_LANE0_SHIFT_BITS) | in interp_config_set_shift()
139 …c->ctrl = (c->ctrl & ~(SIO_INTERP0_CTRL_LANE0_MASK_LSB_BITS | SIO_INTERP0_CTRL_LANE0_MASK_MSB_BITS… in interp_config_set_mask()
155 c->ctrl = (c->ctrl & ~SIO_INTERP0_CTRL_LANE0_CROSS_INPUT_BITS) | in interp_config_set_cross_input()
168 c->ctrl = (c->ctrl & ~SIO_INTERP0_CTRL_LANE0_CROSS_RESULT_BITS) | in interp_config_set_cross_result()
182 c->ctrl = (c->ctrl & ~SIO_INTERP0_CTRL_LANE0_SIGNED_BITS) | in interp_config_set_signed()
195 c->ctrl = (c->ctrl & ~SIO_INTERP0_CTRL_LANE0_ADD_RAW_BITS) | in interp_config_set_add_raw()
215 c->ctrl = (c->ctrl & ~SIO_INTERP0_CTRL_LANE0_BLEND_BITS) | in interp_config_set_blend()
230 c->ctrl = (c->ctrl & ~SIO_INTERP1_CTRL_LANE0_CLAMP_BITS) | in interp_config_set_clamp()
248 c->ctrl = (c->ctrl & ~SIO_INTERP0_CTRL_LANE0_FORCE_MSB_BITS) | in interp_config_set_force_bits()
[all …]
/hal_rpi_pico-3.4.0/src/rp2_common/hardware_dma/
Ddma.c76 uint32_t ctrl = channel->ctrl_trig; in print_dma_ctrl() local
77 int rgsz = (ctrl & DMA_CH0_CTRL_TRIG_RING_SIZE_BITS) >> DMA_CH0_CTRL_TRIG_RING_SIZE_LSB; in print_dma_ctrl()
79 (uint) ctrl, in print_dma_ctrl()
80 ctrl & DMA_CH0_CTRL_TRIG_AHB_ERROR_BITS ? 1 : 0, in print_dma_ctrl()
81 ctrl & DMA_CH0_CTRL_TRIG_READ_ERROR_BITS ? 1 : 0, in print_dma_ctrl()
82 ctrl & DMA_CH0_CTRL_TRIG_WRITE_ERROR_BITS ? 1 : 0, in print_dma_ctrl()
83 ctrl & DMA_CH0_CTRL_TRIG_BUSY_BITS ? 1 : 0, in print_dma_ctrl()
84 (int) ((ctrl & DMA_CH0_CTRL_TRIG_TREQ_SEL_BITS) >> DMA_CH0_CTRL_TRIG_TREQ_SEL_LSB), in print_dma_ctrl()
85 (int) ((ctrl & DMA_CH0_CTRL_TRIG_CHAIN_TO_BITS) >> DMA_CH0_CTRL_TRIG_CHAIN_TO_LSB), in print_dma_ctrl()
86 ctrl & DMA_CH0_CTRL_TRIG_RING_SEL_BITS ? 1 : 0, in print_dma_ctrl()
[all …]
/hal_rpi_pico-3.4.0/src/rp2_common/hardware_dma/include/hardware/
Ddma.h140 uint32_t ctrl; member
151 …c->ctrl = incr ? (c->ctrl | DMA_CH0_CTRL_TRIG_INCR_READ_BITS) : (c->ctrl & ~DMA_CH0_CTRL_TRIG_INCR… in channel_config_set_read_increment()
162 …c->ctrl = incr ? (c->ctrl | DMA_CH0_CTRL_TRIG_INCR_WRITE_BITS) : (c->ctrl & ~DMA_CH0_CTRL_TRIG_INC… in channel_config_set_write_increment()
182 … c->ctrl = (c->ctrl & ~DMA_CH0_CTRL_TRIG_TREQ_SEL_BITS) | (dreq << DMA_CH0_CTRL_TRIG_TREQ_SEL_LSB); in channel_config_set_dreq()
196 …c->ctrl = (c->ctrl & ~DMA_CH0_CTRL_TRIG_CHAIN_TO_BITS) | (chain_to << DMA_CH0_CTRL_TRIG_CHAIN_TO_L… in channel_config_set_chain_to()
210 …c->ctrl = (c->ctrl & ~DMA_CH0_CTRL_TRIG_DATA_SIZE_BITS) | (((uint)size) << DMA_CH0_CTRL_TRIG_DATA_… in channel_config_set_transfer_data_size()
230 c->ctrl = (c->ctrl & ~(DMA_CH0_CTRL_TRIG_RING_SIZE_BITS | DMA_CH0_CTRL_TRIG_RING_SEL_BITS)) | in channel_config_set_ring()
245 …c->ctrl = bswap ? (c->ctrl | DMA_CH0_CTRL_TRIG_BSWAP_BITS) : (c->ctrl & ~DMA_CH0_CTRL_TRIG_BSWAP_B… in channel_config_set_bswap()
259 …c->ctrl = irq_quiet ? (c->ctrl | DMA_CH0_CTRL_TRIG_IRQ_QUIET_BITS) : (c->ctrl & ~DMA_CH0_CTRL_TRIG… in channel_config_set_irq_quiet()
277 …c->ctrl = high_priority ? (c->ctrl | DMA_CH0_CTRL_TRIG_HIGH_PRIORITY_BITS) : (c->ctrl & ~DMA_CH0_C… in channel_config_set_high_priority()
[all …]
/hal_rpi_pico-3.4.0/src/rp2_common/hardware_watchdog/
Dwatchdog.c31 return (watchdog_hw->ctrl & WATCHDOG_CTRL_TIME_BITS) / 2 ; in watchdog_get_count()
37 hw_clear_bits(&watchdog_hw->ctrl, WATCHDOG_CTRL_ENABLE_BITS); in _watchdog_enable()
47 hw_set_bits(&watchdog_hw->ctrl, dbg_bits); in _watchdog_enable()
49 hw_clear_bits(&watchdog_hw->ctrl, dbg_bits); in _watchdog_enable()
53 hw_set_bits(&watchdog_hw->ctrl, WATCHDOG_CTRL_TRIGGER_BITS); in _watchdog_enable()
63 hw_set_bits(&watchdog_hw->ctrl, WATCHDOG_CTRL_ENABLE_BITS); in _watchdog_enable()
81 hw_clear_bits(&watchdog_hw->ctrl, WATCHDOG_CTRL_ENABLE_BITS); in watchdog_reboot()
/hal_rpi_pico-3.4.0/src/rp2_common/hardware_interp/
Dinterp.c56 saver->ctrl[0] = interp->ctrl[0]; in interp_save()
57 saver->ctrl[1] = interp->ctrl[1]; in interp_save()
66 interp->ctrl[0] = saver->ctrl[0]; in interp_restore()
67 interp->ctrl[1] = saver->ctrl[1]; in interp_restore()
/hal_rpi_pico-3.4.0/src/rp2_common/hardware_clocks/
Dclocks.c37 hw_clear_bits(&clock->ctrl, CLOCKS_CLK_USB_CTRL_ENABLE_BITS); in clock_stop()
65 hw_clear_bits(&clock->ctrl, CLOCKS_CLK_REF_CTRL_SRC_BITS); in clock_configure()
75 hw_clear_bits(&clock->ctrl, CLOCKS_CLK_GPOUT0_CTRL_ENABLE_BITS); in clock_configure()
92 hw_write_masked(&clock->ctrl, in clock_configure()
98 hw_write_masked(&clock->ctrl, in clock_configure()
108 hw_set_bits(&clock->ctrl, CLOCKS_CLK_GPOUT0_CTRL_ENABLE_BITS); in clock_configure()
135 clocks_hw->resus.ctrl = 0; in clocks_init()
141 hw_clear_bits(&clocks_hw->clk[clk_sys].ctrl, CLOCKS_CLK_SYS_CTRL_SRC_BITS); in clocks_init()
144 hw_clear_bits(&clocks_hw->clk[clk_ref].ctrl, CLOCKS_CLK_REF_CTRL_SRC_BITS); in clocks_init()
264 hw_set_bits(&clocks_hw->resus.ctrl, CLOCKS_CLK_SYS_RESUS_CTRL_CLEAR_BITS); in clocks_handle_resus()
[all …]
/hal_rpi_pico-3.4.0/src/rp2_common/hardware_xosc/
Dxosc.c29 xosc_hw->ctrl = XOSC_CTRL_FREQ_RANGE_VALUE_1_15MHZ; in xosc_init()
35 hw_set_bits(&xosc_hw->ctrl, XOSC_CTRL_ENABLE_VALUE_ENABLE << XOSC_CTRL_ENABLE_LSB); in xosc_init()
42 uint32_t tmp = xosc_hw->ctrl; in xosc_disable()
45 xosc_hw->ctrl = tmp; in xosc_disable()
/hal_rpi_pico-3.4.0/src/rp2_common/pico_fix/rp2040_usb_device_enumeration/
Drp2040_usb_device_enumeration.c95 gpio_ctrl_prev = iobank0_hw->io[dp].ctrl; in hw_enumeration_fix_force_ls_j()
104 hw_write_masked(&iobank0_hw->io[dp].ctrl, in hw_enumeration_fix_force_ls_j()
144 iobank0_hw->io[dp].ctrl = gpio_ctrl_prev; in hw_enumeration_fix_finish()
/hal_rpi_pico-3.4.0/src/rp2_common/hardware_rtc/
Drtc.c19 return (rtc_hw->ctrl & RTC_CTRL_RTC_ACTIVE_BITS); in rtc_running()
61 rtc_hw->ctrl = 0; in rtc_set_datetime()
77 rtc_hw->ctrl = RTC_CTRL_LOAD_BITS; in rtc_set_datetime()
80 rtc_hw->ctrl = RTC_CTRL_RTC_ENABLE_BITS; in rtc_set_datetime()
/hal_rpi_pico-3.4.0/src/rp2_common/hardware_gpio/
Dgpio.c42 iobank0_hw->io[gpio].ctrl = fn << IO_BANK0_GPIO0_CTRL_FUNCSEL_LSB; in gpio_set_function()
48 …return (enum gpio_function) ((iobank0_hw->io[gpio].ctrl & IO_BANK0_GPIO0_CTRL_FUNCSEL_BITS) >> IO_… in gpio_get_function()
65 hw_write_masked(&iobank0_hw->io[gpio].ctrl, in gpio_set_irqover()
74 hw_write_masked(&iobank0_hw->io[gpio].ctrl, in gpio_set_inover()
82 hw_write_masked(&iobank0_hw->io[gpio].ctrl, in gpio_set_outover()
90 hw_write_masked(&iobank0_hw->io[gpio].ctrl, in gpio_set_oeover()
/hal_rpi_pico-3.4.0/src/rp2040/hardware_structs/include/hardware/structs/
Dclocks.h52 io_rw_32 ctrl;
72 io_rw_32 ctrl;
Dwatchdog.h32 io_rw_32 ctrl;
Dmpu.h36 io_rw_32 ctrl;
Dxosc.h29 io_rw_32 ctrl;
Dinterp.h64 io_rw_32 ctrl[2];
Drosc.h28 io_rw_32 ctrl;
Diobank0.h43 io_rw_32 ctrl;
Dioqspi.h43 io_rw_32 ctrl;
Dxip_ctrl.h29 io_rw_32 ctrl;
Dusb.h100 io_rw_32 ctrl; member
109 io_rw_32 ctrl; member
Drtc.h50 io_rw_32 ctrl;
Dpio.h85 io_rw_32 ctrl;
/hal_rpi_pico-3.4.0/src/rp2_common/hardware_pio/include/hardware/
Dpio.h549 pio->ctrl = (pio->ctrl & ~(1u << sm)) | (bool_to_bit(enabled) << sm); in pio_sm_set_enabled()
568 pio->ctrl = (pio->ctrl & ~mask) | (enabled ? mask : 0u); in pio_set_sm_mask_enabled()
583 hw_set_bits(&pio->ctrl, 1u << (PIO_CTRL_SM_RESTART_LSB + sm)); in pio_sm_restart()
598 hw_set_bits(&pio->ctrl, (mask << PIO_CTRL_SM_RESTART_LSB) & PIO_CTRL_SM_RESTART_BITS); in pio_restart_sm_mask()
625 hw_set_bits(&pio->ctrl, 1u << (PIO_CTRL_CLKDIV_RESTART_LSB + sm)); in pio_sm_clkdiv_restart()
660 hw_set_bits(&pio->ctrl, (mask << PIO_CTRL_CLKDIV_RESTART_LSB) & PIO_CTRL_CLKDIV_RESTART_BITS); in pio_clkdiv_restart_sm_mask()
677 hw_set_bits(&pio->ctrl, in pio_enable_sm_mask_in_sync()
/hal_rpi_pico-3.4.0/src/rp2_common/pico_runtime/
Druntime.c47 if (mpu_hw->ctrl) { in runtime_install_stack_guard()
59 mpu_hw->ctrl = 5; // enable mpu with background default map in runtime_install_stack_guard()
/hal_rpi_pico-3.4.0/src/rp2_common/hardware_flash/
Dflash.c118 hw_write_masked(&ioqspi_hw->io[1].ctrl, in __no_inline_not_in_flash_func()

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