1 // THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
2 
3 /*
4  * Copyright (c) 2021 Raspberry Pi (Trading) Ltd.
5  *
6  * SPDX-License-Identifier: BSD-3-Clause
7  */
8 
9 #ifndef _HARDWARE_STRUCTS_XIP_CTRL_H
10 #define _HARDWARE_STRUCTS_XIP_CTRL_H
11 
12 #include "hardware/address_mapped.h"
13 #include "hardware/regs/xip.h"
14 
15 // Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_xip
16 //
17 // The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature)
18 // _REG_(x) will link to the corresponding register in hardware/regs/xip.h.
19 //
20 // Bit-field descriptions are of the form:
21 // BITMASK [BITRANGE]: FIELDNAME (RESETVALUE): DESCRIPTION
22 
23 typedef struct {
24     _REG_(XIP_CTRL_OFFSET) // XIP_CTRL
25     // Cache control
26     // 0x00000008 [3]     : POWER_DOWN (0): When 1, the cache memories are powered down
27     // 0x00000002 [1]     : ERR_BADWRITE (1): When 1, writes to any alias other than 0x0 (caching, allocating)
28     // 0x00000001 [0]     : EN (1): When 1, enable the cache
29     io_rw_32 ctrl;
30 
31     _REG_(XIP_FLUSH_OFFSET) // XIP_FLUSH
32     // Cache Flush control
33     // 0x00000001 [0]     : FLUSH (0): Write 1 to flush the cache
34     io_rw_32 flush;
35 
36     _REG_(XIP_STAT_OFFSET) // XIP_STAT
37     // Cache Status
38     // 0x00000004 [2]     : FIFO_FULL (0): When 1, indicates the XIP streaming FIFO is completely full
39     // 0x00000002 [1]     : FIFO_EMPTY (1): When 1, indicates the XIP streaming FIFO is completely empty
40     // 0x00000001 [0]     : FLUSH_READY (0): Reads as 0 while a cache flush is in progress, and 1 otherwise
41     io_ro_32 stat;
42 
43     _REG_(XIP_CTR_HIT_OFFSET) // XIP_CTR_HIT
44     // Cache Hit counter
45     io_rw_32 ctr_hit;
46 
47     _REG_(XIP_CTR_ACC_OFFSET) // XIP_CTR_ACC
48     // Cache Access counter
49     io_rw_32 ctr_acc;
50 
51     _REG_(XIP_STREAM_ADDR_OFFSET) // XIP_STREAM_ADDR
52     // FIFO stream address
53     // 0xfffffffc [31:2]  : STREAM_ADDR (0): The address of the next word to be streamed from flash to the streaming FIFO
54     io_rw_32 stream_addr;
55 
56     _REG_(XIP_STREAM_CTR_OFFSET) // XIP_STREAM_CTR
57     // FIFO stream control
58     // 0x003fffff [21:0]  : STREAM_CTR (0): Write a nonzero value to start a streaming read
59     io_rw_32 stream_ctr;
60 
61     _REG_(XIP_STREAM_FIFO_OFFSET) // XIP_STREAM_FIFO
62     // FIFO stream data
63     io_ro_32 stream_fifo;
64 } xip_ctrl_hw_t;
65 
66 #define xip_ctrl_hw ((xip_ctrl_hw_t *)XIP_CTRL_BASE)
67 
68 #define XIP_STAT_FIFO_FULL XIP_STAT_FIFO_FULL_BITS
69 #define XIP_STAT_FIFO_EMPTY XIP_STAT_FIFO_EMPTY_BITS
70 #define XIP_STAT_FLUSH_RDY XIP_STAT_FLUSH_READY_BITS
71 
72 #endif
73