| /hal_nxp-latest/mcux/mcux-sdk/drivers/acmp/ |
| D | fsl_acmp.c | 74 uint32_t tmp32; in ACMP_Init() local
87 … tmp32 = (base->C0 & (~(CMP_C0_PMODE_MASK | CMP_C0_INVT_MASK | CMP_C0_COS_MASK | CMP_C0_OPE_MASK | in ACMP_Init()
93 tmp32 &= ~CMP_C0_OFFSET_MASK; in ACMP_Init()
97 tmp32 |= CMP_C0_PMODE_MASK; in ACMP_Init()
101 tmp32 |= CMP_C0_INVT_MASK; in ACMP_Init()
105 tmp32 |= CMP_C0_COS_MASK; in ACMP_Init()
109 tmp32 |= CMP_C0_OPE_MASK; in ACMP_Init()
112 tmp32 |= CMP_C0_HYSTCTR(config->hysteresisMode); in ACMP_Init()
115 tmp32 |= CMP_C0_OFFSET(config->offsetMode); in ACMP_Init()
117 base->C0 = tmp32; in ACMP_Init()
[all …]
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| /hal_nxp-latest/mcux/mcux-sdk/drivers/dcdc_1/ |
| D | fsl_dcdc.c | 98 uint32_t tmp32 = base->CTRL0; in DCDC_Init() local
100 …tmp32 |= DCDC_CTRL0_CONTROL_MODE(config->controlMode) | DCDC_CTRL0_TRIM_HOLD(config->trimInputMode… in DCDC_Init()
104 tmp32 |= DCDC_CTRL0_ENABLE_DCDC_CNT_MASK; in DCDC_Init()
108 tmp32 |= DCDC_CTRL0_DIG_EN_MASK; in DCDC_Init()
111 base->CTRL0 = tmp32; in DCDC_Init()
202 uint32_t tmp32; in DCDC_SetClockSource() local
205 tmp32 = base->REG0 & ~(DCDC_REG0_XTAL_24M_OK_MASK | DCDC_REG0_DISABLE_AUTO_CLK_SWITCH_MASK | in DCDC_SetClockSource()
210 tmp32 |= DCDC_REG0_DISABLE_AUTO_CLK_SWITCH_MASK; in DCDC_SetClockSource()
214 …tmp32 |= DCDC_REG0_DISABLE_AUTO_CLK_SWITCH_MASK | DCDC_REG0_SEL_CLK_MASK | DCDC_REG0_PWD_OSC_INT_M… in DCDC_SetClockSource()
218 tmp32 |= DCDC_REG0_XTAL_24M_OK_MASK; in DCDC_SetClockSource()
[all …]
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| /hal_nxp-latest/mcux/mcux-sdk/components/flash/nor/ |
| D | fsl_sfdp_parser.c | 1068 uint32_t tmp32 = 0UL; in SFDP_GetSectorEraseCmdInfo() local
1072 tmp32 = handle->bfp.dw8; in SFDP_GetSectorEraseCmdInfo()
1076 tmp32 = handle->bfp.dw9; in SFDP_GetSectorEraseCmdInfo()
1079 tmp32 = (tmp32 >> (16UL * ((uint32_t)type % 2UL))) & 0xFFFFUL; in SFDP_GetSectorEraseCmdInfo()
1081 sizeFactor = tmp32 & 0xFFUL; in SFDP_GetSectorEraseCmdInfo()
1088 ptrEraseCmdInfo->instruction = (tmp32 & 0xFF00UL) >> 8UL; in SFDP_GetSectorEraseCmdInfo()
1095 tmp32 = (handle->bfp.dw10) >> 4UL; in SFDP_GetSectorEraseCmdInfo()
1096 tmp32 = (tmp32 >> (7UL * ((uint32_t)type % 2UL))) & 0x7FUL; in SFDP_GetSectorEraseCmdInfo()
1098 switch ((tmp32 & 0x60U) >> 5U) in SFDP_GetSectorEraseCmdInfo()
1102 ptrEraseCmdInfo->typicalTime = tmp32 & 0x1FUL; in SFDP_GetSectorEraseCmdInfo()
[all …]
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| /hal_nxp-latest/mcux/mcux-sdk/drivers/adc16/ |
| D | fsl_adc16.c | 68 uint32_t tmp32; in ADC16_Init() local
76 tmp32 = ADC_CFG1_ADICLK(config->clockSource) | ADC_CFG1_MODE(config->resolution); in ADC16_Init()
79 tmp32 |= ADC_CFG1_ADLSMP_MASK; in ADC16_Init()
81 tmp32 |= ADC_CFG1_ADIV(config->clockDivider); in ADC16_Init()
84 tmp32 |= ADC_CFG1_ADLPC_MASK; in ADC16_Init()
86 base->CFG1 = tmp32; in ADC16_Init()
89 tmp32 = base->CFG2 & ~(ADC_CFG2_ADACKEN_MASK | ADC_CFG2_ADHSC_MASK | ADC_CFG2_ADLSTS_MASK); in ADC16_Init()
92 tmp32 |= ADC_CFG2_ADLSTS(config->longSampleMode); in ADC16_Init()
96 tmp32 |= ADC_CFG2_ADHSC_MASK; in ADC16_Init()
100 tmp32 |= ADC_CFG2_ADACKEN_MASK; in ADC16_Init()
[all …]
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| /hal_nxp-latest/mcux/mcux-sdk/drivers/lpcmp/ |
| D | fsl_lpcmp.c | 104 uint32_t tmp32; in LPCMP_Init() local
138 …tmp32 = (base->CCR1 & (~(LPCMP_CCR1_COUT_PEN_MASK | LPCMP_CCR1_COUT_SEL_MASK | LPCMP_CCR1_COUT_INV… in LPCMP_Init()
146 tmp32 |= LPCMP_CCR1_COUT_PEN_MASK; in LPCMP_Init()
150 tmp32 |= LPCMP_CCR1_COUT_SEL_MASK; in LPCMP_Init()
154 tmp32 |= LPCMP_CCR1_COUT_INV_MASK; in LPCMP_Init()
157 tmp32 |= LPCMP_CCR1_FUNC_CLK_SEL(config->functionalSourceClock); in LPCMP_Init()
159 base->CCR1 = tmp32; in LPCMP_Init()
161 …tmp32 = base->CCR2 & ~(LPCMP_CCR2_HYSTCTR_MASK | LPCMP_CCR2_CMP_NPMD_MASK | LPCMP_CCR2_CMP_HPMD_MA… in LPCMP_Init()
162 tmp32 |= LPCMP_CCR2_HYSTCTR(config->hysteresisMode); in LPCMP_Init()
163 tmp32 |= ((uint32_t)(config->powerMode) << LPCMP_CCR2_CMP_HPMD_SHIFT); in LPCMP_Init()
[all …]
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| /hal_nxp-latest/mcux/mcux-sdk/drivers/lpc_adc/ |
| D | fsl_adc.c | 62 uint32_t tmp32 = 0U; in ADC_Init() local
77 tmp32 = ADC_CTRL_CLKDIV(config->clockDividerNumber); in ADC_Init()
84 tmp32 |= ADC_CTRL_ASYNMODE_MASK; in ADC_Init()
94 tmp32 |= ADC_CTRL_RESOL(config->resolution); in ADC_Init()
100 tmp32 |= ADC_CTRL_BYPASSCAL_MASK; in ADC_Init()
110 tmp32 |= ADC_CTRL_TSAMP(config->sampleTimeNumber); in ADC_Init()
118 tmp32 |= ADC_CTRL_LPWRMODE_MASK; in ADC_Init()
122 base->CTRL = tmp32; in ADC_Init()
134 tmp32 = *(uint32_t *)FSL_FEATURE_FLASH_ADDR_OF_TEMP_CAL; in ADC_Init()
135 if (tmp32 & FSL_FEATURE_FLASH_ADDR_OF_TEMP_CAL_VALID) in ADC_Init()
[all …]
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| /hal_nxp-latest/mcux/mcux-sdk/drivers/adc12/ |
| D | fsl_adc12.c | 141 uint32_t tmp32; in ADC12_Init() local
149 tmp32 = (base->CFG1 & ~(ADC_CFG1_ADICLK_MASK | ADC_CFG1_ADIV_MASK | ADC_CFG1_MODE_MASK)); in ADC12_Init()
150 tmp32 |= (ADC_CFG1_ADICLK(config->clockSource) | ADC_CFG1_ADIV(config->clockDivider) | in ADC12_Init()
152 base->CFG1 = tmp32; in ADC12_Init()
155 tmp32 = (base->CFG2 & ~ADC_CFG2_SMPLTS_MASK); in ADC12_Init()
156 tmp32 |= ADC_CFG2_SMPLTS(config->sampleClockCount - 1U); in ADC12_Init()
157 base->CFG2 = tmp32; in ADC12_Init()
160 tmp32 = (base->SC2 & ~ADC_SC2_REFSEL_MASK); in ADC12_Init()
161 tmp32 |= ADC_SC2_REFSEL(config->referenceVoltageSource); in ADC12_Init()
162 base->SC2 = tmp32; in ADC12_Init()
[all …]
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1172/drivers/ |
| D | fsl_dcdc.c | 98 uint32_t tmp32 = base->CTRL0; in DCDC_Init() local
100 …tmp32 |= DCDC_CTRL0_CONTROL_MODE(config->controlMode) | DCDC_CTRL0_TRIM_HOLD(config->trimInputMode… in DCDC_Init()
104 tmp32 |= DCDC_CTRL0_ENABLE_DCDC_CNT_MASK; in DCDC_Init()
108 tmp32 |= DCDC_CTRL0_DIG_EN_MASK; in DCDC_Init()
110 tmp32 |= DCDC_CTRL0_ENABLE_MASK; in DCDC_Init()
111 base->CTRL0 = tmp32; in DCDC_Init()
200 uint32_t tmp32; in DCDC_SetDetectionConfig() local
202 tmp32 = base->REG0 & in DCDC_SetDetectionConfig()
207 tmp32 |= DCDC_REG0_CUR_SNS_THRSH(config->PeakCurrentThreshold); in DCDC_SetDetectionConfig()
210 tmp32 |= DCDC_REG0_XTALOK_DISABLE_MASK; in DCDC_SetDetectionConfig()
[all …]
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1175/drivers/ |
| D | fsl_dcdc.c | 98 uint32_t tmp32 = base->CTRL0; in DCDC_Init() local
100 …tmp32 |= DCDC_CTRL0_CONTROL_MODE(config->controlMode) | DCDC_CTRL0_TRIM_HOLD(config->trimInputMode… in DCDC_Init()
104 tmp32 |= DCDC_CTRL0_ENABLE_DCDC_CNT_MASK; in DCDC_Init()
108 tmp32 |= DCDC_CTRL0_DIG_EN_MASK; in DCDC_Init()
110 tmp32 |= DCDC_CTRL0_ENABLE_MASK; in DCDC_Init()
111 base->CTRL0 = tmp32; in DCDC_Init()
200 uint32_t tmp32; in DCDC_SetDetectionConfig() local
202 tmp32 = base->REG0 & in DCDC_SetDetectionConfig()
207 tmp32 |= DCDC_REG0_CUR_SNS_THRSH(config->PeakCurrentThreshold); in DCDC_SetDetectionConfig()
210 tmp32 |= DCDC_REG0_XTALOK_DISABLE_MASK; in DCDC_SetDetectionConfig()
[all …]
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1165/drivers/ |
| D | fsl_dcdc.c | 98 uint32_t tmp32 = base->CTRL0; in DCDC_Init() local
100 …tmp32 |= DCDC_CTRL0_CONTROL_MODE(config->controlMode) | DCDC_CTRL0_TRIM_HOLD(config->trimInputMode… in DCDC_Init()
104 tmp32 |= DCDC_CTRL0_ENABLE_DCDC_CNT_MASK; in DCDC_Init()
108 tmp32 |= DCDC_CTRL0_DIG_EN_MASK; in DCDC_Init()
110 tmp32 |= DCDC_CTRL0_ENABLE_MASK; in DCDC_Init()
111 base->CTRL0 = tmp32; in DCDC_Init()
200 uint32_t tmp32; in DCDC_SetDetectionConfig() local
202 tmp32 = base->REG0 & in DCDC_SetDetectionConfig()
207 tmp32 |= DCDC_REG0_CUR_SNS_THRSH(config->PeakCurrentThreshold); in DCDC_SetDetectionConfig()
210 tmp32 |= DCDC_REG0_XTALOK_DISABLE_MASK; in DCDC_SetDetectionConfig()
[all …]
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1176/drivers/ |
| D | fsl_dcdc.c | 98 uint32_t tmp32 = base->CTRL0; in DCDC_Init() local
100 …tmp32 |= DCDC_CTRL0_CONTROL_MODE(config->controlMode) | DCDC_CTRL0_TRIM_HOLD(config->trimInputMode… in DCDC_Init()
104 tmp32 |= DCDC_CTRL0_ENABLE_DCDC_CNT_MASK; in DCDC_Init()
108 tmp32 |= DCDC_CTRL0_DIG_EN_MASK; in DCDC_Init()
110 tmp32 |= DCDC_CTRL0_ENABLE_MASK; in DCDC_Init()
111 base->CTRL0 = tmp32; in DCDC_Init()
200 uint32_t tmp32; in DCDC_SetDetectionConfig() local
202 tmp32 = base->REG0 & in DCDC_SetDetectionConfig()
207 tmp32 |= DCDC_REG0_CUR_SNS_THRSH(config->PeakCurrentThreshold); in DCDC_SetDetectionConfig()
210 tmp32 |= DCDC_REG0_XTALOK_DISABLE_MASK; in DCDC_SetDetectionConfig()
[all …]
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| D | fsl_gpc.c | 96 uint32_t tmp32 = *(uint32_t *)((uint32_t)base + s_cmRegOffset[step]); in GPC_CM_ConfigCpuModeTransitionStep() local
100 tmp32 &= ~(GPC_CPU_MODE_CTRL_CM_SLEEP_SSAR_CTRL_STEP_CNT_MASK | in GPC_CM_ConfigCpuModeTransitionStep()
102 tmp32 |= GPC_CPU_MODE_CTRL_CM_SLEEP_SSAR_CTRL_CNT_MODE(config->cntMode); in GPC_CM_ConfigCpuModeTransitionStep()
105 tmp32 |= GPC_CPU_MODE_CTRL_CM_SLEEP_SSAR_CTRL_STEP_CNT(config->stepCount); in GPC_CM_ConfigCpuModeTransitionStep()
107 tmp32 &= ~GPC_CPU_MODE_CTRL_CM_SLEEP_SSAR_CTRL_DISABLE_MASK; in GPC_CM_ConfigCpuModeTransitionStep()
111 tmp32 |= GPC_CPU_MODE_CTRL_CM_SLEEP_SSAR_CTRL_DISABLE_MASK; in GPC_CM_ConfigCpuModeTransitionStep()
113 *(uint32_t *)((uint32_t)base + s_cmRegOffset[step]) = tmp32; in GPC_CM_ConfigCpuModeTransitionStep()
133 uint32_t tmp32 = base->CM_SP_CTRL; in GPC_CM_RequestSleepModeSetPointTransition() local
135 …tmp32 &= ~(GPC_CPU_MODE_CTRL_CM_SP_CTRL_CPU_SP_RUN_EN_MASK | GPC_CPU_MODE_CTRL_CM_SP_CTRL_CPU_SP_S… in GPC_CM_RequestSleepModeSetPointTransition()
138 tmp32 |= in GPC_CM_RequestSleepModeSetPointTransition()
[all …]
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1173/drivers/ |
| D | fsl_dcdc.c | 98 uint32_t tmp32 = base->CTRL0; in DCDC_Init() local
100 …tmp32 |= DCDC_CTRL0_CONTROL_MODE(config->controlMode) | DCDC_CTRL0_TRIM_HOLD(config->trimInputMode… in DCDC_Init()
104 tmp32 |= DCDC_CTRL0_ENABLE_DCDC_CNT_MASK; in DCDC_Init()
108 tmp32 |= DCDC_CTRL0_DIG_EN_MASK; in DCDC_Init()
110 tmp32 |= DCDC_CTRL0_ENABLE_MASK; in DCDC_Init()
111 base->CTRL0 = tmp32; in DCDC_Init()
200 uint32_t tmp32; in DCDC_SetDetectionConfig() local
202 tmp32 = base->REG0 & in DCDC_SetDetectionConfig()
207 tmp32 |= DCDC_REG0_CUR_SNS_THRSH(config->PeakCurrentThreshold); in DCDC_SetDetectionConfig()
210 tmp32 |= DCDC_REG0_XTALOK_DISABLE_MASK; in DCDC_SetDetectionConfig()
[all …]
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1171/drivers/ |
| D | fsl_dcdc.c | 98 uint32_t tmp32 = base->CTRL0; in DCDC_Init() local
100 …tmp32 |= DCDC_CTRL0_CONTROL_MODE(config->controlMode) | DCDC_CTRL0_TRIM_HOLD(config->trimInputMode… in DCDC_Init()
104 tmp32 |= DCDC_CTRL0_ENABLE_DCDC_CNT_MASK; in DCDC_Init()
108 tmp32 |= DCDC_CTRL0_DIG_EN_MASK; in DCDC_Init()
110 tmp32 |= DCDC_CTRL0_ENABLE_MASK; in DCDC_Init()
111 base->CTRL0 = tmp32; in DCDC_Init()
200 uint32_t tmp32; in DCDC_SetDetectionConfig() local
202 tmp32 = base->REG0 & in DCDC_SetDetectionConfig()
207 tmp32 |= DCDC_REG0_CUR_SNS_THRSH(config->PeakCurrentThreshold); in DCDC_SetDetectionConfig()
210 tmp32 |= DCDC_REG0_XTALOK_DISABLE_MASK; in DCDC_SetDetectionConfig()
[all …]
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1166/drivers/ |
| D | fsl_dcdc.c | 98 uint32_t tmp32 = base->CTRL0; in DCDC_Init() local
100 …tmp32 |= DCDC_CTRL0_CONTROL_MODE(config->controlMode) | DCDC_CTRL0_TRIM_HOLD(config->trimInputMode… in DCDC_Init()
104 tmp32 |= DCDC_CTRL0_ENABLE_DCDC_CNT_MASK; in DCDC_Init()
108 tmp32 |= DCDC_CTRL0_DIG_EN_MASK; in DCDC_Init()
110 tmp32 |= DCDC_CTRL0_ENABLE_MASK; in DCDC_Init()
111 base->CTRL0 = tmp32; in DCDC_Init()
200 uint32_t tmp32; in DCDC_SetDetectionConfig() local
202 tmp32 = base->REG0 & in DCDC_SetDetectionConfig()
207 tmp32 |= DCDC_REG0_CUR_SNS_THRSH(config->PeakCurrentThreshold); in DCDC_SetDetectionConfig()
210 tmp32 |= DCDC_REG0_XTALOK_DISABLE_MASK; in DCDC_SetDetectionConfig()
[all …]
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| /hal_nxp-latest/mcux/mcux-sdk/drivers/adc_12b1msps_sar/ |
| D | fsl_adc.c | 68 uint32_t tmp32; in ADC_Init() local
75 tmp32 = base->CFG & (ADC_CFG_AVGS_MASK | ADC_CFG_ADTRG_MASK); /* Reserve AVGS and ADTRG bits. */ in ADC_Init()
76 …tmp32 |= ADC_CFG_REFSEL(config->referenceVoltageSource) | ADC_CFG_ADSTS(config->samplePeriodMode) | in ADC_Init()
80 tmp32 |= ADC_CFG_OVWREN_MASK; in ADC_Init()
84 tmp32 |= ADC_CFG_ADLSMP_MASK; in ADC_Init()
88 tmp32 |= ADC_CFG_ADLPC_MASK; in ADC_Init()
92 tmp32 |= ADC_CFG_ADHSC_MASK; in ADC_Init()
94 base->CFG = tmp32; in ADC_Init()
97 tmp32 = base->GC & ~(ADC_GC_ADCO_MASK | ADC_GC_ADACKEN_MASK); in ADC_Init()
100 tmp32 |= ADC_GC_ADCO_MASK; in ADC_Init()
[all …]
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| /hal_nxp-latest/mcux/mcux-sdk/drivers/spm/ |
| D | fsl_spm.c | 28 …volatile uint32_t tmp32 = base->RSR; /* volatile here is to make sure this value is actually from … in SPM_GetRegulatorStatus() local
31 …(spm_mcu_low_power_mode_status_t)(uint32_t)((tmp32 & SPM_RSR_MCUPMSTAT_MASK) >> SPM_RSR_MCUPMSTAT_… in SPM_GetRegulatorStatus()
33 …(0x4UL == (0x4UL & ((tmp32 & SPM_RSR_REGSEL_MASK) >> SPM_RSR_REGSEL_SHIFT))); /* 1<<2 responses DC… in SPM_GetRegulatorStatus()
35 …(0x2UL == (0x2UL & ((tmp32 & SPM_RSR_REGSEL_MASK) >> SPM_RSR_REGSEL_SHIFT))); /* 1<<1 responses AU… in SPM_GetRegulatorStatus()
37 …(0x1UL == (0x1UL & ((tmp32 & SPM_RSR_REGSEL_MASK) >> SPM_RSR_REGSEL_SHIFT))); /* 1<<0 responses CO… in SPM_GetRegulatorStatus()
51 …uint32_t tmp32 = base->LVDSC1 & ~(SPM_LVDSC1_VDD_LVDIE_MASK | SPM_LVDSC1_VDD_LVDRE_MASK | SPM_LVDS… in SPM_SetLowVoltDetectConfig() local
55 tmp32 |= SPM_LVDSC1_VDD_LVDV(config->vddLowVoltDetectSelect); in SPM_SetLowVoltDetectConfig()
58 tmp32 |= SPM_LVDSC1_VDD_LVDIE_MASK; in SPM_SetLowVoltDetectConfig()
62 tmp32 |= SPM_LVDSC1_VDD_LVDRE_MASK; in SPM_SetLowVoltDetectConfig()
65 tmp32 |= SPM_LVDSC1_VDD_LVDACK_MASK; in SPM_SetLowVoltDetectConfig()
[all …]
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1181/drivers/ |
| D | fsl_dcdc.c | 72 uint32_t tmp32 = base->CTRL0; in DCDC_Init() local
73 tmp32 &= ~(DCDC_CTRL0_TRG_GPC_EN_MASK | DCDC_CTRL0_TRIM_HOLD_MASK); in DCDC_Init()
74 … tmp32 |= DCDC_CTRL0_TRG_GPC_EN(config->controlMode) | DCDC_CTRL0_TRIM_HOLD(config->trimInputMode); in DCDC_Init()
75 base->CTRL0 = tmp32; in DCDC_Init()
157 uint32_t tmp32; in DCDC_SetDetectionConfig() local
159 tmp32 = base->REG0 & in DCDC_SetDetectionConfig()
165 tmp32 |= DCDC_REG0_XTALOK_DISABLE_MASK; in DCDC_SetDetectionConfig()
169 tmp32 |= DCDC_REG0_PWD_HIGH_VDD1P8_DET_MASK; in DCDC_SetDetectionConfig()
173 tmp32 |= DCDC_REG0_PWD_HIGH_VDD1P0_DET_MASK; in DCDC_SetDetectionConfig()
177 tmp32 |= DCDC_REG0_PWD_CMP_DCDC_IN_DET_MASK; in DCDC_SetDetectionConfig()
[all …]
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1189/drivers/ |
| D | fsl_dcdc.c | 72 uint32_t tmp32 = base->CTRL0; in DCDC_Init() local
73 tmp32 &= ~(DCDC_CTRL0_TRG_GPC_EN_MASK | DCDC_CTRL0_TRIM_HOLD_MASK); in DCDC_Init()
74 … tmp32 |= DCDC_CTRL0_TRG_GPC_EN(config->controlMode) | DCDC_CTRL0_TRIM_HOLD(config->trimInputMode); in DCDC_Init()
75 base->CTRL0 = tmp32; in DCDC_Init()
157 uint32_t tmp32; in DCDC_SetDetectionConfig() local
159 tmp32 = base->REG0 & in DCDC_SetDetectionConfig()
165 tmp32 |= DCDC_REG0_XTALOK_DISABLE_MASK; in DCDC_SetDetectionConfig()
169 tmp32 |= DCDC_REG0_PWD_HIGH_VDD1P8_DET_MASK; in DCDC_SetDetectionConfig()
173 tmp32 |= DCDC_REG0_PWD_HIGH_VDD1P0_DET_MASK; in DCDC_SetDetectionConfig()
177 tmp32 |= DCDC_REG0_PWD_CMP_DCDC_IN_DET_MASK; in DCDC_SetDetectionConfig()
[all …]
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1182/drivers/ |
| D | fsl_dcdc.c | 72 uint32_t tmp32 = base->CTRL0; in DCDC_Init() local
73 tmp32 &= ~(DCDC_CTRL0_TRG_GPC_EN_MASK | DCDC_CTRL0_TRIM_HOLD_MASK); in DCDC_Init()
74 … tmp32 |= DCDC_CTRL0_TRG_GPC_EN(config->controlMode) | DCDC_CTRL0_TRIM_HOLD(config->trimInputMode); in DCDC_Init()
75 base->CTRL0 = tmp32; in DCDC_Init()
157 uint32_t tmp32; in DCDC_SetDetectionConfig() local
159 tmp32 = base->REG0 & in DCDC_SetDetectionConfig()
165 tmp32 |= DCDC_REG0_XTALOK_DISABLE_MASK; in DCDC_SetDetectionConfig()
169 tmp32 |= DCDC_REG0_PWD_HIGH_VDD1P8_DET_MASK; in DCDC_SetDetectionConfig()
173 tmp32 |= DCDC_REG0_PWD_HIGH_VDD1P0_DET_MASK; in DCDC_SetDetectionConfig()
177 tmp32 |= DCDC_REG0_PWD_CMP_DCDC_IN_DET_MASK; in DCDC_SetDetectionConfig()
[all …]
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1187/drivers/ |
| D | fsl_dcdc.c | 72 uint32_t tmp32 = base->CTRL0; in DCDC_Init() local
73 tmp32 &= ~(DCDC_CTRL0_TRG_GPC_EN_MASK | DCDC_CTRL0_TRIM_HOLD_MASK); in DCDC_Init()
74 … tmp32 |= DCDC_CTRL0_TRG_GPC_EN(config->controlMode) | DCDC_CTRL0_TRIM_HOLD(config->trimInputMode); in DCDC_Init()
75 base->CTRL0 = tmp32; in DCDC_Init()
157 uint32_t tmp32; in DCDC_SetDetectionConfig() local
159 tmp32 = base->REG0 & in DCDC_SetDetectionConfig()
165 tmp32 |= DCDC_REG0_XTALOK_DISABLE_MASK; in DCDC_SetDetectionConfig()
169 tmp32 |= DCDC_REG0_PWD_HIGH_VDD1P8_DET_MASK; in DCDC_SetDetectionConfig()
173 tmp32 |= DCDC_REG0_PWD_HIGH_VDD1P0_DET_MASK; in DCDC_SetDetectionConfig()
177 tmp32 |= DCDC_REG0_PWD_CMP_DCDC_IN_DET_MASK; in DCDC_SetDetectionConfig()
[all …]
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| /hal_nxp-latest/mcux/mcux-sdk/drivers/rtc/ |
| D | fsl_rtc.c | 407 uint32_t tmp32 = 0U; in RTC_EnableInterrupts() local
412 tmp32 |= RTC_IER_TIIE_MASK; in RTC_EnableInterrupts()
416 tmp32 |= RTC_IER_TOIE_MASK; in RTC_EnableInterrupts()
420 tmp32 |= RTC_IER_TAIE_MASK; in RTC_EnableInterrupts()
424 tmp32 |= RTC_IER_TSIE_MASK; in RTC_EnableInterrupts()
429 tmp32 |= RTC_IER_MOIE_MASK; in RTC_EnableInterrupts()
432 base->IER |= tmp32; in RTC_EnableInterrupts()
435 tmp32 = 0U; in RTC_EnableInterrupts()
440 tmp32 |= RTC_TIR_TMIE_MASK; in RTC_EnableInterrupts()
444 tmp32 |= RTC_TIR_FSIE_MASK; in RTC_EnableInterrupts()
[all …]
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| /hal_nxp-latest/mcux/mcux-sdk/drivers/lpc_freqme/ |
| D | fsl_freqme.h | 155 uint32_t tmp32; in FREQME_StartMeasurementCycle() local
157 tmp32 = base->CTRLSTAT; in FREQME_StartMeasurementCycle()
158 tmp32 &= ~(FREQME_CTRLSTAT_LT_MIN_STAT_MASK | FREQME_CTRLSTAT_MEASURE_IN_PROGRESS_MASK | in FREQME_StartMeasurementCycle()
160 tmp32 |= FREQME_CTRL_W_MEASURE_IN_PROGRESS_MASK; in FREQME_StartMeasurementCycle()
161 base->CTRL_W = tmp32; in FREQME_StartMeasurementCycle()
172 uint32_t tmp32; in FREQME_TerminateMeasurementCycle() local
174 tmp32 = base->CTRLSTAT; in FREQME_TerminateMeasurementCycle()
175 tmp32 &= ~(FREQME_CTRLSTAT_LT_MIN_STAT_MASK | FREQME_CTRLSTAT_MEASURE_IN_PROGRESS_MASK | in FREQME_TerminateMeasurementCycle()
177 base->CTRL_W = tmp32; in FREQME_TerminateMeasurementCycle()
190 uint32_t tmp32; in FREQME_EnableContinuousMode() local
[all …]
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| /hal_nxp-latest/mcux/mcux-sdk/drivers/lpadc/ |
| D | fsl_lpadc.c | 125 uint32_t tmp32 = 0U; in LPADC_GetGainConvResult() local
131 …tmp32 = (uint32_t)((gainAdjustment) / ((float)(1.0 / (double)(1U << (0x10U - (i - 1U)))))… in LPADC_GetGainConvResult()
132 GCRa[i - 1U] = tmp32; in LPADC_GetGainConvResult()
133 …gainAdjustment = gainAdjustment - ((float)tmp32) * ((float)(1.0 / (double)(1U << (0x10U - (i - 1U)… in LPADC_GetGainConvResult()
157 uint32_t tmp32 = 0U; in LPADC_Init() local
199 tmp32 |= ADC_CFG_ADCKEN_MASK; in LPADC_Init()
205 tmp32 |= ADC_CFG_VREF1RNG_MASK; in LPADC_Init()
210 tmp32 |= ADC_CFG_PWREN_MASK; in LPADC_Init()
212 tmp32 |= (ADC_CFG_PUDLY(config->powerUpDelay) /* Power up delay. */ in LPADC_Init()
219 tmp32 |= ADC_CFG_TPRICTRL(GET_ADC_CFG_TPRICTRL_VALUE(config->triggerPriorityPolicy)); in LPADC_Init()
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| /hal_nxp-latest/mcux/mcux-sdk/drivers/cns_adc/ |
| D | fsl_adc.c | 77 uint32_t tmp32; in ADC_Init() local
84 tmp32 = base->ADC_REG_CONFIG; in ADC_Init()
85 tmp32 &= in ADC_Init()
88 tmp32 |= ADC_ADC_REG_CONFIG_CONT_CONV_EN(config->conversionMode) | in ADC_Init()
92 …tmp32 |= ADC_ADC_REG_CONFIG_TRIGGER_EN_MASK | ADC_ADC_REG_CONFIG_TRIGGER_SEL(config->triggerSource… in ADC_Init()
94 base->ADC_REG_CONFIG = tmp32; in ADC_Init()
96 tmp32 = base->ADC_REG_INTERVAL; in ADC_Init()
99 tmp32 |= ADC_ADC_REG_INTERVAL_BYPASS_WARMUP_MASK; in ADC_Init()
103 tmp32 = in ADC_Init()
104 …(tmp32 & ~(ADC_ADC_REG_INTERVAL_WARMUP_TIME_MASK)) | ADC_ADC_REG_INTERVAL_WARMUP_TIME(config->warm… in ADC_Init()
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