72     uint32_t tmp32 = base->CTRL0;  in DCDC_Init()  local
73     tmp32 &= ~(DCDC_CTRL0_TRG_GPC_EN_MASK | DCDC_CTRL0_TRIM_HOLD_MASK);  in DCDC_Init()
74 … tmp32 |= DCDC_CTRL0_TRG_GPC_EN(config->controlMode) | DCDC_CTRL0_TRIM_HOLD(config->trimInputMode);  in DCDC_Init()
75     base->CTRL0 = tmp32;  in DCDC_Init()
157     uint32_t tmp32;  in DCDC_SetDetectionConfig()  local
159     tmp32 = base->REG0 &  in DCDC_SetDetectionConfig()
165         tmp32 |= DCDC_REG0_XTALOK_DISABLE_MASK;  in DCDC_SetDetectionConfig()
169         tmp32 |= DCDC_REG0_PWD_HIGH_VDD1P8_DET_MASK;  in DCDC_SetDetectionConfig()
173         tmp32 |= DCDC_REG0_PWD_HIGH_VDD1P0_DET_MASK;  in DCDC_SetDetectionConfig()
177         tmp32 |= DCDC_REG0_PWD_CMP_DCDC_IN_DET_MASK;  in DCDC_SetDetectionConfig()
181         tmp32 |= DCDC_REG0_PWD_OVERCUR_DET_MASK;  in DCDC_SetDetectionConfig()
183     base->REG0 = tmp32;  in DCDC_SetDetectionConfig()
194     uint32_t tmp32;  in DCDC_SetClockSource()  local
197     tmp32 = base->REG0 & ~(DCDC_REG0_XTAL_24M_OK_MASK | DCDC_REG0_DISABLE_AUTO_CLK_SWITCH_MASK |  in DCDC_SetClockSource()
202             tmp32 |= DCDC_REG0_DISABLE_AUTO_CLK_SWITCH_MASK;  in DCDC_SetClockSource()
206 …tmp32 |= DCDC_REG0_DISABLE_AUTO_CLK_SWITCH_MASK | DCDC_REG0_SEL_CLK_MASK | DCDC_REG0_PWD_OSC_INT_M…  in DCDC_SetClockSource()
210             tmp32 |= DCDC_REG0_XTAL_24M_OK_MASK;  in DCDC_SetClockSource()
216     base->REG0 = tmp32;  in DCDC_SetClockSource()
264     uint32_t tmp32;  in DCDC_SetLoopControlConfig()  local
267     tmp32 = base->REG1 & ~(DCDC_REG1_LOOPCTRL_EN_DF_HYST_MASK | DCDC_REG1_LOOPCTRL_EN_CM_HYST_MASK |  in DCDC_SetLoopControlConfig()
271         tmp32 |= DCDC_REG1_LOOPCTRL_EN_CM_HYST_MASK;  in DCDC_SetLoopControlConfig()
275         tmp32 |= DCDC_REG1_LOOPCTRL_CM_HST_THRESH_MASK;  in DCDC_SetLoopControlConfig()
279         tmp32 |= DCDC_REG1_LOOPCTRL_EN_DF_HYST_MASK;  in DCDC_SetLoopControlConfig()
283         tmp32 |= DCDC_REG1_LOOPCTRL_DF_HST_THRESH_MASK;  in DCDC_SetLoopControlConfig()
286     base->REG1 = tmp32;  in DCDC_SetLoopControlConfig()
289 … tmp32 = base->REG2 & ~(DCDC_REG2_LOOPCTRL_HYST_SIGN_MASK | DCDC_REG2_LOOPCTRL_RCSCALE_THRSH_MASK |  in DCDC_SetLoopControlConfig()
292     tmp32 |= DCDC_REG2_LOOPCTRL_DC_FF(config->complementFeedForwardStep) |  in DCDC_SetLoopControlConfig()
298         tmp32 |= DCDC_REG2_LOOPCTRL_HYST_SIGN_MASK;  in DCDC_SetLoopControlConfig()
302         tmp32 |= DCDC_REG2_LOOPCTRL_RCSCALE_THRSH_MASK;  in DCDC_SetLoopControlConfig()
304     base->REG2 = tmp32;  in DCDC_SetLoopControlConfig()
317     uint32_t tmp32;  in DCDC_SetInternalRegulatorConfig()  local
319     tmp32 = base->REG3 & ~DCDC_REG3_REG_FBK_SEL_MASK;  in DCDC_SetInternalRegulatorConfig()
320     tmp32 |= DCDC_REG3_REG_FBK_SEL(config->feedbackPoint);  in DCDC_SetInternalRegulatorConfig()
321     base->REG3 = tmp32;  in DCDC_SetInternalRegulatorConfig()