98     uint32_t tmp32 = base->CTRL0;  in DCDC_Init()  local
100 …tmp32 |= DCDC_CTRL0_CONTROL_MODE(config->controlMode) | DCDC_CTRL0_TRIM_HOLD(config->trimInputMode…  in DCDC_Init()
104         tmp32 |= DCDC_CTRL0_ENABLE_DCDC_CNT_MASK;  in DCDC_Init()
108         tmp32 |= DCDC_CTRL0_DIG_EN_MASK;  in DCDC_Init()
111     base->CTRL0 = tmp32;  in DCDC_Init()
202     uint32_t tmp32;  in DCDC_SetClockSource()  local
205     tmp32 = base->REG0 & ~(DCDC_REG0_XTAL_24M_OK_MASK | DCDC_REG0_DISABLE_AUTO_CLK_SWITCH_MASK |  in DCDC_SetClockSource()
210             tmp32 |= DCDC_REG0_DISABLE_AUTO_CLK_SWITCH_MASK;  in DCDC_SetClockSource()
214 …tmp32 |= DCDC_REG0_DISABLE_AUTO_CLK_SWITCH_MASK | DCDC_REG0_SEL_CLK_MASK | DCDC_REG0_PWD_OSC_INT_M…  in DCDC_SetClockSource()
218             tmp32 |= DCDC_REG0_XTAL_24M_OK_MASK;  in DCDC_SetClockSource()
224     base->REG0 = tmp32;  in DCDC_SetClockSource()
277     uint32_t tmp32;  in DCDC_SetDetectionConfig()  local
279     tmp32 = base->REG0 & ~(DCDC_REG0_XTALOK_DISABLE_MASK  in DCDC_SetDetectionConfig()
293     tmp32 |= DCDC_REG0_CUR_SNS_THRSH(config->PeakCurrentThreshold) |  in DCDC_SetDetectionConfig()
297         tmp32 |= DCDC_REG0_XTALOK_DISABLE_MASK;  in DCDC_SetDetectionConfig()
302         tmp32 |= DCDC_REG0_PWD_HIGH_VDD1P8_DET_MASK;  in DCDC_SetDetectionConfig()
306         tmp32 |= DCDC_REG0_PWD_HIGH_VDD1P0_DET_MASK;  in DCDC_SetDetectionConfig()
311         tmp32 |= DCDC_REG0_PWD_HIGH_VOLT_DET_MASK;  in DCDC_SetDetectionConfig()
317         tmp32 |= DCDC_REG0_PWD_CMP_DCDC_IN_DET_MASK;  in DCDC_SetDetectionConfig()
319         tmp32 |= DCDC_REG0_PWD_CMP_BATT_DET_MASK;  in DCDC_SetDetectionConfig()
324         tmp32 |= DCDC_REG0_PWD_OVERCUR_DET_MASK;  in DCDC_SetDetectionConfig()
328         tmp32 |= DCDC_REG0_PWD_CUR_SNS_CMP_MASK;  in DCDC_SetDetectionConfig()
332         tmp32 |= DCDC_REG0_PWD_ZCD_MASK;  in DCDC_SetDetectionConfig()
334     base->REG0 = tmp32;  in DCDC_SetDetectionConfig()
375     uint32_t tmp32;  in DCDC_SetLowPowerConfig()  local
377     tmp32 = base->REG0 &  in DCDC_SetLowPowerConfig()
383     tmp32 |= DCDC_REG0_LP_OVERLOAD_FREQ_SEL(config->countChargingTimePeriod) |  in DCDC_SetLowPowerConfig()
388         tmp32 |= DCDC_REG0_EN_LP_OVERLOAD_SNS_MASK;  in DCDC_SetLowPowerConfig()
393         tmp32 |= DCDC_REG0_LP_HIGH_HYS_MASK;  in DCDC_SetLowPowerConfig()
395     base->REG0 = tmp32;  in DCDC_SetLowPowerConfig()
406     uint32_t tmp32 = 0U;  in DCDC_GetstatusFlags()  local
410         tmp32 |= (uint32_t)kDCDC_LockedOKStatus;  in DCDC_GetstatusFlags()
413     return tmp32;  in DCDC_GetstatusFlags()
477     uint32_t tmp32;  in DCDC_SetLoopControlConfig()  local
482     tmp32 = base->REG1 & ~(DCDC_REG1_LOOPCTRL_EN_DF_HYST_MASK | DCDC_REG1_LOOPCTRL_EN_CM_HYST_MASK |  in DCDC_SetLoopControlConfig()
486         tmp32 |= DCDC_REG1_LOOPCTRL_EN_CM_HYST_MASK;  in DCDC_SetLoopControlConfig()
490         tmp32 |= DCDC_REG1_LOOPCTRL_CM_HST_THRESH_MASK;  in DCDC_SetLoopControlConfig()
494         tmp32 |= DCDC_REG1_LOOPCTRL_EN_DF_HYST_MASK;  in DCDC_SetLoopControlConfig()
498         tmp32 |= DCDC_REG1_LOOPCTRL_DF_HST_THRESH_MASK;  in DCDC_SetLoopControlConfig()
501     tmp32 = base->REG1 & ~(DCDC_REG1_LOOPCTRL_EN_HYST_MASK | DCDC_REG1_LOOPCTRL_HST_THRESH_MASK);  in DCDC_SetLoopControlConfig()
504         tmp32 |= DCDC_REG1_LOOPCTRL_EN_HYST_MASK;  in DCDC_SetLoopControlConfig()
508         tmp32 |= DCDC_REG1_LOOPCTRL_HST_THRESH_MASK;  in DCDC_SetLoopControlConfig()
511     base->REG1 = tmp32;  in DCDC_SetLoopControlConfig()
514 … tmp32 = base->REG2 & ~(DCDC_REG2_LOOPCTRL_HYST_SIGN_MASK | DCDC_REG2_LOOPCTRL_RCSCALE_THRSH_MASK |  in DCDC_SetLoopControlConfig()
516     tmp32 |= DCDC_REG2_LOOPCTRL_DC_FF(config->complementFeedForwardStep) |  in DCDC_SetLoopControlConfig()
520         tmp32 |= DCDC_REG2_LOOPCTRL_HYST_SIGN_MASK;  in DCDC_SetLoopControlConfig()
524         tmp32 |= DCDC_REG2_LOOPCTRL_RCSCALE_THRSH_MASK;  in DCDC_SetLoopControlConfig()
526     base->REG2 = tmp32;  in DCDC_SetLoopControlConfig()
539     uint32_t tmp32;  in DCDC_SetMinPowerConfig()  local
541     tmp32 = base->REG3 & ~DCDC_REG3_MINPWR_DC_HALFCLK_MASK;  in DCDC_SetMinPowerConfig()
544         tmp32 |= DCDC_REG3_MINPWR_DC_HALFCLK_MASK;  in DCDC_SetMinPowerConfig()
546     base->REG3 = tmp32;  in DCDC_SetMinPowerConfig()
567     uint32_t tmp32;  in DCDC_AdjustTargetVoltage()  local
575 …     tmp32 = base->CTRL1 & ~(DCDC_CTRL1_VDD1P8CTRL_STBY_TRG_MASK | DCDC_CTRL1_VDD1P8CTRL_TRG_MASK);  in DCDC_AdjustTargetVoltage()
577         tmp32 |= DCDC_CTRL1_VDD1P8CTRL_STBY_TRG(VDDStandby) | DCDC_CTRL1_VDD1P8CTRL_TRG(VDDRun);  in DCDC_AdjustTargetVoltage()
578         base->CTRL1 = tmp32;  in DCDC_AdjustTargetVoltage()
586 …     tmp32 = base->CTRL1 & ~(DCDC_CTRL1_VDD1P0CTRL_STBY_TRG_MASK | DCDC_CTRL1_VDD1P0CTRL_TRG_MASK);  in DCDC_AdjustTargetVoltage()
588         tmp32 |= DCDC_CTRL1_VDD1P0CTRL_STBY_TRG(VDDStandby) | DCDC_CTRL1_VDD1P0CTRL_TRG(VDDRun);  in DCDC_AdjustTargetVoltage()
589         base->CTRL1 = tmp32;  in DCDC_AdjustTargetVoltage()
617     uint32_t tmp32;  in DCDC_AdjustRunTargetVoltage()  local
625         tmp32 = base->CTRL1 & ~DCDC_CTRL1_VDD1P8CTRL_TRG_MASK;  in DCDC_AdjustRunTargetVoltage()
627         tmp32 |= DCDC_CTRL1_VDD1P8CTRL_TRG(VDDRun);  in DCDC_AdjustRunTargetVoltage()
628         base->CTRL1 = tmp32;  in DCDC_AdjustRunTargetVoltage()
636         tmp32 = base->CTRL1 & ~DCDC_CTRL1_VDD1P0CTRL_TRG_MASK;  in DCDC_AdjustRunTargetVoltage()
638         tmp32 |= DCDC_CTRL1_VDD1P0CTRL_TRG(VDDRun);  in DCDC_AdjustRunTargetVoltage()
639         base->CTRL1 = tmp32;  in DCDC_AdjustRunTargetVoltage()
667     uint32_t tmp32;  in DCDC_AdjustLowPowerTargetVoltage()  local
675         tmp32 = base->CTRL1 & ~(DCDC_CTRL1_VDD1P8CTRL_STBY_TRG_MASK);  in DCDC_AdjustLowPowerTargetVoltage()
677         tmp32 |= DCDC_CTRL1_VDD1P8CTRL_STBY_TRG(VDDStandby);  in DCDC_AdjustLowPowerTargetVoltage()
678         base->CTRL1 = tmp32;  in DCDC_AdjustLowPowerTargetVoltage()
686         tmp32 = base->CTRL1 & ~(DCDC_CTRL1_VDD1P0CTRL_STBY_TRG_MASK);  in DCDC_AdjustLowPowerTargetVoltage()
688         tmp32 |= DCDC_CTRL1_VDD1P0CTRL_STBY_TRG(VDDStandby);  in DCDC_AdjustLowPowerTargetVoltage()
689         base->CTRL1 = tmp32;  in DCDC_AdjustLowPowerTargetVoltage()
720     uint32_t tmp32;  in DCDC_AdjustTargetVoltage()  local
726     tmp32 = base->REG3 & ~(DCDC_REG3_TARGET_LP_MASK | DCDC_REG3_TRG_MASK);  in DCDC_AdjustTargetVoltage()
728     tmp32 |= DCDC_REG3_TARGET_LP(VDDStandby) | DCDC_REG3_TRG(VDDRun);  in DCDC_AdjustTargetVoltage()
729     base->REG3 = tmp32;  in DCDC_AdjustTargetVoltage()
751     uint32_t tmp32;  in DCDC_AdjustRunTargetVoltage()  local
757     tmp32 = base->REG3 & ~DCDC_REG3_TRG_MASK;  in DCDC_AdjustRunTargetVoltage()
759     tmp32 |= DCDC_REG3_TRG(VDDRun);  in DCDC_AdjustRunTargetVoltage()
760     base->REG3 = tmp32;  in DCDC_AdjustRunTargetVoltage()
782     uint32_t tmp32;  in DCDC_AdjustLowPowerTargetVoltage()  local
788     tmp32 = base->REG3 & ~DCDC_REG3_TARGET_LP_MASK;  in DCDC_AdjustLowPowerTargetVoltage()
790     tmp32 |= DCDC_REG3_TARGET_LP(VDDStandby);  in DCDC_AdjustLowPowerTargetVoltage()
791     base->REG3 = tmp32;  in DCDC_AdjustLowPowerTargetVoltage()
811     uint32_t tmp32;  in DCDC_SetInternalRegulatorConfig()  local
814     tmp32 = base->REG3 & ~DCDC_REG3_REG_FBK_SEL_MASK;  in DCDC_SetInternalRegulatorConfig()
815     tmp32 |= DCDC_REG3_REG_FBK_SEL(config->feedbackPoint);  in DCDC_SetInternalRegulatorConfig()
816     base->REG3 = tmp32;  in DCDC_SetInternalRegulatorConfig()
818     tmp32 = base->REG1 & ~DCDC_REG1_REG_RLOAD_SW_MASK;  in DCDC_SetInternalRegulatorConfig()
821     tmp32 = base->REG1 & ~(DCDC_REG1_REG_FBK_SEL_MASK | DCDC_REG1_REG_RLOAD_SW_MASK);  in DCDC_SetInternalRegulatorConfig()
822     tmp32 |= DCDC_REG1_REG_FBK_SEL(config->feedbackPoint);  in DCDC_SetInternalRegulatorConfig()
827         tmp32 |= DCDC_REG1_REG_RLOAD_SW_MASK;  in DCDC_SetInternalRegulatorConfig()
829     base->REG1 = tmp32;  in DCDC_SetInternalRegulatorConfig()