98     uint32_t tmp32 = base->CTRL0;  in DCDC_Init()  local
100 …tmp32 |= DCDC_CTRL0_CONTROL_MODE(config->controlMode) | DCDC_CTRL0_TRIM_HOLD(config->trimInputMode…  in DCDC_Init()
104         tmp32 |= DCDC_CTRL0_ENABLE_DCDC_CNT_MASK;  in DCDC_Init()
108         tmp32 |= DCDC_CTRL0_DIG_EN_MASK;  in DCDC_Init()
110     tmp32 |= DCDC_CTRL0_ENABLE_MASK;  in DCDC_Init()
111     base->CTRL0 = tmp32;  in DCDC_Init()
200     uint32_t tmp32;  in DCDC_SetDetectionConfig()  local
202     tmp32 = base->REG0 &  in DCDC_SetDetectionConfig()
207     tmp32 |= DCDC_REG0_CUR_SNS_THRSH(config->PeakCurrentThreshold);  in DCDC_SetDetectionConfig()
210         tmp32 |= DCDC_REG0_XTALOK_DISABLE_MASK;  in DCDC_SetDetectionConfig()
214         tmp32 |= DCDC_REG0_PWD_HIGH_VDD1P8_DET_MASK;  in DCDC_SetDetectionConfig()
218         tmp32 |= DCDC_REG0_PWD_HIGH_VDD1P0_DET_MASK;  in DCDC_SetDetectionConfig()
222         tmp32 |= DCDC_REG0_PWD_CMP_DCDC_IN_DET_MASK;  in DCDC_SetDetectionConfig()
226         tmp32 |= DCDC_REG0_PWD_OVERCUR_DET_MASK;  in DCDC_SetDetectionConfig()
230         tmp32 |= DCDC_REG0_PWD_CUR_SNS_CMP_MASK;  in DCDC_SetDetectionConfig()
234         tmp32 |= DCDC_REG0_PWD_ZCD_MASK;  in DCDC_SetDetectionConfig()
236     base->REG0 = tmp32;  in DCDC_SetDetectionConfig()
247     uint32_t tmp32;  in DCDC_SetClockSource()  local
250     tmp32 = base->REG0 & ~(DCDC_REG0_XTAL_24M_OK_MASK | DCDC_REG0_DISABLE_AUTO_CLK_SWITCH_MASK |  in DCDC_SetClockSource()
255             tmp32 |= DCDC_REG0_DISABLE_AUTO_CLK_SWITCH_MASK;  in DCDC_SetClockSource()
259 …tmp32 |= DCDC_REG0_DISABLE_AUTO_CLK_SWITCH_MASK | DCDC_REG0_SEL_CLK_MASK | DCDC_REG0_PWD_OSC_INT_M…  in DCDC_SetClockSource()
263             tmp32 |= DCDC_REG0_XTAL_24M_OK_MASK;  in DCDC_SetClockSource()
269     base->REG0 = tmp32;  in DCDC_SetClockSource()
302     uint32_t tmp32;  in DCDC_SetLowPowerConfig()  local
304     tmp32 = base->REG0 & ~(DCDC_REG0_LP_HIGH_HYS_MASK);  in DCDC_SetLowPowerConfig()
308         tmp32 |= DCDC_REG0_LP_HIGH_HYS_MASK;  in DCDC_SetLowPowerConfig()
310     base->REG0 = tmp32;  in DCDC_SetLowPowerConfig()
358     uint32_t tmp32;  in DCDC_SetLoopControlConfig()  local
361     tmp32 = base->REG1 & ~(DCDC_REG1_LOOPCTRL_EN_DF_HYST_MASK | DCDC_REG1_LOOPCTRL_EN_CM_HYST_MASK |  in DCDC_SetLoopControlConfig()
365         tmp32 |= DCDC_REG1_LOOPCTRL_EN_CM_HYST_MASK;  in DCDC_SetLoopControlConfig()
369         tmp32 |= DCDC_REG1_LOOPCTRL_CM_HST_THRESH_MASK;  in DCDC_SetLoopControlConfig()
373         tmp32 |= DCDC_REG1_LOOPCTRL_EN_DF_HYST_MASK;  in DCDC_SetLoopControlConfig()
377         tmp32 |= DCDC_REG1_LOOPCTRL_DF_HST_THRESH_MASK;  in DCDC_SetLoopControlConfig()
380     base->REG1 = tmp32;  in DCDC_SetLoopControlConfig()
383 … tmp32 = base->REG2 & ~(DCDC_REG2_LOOPCTRL_HYST_SIGN_MASK | DCDC_REG2_LOOPCTRL_RCSCALE_THRSH_MASK |  in DCDC_SetLoopControlConfig()
386     tmp32 |= DCDC_REG2_LOOPCTRL_DC_FF(config->complementFeedForwardStep) |  in DCDC_SetLoopControlConfig()
392         tmp32 |= DCDC_REG2_LOOPCTRL_HYST_SIGN_MASK;  in DCDC_SetLoopControlConfig()
396         tmp32 |= DCDC_REG2_LOOPCTRL_RCSCALE_THRSH_MASK;  in DCDC_SetLoopControlConfig()
398     base->REG2 = tmp32;  in DCDC_SetLoopControlConfig()
411     uint32_t tmp32;  in DCDC_SetMinPowerConfig()  local
413     tmp32 = base->REG3 & ~DCDC_REG3_MINPWR_DC_HALFCLK_MASK;  in DCDC_SetMinPowerConfig()
416         tmp32 |= DCDC_REG3_MINPWR_DC_HALFCLK_MASK;  in DCDC_SetMinPowerConfig()
418     base->REG3 = tmp32;  in DCDC_SetMinPowerConfig()
431     uint32_t tmp32;  in DCDC_SetInternalRegulatorConfig()  local
433     tmp32 = base->REG3 & ~DCDC_REG3_REG_FBK_SEL_MASK;  in DCDC_SetInternalRegulatorConfig()
434     tmp32 |= DCDC_REG3_REG_FBK_SEL(config->feedbackPoint);  in DCDC_SetInternalRegulatorConfig()
435     base->REG3 = tmp32;  in DCDC_SetInternalRegulatorConfig()