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Searched refs:pin (Results 1 – 25 of 266) sorted by relevance

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/hal_nxp-latest/dts/nxp/nxp_imx/rt/
Dmimxrt1189xvm8b-pinctrl.dtsi10 * These definitions define SOC level defaults for each pin,
11 * and select the pinmux for the pin. Pinmux entries are a tuple of:
16 * the pin based on the devicetree properties set
27 pin-pue;
31 pin-pue;
35 pin-pue;
39 pin-pue;
43 pin-pue;
47 pin-pue;
51 pin-pue;
[all …]
Dmimxrt1189cvm8b-pinctrl.dtsi10 * These definitions define SOC level defaults for each pin,
11 * and select the pinmux for the pin. Pinmux entries are a tuple of:
16 * the pin based on the devicetree properties set
27 pin-pue;
31 pin-pue;
35 pin-pue;
39 pin-pue;
43 pin-pue;
47 pin-pue;
51 pin-pue;
[all …]
Dmimxrt1176avm8a-pinctrl.dtsi11 * These definitions define SOC level defaults for each pin,
12 * and select the pinmux for the pin. Pinmux entries are a tuple of:
17 * the pin based on the devicetree properties set
23 pin-pue;
27 pin-pue;
31 pin-pue;
35 pin-pue;
39 pin-pue;
43 pin-pue;
47 pin-pue;
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Dmimxrt1176cvm8a-pinctrl.dtsi11 * These definitions define SOC level defaults for each pin,
12 * and select the pinmux for the pin. Pinmux entries are a tuple of:
17 * the pin based on the devicetree properties set
23 pin-pue;
27 pin-pue;
31 pin-pue;
35 pin-pue;
39 pin-pue;
43 pin-pue;
47 pin-pue;
[all …]
Dmimxrt1176dvmaa-pinctrl.dtsi11 * These definitions define SOC level defaults for each pin,
12 * and select the pinmux for the pin. Pinmux entries are a tuple of:
17 * the pin based on the devicetree properties set
23 pin-pue;
27 pin-pue;
31 pin-pue;
35 pin-pue;
39 pin-pue;
43 pin-pue;
47 pin-pue;
[all …]
Dmimxrt1166cvm5a-pinctrl.dtsi11 * These definitions define SOC level defaults for each pin,
12 * and select the pinmux for the pin. Pinmux entries are a tuple of:
17 * the pin based on the devicetree properties set
23 pin-pue;
27 pin-pue;
31 pin-pue;
35 pin-pue;
39 pin-pue;
43 pin-pue;
47 pin-pue;
[all …]
Dmimxrt1166dvm6a-pinctrl.dtsi11 * These definitions define SOC level defaults for each pin,
12 * and select the pinmux for the pin. Pinmux entries are a tuple of:
17 * the pin based on the devicetree properties set
23 pin-pue;
27 pin-pue;
31 pin-pue;
35 pin-pue;
39 pin-pue;
43 pin-pue;
47 pin-pue;
[all …]
Dmimxrt1166xvm5a-pinctrl.dtsi11 * These definitions define SOC level defaults for each pin,
12 * and select the pinmux for the pin. Pinmux entries are a tuple of:
17 * the pin based on the devicetree properties set
23 pin-pue;
27 pin-pue;
31 pin-pue;
35 pin-pue;
39 pin-pue;
43 pin-pue;
47 pin-pue;
[all …]
/hal_nxp-latest/mcux/mcux-sdk/components/gpio/
Dfsl_adapter_gint.c26 uint16_t pin : 5U; member
35 hal_gpio_pin_t pin; member
117 gpioStateHandle->pin.pin = pinConfig->pin; in HAL_GpioInit()
118 gpioStateHandle->pin.port = pinConfig->port; in HAL_GpioInit()
119 gpioStateHandle->pin.direction = (uint16_t)pinConfig->direction; in HAL_GpioInit()
138 …GINT_ConfigPins(gintList[gpioStateHandle->gintInstance], (gint_port_t)gpioStateHandle->pin.port, 0… in HAL_GpioDeinit()
174 *gpioTrigger = (hal_gpio_interrupt_trigger_t)gpioStateHandle->pin.trigger; in HAL_GpioGetTriggerMode()
193 assert((uint16_t)kHAL_GpioDirectionOut != gpioStateHandle->pin.direction); in HAL_GpioSetTriggerMode()
199 polarityMask = ~((uint32_t)1U << gpioStateHandle->pin.pin); in HAL_GpioSetTriggerMode()
200 enableMask = ((uint32_t)1U << gpioStateHandle->pin.pin); in HAL_GpioSetTriggerMode()
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Dfsl_adapter_rt_gpio.c26 uint16_t pin : 5U; member
37 hal_gpio_pin_t pin; member
67 portIntFlags = GPIO_PortGetInterruptStatus(GPIO, head->pin.port, intNum); in HAL_GpioInterruptHandle()
68 if (0U != (portIntFlags & (1UL << head->pin.pin))) in HAL_GpioInterruptHandle()
74 GPIO_PinClearInterruptFlag(GPIO, head->pin.port, head->pin.pin, intNum); in HAL_GpioInterruptHandle()
75 if ((uint16_t)kHAL_GpioInterruptEitherEdge == head->pin.trigger) in HAL_GpioInterruptHandle()
77 pinLevel = (uint8_t)GPIO_PinRead(GPIO, head->pin.port, head->pin.pin); in HAL_GpioInterruptHandle()
81 GPIO_SetPinInterruptConfig(GPIO, head->pin.port, head->pin.pin, &triggerConfig); in HAL_GpioInterruptHandle()
106 static hal_gpio_status_t HAL_GpioConflictSearch(hal_gpio_state_t *head, uint8_t port, uint8_t pin) in HAL_GpioConflictSearch() argument
110 if ((head->pin.port == port) && (head->pin.pin == pin)) in HAL_GpioConflictSearch()
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Dfsl_adapter_lpc_gpio.c29 #define HAL_INPUTMUX_GpioPortPinToPintsel(port, pin) \ argument
30 ((uint32_t)(pin) + ((uint32_t)(port) << 5U) + ((uint32_t)PINTSEL_ID << SYSCON_SHIFT))
32 #define HAL_INPUTMUX_GpioPortPinToPintsel(port, pin) \ argument
33 ((uint32_t)(pin) + ((uint32_t)(port) << 5U) + ((uint32_t)PINTSEL_PMUX_ID << PMUX_SHIFT))
40 uint8_t pin; member
60 hal_gpio_pin_t pin; member
63 #define HAL_GPIO_INPUTMUX_PIN_FLAG(port, pin) (((port) << 5U) + (pin)) argument
74 static void HAL_GpioInterruptHandle(uint8_t port, uint8_t pin);
103 static void HAL_GpioInterruptHandle(uint8_t port, uint8_t pin) in HAL_GpioInterruptHandle() argument
109 if ((pin == head->pin.pin) && (port == head->pin.port)) in HAL_GpioInterruptHandle()
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Dfsl_adapter_igpio.c26 uint16_t pin : 5U; member
37 hal_gpio_pin_t pin; member
69 if (kHAL_GpioInterruptDisable != (hal_gpio_interrupt_trigger_t)head->pin.trigger) in HAL_GpioInterruptHandle()
71 if ((gpio_port == head->pin.port) && (0U != (intFlag & ((uint32_t)1 << head->pin.pin)))) in HAL_GpioInterruptHandle()
190 …ic hal_gpio_status_t HAL_GpioConflictSearch(hal_gpio_state_t *head, uint8_t gpio_port, uint8_t pin) in HAL_GpioConflictSearch() argument
194 if ((head->pin.port == gpio_port) && (head->pin.pin == pin)) in HAL_GpioConflictSearch()
293 … (kStatus_HAL_GpioSuccess != HAL_GpioConflictSearch(s_GpioHead, pinConfig->port, pinConfig->pin))) in HAL_GpioInit()
304 gpioState->pin.pin = pinConfig->pin; in HAL_GpioInit()
305 gpioState->pin.port = pinConfig->port; in HAL_GpioInit()
306 gpioState->pin.direction = (uint16_t)pinConfig->direction; in HAL_GpioInit()
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Dfsl_adapter_rgpio.c26 uint16_t pin : 5U; member
38 hal_gpio_pin_t pin; member
75 if (0U != (portIntFlags & (1UL << head->pin.pin))) in HAL_GpioInterruptHandle()
146 …ic hal_gpio_status_t HAL_GpioConflictSearch(hal_gpio_state_t *head, uint8_t gpio_port, uint8_t pin) in HAL_GpioConflictSearch() argument
150 if ((head->pin.port == gpio_port) && (head->pin.pin == pin)) in HAL_GpioConflictSearch()
238 … (kStatus_HAL_GpioSuccess != HAL_GpioConflictSearch(s_GpioHead, pinConfig->port, pinConfig->pin))) in HAL_GpioInit()
249 gpioState->pin.pin = pinConfig->pin; in HAL_GpioInit()
250 gpioState->pin.port = pinConfig->port; in HAL_GpioInit()
251 gpioState->pin.direction = (uint16_t)pinConfig->direction; in HAL_GpioInit()
252 gpioState->pin.trigger = (uint16_t)kHAL_GpioInterruptDisable; in HAL_GpioInit()
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/hal_nxp-latest/mcux/mcux-sdk/cmsis_drivers/lpc_gpio/
Dfsl_gpio_cmsis.c105 static gpio_cmsis_map_t const *CMSIS_GPIO_GetMapResource(gpio_cmsis_handle_t *handle, uint32_t pin) in CMSIS_GPIO_GetMapResource() argument
109 if (pin == handle->maps[i].pin_index) in CMSIS_GPIO_GetMapResource()
198 static int32_t CMSIS_GPIO_DeinitPin(gpio_cmsis_handle_t *handle, uint32_t pin) in CMSIS_GPIO_DeinitPin() argument
201 gpio_cmsis_map_t const *map = CMSIS_GPIO_GetMapResource(handle, pin); in CMSIS_GPIO_DeinitPin()
202 uint32_t mask = 0x01UL << pin; in CMSIS_GPIO_DeinitPin()
235 static int32_t CMSIS_GPIO_InitPinAsOutput(gpio_cmsis_handle_t *handle, uint32_t pin, uint32_t outpu… in CMSIS_GPIO_InitPinAsOutput() argument
241 GPIO_PinInit(handle->config->gpio_base, handle->config->port_index, pin, &pin_config); in CMSIS_GPIO_InitPinAsOutput()
244 gpio_cmsis_map_t const *map = CMSIS_GPIO_GetMapResource(handle, pin); in CMSIS_GPIO_InitPinAsOutput()
265 uint32_t pin, in CMSIS_GPIO_InitPinAsInput() argument
272 gpio_cmsis_map_t const *map = CMSIS_GPIO_GetMapResource(handle, pin); in CMSIS_GPIO_InitPinAsInput()
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/hal_nxp-latest/imx/drivers/
Dgpio_imx.c49 uint32_t pin; in GPIO_Init() local
57 pin = initConfig->pin; in GPIO_Init()
61 GPIO_GDIR_REG(base) |= (1U << pin); in GPIO_Init()
63 GPIO_GDIR_REG(base) &= ~(1U << pin); in GPIO_Init()
66 if(pin < 16) in GPIO_Init()
71 pin -= 16; in GPIO_Init()
77 *icr &= ~(0x3<<(2*pin)); in GPIO_Init()
82 *icr = (*icr & (~(0x3<<(2*pin)))) | (0x1<<(2*pin)); in GPIO_Init()
87 *icr = (*icr & (~(0x3<<(2*pin)))) | (0x2<<(2*pin)); in GPIO_Init()
92 *icr |= (0x3<<(2*pin)); in GPIO_Init()
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Dgpio_imx.h75 uint32_t pin; /*!< Specifies the pin number. */ member
117 static inline uint8_t GPIO_ReadPinInput(GPIO_Type* base, uint32_t pin) in GPIO_ReadPinInput() argument
119 assert(pin < 32); in GPIO_ReadPinInput()
121 return (uint8_t)((GPIO_DR_REG(base) >> pin) & 1U); in GPIO_ReadPinInput()
143 static inline uint8_t GPIO_ReadPinOutput(GPIO_Type* base, uint32_t pin) in GPIO_ReadPinOutput() argument
145 assert(pin < 32); in GPIO_ReadPinOutput()
147 return (uint8_t)((GPIO_DR_REG(base) >> pin) & 0x1U); in GPIO_ReadPinOutput()
169 void GPIO_WritePinOutput(GPIO_Type* base, uint32_t pin, gpio_pin_action_t pinVal);
197 static inline uint8_t GPIO_ReadPadStatus(GPIO_Type* base, uint32_t pin) in GPIO_ReadPadStatus() argument
199 assert(pin < 32); in GPIO_ReadPadStatus()
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/hal_nxp-latest/mcux/mcux-sdk/drivers/lpc_gpio/
Dfsl_gpio.c97 void GPIO_PinInit(GPIO_Type *base, uint32_t port, uint32_t pin, const gpio_pin_config_t *config) in GPIO_PinInit() argument
104 base->DIRCLR[port] = 1UL << pin; in GPIO_PinInit()
106 base->DIR[port] &= ~(1UL << pin); in GPIO_PinInit()
114 base->CLR[port] = (1UL << pin); in GPIO_PinInit()
118 base->SET[port] = (1UL << pin); in GPIO_PinInit()
122 base->DIRSET[port] = 1UL << pin; in GPIO_PinInit()
124 base->DIR[port] |= 1UL << pin; in GPIO_PinInit()
138 void GPIO_SetPinInterruptConfig(GPIO_Type *base, uint32_t port, uint32_t pin, gpio_interrupt_config… in GPIO_SetPinInterruptConfig() argument
140 base->INTEDG[port] = (base->INTEDG[port] & ~(1UL << pin)) | ((uint32_t)config->mode << pin); in GPIO_SetPinInterruptConfig()
142 base->INTPOL[port] = (base->INTPOL[port] & ~(1UL << pin)) | ((uint32_t)config->polarity << pin); in GPIO_SetPinInterruptConfig()
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/hal_nxp-latest/mcux/mcux-sdk/drivers/rgpio/
Dfsl_rgpio.h149 void RGPIO_PinInit(RGPIO_Type *base, uint32_t pin, const rgpio_pin_config_t *config);
172 static inline void RGPIO_PinWrite(RGPIO_Type *base, uint32_t pin, uint8_t output) in RGPIO_PinWrite() argument
176 base->PCOR = 1UL << pin; in RGPIO_PinWrite()
180 base->PSOR = 1UL << pin; in RGPIO_PinWrite()
188 static inline void RGPIO_WritePinOutput(RGPIO_Type *base, uint32_t pin, uint8_t output) in RGPIO_WritePinOutput() argument
190 RGPIO_PinWrite(base, pin, output); in RGPIO_WritePinOutput()
269 static inline uint32_t RGPIO_PinRead(RGPIO_Type *base, uint32_t pin) in RGPIO_PinRead() argument
271 return (((base->PDIR) >> pin) & 0x01U); in RGPIO_PinRead()
278 static inline uint32_t RGPIO_ReadPinInput(RGPIO_Type *base, uint32_t pin) in RGPIO_ReadPinInput() argument
280 return RGPIO_PinRead(base, pin); in RGPIO_ReadPinInput()
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/hal_nxp-latest/mcux/mcux-sdk/drivers/igpio/
Dfsl_gpio.c75 void GPIO_PinInit(GPIO_Type *base, uint32_t pin, const gpio_pin_config_t *Config) in GPIO_PinInit() argument
89 base->IMR &= ~(1UL << pin); in GPIO_PinInit()
94 base->GDIR &= ~(1UL << pin); in GPIO_PinInit()
98 GPIO_PinWrite(base, pin, Config->outputLogic); in GPIO_PinInit()
99 base->GDIR |= (1UL << pin); in GPIO_PinInit()
103 GPIO_SetPinInterruptConfig(base, pin, Config->interruptMode); in GPIO_PinInit()
115 void GPIO_PinWrite(GPIO_Type *base, uint32_t pin, uint8_t output) in GPIO_PinWrite() argument
117 assert(pin < 32U); in GPIO_PinWrite()
121 base->DR_CLEAR = (1UL << pin); in GPIO_PinWrite()
123 base->DR &= ~(1UL << pin); /* Set pin output to low level.*/ in GPIO_PinWrite()
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Dfsl_gpio.h78 void GPIO_PinInit(GPIO_Type *base, uint32_t pin, const gpio_pin_config_t *Config);
95 void GPIO_PinWrite(GPIO_Type *base, uint32_t pin, uint8_t output);
101 static inline void GPIO_WritePinOutput(GPIO_Type *base, uint32_t pin, uint8_t output) in GPIO_WritePinOutput() argument
103 GPIO_PinWrite(base, pin, output); in GPIO_WritePinOutput()
176 static inline uint32_t GPIO_PinRead(GPIO_Type *base, uint32_t pin) in GPIO_PinRead() argument
178 assert(pin < 32U); in GPIO_PinRead()
180 return (((base->DR) >> pin) & 0x1U); in GPIO_PinRead()
187 static inline uint32_t GPIO_ReadPinInput(GPIO_Type *base, uint32_t pin) in GPIO_ReadPinInput() argument
189 return GPIO_PinRead(base, pin); in GPIO_ReadPinInput()
205 static inline uint8_t GPIO_PinReadPadStatus(GPIO_Type *base, uint32_t pin) in GPIO_PinReadPadStatus() argument
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/hal_nxp-latest/mcux/mcux-sdk/drivers/gpio/
Dfsl_gpio.h178 void GPIO_PinInit(GPIO_Type *base, uint32_t pin, const gpio_pin_config_t *config);
329 static inline void GPIO_PinWrite(GPIO_Type *base, uint32_t pin, uint8_t output) in GPIO_PinWrite() argument
334 base->PCOR = GPIO_FIT_REG(1UL << pin); in GPIO_PinWrite()
338 base->PSOR = GPIO_FIT_REG(1UL << pin); in GPIO_PinWrite()
343 base->PDOR |= GPIO_FIT_REG(1UL << pin); in GPIO_PinWrite()
347 base->PDOR &= ~GPIO_FIT_REG(1UL << pin); in GPIO_PinWrite()
411 static inline uint32_t GPIO_PinRead(GPIO_Type *base, uint32_t pin) in GPIO_PinRead() argument
413 return (((uint32_t)(base->PDIR) >> pin) & 0x01UL); in GPIO_PinRead()
466 static inline void GPIO_SetPinInterruptConfig(GPIO_Type *base, uint32_t pin, gpio_interrupt_config_… in GPIO_SetPinInterruptConfig() argument
470 base->ICR[pin] = GPIO_FIT_REG((base->ICR[pin] & ~GPIO_ICR_IRQC_MASK) | GPIO_ICR_IRQC(config)); in GPIO_SetPinInterruptConfig()
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/hal_nxp-latest/mcux/mcux-sdk/drivers/gpio_1/
Dfsl_gpio.c79 void GPIO_PinInit(gpio_port_num_t port, uint8_t pin, const gpio_pin_config_t *config) in GPIO_PinInit() argument
89 base->PDDR &= ~(1UL << ((uint32_t)pin + (shift * PIN_NUMBERS_EACH_PORT))); in GPIO_PinInit()
90 base->PIDR &= ~(1UL << ((uint32_t)pin + (shift * PIN_NUMBERS_EACH_PORT))); in GPIO_PinInit()
94 GPIO_PinWrite(port, pin, config->outputLogic); in GPIO_PinInit()
95 base->PDDR |= (1UL << ((uint32_t)pin + (shift * PIN_NUMBERS_EACH_PORT))); in GPIO_PinInit()
96 base->PIDR |= (1UL << ((uint32_t)pin + (shift * PIN_NUMBERS_EACH_PORT))); in GPIO_PinInit()
113 void GPIO_PinWrite(gpio_port_num_t port, uint8_t pin, uint8_t output) in GPIO_PinWrite() argument
121 base->PCOR = 1UL << ((uint32_t)pin + (shift * PIN_NUMBERS_EACH_PORT)); in GPIO_PinWrite()
125 base->PSOR = 1UL << ((uint32_t)pin + (shift * PIN_NUMBERS_EACH_PORT)); in GPIO_PinWrite()
199 uint32_t GPIO_PinRead(gpio_port_num_t port, uint8_t pin) in GPIO_PinRead() argument
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/hal_nxp-latest/mcux/scripts/pinctrl/lpc/
Dlpc_cfg_utils.py73 pin = int(match.group(3))
75 self._offset = (port * 32) + pin
77 self._offset = ((port - 4) * 32) + pin
79 self._offset = ((port - 8) * 32) + pin
83 pin = int(match.group(2))
84 self._offset = (port * 32) + pin
239 def __init__(self, pin, imx_rt = ''): argument
245 pin_regex = re.search(r'PIO(\d+)_(\d+)', pin.attrib['name'])
246 if (imx_rt and (pin.attrib['name'] == 'PMIC_I2C_SCL' or
247 pin.attrib['name'] == 'PMIC_I2C_SDA')):
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/hal_nxp-latest/mcux/mcux-sdk/drivers/flexio/
Dfsl_flexio.h795 void FLEXIO_SetPinConfig(FLEXIO_Type *base, uint32_t pin, flexio_gpio_config_t *config);
844 static inline void FLEXIO_PinWrite(FLEXIO_Type *base, uint32_t pin, uint8_t output) in FLEXIO_PinWrite() argument
848 FLEXIO_ClearPortOutput(base, 1UL << pin); in FLEXIO_PinWrite()
852 FLEXIO_SetPortOutput(base, 1UL << pin); in FLEXIO_PinWrite()
862 static inline void FLEXIO_EnablePinOutput(FLEXIO_Type *base, uint32_t pin) in FLEXIO_EnablePinOutput() argument
864 base->PINOUTE |= (1UL << pin); in FLEXIO_EnablePinOutput()
882 static inline uint32_t FLEXIO_PinRead(FLEXIO_Type *base, uint32_t pin) in FLEXIO_PinRead() argument
884 return (((base->PIN) >> pin) & 0x01U); in FLEXIO_PinRead()
896 static inline uint32_t FLEXIO_GetPinStatus(FLEXIO_Type *base, uint32_t pin) in FLEXIO_GetPinStatus() argument
898 return (((base->PINSTAT) >> pin) & 0x01U); in FLEXIO_GetPinStatus()
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/hal_nxp-latest/mcux/mcux-sdk/drivers/port/
Dfsl_port.h360 static inline void PORT_SetPinConfig(PORT_Type *base, uint32_t pin, const port_pin_config_t *config) in PORT_SetPinConfig() argument
363 uint32_t addr = (uint32_t)&base->PCR[pin]; in PORT_SetPinConfig()
463 static inline void PORT_SetPinMux(PORT_Type *base, uint32_t pin, port_mux_t mux) in PORT_SetPinMux() argument
465 base->PCR[pin] = (base->PCR[pin] & ~PORT_PCR_MUX_MASK) | PORT_PCR_MUX(mux); in PORT_SetPinMux()
532 static inline void PORT_SetPinInterruptConfig(PORT_Type *base, uint32_t pin, port_interrupt_t confi… in PORT_SetPinInterruptConfig() argument
534 base->PCR[pin] = (base->PCR[pin] & ~PORT_PCR_IRQC_MASK) | PORT_PCR_IRQC(config); in PORT_SetPinInterruptConfig()
548 static inline void PORT_SetPinDriveStrength(PORT_Type *base, uint32_t pin, uint8_t strength) in PORT_SetPinDriveStrength() argument
550 base->PCR[pin] = (base->PCR[pin] & ~PORT_PCR_DSE_MASK) | PORT_PCR_DSE(strength); in PORT_SetPinDriveStrength()
562 static inline void PORT_EnablePinDoubleDriveStrength(PORT_Type *base, uint32_t pin, bool enable) in PORT_EnablePinDoubleDriveStrength() argument
564 base->PCR[pin] = (base->PCR[pin] & ~PORT_PCR_DSE1_MASK) | PORT_PCR_DSE1(enable); in PORT_EnablePinDoubleDriveStrength()
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