1 /*
2 * Copyright (c) 2015, Freescale Semiconductor, Inc.
3 * Copyright 2016-2022, 2024 NXP
4 * All rights reserved.
5 *
6 * SPDX-License-Identifier: BSD-3-Clause
7 */
8 #ifndef FSL_PORT_H_
9 #define FSL_PORT_H_
10
11 #include "fsl_common.h"
12
13 /*!
14 * @addtogroup port
15 * @{
16 */
17
18 /*******************************************************************************
19 * Definitions
20 ******************************************************************************/
21
22 /* Component ID definition, used by tools. */
23 #ifndef FSL_COMPONENT_ID
24 #define FSL_COMPONENT_ID "platform.drivers.port"
25 #endif
26
27 /*! @name Driver version */
28 /*! @{ */
29 /*! @brief PORT driver version. */
30 #define FSL_PORT_DRIVER_VERSION (MAKE_VERSION(2, 5, 0))
31 /*! @} */
32
33 #if defined(FSL_FEATURE_PORT_HAS_PULL_ENABLE) && FSL_FEATURE_PORT_HAS_PULL_ENABLE
34 /*! @brief Internal resistor pull feature selection */
35 enum _port_pull
36 {
37 kPORT_PullDisable = 0U, /*!< Internal pull-up/down resistor is disabled. */
38 kPORT_PullDown = 2U, /*!< Internal pull-down resistor is enabled. */
39 kPORT_PullUp = 3U, /*!< Internal pull-up resistor is enabled. */
40 };
41 #endif /* FSL_FEATURE_PORT_HAS_PULL_ENABLE */
42
43 #if defined(FSL_FEATURE_PORT_PCR_HAS_PULL_VALUE) && FSL_FEATURE_PORT_PCR_HAS_PULL_VALUE
44 /*! @brief Internal resistor pull value selection */
45 enum _port_pull_value
46 {
47 kPORT_LowPullResistor = 0U, /*!< Low internal pull resistor value is selected. */
48 kPORT_HighPullResistor = 1U, /*!< High internal pull resistor value is selected. */
49 };
50 #endif /* FSL_FEATURE_PORT_PCR_HAS_PULL_VALUE */
51
52 #if defined(FSL_FEATURE_PORT_HAS_SLEW_RATE) && FSL_FEATURE_PORT_HAS_SLEW_RATE
53 /*! @brief Slew rate selection */
54 enum _port_slew_rate
55 {
56 kPORT_FastSlewRate = 0U, /*!< Fast slew rate is configured. */
57 kPORT_SlowSlewRate = 1U, /*!< Slow slew rate is configured. */
58 };
59 #endif /* FSL_FEATURE_PORT_HAS_SLEW_RATE */
60
61 #if defined(FSL_FEATURE_PORT_HAS_OPEN_DRAIN) && FSL_FEATURE_PORT_HAS_OPEN_DRAIN
62 /*! @brief Open Drain feature enable/disable */
63 enum _port_open_drain_enable
64 {
65 kPORT_OpenDrainDisable = 0U, /*!< Open drain output is disabled. */
66 kPORT_OpenDrainEnable = 1U, /*!< Open drain output is enabled. */
67 };
68 #endif /* FSL_FEATURE_PORT_HAS_OPEN_DRAIN */
69
70 #if defined(FSL_FEATURE_PORT_HAS_PASSIVE_FILTER) && FSL_FEATURE_PORT_HAS_PASSIVE_FILTER
71 /*! @brief Passive filter feature enable/disable */
72 enum _port_passive_filter_enable
73 {
74 kPORT_PassiveFilterDisable = 0U, /*!< Passive input filter is disabled. */
75 kPORT_PassiveFilterEnable = 1U, /*!< Passive input filter is enabled. */
76 };
77 #endif
78
79 #if defined(FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH) && FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH
80 /*! @brief Configures the drive strength. */
81 enum _port_drive_strength
82 {
83 kPORT_LowDriveStrength = 0U, /*!< Low-drive strength is configured. */
84 kPORT_HighDriveStrength = 1U, /*!< High-drive strength is configured. */
85 };
86 #endif /* FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH */
87
88 #if defined(FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH1) && FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH1
89 /*! @brief Configures the drive strength1. */
90 enum _port_drive_strength1
91 {
92 kPORT_NormalDriveStrength = 0U, /*!< Normal drive strength */
93 kPORT_DoubleDriveStrength = 1U, /*!< Double drive strength */
94 };
95 #endif /* FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH1 */
96
97 #if defined(FSL_FEATURE_PORT_HAS_INPUT_BUFFER) && FSL_FEATURE_PORT_HAS_INPUT_BUFFER
98 /*! @brief input buffer disable/enable. */
99 enum _port_input_buffer
100 {
101 kPORT_InputBufferDisable = 0U, /*!< Digital input is disabled */
102 kPORT_InputBufferEnable = 1U, /*!< Digital input is enabled */
103 };
104 #endif /* FSL_FEATURE_PORT_HAS_INPUT_BUFFER */
105
106 #if defined(FSL_FEATURE_PORT_HAS_INVERT_INPUT) && FSL_FEATURE_PORT_HAS_INVERT_INPUT
107 /*! @brief Digital input is not inverted or it is inverted. */
108 enum _port_invet_input
109 {
110 kPORT_InputNormal = 0U, /*!< Digital input is not inverted */
111 kPORT_InputInvert = 1U, /*!< Digital input is inverted */
112 };
113 #endif /* FSL_FEATURE_PORT_HAS_INVERT_INPUT */
114
115 #if defined(FSL_FEATURE_PORT_HAS_PIN_CONTROL_LOCK) && FSL_FEATURE_PORT_HAS_PIN_CONTROL_LOCK
116 /*! @brief Unlock/lock the pin control register field[15:0] */
117 enum _port_lock_register
118 {
119 kPORT_UnlockRegister = 0U, /*!< Pin Control Register fields [15:0] are not locked. */
120 kPORT_LockRegister = 1U, /*!< Pin Control Register fields [15:0] are locked. */
121 };
122 #endif /* FSL_FEATURE_PORT_HAS_PIN_CONTROL_LOCK */
123
124 #if defined(FSL_FEATURE_PORT_PCR_MUX_WIDTH) && FSL_FEATURE_PORT_PCR_MUX_WIDTH
125 /*! @brief Pin mux selection */
126 typedef enum _port_mux
127 {
128 #if defined(FSL_FEATURE_PORT_PCR_MUX_GPIO) && (FSL_FEATURE_PORT_PCR_MUX_GPIO == 0)
129 kPORT_MuxAsGpio = 0U, /*!< Corresponding pin is configured as GPIO. */
130 #else
131 kPORT_PinDisabledOrAnalog = 0U, /*!< Corresponding pin is disabled, but is used as an analog pin. */
132 kPORT_MuxAsGpio = 1U, /*!< Corresponding pin is configured as GPIO. */
133 #endif
134 kPORT_MuxAlt0 = 0U, /*!< Chip-specific */
135 kPORT_MuxAlt1 = 1U, /*!< Chip-specific */
136 kPORT_MuxAlt2 = 2U, /*!< Chip-specific */
137 kPORT_MuxAlt3 = 3U, /*!< Chip-specific */
138 kPORT_MuxAlt4 = 4U, /*!< Chip-specific */
139 kPORT_MuxAlt5 = 5U, /*!< Chip-specific */
140 kPORT_MuxAlt6 = 6U, /*!< Chip-specific */
141 kPORT_MuxAlt7 = 7U, /*!< Chip-specific */
142 kPORT_MuxAlt8 = 8U, /*!< Chip-specific */
143 kPORT_MuxAlt9 = 9U, /*!< Chip-specific */
144 kPORT_MuxAlt10 = 10U, /*!< Chip-specific */
145 kPORT_MuxAlt11 = 11U, /*!< Chip-specific */
146 kPORT_MuxAlt12 = 12U, /*!< Chip-specific */
147 kPORT_MuxAlt13 = 13U, /*!< Chip-specific */
148 kPORT_MuxAlt14 = 14U, /*!< Chip-specific */
149 kPORT_MuxAlt15 = 15U, /*!< Chip-specific */
150 } port_mux_t;
151 #endif /* FSL_FEATURE_PORT_PCR_MUX_WIDTH */
152
153 #if !(defined(FSL_FEATURE_PORT_HAS_NO_INTERRUPT) && FSL_FEATURE_PORT_HAS_NO_INTERRUPT)
154 /*! @brief Configures the interrupt generation condition. */
155 typedef enum _port_interrupt
156 {
157 kPORT_InterruptOrDMADisabled = 0x0U, /*!< Interrupt/DMA request is disabled. */
158 #if defined(FSL_FEATURE_PORT_HAS_DMA_REQUEST) && FSL_FEATURE_PORT_HAS_DMA_REQUEST || defined(DOXYGEN_OUTPUT)
159 kPORT_DMARisingEdge = 0x1U, /*!< DMA request on rising edge. */
160 kPORT_DMAFallingEdge = 0x2U, /*!< DMA request on falling edge. */
161 kPORT_DMAEitherEdge = 0x3U, /*!< DMA request on either edge. */
162 #endif
163 #if defined(FSL_FEATURE_PORT_HAS_IRQC_FLAG) && FSL_FEATURE_PORT_HAS_IRQC_FLAG || defined(DOXYGEN_OUTPUT)
164 kPORT_FlagRisingEdge = 0x05U, /*!< Flag sets on rising edge. */
165 kPORT_FlagFallingEdge = 0x06U, /*!< Flag sets on falling edge. */
166 kPORT_FlagEitherEdge = 0x07U, /*!< Flag sets on either edge. */
167 #endif
168 kPORT_InterruptLogicZero = 0x8U, /*!< Interrupt when logic zero. */
169 kPORT_InterruptRisingEdge = 0x9U, /*!< Interrupt on rising edge. */
170 kPORT_InterruptFallingEdge = 0xAU, /*!< Interrupt on falling edge. */
171 kPORT_InterruptEitherEdge = 0xBU, /*!< Interrupt on either edge. */
172 kPORT_InterruptLogicOne = 0xCU, /*!< Interrupt when logic one. */
173 #if defined(FSL_FEATURE_PORT_HAS_IRQC_TRIGGER) && FSL_FEATURE_PORT_HAS_IRQC_TRIGGER || defined(DOXYGEN_OUTPUT)
174 kPORT_ActiveHighTriggerOutputEnable = 0xDU, /*!< Enable active high-trigger output. */
175 kPORT_ActiveLowTriggerOutputEnable = 0xEU, /*!< Enable active low-trigger output. */
176 #endif
177 } port_interrupt_t;
178 #endif
179
180 #if defined(FSL_FEATURE_PORT_HAS_DIGITAL_FILTER) && FSL_FEATURE_PORT_HAS_DIGITAL_FILTER
181 /*! @brief Digital filter clock source selection */
182 typedef enum _port_digital_filter_clock_source
183 {
184 kPORT_BusClock = 0U, /*!< Digital filters are clocked by the bus clock. */
185 kPORT_LpoClock = 1U, /*!< Digital filters are clocked by the 1 kHz LPO clock. */
186 } port_digital_filter_clock_source_t;
187
188 /*! @brief PORT digital filter feature configuration definition */
189 typedef struct _port_digital_filter_config
190 {
191 uint32_t digitalFilterWidth; /*!< Set digital filter width */
192 port_digital_filter_clock_source_t clockSource; /*!< Set digital filter clockSource */
193 } port_digital_filter_config_t;
194 #endif /* FSL_FEATURE_PORT_HAS_DIGITAL_FILTER */
195
196 #if defined(FSL_FEATURE_PORT_PCR_MUX_WIDTH) && FSL_FEATURE_PORT_PCR_MUX_WIDTH
197 /*! @brief PORT pin configuration structure */
198 typedef struct _port_pin_config
199 {
200 #if defined(FSL_FEATURE_PORT_HAS_PULL_ENABLE) && FSL_FEATURE_PORT_HAS_PULL_ENABLE
201 uint16_t pullSelect : 2; /*!< No-pull/pull-down/pull-up select */
202 #else
203 uint16_t : 2;
204 #endif /* FSL_FEATURE_PORT_HAS_PULL_ENABLE */
205
206 #if defined(FSL_FEATURE_PORT_PCR_HAS_PULL_VALUE) && FSL_FEATURE_PORT_PCR_HAS_PULL_VALUE
207 uint16_t pullValueSelect : 1; /*!< Pull value select */
208 #endif /* FSL_FEATURE_PORT_PCR_HAS_PULL_VALUE */
209
210 #if defined(FSL_FEATURE_PORT_HAS_SLEW_RATE) && FSL_FEATURE_PORT_HAS_SLEW_RATE
211 uint16_t slewRate : 1; /*!< Fast/slow slew rate Configure */
212 #else
213 uint16_t : 1;
214 #endif /* FSL_FEATURE_PORT_HAS_SLEW_RATE */
215
216 #if !(defined(FSL_FEATURE_PORT_PCR_HAS_PULL_VALUE) && FSL_FEATURE_PORT_PCR_HAS_PULL_VALUE)
217 uint16_t : 1;
218 #endif /* FSL_FEATURE_PORT_PCR_HAS_PULL_VALUE */
219
220 #if defined(FSL_FEATURE_PORT_HAS_PASSIVE_FILTER) && FSL_FEATURE_PORT_HAS_PASSIVE_FILTER
221 uint16_t passiveFilterEnable : 1; /*!< Passive filter enable/disable */
222 #else
223 uint16_t : 1;
224 #endif /* FSL_FEATURE_PORT_HAS_PASSIVE_FILTER */
225
226 #if defined(FSL_FEATURE_PORT_HAS_OPEN_DRAIN) && FSL_FEATURE_PORT_HAS_OPEN_DRAIN
227 uint16_t openDrainEnable : 1; /*!< Open drain enable/disable */
228 #else
229 uint16_t : 1;
230 #endif /* FSL_FEATURE_PORT_HAS_OPEN_DRAIN */
231
232 #if defined(FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH) && FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH
233 uint16_t driveStrength : 1; /*!< Fast/slow drive strength configure */
234 #else
235 uint16_t : 1;
236 #endif
237
238 #if defined(FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH1) && FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH1
239 uint16_t driveStrength1 : 1; /*!< Normal/Double drive strength enable/disable */
240 #else
241 uint16_t : 1;
242 #endif /* FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH1 */
243
244 #if defined(FSL_FEATURE_PORT_PCR_MUX_WIDTH) && (FSL_FEATURE_PORT_PCR_MUX_WIDTH == 3)
245 uint16_t mux : 3; /*!< Pin mux Configure */
246 uint16_t : 1;
247 #elif defined(FSL_FEATURE_PORT_PCR_MUX_WIDTH) && (FSL_FEATURE_PORT_PCR_MUX_WIDTH == 4)
248 uint16_t mux : 4; /*!< Pin mux Configure */
249 #else
250 uint16_t : 4;
251 #endif
252
253 #if defined(FSL_FEATURE_PORT_HAS_INPUT_BUFFER) && FSL_FEATURE_PORT_HAS_INPUT_BUFFER
254 uint16_t inputBuffer : 1; /*!< Input Buffer Configure */
255 #else
256 uint16_t : 1;
257 #endif /* FSL_FEATURE_PORT_HAS_INPUT_BUFFER */
258
259 #if defined(FSL_FEATURE_PORT_HAS_INVERT_INPUT) && FSL_FEATURE_PORT_HAS_INVERT_INPUT
260 uint16_t invertInput : 1; /*!< Invert Input Configure */
261 #else
262 uint16_t : 1;
263 #endif /* FSL_FEATURE_PORT_HAS_INVERT_INPUT */
264
265 uint16_t : 1;
266
267 #if defined(FSL_FEATURE_PORT_HAS_PIN_CONTROL_LOCK) && FSL_FEATURE_PORT_HAS_PIN_CONTROL_LOCK
268 uint16_t lockRegister : 1; /*!< Lock/unlock the PCR field[15:0] */
269 #else
270 uint16_t : 1;
271 #endif /* FSL_FEATURE_PORT_HAS_PIN_CONTROL_LOCK */
272 } port_pin_config_t;
273 #endif /* FSL_FEATURE_PORT_PCR_MUX_WIDTH */
274
275 #if defined(FSL_FEATURE_PORT_HAS_VERSION_INFO_REGISTER) && FSL_FEATURE_PORT_HAS_VERSION_INFO_REGISTER
276 /*! @brief PORT version information. */
277 typedef struct _port_version_info
278 {
279 uint16_t feature; /*!< Feature Specification Number. */
280 uint8_t minor; /*!< Minor Version Number. */
281 uint8_t major; /*!< Major Version Number. */
282 } port_version_info_t;
283 #endif /* FSL_FEATURE_PORT_HAS_VERSION_INFO_REGISTER */
284
285 #if defined(FSL_FEATURE_PORT_SUPPORT_DIFFERENT_VOLTAGE_RANGE) && FSL_FEATURE_PORT_SUPPORT_DIFFERENT_VOLTAGE_RANGE
286 /*! @brief PORT voltage range. */
287 typedef enum _port_voltage_range
288 {
289 kPORT_VoltageRange1Dot71V_3Dot6V = 0x0U, /*!< Port voltage range is 1.71 V - 3.6 V. */
290 kPORT_VoltageRange2Dot70V_3Dot6V = 0x1U, /*!< Port voltage range is 2.70 V - 3.6 V. */
291 } port_voltage_range_t;
292 #endif /* FSL_FEATURE_PORT_SUPPORT_DIFFERENT_VOLTAGE_RANGE */
293
294 /*******************************************************************************
295 * API
296 ******************************************************************************/
297
298 #if defined(__cplusplus)
299 extern "C" {
300 #endif
301
302 /*! @name Configuration */
303 /*! @{ */
304
305 #if defined(FSL_FEATURE_PORT_PCR_MUX_WIDTH) && FSL_FEATURE_PORT_PCR_MUX_WIDTH
306
307 #if defined(FSL_FEATURE_PORT_HAS_VERSION_INFO_REGISTER) && FSL_FEATURE_PORT_HAS_VERSION_INFO_REGISTER
308 /*!
309 * @brief Get PORT version information.
310 *
311 * @param base PORT peripheral base pointer
312 * @param info PORT version information
313 */
PORT_GetVersionInfo(PORT_Type * base,port_version_info_t * info)314 static inline void PORT_GetVersionInfo(PORT_Type *base, port_version_info_t *info)
315 {
316 uint32_t verid = base->VERID;
317 info->feature = (uint16_t)verid;
318 info->minor = (uint8_t)(verid >> PORT_VERID_MINOR_SHIFT);
319 info->major = (uint8_t)(verid >> PORT_VERID_MAJOR_SHIFT);
320 }
321 #endif /* FSL_FEATURE_PORT_HAS_VERSION_INFO_REGISTER */
322
323 #if defined(FSL_FEATURE_PORT_SUPPORT_DIFFERENT_VOLTAGE_RANGE) && FSL_FEATURE_PORT_SUPPORT_DIFFERENT_VOLTAGE_RANGE
324 /*!
325 * @brief Get PORT version information.
326 *
327 * @note : PORTA_CONFIG[RANGE] controls the voltage ranges of Port A, B, and C. Read or write PORTB_CONFIG[RANGE] and
328 * PORTC_CONFIG[RANGE] does not take effect.
329 *
330 * @param base PORT peripheral base pointer
331 * @param range port voltage range
332 */
PORT_SecletPortVoltageRange(PORT_Type * base,port_voltage_range_t range)333 static inline void PORT_SecletPortVoltageRange(PORT_Type *base, port_voltage_range_t range)
334 {
335 base->CONFIG = (uint32_t)range;
336 }
337 #endif /* FSL_FEATURE_PORT_SUPPORT_DIFFERENT_VOLTAGE_RANGE */
338
339 /*!
340 * @brief Sets the port PCR register.
341 *
342 * This is an example to define an input pin or output pin PCR configuration.
343 * @code
344 * // Define a digital input pin PCR configuration
345 * port_pin_config_t config = {
346 * kPORT_PullUp,
347 * kPORT_FastSlewRate,
348 * kPORT_PassiveFilterDisable,
349 * kPORT_OpenDrainDisable,
350 * kPORT_LowDriveStrength,
351 * kPORT_MuxAsGpio,
352 * kPORT_UnLockRegister,
353 * };
354 * @endcode
355 *
356 * @param base PORT peripheral base pointer.
357 * @param pin PORT pin number.
358 * @param config PORT PCR register configuration structure.
359 */
PORT_SetPinConfig(PORT_Type * base,uint32_t pin,const port_pin_config_t * config)360 static inline void PORT_SetPinConfig(PORT_Type *base, uint32_t pin, const port_pin_config_t *config)
361 {
362 assert(config);
363 uint32_t addr = (uint32_t)&base->PCR[pin];
364 *(volatile uint16_t *)(addr) = *((const uint16_t *)(const void *)config);
365 }
366
367 /*!
368 * @brief Sets the port PCR register for multiple pins.
369 *
370 * This is an example to define input pins or output pins PCR configuration.
371 * @code
372 * Define a digital input pin PCR configuration
373 * port_pin_config_t config = {
374 * kPORT_PullUp ,
375 * kPORT_PullEnable,
376 * kPORT_FastSlewRate,
377 * kPORT_PassiveFilterDisable,
378 * kPORT_OpenDrainDisable,
379 * kPORT_LowDriveStrength,
380 * kPORT_MuxAsGpio,
381 * kPORT_UnlockRegister,
382 * };
383 * @endcode
384 *
385 * @param base PORT peripheral base pointer.
386 * @param mask PORT pin number macro.
387 * @param config PORT PCR register configuration structure.
388 */
PORT_SetMultiplePinsConfig(PORT_Type * base,uint32_t mask,const port_pin_config_t * config)389 static inline void PORT_SetMultiplePinsConfig(PORT_Type *base, uint32_t mask, const port_pin_config_t *config)
390 {
391 assert(config);
392
393 uint16_t pcrl = *((const uint16_t *)(const void *)config);
394
395 if (0U != (mask & 0xffffU))
396 {
397 base->GPCLR = ((mask & 0xffffU) << 16) | pcrl;
398 }
399 if (0U != (mask >> 16))
400 {
401 base->GPCHR = (mask & 0xffff0000U) | pcrl;
402 }
403 }
404
405 #if defined(FSL_FEATURE_PORT_HAS_MULTIPLE_IRQ_CONFIG) && FSL_FEATURE_PORT_HAS_MULTIPLE_IRQ_CONFIG
406 /*!
407 * @brief Sets the port interrupt configuration in PCR register for multiple pins.
408 *
409 * @param base PORT peripheral base pointer.
410 * @param mask PORT pin number macro.
411 * @param config PORT pin interrupt configuration.
412 * - #kPORT_InterruptOrDMADisabled: Interrupt/DMA request disabled.
413 * - #kPORT_DMARisingEdge : DMA request on rising edge(if the DMA requests exit).
414 * - #kPORT_DMAFallingEdge: DMA request on falling edge(if the DMA requests exit).
415 * - #kPORT_DMAEitherEdge : DMA request on either edge(if the DMA requests exit).
416 * - #kPORT_FlagRisingEdge : Flag sets on rising edge(if the Flag states exit).
417 * - #kPORT_FlagFallingEdge : Flag sets on falling edge(if the Flag states exit).
418 * - #kPORT_FlagEitherEdge : Flag sets on either edge(if the Flag states exit).
419 * - #kPORT_InterruptLogicZero : Interrupt when logic zero.
420 * - #kPORT_InterruptRisingEdge : Interrupt on rising edge.
421 * - #kPORT_InterruptFallingEdge: Interrupt on falling edge.
422 * - #kPORT_InterruptEitherEdge : Interrupt on either edge.
423 * - #kPORT_InterruptLogicOne : Interrupt when logic one.
424 * - #kPORT_ActiveHighTriggerOutputEnable : Enable active high-trigger output (if the trigger states exit).
425 * - #kPORT_ActiveLowTriggerOutputEnable : Enable active low-trigger output (if the trigger states exit)..
426 */
PORT_SetMultipleInterruptPinsConfig(PORT_Type * base,uint32_t mask,port_interrupt_t config)427 static inline void PORT_SetMultipleInterruptPinsConfig(PORT_Type *base, uint32_t mask, port_interrupt_t config)
428 {
429 assert(config);
430
431 if (0U != ((uint32_t)mask & 0xffffU))
432 {
433 base->GICLR = ((uint32_t)config << 16U) | ((uint32_t)mask & 0xffffU);
434 }
435 mask = mask >> 16;
436 if (0U != mask)
437 {
438 base->GICHR = ((uint32_t)config << 16U) | ((uint32_t)mask & 0xffffU);
439 }
440 }
441 #endif
442
443 /*!
444 * @brief Configures the pin muxing.
445 *
446 * @param base PORT peripheral base pointer.
447 * @param pin PORT pin number.
448 * @param mux pin muxing slot selection.
449 * - #kPORT_PinDisabledOrAnalog: Pin disabled or work in analog function.
450 * - #kPORT_MuxAsGpio : Set as GPIO.
451 * - #kPORT_MuxAlt2 : chip-specific.
452 * - #kPORT_MuxAlt3 : chip-specific.
453 * - #kPORT_MuxAlt4 : chip-specific.
454 * - #kPORT_MuxAlt5 : chip-specific.
455 * - #kPORT_MuxAlt6 : chip-specific.
456 * - #kPORT_MuxAlt7 : chip-specific.
457 * @note : This function is NOT recommended to use together with the PORT_SetPinsConfig, because
458 * the PORT_SetPinsConfig need to configure the pin mux anyway (Otherwise the pin mux is
459 * reset to zero : kPORT_PinDisabledOrAnalog).
460 * This function is recommended to use to reset the pin mux
461 *
462 */
PORT_SetPinMux(PORT_Type * base,uint32_t pin,port_mux_t mux)463 static inline void PORT_SetPinMux(PORT_Type *base, uint32_t pin, port_mux_t mux)
464 {
465 base->PCR[pin] = (base->PCR[pin] & ~PORT_PCR_MUX_MASK) | PORT_PCR_MUX(mux);
466 }
467 #endif /* FSL_FEATURE_PORT_PCR_MUX_WIDTH */
468
469 #if defined(FSL_FEATURE_PORT_HAS_DIGITAL_FILTER) && FSL_FEATURE_PORT_HAS_DIGITAL_FILTER
470
471 /*!
472 * @brief Enables the digital filter in one port, each bit of the 32-bit register represents one pin.
473 *
474 * @param base PORT peripheral base pointer.
475 * @param mask PORT pin number macro.
476 * @param enable PORT digital filter configuration.
477 */
PORT_EnablePinsDigitalFilter(PORT_Type * base,uint32_t mask,bool enable)478 static inline void PORT_EnablePinsDigitalFilter(PORT_Type *base, uint32_t mask, bool enable)
479 {
480 if (enable == true)
481 {
482 base->DFER |= mask;
483 }
484 else
485 {
486 base->DFER &= ~mask;
487 }
488 }
489
490 /*!
491 * @brief Sets the digital filter in one port, each bit of the 32-bit register represents one pin.
492 *
493 * @param base PORT peripheral base pointer.
494 * @param config PORT digital filter configuration structure.
495 */
PORT_SetDigitalFilterConfig(PORT_Type * base,const port_digital_filter_config_t * config)496 static inline void PORT_SetDigitalFilterConfig(PORT_Type *base, const port_digital_filter_config_t *config)
497 {
498 assert(config);
499
500 base->DFCR = PORT_DFCR_CS(config->clockSource);
501 base->DFWR = PORT_DFWR_FILT(config->digitalFilterWidth);
502 }
503
504 #endif /* FSL_FEATURE_PORT_HAS_DIGITAL_FILTER */
505 /*! @} */
506
507 /*! @name Interrupt */
508 /*! @{ */
509
510 #if !(defined(FSL_FEATURE_PORT_HAS_NO_INTERRUPT) && FSL_FEATURE_PORT_HAS_NO_INTERRUPT)
511 /*!
512 * @brief Configures the port pin interrupt/DMA request.
513 *
514 * @param base PORT peripheral base pointer.
515 * @param pin PORT pin number.
516 * @param config PORT pin interrupt configuration.
517 * - #kPORT_InterruptOrDMADisabled: Interrupt/DMA request disabled.
518 * - #kPORT_DMARisingEdge : DMA request on rising edge(if the DMA requests exit).
519 * - #kPORT_DMAFallingEdge: DMA request on falling edge(if the DMA requests exit).
520 * - #kPORT_DMAEitherEdge : DMA request on either edge(if the DMA requests exit).
521 * - #kPORT_FlagRisingEdge : Flag sets on rising edge(if the Flag states exit).
522 * - #kPORT_FlagFallingEdge : Flag sets on falling edge(if the Flag states exit).
523 * - #kPORT_FlagEitherEdge : Flag sets on either edge(if the Flag states exit).
524 * - #kPORT_InterruptLogicZero : Interrupt when logic zero.
525 * - #kPORT_InterruptRisingEdge : Interrupt on rising edge.
526 * - #kPORT_InterruptFallingEdge: Interrupt on falling edge.
527 * - #kPORT_InterruptEitherEdge : Interrupt on either edge.
528 * - #kPORT_InterruptLogicOne : Interrupt when logic one.
529 * - #kPORT_ActiveHighTriggerOutputEnable : Enable active high-trigger output (if the trigger states exit).
530 * - #kPORT_ActiveLowTriggerOutputEnable : Enable active low-trigger output (if the trigger states exit).
531 */
PORT_SetPinInterruptConfig(PORT_Type * base,uint32_t pin,port_interrupt_t config)532 static inline void PORT_SetPinInterruptConfig(PORT_Type *base, uint32_t pin, port_interrupt_t config)
533 {
534 base->PCR[pin] = (base->PCR[pin] & ~PORT_PCR_IRQC_MASK) | PORT_PCR_IRQC(config);
535 }
536 #endif
537
538 #if defined(FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH) && FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH
539 /*!
540 * @brief Configures the port pin drive strength.
541 *
542 * @param base PORT peripheral base pointer.
543 * @param pin PORT pin number.
544 * @param strength PORT pin drive strength
545 * - #kPORT_LowDriveStrength = 0U - Low-drive strength is configured.
546 * - #kPORT_HighDriveStrength = 1U - High-drive strength is configured.
547 */
PORT_SetPinDriveStrength(PORT_Type * base,uint32_t pin,uint8_t strength)548 static inline void PORT_SetPinDriveStrength(PORT_Type *base, uint32_t pin, uint8_t strength)
549 {
550 base->PCR[pin] = (base->PCR[pin] & ~PORT_PCR_DSE_MASK) | PORT_PCR_DSE(strength);
551 }
552 #endif
553
554 #if defined(FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH1) && FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH1
555 /*!
556 * @brief Enables the port pin double drive strength.
557 *
558 * @param base PORT peripheral base pointer.
559 * @param pin PORT pin number.
560 * @param enable PORT pin drive strength configuration.
561 */
PORT_EnablePinDoubleDriveStrength(PORT_Type * base,uint32_t pin,bool enable)562 static inline void PORT_EnablePinDoubleDriveStrength(PORT_Type *base, uint32_t pin, bool enable)
563 {
564 base->PCR[pin] = (base->PCR[pin] & ~PORT_PCR_DSE1_MASK) | PORT_PCR_DSE1(enable);
565 }
566 #endif
567
568 #if defined(FSL_FEATURE_PORT_PCR_HAS_PULL_VALUE) && FSL_FEATURE_PORT_PCR_HAS_PULL_VALUE
569 /*!
570 * @brief Configures the port pin pull value.
571 *
572 * @param base PORT peripheral base pointer.
573 * @param pin PORT pin number.
574 * @param value PORT pin pull value
575 * - #kPORT_LowPullResistor = 0U - Low internal pull resistor value is selected.
576 * - #kPORT_HighPullResistor = 1U - High internal pull resistor value is selected.
577 */
PORT_SetPinPullValue(PORT_Type * base,uint32_t pin,uint8_t value)578 static inline void PORT_SetPinPullValue(PORT_Type *base, uint32_t pin, uint8_t value)
579 {
580 base->PCR[pin] = (base->PCR[pin] & ~PORT_PCR_PV_MASK) | PORT_PCR_PV(value);
581 }
582 #endif /* FSL_FEATURE_PORT_PCR_HAS_PULL_VALUE */
583
584 #if !(defined(FSL_FEATURE_PORT_HAS_NO_INTERRUPT) && FSL_FEATURE_PORT_HAS_NO_INTERRUPT)
585 /*!
586 * @brief Reads the whole port status flag.
587 *
588 * If a pin is configured to generate the DMA request, the corresponding flag
589 * is cleared automatically at the completion of the requested DMA transfer.
590 * Otherwise, the flag remains set until a logic one is written to that flag.
591 * If configured for a level sensitive interrupt that remains asserted, the flag
592 * is set again immediately.
593 *
594 * @param base PORT peripheral base pointer.
595 * @return Current port interrupt status flags, for example, 0x00010001 means the
596 * pin 0 and 16 have the interrupt.
597 */
PORT_GetPinsInterruptFlags(PORT_Type * base)598 static inline uint32_t PORT_GetPinsInterruptFlags(PORT_Type *base)
599 {
600 return base->ISFR;
601 }
602
603 /*!
604 * @brief Clears the multiple pin interrupt status flag.
605 *
606 * @param base PORT peripheral base pointer.
607 * @param mask PORT pin number macro.
608 */
PORT_ClearPinsInterruptFlags(PORT_Type * base,uint32_t mask)609 static inline void PORT_ClearPinsInterruptFlags(PORT_Type *base, uint32_t mask)
610 {
611 base->ISFR = mask;
612 }
613 #endif
614
615 #if defined(FSL_FEATURE_PORT_SUPPORT_EFT) && FSL_FEATURE_PORT_SUPPORT_EFT
616 /*!
617 * @brief Get EFT detect flags.
618 *
619 * @param base PORT peripheral base pointer
620 * @return EFT detect flags
621 */
PORT_GetEFTDetectFlags(PORT_Type * base)622 static inline uint32_t PORT_GetEFTDetectFlags(PORT_Type *base)
623 {
624 return base->EDFR;
625 }
626
627 /*!
628 * @brief Enable EFT detect interrupts.
629 *
630 * @param base PORT peripheral base pointer
631 * @param interrupt EFT detect interrupt
632 */
PORT_EnableEFTDetectInterrupts(PORT_Type * base,uint32_t interrupt)633 static inline void PORT_EnableEFTDetectInterrupts(PORT_Type *base, uint32_t interrupt)
634 {
635 base->EDIER |= interrupt;
636 }
637
638 /*!
639 * @brief Disable EFT detect interrupts.
640 *
641 * @param base PORT peripheral base pointer
642 * @param interrupt EFT detect interrupt
643 */
PORT_DisableEFTDetectInterrupts(PORT_Type * base,uint32_t interrupt)644 static inline void PORT_DisableEFTDetectInterrupts(PORT_Type *base, uint32_t interrupt)
645 {
646 base->EDIER &= ~interrupt;
647 }
648
649 /*!
650 * @brief Clear all low EFT detector.
651 *
652 * @note : Port B and Port C pins share the same EFT detector clear control from PORTC_EDCR register. Any write to the
653 * PORTB_EDCR does not take effect.
654 * @param base PORT peripheral base pointer
655 * @param interrupt EFT detect interrupt
656 */
PORT_ClearAllLowEFTDetectors(PORT_Type * base)657 static inline void PORT_ClearAllLowEFTDetectors(PORT_Type *base)
658 {
659 base->EDCR |= PORT_EDCR_EDLC_MASK;
660 base->EDCR &= ~PORT_EDCR_EDLC_MASK;
661 }
662
663 /*!
664 * @brief Clear all high EFT detector.
665 *
666 * @param base PORT peripheral base pointer
667 * @param interrupt EFT detect interrupt
668 */
PORT_ClearAllHighEFTDetectors(PORT_Type * base)669 static inline void PORT_ClearAllHighEFTDetectors(PORT_Type *base)
670 {
671 base->EDCR |= PORT_EDCR_EDHC_MASK;
672 base->EDCR &= ~PORT_EDCR_EDHC_MASK;
673 }
674 #endif /* FSL_FEATURE_PORT_SUPPORT_EFT */
675
676 /*! @} */
677
678 #if defined(__cplusplus)
679 }
680 #endif
681
682 /*! @}*/
683
684 #endif /* FSL_PORT_H_ */
685
