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Searched refs:SYSCON_FRG_FRGDIV_DIV_MASK (Results 1 – 18 of 18) sorted by relevance

/hal_nxp-latest/mcux/mcux-sdk/devices/LPC804/drivers/
Dfsl_clock.c86 CLK_FRG_DIV_REG_MAP(base) = SYSCON_FRG_FRGDIV_DIV_MASK; in CLOCK_SetFRGClkFreq()
Dfsl_clock.h442 CLK_FRG_DIV_REG_MAP(base) = SYSCON_FRG_FRGDIV_DIV_MASK; in CLOCK_SetFRGClkMul()
/hal_nxp-latest/mcux/mcux-sdk/devices/LPC802/drivers/
Dfsl_clock.c93 CLK_FRG_DIV_REG_MAP(base) = SYSCON_FRG_FRGDIV_DIV_MASK; in CLOCK_SetFRGClkFreq()
Dfsl_clock.h422 CLK_FRG_DIV_REG_MAP(base) = SYSCON_FRG_FRGDIV_DIV_MASK; in CLOCK_SetFRGClkMul()
/hal_nxp-latest/mcux/mcux-sdk/devices/LPC845/drivers/
Dfsl_clock.c93 CLK_FRG_DIV_REG_MAP(base) = SYSCON_FRG_FRGDIV_DIV_MASK; in CLOCK_SetFRGClkFreq()
Dfsl_clock.h638 CLK_FRG_DIV_REG_MAP(base) = SYSCON_FRG_FRGDIV_DIV_MASK; in CLOCK_SetFRGClkMul()
/hal_nxp-latest/mcux/mcux-sdk/devices/LPC864/drivers/
Dfsl_clock.c91 CLK_FRG_DIV_REG_MAP(base) = SYSCON_FRG_FRGDIV_DIV_MASK; in CLOCK_SetFRGClkFreq()
Dfsl_clock.h555 CLK_FRG_DIV_REG_MAP(base) = SYSCON_FRG_FRGDIV_DIV_MASK; in CLOCK_SetFRGClkMul()
/hal_nxp-latest/mcux/mcux-sdk/devices/LPC865/drivers/
Dfsl_clock.c91 CLK_FRG_DIV_REG_MAP(base) = SYSCON_FRG_FRGDIV_DIV_MASK; in CLOCK_SetFRGClkFreq()
Dfsl_clock.h555 CLK_FRG_DIV_REG_MAP(base) = SYSCON_FRG_FRGDIV_DIV_MASK; in CLOCK_SetFRGClkMul()
/hal_nxp-latest/mcux/mcux-sdk/devices/LPC844/drivers/
Dfsl_clock.c93 CLK_FRG_DIV_REG_MAP(base) = SYSCON_FRG_FRGDIV_DIV_MASK; in CLOCK_SetFRGClkFreq()
Dfsl_clock.h588 CLK_FRG_DIV_REG_MAP(base) = SYSCON_FRG_FRGDIV_DIV_MASK; in CLOCK_SetFRGClkMul()
/hal_nxp-latest/mcux/mcux-sdk/devices/LPC802/
DLPC802.h5022 #define SYSCON_FRG_FRGDIV_DIV_MASK (0xFFU) macro
5027 … (((uint32_t)(((uint32_t)(x)) << SYSCON_FRG_FRGDIV_DIV_SHIFT)) & SYSCON_FRG_FRGDIV_DIV_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/LPC804/
DLPC804.h6016 #define SYSCON_FRG_FRGDIV_DIV_MASK (0xFFU) macro
6021 … (((uint32_t)(((uint32_t)(x)) << SYSCON_FRG_FRGDIV_DIV_SHIFT)) & SYSCON_FRG_FRGDIV_DIV_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/LPC844/
DLPC844.h8130 #define SYSCON_FRG_FRGDIV_DIV_MASK (0xFFU) macro
8135 … (((uint32_t)(((uint32_t)(x)) << SYSCON_FRG_FRGDIV_DIV_SHIFT)) & SYSCON_FRG_FRGDIV_DIV_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/LPC845/
DLPC845.h8654 #define SYSCON_FRG_FRGDIV_DIV_MASK (0xFFU) macro
8659 … (((uint32_t)(((uint32_t)(x)) << SYSCON_FRG_FRGDIV_DIV_SHIFT)) & SYSCON_FRG_FRGDIV_DIV_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/LPC865/
DLPC865.h10045 #define SYSCON_FRG_FRGDIV_DIV_MASK (0xFFU) macro
10050 … (((uint32_t)(((uint32_t)(x)) << SYSCON_FRG_FRGDIV_DIV_SHIFT)) & SYSCON_FRG_FRGDIV_DIV_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/LPC864/
DLPC864.h10043 #define SYSCON_FRG_FRGDIV_DIV_MASK (0xFFU) macro
10048 … (((uint32_t)(((uint32_t)(x)) << SYSCON_FRG_FRGDIV_DIV_SHIFT)) & SYSCON_FRG_FRGDIV_DIV_MASK)