1 /*
2 * Copyright 2017-2021 NXP
3 * All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7
8 #ifndef _FSL_CLOCK_H_
9 #define _FSL_CLOCK_H_
10
11 #include "fsl_common.h"
12
13 /*! @addtogroup clock */
14 /*! @{ */
15
16 /*! @file */
17
18 /*******************************************************************************
19 * Definitions
20 *****************************************************************************/
21
22 /*! @name Driver version */
23 /*@{*/
24 /*! @brief CLOCK driver version 2.3.3. */
25 #define FSL_CLOCK_DRIVER_VERSION (MAKE_VERSION(2, 3, 4))
26 /*@}*/
27
28 /* Definition for delay API in clock driver, users can redefine it to the real application. */
29 #ifndef SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY
30 #define SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY (60000000UL)
31 #endif
32
33 /*! @brief Low power oscilltor clock frequency.
34 *
35 * Definition for the low power oscillator frequency which is
36 * 1 Mhz at default, and it is returned by CLOCK_GetLpOscFreq.
37 */
38 #define g_Lp_Osc_Freq 1000000U;
39
40 /*! @brief external clock frequency.
41 *
42 * This variable is used to store the external clock frequency which is include
43 * external oscillator clock and external clk in clock frequency value, it is
44 * set by CLOCK_InitExtClkin when CLK IN is used as external clock or by CLOCK_InitSysOsc
45 * when external oscillator is used as external clock ,and it is returned by
46 * CLOCK_GetExtClkFreq.
47 */
48 extern volatile uint32_t g_Ext_Clk_Freq;
49
50 /*! @brief FRO clock setting API address in ROM. */
51 #define CLOCK_FRO_SETTING_API_ROM_ADDRESS (0x0F001B5DU)
52 /*! @brief FAIM base address*/
53 #define CLOCK_FAIM_BASE (0x50010000U)
54
55 /*! @brief Clock ip name array for ADC. */
56 #define ADC_CLOCKS \
57 { \
58 kCLOCK_Adc, \
59 }
60 /*! @brief Clock ip name array for ACMP. */
61 #define ACMP_CLOCKS \
62 { \
63 kCLOCK_Acmp, \
64 }
65 /*! @brief Clock ip name array for SWM. */
66 #define SWM_CLOCKS \
67 { \
68 kCLOCK_Swm, \
69 }
70 /*! @brief Clock ip name array for ROM. */
71 #define ROM_CLOCKS \
72 { \
73 kCLOCK_Rom, \
74 }
75 /*! @brief Clock ip name array for SRAM. */
76 #define SRAM_CLOCKS \
77 { \
78 kCLOCK_Ram0_1, \
79 }
80 /*! @brief Clock ip name array for IOCON. */
81 #define IOCON_CLOCKS \
82 { \
83 kCLOCK_Iocon, \
84 }
85 /*! @brief Clock ip name array for GPIO. */
86 #define GPIO_CLOCKS \
87 { \
88 kCLOCK_Gpio0, kCLOCK_Gpio1, \
89 }
90 /*! @brief Clock ip name array for GPIO_INT. */
91 #define GPIO_INT_CLOCKS \
92 { \
93 kCLOCK_GpioInt, \
94 }
95 /*! @brief Clock ip name array for DMA. */
96 #define DMA_CLOCKS \
97 { \
98 kCLOCK_Dma, \
99 }
100 /*! @brief Clock ip name array for CRC. */
101 #define CRC_CLOCKS \
102 { \
103 kCLOCK_Crc, \
104 }
105 /*! @brief Clock ip name array for WWDT. */
106 #define WWDT_CLOCKS \
107 { \
108 kCLOCK_Wwdt, \
109 }
110 /*! @brief Clock ip name array for I2C. */
111 #define I2C_CLOCKS \
112 { \
113 kCLOCK_I2c0, \
114 }
115 /*! @brief Clock ip name array for I2C. */
116 #define USART_CLOCKS \
117 { \
118 kCLOCK_Uart0, kCLOCK_Uart1, kCLOCK_Uart2, \
119 }
120 /*! @brief Clock ip name array for SPI. */
121 #define SPI_CLOCKS \
122 { \
123 kCLOCK_Spi0, kCLOCK_Spi1, \
124 }
125 /*! @brief Clock ip name array for MRT. */
126 #define MRT_CLOCKS \
127 { \
128 kCLOCK_Mrt, \
129 }
130 /*! @brief Clock ip name array for WKT. */
131 #define WKT_CLOCKS \
132 { \
133 kCLOCK_Wkt, \
134 }
135 /*! @brief Clock ip name array for FLEXTMR. */
136 #define FTM_CLOCKS \
137 { \
138 kCLOCK_Ftm0, kCLOCK_Ftm1 \
139 }
140 /*! @brief Clock ip name array for I3C */
141 #define I3C_CLOCKS \
142 { \
143 kCLOCK_I3c0 \
144 }
145
146 /*! @brief Internal used Clock definition only. */
147 #define CLK_GATE_DEFINE(reg, bit) ((((reg) & 0xFFU) << 8U) | ((bit) & 0xFFU))
148 #define CLK_GATE_GET_REG(x) (((uint32_t)(x) >> 8U) & 0xFFU)
149 #define CLK_GATE_GET_BITS_SHIFT(x) ((uint32_t)(x) & 0xFFU)
150 /* clock mux register definition */
151 #define CLK_MUX_DEFINE(reg, mux) (((offsetof(SYSCON_Type, reg) & 0xFFU) << 8U) | ((mux) & 0xFFU))
152 #define CLK_MUX_GET_REG(x) ((volatile uint32_t *)(((uint32_t)(SYSCON)) + (((uint32_t)(x) >> 8U) & 0xFFU)))
153 #define CLK_MUX_GET_MUX(x) (((uint32_t)(x)) & 0xFFU)
154 #define CLK_MAIN_CLK_MUX_DEFINE(preMux, mux) ((preMux) << 8U | (mux))
155 #define CLK_MAIN_CLK_MUX_GET_PRE_MUX(x) (((uint32_t)(x) >> 8U) & 0xFFU)
156 #define CLK_MAIN_CLK_MUX_GET_MUX(x) ((uint32_t)(x) & 0xFFU)
157 /* clock divider register definition */
158 #define CLK_DIV_DEFINE(reg) (((uint32_t)offsetof(SYSCON_Type, reg)) & 0xFFFU)
159 #define CLK_DIV_GET_REG(x) *((volatile uint32_t *)(((uint32_t)(SYSCON)) + ((uint32_t)(x) & 0xFFFU)))
160 /* watch dog oscillator definition */
161 #define CLK_WDT_OSC_DEFINE(freq, regValue) (((freq) & 0xFFFFFFU) | (((regValue) & 0xFFU) << 24U))
162 #define CLK_WDT_OSC_GET_FREQ(x) ((uint32_t)(x) & 0xFFFFFFU)
163 #define CLK_WDT_OSC_GET_REG(x) (((x) >> 24U) & 0xFFU)
164 /* Fractional clock register map */
165 #define CLK_FRG_DIV_REG_MAP(base) (*(base))
166 #define CLK_FRG_MUL_REG_MAP(base) (*((uint32_t *)((uint32_t)(base) + 4U)))
167 #define CLK_FRG_SEL_REG_MAP(base) (*((uint32_t *)((uint32_t)(base) + 8U)))
168 /* register offset */
169 #define SYS_AHB_CLK_CTRL0 (0U)
170 #define SYS_AHB_CLK_CTRL1 (4U)
171
172 /*! @brief Clock gate name used for CLOCK_EnableClock/CLOCK_DisableClock. */
173 typedef enum _clock_ip_name
174 {
175 kCLOCK_IpInvalid = 0U, /*!< Invalid Ip Name. */
176 kCLOCK_Rom = CLK_GATE_DEFINE(SYS_AHB_CLK_CTRL0, 1U), /*!< Clock gate name: Rom. */
177
178 kCLOCK_Ram0_1 = CLK_GATE_DEFINE(SYS_AHB_CLK_CTRL0, 2U), /*!< Clock gate name: Ram0_1. */
179
180 kCLOCK_I2c0 = CLK_GATE_DEFINE(SYS_AHB_CLK_CTRL0, 5U), /*!< Clock gate name: I2c0. */
181
182 kCLOCK_Gpio0 = CLK_GATE_DEFINE(SYS_AHB_CLK_CTRL0, 6U), /*!< Clock gate name: Gpio0. */
183
184 kCLOCK_Swm = CLK_GATE_DEFINE(SYS_AHB_CLK_CTRL0, 7U), /*!< Clock gate name: Swm. */
185
186 kCLOCK_Wkt = CLK_GATE_DEFINE(SYS_AHB_CLK_CTRL0, 9U), /*!< Clock gate name: Wkt. */
187
188 kCLOCK_Mrt = CLK_GATE_DEFINE(SYS_AHB_CLK_CTRL0, 10U), /*!< Clock gate name: Mrt. */
189
190 kCLOCK_Spi0 = CLK_GATE_DEFINE(SYS_AHB_CLK_CTRL0, 11U), /*!< Clock gate name: Spi0. */
191
192 kCLOCK_Spi1 = CLK_GATE_DEFINE(SYS_AHB_CLK_CTRL0, 12U), /*!< Clock gate name: Spi1. */
193
194 kCLOCK_Crc = CLK_GATE_DEFINE(SYS_AHB_CLK_CTRL0, 13U), /*!< Clock gate name: Crc. */
195
196 kCLOCK_Uart0 = CLK_GATE_DEFINE(SYS_AHB_CLK_CTRL0, 14U), /*!< Clock gate name: Uart0. */
197
198 kCLOCK_Uart1 = CLK_GATE_DEFINE(SYS_AHB_CLK_CTRL0, 15U), /*!< Clock gate name: Uart1. */
199
200 kCLOCK_Uart2 = CLK_GATE_DEFINE(SYS_AHB_CLK_CTRL0, 16U), /*!< Clock gate name: Uart2. */
201
202 kCLOCK_Wwdt = CLK_GATE_DEFINE(SYS_AHB_CLK_CTRL0, 17U), /*!< Clock gate name: Wwdt. */
203
204 kCLOCK_Iocon = CLK_GATE_DEFINE(SYS_AHB_CLK_CTRL0, 18U), /*!< Clock gate name: Iocon. */
205
206 kCLOCK_Acmp = CLK_GATE_DEFINE(SYS_AHB_CLK_CTRL0, 19U), /*!< Clock gate name: Acmp. */
207
208 kCLOCK_Gpio1 = CLK_GATE_DEFINE(SYS_AHB_CLK_CTRL0, 20U), /*!< Clock gate name: Gpio1. */
209
210 kCLOCK_Ftm0 = CLK_GATE_DEFINE(SYS_AHB_CLK_CTRL0, 21U), /*!< Clock gate name: Ftm0. */
211
212 kCLOCK_Ftm1 = CLK_GATE_DEFINE(SYS_AHB_CLK_CTRL0, 22U), /*!< Clock gate name: Ftm1. */
213
214 kCLOCK_I3c0 = CLK_GATE_DEFINE(SYS_AHB_CLK_CTRL0, 23U), /*!< Clock gate name: I3c0. */
215
216 kCLOCK_Adc = CLK_GATE_DEFINE(SYS_AHB_CLK_CTRL0, 24U), /*!< Clock gate name: Adc. */
217
218 kCLOCK_GpioInt = CLK_GATE_DEFINE(SYS_AHB_CLK_CTRL0, 28U), /*!< Clock gate name: GpioInt. */
219
220 kCLOCK_Dma = CLK_GATE_DEFINE(SYS_AHB_CLK_CTRL0, 29U), /*!< Clock gate name: Dma. */
221
222 } clock_ip_name_t;
223
224 /*! @brief Clock name used to get clock frequency. */
225 typedef enum _clock_name
226 {
227 kCLOCK_CoreSysClk, /*!< Cpu/AHB/AHB matrix/Memories,etc */
228 kCLOCK_MainClk, /*!< Main clock */
229
230 kCLOCK_Fro, /*!< FRO18/24/30 */
231 kCLOCK_FroDiv, /*!< FRO div clock */
232 kCLOCK_ExtClk, /*!< External Clock */
233 kCLOCK_PllOut, /*!< PLL Output */
234 kCLOCK_LpOsc, /*!< Low power Oscillator */
235 kCLOCK_Frg0, /*!< fractional rate0 */
236 kCLOCK_Frg1, /*!< fractional rate1 */
237 } clock_name_t;
238
239 /*! @brief Clock Mux Switches
240 *CLK_MUX_DEFINE(reg, mux)
241 *reg is used to define the mux register
242 *mux is used to define the mux value
243 *
244 */
245 typedef enum _clock_select
246 {
247 kADC_Clk_From_Fro = CLK_MUX_DEFINE(ADCCLKSEL, 0U), /*!< Mux ADC_Clk from Fro. */
248
249 kADC_Clk_From_SysPll_DIV = CLK_MUX_DEFINE(ADCCLKSEL, 1U), /*!< Mux ADC_Clk from SysPllDiv. */
250
251 kEXT_Clk_From_SysOsc = CLK_MUX_DEFINE(EXTCLKSEL, 0U), /*!< Mux EXT_Clk from SysOsc. */
252
253 kEXT_Clk_From_ClkIn = CLK_MUX_DEFINE(EXTCLKSEL, 1U), /*!< Mux EXT_Clk from ClkIn. */
254
255 kUART0_Clk_From_Fro = CLK_MUX_DEFINE(FCLKSEL[0U], 0U), /*!< Mux UART0_Clk from Fro. */
256
257 kUART0_Clk_From_MainClk = CLK_MUX_DEFINE(FCLKSEL[0U], 1U), /*!< Mux UART0_Clk from MainClk. */
258
259 kUART0_Clk_From_Frg0Clk = CLK_MUX_DEFINE(FCLKSEL[0U], 2U), /*!< Mux UART0_Clk from Frg0Clk. */
260
261 kUART0_Clk_From_Frg1Clk = CLK_MUX_DEFINE(FCLKSEL[0U], 3U), /*!< Mux UART0_Clk from Frg1Clk. */
262
263 kUART0_Clk_From_Fro_Div = CLK_MUX_DEFINE(FCLKSEL[0U], 4U), /*!< Mux UART0_Clk from Fro_Div. */
264
265 kUART1_Clk_From_Fro = CLK_MUX_DEFINE(FCLKSEL[1U], 0U), /*!< Mux UART1_Clk from Fro. */
266
267 kUART1_Clk_From_MainClk = CLK_MUX_DEFINE(FCLKSEL[1U], 1U), /*!< Mux UART1_Clk from MainClk. */
268
269 kUART1_Clk_From_Frg0Clk = CLK_MUX_DEFINE(FCLKSEL[1U], 2U), /*!< Mux UART1_Clk from Frg0Clk. */
270
271 kUART1_Clk_From_Frg1Clk = CLK_MUX_DEFINE(FCLKSEL[1U], 3U), /*!< Mux UART1_Clk from Frg1Clk. */
272
273 kUART1_Clk_From_Fro_Div = CLK_MUX_DEFINE(FCLKSEL[1U], 4U), /*!< Mux UART1_Clk from Fro_Div. */
274
275 kUART2_Clk_From_Fro = CLK_MUX_DEFINE(FCLKSEL[2U], 0U), /*!< Mux UART2_Clk from Fro. */
276
277 kUART2_Clk_From_MainClk = CLK_MUX_DEFINE(FCLKSEL[2U], 1U), /*!< Mux UART2_Clk from MainClk. */
278
279 kUART2_Clk_From_Frg0Clk = CLK_MUX_DEFINE(FCLKSEL[2U], 2U), /*!< Mux UART2_Clk from Frg0Clk. */
280
281 kUART2_Clk_From_Frg1Clk = CLK_MUX_DEFINE(FCLKSEL[2U], 3U), /*!< Mux UART2_Clk from Frg1Clk. */
282
283 kUART2_Clk_From_Fro_Div = CLK_MUX_DEFINE(FCLKSEL[2U], 4U), /*!< Mux UART2_Clk from Fro_Div. */
284
285 kI2C0_Clk_From_Fro = CLK_MUX_DEFINE(FCLKSEL[5U], 0U), /*!< Mux I2C0_Clk from Fro. */
286
287 kI2C0_Clk_From_MainClk = CLK_MUX_DEFINE(FCLKSEL[5U], 1U), /*!< Mux I2C0_Clk from MainClk. */
288
289 kI2C0_Clk_From_Frg0Clk = CLK_MUX_DEFINE(FCLKSEL[5U], 2U), /*!< Mux I2C0_Clk from Frg0Clk. */
290
291 kI2C0_Clk_From_Frg1Clk = CLK_MUX_DEFINE(FCLKSEL[5U], 3U), /*!< Mux I2C0_Clk from Frg1Clk. */
292
293 kI2C0_Clk_From_Fro_Div = CLK_MUX_DEFINE(FCLKSEL[5U], 4U), /*!< Mux I2C0_Clk from Fro_Div. */
294
295 kI3C_Clk_From_Fro = CLK_MUX_DEFINE(I3CCLKSEL, 0U), /*!< Mux I3C_Clk from Fro. */
296
297 kI3C_Clk_From_ExtClk = CLK_MUX_DEFINE(I3CCLKSEL, 1U), /*!< Mux I3C_Clk from ExtClk. */
298
299 kI3C_TC_Clk_From_I3C_Clk = CLK_MUX_DEFINE(I3CSLOWTCCLKSEL, 0U), /*!< Mux I3C_TC_Clk from I3C_Clk. */
300
301 kI3C_TC_Clk_From_LpOsc = CLK_MUX_DEFINE(I3CSLOWTCCLKSEL, 1U), /*!< Mux I3C_TC_Clk from LpOsc. */
302
303 kSPI0_Clk_From_Fro = CLK_MUX_DEFINE(FCLKSEL2[0U], 0U), /*!< Mux SPI0_Clk from Fro. */
304
305 kSPI0_Clk_From_MainClk = CLK_MUX_DEFINE(FCLKSEL2[0U], 1U), /*!< Mux SPI0_Clk from MainClk. */
306
307 kSPI0_Clk_From_Frg0Clk = CLK_MUX_DEFINE(FCLKSEL2[0U], 2U), /*!< Mux SPI0_Clk from Frg0Clk. */
308
309 kSPI0_Clk_From_Frg1Clk = CLK_MUX_DEFINE(FCLKSEL2[0U], 3U), /*!< Mux SPI0_Clk from Frg1Clk. */
310
311 kSPI0_Clk_From_Fro_Div = CLK_MUX_DEFINE(FCLKSEL2[0U], 4U), /*!< Mux SPI0_Clk from Fro_Div. */
312
313 kSPI1_Clk_From_Fro = CLK_MUX_DEFINE(FCLKSEL2[1U], 0U), /*!< Mux SPI1_Clk from Fro. */
314
315 kSPI1_Clk_From_MainClk = CLK_MUX_DEFINE(FCLKSEL2[1U], 1U), /*!< Mux SPI1_Clk from MainClk. */
316
317 kSPI1_Clk_From_Frg0Clk = CLK_MUX_DEFINE(FCLKSEL2[1U], 2U), /*!< Mux SPI1_Clk from Frg0Clk. */
318
319 kSPI1_Clk_From_Frg1Clk = CLK_MUX_DEFINE(FCLKSEL2[1U], 3U), /*!< Mux SPI1_Clk from Frg1Clk. */
320
321 kSPI1_Clk_From_Fro_Div = CLK_MUX_DEFINE(FCLKSEL2[1U], 4U), /*!< Mux SPI1_Clk from Fro_Div. */
322
323 kFRG0_Clk_From_Fro = CLK_MUX_DEFINE(FRG[0U].FRGCLKSEL, 0U), /*!< Mux FRG0_Clk from Fro. */
324
325 kFRG0_Clk_From_MainClk = CLK_MUX_DEFINE(FRG[0U].FRGCLKSEL, 1U), /*!< Mux FRG0_Clk from MainClk. */
326
327 kFRG0_Clk_From_SysPll_DIV = CLK_MUX_DEFINE(FRG[0U].FRGCLKSEL, 2U), /*!< Mux FRG0_Clk from SysPllDiv. */
328
329 kFRG1_Clk_From_Fro = CLK_MUX_DEFINE(FRG[1U].FRGCLKSEL, 0U), /*!< Mux FRG1_Clk from Fro. */
330
331 kFRG1_Clk_From_MainClk = CLK_MUX_DEFINE(FRG[1U].FRGCLKSEL, 1U), /*!< Mux FRG1_Clk from MainClk. */
332
333 kFRG1_Clk_From_SysPll_DIV = CLK_MUX_DEFINE(FRG[1U].FRGCLKSEL, 2U), /*!< Mux FRG1_Clk from SysPllDiv. */
334
335 kCLKOUT_From_Fro = CLK_MUX_DEFINE(CLKOUTSEL, 0U), /*!< Mux CLKOUT from Fro. */
336
337 kCLKOUT_From_MainClk = CLK_MUX_DEFINE(CLKOUTSEL, 1U), /*!< Mux CLKOUT from MainClk. */
338
339 kCLKOUT_From_SysPll_DIV = CLK_MUX_DEFINE(CLKOUTSEL, 2U), /*!< Mux CLKOUT from SysPllDiv. */
340
341 kCLKOUT_From_ExtClk = CLK_MUX_DEFINE(CLKOUTSEL, 3U), /*!< Mux CLKOUT from ExtClk. */
342
343 kCLKOUT_From_LpOsc = CLK_MUX_DEFINE(CLKOUTSEL, 4U), /*!< Mux CLKOUT from LpOsc. */
344
345 kWKT_Clk_From_Fro = CLK_MUX_DEFINE(WKTCLKSEL, 0U), /*!< Mux Wkt_Clk from FroOsc. */
346
347 kWKT_Clk_From_LpOsc = CLK_MUX_DEFINE(WKTCLKSEL, 1U), /*!< Mux Wkt_Clk from LpOsc. */
348
349 } clock_select_t;
350
351 /*! @brief Clock divider
352 */
353 typedef enum _clock_divider
354 {
355 kCLOCK_DivPllClk = CLK_DIV_DEFINE(SYSPLLDIV), /*!< Pll Clock Divider. */
356
357 kCLOCK_DivAdcClk = CLK_DIV_DEFINE(ADCCLKDIV), /*!< Adc Clock Divider. */
358
359 kCLOCK_DivClkOut = CLK_DIV_DEFINE(CLKOUTDIV), /*!< Clk Out Divider. */
360
361 kCLOCK_IOCONCLKDiv6 = CLK_DIV_DEFINE(IOCONCLKDIV6), /*!< IOCON Clock Div6 Divider. */
362
363 kCLOCK_IOCONCLKDiv5 = CLK_DIV_DEFINE(IOCONCLKDIV5), /*!< IOCON Clock Div5 Divider. */
364
365 kCLOCK_IOCONCLKDiv4 = CLK_DIV_DEFINE(IOCONCLKDIV4), /*!< IOCON Clock Div4 Divider. */
366
367 kCLOCK_IOCONCLKDiv3 = CLK_DIV_DEFINE(IOCONCLKDIV3), /*!< IOCON Clock Div3 Divider. */
368
369 kCLOCK_IOCONCLKDiv2 = CLK_DIV_DEFINE(IOCONCLKDIV2), /*!< IOCON Clock Div2 Divider. */
370
371 kCLOCK_IOCONCLKDiv1 = CLK_DIV_DEFINE(IOCONCLKDIV1), /*!< IOCON Clock Div1 Divider. */
372
373 kCLOCK_IOCONCLKDiv0 = CLK_DIV_DEFINE(IOCONCLKDIV0), /*!< IOCON Clock Div0 Divider. */
374
375 } clock_divider_t;
376
377 /*! @brief fro output frequency source definition */
378 typedef enum _clock_fro_src
379 {
380 kCLOCK_FroSrcFroOscDiv = 0U, /*!< fro source from the fro oscillator divided by 2 */
381 kCLOCK_FroSrcFroOsc = 1U << SYSCON_FROOSCCTRL_FRO_DIRECT_SHIFT, /*!< fre source from the fro oscillator directly */
382 } clock_fro_src_t;
383
384 /*! @brief fro oscillator output frequency value definition */
385 typedef enum _clock_fro_osc_freq
386 {
387 kCLOCK_FroOscOut36M = 36000U, /*!< FRO oscillator output 36M */
388 kCLOCK_FroOscOut48M = 48000U, /*!< FRO oscillator output 48M */
389 kCLOCK_FroOscOut60M = 60000U, /*!< FRO oscillator output 60M */
390 } clock_fro_osc_freq_t;
391
392 /*! @brief PLL clock definition.*/
393 typedef enum _clock_sys_pll_src
394 {
395 kCLOCK_SysPllSrcFRO = 0U, /*!< system pll source from FRO */
396 kCLOCK_SysPllSrcExtClk = 1U, /*!< system pll source from external clock */
397 kCLOCK_SysPllSrcLpOsc = 2U, /*!< system pll source from Low power oscillator */
398 kCLOCK_SysPllSrcFroDiv = 3U, /*!< system pll source from FRO divided clock */
399 } clock_sys_pll_src;
400
401 /*! @brief Main clock source definition */
402 typedef enum _clock_main_clk_src
403 {
404 kCLOCK_MainClkSrcFro = CLK_MAIN_CLK_MUX_DEFINE(0U, 0U), /*!< main clock source from FRO */
405 kCLOCK_MainClkSrcExtClk = CLK_MAIN_CLK_MUX_DEFINE(1U, 0U), /*!< main clock source from Ext clock */
406 kCLOCK_MainClkSrcLpOsc = CLK_MAIN_CLK_MUX_DEFINE(2U, 0U), /*!< main clock source from Low power oscillator */
407 kCLOCK_MainClkSrcFroDiv = CLK_MAIN_CLK_MUX_DEFINE(3U, 0U), /*!< main clock source from FRO Div */
408 kCLOCK_MainClkSrcSysPll = CLK_MAIN_CLK_MUX_DEFINE(0U, 1U), /*!< main clock source from system pll */
409 } clock_main_clk_src_t;
410
411 /*! @brief PLL configuration structure */
412 typedef struct _clock_sys_pll
413 {
414 uint32_t targetFreq; /*!< System pll fclk output frequency, the output frequency should be lower than 100MHZ*/
415 clock_sys_pll_src src; /*!< System pll clock source */
416 } clock_sys_pll_t;
417
418 /*******************************************************************************
419 * API
420 ******************************************************************************/
421
422 #if defined(__cplusplus)
423 extern "C" {
424 #endif /* __cplusplus */
425
426 /*!
427 * @name Clock gate, mux, and divider.
428 * @{
429 */
430
431 /*
432 *! @brief enable ip clock.
433 *
434 * @param clk clock ip definition.
435 */
CLOCK_EnableClock(clock_ip_name_t clk)436 static inline void CLOCK_EnableClock(clock_ip_name_t clk)
437 {
438 *(volatile uint32_t *)(((uint32_t)(&SYSCON->SYSAHBCLKCTRL0)) + CLK_GATE_GET_REG(clk)) |=
439 1UL << CLK_GATE_GET_BITS_SHIFT(clk);
440 }
441
442 /*
443 *!@brief disable ip clock.
444 *
445 * @param clk clock ip definition.
446 */
CLOCK_DisableClock(clock_ip_name_t clk)447 static inline void CLOCK_DisableClock(clock_ip_name_t clk)
448 {
449 *(volatile uint32_t *)(((uint32_t)(&SYSCON->SYSAHBCLKCTRL0)) + CLK_GATE_GET_REG(clk)) &=
450 ~(1UL << CLK_GATE_GET_BITS_SHIFT(clk));
451 }
452
453 /*
454 *! @brief Configure the clock selection muxes.
455 * @param mux : Clock to be configured.
456 * @return Nothing
457 */
CLOCK_Select(clock_select_t sel)458 static inline void CLOCK_Select(clock_select_t sel)
459 {
460 *(CLK_MUX_GET_REG(sel)) = CLK_MUX_GET_MUX(sel);
461 }
462
463 /*
464 *! @brief Setup peripheral clock dividers.
465 * @param name : Clock divider name
466 * @param value: Value to be divided
467 * @return Nothing
468 */
CLOCK_SetClkDivider(clock_divider_t name,uint32_t value)469 static inline void CLOCK_SetClkDivider(clock_divider_t name, uint32_t value)
470 {
471 CLK_DIV_GET_REG(name) = value & 0xFFU;
472 }
473
474 /*
475 *! @brief Get peripheral clock dividers.
476 * @param name : Clock divider name
477 * @return clock divider value
478 */
CLOCK_GetClkDivider(clock_divider_t name)479 static inline uint32_t CLOCK_GetClkDivider(clock_divider_t name)
480 {
481 return CLK_DIV_GET_REG(name) & 0xFFU;
482 }
483
484 /*
485 *! @brief Setup Core clock dividers.
486 * Be careful about the core divider value, due to core/system frequency should be lower than 30MHZ.
487 * @param value: Value to be divided
488 * @return Nothing
489 */
CLOCK_SetCoreSysClkDiv(uint32_t value)490 static inline void CLOCK_SetCoreSysClkDiv(uint32_t value)
491 {
492 assert(value != 0U);
493
494 SYSCON->SYSAHBCLKDIV = (SYSCON->SYSAHBCLKDIV & (~SYSCON_SYSAHBCLKDIV_DIV_MASK)) | SYSCON_SYSAHBCLKDIV_DIV(value);
495 }
496
497 /*
498 *! @brief Setup I3C FClk clock dividers.
499 * @param value: Value to be divided
500 * @return Nothing
501 */
CLOCK_SetI3CFClkDiv(uint32_t value)502 static inline void CLOCK_SetI3CFClkDiv(uint32_t value)
503 {
504 assert(value != 0U);
505
506 SYSCON->I3CCLKDIV =
507 (SYSCON->I3CCLKDIV & (~SYSCON_I3CCLKDIV_I3C_FCLK_DIV_MASK)) | SYSCON_I3CCLKDIV_I3C_FCLK_DIV(value);
508 }
509
510 /*
511 *! @brief Setup I3C TC clock dividers.
512 * @param value: Value to be divided
513 * @return Nothing
514 */
CLOCK_SetI3CTCClkDiv(uint32_t value)515 static inline void CLOCK_SetI3CTCClkDiv(uint32_t value)
516 {
517 assert(value != 0U);
518
519 SYSCON->I3CCLKDIV = (SYSCON->I3CCLKDIV & (~SYSCON_I3CCLKDIV_I3C_SLOW_TC_CLK_DIV_MASK)) |
520 SYSCON_I3CCLKDIV_I3C_SLOW_TC_CLK_DIV(value);
521 }
522
523 /*
524 *! @brief Setup I3C Slow clock dividers.
525 * @param value: Value to be divided
526 * @return Nothing
527 */
CLOCK_SetI3CSClkDiv(uint32_t value)528 static inline void CLOCK_SetI3CSClkDiv(uint32_t value)
529 {
530 assert(value != 0U);
531
532 SYSCON->I3CCLKDIV =
533 (SYSCON->I3CCLKDIV & (~SYSCON_I3CCLKDIV_I3C_SLOW_CLK_DIV_MASK)) | SYSCON_I3CCLKDIV_I3C_SLOW_CLK_DIV(value);
534 }
535
536 /*! @brief Set main clock reference source.
537 * @param src Refer to clock_main_clk_src_t to set the main clock source.
538 */
539 void CLOCK_SetMainClkSrc(clock_main_clk_src_t src);
540
541 /*! @brief Set FRO clock source
542 * @param src Please refer to _clock_fro_src definition.
543 *
544 */
545 void CLOCK_SetFroOutClkSrc(clock_fro_src_t src);
546
547 /*
548 *! @brief Set Fractional generator multiplier value.
549 * @param base: Fractional generator register address
550 * @param mul : FRG multiplier value.
551 * @return Nothing
552 */
CLOCK_SetFRGClkMul(uint32_t * base,uint32_t mul)553 static inline void CLOCK_SetFRGClkMul(uint32_t *base, uint32_t mul)
554 {
555 CLK_FRG_DIV_REG_MAP(base) = SYSCON_FRG_FRGDIV_DIV_MASK;
556 CLK_FRG_MUL_REG_MAP(base) = SYSCON_FRG_FRGMULT_MULT(mul);
557 }
558
559 /*! @brief Set the flash wait states for the input freuqency.
560 * @param iFreq : Input frequency
561 */
562 void CLOCK_SetFLASHAccessCyclesForFreq(uint32_t iFreq);
563 /* @} */
564
565 /*!
566 * @name Get frequency
567 * @{
568 */
569
570 /*! @brief Return Frequency of FRG0 Clock.
571 * @return Frequency of FRG0 Clock.
572 */
573 uint32_t CLOCK_GetFRG0ClkFreq(void);
574
575 /*! @brief Return Frequency of FRG1 Clock.
576 * @return Frequency of FRG1 Clock.
577 */
578 uint32_t CLOCK_GetFRG1ClkFreq(void);
579
580 /*! @brief Return Frequency of Main Clock.
581 * @return Frequency of Main Clock.
582 */
583 uint32_t CLOCK_GetMainClkFreq(void);
584
585 /*! @brief Return Frequency of FRO.
586 * @return Frequency of FRO.
587 */
588 uint32_t CLOCK_GetFroFreq(void);
589
590 /*! @brief Return Frequency of core.
591 * @return Frequency of core.
592 */
CLOCK_GetCoreSysClkFreq(void)593 static inline uint32_t CLOCK_GetCoreSysClkFreq(void)
594 {
595 return CLOCK_GetMainClkFreq() / (SYSCON->SYSAHBCLKDIV & 0xffU);
596 }
597
598 /*! @brief Return Frequency of ClockOut
599 * @return Frequency of ClockOut
600 */
601 uint32_t CLOCK_GetClockOutClkFreq(void);
602
603 /*! @brief Get UART0 frequency
604 * @retval UART0 frequency value.
605 */
606 uint32_t CLOCK_GetUart0ClkFreq(void);
607
608 /*! @brief Get UART1 frequency
609 * @retval UART1 frequency value.
610 */
611 uint32_t CLOCK_GetUart1ClkFreq(void);
612
613 /*! @brief Get UART2 frequency
614 * @retval UART2 frequency value.
615 */
616 uint32_t CLOCK_GetUart2ClkFreq(void);
617
618 /*! @brief Get UART3 frequency
619 * @retval UART3 frequency value.
620 */
621 uint32_t CLOCK_GetUart3ClkFreq(void);
622
623 /*! @brief Get UART4 frequency
624 * @retval UART4 frequency value.
625 */
626 uint32_t CLOCK_GetUart4ClkFreq(void);
627
628 /*! @brief Get I3C frequency
629 * @retval I3C frequency value.
630 */
631 uint32_t CLOCK_GetI3cClkFreq(void);
632
633 /*! @brief Get LP_OSC frequency
634 * @retval LP_OSC frequency value.
635 */
636 uint32_t CLOCK_GetLpOscClkFreq(void);
637
638 /*! @brief Return Frequency of selected clock
639 * @return Frequency of selected clock
640 */
641 uint32_t CLOCK_GetFreq(clock_name_t clockName);
642
643 /*! @brief Return System PLL input clock rate
644 * @return System PLL input clock rate
645 */
646 uint32_t CLOCK_GetSystemPLLInClockRate(void);
647
648 /*! @brief Return Frequency of System PLL
649 * @return Frequency of PLL
650 */
CLOCK_GetSystemPLLFreq(void)651 static inline uint32_t CLOCK_GetSystemPLLFreq(void)
652 {
653 return CLOCK_GetSystemPLLInClockRate() * ((SYSCON->SYSPLLCTRL & SYSCON_SYSPLLCTRL_MSEL_MASK) + 1U);
654 }
655
656 /*! @brief Get low power OSC frequency
657 * @retval low power OSC frequency value.
658 */
CLOCK_GetLpOscFreq(void)659 static inline uint32_t CLOCK_GetLpOscFreq(void)
660 {
661 return g_Lp_Osc_Freq;
662 }
663
664 /*! @brief Get external clock frequency
665 * @retval external clock frequency value.
666 */
CLOCK_GetExtClkFreq(void)667 static inline uint32_t CLOCK_GetExtClkFreq(void)
668 {
669 return g_Ext_Clk_Freq;
670 }
671 /* @} */
672
673 /*!
674 * @name PLL operations
675 * @{
676 */
677
678 /*! @brief System PLL initialize.
679 * @param config System PLL configurations.
680 */
681 void CLOCK_InitSystemPll(const clock_sys_pll_t *config);
682
683 /*! @brief System PLL Deinitialize.*/
CLOCK_DenitSystemPll(void)684 static inline void CLOCK_DenitSystemPll(void)
685 {
686 /* Power off PLL */
687 SYSCON->PDRUNCFG |= SYSCON_PDRUNCFG_SYSPLL_PD_MASK;
688 }
689
690 /* @} */
691
692 /*!
693 * @name Fractional clock operations
694 * @{
695 */
696
697 /*! @brief Set FRG0 output frequency.
698 * @param freq Target output frequency, freq < input and (input / freq) < 2 should be satisfy.
699 * @retval true - successfully, false - input argument is invalid.
700 *
701 */
702 bool CLOCK_SetFRG0ClkFreq(uint32_t freq);
703
704 /*! @brief Set FRG1 output frequency.
705 * @param freq Target output frequency, freq < input and (input / freq) < 2 should be satisfy.
706 * @retval true - successfully, false - input argument is invalid.
707 *
708 */
709 bool CLOCK_SetFRG1ClkFreq(uint32_t freq);
710
711 /* @} */
712
713 /*!
714 * @name External/internal oscillator clock operations
715 * @{
716 */
717
718 /*! @brief Init external CLK IN, select the CLKIN as the external clock source.
719 * @param clkInFreq external clock in frequency.
720 */
721 void CLOCK_InitExtClkin(uint32_t clkInFreq);
722
723 /*! @brief Init SYS OSC
724 * @param oscFreq oscillator frequency value.
725 */
726 void CLOCK_InitSysOsc(uint32_t oscFreq);
727
728 /*! @brief XTALIN init function
729 * system oscillator is bypassed, sys_osc_clk is fed driectly from the XTALIN.
730 * @param xtalInFreq XTALIN frequency value
731 * @return Frequency of PLL
732 */
733 void CLOCK_InitXtalin(uint32_t xtalInFreq);
734
735 /*! @brief Deinit SYS OSC
736 */
CLOCK_DeinitSysOsc(void)737 static inline void CLOCK_DeinitSysOsc(void)
738 {
739 /* Deinit system osc power */
740 SYSCON->PDRUNCFG |= SYSCON_PDRUNCFG_SYSOSC_PD_MASK;
741 }
742
743 /*! @brief Set FRO oscillator output frequency.
744 * Initialize the FRO clock to given frequency (36, 48 or 60 MHz).
745 * @param freq Please refer to clock_fro_osc_freq_t definition, frequency must be one of 36000, 48000 or 60000 KHz.
746 *
747 */
CLOCK_SetFroOscFreq(clock_fro_osc_freq_t freq)748 static inline void CLOCK_SetFroOscFreq(clock_fro_osc_freq_t freq)
749 {
750 (*((void (*)(uint32_t freq))(CLOCK_FRO_SETTING_API_ROM_ADDRESS)))(freq);
751 }
752
753 /* @} */
754
755 #if defined(__cplusplus)
756 }
757 #endif /* __cplusplus */
758
759 /*! @} */
760
761 #endif /* _FSL_CLOCK_H_ */
762
