1 /*
2 * Copyright 2017-2019, 2021 NXP
3 * All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7
8 #ifndef _FSL_CLOCK_H_
9 #define _FSL_CLOCK_H_
10
11 #include "fsl_common.h"
12
13 /*! @addtogroup clock */
14 /*! @{ */
15
16 /*! @file */
17
18 /*******************************************************************************
19 * Definitions
20 *****************************************************************************/
21
22 /*! @name Driver version */
23 /*@{*/
24 /*! @brief CLOCK driver version 2.3.3. */
25 #define FSL_CLOCK_DRIVER_VERSION (MAKE_VERSION(2, 3, 3))
26 /*@}*/
27
28 /* Definition for delay API in clock driver, users can redefine it to the real application. */
29 #ifndef SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY
30 #define SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY (15000000UL)
31 #endif
32
33 /*! @brief lower power oscilltor clock frequency.
34 *
35 * This variable is used to store the lower power oscillator frequency which is
36 * set by CLOCK_InitLPOsc, and it is returned by CLOCK_GetLPOscFreq.
37 */
38 extern volatile uint32_t g_LP_Osc_Freq;
39
40 /*! @brief external clock frequency.
41 *
42 * This variable is used to store the external clock frequency which is include
43 * external oscillator clock and external clk in clock frequency value, it is
44 * set by CLOCK_InitExtClkin when CLK IN is used as external clock or by CLOCK_InitSysOsc
45 * when external oscillator is used as external clock ,and it is returned by
46 * CLOCK_GetExtClkFreq.
47 */
48 extern volatile uint32_t g_Ext_Clk_Freq;
49
50 /*! @brief external clock frequency.
51 *
52 * This variable is used to store the FRO osc clock frequency.
53 */
54 extern volatile uint32_t g_Fro_Osc_Freq;
55
56 /*! @brief FRO clock setting API address in ROM. */
57 #define CLOCK_FRO_SETTING_API_ROM_ADDRESS (0x0F001CD3U)
58 /*! @brief FAIM base address*/
59 #define CLOCK_FAIM_BASE (0x50010000U)
60
61 /*! @brief Clock ip name array for ADC. */
62 #define ADC_CLOCKS \
63 { \
64 kCLOCK_Adc, \
65 }
66 /*! @brief Clock ip name array for ACMP. */
67 #define ACMP_CLOCKS \
68 { \
69 kCLOCK_Acmp, \
70 }
71 /*! @brief Clock ip name array for DAC. */
72 #define DAC_CLOCKS \
73 { \
74 kCLOCK_Dac, \
75 }
76 /*! @brief Clock ip name array for SWM. */
77 #define SWM_CLOCKS \
78 { \
79 kCLOCK_Swm, \
80 }
81 /*! @brief Clock ip name array for ROM. */
82 #define ROM_CLOCKS \
83 { \
84 kCLOCK_Rom, \
85 }
86 /*! @brief Clock ip name array for SRAM. */
87 #define SRAM_CLOCKS \
88 { \
89 kCLOCK_Ram0, \
90 }
91 /*! @brief Clock ip name array for IOCON. */
92 #define IOCON_CLOCKS \
93 { \
94 kCLOCK_Iocon, \
95 }
96 /*! @brief Clock ip name array for GPIO. */
97 #define GPIO_CLOCKS \
98 { \
99 kCLOCK_Gpio0, \
100 }
101 /*! @brief Clock ip name array for GPIO_INT. */
102 #define GPIO_INT_CLOCKS \
103 { \
104 kCLOCK_GpioInt, \
105 }
106 /*! @brief Clock ip name array for CRC. */
107 #define CRC_CLOCKS \
108 { \
109 kCLOCK_Crc, \
110 }
111 /*! @brief Clock ip name array for WWDT. */
112 #define WWDT_CLOCKS \
113 { \
114 kCLOCK_Wwdt, \
115 }
116 /*! @brief Clock ip name array for SCT0. */
117 #define SCT_CLOCKS \
118 { \
119 kCLOCK_Sct, \
120 }
121 /*! @brief Clock ip name array for I2C. */
122 #define I2C_CLOCKS \
123 { \
124 kCLOCK_I2c0, kCLOCK_I2c1, \
125 }
126 /*! @brief Clock ip name array for I2C. */
127 #define USART_CLOCKS \
128 { \
129 kCLOCK_Uart0, kCLOCK_Uart1, \
130 }
131 /*! @brief Clock ip name array for SPI. */
132 #define SPI_CLOCKS \
133 { \
134 kCLOCK_Spi0, \
135 }
136 /*! @brief Clock ip name array for CAPT. */
137 #define CAPT_CLOCKS \
138 { \
139 kCLOCK_Capt, \
140 }
141 /*! @brief Clock ip name array for CTIMER. */
142 #define CTIMER_CLOCKS \
143 { \
144 kCLOCK_Ctimer0, \
145 }
146 /*! @brief Clock ip name array for MRT. */
147 #define MRT_CLOCKS \
148 { \
149 kCLOCK_Mrt, \
150 }
151 /*! @brief Clock ip name array for WKT. */
152 #define WKT_CLOCKS \
153 { \
154 kCLOCK_Wkt, \
155 }
156 /*! @brief Clock ip name array for PLU. */
157 #define PLU_CLOCKS \
158 { \
159 kCLOCK_PLU, \
160 }
161
162 /*! @brief Internal used Clock definition only. */
163 #define CLK_GATE_DEFINE(reg, bit) ((((reg)&0xFFU) << 8U) | ((bit)&0xFFU))
164 #define CLK_GATE_GET_REG(x) (((uint32_t)(x) >> 8U) & 0xFFU)
165 #define CLK_GATE_GET_BITS_SHIFT(x) ((uint32_t)(x)&0xFFU)
166 /* clock mux register definition */
167 #define CLK_MUX_DEFINE(reg, mux) (((offsetof(SYSCON_Type, reg) & 0xFFU) << 8U) | ((mux)&0xFFU))
168 #define CLK_MUX_GET_REG(x) ((volatile uint32_t *)(((uint32_t)(SYSCON)) + (((uint32_t)(x) >> 8U) & 0xFFU)))
169 #define CLK_MUX_GET_MUX(x) ((uint32_t)(x)&0xFFU)
170 #define CLK_MAIN_CLK_MUX_DEFINE(preMux, mux) ((preMux) << 8U | (mux))
171 #define CLK_MAIN_CLK_MUX_GET_PRE_MUX(x) (((uint32_t)(x) >> 8U) & 0xFFU)
172 #define CLK_MAIN_CLK_MUX_GET_MUX(x) ((uint32_t)(x)&0xFFU)
173 /* clock divider register definition */
174 #define CLK_DIV_DEFINE(reg) (((uint32_t)offsetof(SYSCON_Type, reg)) & 0xFFFU)
175 #define CLK_DIV_GET_REG(x) *((volatile uint32_t *)(((uint32_t)(SYSCON)) + ((uint32_t)(x)&0xFFFU)))
176 /* watch dog oscillator definition */
177 //#define CLK_WDT_OSC_DEFINE(freq, regValue) ((freq & 0xFFFFFFU) | ((regValue & 0xFFU) << 24U))
178 //#define CLK_WDT_OSC_GET_FREQ(x) ((uint32_t)x & 0xFFFFFFU)
179 //#define CLK_WDT_OSC_GET_REG(x) ((x >> 24U) & 0xFFU)
180 /* Fractional clock register map */
181 /* Fractional clock register map */
182 #define CLK_FRG_DIV_REG_MAP(base) (*(base))
183 #define CLK_FRG_MUL_REG_MAP(base) (*((uint32_t *)((uint32_t)(base) + 4U)))
184 #define CLK_FRG_SEL_REG_MAP(base) (*((uint32_t *)((uint32_t)(base) + 8U)))
185 /* register offset */
186 #define SYS_AHB_CLK_CTRL0 (0U)
187 #define SYS_AHB_CLK_CTRL1 (4U)
188 /*! @brief Clock gate name used for CLOCK_EnableClock/CLOCK_DisableClock. */
189 typedef enum _clock_ip_name
190 {
191 kCLOCK_IpInvalid = 0U, /*!< Invalid Ip Name. */
192 kCLOCK_Sys = CLK_GATE_DEFINE(SYS_AHB_CLK_CTRL0, 0U), /*!< Clock gate name: Sys. */
193 kCLOCK_Rom = CLK_GATE_DEFINE(SYS_AHB_CLK_CTRL0, 1U), /*!< Clock gate name: Rom. */
194 kCLOCK_Ram0 = CLK_GATE_DEFINE(SYS_AHB_CLK_CTRL0, 2U), /*!< Clock gate name: Ram0. */
195 kCLOCK_Flash = CLK_GATE_DEFINE(SYS_AHB_CLK_CTRL0, 4U), /*!< Clock gate name: Flash. */
196 kCLOCK_I2c0 = CLK_GATE_DEFINE(SYS_AHB_CLK_CTRL0, 5U), /*!< Clock gate name: I2c0. */
197 kCLOCK_Gpio0 = CLK_GATE_DEFINE(SYS_AHB_CLK_CTRL0, 6U), /*!< Clock gate name: Gpio0. */
198 kCLOCK_Swm = CLK_GATE_DEFINE(SYS_AHB_CLK_CTRL0, 7U), /*!< Clock gate name: Swm. */
199 kCLOCK_Wkt = CLK_GATE_DEFINE(SYS_AHB_CLK_CTRL0, 9U), /*!< Clock gate name: Wkt. */
200 kCLOCK_Mrt = CLK_GATE_DEFINE(SYS_AHB_CLK_CTRL0, 10U), /*!< Clock gate name: Mrt. */
201 kCLOCK_Spi0 = CLK_GATE_DEFINE(SYS_AHB_CLK_CTRL0, 11U), /*!< Clock gate name: Spi0. */
202 kCLOCK_Crc = CLK_GATE_DEFINE(SYS_AHB_CLK_CTRL0, 13U), /*!< Clock gate name: Crc. */
203 kCLOCK_Uart0 = CLK_GATE_DEFINE(SYS_AHB_CLK_CTRL0, 14U), /*!< Clock gate name: Uart0. */
204 kCLOCK_Uart1 = CLK_GATE_DEFINE(SYS_AHB_CLK_CTRL0, 15U), /*!< Clock gate name: Uart1. */
205 kCLOCK_Wwdt = CLK_GATE_DEFINE(SYS_AHB_CLK_CTRL0, 17U), /*!< Clock gate name: Wwdt. */
206 kCLOCK_Iocon = CLK_GATE_DEFINE(SYS_AHB_CLK_CTRL0, 18U), /*!< Clock gate name: Iocon. */
207 kCLOCK_Acmp = CLK_GATE_DEFINE(SYS_AHB_CLK_CTRL0, 19U), /*!< Clock gate name: Acmp. */
208 kCLOCK_I2c1 = CLK_GATE_DEFINE(SYS_AHB_CLK_CTRL0, 21U), /*!< Clock gate name: I2c1. */
209 kCLOCK_Adc = CLK_GATE_DEFINE(SYS_AHB_CLK_CTRL0, 24U), /*!< Clock gate name: Adc. */
210 kCLOCK_Ctimer0 = CLK_GATE_DEFINE(SYS_AHB_CLK_CTRL0, 25U), /*!< Clock gate name: Ctimer0. */
211 kCLOCK_Dac = CLK_GATE_DEFINE(SYS_AHB_CLK_CTRL0, 27U), /*!< Clock gate name: Dac. */
212 kCLOCK_GpioInt = CLK_GATE_DEFINE(SYS_AHB_CLK_CTRL0, 28U), /*!< Clock gate name: GpioInt. */
213 kCLOCK_Capt = CLK_GATE_DEFINE(SYS_AHB_CLK_CTRL1, 0U), /*!< Clock gate name: Capt. */
214 kCLOCK_PLU = CLK_GATE_DEFINE(SYS_AHB_CLK_CTRL1, 5U), /*!< Clock gate name: PLU. */
215 } clock_ip_name_t;
216
217 /*! @brief Clock name used to get clock frequency. */
218 typedef enum _clock_name
219 {
220 kCLOCK_CoreSysClk, /*!< Cpu/AHB/AHB matrix/Memories,etc */
221 kCLOCK_MainClk, /*!< Main clock */
222 kCLOCK_Fro, /*!< FRO18/24/30 */
223 kCLOCK_FroDiv, /*!< FRO div clock */
224 kCLOCK_ExtClk, /*!< External Clock */
225 kCLOCK_LPOsc, /*!< Watchdog Oscillator */
226 kCLOCK_Frg0, /*!< fractional rate0 */
227 } clock_name_t;
228
229 /*! @brief Clock Mux Switches
230 *CLK_MUX_DEFINE(reg, mux)
231 *reg is used to define the mux register
232 *mux is used to define the mux value
233 *
234 */
235 typedef enum _clock_select
236 {
237 kCAPT_Clk_From_Fro = CLK_MUX_DEFINE(CAPTCLKSEL, 0U), /*!< Mux CAPT_Clk from Fro. */
238 kCAPT_Clk_From_MainClk = CLK_MUX_DEFINE(CAPTCLKSEL, 1U), /*!< Mux CAPT_Clk from MainClk. */
239 kCAPT_Clk_From_Fro_Div = CLK_MUX_DEFINE(CAPTCLKSEL, 3U), /*!< Mux CAPT_Clk from Fro_Div. */
240 kCAPT_Clk_From_LPOsc = CLK_MUX_DEFINE(CAPTCLKSEL, 4U), /*!< Mux CAPT_Clk from LPOsc. */
241
242 kADC_Clk_From_Fro = CLK_MUX_DEFINE(ADCCLKSEL, 0U), /*!< Mux ADC_Clk from Fro. */
243 kADC_Clk_From_Extclk = CLK_MUX_DEFINE(ADCCLKSEL, 1U), /*!< Mux ADC_Clk from Extclk. */
244
245 kUART0_Clk_From_Fro = CLK_MUX_DEFINE(UART0CLKSEL, 0U), /*!< Mux UART0_Clk from Fro. */
246 kUART0_Clk_From_MainClk = CLK_MUX_DEFINE(UART0CLKSEL, 1U), /*!< Mux UART0_Clk from MainClk. */
247 kUART0_Clk_From_Frg0Clk = CLK_MUX_DEFINE(UART0CLKSEL, 2U), /*!< Mux UART0_Clk from Frg0Clk. */
248 kUART0_Clk_From_Fro_Div = CLK_MUX_DEFINE(UART0CLKSEL, 4U), /*!< Mux UART0_Clk from Fro_Div. */
249
250 kUART1_Clk_From_Fro = CLK_MUX_DEFINE(UART1CLKSEL, 0U), /*!< Mux UART1_Clk from Fro. */
251 kUART1_Clk_From_MainClk = CLK_MUX_DEFINE(UART1CLKSEL, 1U), /*!< Mux UART1_Clk from MainClk. */
252 kUART1_Clk_From_Frg0Clk = CLK_MUX_DEFINE(UART1CLKSEL, 2U), /*!< Mux UART1_Clk from Frg0Clk. */
253 kUART1_Clk_From_Fro_Div = CLK_MUX_DEFINE(UART1CLKSEL, 4U), /*!< Mux UART1_Clk from Fro_Div. */
254
255 kI2C0_Clk_From_Fro = CLK_MUX_DEFINE(I2C0CLKSEL, 0U), /*!< Mux I2C0_Clk from Fro. */
256 kI2C0_Clk_From_MainClk = CLK_MUX_DEFINE(I2C0CLKSEL, 1U), /*!< Mux I2C0_Clk from MainClk. */
257 kI2C0_Clk_From_Frg0Clk = CLK_MUX_DEFINE(I2C0CLKSEL, 2U), /*!< Mux I2C0_Clk from Frg0Clk. */
258 kI2C0_Clk_From_Fro_Div = CLK_MUX_DEFINE(I2C0CLKSEL, 4U), /*!< Mux I2C0_Clk from Fro_Div. */
259
260 kI2C1_Clk_From_Fro = CLK_MUX_DEFINE(I2C1CLKSEL, 0U), /*!< Mux I2C1_Clk from Fro. */
261 kI2C1_Clk_From_MainClk = CLK_MUX_DEFINE(I2C1CLKSEL, 1U), /*!< Mux I2C1_Clk from MainClk. */
262 kI2C1_Clk_From_Frg0Clk = CLK_MUX_DEFINE(I2C1CLKSEL, 2U), /*!< Mux I2C1_Clk from Frg0Clk. */
263 kI2C1_Clk_From_Fro_Div = CLK_MUX_DEFINE(I2C1CLKSEL, 4U), /*!< Mux I2C1_Clk from Fro_Div. */
264
265 kSPI0_Clk_From_Fro = CLK_MUX_DEFINE(SPI0CLKSEL, 0U), /*!< Mux SPI0_Clk from Fro. */
266 kSPI0_Clk_From_MainClk = CLK_MUX_DEFINE(SPI0CLKSEL, 1U), /*!< Mux SPI0_Clk from MainClk. */
267 kSPI0_Clk_From_Frg0Clk = CLK_MUX_DEFINE(SPI0CLKSEL, 2U), /*!< Mux SPI0_Clk from Frg0Clk. */
268 kSPI0_Clk_From_Fro_Div = CLK_MUX_DEFINE(SPI0CLKSEL, 4U), /*!< Mux SPI0_Clk from Fro_Div. */
269
270 kFRG0_Clk_From_Fro = CLK_MUX_DEFINE(FRG[0].FRGCLKSEL, 0U), /*!< Mux FRG0_Clk from Fro. */
271 kFRG0_Clk_From_MainClk = CLK_MUX_DEFINE(FRG[0].FRGCLKSEL, 1U), /*!< Mux FRG0_Clk from MainClk. */
272
273 kCLKOUT_From_Fro = CLK_MUX_DEFINE(CLKOUTSEL, 0U), /*!< Mux CLKOUT from Fro. */
274 kCLKOUT_From_MainClk = CLK_MUX_DEFINE(CLKOUTSEL, 1U), /*!< Mux CLKOUT from MainClk. */
275 kCLKOUT_From_ExtClk = CLK_MUX_DEFINE(CLKOUTSEL, 3U), /*!< Mux CLKOUT from ExtClk. */
276 kCLKOUT_From_Lposc = CLK_MUX_DEFINE(CLKOUTSEL, 4U), /*!< Mux CLKOUT from Lposc. */
277 } clock_select_t;
278
279 /*! @brief Clock divider
280 */
281 typedef enum _clock_divider
282 {
283 kCLOCK_DivAhbClk = CLK_DIV_DEFINE(SYSAHBCLKDIV), /*!< Ahb Clock Divider. */
284 kCLOCK_DivAdcClk = CLK_DIV_DEFINE(ADCCLKDIV), /*!< Adc Clock Divider. */
285 kCLOCK_DivClkOut = CLK_DIV_DEFINE(CLKOUTDIV), /*!< Clk Out Divider. */
286 } clock_divider_t;
287
288 //
289 // typedef enum _clock_wdt_analog_freq
290 //{
291 // kCLOCK_WdtAnaFreq0HZ = CLK_WDT_OSC_DEFINE(0U, 0U),
292 // kCLOCK_WdtAnaFreq600KHZ = CLK_WDT_OSC_DEFINE(600000U, 1U),
293 // kCLOCK_WdtAnaFreq1050KHZ = CLK_WDT_OSC_DEFINE(1050000U, 2u),
294 // kCLOCK_WdtAnaFreq1400KHZ = CLK_WDT_OSC_DEFINE(1400000U, 3U),
295 // kCLOCK_WdtAnaFreq1750KHZ = CLK_WDT_OSC_DEFINE(1750000U, 4U),
296 // kCLOCK_WdtAnaFreq2100KHZ = CLK_WDT_OSC_DEFINE(2100000U, 5U),
297 // kCLOCK_WdtAnaFreq2400KHZ = CLK_WDT_OSC_DEFINE(2400000U, 6U),
298 // kCLOCK_WdtAnaFreq2700KHZ = CLK_WDT_OSC_DEFINE(2700000U, 7U),
299 // kCLOCK_WdtAnaFreq3000KHZ = CLK_WDT_OSC_DEFINE(3000000U, 8U),
300 // kCLOCK_WdtAnaFreq3250KHZ = CLK_WDT_OSC_DEFINE(3250000U, 9U),
301 // kCLOCK_WdtAnaFreq3500KHZ = CLK_WDT_OSC_DEFINE(3500000U, 10U),
302 // kCLOCK_WdtAnaFreq3750KHZ = CLK_WDT_OSC_DEFINE(3750000U, 11U),
303 // kCLOCK_WdtAnaFreq4000KHZ = CLK_WDT_OSC_DEFINE(4000000U, 12U),
304 // kCLOCK_WdtAnaFreq4200KHZ = CLK_WDT_OSC_DEFINE(4200000U, 13U),
305 // kCLOCK_WdtAnaFreq4400KHZ = CLK_WDT_OSC_DEFINE(4400000U, 14U),
306 // kCLOCK_WdtAnaFreq4600KHZ = CLK_WDT_OSC_DEFINE(4600000U, 15U),
307 //} clock_wdt_analog_freq_t;
308
309 /*! @brief fro output frequency source definition */
310 // typedef enum _clock_fro_src
311 //{
312 // kCLOCK_FroSrcLpwrBootValue = 0U,
313 // kCLOCK_FroSrcFroOsc = 1U << SYSCON_FROOSCCTRL_DIRECT_SHIFT,
314 //} clock_fro_src_t;
315
316 /*! @brief fro oscillator output frequency value definition */
317 typedef enum _clock_fro_osc_freq
318 {
319 kCLOCK_FroOscOut18M = 18000U, /*!< FRO oscillator output 18M */
320 kCLOCK_FroOscOut24M = 24000U, /*!< FRO oscillator output 24M */
321 kCLOCK_FroOscOut30M = 30000U, /*!< FRO oscillator output 30M */
322 } clock_fro_osc_freq_t;
323
324 /*! @brief PLL clock definition.*/
325 // typedef enum _clock_sys_pll_src
326 //{
327 // kCLOCK_SysPllSrcFRO = 0U,
328 // kCLOCK_SysPllSrcExtClk = 1U,
329 // kCLOCK_SysPllSrcWdtOsc = 2U,
330 // kCLOCK_SysPllSrcFroDiv = 3U,
331 //} clock_sys_pll_src;
332
333 /*!< Main clock source definition */
334 typedef enum _clock_main_clk_src
335 {
336 kCLOCK_MainClkSrcFro = CLK_MAIN_CLK_MUX_DEFINE(0U, 0U), /*!< main clock source from FRO */
337 kCLOCK_MainClkSrcExtClk = CLK_MAIN_CLK_MUX_DEFINE(1U, 0U), /*!< main clock source from Ext clock */
338 kCLOCK_MainClkSrcLPOsc = CLK_MAIN_CLK_MUX_DEFINE(2U, 0U), /*!< main clock source from lower power oscillator */
339 kCLOCK_MainClkSrcFroDiv = CLK_MAIN_CLK_MUX_DEFINE(3U, 0U), /*!< main clock source from FRO Div */
340 // kCLOCK_MainClkSrcSysPll = CLK_MAIN_CLK_MUX_DEFINE(0U, 1U),
341 } clock_main_clk_src_t;
342
343 /*! @brief PLL configuration structure */
344 // typedef struct _clock_sys_pll
345 //{
346 // uint32_t targetFreq;
347 // clock_sys_pll_src src;
348 //} clock_sys_pll_t;
349
350 /*******************************************************************************
351 * API
352 ******************************************************************************/
353
354 #if defined(__cplusplus)
355 extern "C" {
356 #endif /* __cplusplus */
357
358 /*!
359 * @name Clock gate, mux, and divider.
360 * @{
361 */
362
363 /*
364 *! @brief enable ip clock.
365 *
366 * @param clk clock ip definition.
367 */
CLOCK_EnableClock(clock_ip_name_t clk)368 static inline void CLOCK_EnableClock(clock_ip_name_t clk)
369 {
370 *(volatile uint32_t *)(((uint32_t)(&SYSCON->SYSAHBCLKCTRL0)) + CLK_GATE_GET_REG(clk)) |=
371 1UL << CLK_GATE_GET_BITS_SHIFT(clk);
372 }
373
374 /*
375 *!@brief disable ip clock.
376 *
377 * @param clk clock ip definition.
378 */
CLOCK_DisableClock(clock_ip_name_t clk)379 static inline void CLOCK_DisableClock(clock_ip_name_t clk)
380 {
381 *(volatile uint32_t *)(((uint32_t)(&SYSCON->SYSAHBCLKCTRL0)) + CLK_GATE_GET_REG(clk)) &=
382 ~(1UL << CLK_GATE_GET_BITS_SHIFT(clk));
383 }
384
385 /*
386 *! @brief Configure the clock selection muxes.
387 * @param mux : Clock to be configured.
388 * @return Nothing
389 */
CLOCK_Select(clock_select_t sel)390 static inline void CLOCK_Select(clock_select_t sel)
391 {
392 *(CLK_MUX_GET_REG(sel)) = CLK_MUX_GET_MUX(sel);
393 }
394
395 /*
396 *! @brief Setup peripheral clock dividers.
397 * @param name : Clock divider name
398 * @param value: Value to be divided
399 * @return Nothing
400 */
CLOCK_SetClkDivider(clock_divider_t name,uint32_t value)401 static inline void CLOCK_SetClkDivider(clock_divider_t name, uint32_t value)
402 {
403 CLK_DIV_GET_REG(name) = value & 0xFFU;
404 }
405
406 /*
407 *! @brief Get peripheral clock dividers.
408 * @param name : Clock divider name
409 * @return clock divider value
410 */
CLOCK_GetClkDivider(clock_divider_t name)411 static inline uint32_t CLOCK_GetClkDivider(clock_divider_t name)
412 {
413 return CLK_DIV_GET_REG(name) & 0xFFU;
414 }
415
416 /*
417 *! @brief Setup Core clock dividers.
418 * Be careful about the core divider value, due to core/system frequency should be lower than 30MHZ.
419 * @param value: Value to be divided
420 * @return Nothing
421 */
CLOCK_SetCoreSysClkDiv(uint32_t value)422 static inline void CLOCK_SetCoreSysClkDiv(uint32_t value)
423 {
424 assert(value != 0U);
425
426 SYSCON->SYSAHBCLKDIV = (SYSCON->SYSAHBCLKDIV & (~SYSCON_SYSAHBCLKDIV_DIV_MASK)) | SYSCON_SYSAHBCLKDIV_DIV(value);
427 }
428
429 /*! @brief Set main clock reference source.
430 * @param src Reference clock_main_clk_src_t to set the main clock source.
431 */
432 void CLOCK_SetMainClkSrc(clock_main_clk_src_t src);
433
434 /*
435 *! @brief Set Fractional generator multiplier value.
436 * @param base: Fractional generator register address
437 * @param mul : FRG multiplier value.
438 * @return Nothing
439 */
CLOCK_SetFRGClkMul(uint32_t * base,uint32_t mul)440 static inline void CLOCK_SetFRGClkMul(uint32_t *base, uint32_t mul)
441 {
442 CLK_FRG_DIV_REG_MAP(base) = SYSCON_FRG_FRGDIV_DIV_MASK;
443 CLK_FRG_MUL_REG_MAP(base) = SYSCON_FRG_FRGMULT_MULT(mul);
444 }
445
446 /*! @brief Set FRO clock source
447 * @param src, please reference _clock_fro_src definition.
448 *
449 */
450 // void CLOCK_SetFroOutClkSrc(clock_fro_src_t src);
451
452 /* @} */
453
454 /*!
455 * @name Get frequency
456 * @{
457 */
458
459 /*! @brief Return Frequency of FRG0 Clock.
460 * @return Frequency of FRG0 Clock.
461 */
462 uint32_t CLOCK_GetFRG0ClkFreq(void);
463
464 /*! @brief Return Frequency of Main Clock.
465 * @return Frequency of Main Clock.
466 */
467 uint32_t CLOCK_GetMainClkFreq(void);
468
469 /*! @brief Return Frequency of FRO.
470 * @return Frequency of FRO.
471 */
472 uint32_t CLOCK_GetFroFreq(void);
473
474 /*! @brief Return Frequency of core.
475 * @return Frequency of core.
476 */
CLOCK_GetCoreSysClkFreq(void)477 static inline uint32_t CLOCK_GetCoreSysClkFreq(void)
478 {
479 return CLOCK_GetMainClkFreq() / (SYSCON->SYSAHBCLKDIV & 0xffU);
480 }
481
482 /*! @brief Return Frequency of ClockOut
483 * @return Frequency of ClockOut
484 */
485 uint32_t CLOCK_GetClockOutClkFreq(void);
486
487 /*! @brief Get UART0 frequency
488 * @retval UART0 frequency value.
489 */
490 uint32_t CLOCK_GetUart0ClkFreq(void);
491
492 /*! @brief Get UART1 frequency
493 * @retval UART1 frequency value.
494 */
495 uint32_t CLOCK_GetUart1ClkFreq(void);
496
497 /*! @brief Return Frequency of selected clock
498 * @return Frequency of selected clock
499 */
500 uint32_t CLOCK_GetFreq(clock_name_t clockName);
501
502 /*! @brief Get watch dog OSC frequency
503 * @retval watch dog OSC frequency value.
504 */
CLOCK_GetLPOscFreq(void)505 static inline uint32_t CLOCK_GetLPOscFreq(void)
506 {
507 return g_LP_Osc_Freq;
508 }
509
510 /*! @brief Get external clock frequency
511 * @retval external clock frequency value.
512 */
CLOCK_GetExtClkFreq(void)513 static inline uint32_t CLOCK_GetExtClkFreq(void)
514 {
515 return g_Ext_Clk_Freq;
516 }
517 /* @} */
518
519 /*!
520 * @name PLL operations
521 * @{
522 */
523
524 /*! @brief System PLL initialize.
525 * @param config System PLL configurations.
526 */
527 // void CLOCK_InitSystemPll(const clock_sys_pll_t *config);
528
529 /* @} */
530
531 /*!
532 * @name Fractional clock operations
533 * @{
534 */
535
536 /*! @brief Set FRG0 output frequency.
537 * @param freq target output frequency,freq < input and (input / freq) < 2 should be satisfy.
538 * @retval true - successfully, false - input argument is invalid.
539 *
540 */
541 bool CLOCK_SetFRG0ClkFreq(uint32_t freq);
542
543 /* @} */
544
545 /*!
546 * @name External/internal oscillator clock operations
547 * @{
548 */
549
550 /*! @brief Init external CLK IN, select the CLKIN as the external clock source.
551 * @param clkInFreq external clock in frequency.
552 */
553 void CLOCK_InitExtClkin(uint32_t clkInFreq);
554
555 /*! @brief Deinit watch dog OSC */
CLOCK_DeinitLpOsc(void)556 static inline void CLOCK_DeinitLpOsc(void)
557 {
558 SYSCON->PDRUNCFG |= SYSCON_PDRUNCFG_LPOSC_PD_MASK;
559 }
560
561 // void CLOCK_InitSysOsc(uint32_t oscFreq);
562
563 // static inline void CLOCK_DeinitSysOsc(void)
564 //{
565 //
566 // SYSCON->PDRUNCFG |= SYSCON_PDRUNCFG_SYSOSC_PD_MASK;
567 //}
568
569 // void CLOCK_InitWdtOsc(clock_wdt_analog_freq_t wdtOscFreq, uint32_t wdtOscDiv);
570
571 // static inline void CLOCK_DeinitWdtOsc(void)
572 //{
573 // SYSCON->PDRUNCFG |= SYSCON_PDRUNCFG_LPOSC_PD_MASK;
574 //}
575
576 /*! @brief Set FRO oscillator output frequency.
577 * Initialize the FRO clock to given frequency (18, 24 or 30 MHz).
578 * @param freq Please refer to definition of clock_fro_osc_freq_t, frequency must be one of 18000, 24000 or 30000 KHz.
579 *
580 */
581 void CLOCK_SetFroOscFreq(clock_fro_osc_freq_t freq);
582
583 /* @} */
584
585 #if defined(__cplusplus)
586 }
587 #endif /* __cplusplus */
588
589 /*! @} */
590
591 #endif /* _FSL_CLOCK_H_ */
592
