1 /*
2 * Copyright 2017-2021, 2023 NXP
3 * All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7
8 #ifndef _FSL_CLOCK_H_
9 #define _FSL_CLOCK_H_
10
11 #include "fsl_common.h"
12
13 /*! @addtogroup clock */
14 /*! @{ */
15
16 /*! @file */
17
18 /*******************************************************************************
19 * Definitions
20 *****************************************************************************/
21
22 /*! @name Driver version */
23 /*@{*/
24 /*! @brief CLOCK driver version 2.3.4. */
25 #define FSL_CLOCK_DRIVER_VERSION (MAKE_VERSION(2, 3, 4))
26 /*@}*/
27
28 /* Definition for delay API in clock driver, users can redefine it to the real application. */
29 #ifndef SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY
30 #define SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY (15000000UL)
31 #endif
32
33 /*! @brief watchdog oscilltor clock frequency.
34 *
35 * This variable is used to store the watchdog oscillator frequency which is
36 * set by CLOCK_InitWdtOsc, and it is returned by CLOCK_GetWdtOscFreq.
37 */
38 extern volatile uint32_t g_Wdt_Osc_Freq;
39
40 /*! @brief external clock frequency.
41 *
42 * This variable is used to store the external clock frequency which is include
43 * external oscillator clock and external clk in clock frequency value, it is
44 * set by CLOCK_InitExtClkin when CLK IN is used as external clock or by CLOCK_InitSysOsc
45 * when external oscillator is used as external clock ,and it is returned by
46 * CLOCK_GetExtClkFreq.
47 */
48 extern volatile uint32_t g_Ext_Clk_Freq;
49
50 /*! @brief FRO clock setting API address in ROM. */
51 #define CLOCK_FRO_SETTING_API_ROM_ADDRESS (0x0F001CD3U)
52 /*! @brief FAIM base address*/
53 #define CLOCK_FAIM_BASE (0x50010000U)
54
55 /*! @brief Clock ip name array for ADC. */
56 #define ADC_CLOCKS \
57 { \
58 kCLOCK_Adc, \
59 }
60 /*! @brief Clock ip name array for ACMP. */
61 #define ACMP_CLOCKS \
62 { \
63 kCLOCK_Acmp, \
64 }
65 /*! @brief Clock ip name array for DAC. */
66 #define DAC_CLOCKS \
67 { \
68 kCLOCK_Dac0, kCLOCK_Dac1, \
69 }
70 /*! @brief Clock ip name array for SWM. */
71 #define SWM_CLOCKS \
72 { \
73 kCLOCK_Swm, \
74 }
75 /*! @brief Clock ip name array for ROM. */
76 #define ROM_CLOCKS \
77 { \
78 kCLOCK_Rom, \
79 }
80 /*! @brief Clock ip name array for SRAM. */
81 #define SRAM_CLOCKS \
82 { \
83 kCLOCK_Ram0_1, \
84 }
85 /*! @brief Clock ip name array for IOCON. */
86 #define IOCON_CLOCKS \
87 { \
88 kCLOCK_Iocon, \
89 }
90 /*! @brief Clock ip name array for GPIO. */
91 #define GPIO_CLOCKS \
92 { \
93 kCLOCK_Gpio0, \
94 }
95 /*! @brief Clock ip name array for GPIO_INT. */
96 #define GPIO_INT_CLOCKS \
97 { \
98 kCLOCK_GpioInt, \
99 }
100 /*! @brief Clock ip name array for DMA. */
101 #define DMA_CLOCKS \
102 { \
103 kCLOCK_Dma, \
104 }
105 /*! @brief Clock ip name array for CRC. */
106 #define CRC_CLOCKS \
107 { \
108 kCLOCK_Crc, \
109 }
110 /*! @brief Clock ip name array for WWDT. */
111 #define WWDT_CLOCKS \
112 { \
113 kCLOCK_Wwdt, \
114 }
115 /*! @brief Clock ip name array for SCT0. */
116 #define SCT_CLOCKS \
117 { \
118 kCLOCK_Sct, \
119 }
120 /*! @brief Clock ip name array for I2C. */
121 #define I2C_CLOCKS \
122 { \
123 kCLOCK_I2c0, \
124 }
125 /*! @brief Clock ip name array for I2C. */
126 #define USART_CLOCKS \
127 { \
128 kCLOCK_Uart0, kCLOCK_Uart1, \
129 }
130 /*! @brief Clock ip name array for SPI. */
131 #define SPI_CLOCKS \
132 { \
133 kCLOCK_Spi0, \
134 }
135 /*! @brief Clock ip name array for CAPT. */
136 #define CAPT_CLOCKS \
137 { \
138 kCLOCK_Capt, \
139 }
140 /*! @brief Clock ip name array for CTIMER. */
141 #define CTIMER_CLOCKS \
142 { \
143 kCLOCK_Ctimer0, \
144 }
145 /*! @brief Clock ip name array for MTB. */
146 #define MTB_CLOCKS \
147 { \
148 kCLOCK_Mtb, \
149 }
150 /*! @brief Clock ip name array for MRT. */
151 #define MRT_CLOCKS \
152 { \
153 kCLOCK_Mrt, \
154 }
155 /*! @brief Clock ip name array for WKT. */
156 #define WKT_CLOCKS \
157 { \
158 kCLOCK_Wkt, \
159 }
160
161 /*! @brief Internal used Clock definition only. */
162 #define CLK_GATE_DEFINE(reg, bit) ((((reg)&0xFFU) << 8U) | ((bit)&0xFFU))
163 #define CLK_GATE_GET_REG(x) (((x) >> 8U) & 0xFFU)
164 #define CLK_GATE_GET_BITS_SHIFT(x) ((uint32_t)(x)&0xFFU)
165 /* clock mux register definition */
166 #define CLK_MUX_DEFINE(reg, mux) (((offsetof(SYSCON_Type, reg) & 0xFFU) << 8U) | ((mux)&0xFFU))
167 #define CLK_MUX_GET_REG(x) ((volatile uint32_t *)(((uint32_t)(SYSCON)) + (((uint32_t)(x) >> 8U) & 0xFFU)))
168 #define CLK_MUX_GET_MUX(x) (((uint32_t)x) & 0xFFU)
169 #define CLK_MAIN_CLK_MUX_DEFINE(preMux, mux) ((preMux) << 8U | (mux))
170 #define CLK_MAIN_CLK_MUX_GET_PRE_MUX(x) ((((uint32_t)(x)) >> 8U) & 0xFFU)
171 #define CLK_MAIN_CLK_MUX_GET_MUX(x) (((uint32_t)(x)) & 0xFFU)
172 /* clock divider register definition */
173 #define CLK_DIV_DEFINE(reg) (((uint32_t)offsetof(SYSCON_Type, reg)) & 0xFFFU)
174
175 #define CLK_DIV_GET_REG(x) *((volatile uint32_t *)(((uint32_t)(SYSCON)) + (((uint32_t)(x)) & 0xFFFU)))
176 /* watch dog oscillator definition */
177 #define CLK_WDT_OSC_DEFINE(freq, regValue) (((freq)&0xFFFFFFU) | (((regValue)&0xFFU) << 24U))
178 #define CLK_WDT_OSC_GET_FREQ(x) ((x)&0xFFFFFFU)
179 #define CLK_WDT_OSC_GET_REG(x) (((x) >> 24U) & 0xFFU)
180 /* Fractional clock register map */
181 #define CLK_FRG_DIV_REG_MAP(base) (*(base))
182 #define CLK_FRG_MUL_REG_MAP(base) (*((uint32_t *)((uint32_t)(base) + 4U)))
183 #define CLK_FRG_SEL_REG_MAP(base) (*((uint32_t *)((uint32_t)(base) + 8U)))
184 /* register offset */
185 #define SYS_AHB_CLK_CTRL0 (0U)
186 /*! @brief Clock gate name used for CLOCK_EnableClock/CLOCK_DisableClock. */
187 typedef enum _clock_ip_name
188 {
189 kCLOCK_IpInvalid = 0U, /*!< Invalid Ip Name. */
190 kCLOCK_Rom = CLK_GATE_DEFINE(SYS_AHB_CLK_CTRL0, 1U), /*!< Clock gate name: Rom. */
191
192 kCLOCK_Ram0 = CLK_GATE_DEFINE(SYS_AHB_CLK_CTRL0, 2U), /*!< Clock gate name: Ram0. */
193
194 kCLOCK_Flash = CLK_GATE_DEFINE(SYS_AHB_CLK_CTRL0, 4U), /*!< Clock gate name: Flash. */
195
196 kCLOCK_I2c0 = CLK_GATE_DEFINE(SYS_AHB_CLK_CTRL0, 5U), /*!< Clock gate name: I2c0. */
197
198 kCLOCK_Gpio0 = CLK_GATE_DEFINE(SYS_AHB_CLK_CTRL0, 6U), /*!< Clock gate name: Gpio0. */
199
200 kCLOCK_Swm = CLK_GATE_DEFINE(SYS_AHB_CLK_CTRL0, 7U), /*!< Clock gate name: Swm. */
201
202 kCLOCK_Wkt = CLK_GATE_DEFINE(SYS_AHB_CLK_CTRL0, 9U), /*!< Clock gate name: Wkt. */
203
204 kCLOCK_Mrt = CLK_GATE_DEFINE(SYS_AHB_CLK_CTRL0, 10U), /*!< Clock gate name: Mrt. */
205
206 kCLOCK_Spi0 = CLK_GATE_DEFINE(SYS_AHB_CLK_CTRL0, 11U), /*!< Clock gate name: Spi0. */
207
208 kCLOCK_Crc = CLK_GATE_DEFINE(SYS_AHB_CLK_CTRL0, 13U), /*!< Clock gate name: Crc. */
209
210 kCLOCK_Uart0 = CLK_GATE_DEFINE(SYS_AHB_CLK_CTRL0, 14U), /*!< Clock gate name: Uart0. */
211
212 kCLOCK_Uart1 = CLK_GATE_DEFINE(SYS_AHB_CLK_CTRL0, 15U), /*!< Clock gate name: Uart1. */
213
214 kCLOCK_Wwdt = CLK_GATE_DEFINE(SYS_AHB_CLK_CTRL0, 17U), /*!< Clock gate name: Wwdt. */
215
216 kCLOCK_Iocon = CLK_GATE_DEFINE(SYS_AHB_CLK_CTRL0, 18U), /*!< Clock gate name: Iocon. */
217
218 kCLOCK_Acmp = CLK_GATE_DEFINE(SYS_AHB_CLK_CTRL0, 19U), /*!< Clock gate name: Acmp. */
219
220 kCLOCK_Adc = CLK_GATE_DEFINE(SYS_AHB_CLK_CTRL0, 24U), /*!< Clock gate name: Adc. */
221
222 kCLOCK_Ctimer0 = CLK_GATE_DEFINE(SYS_AHB_CLK_CTRL0, 25U), /*!< Clock gate name: Ctimer0. */
223
224 kCLOCK_GpioInt = CLK_GATE_DEFINE(SYS_AHB_CLK_CTRL0, 28U), /*!< Clock gate name: GpioInt. */
225
226 } clock_ip_name_t;
227
228 /*! @brief Clock name used to get clock frequency. */
229 typedef enum _clock_name
230 {
231 kCLOCK_CoreSysClk, /*!< Cpu/AHB/AHB matrix/Memories,etc */
232 kCLOCK_MainClk, /*!< Main clock */
233
234 kCLOCK_Fro, /*!< FRO18/24/30 */
235 kCLOCK_FroDiv, /*!< FRO div clock */
236 kCLOCK_ExtClk, /*!< External Clock */
237 kCLOCK_LPOsc, /*!< Low power Oscillator */
238 kCLOCK_Frg, /*!< fractional rate0 */
239 } clock_name_t;
240
241 /*! @brief Clock Mux Switches
242 *CLK_MUX_DEFINE(reg, mux)
243 *reg is used to define the mux register
244 *mux is used to define the mux value
245 *
246 */
247 typedef enum _clock_select
248 {
249
250 kADC_Clk_From_Fro = CLK_MUX_DEFINE(ADCCLKSEL, 0U), /*!< Mux ADC_Clk from Fro. */
251
252 kADC_Clk_From_ClkIn = CLK_MUX_DEFINE(ADCCLKSEL, 1U), /*!< Mux ADC_Clk from ClkIn. */
253
254 kUART0_Clk_From_Fro = CLK_MUX_DEFINE(UART0CLKSEL, 0U), /*!< Mux UART0_Clk from Fro. */
255
256 kUART0_Clk_From_MainClk = CLK_MUX_DEFINE(UART0CLKSEL, 1U), /*!< Mux UART0_Clk from MainClk. */
257
258 kUART0_Clk_From_Frg0Clk = CLK_MUX_DEFINE(UART0CLKSEL, 2U), /*!< Mux UART0_Clk from Frg0Clk. */
259
260 kUART0_Clk_From_Fro_Div = CLK_MUX_DEFINE(UART0CLKSEL, 4U), /*!< Mux UART0_Clk from Fro_Div. */
261
262 kUART1_Clk_From_Fro = CLK_MUX_DEFINE(UART1CLKSEL, 0U), /*!< Mux UART1_Clk from Fro. */
263
264 kUART1_Clk_From_MainClk = CLK_MUX_DEFINE(UART1CLKSEL, 1U), /*!< Mux UART1_Clk from MainClk. */
265
266 kUART1_Clk_From_Frg0Clk = CLK_MUX_DEFINE(UART1CLKSEL, 2U), /*!< Mux UART1_Clk from Frg0Clk. */
267
268 kUART1_Clk_From_Fro_Div = CLK_MUX_DEFINE(UART1CLKSEL, 4U), /*!< Mux UART1_Clk from Fro_Div. */
269
270 kI2C_Clk_From_Fro = CLK_MUX_DEFINE(I2C0CLKSEL, 0U), /*!< Mux I2C_Clk from Fro. */
271
272 kI2C_Clk_From_MainClk = CLK_MUX_DEFINE(I2C0CLKSEL, 1U), /*!< Mux I2C_Clk from MainClk. */
273
274 kI2C_Clk_From_Frg0Clk = CLK_MUX_DEFINE(I2C0CLKSEL, 2U), /*!< Mux I2C_Clk from Frg0Clk. */
275
276 kI2C_Clk_From_Fro_Div = CLK_MUX_DEFINE(I2C0CLKSEL, 4U), /*!< Mux I2C_Clk from Fro_Div. */
277
278 kSPI_Clk_From_Fro = CLK_MUX_DEFINE(SPI0CLKSEL, 0U), /*!< Mux SPI_Clk from Fro. */
279
280 kSPI_Clk_From_MainClk = CLK_MUX_DEFINE(SPI0CLKSEL, 1U), /*!< Mux SPI_Clk from MainClk. */
281
282 kSPI_Clk_From_Frg0Clk = CLK_MUX_DEFINE(SPI0CLKSEL, 2U), /*!< Mux SPI_Clk from Frg0Clk. */
283
284 kSPI_Clk_From_Fro_Div = CLK_MUX_DEFINE(SPI0CLKSEL, 4U), /*!< Mux SPI_Clk from Fro_Div. */
285
286 kFRG0_Clk_From_Fro = CLK_MUX_DEFINE(FRG[0].FRGCLKSEL, 0U), /*!< Mux FRG0_Clk from Fro. */
287
288 kFRG0_Clk_From_MainClk = CLK_MUX_DEFINE(FRG[0].FRGCLKSEL, 1U), /*!< Mux FRG0_Clk from MainClk. */
289
290 kCLKOUT_From_Fro = CLK_MUX_DEFINE(CLKOUTSEL, 0U), /*!< Mux CLKOUT from Fro. */
291
292 kCLKOUT_From_MainClk = CLK_MUX_DEFINE(CLKOUTSEL, 1U), /*!< Mux CLKOUT from MainClk. */
293
294 kCLKOUT_From_ExtClk = CLK_MUX_DEFINE(CLKOUTSEL, 3U), /*!< Mux CLKOUT from ExtClk. */
295
296 kCLKOUT_From_WdtOsc = CLK_MUX_DEFINE(CLKOUTSEL, 4U) /*!< Mux clock out from WdtOsc. */
297 } clock_select_t;
298
299 /*! @brief Clock divider
300 */
301 typedef enum _clock_divider
302 {
303 kCLOCK_DivAdcClk = CLK_DIV_DEFINE(ADCCLKDIV), /*!< Adc Clock Divider. */
304
305 kCLOCK_DivClkOut = CLK_DIV_DEFINE(CLKOUTDIV) /*!< Clock out divider. */
306 } clock_divider_t;
307
308 /*! @brief fro output frequency source definition */
309 typedef enum _clock_fro_src
310 {
311 kCLOCK_FroSrcLpwrBootValue = 0U, /*!< fro source from the fro oscillator divided by low power boot value */
312 // kCLOCK_FroSrcFroOsc = 1U << SYSCON_FROOSCCTRL_DIRECT_SHIFT,
313 } clock_fro_src_t;
314
315 /*! @brief fro oscillator output frequency value definition */
316 typedef enum _clock_fro_osc_freq
317 {
318 kCLOCK_FroOscOut18M = 18000U, /*!< FRO oscillator output 18M */
319 kCLOCK_FroOscOut24M = 24000U, /*!< FRO oscillator output 24M */
320 kCLOCK_FroOscOut30M = 30000U, /*!< FRO oscillator output 30M */
321 } clock_fro_osc_freq_t;
322
323 /*! @brief Main clock source definition */
324 typedef enum _clock_main_clk_src
325 {
326 kCLOCK_MainClkSrcFro = CLK_MAIN_CLK_MUX_DEFINE(0U, 0U), /*!< main clock source from FRO */
327 kCLOCK_MainClkSrcExtClk = CLK_MAIN_CLK_MUX_DEFINE(1U, 0U), /*!< main clock source from Ext clock */
328 kCLOCK_MainClkSrcLPOsc = CLK_MAIN_CLK_MUX_DEFINE(2U, 0U), /*!< main clock source from watchdog oscillator */
329 kCLOCK_MainClkSrcFroDiv = CLK_MAIN_CLK_MUX_DEFINE(3U, 0U), /*!< main clock source from FRO Div */
330 } clock_main_clk_src_t;
331
332 /*******************************************************************************
333 * API
334 ******************************************************************************/
335
336 #if defined(__cplusplus)
337 extern "C" {
338 #endif /* __cplusplus */
339
340 /*!
341 * @name Clock gate, mux, and divider.
342 * @{
343 */
344
345 /*
346 *! @brief enable ip clock.
347 *
348 * @param clk clock ip definition.
349 */
CLOCK_EnableClock(clock_ip_name_t clk)350 static inline void CLOCK_EnableClock(clock_ip_name_t clk)
351 {
352 SYSCON->SYSAHBCLKCTRL0 |= 1UL << CLK_GATE_GET_BITS_SHIFT(clk);
353 }
354
355 /*
356 *!@brief disable ip clock.
357 *
358 * @param clk clock ip definition.
359 */
CLOCK_DisableClock(clock_ip_name_t clk)360 static inline void CLOCK_DisableClock(clock_ip_name_t clk)
361 {
362 SYSCON->SYSAHBCLKCTRL0 &= ~(1UL << CLK_GATE_GET_BITS_SHIFT(clk));
363 }
364
365 /*
366 *! @brief Configure the clock selection muxes.
367 * @param mux : Clock to be configured.
368 * @return Nothing
369 */
CLOCK_Select(clock_select_t sel)370 static inline void CLOCK_Select(clock_select_t sel)
371 {
372 *(CLK_MUX_GET_REG(sel)) = CLK_MUX_GET_MUX(sel);
373 }
374
375 /*
376 *! @brief Setup peripheral clock dividers.
377 * @param name : Clock divider name
378 * @param value: Value to be divided
379 * @return Nothing
380 */
CLOCK_SetClkDivider(clock_divider_t name,uint32_t value)381 static inline void CLOCK_SetClkDivider(clock_divider_t name, uint32_t value)
382 {
383 CLK_DIV_GET_REG(name) = value & 0xFFU;
384 }
385
386 /*
387 *! @brief Get peripheral clock dividers.
388 * @param name : Clock divider name
389 * @return clock divider value
390 */
CLOCK_GetClkDivider(clock_divider_t name)391 static inline uint32_t CLOCK_GetClkDivider(clock_divider_t name)
392 {
393 return CLK_DIV_GET_REG(name) & 0xFFU;
394 }
395
396 /*
397 *! @brief Setup Core clock dividers.
398 * Be careful about the core divider value, due to core/system frequency should be lower than 30MHZ.
399 * @param value: Value to be divided
400 * @return Nothing
401 */
CLOCK_SetCoreSysClkDiv(uint32_t value)402 static inline void CLOCK_SetCoreSysClkDiv(uint32_t value)
403 {
404 assert(value != 0U);
405
406 SYSCON->SYSAHBCLKDIV = (SYSCON->SYSAHBCLKDIV & (~SYSCON_SYSAHBCLKDIV_DIV_MASK)) | SYSCON_SYSAHBCLKDIV_DIV(value);
407 }
408
409 /*! @brief Set main clock reference source.
410 * @param src Reference clock_main_clk_src_t to set the main clock source.
411 */
412 void CLOCK_SetMainClkSrc(clock_main_clk_src_t src);
413
414 /*
415 *! @brief Set Fractional generator multiplier value.
416 * @param base: Fractional generator register address
417 * @param mul : FRG multiplier value.
418 * @return Nothing
419 */
CLOCK_SetFRGClkMul(uint32_t * base,uint32_t mul)420 static inline void CLOCK_SetFRGClkMul(uint32_t *base, uint32_t mul)
421 {
422 CLK_FRG_DIV_REG_MAP(base) = SYSCON_FRG_FRGDIV_DIV_MASK;
423 CLK_FRG_MUL_REG_MAP(base) = SYSCON_FRG_FRGMULT_MULT(mul);
424 }
425 /* @} */
426
427 /*!
428 * @name Get frequency
429 * @{
430 */
431
432 /*! @brief Return Frequency of FRG0 Clock.
433 * @return Frequency of FRG0 Clock.
434 */
435 uint32_t CLOCK_GetFRGClkFreq(void);
436
437 /*! @brief Return Frequency of Main Clock.
438 * @return Frequency of Main Clock.
439 */
440 uint32_t CLOCK_GetMainClkFreq(void);
441
442 /*! @brief Return Frequency of FRO.
443 * @return Frequency of FRO.
444 */
445 uint32_t CLOCK_GetFroFreq(void);
446
447 /*! @brief Return Frequency of core.
448 * @return Frequency of core.
449 */
CLOCK_GetCoreSysClkFreq(void)450 static inline uint32_t CLOCK_GetCoreSysClkFreq(void)
451 {
452 return CLOCK_GetMainClkFreq() / (SYSCON->SYSAHBCLKDIV & 0xffU);
453 }
454
455 /*! @brief Return Frequency of ClockOut
456 * @return Frequency of ClockOut
457 */
458 uint32_t CLOCK_GetClockOutClkFreq(void);
459
460 /*! @brief Get UART0 frequency
461 * @retval UART0 frequency value.
462 */
463 uint32_t CLOCK_GetUart0ClkFreq(void);
464
465 /*! @brief Get UART1 frequency
466 * @retval UART1 frequency value.
467 */
468 uint32_t CLOCK_GetUart1ClkFreq(void);
469
470 /*! @brief Return Frequency of selected clock
471 * @return Frequency of selected clock
472 */
473 uint32_t CLOCK_GetFreq(clock_name_t clockName);
474
475 /*! @brief Get watch dog OSC frequency
476 * @retval watch dog OSC frequency value.
477 */
CLOCK_GetLPOscFreq(void)478 static inline uint32_t CLOCK_GetLPOscFreq(void)
479 {
480 return 1000000;
481 }
482
483 /*! @brief Get external clock frequency
484 * @retval external clock frequency value.
485 */
CLOCK_GetExtClkFreq(void)486 static inline uint32_t CLOCK_GetExtClkFreq(void)
487 {
488 return g_Ext_Clk_Freq;
489 }
490 /* @} */
491
492 /* @} */
493
494 /*!
495 * @name Fractional clock operations
496 * @{
497 */
498
499 /*! @brief Set FRG0 output frequency.
500 * @param freq, target output frequency,freq < input and (input / freq) < 2 should be satisfy.
501 * @retval true - successfully, false - input argument is invalid.
502 *
503 */
504 bool CLOCK_SetFRGClkFreq(uint32_t freq);
505
506 /* @} */
507
508 /*!
509 * @name External/internal oscillator clock operations
510 * @{
511 */
512
513 /*! @brief Init external CLK IN, select the CLKIN as the external clock source.
514 * @param clkInFreq external clock in frequency.
515 */
516 void CLOCK_InitExtClkin(uint32_t clkInFreq);
517
518 /*! @brief Deinit watch dog OSC
519 * @param config oscillator configuration.
520 */
CLOCK_DeinitLPOsc(void)521 static inline void CLOCK_DeinitLPOsc(void)
522 {
523 SYSCON->PDRUNCFG |= SYSCON_PDRUNCFG_LPOSC_PD_MASK;
524 }
525
526 /*! @brief Set FRO oscillator output frequency.
527 * Initialize the FRO clock to given frequency (18, 24 or 30 MHz).
528 * @param freq, please reference clock_fro_osc_freq_t definition, frequency must be one of 18000, 24000 or 30000 KHz.
529 *
530 */
531 void CLOCK_SetFroOscFreq(clock_fro_osc_freq_t freq);
532
533 /* @} */
534
535 #if defined(__cplusplus)
536 }
537 #endif /* __cplusplus */
538
539 /*! @} */
540
541 #endif /* _FSL_CLOCK_H_ */
542
