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Searched refs:SPI_CFG_SPOL0_MASK (Results 1 – 25 of 67) sorted by relevance

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/hal_nxp-latest/mcux/mcux-sdk/drivers/lpc_minispi/
Dfsl_spi.h111 kSPI_Spol0ActiveHigh = SPI_CFG_SPOL0_MASK,
122 kSPI_SpolActiveAllHigh = (SPI_CFG_SPOL0_MASK
/hal_nxp-latest/mcux/mcux-sdk/drivers/flexcomm/spi/
Dfsl_spi.c34 #define SPI_SSELPOL_MASK ((SPI_CFG_SPOL0_MASK) | (SPI_CFG_SPOL1_MASK) | (SPI_CFG_SPOL2_MASK))
37 #define SPI_SSELPOL_MASK ((SPI_CFG_SPOL0_MASK) | (SPI_CFG_SPOL1_MASK))
39 #define SPI_SSELPOL_MASK ((SPI_CFG_SPOL0_MASK) | (SPI_CFG_SPOL1_MASK) | (SPI_CFG_SPOL2_MASK) | (SPI…
/hal_nxp-latest/mcux/mcux-sdk/devices/LPC811/
DLPC811.h3756 #define SPI_CFG_SPOL0_MASK (0x100U) macro
3762 … (((uint32_t)(((uint32_t)(x)) << SPI_CFG_SPOL0_SHIFT)) & SPI_CFG_SPOL0_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/LPC812/
DLPC812.h3760 #define SPI_CFG_SPOL0_MASK (0x100U) macro
3766 … (((uint32_t)(((uint32_t)(x)) << SPI_CFG_SPOL0_SHIFT)) & SPI_CFG_SPOL0_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/LPC810/
DLPC810.h3756 #define SPI_CFG_SPOL0_MASK (0x100U) macro
3762 … (((uint32_t)(((uint32_t)(x)) << SPI_CFG_SPOL0_SHIFT)) & SPI_CFG_SPOL0_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/LPC802/
DLPC802.h3565 #define SPI_CFG_SPOL0_MASK (0x100U) macro
3571 … (((uint32_t)(((uint32_t)(x)) << SPI_CFG_SPOL0_SHIFT)) & SPI_CFG_SPOL0_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/LPC804/
DLPC804.h4236 #define SPI_CFG_SPOL0_MASK (0x100U) macro
4242 … (((uint32_t)(((uint32_t)(x)) << SPI_CFG_SPOL0_SHIFT)) & SPI_CFG_SPOL0_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/LPC824/
DLPC824.h5412 #define SPI_CFG_SPOL0_MASK (0x100U) macro
5418 … (((uint32_t)(((uint32_t)(x)) << SPI_CFG_SPOL0_SHIFT)) & SPI_CFG_SPOL0_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/LPC822/
DLPC822.h5412 #define SPI_CFG_SPOL0_MASK (0x100U) macro
5418 … (((uint32_t)(((uint32_t)(x)) << SPI_CFG_SPOL0_SHIFT)) & SPI_CFG_SPOL0_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/LPC834/
DLPC834.h5256 #define SPI_CFG_SPOL0_MASK (0x100U) macro
5262 … (((uint32_t)(((uint32_t)(x)) << SPI_CFG_SPOL0_SHIFT)) & SPI_CFG_SPOL0_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/LPC832/
DLPC832.h5256 #define SPI_CFG_SPOL0_MASK (0x100U) macro
5262 … (((uint32_t)(((uint32_t)(x)) << SPI_CFG_SPOL0_SHIFT)) & SPI_CFG_SPOL0_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/LPC844/
DLPC844.h5912 #define SPI_CFG_SPOL0_MASK (0x100U) macro
5918 … (((uint32_t)(((uint32_t)(x)) << SPI_CFG_SPOL0_SHIFT)) & SPI_CFG_SPOL0_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/LPC845/
DLPC845.h6436 #define SPI_CFG_SPOL0_MASK (0x100U) macro
6442 … (((uint32_t)(((uint32_t)(x)) << SPI_CFG_SPOL0_SHIFT)) & SPI_CFG_SPOL0_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/LPC865/
DLPC865.h7843 #define SPI_CFG_SPOL0_MASK (0x100U) macro
7849 … (((uint32_t)(((uint32_t)(x)) << SPI_CFG_SPOL0_SHIFT)) & SPI_CFG_SPOL0_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/LPC864/
DLPC864.h7841 #define SPI_CFG_SPOL0_MASK (0x100U) macro
7847 … (((uint32_t)(((uint32_t)(x)) << SPI_CFG_SPOL0_SHIFT)) & SPI_CFG_SPOL0_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/LPC51U68/
DLPC51U68.h7036 #define SPI_CFG_SPOL0_MASK (0x100U) macro
7042 … (((uint32_t)(((uint32_t)(x)) << SPI_CFG_SPOL0_SHIFT)) & SPI_CFG_SPOL0_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/LPC54114/
DLPC54114_cm0plus.h7337 #define SPI_CFG_SPOL0_MASK (0x100U) macro
7343 … (((uint32_t)(((uint32_t)(x)) << SPI_CFG_SPOL0_SHIFT)) & SPI_CFG_SPOL0_MASK)
DLPC54114_cm4.h7348 #define SPI_CFG_SPOL0_MASK (0x100U) macro
7354 … (((uint32_t)(((uint32_t)(x)) << SPI_CFG_SPOL0_SHIFT)) & SPI_CFG_SPOL0_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/LPC54113/
DLPC54113.h7349 #define SPI_CFG_SPOL0_MASK (0x100U) macro
7355 … (((uint32_t)(((uint32_t)(x)) << SPI_CFG_SPOL0_SHIFT)) & SPI_CFG_SPOL0_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/LPC54607/
DLPC54607.h11431 #define SPI_CFG_SPOL0_MASK (0x100U) macro
11437 … (((uint32_t)(((uint32_t)(x)) << SPI_CFG_SPOL0_SHIFT)) & SPI_CFG_SPOL0_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/LPC54S005/
DLPC54S005.h11449 #define SPI_CFG_SPOL0_MASK (0x100U) macro
11455 … (((uint32_t)(((uint32_t)(x)) << SPI_CFG_SPOL0_SHIFT)) & SPI_CFG_SPOL0_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/LPC54005/
DLPC54005.h10657 #define SPI_CFG_SPOL0_MASK (0x100U) macro
10663 … (((uint32_t)(((uint32_t)(x)) << SPI_CFG_SPOL0_SHIFT)) & SPI_CFG_SPOL0_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/LPC54605/
DLPC54605.h10787 #define SPI_CFG_SPOL0_MASK (0x100U) macro
10793 … (((uint32_t)(((uint32_t)(x)) << SPI_CFG_SPOL0_SHIFT)) & SPI_CFG_SPOL0_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/LPC54606/
DLPC54606.h14935 #define SPI_CFG_SPOL0_MASK (0x100U) macro
14941 … (((uint32_t)(((uint32_t)(x)) << SPI_CFG_SPOL0_SHIFT)) & SPI_CFG_SPOL0_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/LPC54016/
DLPC54016.h14038 #define SPI_CFG_SPOL0_MASK (0x100U) macro
14044 … (((uint32_t)(((uint32_t)(x)) << SPI_CFG_SPOL0_SHIFT)) & SPI_CFG_SPOL0_MASK)

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