1 /*
2 * Copyright 2017-2020,2022 NXP
3 * All rights reserved.
4 *
5 *
6 * SPDX-License-Identifier: BSD-3-Clause
7 */
8
9 #ifndef FSL_SPI_H_
10 #define FSL_SPI_H_
11
12 #include "fsl_common.h"
13
14 /*!
15 * @addtogroup spi_driver
16 * @{
17 */
18
19 /*! @file */
20
21 /*******************************************************************************
22 * Definitions
23 ******************************************************************************/
24
25 /*! @name Driver version */
26 /*! @{ */
27 /*! @brief SPI driver version. */
28 #define FSL_SPI_DRIVER_VERSION (MAKE_VERSION(2, 0, 7))
29 /*! @} */
30
31 #ifndef SPI_DUMMYDATA
32 /*! @brief SPI dummy transfer data, the data is sent while txBuff is NULL. */
33 #define SPI_DUMMYDATA (0x00U)
34 #endif
35
36 /* Macro gate for enable/disable the SPI transactional API. 1 for enable, 0 for disable. */
37 #ifndef FSL_SDK_ENABLE_SPI_DRIVER_TRANSACTIONAL_APIS
38 #define FSL_SDK_ENABLE_SPI_DRIVER_TRANSACTIONAL_APIS 1
39 #endif
40
41 /*! @brief Retry times for waiting flag. */
42 #ifndef SPI_RETRY_TIMES
43 #define SPI_RETRY_TIMES 0U /* Define to zero means keep waiting until the flag is assert/deassert. */
44 #endif
45
46 /* @brief Dummy data for each instance. This data is used when user's tx buffer is NULL*/
47 extern volatile uint16_t s_dummyData[];
48
49 /*! @brief SPI transfer option.*/
50 enum _spi_xfer_option
51 {
52 kSPI_EndOfFrame = (SPI_TXDATCTL_EOF_MASK), /*!< Add delay at the end of each frame(the last clk edge). */
53 kSPI_EndOfTransfer =
54 (SPI_TXDATCTL_EOT_MASK), /*!< Re-assert the CS signal after transfer finishes to deselect slave. */
55 kSPI_ReceiveIgnore = (SPI_TXDATCTL_RXIGNORE_MASK), /*!< Ignore the receive data. */
56 };
57
58 /*! @brief SPI data shifter direction options.*/
59 typedef enum _spi_shift_direction
60 {
61 kSPI_MsbFirst = 0U, /*!< Data transfers start with most significant bit. */
62 kSPI_LsbFirst = 1U, /*!< Data transfers start with least significant bit. */
63 } spi_shift_direction_t;
64
65 /*! @brief SPI clock polarity configuration.*/
66 typedef enum _spi_clock_polarity
67 {
68 kSPI_ClockPolarityActiveHigh = 0x0U, /*!< Active-high SPI clock (idles low). */
69 kSPI_ClockPolarityActiveLow = 0x1U, /*!< Active-low SPI clock (idles high). */
70 } spi_clock_polarity_t;
71
72 /*! @brief SPI clock phase configuration.*/
73 typedef enum _spi_clock_phase
74 {
75 kSPI_ClockPhaseFirstEdge = 0x0U, /*!< First edge on SCK occurs at the middle of the first
76 * cycle of a data transfer. */
77 kSPI_ClockPhaseSecondEdge = 0x1U, /*!< First edge on SCK occurs at the start of the
78 * first cycle of a data transfer. */
79 } spi_clock_phase_t;
80
81 /*! @brief Slave select */
82 typedef enum _spi_ssel
83 {
84 kSPI_Ssel0Assert = (int)(~SPI_TXDATCTL_TXSSEL0_N_MASK), /*!< Slave select 0 */
85 #if defined(SPI_TXDATCTL_TXSSEL1_N_MASK)
86 kSPI_Ssel1Assert = (int)(~SPI_TXDATCTL_TXSSEL1_N_MASK), /*!< Slave select 1 */
87 #endif
88 #if defined(SPI_TXDATCTL_TXSSEL2_N_MASK)
89 kSPI_Ssel2Assert = (int)(~SPI_TXDATCTL_TXSSEL2_N_MASK), /*!< Slave select 2 */
90 #endif
91 #if defined(SPI_TXDATCTL_TXSSEL3_N_MASK)
92 kSPI_Ssel3Assert = (int)(~SPI_TXDATCTL_TXSSEL3_N_MASK), /*!< Slave select 3 */
93 #endif
94 kSPI_SselDeAssertAll = (SPI_TXDATCTL_TXSSEL0_N_MASK
95 #if defined(FSL_FEATURE_SPI_HAS_SSEL1) & FSL_FEATURE_SPI_HAS_SSEL1
96 | SPI_TXDATCTL_TXSSEL1_N_MASK
97 #endif
98 #if defined(FSL_FEATURE_SPI_HAS_SSEL2) & FSL_FEATURE_SPI_HAS_SSEL2
99 | SPI_TXDATCTL_TXSSEL2_N_MASK
100 #endif
101 #if defined(FSL_FEATURE_SPI_HAS_SSEL3) & FSL_FEATURE_SPI_HAS_SSEL3
102 | SPI_TXDATCTL_TXSSEL3_N_MASK
103 #endif
104 ),
105 } spi_ssel_t;
106
107 /*! @brief ssel polarity */
108 typedef enum _spi_spol
109 {
110 #if defined(FSL_FEATURE_SPI_HAS_SSEL0) & FSL_FEATURE_SPI_HAS_SSEL0
111 kSPI_Spol0ActiveHigh = SPI_CFG_SPOL0_MASK,
112 #endif
113 #if defined(FSL_FEATURE_SPI_HAS_SSEL1) & FSL_FEATURE_SPI_HAS_SSEL1
114 kSPI_Spol1ActiveHigh = SPI_CFG_SPOL1_MASK,
115 #endif
116 #if defined(FSL_FEATURE_SPI_HAS_SSEL2) & FSL_FEATURE_SPI_HAS_SSEL2
117 kSPI_Spol2ActiveHigh = SPI_CFG_SPOL2_MASK,
118 #endif
119 #if defined(FSL_FEATURE_SPI_HAS_SSEL3) & FSL_FEATURE_SPI_HAS_SSEL3
120 kSPI_Spol3ActiveHigh = SPI_CFG_SPOL3_MASK,
121 #endif
122 kSPI_SpolActiveAllHigh = (SPI_CFG_SPOL0_MASK
123 #if defined(FSL_FEATURE_SPI_HAS_SSEL1) & FSL_FEATURE_SPI_HAS_SSEL1
124 | SPI_CFG_SPOL1_MASK
125 #endif
126 #if defined(FSL_FEATURE_SPI_HAS_SSEL2) & FSL_FEATURE_SPI_HAS_SSEL2
127 | SPI_CFG_SPOL2_MASK
128 #endif
129 #if defined(FSL_FEATURE_SPI_HAS_SSEL3) & FSL_FEATURE_SPI_HAS_SSEL3
130 | SPI_CFG_SPOL3_MASK
131 #endif
132 ),
133 kSPI_SpolActiveAllLow = (int)(~kSPI_SpolActiveAllHigh),
134 } spi_spol_t;
135
136 /*! @brief Transfer data width */
137 typedef enum _spi_data_width
138 {
139 kSPI_Data4Bits = 3, /*!< 4 bits data width */
140 kSPI_Data5Bits = 4, /*!< 5 bits data width */
141 kSPI_Data6Bits = 5, /*!< 6 bits data width */
142 kSPI_Data7Bits = 6, /*!< 7 bits data width */
143 kSPI_Data8Bits = 7, /*!< 8 bits data width */
144 kSPI_Data9Bits = 8, /*!< 9 bits data width */
145 kSPI_Data10Bits = 9, /*!< 10 bits data width */
146 kSPI_Data11Bits = 10, /*!< 11 bits data width */
147 kSPI_Data12Bits = 11, /*!< 12 bits data width */
148 kSPI_Data13Bits = 12, /*!< 13 bits data width */
149 kSPI_Data14Bits = 13, /*!< 14 bits data width */
150 kSPI_Data15Bits = 14, /*!< 15 bits data width */
151 kSPI_Data16Bits = 15, /*!< 16 bits data width */
152 } spi_data_width_t;
153
154 /*! @brief SPI delay time configure structure.*/
155 typedef struct _spi_delay_config
156 {
157 uint8_t preDelay; /*!< Delay between SSEL assertion and the beginning of transfer. */
158 uint8_t postDelay; /*!< Delay between the end of transfer and SSEL deassertion. */
159 uint8_t frameDelay; /*!< Delay between frame to frame. */
160 uint8_t transferDelay; /*!< Delay between transfer to transfer. */
161 } spi_delay_config_t;
162
163 /*! @brief SPI master user configure structure.*/
164 typedef struct _spi_master_config
165 {
166 bool enableLoopback; /*!< Enable loopback for test purpose */
167 bool enableMaster; /*!< Enable SPI at initialization time */
168 uint32_t baudRate_Bps; /*!< Baud Rate for SPI in Hz */
169 spi_clock_polarity_t clockPolarity; /*!< Clock polarity */
170 spi_clock_phase_t clockPhase; /*!< Clock phase */
171 spi_shift_direction_t direction; /*!< MSB or LSB */
172 uint8_t dataWidth; /*!< Width of the data */
173 spi_ssel_t sselNumber; /*!< Slave select number */
174 spi_spol_t sselPolarity; /*!< Configure active CS polarity */
175 spi_delay_config_t delayConfig; /*!< Configure for delay time. */
176 } spi_master_config_t;
177
178 /*! @brief SPI slave user configure structure.*/
179 typedef struct _spi_slave_config
180 {
181 bool enableSlave; /*!< Enable SPI at initialization time */
182 spi_clock_polarity_t clockPolarity; /*!< Clock polarity */
183 spi_clock_phase_t clockPhase; /*!< Clock phase */
184 spi_shift_direction_t direction; /*!< MSB or LSB */
185 uint8_t dataWidth; /*!< Width of the data */
186 spi_spol_t sselPolarity; /*!< Configure active CS polarity */
187 } spi_slave_config_t;
188
189 /*! @brief SPI transfer status.*/
190 enum
191 {
192 kStatus_SPI_Busy = MAKE_STATUS(kStatusGroup_LPC_MINISPI, 0), /*!< SPI bus is busy */
193 kStatus_SPI_Idle = MAKE_STATUS(kStatusGroup_LPC_MINISPI, 1), /*!< SPI is idle */
194 kStatus_SPI_Error = MAKE_STATUS(kStatusGroup_LPC_MINISPI, 2), /*!< SPI error */
195 kStatus_SPI_BaudrateNotSupport =
196 MAKE_STATUS(kStatusGroup_LPC_MINISPI, 3), /*!< Baudrate is not support in current clock source */
197 kStatus_SPI_Timeout = MAKE_STATUS(kStatusGroup_LPC_MINISPI, 4) /*!< SPI Timeout polling status flags. */
198 };
199
200 /*! @brief SPI interrupt sources.*/
201 enum _spi_interrupt_enable
202 {
203 kSPI_RxReadyInterruptEnable = SPI_INTENSET_RXRDYEN_MASK, /*!< Rx ready interrupt */
204 kSPI_TxReadyInterruptEnable = SPI_INTENSET_TXRDYEN_MASK, /*!< Tx ready interrupt */
205 kSPI_RxOverrunInterruptEnable = SPI_INTENSET_RXOVEN_MASK, /*!< Rx overrun interrupt */
206 kSPI_TxUnderrunInterruptEnable = SPI_INTENSET_TXUREN_MASK, /*!< Tx underrun interrupt */
207 kSPI_SlaveSelectAssertInterruptEnable = SPI_INTENSET_SSAEN_MASK, /*!< Slave select assert interrupt */
208 kSPI_SlaveSelectDeassertInterruptEnable = SPI_INTENSET_SSDEN_MASK, /*!< Slave select deassert interrupt */
209 kSPI_AllInterruptEnable = (SPI_INTENSET_RXRDYEN_MASK | SPI_INTENSET_TXRDYEN_MASK | SPI_INTENSET_RXOVEN_MASK |
210 SPI_INTENSET_TXUREN_MASK | SPI_INTENSET_SSAEN_MASK | SPI_INTENSET_SSDEN_MASK)
211 };
212
213 /*! @brief SPI status flags.*/
214 enum _spi_status_flags
215 {
216 kSPI_RxReadyFlag = SPI_STAT_RXRDY_MASK, /*!< Receive ready flag. */
217 kSPI_TxReadyFlag = SPI_STAT_TXRDY_MASK, /*!< Transmit ready flag. */
218 kSPI_RxOverrunFlag = SPI_STAT_RXOV_MASK, /*!< Receive overrun flag. */
219 kSPI_TxUnderrunFlag = SPI_STAT_TXUR_MASK, /*!< Transmit underrun flag. */
220 kSPI_SlaveSelectAssertFlag = SPI_STAT_SSA_MASK, /*!< Slave select assert flag. */
221 kSPI_SlaveSelectDeassertFlag = SPI_STAT_SSD_MASK, /*!< slave select deassert flag. */
222 kSPI_StallFlag = SPI_STAT_STALLED_MASK, /*!< Stall flag. */
223 kSPI_EndTransferFlag = SPI_STAT_ENDTRANSFER_MASK, /*!< End transfer bit. */
224 kSPI_MasterIdleFlag = SPI_STAT_MSTIDLE_MASK, /*!< Master in idle status flag. */
225 };
226
227 /*! @brief SPI transfer structure */
228 typedef struct _spi_transfer
229 {
230 const uint8_t *txData; /*!< Send buffer */
231 uint8_t *rxData; /*!< Receive buffer */
232 size_t dataSize; /*!< Transfer bytes */
233 uint32_t configFlags; /*!< Additional option to control transfer @ref _spi_xfer_option. */
234 } spi_transfer_t;
235
236 #if defined(FSL_SDK_ENABLE_SPI_DRIVER_TRANSACTIONAL_APIS) && (FSL_SDK_ENABLE_SPI_DRIVER_TRANSACTIONAL_APIS)
237 /*! @brief Master handle type */
238 typedef struct _spi_master_handle spi_master_handle_t;
239
240 /*! @brief Slave handle type */
241 typedef spi_master_handle_t spi_slave_handle_t;
242
243 /*! @brief SPI master callback for finished transmit */
244 typedef void (*spi_master_callback_t)(SPI_Type *base, spi_master_handle_t *handle, status_t status, void *userData);
245
246 /*! @brief SPI slave callback for finished transmit */
247 typedef void (*spi_slave_callback_t)(SPI_Type *base, spi_slave_handle_t *handle, status_t status, void *userData);
248
249 /*! @brief SPI transfer handle structure */
250 struct _spi_master_handle
251 {
252 const uint8_t *volatile txData; /*!< Transfer buffer */
253 uint8_t *volatile rxData; /*!< Receive buffer */
254 volatile size_t txRemainingBytes; /*!< Number of data to be transmitted [in bytes] */
255 volatile size_t rxRemainingBytes; /*!< Number of data to be received [in bytes] */
256 size_t totalByteCount; /*!< A number of transfer bytes */
257 volatile uint32_t state; /*!< SPI internal state */
258 spi_master_callback_t callback; /*!< SPI callback */
259 void *userData; /*!< Callback parameter */
260 uint8_t dataWidth; /*!< Width of the data [Valid values: 1 to 16] */
261 uint32_t lastCommand; /*!< Last command for transfer. */
262 };
263 #endif /* FSL_SDK_ENABLE_SPI_DRIVER_TRANSACTIONAL_APIS */
264
265 #if defined(__cplusplus)
266 extern "C" {
267 #endif
268 /*******************************************************************************
269 * API
270 ******************************************************************************/
271
272 /*! @brief Returns instance number for SPI peripheral base address. */
273 uint32_t SPI_GetInstance(SPI_Type *base);
274
275 /*!
276 * @name Initialization and deinitialization
277 * @{
278 */
279
280 /*!
281 * @brief Sets the SPI master configuration structure to default values.
282 *
283 * The purpose of this API is to get the configuration structure initialized for use in SPI_MasterInit().
284 * User may use the initialized structure unchanged in SPI_MasterInit(), or modify
285 * some fields of the structure before calling SPI_MasterInit(). After calling this API,
286 * the master is ready to transfer.
287 * Example:
288 @code
289 spi_master_config_t config;
290 SPI_MasterGetDefaultConfig(&config);
291 @endcode
292 *
293 * @param config pointer to master config structure
294 */
295 void SPI_MasterGetDefaultConfig(spi_master_config_t *config);
296
297 /*!
298 * @brief Initializes the SPI with master configuration.
299 *
300 * The configuration structure can be filled by user from scratch, or be set with default
301 * values by SPI_MasterGetDefaultConfig(). After calling this API, the slave is ready to transfer.
302 * Example
303 @code
304 spi_master_config_t config = {
305 .baudRate_Bps = 500000,
306 ...
307 };
308 SPI_MasterInit(SPI0, &config);
309 @endcode
310 *
311 * @param base SPI base pointer
312 * @param config pointer to master configuration structure
313 * @param srcClock_Hz Source clock frequency.
314 */
315 status_t SPI_MasterInit(SPI_Type *base, const spi_master_config_t *config, uint32_t srcClock_Hz);
316
317 /*!
318 * @brief Sets the SPI slave configuration structure to default values.
319 *
320 * The purpose of this API is to get the configuration structure initialized for use in SPI_SlaveInit().
321 * Modify some fields of the structure before calling SPI_SlaveInit().
322 * Example:
323 @code
324 spi_slave_config_t config;
325 SPI_SlaveGetDefaultConfig(&config);
326 @endcode
327 *
328 * @param config pointer to slave configuration structure
329 */
330 void SPI_SlaveGetDefaultConfig(spi_slave_config_t *config);
331
332 /*!
333 * @brief Initializes the SPI with slave configuration.
334 *
335 * The configuration structure can be filled by user from scratch or be set with
336 * default values by SPI_SlaveGetDefaultConfig().
337 * After calling this API, the slave is ready to transfer.
338 * Example
339 @code
340 spi_slave_config_t config = {
341 .polarity = kSPI_ClockPolarityActiveHigh;
342 .phase = kSPI_ClockPhaseFirstEdge;
343 .direction = kSPI_MsbFirst;
344 ...
345 };
346 SPI_SlaveInit(SPI0, &config);
347 @endcode
348 *
349 * @param base SPI base pointer
350 * @param config pointer to slave configuration structure
351 */
352 status_t SPI_SlaveInit(SPI_Type *base, const spi_slave_config_t *config);
353
354 /*!
355 * @brief De-initializes the SPI.
356 *
357 * Calling this API resets the SPI module, gates the SPI clock.
358 * Disable the fifo if enabled.
359 * The SPI module can't work unless calling the SPI_MasterInit/SPI_SlaveInit to initialize module.
360 *
361 * @param base SPI base pointer
362 */
363 void SPI_Deinit(SPI_Type *base);
364
365 /*!
366
367 * @brief Enable or disable the SPI Master or Slave
368 * @param base SPI base pointer
369 * @param enable or disable ( true = enable, false = disable)
370 */
SPI_Enable(SPI_Type * base,bool enable)371 static inline void SPI_Enable(SPI_Type *base, bool enable)
372 {
373 if (enable)
374 {
375 base->CFG |= SPI_CFG_ENABLE_MASK;
376 }
377 else
378 {
379 base->CFG &= ~SPI_CFG_ENABLE_MASK;
380 }
381 }
382
383 /*! @} */
384
385 /*!
386 * @name Status
387 * @{
388 */
389
390 /*!
391 * @brief Gets the status flag.
392 *
393 * @param base SPI base pointer
394 * @return SPI Status, use status flag to AND @ref _spi_status_flags could get the related status.
395 */
SPI_GetStatusFlags(SPI_Type * base)396 static inline uint32_t SPI_GetStatusFlags(SPI_Type *base)
397 {
398 assert(NULL != base);
399 return base->STAT;
400 }
401
402 /*!
403 * @brief Clear the status flag.
404 *
405 * @param base SPI base pointer
406 * @param mask SPI Status, use status flag to AND @ref _spi_status_flags could get the related status.
407 */
SPI_ClearStatusFlags(SPI_Type * base,uint32_t mask)408 static inline void SPI_ClearStatusFlags(SPI_Type *base, uint32_t mask)
409 {
410 assert(NULL != base);
411 base->STAT |= mask;
412 }
413 /*! @} */
414
415 /*!
416 * @name Interrupts
417 * @{
418 */
419
420 /*!
421 * @brief Enables the interrupt for the SPI.
422 *
423 * @param base SPI base pointer
424 * @param irqs SPI interrupt source. The parameter can be any combination of the following values:
425 * @arg kSPI_RxReadyInterruptEnable
426 * @arg kSPI_TxReadyInterruptEnable
427 */
SPI_EnableInterrupts(SPI_Type * base,uint32_t irqs)428 static inline void SPI_EnableInterrupts(SPI_Type *base, uint32_t irqs)
429 {
430 assert(NULL != base);
431 base->INTENSET = irqs;
432 }
433
434 /*!
435 * @brief Disables the interrupt for the SPI.
436 *
437 * @param base SPI base pointer
438 * @param irqs SPI interrupt source. The parameter can be any combination of the following values:
439 * @arg kSPI_RxReadyInterruptEnable
440 * @arg kSPI_TxReadyInterruptEnable
441 */
SPI_DisableInterrupts(SPI_Type * base,uint32_t irqs)442 static inline void SPI_DisableInterrupts(SPI_Type *base, uint32_t irqs)
443 {
444 assert(NULL != base);
445 base->INTENCLR = irqs;
446 }
447 /*! @} */
448
449 /*!
450 * @name Bus Operations
451 * @{
452 */
453
454 /*!
455 * @brief Returns whether the SPI module is in master mode.
456 *
457 * @param base SPI peripheral address.
458 * @return Returns true if the module is in master mode or false if the module is in slave mode.
459 */
SPI_IsMaster(SPI_Type * base)460 static inline bool SPI_IsMaster(SPI_Type *base)
461 {
462 return (bool)(((base->CFG) & SPI_CFG_MASTER_MASK) >> SPI_CFG_MASTER_SHIFT);
463 }
464 /*!
465 * @brief Sets the baud rate for SPI transfer. This is only used in master.
466 *
467 * @param base SPI base pointer
468 * @param baudrate_Bps baud rate needed in Hz.
469 * @param srcClock_Hz SPI source clock frequency in Hz.
470 */
471 status_t SPI_MasterSetBaudRate(SPI_Type *base, uint32_t baudrate_Bps, uint32_t srcClock_Hz);
472
473 /*!
474 * @brief Writes a data into the SPI data register directly.
475 *
476 * @param base SPI base pointer
477 * @param data needs to be write.
478 */
SPI_WriteData(SPI_Type * base,uint16_t data)479 static inline void SPI_WriteData(SPI_Type *base, uint16_t data)
480 {
481 base->TXDAT = ((uint32_t)data & 0x0000FFFFU);
482 }
483
484 /*!
485 * @brief Writes a data into the SPI TXCTL register directly.
486 *
487 * @param base SPI base pointer
488 * @param configFlags control command needs to be written.
489 */
SPI_WriteConfigFlags(SPI_Type * base,uint32_t configFlags)490 static inline void SPI_WriteConfigFlags(SPI_Type *base, uint32_t configFlags)
491 {
492 base->TXCTL = (base->TXCTL & ~(SPI_TXCTL_EOT_MASK | SPI_TXCTL_EOF_MASK | SPI_TXCTL_RXIGNORE_MASK)) |
493 (configFlags & (SPI_TXCTL_EOT_MASK | SPI_TXCTL_EOF_MASK | SPI_TXCTL_RXIGNORE_MASK));
494 }
495
496 /*!
497 * @brief Writes a data control info and data into the SPI TX register directly.
498 *
499 * @param base SPI base pointer
500 * @param data value needs to be written.
501 * @param configFlags control command needs to be written.
502 */
503 void SPI_WriteDataWithConfigFlags(SPI_Type *base, uint16_t data, uint32_t configFlags);
504
505 /*!
506 * @brief Gets a data from the SPI data register.
507 *
508 * @param base SPI base pointer
509 * @return Data in the register.
510 */
SPI_ReadData(SPI_Type * base)511 static inline uint32_t SPI_ReadData(SPI_Type *base)
512 {
513 return (base->RXDAT & 0x0000FFFFU);
514 }
515
516 /*!
517 * @brief Set delay time for transfer.
518 * the delay uint is SPI clock time, maximum value is 0xF.
519 * @param base SPI base pointer
520 * @param config configuration for delay option @ref spi_delay_config_t.
521 */
522 void SPI_SetTransferDelay(SPI_Type *base, const spi_delay_config_t *config);
523
524 /*!
525 * @brief Set up the dummy data. This API can change the default data to be transferred
526 * when users set the tx buffer to NULL.
527 *
528 * @param base SPI peripheral address.
529 * @param dummyData Data to be transferred when tx buffer is NULL.
530 */
531 void SPI_SetDummyData(SPI_Type *base, uint16_t dummyData);
532
533 /*!
534 * @brief Transfers a block of data using a polling method.
535 *
536 * @param base SPI base pointer
537 * @param xfer pointer to spi_xfer_config_t structure
538 * @retval kStatus_Success Successfully start a transfer.
539 * @retval kStatus_InvalidArgument Input argument is invalid.
540 * @retval kStatus_SPI_Timeout The transfer timed out and was aborted.
541 */
542 status_t SPI_MasterTransferBlocking(SPI_Type *base, spi_transfer_t *xfer);
543 /*! @} */
544
545 #if defined(FSL_SDK_ENABLE_SPI_DRIVER_TRANSACTIONAL_APIS) && (FSL_SDK_ENABLE_SPI_DRIVER_TRANSACTIONAL_APIS)
546 /*!
547 * @name Transactional
548 * @{
549 */
550
551 /*!
552 * @brief Initializes the SPI master handle.
553 *
554 * This function initializes the SPI master handle which can be used for other SPI master transactional APIs. Usually,
555 * for a specified SPI instance, call this API once to get the initialized handle.
556 *
557 * @param base SPI peripheral base address.
558 * @param handle SPI handle pointer.
559 * @param callback Callback function.
560 * @param userData User data.
561 */
562 status_t SPI_MasterTransferCreateHandle(SPI_Type *base,
563 spi_master_handle_t *handle,
564 spi_master_callback_t callback,
565 void *userData);
566
567 /*!
568 * @brief Performs a non-blocking SPI interrupt transfer.
569 *
570 * @param base SPI peripheral base address.
571 * @param handle pointer to spi_master_handle_t structure which stores the transfer state
572 * @param xfer pointer to spi_xfer_config_t structure
573 * @retval kStatus_Success Successfully start a transfer.
574 * @retval kStatus_InvalidArgument Input argument is invalid.
575 * @retval kStatus_SPI_Busy SPI is not idle, is running another transfer.
576 */
577 status_t SPI_MasterTransferNonBlocking(SPI_Type *base, spi_master_handle_t *handle, spi_transfer_t *xfer);
578
579 /*!
580 * @brief Gets the master transfer count.
581 *
582 * This function gets the master transfer count.
583 *
584 * @param base SPI peripheral base address.
585 * @param handle Pointer to the spi_master_handle_t structure which stores the transfer state.
586 * @param count The number of bytes transferred by using the non-blocking transaction.
587 * @return status of status_t.
588 */
589 status_t SPI_MasterTransferGetCount(SPI_Type *base, spi_master_handle_t *handle, size_t *count);
590
591 /*!
592 * @brief SPI master aborts a transfer using an interrupt.
593 *
594 * This function aborts a transfer using an interrupt.
595 *
596 * @param base SPI peripheral base address.
597 * @param handle Pointer to the spi_master_handle_t structure which stores the transfer state.
598 */
599 void SPI_MasterTransferAbort(SPI_Type *base, spi_master_handle_t *handle);
600
601 /*!
602 * @brief Interrupts the handler for the SPI.
603 *
604 * @param base SPI peripheral base address.
605 * @param handle pointer to spi_master_handle_t structure which stores the transfer state.
606 */
607 void SPI_MasterTransferHandleIRQ(SPI_Type *base, spi_master_handle_t *handle);
608
609 /*!
610 * @brief Initializes the SPI slave handle.
611 *
612 * This function initializes the SPI slave handle which can be used for other SPI slave transactional APIs. Usually,
613 * for a specified SPI instance, call this API once to get the initialized handle.
614 *
615 * @param base SPI peripheral base address.
616 * @param handle SPI handle pointer.
617 * @param callback Callback function.
618 * @param userData User data.
619 */
620 status_t SPI_SlaveTransferCreateHandle(SPI_Type *base,
621 spi_slave_handle_t *handle,
622 spi_slave_callback_t callback,
623 void *userData);
624
625 /*!
626 * @brief Performs a non-blocking SPI slave interrupt transfer.
627 *
628 * @note The API returns immediately after the transfer initialization is finished.
629 *
630 * @param base SPI peripheral base address.
631 * @param handle pointer to spi_master_handle_t structure which stores the transfer state
632 * @param xfer pointer to spi_xfer_config_t structure
633 * @retval kStatus_Success Successfully start a transfer.
634 * @retval kStatus_InvalidArgument Input argument is invalid.
635 * @retval kStatus_SPI_Busy SPI is not idle, is running another transfer.
636 */
637 status_t SPI_SlaveTransferNonBlocking(SPI_Type *base, spi_slave_handle_t *handle, spi_transfer_t *xfer);
638
639 /*!
640 * @brief Gets the slave transfer count.
641 *
642 * This function gets the slave transfer count.
643 *
644 * @param base SPI peripheral base address.
645 * @param handle Pointer to the spi_master_handle_t structure which stores the transfer state.
646 * @param count The number of bytes transferred by using the non-blocking transaction.
647 * @return status of status_t.
648 */
SPI_SlaveTransferGetCount(SPI_Type * base,spi_slave_handle_t * handle,size_t * count)649 static inline status_t SPI_SlaveTransferGetCount(SPI_Type *base, spi_slave_handle_t *handle, size_t *count)
650 {
651 return SPI_MasterTransferGetCount(base, (spi_master_handle_t *)handle, count);
652 }
653
654 /*!
655 * @brief SPI slave aborts a transfer using an interrupt.
656 *
657 * This function aborts a transfer using an interrupt.
658 *
659 * @param base SPI peripheral base address.
660 * @param handle Pointer to the spi_slave_handle_t structure which stores the transfer state.
661 */
SPI_SlaveTransferAbort(SPI_Type * base,spi_slave_handle_t * handle)662 static inline void SPI_SlaveTransferAbort(SPI_Type *base, spi_slave_handle_t *handle)
663 {
664 SPI_MasterTransferAbort(base, (spi_master_handle_t *)handle);
665 }
666
667 /*!
668 * @brief Interrupts a handler for the SPI slave.
669 *
670 * @param base SPI peripheral base address.
671 * @param handle pointer to spi_slave_handle_t structure which stores the transfer state
672 */
673 void SPI_SlaveTransferHandleIRQ(SPI_Type *base, spi_slave_handle_t *handle);
674 /*! @} */
675 #endif /* FSL_SDK_ENABLE_SPI_DRIVER_TRANSACTIONAL_APIS */
676
677 #if defined(__cplusplus)
678 }
679 #endif
680
681 /*! @} */
682
683 #endif /* FSL_SPI_H_*/
684
