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Searched refs:CLR (Results 1 – 25 of 177) sorted by relevance

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/hal_nxp-latest/mcux/mcux-sdk/drivers/epdc/
Dfsl_epdc.h520 base->IRQ_MASK.CLR = ((uint32_t)interrupts << 16U); in EPDC_DisableInterrupts()
554 base->IRQ.CLR = ((uint32_t)statusFlags << 12U); in EPDC_ClearStatusFlags()
584 base->IRQ_MASK1.CLR = (uint32_t)interrupts; in EPDC_DisableLutCompleteInterrupts()
585 base->IRQ_MASK2.CLR = (uint32_t)(interrupts >> 32U); in EPDC_DisableLutCompleteInterrupts()
621 base->IRQ1.CLR = (uint32_t)statusFlags; in EPDC_ClearLutCompleteStatusFlags()
622 base->IRQ2.CLR = (uint32_t)(statusFlags >> 32U); in EPDC_ClearLutCompleteStatusFlags()
701 base->FIFOCTRL.CLR = EPDC_FIFOCTRL_ENABLE_PRIORITY_MASK; in EPDC_EnableFifoPanic()
Dfsl_epdc.c91 base->CTRL.CLR = (EPDC_CTRL_SFTRST_MASK | EPDC_CTRL_CLKGATE_MASK); in EPDC_ResetToInit()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1181/drivers/
Dfsl_clock.c613 base->CTRL0.CLR = PLL_CTRL0_POWERUP_MASK; in ANATOP_PllSetPower()
625 base->CTRL0.CLR = PLL_CTRL0_BYPASS_MASK; in ANATOP_PllBypass()
637 base->CTRL0.CLR = PLL_CTRL0_PLL_REG_EN_MASK; in ANATOP_PllEnablePllReg()
649 base->CTRL0.CLR = PLL_CTRL0_HOLD_RING_OFF_MASK; in ANATOP_PllHoldRingOff()
668 base->CTRL0.CLR = PLL_CTRL0_ENABLE_MASK; in ANATOP_PllEnableSs()
680 base->CTRL0.CLR = PLL_CTRL0_ENABLE_MASK; in ANATOP_PllEnableClk()
698 base->CTRL0.CLR = PLL_CTRL0_DIV_SELECT_MASK; in ANATOP_PllConfigure()
702 base->CTRL0.CLR = PLL_CTRL0_POST_DIV_SEL_MASK; in ANATOP_PllConfigure()
1140 OSC_RC_400M->CTRL2.CLR = OSC_RC_400M_CTRL2_TUNE_BYP_MASK; in CLOCK_OSC_BypassOscRc400MTuneLogic()
1159 OSC_RC_400M->CTRL2.CLR = OSC_RC_400M_CTRL2_TUNE_START_MASK; in CLOCK_OSC_EnableOscRc400MTuneLogic()
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Dfsl_pmu.c336 VMBANDGAP->CTRL0.CLR = VMBANDGAP_CTRL0_REFTOP_SELFBIASOFF_MASK; in PMU_EnableBandgapSelfBiasBeforePowerDown()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1189/drivers/
Dfsl_clock.c613 base->CTRL0.CLR = PLL_CTRL0_POWERUP_MASK; in ANATOP_PllSetPower()
625 base->CTRL0.CLR = PLL_CTRL0_BYPASS_MASK; in ANATOP_PllBypass()
637 base->CTRL0.CLR = PLL_CTRL0_PLL_REG_EN_MASK; in ANATOP_PllEnablePllReg()
649 base->CTRL0.CLR = PLL_CTRL0_HOLD_RING_OFF_MASK; in ANATOP_PllHoldRingOff()
668 base->CTRL0.CLR = PLL_CTRL0_ENABLE_MASK; in ANATOP_PllEnableSs()
680 base->CTRL0.CLR = PLL_CTRL0_ENABLE_MASK; in ANATOP_PllEnableClk()
698 base->CTRL0.CLR = PLL_CTRL0_DIV_SELECT_MASK; in ANATOP_PllConfigure()
702 base->CTRL0.CLR = PLL_CTRL0_POST_DIV_SEL_MASK; in ANATOP_PllConfigure()
1140 OSC_RC_400M->CTRL2.CLR = OSC_RC_400M_CTRL2_TUNE_BYP_MASK; in CLOCK_OSC_BypassOscRc400MTuneLogic()
1159 OSC_RC_400M->CTRL2.CLR = OSC_RC_400M_CTRL2_TUNE_START_MASK; in CLOCK_OSC_EnableOscRc400MTuneLogic()
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Dfsl_pmu.c336 VMBANDGAP->CTRL0.CLR = VMBANDGAP_CTRL0_REFTOP_SELFBIASOFF_MASK; in PMU_EnableBandgapSelfBiasBeforePowerDown()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1182/drivers/
Dfsl_clock.c613 base->CTRL0.CLR = PLL_CTRL0_POWERUP_MASK; in ANATOP_PllSetPower()
625 base->CTRL0.CLR = PLL_CTRL0_BYPASS_MASK; in ANATOP_PllBypass()
637 base->CTRL0.CLR = PLL_CTRL0_PLL_REG_EN_MASK; in ANATOP_PllEnablePllReg()
649 base->CTRL0.CLR = PLL_CTRL0_HOLD_RING_OFF_MASK; in ANATOP_PllHoldRingOff()
668 base->CTRL0.CLR = PLL_CTRL0_ENABLE_MASK; in ANATOP_PllEnableSs()
680 base->CTRL0.CLR = PLL_CTRL0_ENABLE_MASK; in ANATOP_PllEnableClk()
698 base->CTRL0.CLR = PLL_CTRL0_DIV_SELECT_MASK; in ANATOP_PllConfigure()
702 base->CTRL0.CLR = PLL_CTRL0_POST_DIV_SEL_MASK; in ANATOP_PllConfigure()
1140 OSC_RC_400M->CTRL2.CLR = OSC_RC_400M_CTRL2_TUNE_BYP_MASK; in CLOCK_OSC_BypassOscRc400MTuneLogic()
1159 OSC_RC_400M->CTRL2.CLR = OSC_RC_400M_CTRL2_TUNE_START_MASK; in CLOCK_OSC_EnableOscRc400MTuneLogic()
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Dfsl_pmu.c336 VMBANDGAP->CTRL0.CLR = VMBANDGAP_CTRL0_REFTOP_SELFBIASOFF_MASK; in PMU_EnableBandgapSelfBiasBeforePowerDown()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1187/drivers/
Dfsl_clock.c613 base->CTRL0.CLR = PLL_CTRL0_POWERUP_MASK; in ANATOP_PllSetPower()
625 base->CTRL0.CLR = PLL_CTRL0_BYPASS_MASK; in ANATOP_PllBypass()
637 base->CTRL0.CLR = PLL_CTRL0_PLL_REG_EN_MASK; in ANATOP_PllEnablePllReg()
649 base->CTRL0.CLR = PLL_CTRL0_HOLD_RING_OFF_MASK; in ANATOP_PllHoldRingOff()
668 base->CTRL0.CLR = PLL_CTRL0_ENABLE_MASK; in ANATOP_PllEnableSs()
680 base->CTRL0.CLR = PLL_CTRL0_ENABLE_MASK; in ANATOP_PllEnableClk()
698 base->CTRL0.CLR = PLL_CTRL0_DIV_SELECT_MASK; in ANATOP_PllConfigure()
702 base->CTRL0.CLR = PLL_CTRL0_POST_DIV_SEL_MASK; in ANATOP_PllConfigure()
1140 OSC_RC_400M->CTRL2.CLR = OSC_RC_400M_CTRL2_TUNE_BYP_MASK; in CLOCK_OSC_BypassOscRc400MTuneLogic()
1159 OSC_RC_400M->CTRL2.CLR = OSC_RC_400M_CTRL2_TUNE_START_MASK; in CLOCK_OSC_EnableOscRc400MTuneLogic()
[all …]
Dfsl_pmu.c336 VMBANDGAP->CTRL0.CLR = VMBANDGAP_CTRL0_REFTOP_SELFBIASOFF_MASK; in PMU_EnableBandgapSelfBiasBeforePowerDown()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX9131/drivers/
Dfsl_clock.h73 pll->CTRL.CLR = PLL_CTRL_CLKMUX_EN_MASK | PLL_CTRL_POWERUP_MASK; in CLOCK_PllInit()
77 pll->SPREAD_SPECTRUM.CLR = PLL_SPREAD_SPECTRUM_ENABLE_MASK; in CLOCK_PllInit()
90 pll->CTRL.CLR = PLL_CTRL_CLKMUX_BYPASS_MASK; in CLOCK_PllInit()
107 pll->DFS[pfd_n].DFS_CTRL.CLR = PLL_DFS_CLKOUT_EN_MASK | PLL_DFS_ENABLE_MASK; in CLOCK_PllPfdInit()
123 pll->DFS[pfd_n].DFS_CTRL.CLR = PLL_DFS_BYPASS_EN_MASK; in CLOCK_PllPfdInit()
1201 CCM_CTRL->CLOCK_ROOT[root].CLOCK_ROOT_CONTROL.CLR = CCM_CLOCK_ROOT_OFF_MASK; in CLOCK_PowerOnRootClock()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX9352/drivers/
Dfsl_clock.h73 pll->CTRL.CLR = PLL_CTRL_CLKMUX_EN_MASK | PLL_CTRL_POWERUP_MASK; in CLOCK_PllInit()
77 pll->SPREAD_SPECTRUM.CLR = PLL_SPREAD_SPECTRUM_ENABLE_MASK; in CLOCK_PllInit()
90 pll->CTRL.CLR = PLL_CTRL_CLKMUX_BYPASS_MASK; in CLOCK_PllInit()
107 pll->DFS[pfd_n].DFS_CTRL.CLR = PLL_DFS_CLKOUT_EN_MASK | PLL_DFS_ENABLE_MASK; in CLOCK_PllPfdInit()
123 pll->DFS[pfd_n].DFS_CTRL.CLR = PLL_DFS_BYPASS_EN_MASK; in CLOCK_PllPfdInit()
1201 CCM_CTRL->CLOCK_ROOT[root].CLOCK_ROOT_CONTROL.CLR = CCM_CLOCK_ROOT_OFF_MASK; in CLOCK_PowerOnRootClock()
/hal_nxp-latest/mcux/mcux-sdk/drivers/prg/
Dfsl_prg.h81 base->PRG_CTRL.CLR = PRG_PRG_CTRL_BYPASS_MASK; in PRG_Enable()
107 base->PRG_CTRL.CLR = PRG_PRG_CTRL_SHADOW_EN_MASK; in PRG_EnableShadowLoad()
/hal_nxp-latest/mcux/mcux-sdk/drivers/ci_pi/
Dfsl_ci_pi.c176 …base->CSI_CTRL_REG.CLR = CI_PI_CSR_CSI_CTRL_REG_HSYNC_FORCE_EN_MASK | CI_PI_CSR_CSI_CTRL_REG_VSYNC… in CI_PI_Start()
187 base->CSI_CTRL_REG.CLR = CI_PI_CSR_CSI_CTRL_REG_CSI_EN_MASK; in CI_PI_Stop()
Dfsl_ci_pi.h161 base->CSI_CTRL_REG.CLR = CI_PI_CSR_CSI_CTRL_REG_SOFTRST_MASK; in CI_PI_Reset()
/hal_nxp-latest/mcux/mcux-sdk/drivers/sctimer/
Dfsl_sctimer.c413 bool isHighTrue = (0U != (base->OUT[output].CLR & (1UL << (event + 1U)))); in SCTIMER_UpdatePwmDutycycle()
669 base->OUT[whichIO].CLR |= (1UL << event); in SCTIMER_SetupOutputToggleAction()
Dfsl_sctimer.h913 base->OUT[whichIO].CLR |= (1UL << event); in SCTIMER_SetupOutputClearAction()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT735S/drivers/
Dfsl_clock.c715 base->CSR.CLR = ((base->CSR.RW & FRO_CSR_CLKGATE_MASK) ^ divOutEnable) & FRO_CSR_CLKGATE_MASK; in CLOCK_EnableFroClkOutput()
751 base->CSR.CLR = FRO_CSR_FROEN_MASK | FRO_CSR_TREN_MASK | FRO_CSR_TRUPEN_MASK; in CLOCK_EnableFroAutoTuning()
776 base->CSR.CLR = FRO_CSR_COARSEN_MASK; in CLOCK_EnableFroAutoTuning()
790 base->CSR.CLR = FRO_CSR_TREN_MASK | FRO_CSR_TRUPEN_MASK; in CLOCK_EnableFroAutoTuning()
865 base->CSR.CLR = FRO_CSR_FROEN_MASK | FRO_CSR_TREN_MASK | FRO_CSR_TRUPEN_MASK; in CLOCK_DisableFro()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT798S/drivers/
Dfsl_clock.c715 base->CSR.CLR = ((base->CSR.RW & FRO_CSR_CLKGATE_MASK) ^ divOutEnable) & FRO_CSR_CLKGATE_MASK; in CLOCK_EnableFroClkOutput()
751 base->CSR.CLR = FRO_CSR_FROEN_MASK | FRO_CSR_TREN_MASK | FRO_CSR_TRUPEN_MASK; in CLOCK_EnableFroAutoTuning()
776 base->CSR.CLR = FRO_CSR_COARSEN_MASK; in CLOCK_EnableFroAutoTuning()
790 base->CSR.CLR = FRO_CSR_TREN_MASK | FRO_CSR_TRUPEN_MASK; in CLOCK_EnableFroAutoTuning()
865 base->CSR.CLR = FRO_CSR_FROEN_MASK | FRO_CSR_TREN_MASK | FRO_CSR_TRUPEN_MASK; in CLOCK_DisableFro()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT758S/drivers/
Dfsl_clock.c715 base->CSR.CLR = ((base->CSR.RW & FRO_CSR_CLKGATE_MASK) ^ divOutEnable) & FRO_CSR_CLKGATE_MASK; in CLOCK_EnableFroClkOutput()
751 base->CSR.CLR = FRO_CSR_FROEN_MASK | FRO_CSR_TREN_MASK | FRO_CSR_TRUPEN_MASK; in CLOCK_EnableFroAutoTuning()
776 base->CSR.CLR = FRO_CSR_COARSEN_MASK; in CLOCK_EnableFroAutoTuning()
790 base->CSR.CLR = FRO_CSR_TREN_MASK | FRO_CSR_TRUPEN_MASK; in CLOCK_EnableFroAutoTuning()
865 base->CSR.CLR = FRO_CSR_FROEN_MASK | FRO_CSR_TREN_MASK | FRO_CSR_TRUPEN_MASK; in CLOCK_DisableFro()
/hal_nxp-latest/mcux/mcux-sdk/drivers/lpc_gpio/
Dfsl_gpio.h200 base->CLR[port] = mask; in GPIO_PortClear()
Dfsl_gpio.c114 base->CLR[port] = (1UL << pin); in GPIO_PinInit()
/hal_nxp-latest/mcux/mcux-sdk/boards/mcimx93qsb/
Dboard.c543 CCM_CTRL->GPR_SHARED2.CLR |= CCM_GPR_SHARED2_DRAM_PLL_BYPASS_MASK; in BOARD_DDR_Disable_Bypass()
/hal_nxp-latest/mcux/mcux-sdk/boards/mcimx93evk/
Dboard.c585 CCM_CTRL->GPR_SHARED2.CLR |= CCM_GPR_SHARED2_DRAM_PLL_BYPASS_MASK; in BOARD_DDR_Disable_Bypass()
/hal_nxp-latest/mcux/mcux-sdk/boards/mcimx93autoevk/
Dboard.c556 CCM_CTRL->GPR_SHARED2.CLR |= CCM_GPR_SHARED2_DRAM_PLL_BYPASS_MASK; in BOARD_DDR_Disable_Bypass()

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