Lines Matching refs:CLR
613 base->CTRL0.CLR = PLL_CTRL0_POWERUP_MASK; in ANATOP_PllSetPower()
625 base->CTRL0.CLR = PLL_CTRL0_BYPASS_MASK; in ANATOP_PllBypass()
637 base->CTRL0.CLR = PLL_CTRL0_PLL_REG_EN_MASK; in ANATOP_PllEnablePllReg()
649 base->CTRL0.CLR = PLL_CTRL0_HOLD_RING_OFF_MASK; in ANATOP_PllHoldRingOff()
668 base->CTRL0.CLR = PLL_CTRL0_ENABLE_MASK; in ANATOP_PllEnableSs()
680 base->CTRL0.CLR = PLL_CTRL0_ENABLE_MASK; in ANATOP_PllEnableClk()
698 base->CTRL0.CLR = PLL_CTRL0_DIV_SELECT_MASK; in ANATOP_PllConfigure()
702 base->CTRL0.CLR = PLL_CTRL0_POST_DIV_SEL_MASK; in ANATOP_PllConfigure()
1140 OSC_RC_400M->CTRL2.CLR = OSC_RC_400M_CTRL2_TUNE_BYP_MASK; in CLOCK_OSC_BypassOscRc400MTuneLogic()
1159 OSC_RC_400M->CTRL2.CLR = OSC_RC_400M_CTRL2_TUNE_START_MASK; in CLOCK_OSC_EnableOscRc400MTuneLogic()
1178 OSC_RC_400M->CTRL2.CLR = OSC_RC_400M_CTRL2_TUNE_EN_MASK; in CLOCK_OSC_FreezeOscRc400MTuneValue()
1663 … OSC_RC_400M->CTRL2.CLR = OSC_RC_400M_CTRL2_OSC_TUNE_VAL_MASK | OSC_RC_400M_CTRL2_TUNE_BYP_MASK; in CLOCK_OSC_TrimOscRc400M()