1 /*
2 * Copyright 2025 NXP
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7 #ifndef _FSL_CLOCK_H_
8 #define _FSL_CLOCK_H_
9
10 #include "fsl_common.h"
11
12 /*! @brief CLOCK driver version. */
13 #define FSL_CLOCK_DRIVER_VERSION (MAKE_VERSION(1, 0, 1))
14
15 /*!
16 * @brief CCM reg macros to map corresponding registers.
17 */
18 #define CCM_REG_OFF(root, off) (*((volatile uint32_t *)((uintptr_t)(root) + (off))))
19 #define CCM_REG(root) CCM_REG_OFF(root, 0U)
20
21 /* Definition for delay API in clock driver, users can redefine it to the real application. */
22 #ifndef SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY
23 #define SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY \
24 (250000000UL) /* When using Overdrive Voltage, the maximum frequency of cm33 is 250 MHz */
25 #endif
26
27 /*! LPM_SETTING
28 * 0b000..LPCG will be OFF in any CPU mode.
29 * 0b001..LPCG will be ON in RUN mode, OFF in WAIT/STOP/SUSPEND mode.
30 * 0b010..LPCG will be ON in RUN/WAIT mode, OFF in STOP/SUSPEND mode.
31 * 0b011..LPCG will be ON in RUN/WAIT/STOP mode, OFF in SUSPEND mode.
32 * 0b100..LPCG will be ON in RUN/WAIT/STOP/SUSPEND mode.
33 */
34 #define CCM_LPCG_LPM_SETTING_0 (0U)
35 #define CCM_LPCG_LPM_SETTING_1 (1U)
36 #define CCM_LPCG_LPM_SETTING_2 (2U)
37 #define CCM_LPCG_LPM_SETTING_3 (3U)
38 #define CCM_LPCG_LPM_SETTING_4 (4U)
39
40 /*******************************************************************************
41 * PLL Definitions
42 ******************************************************************************/
43
44 /*! @brief PLL initialzation data. */
45 typedef struct _fracn_pll_init
46 {
47 uint32_t rdiv;
48 uint32_t mfi;
49 uint32_t mfn;
50 uint32_t mfd;
51 uint32_t odiv;
52 } fracn_pll_init_t;
53
54 /*! @brief PLL PFD initialzation data. */
55 typedef struct _fracn_pll_pfd_init
56 {
57 uint32_t mfi;
58 uint32_t mfn;
59 bool div2_en;
60 } fracn_pll_pfd_init_t;
61
62 /*!
63 * @brief PLL init.
64 *
65 * @param pll PLL base addr.
66 * @param pll_cfg PLL initailization data.
67 */
CLOCK_PllInit(PLL_Type * pll,const fracn_pll_init_t * pll_cfg)68 static inline void CLOCK_PllInit(PLL_Type *pll, const fracn_pll_init_t *pll_cfg)
69 {
70 /* Bypass PLL */
71 pll->CTRL.SET = PLL_CTRL_CLKMUX_BYPASS_MASK;
72 /* Disable output and PLL */
73 pll->CTRL.CLR = PLL_CTRL_CLKMUX_EN_MASK | PLL_CTRL_POWERUP_MASK;
74 /* Set rdiv, mfi, and odiv */
75 pll->DIV.RW = PLL_DIV_RDIV(pll_cfg->rdiv) | PLL_DIV_MFI(pll_cfg->mfi) | PLL_DIV_ODIV(pll_cfg->odiv);
76 /* Disable spread spectrum modulation */
77 pll->SPREAD_SPECTRUM.CLR = PLL_SPREAD_SPECTRUM_ENABLE_MASK;
78 /* Set mfn and mfd */
79 pll->NUMERATOR.RW = PLL_NUMERATOR_MFN(pll_cfg->mfn);
80 pll->DENOMINATOR.RW = PLL_DENOMINATOR_MFD(pll_cfg->mfd);
81
82 /* Power up for locking */
83 pll->CTRL.SET = PLL_CTRL_POWERUP_MASK;
84 while ((pll->PLL_STATUS & PLL_PLL_STATUS_PLL_LOCK_MASK) == 0UL)
85 {
86 }
87
88 /* Enable PLL and clean bypass*/
89 pll->CTRL.SET = PLL_CTRL_CLKMUX_EN_MASK;
90 pll->CTRL.CLR = PLL_CTRL_CLKMUX_BYPASS_MASK;
91 __DSB();
92 __ISB();
93 }
94
95 /*!
96 * @brief PLL PFD init.
97 *
98 * @param pll PLL base addr.
99 * @param pfd_n The PFD index number.
100 * @param pfd_cfg PLL PFD initailization data.
101 */
CLOCK_PllPfdInit(PLL_Type * pll,uint32_t pfd_n,const fracn_pll_pfd_init_t * pfd_cfg)102 static inline void CLOCK_PllPfdInit(PLL_Type *pll, uint32_t pfd_n, const fracn_pll_pfd_init_t *pfd_cfg)
103 {
104 /* Bypass DFS*/
105 pll->DFS[pfd_n].DFS_CTRL.SET = PLL_DFS_BYPASS_EN_MASK;
106 /* Disable output and DFS */
107 pll->DFS[pfd_n].DFS_CTRL.CLR = PLL_DFS_CLKOUT_EN_MASK | PLL_DFS_ENABLE_MASK;
108 /* Set mfi and mfn */
109 pll->DFS[pfd_n].DFS_DIV.RW = PLL_DFS_MFI(pfd_cfg->mfi) | PLL_DFS_MFN(pfd_cfg->mfn);
110 /* Enable output and DFS*/
111 pll->DFS[pfd_n].DFS_CTRL.SET = PLL_DFS_CLKOUT_EN_MASK;
112 /* Enable div2 */
113 if (pfd_cfg->div2_en)
114 {
115 pll->DFS[pfd_n].DFS_CTRL.SET = PLL_DFS_CLKOUT_DIVBY2_EN_MASK;
116 }
117 /* Enable DFS for locking*/
118 pll->DFS[pfd_n].DFS_CTRL.SET = PLL_DFS_ENABLE_MASK;
119 while (((pll->DFS_STATUS & PLL_DFS_STATUS_DFS_OK_MASK) & (1UL << pfd_n)) == 0UL)
120 {
121 }
122 /* Clean bypass */
123 pll->DFS[pfd_n].DFS_CTRL.CLR = PLL_DFS_BYPASS_EN_MASK;
124 __DSB();
125 __ISB();
126 }
127
128 /*******************************************************************************
129 * Clock Source Definitions
130 ******************************************************************************/
131
132 /*!
133 * @brief Clock name.
134 */
135 typedef enum _clock_name
136 {
137 kCLOCK_Osc24M = 0, /*!< 24MHz Oscillator. */
138 kCLOCK_ArmPll = 1, /* ARM PLL */
139 kCLOCK_ArmPllOut = 2, /* ARM PLL Out */
140 kCLOCK_DramPll = 3, /* DRAM PLL */
141 kCLOCK_DramPllOut = 4, /* DRAM PLL Out */
142 kCLOCK_SysPll1 = 5, /* SYSTEM PLL1 */
143 kCLOCK_SysPll1Pfd0 = 6, /* SYSTEM PLL1 PFD0 */
144 kCLOCK_SysPll1Pfd0Div2 = 7, /* SYSTEM PLL1 PFD0 DIV2 */
145 kCLOCK_SysPll1Pfd1 = 8, /* SYSTEM PLL1 PFD1 */
146 kCLOCK_SysPll1Pfd1Div2 = 9, /* SYSTEM PLL1 PFD1 DIV2 */
147 kCLOCK_SysPll1Pfd2 = 10, /* SYSTEM PLL1 PFD2 */
148 kCLOCK_SysPll1Pfd2Div2 = 11, /* SYSTEM PLL1 PFD2 DIV2 */
149 kCLOCK_AudioPll1 = 12, /* AUDIO PLL1 */
150 kCLOCK_AudioPll1Out = 13, /* AUDIO PLL1 Out */
151 kCLOCK_VideoPll1 = 14, /* VEDIO PLL1 */
152 kCLOCK_VideoPll1Out = 15, /* VEDIO PLL1 Out */
153 kCLOCK_Ext = 16, /* Ext */
154 } clock_name_t;
155
156 extern const clock_name_t s_clockSourceName[][4];
157 /*******************************************************************************
158 * Clock Root Definitions
159 ******************************************************************************/
160
161 /*! @brief Clock root configuration */
162 typedef struct _clock_root_config_t
163 {
164 bool clockOff;
165 uint8_t mux; /*!< See #clock_root_mux_source_t for details. */
166 uint8_t div; /*!< it's the actual divider */
167 } clock_root_config_t;
168
169 /*!
170 * @brief Root clock index
171 */
172 typedef enum _clock_root
173 {
174 kCLOCK_Root_A55Periph = 0, /*!< CLOCK Root Arm A55 Periph. */
175 kCLOCK_Root_A55MtrBus = 1, /*!< CLOCK Root Arm A55 MTR BUS. */
176 kCLOCK_Root_A55 = 2, /*!< CLOCK Root Arm A55. */
177 kCLOCK_Root_M33 = 3, /*!< CLOCK Root M33. */
178 kCLOCK_Root_Sentinel = 4, /*!< CLOCK Root Sentinel. */
179 kCLOCK_Root_BusWakeup = 5, /*!< CLOCK Root Bus Wakeup. */
180 kCLOCK_Root_BusAon = 6, /*!< CLOCK Root Bus Aon. */
181 kCLOCK_Root_WakeupAxi = 7, /*!< CLOCK Root Wakeup Axi. */
182 kCLOCK_Root_SwoTrace = 8, /*!< CLOCK Root Swo Trace. */
183 kCLOCK_Root_M33Systick = 9, /*!< CLOCK Root M33 Systick. */
184 kCLOCK_Root_Flexio1 = 10, /*!< CLOCK Root Flexio1. */
185 kCLOCK_Root_Flexio2 = 11, /*!< CLOCK Root Flexio2. */
186 kCLOCK_Root_Lpit1 = 12, /*!< CLOCK Root Lpit1. */
187 kCLOCK_Root_Lpit2 = 13, /*!< CLOCK Root Lpit2. */
188 kCLOCK_Root_Lptmr1 = 14, /*!< CLOCK Root Lptmr1. */
189 kCLOCK_Root_Lptmr2 = 15, /*!< CLOCK Root Lptmr2. */
190 kCLOCK_Root_Tpm1 = 16, /*!< CLOCK Root Tpm1. */
191 kCLOCK_Root_Tpm2 = 17, /*!< CLOCK Root Tpm2. */
192 kCLOCK_Root_Tpm3 = 18, /*!< CLOCK Root Tpm3. */
193 kCLOCK_Root_Tpm4 = 19, /*!< CLOCK Root Tpm4. */
194 kCLOCK_Root_Tpm5 = 20, /*!< CLOCK Root Tpm5. */
195 kCLOCK_Root_Tpm6 = 21, /*!< CLOCK Root Tpm6. */
196 kCLOCK_Root_Flexspi1 = 22, /*!< CLOCK Root Flexspi1. */
197 kCLOCK_Root_Can1 = 23, /*!< CLOCK Root Can1. */
198 kCLOCK_Root_Can2 = 24, /*!< CLOCK Root Can2. */
199 kCLOCK_Root_Lpuart1 = 25, /*!< CLOCK Root Lpuart1. */
200 kCLOCK_Root_Lpuart2 = 26, /*!< CLOCK Root Lpuart2. */
201 kCLOCK_Root_Lpuart3 = 27, /*!< CLOCK Root Lpuart3. */
202 kCLOCK_Root_Lpuart4 = 28, /*!< CLOCK Root Lpuart4. */
203 kCLOCK_Root_Lpuart5 = 29, /*!< CLOCK Root Lpuart5. */
204 kCLOCK_Root_Lpuart6 = 30, /*!< CLOCK Root Lpuart6. */
205 kCLOCK_Root_Lpuart7 = 31, /*!< CLOCK Root Lpuart7. */
206 kCLOCK_Root_Lpuart8 = 32, /*!< CLOCK Root Lpuart8. */
207 kCLOCK_Root_Lpi2c1 = 33, /*!< CLOCK Root Lpi2c1. */
208 kCLOCK_Root_Lpi2c2 = 34, /*!< CLOCK Root Lpi2c2. */
209 kCLOCK_Root_Lpi2c3 = 35, /*!< CLOCK Root Lpi2c3. */
210 kCLOCK_Root_Lpi2c4 = 36, /*!< CLOCK Root Lpi2c4. */
211 kCLOCK_Root_Lpi2c5 = 37, /*!< CLOCK Root Lpi2c5. */
212 kCLOCK_Root_Lpi2c6 = 38, /*!< CLOCK Root Lpi2c6. */
213 kCLOCK_Root_Lpi2c7 = 39, /*!< CLOCK Root Lpi2c7. */
214 kCLOCK_Root_Lpi2c8 = 40, /*!< CLOCK Root Lpi2c8. */
215 kCLOCK_Root_Lpspi1 = 41, /*!< CLOCK Root Lpspi1. */
216 kCLOCK_Root_Lpspi2 = 42, /*!< CLOCK Root Lpspi2. */
217 kCLOCK_Root_Lpspi3 = 43, /*!< CLOCK Root Lpspi3. */
218 kCLOCK_Root_Lpspi4 = 44, /*!< CLOCK Root Lpspi4. */
219 kCLOCK_Root_Lpspi5 = 45, /*!< CLOCK Root Lpspi5. */
220 kCLOCK_Root_Lpspi6 = 46, /*!< CLOCK Root Lpspi6. */
221 kCLOCK_Root_Lpspi7 = 47, /*!< CLOCK Root Lpspi7. */
222 kCLOCK_Root_Lpspi8 = 48, /*!< CLOCK Root Lpspi8. */
223 kCLOCK_Root_I3c1 = 49, /*!< CLOCK Root I3c1. */
224 kCLOCK_Root_I3c2 = 50, /*!< CLOCK Root I3c2. */
225 kCLOCK_Root_Usdhc1 = 51, /*!< CLOCK Root Usdhc1. */
226 kCLOCK_Root_Usdhc2 = 52, /*!< CLOCK Root Usdhc2. */
227 kCLOCK_Root_Usdhc3 = 53, /*!< CLOCK Root Usdhc3. */
228 kCLOCK_Root_Sai1 = 54, /*!< CLOCK Root Sai1. */
229 kCLOCK_Root_Sai2 = 55, /*!< CLOCK Root Sai2. */
230 kCLOCK_Root_Sai3 = 56, /*!< CLOCK Root Sai3. */
231 kCLOCK_Root_CcmCko1 = 57, /*!< CLOCK Root Ccm Cko1. */
232 kCLOCK_Root_CcmCko2 = 58, /*!< CLOCK Root Ccm Cko2. */
233 kCLOCK_Root_CcmCko3 = 59, /*!< CLOCK Root Ccm Cko3. */
234 kCLOCK_Root_CcmCko4 = 60, /*!< CLOCK Root Ccm Cko4. */
235 kCLOCK_Root_Hsio = 61, /*!< CLOCK Root Hsio. */
236 kCLOCK_Root_HsioUsbTest60M = 62, /*!< CLOCK Root Hsio Usb Test 60M. */
237 kCLOCK_Root_HsioAcscan80M = 63, /*!< CLOCK Root Hsio Acscan 80M. */
238 kCLOCK_Root_HsioAcscan480M = 64, /*!< CLOCK Root Hsio Acscan 480M. */
239 kCLOCK_Root_Nic = 65, /*!< CLOCK Root Nic. */
240 kCLOCK_Root_NicApb = 66, /*!< CLOCK Root Nic Apb. */
241 kCLOCK_Root_MlApb = 67, /*!< CLOCK Root Ml Apb. */
242 kCLOCK_Root_Ml = 68, /*!< CLOCK Root Ml. */
243 kCLOCK_Root_MediaAxi = 69, /*!< CLOCK Root Media Axi. */
244 kCLOCK_Root_MediaApb = 70, /*!< CLOCK Root Media Apb. */
245 kCLOCK_Root_MediaLdb = 71, /*!< CLOCK Root Media Ldb. */
246 kCLOCK_Root_MediaDispPix = 72, /*!< CLOCK Root Media Disp Pix. */
247 kCLOCK_Root_CamPix = 73, /*!< CLOCK Root Cam Pix. */
248 kCLOCK_Root_MipiTestByte = 74, /*!< CLOCK Root Mipi Test Byte. */
249 kCLOCK_Root_MipiPhyCfg = 75, /*!< CLOCK Root Mipi Phy Cfg. */
250 kCLOCK_Root_DramAlt = 76, /*!< CLOCK Root Dram Alt. */
251 kCLOCK_Root_DramApb = 77, /*!< CLOCK Root Dram Apb. */
252 kCLOCK_Root_Adc = 78, /*!< CLOCK Root Adc. */
253 kCLOCK_Root_Pdm = 79, /*!< CLOCK Root Pdm. */
254 kCLOCK_Root_Tstmr1 = 80, /*!< CLOCK Root Tstmr1. */
255 kCLOCK_Root_Tstmr2 = 81, /*!< CLOCK Root Tstmr2. */
256 kCLOCK_Root_Mqs1 = 82, /*!< CLOCK Root MQS1. */
257 kCLOCK_Root_Mqs2 = 83, /*!< CLOCK Root MQS2. */
258 kCLOCK_Root_AudioXCVR = 84, /*!< CLOCK Root Audio XCVR. */
259 kCLOCK_Root_Spdif = 85, /*!< CLOCK Root Spdif. */
260 kCLOCK_Root_Enet = 86, /*!< CLOCK Root Enet. */
261 kCLOCK_Root_EnetTimer1 = 87, /*!< CLOCK Root Enet Timer1. */
262 kCLOCK_Root_EnetTimer2 = 88, /*!< CLOCK Root Enet Timer2. */
263 kCLOCK_Root_EnetRef = 89, /*!< CLOCK Root Enet Ref. */
264 kCLOCK_Root_EnetRefPhy = 90, /*!< CLOCK Root Enet Ref Phy. */
265 kCLOCK_Root_I3c1Slow = 91, /*!< CLOCK Root I3c1Slow. */
266 kCLOCK_Root_I3c2Slow = 92, /*!< CLOCK Root I3c2Slow. */
267 kCLOCK_Root_UsbPhyBurunin = 93, /*!< CLOCK Root Usb Phy Burunin. */
268 kCLOCK_Root_PalCameScan = 94, /*!< CLOCK Root Pal Came Scan. */
269 } clock_root_t;
270
271 /*!
272 * @brief The enumerator of clock roots' clock source mux value.
273 */
274 typedef enum _clock_root_mux_source
275 {
276 /* ARM A55 Periph */
277 kCLOCK_A55PERIPH_ClockRoot_MuxOsc24M = 0U,
278 kCLOCK_A55PERIPH_ClockRoot_MuxSysPll1Pfd0 = 1U,
279 kCLOCK_A55PERIPH_ClockRoot_MuxSysPll1Pfd1 = 2U,
280 kCLOCK_A55PERIPH_ClockRoot_MuxSysPll1Pfd2 = 3U,
281
282 /* ARM A55 MTR BUS */
283 kCLOCK_A55MTRBUS_ClockRoot_MuxOsc24M = 0U,
284 kCLOCK_A55MTRBUS_ClockRoot_MuxSysPll1Pfd0Div2 = 1U,
285 kCLOCK_A55MTRBUS_ClockRoot_MuxSysPll1Pfd1Div2 = 2U,
286 kCLOCK_A55MTRBUS_ClockRoot_MuxVideoPll1Out = 3U,
287
288 /* ARM A55 */
289 kCLOCK_A55_ClockRoot_MuxOsc24M = 0U,
290 kCLOCK_A55_ClockRoot_MuxSysPll1Pfd0 = 1U,
291 kCLOCK_A55_ClockRoot_MuxSysPll1Pfd1 = 2U,
292 kCLOCK_A55_ClockRoot_MuxSysPll1Pfd2 = 3U,
293
294 /* M33 */
295 kCLOCK_M33_ClockRoot_MuxOsc24M = 0U,
296 kCLOCK_M33_ClockRoot_MuxSysPll1Pfd0Div2 = 1U,
297 kCLOCK_M33_ClockRoot_MuxSysPll1Pfd1Div2 = 2U,
298 kCLOCK_M33_ClockRoot_MuxVideoPll1Out = 3U,
299
300 /* Sentinel */
301 kCLOCK_SENTINEL_ClockRoot_MuxOsc24M = 0U,
302 kCLOCK_SENTINEL_ClockRoot_MuxSysPll1Pfd0Div2 = 1U,
303 kCLOCK_SENTINEL_ClockRoot_MuxSysPll1Pfd1Div2 = 2U,
304 kCLOCK_SENTINEL_ClockRoot_MuxVideoPll1Out = 3U,
305
306 /* Bus Wakeup */
307 kCLOCK_BUSWAKEUP_ClockRoot_MuxOsc24M = 0U,
308 kCLOCK_BUSWAKEUP_ClockRoot_MuxSysPll1Pfd0Div2 = 1U,
309 kCLOCK_BUSWAKEUP_ClockRoot_MuxSysPll1Pfd1Div2 = 2U,
310 kCLOCK_BUSWAKEUP_ClockRoot_MuxVideoPll1Out = 3U,
311
312 /* Bus Aon */
313 kCLOCK_BUSAON_ClockRoot_MuxOsc24M = 0U,
314 kCLOCK_BUSAON_ClockRoot_MuxSysPll1Pfd0Div2 = 1U,
315 kCLOCK_BUSAON_ClockRoot_MuxSysPll1Pfd1Div2 = 2U,
316 kCLOCK_BUSAON_ClockRoot_MuxVideoPll1Out = 3U,
317
318 /* Wakeup Axi */
319 kCLOCK_WAKEUPAXI_ClockRoot_MuxOsc24M = 0U,
320 kCLOCK_WAKEUPAXI_ClockRoot_MuxSysPll1Pfd0 = 1U,
321 kCLOCK_WAKEUPAXI_ClockRoot_MuxSysPll1Pfd1 = 2U,
322 kCLOCK_WAKEUPAXI_ClockRoot_MuxSysPll1Pfd2 = 3U,
323
324 /* Swo Trace */
325 kCLOCK_SWOTRACE_ClockRoot_MuxOsc24M = 0U,
326 kCLOCK_SWOTRACE_ClockRoot_MuxSysPll1Pfd0Div2 = 1U,
327 kCLOCK_SWOTRACE_ClockRoot_MuxSysPll1Pfd1Div2 = 2U,
328 kCLOCK_SWOTRACE_ClockRoot_MuxVideoPll1Out = 3U,
329
330 /* M33 Systick */
331 kCLOCK_M33SYSTICK_ClockRoot_MuxOsc24M = 0U,
332 kCLOCK_M33SYSTICK_ClockRoot_MuxSysPll1Pfd0Div2 = 1U,
333 kCLOCK_M33SYSTICK_ClockRoot_MuxSysPll1Pfd1Div2 = 2U,
334 kCLOCK_M33SYSTICK_ClockRoot_MuxVideoPll1Out = 3U,
335
336 /* Flexio1 */
337 kCLOCK_FLEXIO1_ClockRoot_MuxOsc24M = 0U,
338 kCLOCK_FLEXIO1_ClockRoot_MuxSysPll1Pfd0Div2 = 1U,
339 kCLOCK_FLEXIO1_ClockRoot_MuxSysPll1Pfd1Div2 = 2U,
340 kCLOCK_FLEXIO1_ClockRoot_MuxVideoPll1Out = 3U,
341
342 /* Flexio2 */
343 kCLOCK_FLEXIO2_ClockRoot_MuxOsc24M = 0U,
344 kCLOCK_FLEXIO2_ClockRoot_MuxSysPll1Pfd0Div2 = 1U,
345 kCLOCK_FLEXIO2_ClockRoot_MuxSysPll1Pfd1Div2 = 2U,
346 kCLOCK_FLEXIO2_ClockRoot_MuxVideoPll1Out = 3U,
347
348 /* Lpit1 */
349 kCLOCK_LPIT1_ClockRoot_MuxOsc24M = 0U,
350 kCLOCK_LPIT1_ClockRoot_MuxSysPll1Pfd0Div2 = 1U,
351 kCLOCK_LPIT1_ClockRoot_MuxSysPll1Pfd1Div2 = 2U,
352 kCLOCK_LPIT1_ClockRoot_MuxVideoPll1Out = 3U,
353
354 /* Lpit2 */
355 kCLOCK_LPIT2_ClockRoot_MuxOsc24M = 0U,
356 kCLOCK_LPIT2_ClockRoot_MuxSysPll1Pfd0Div2 = 1U,
357 kCLOCK_LPIT2_ClockRoot_MuxSysPll1Pfd1Div2 = 2U,
358 kCLOCK_LPIT2_ClockRoot_MuxVideoPll1Out = 3U,
359
360 /* Lptmr1 */
361 kCLOCK_LPTMR1_ClockRoot_MuxOsc24M = 0U,
362 kCLOCK_LPTMR1_ClockRoot_MuxSysPll1Pfd0Div2 = 1U,
363 kCLOCK_LPTMR1_ClockRoot_MuxSysPll1Pfd1Div2 = 2U,
364 kCLOCK_LPTMR1_ClockRoot_MuxVideoPll1Out = 3U,
365
366 /* Lptmr2 */
367 kCLOCK_LPTMR2_ClockRoot_MuxOsc24M = 0U,
368 kCLOCK_LPTMR2_ClockRoot_MuxSysPll1Pfd0Div2 = 1U,
369 kCLOCK_LPTMR2_ClockRoot_MuxSysPll1Pfd1Div2 = 2U,
370 kCLOCK_LPTMR2_ClockRoot_MuxVideoPll1Out = 3U,
371
372 /* Tpm1 */
373 kCLOCK_TPM1_ClockRoot_MuxOsc24M = 0U,
374 kCLOCK_TPM1_ClockRoot_MuxSysPll1Pfd0 = 1U,
375 kCLOCK_TPM1_ClockRoot_MuxAudioPll1Out = 2U,
376 kCLOCK_TPM1_ClockRoot_MuxExt = 3U,
377
378 /* Tpm2 */
379 kCLOCK_TPM2_ClockRoot_MuxOsc24M = 0U,
380 kCLOCK_TPM2_ClockRoot_MuxSysPll1Pfd0 = 1U,
381 kCLOCK_TPM2_ClockRoot_MuxAudioPll1Out = 2U,
382 kCLOCK_TPM2_ClockRoot_MuxExt = 3U,
383
384 /* Tpm3 */
385 kCLOCK_TPM3_ClockRoot_MuxOsc24M = 0U,
386 kCLOCK_TPM3_ClockRoot_MuxSysPll1Pfd0 = 1U,
387 kCLOCK_TPM3_ClockRoot_MuxAudioPll1Out = 2U,
388 kCLOCK_TPM3_ClockRoot_MuxExt = 3U,
389
390 /* Tpm4 */
391 kCLOCK_TPM4_ClockRoot_MuxOsc24M = 0U,
392 kCLOCK_TPM4_ClockRoot_MuxSysPll1Pfd0 = 1U,
393 kCLOCK_TPM4_ClockRoot_MuxAudioPll1Out = 2U,
394 kCLOCK_TPM4_ClockRoot_MuxExt = 3U,
395
396 /* Tpm5 */
397 kCLOCK_TPM5_ClockRoot_MuxOsc24M = 0U,
398 kCLOCK_TPM5_ClockRoot_MuxSysPll1Pfd0 = 1U,
399 kCLOCK_TPM5_ClockRoot_MuxAudioPll1Out = 2U,
400 kCLOCK_TPM5_ClockRoot_MuxExt = 3U,
401
402 /* Tpm6 */
403 kCLOCK_TPM6_ClockRoot_MuxOsc24M = 0U,
404 kCLOCK_TPM6_ClockRoot_MuxSysPll1Pfd0 = 1U,
405 kCLOCK_TPM6_ClockRoot_MuxAudioPll1Out = 2U,
406 kCLOCK_TPM6_ClockRoot_MuxExt = 3U,
407
408 /* Flexspi1 */
409 kCLOCK_FLEXSPI1_ClockRoot_MuxOsc24M = 0U,
410 kCLOCK_FLEXSPI1_ClockRoot_MuxSysPll1Pfd0 = 1U,
411 kCLOCK_FLEXSPI1_ClockRoot_MuxSysPll1Pfd1 = 2U,
412 kCLOCK_FLEXSPI1_ClockRoot_MuxSysPll1Pfd2 = 3U,
413
414 /* Can1 */
415 kCLOCK_CAN1_ClockRoot_MuxOsc24M = 0U,
416 kCLOCK_CAN1_ClockRoot_MuxSysPll1Pfd0Div2 = 1U,
417 kCLOCK_CAN1_ClockRoot_MuxSysPll1Pfd1Div2 = 2U,
418 kCLOCK_CAN1_ClockRoot_MuxVideoPll1Out = 3U,
419
420 /* Can2 */
421 kCLOCK_CAN2_ClockRoot_MuxOsc24M = 0U,
422 kCLOCK_CAN2_ClockRoot_MuxSysPll1Pfd0Div2 = 1U,
423 kCLOCK_CAN2_ClockRoot_MuxSysPll1Pfd1Div2 = 2U,
424 kCLOCK_CAN2_ClockRoot_MuxVideoPll1Out = 3U,
425
426 /* Lpuart1 */
427 kCLOCK_LPUART1_ClockRoot_MuxOsc24M = 0U,
428 kCLOCK_LPUART1_ClockRoot_MuxSysPll1Pfd0Div2 = 1U,
429 kCLOCK_LPUART1_ClockRoot_MuxSysPll1Pfd1Div2 = 2U,
430 kCLOCK_LPUART1_ClockRoot_MuxVideoPll1Out = 3U,
431
432 /* Lpuart2 */
433 kCLOCK_LPUART2_ClockRoot_MuxOsc24M = 0U,
434 kCLOCK_LPUART2_ClockRoot_MuxSysPll1Pfd0Div2 = 1U,
435 kCLOCK_LPUART2_ClockRoot_MuxSysPll1Pfd1Div2 = 2U,
436 kCLOCK_LPUART2_ClockRoot_MuxVideoPll1Out = 3U,
437
438 /* Lpuart3 */
439 kCLOCK_LPUART3_ClockRoot_MuxOsc24M = 0U,
440 kCLOCK_LPUART3_ClockRoot_MuxSysPll1Pfd0Div2 = 1U,
441 kCLOCK_LPUART3_ClockRoot_MuxSysPll1Pfd1Div2 = 2U,
442 kCLOCK_LPUART3_ClockRoot_MuxVideoPll1Out = 3U,
443
444 /* Lpuart4 */
445 kCLOCK_LPUART4_ClockRoot_MuxOsc24M = 0U,
446 kCLOCK_LPUART4_ClockRoot_MuxSysPll1Pfd0Div2 = 1U,
447 kCLOCK_LPUART4_ClockRoot_MuxSysPll1Pfd1Div2 = 2U,
448 kCLOCK_LPUART4_ClockRoot_MuxVideoPll1Out = 3U,
449
450 /* Lpuart5 */
451 kCLOCK_LPUART5_ClockRoot_MuxOsc24M = 0U,
452 kCLOCK_LPUART5_ClockRoot_MuxSysPll1Pfd0Div2 = 1U,
453 kCLOCK_LPUART5_ClockRoot_MuxSysPll1Pfd1Div2 = 2U,
454 kCLOCK_LPUART5_ClockRoot_MuxVideoPll1Out = 3U,
455
456 /* Lpuart6 */
457 kCLOCK_LPUART6_ClockRoot_MuxOsc24M = 0U,
458 kCLOCK_LPUART6_ClockRoot_MuxSysPll1Pfd0Div2 = 1U,
459 kCLOCK_LPUART6_ClockRoot_MuxSysPll1Pfd1Div2 = 2U,
460 kCLOCK_LPUART6_ClockRoot_MuxVideoPll1Out = 3U,
461
462 /* Lpuart7 */
463 kCLOCK_LPUART7_ClockRoot_MuxOsc24M = 0U,
464 kCLOCK_LPUART7_ClockRoot_MuxSysPll1Pfd0Div2 = 1U,
465 kCLOCK_LPUART7_ClockRoot_MuxSysPll1Pfd1Div2 = 2U,
466 kCLOCK_LPUART7_ClockRoot_MuxVideoPll1Out = 3U,
467
468 /* Lpuart8 */
469 kCLOCK_LPUART8_ClockRoot_MuxOsc24M = 0U,
470 kCLOCK_LPUART8_ClockRoot_MuxSysPll1Pfd0Div2 = 1U,
471 kCLOCK_LPUART8_ClockRoot_MuxSysPll1Pfd1Div2 = 2U,
472 kCLOCK_LPUART8_ClockRoot_MuxVideoPll1Out = 3U,
473
474 /* Lpi2c1 */
475 kCLOCK_LPI2C1_ClockRoot_MuxOsc24M = 0U,
476 kCLOCK_LPI2C1_ClockRoot_MuxSysPll1Pfd0Div2 = 1U,
477 kCLOCK_LPI2C1_ClockRoot_MuxSysPll1Pfd1Div2 = 2U,
478 kCLOCK_LPI2C1_ClockRoot_MuxVideoPll1Out = 3U,
479
480 /* Lpi2c2 */
481 kCLOCK_LPI2C2_ClockRoot_MuxOsc24M = 0U,
482 kCLOCK_LPI2C2_ClockRoot_MuxSysPll1Pfd0Div2 = 1U,
483 kCLOCK_LPI2C2_ClockRoot_MuxSysPll1Pfd1Div2 = 2U,
484 kCLOCK_LPI2C2_ClockRoot_MuxVideoPll1Out = 3U,
485
486 /* Lpi2c3 */
487 kCLOCK_LPI2C3_ClockRoot_MuxOsc24M = 0U,
488 kCLOCK_LPI2C3_ClockRoot_MuxSysPll1Pfd0Div2 = 1U,
489 kCLOCK_LPI2C3_ClockRoot_MuxSysPll1Pfd1Div2 = 2U,
490 kCLOCK_LPI2C3_ClockRoot_MuxVideoPll1Out = 3U,
491
492 /* Lpi2c4 */
493 kCLOCK_LPI2C4_ClockRoot_MuxOsc24M = 0U,
494 kCLOCK_LPI2C4_ClockRoot_MuxSysPll1Pfd0Div2 = 1U,
495 kCLOCK_LPI2C4_ClockRoot_MuxSysPll1Pfd1Div2 = 2U,
496 kCLOCK_LPI2C4_ClockRoot_MuxVideoPll1Out = 3U,
497
498 /* Lpi2c5 */
499 kCLOCK_LPI2C5_ClockRoot_MuxOsc24M = 0U,
500 kCLOCK_LPI2C5_ClockRoot_MuxSysPll1Pfd0Div2 = 1U,
501 kCLOCK_LPI2C5_ClockRoot_MuxSysPll1Pfd1Div2 = 2U,
502 kCLOCK_LPI2C5_ClockRoot_MuxVideoPll1Out = 3U,
503
504 /* Lpi2c6 */
505 kCLOCK_LPI2C6_ClockRoot_MuxOsc24M = 0U,
506 kCLOCK_LPI2C6_ClockRoot_MuxSysPll1Pfd0Div2 = 1U,
507 kCLOCK_LPI2C6_ClockRoot_MuxSysPll1Pfd1Div2 = 2U,
508 kCLOCK_LPI2C6_ClockRoot_MuxVideoPll1Out = 3U,
509
510 /* Lpi2c7 */
511 kCLOCK_LPI2C7_ClockRoot_MuxOsc24M = 0U,
512 kCLOCK_LPI2C7_ClockRoot_MuxSysPll1Pfd0Div2 = 1U,
513 kCLOCK_LPI2C7_ClockRoot_MuxSysPll1Pfd1Div2 = 2U,
514 kCLOCK_LPI2C7_ClockRoot_MuxVideoPll1Out = 3U,
515
516 /* Lpi2c8 */
517 kCLOCK_LPI2C8_ClockRoot_MuxOsc24M = 0U,
518 kCLOCK_LPI2C8_ClockRoot_MuxSysPll1Pfd0Div2 = 1U,
519 kCLOCK_LPI2C8_ClockRoot_MuxSysPll1Pfd1Div2 = 2U,
520 kCLOCK_LPI2C8_ClockRoot_MuxVideoPll1Out = 3U,
521
522 /* Lpspi1 */
523 kCLOCK_LPSPI1_ClockRoot_MuxOsc24M = 0U,
524 kCLOCK_LPSPI1_ClockRoot_MuxSysPll1Pfd0Div2 = 1U,
525 kCLOCK_LPSPI1_ClockRoot_MuxSysPll1Pfd1Div2 = 2U,
526 kCLOCK_LPSPI1_ClockRoot_MuxVideoPll1Out = 3U,
527
528 /* Lpspi2 */
529 kCLOCK_LPSPI2_ClockRoot_MuxOsc24M = 0U,
530 kCLOCK_LPSPI2_ClockRoot_MuxSysPll1Pfd0Div2 = 1U,
531 kCLOCK_LPSPI2_ClockRoot_MuxSysPll1Pfd1Div2 = 2U,
532 kCLOCK_LPSPI2_ClockRoot_MuxVideoPll1Out = 3U,
533
534 /* Lpspi3 */
535 kCLOCK_LPSPI3_ClockRoot_MuxOsc24M = 0U,
536 kCLOCK_LPSPI3_ClockRoot_MuxSysPll1Pfd0Div2 = 1U,
537 kCLOCK_LPSPI3_ClockRoot_MuxSysPll1Pfd1Div2 = 2U,
538 kCLOCK_LPSPI3_ClockRoot_MuxVideoPll1Out = 3U,
539
540 /* Lpspi4 */
541 kCLOCK_LPSPI4_ClockRoot_MuxOsc24M = 0U,
542 kCLOCK_LPSPI4_ClockRoot_MuxSysPll1Pfd0Div2 = 1U,
543 kCLOCK_LPSPI4_ClockRoot_MuxSysPll1Pfd1Div2 = 2U,
544 kCLOCK_LPSPI4_ClockRoot_MuxVideoPll1Out = 3U,
545
546 /* Lpispi5 */
547 kCLOCK_LPSPI5_ClockRoot_MuxOsc24M = 0U,
548 kCLOCK_LPSPI5_ClockRoot_MuxSysPll1Pfd0Div2 = 1U,
549 kCLOCK_LPSPI5_ClockRoot_MuxSysPll1Pfd1Div2 = 2U,
550 kCLOCK_LPSPI5_ClockRoot_MuxVideoPll1Out = 3U,
551
552 /* Lpspi6 */
553 kCLOCK_LPSPI6_ClockRoot_MuxOsc24M = 0U,
554 kCLOCK_LPSPI6_ClockRoot_MuxSysPll1Pfd0Div2 = 1U,
555 kCLOCK_LPSPI6_ClockRoot_MuxSysPll1Pfd1Div2 = 2U,
556 kCLOCK_LPSPI6_ClockRoot_MuxVideoPll1Out = 3U,
557
558 /* Lpspi7 */
559 kCLOCK_LPSPI7_ClockRoot_MuxOsc24M = 0U,
560 kCLOCK_LPSPI7_ClockRoot_MuxSysPll1Pfd0Div2 = 1U,
561 kCLOCK_LPSPI7_ClockRoot_MuxSysPll1Pfd1Div2 = 2U,
562 kCLOCK_LPSPI7_ClockRoot_MuxVideoPll1Out = 3U,
563
564 /* Lpspi8 */
565 kCLOCK_LPSPI8_ClockRoot_MuxOsc24M = 0U,
566 kCLOCK_LPSPI8_ClockRoot_MuxSysPll1Pfd0Div2 = 1U,
567 kCLOCK_LPSPI8_ClockRoot_MuxSysPll1Pfd1Div2 = 2U,
568 kCLOCK_LPSPI8_ClockRoot_MuxVideoPll1Out = 3U,
569
570 /* I3c1 */
571 kCLOCK_I3C1_ClockRoot_MuxOsc24M = 0U,
572 kCLOCK_I3C1_ClockRoot_MuxSysPll1Pfd0Div2 = 1U,
573 kCLOCK_I3C1_ClockRoot_MuxSysPll1Pfd1Div2 = 2U,
574 kCLOCK_I3C1_ClockRoot_MuxVideoPll1Out = 3U,
575
576 /* I3c2 */
577 kCLOCK_I3C2_ClockRoot_MuxOsc24M = 0U,
578 kCLOCK_I3C2_ClockRoot_MuxSysPll1Pfd0Div2 = 1U,
579 kCLOCK_I3C2_ClockRoot_MuxSysPll1Pfd1Div2 = 2U,
580 kCLOCK_I3C2_ClockRoot_MuxVideoPll1Out = 3U,
581
582 /* Usdhc1 */
583 kCLOCK_Usdhc1_ClockRoot_MuxOsc24M = 0U,
584 kCLOCK_Usdhc1_ClockRoot_MuxSysPll1Pfd0 = 1U,
585 kCLOCK_Usdhc1_ClockRoot_MuxSysPll1Pfd1 = 2U,
586 kCLOCK_Usdhc1_ClockRoot_MuxSysPll1Pfd2 = 3U,
587
588 /* Usdhc2 */
589 kCLOCK_Usdhc2_ClockRoot_MuxOsc24M = 0U,
590 kCLOCK_Usdhc2_ClockRoot_MuxSysPll1Pfd0 = 1U,
591 kCLOCK_Usdhc2_ClockRoot_MuxSysPll1Pfd1 = 2U,
592 kCLOCK_Usdhc2_ClockRoot_MuxSysPll1Pfd2 = 3U,
593
594 /* Usdhc3 */
595 kCLOCK_Usdhc3_ClockRoot_MuxOsc24M = 0U,
596 kCLOCK_Usdhc3_ClockRoot_MuxSysPll1Pfd0 = 1U,
597 kCLOCK_Usdhc3_ClockRoot_MuxSysPll1Pfd1 = 2U,
598 kCLOCK_Usdhc3_ClockRoot_MuxSysPll1Pfd2 = 3U,
599
600 /* Sai1 */
601 kCLOCK_SAI1_ClockRoot_MuxOsc24M = 0U,
602 kCLOCK_SAI1_ClockRoot_MuxAudioPll1Out = 1U,
603 kCLOCK_SAI1_ClockRoot_MuxVideoPll1Out = 2U,
604 kCLOCK_SAI1_ClockRoot_MuxExt = 3U,
605
606 /* Sai2 */
607 kCLOCK_SAI2_ClockRoot_MuxOsc24M = 0U,
608 kCLOCK_SAI2_ClockRoot_MuxAudioPll1Out = 1U,
609 kCLOCK_SAI2_ClockRoot_MuxVideoPll1Out = 2U,
610 kCLOCK_SAI2_ClockRoot_MuxExt = 3U,
611
612 /* Sai3 */
613 kCLOCK_SAI3_ClockRoot_MuxOsc24M = 0U,
614 kCLOCK_SAI3_ClockRoot_MuxAudioPll1Out = 1U,
615 kCLOCK_SAI3_ClockRoot_MuxVideoPll1Out = 2U,
616 kCLOCK_SAI3_ClockRoot_MuxExt = 3U,
617
618 /* Ccm Cko1 */
619 kCLOCK_CCMCKO1_ClockRoot_MuxOsc24M = 0U,
620 kCLOCK_CCMCKO1_ClockRoot_MuxSysPll1Pfd0 = 1U,
621 kCLOCK_CCMCKO1_ClockRoot_MuxSysPll1Pfd1 = 2U,
622 kCLOCK_CCMCKO1_ClockRoot_MuxAudioPll1Out = 3U,
623
624 /* Ccm Cko2 */
625 kCLOCK_CCMCKO2_ClockRoot_MuxOsc24M = 0U,
626 kCLOCK_CCMCKO2_ClockRoot_MuxSysPll1Pfd0 = 1U,
627 kCLOCK_CCMCKO2_ClockRoot_MuxSysPll1Pfd1 = 2U,
628 kCLOCK_CCMCKO2_ClockRoot_MuxVideoPll1Out = 3U,
629
630 /* Ccm Cko3 */
631 kCLOCK_CCMCKO3_ClockRoot_MuxOsc24M = 0U,
632 kCLOCK_CCMCKO3_ClockRoot_MuxSysPll1Pfd0 = 1U,
633 kCLOCK_CCMCKO3_ClockRoot_MuxSysPll1Pfd1 = 2U,
634 kCLOCK_CCMCKO3_ClockRoot_MuxAudioPll1Out = 3U,
635
636 /* Ccm Cko4 */
637 kCLOCK_CCMCKO4_ClockRoot_MuxOsc24M = 0U,
638 kCLOCK_CCMCKO4_ClockRoot_MuxSysPll1Pfd0 = 1U,
639 kCLOCK_CCMCKO4_ClockRoot_MuxSysPll1Pfd1 = 2U,
640 kCLOCK_CCMCKO4_ClockRoot_MuxVideoPll1Out = 3U,
641
642 /* Hsio */
643 kCLOCK_HSIO_ClockRoot_MuxOsc24M = 0U,
644 kCLOCK_HSIO_ClockRoot_MuxSysPll1Pfd0Div2 = 1U,
645 kCLOCK_HSIO_ClockRoot_MuxSysPll1Pfd1Div2 = 2U,
646 kCLOCK_HSIO_ClockRoot_MuxVideoPll1Out = 3U,
647
648 /* Hsio Usb Test 60M */
649 kCLOCK_HSIOUSBTEST60M_ClockRoot_MuxOsc24M = 0U,
650 kCLOCK_HSIOUSBTEST60M_ClockRoot_MuxSysPll1Pfd0Div2 = 1U,
651 kCLOCK_HSIOUSBTEST60M_ClockRoot_MuxSysPll1Pfd1Div2 = 2U,
652 kCLOCK_HSIOUSBTEST60M_ClockRoot_MuxVideoPll1Out = 3U,
653
654 /* Hsio Acscan 80M */
655 kCLOCK_HSIOACSCAN80M_ClockRoot_MuxOsc24M = 0U,
656 kCLOCK_HSIOACSCAN80M_ClockRoot_MuxSysPll1Pfd0Div2 = 1U,
657 kCLOCK_HSIOACSCAN80M_ClockRoot_MuxSysPll1Pfd1Div2 = 2U,
658 kCLOCK_HSIOACSCAN80M_ClockRoot_MuxVideoPll1Out = 3U,
659
660 /* Hsio Acscan 480M */
661 kCLOCK_HSIOACSCAN480M_ClockRoot_MuxOsc24M = 0U,
662 kCLOCK_HSIOACSCAN480M_ClockRoot_MuxSysPll1Pfd0Div2 = 1U,
663 kCLOCK_HSIOACSCAN480M_ClockRoot_MuxSysPll1Pfd1Div2 = 2U,
664 kCLOCK_HSIOACSCAN480M_ClockRoot_MuxVideoPll1Out = 3U,
665
666 /* Nic */
667 kCLOCK_NIC_ClockRoot_MuxOsc24M = 0U,
668 kCLOCK_NIC_ClockRoot_MuxSysPll1Pfd0 = 1U,
669 kCLOCK_NIC_ClockRoot_MuxSysPll1Pfd1 = 2U,
670 kCLOCK_NIC_ClockRoot_MuxSysPll1Pfd2 = 3U,
671
672 /* Nic Apb */
673 kCLOCK_NICAPB_ClockRoot_MuxOsc24M = 0U,
674 kCLOCK_NICAPB_ClockRoot_MuxSysPll1Pfd0Div2 = 1U,
675 kCLOCK_NICAPB_ClockRoot_MuxSysPll1Pfd1Div2 = 2U,
676 kCLOCK_NICAPB_ClockRoot_MuxVideoPll1Out = 3U,
677
678 /* Ml Apb */
679 kCLOCK_MLAPB_ClockRoot_MuxOsc24M = 0U,
680 kCLOCK_MLAPB_ClockRoot_MuxSysPll1Pfd0Div2 = 1U,
681 kCLOCK_MLAPB_ClockRoot_MuxSysPll1Pfd1Div2 = 2U,
682 kCLOCK_MLAPB_ClockRoot_MuxVideoPll1Out = 3U,
683
684 /* Ml */
685 kCLOCK_ML_ClockRoot_MuxOsc24M = 0U,
686 kCLOCK_ML_ClockRoot_MuxSysPll1Pfd0 = 1U,
687 kCLOCK_ML_ClockRoot_MuxSysPll1Pfd1 = 2U,
688 kCLOCK_ML_ClockRoot_MuxSysPll1Pfd2 = 3U,
689
690 /* Media Axi */
691 kCLOCK_MEDIAAXI_ClockRoot_MuxOsc24M = 0U,
692 kCLOCK_MEDIAAXI_ClockRoot_MuxSysPll1Pfd0 = 1U,
693 kCLOCK_MEDIAAXI_ClockRoot_MuxSysPll1Pfd1 = 2U,
694 kCLOCK_MEDIAAXI_ClockRoot_MuxSysPll1Pfd2 = 3U,
695
696 /* Media Apb */
697 kCLOCK_MEDIAAPB_ClockRoot_MuxOsc24M = 0U,
698 kCLOCK_MEDIAAPB_ClockRoot_MuxSysPll1Pfd0Div2 = 1U,
699 kCLOCK_MEDIAAPB_ClockRoot_MuxSysPll1Pfd1Div2 = 2U,
700 kCLOCK_MEDIAAPB_ClockRoot_MuxVideoPll1Out = 3U,
701
702 /* Media Ldb */
703 kCLOCK_MEDIALDB_ClockRoot_MuxOsc24M = 0U,
704 kCLOCK_MEDIALDB_ClockRoot_MuxAudioPll1Out = 1U,
705 kCLOCK_MEDIALDB_ClockRoot_MuxVideoPll1Out = 2U,
706 kCLOCK_MEDIALDB_ClockRoot_MuxSysPll1Pfd0 = 3U,
707
708 /* Media Disp Pix */
709 kCLOCK_MEDIADISPPIX_ClockRoot_MuxOsc24M = 0U,
710 kCLOCK_MEDIADISPPIX_ClockRoot_MuxAudioPll1Out = 1U,
711 kCLOCK_MEDIADISPPIX_ClockRoot_MuxVideoPll1Out = 2U,
712 kCLOCK_MEDIADISPPIX_ClockRoot_MuxSysPll1Pfd0 = 3U,
713
714 /* Cam Pix */
715 kCLOCK_CAMPIX_ClockRoot_MuxOsc24M = 0U,
716 kCLOCK_CAMPIX_ClockRoot_MuxAudioPll1Out = 1U,
717 kCLOCK_CAMPIX_ClockRoot_MuxVideoPll1Out = 2U,
718 kCLOCK_CAMPIX_ClockRoot_MuxSysPll1Pfd0 = 3U,
719
720 /* Mipi Test Byte */
721 kCLOCK_MIPITESTBYTE_ClockRoot_MuxOsc24M = 0U,
722 kCLOCK_MIPITESTBYTE_ClockRoot_MuxAudioPll1Out = 1U,
723 kCLOCK_MIPITESTBYTE_ClockRoot_MuxVideoPll1Out = 2U,
724 kCLOCK_MIPITESTBYTE_ClockRoot_MuxSysPll1Pfd0 = 3U,
725
726 /* Mipi Phy Cfg */
727 kCLOCK_MIPIPHYCFG_ClockRoot_MuxOsc24M = 0U,
728 kCLOCK_MIPIPHYCFG_ClockRoot_MuxAudioPll1Out = 1U,
729 kCLOCK_MIPIPHYCFG_ClockRoot_MuxVideoPll1Out = 2U,
730 kCLOCK_MIPIPHYCFG_ClockRoot_MuxSysPll1Pfd0 = 3U,
731
732 /* Dram Alt */
733 kCLOCK_DRAMALT_ClockRoot_MuxOsc24M = 0U,
734 kCLOCK_DRAMALT_ClockRoot_MuxSysPll1Pfd0 = 1U,
735 kCLOCK_DRAMALT_ClockRoot_MuxSysPll1Pfd1 = 2U,
736 kCLOCK_DRAMALT_ClockRoot_MuxSysPll1Pfd2 = 3U,
737
738 /* Dram Apb */
739 kCLOCK_DRAMAPB_ClockRoot_MuxOsc24M = 0U,
740 kCLOCK_DRAMAPB_ClockRoot_MuxSysPll1Pfd0Div2 = 1U,
741 kCLOCK_DRAMAPB_ClockRoot_MuxSysPll1Pfd1Div2 = 2U,
742 kCLOCK_DRAMAPB_ClockRoot_MuxSysPll1Pfd2Div2 = 3U,
743
744 /* Adc */
745 kCLOCK_ADC_ClockRoot_MuxOsc24M = 0U,
746 kCLOCK_ADC_ClockRoot_MuxSysPll1Pfd0Div2 = 1U,
747 kCLOCK_ADC_ClockRoot_MuxSysPll1Pfd1Div2 = 2U,
748 kCLOCK_ADC_ClockRoot_MuxVideoPll1Out = 3U,
749
750 /* Pdm */
751 kCLOCK_PDM_ClockRoot_MuxOsc24M = 0U,
752 kCLOCK_PDM_ClockRoot_MuxAudioPll1Out = 1U,
753 kCLOCK_PDM_ClockRoot_MuxVideoPll1Out = 2U,
754 kCLOCK_PDM_ClockRoot_MuxExt = 3U,
755
756 /* Tstmr1 */
757 kCLOCK_TSTMR1_ClockRoot_MuxOsc24M = 0U,
758 kCLOCK_TSTMR1_ClockRoot_MuxSysPll1Pfd0Div2 = 1U,
759 kCLOCK_TSTMR1_ClockRoot_MuxSysPll1Pfd1Div2 = 2U,
760 kCLOCK_TSTMR1_ClockRoot_MuxVideoPll1Out = 3U,
761
762 /* Tstmr2 */
763 kCLOCK_TSTMR2_ClockRoot_MuxOsc24M = 0U,
764 kCLOCK_TSTMR2_ClockRoot_MuxSysPll1Pfd0Div2 = 1U,
765 kCLOCK_TSTMR2_ClockRoot_MuxSysPll1Pfd1Div2 = 2U,
766 kCLOCK_TSTMR2_ClockRoot_MuxVideoPll1Out = 3U,
767
768 /* MQS1 */
769 kCLOCK_MQS1_ClockRoot_MuxOsc24M = 0U,
770 kCLOCK_MQS1_ClockRoot_MuxAudioPll1Out = 1U,
771 kCLOCK_MQS1_ClockRoot_MuxVideoPll1Out = 2U,
772 kCLOCK_MQS1_ClockRoot_MuxExt = 3U,
773
774 /* MQS2 */
775 kCLOCK_MQS2_ClockRoot_MuxOsc24M = 0U,
776 kCLOCK_MQS2_ClockRoot_MuxAudioPll1Out = 1U,
777 kCLOCK_MQS2_ClockRoot_MuxVideoPll1Out = 2U,
778 kCLOCK_MQS2_ClockRoot_MuxExt = 3U,
779
780 /* Audio XCVR */
781 kCLOCK_AUDIOXCVR_ClockRoot_MuxOsc24M = 0U,
782 kCLOCK_AUDIOXCVR_ClockRoot_MuxSysPll1Pfd0Div2 = 1U,
783 kCLOCK_AUDIOXCVR_ClockRoot_MuxSysPll1Pfd1Div2 = 2U,
784 kCLOCK_AUDIOXCVR_ClockRoot_MuxSysPll1Pfd2Div2 = 3U,
785
786 /* Spdif */
787 kCLOCK_SPDIF_ClockRoot_MuxOsc24M = 0U,
788 kCLOCK_SPDIF_ClockRoot_MuxAudioPll1Out = 1U,
789 kCLOCK_SPDIF_ClockRoot_MuxVideoPll1Out = 2U,
790 kCLOCK_SPDIF_ClockRoot_MuxExt = 3U,
791
792 /* Enet */
793 kCLOCK_ENET_ClockRoot_MuxOsc24M = 0U,
794 kCLOCK_ENET_ClockRoot_MuxSysPll1Pfd0Div2 = 1U,
795 kCLOCK_ENET_ClockRoot_MuxSysPll1Pfd1Div2 = 2U,
796 kCLOCK_ENET_ClockRoot_MuxSysPll1Pfd2Div2 = 3U,
797
798 /* Enet Timer1 */
799 kCLOCK_ENETTSTMR1_ClockRoot_MuxOsc24M = 0U,
800 kCLOCK_ENETTSTMR1_ClockRoot_MuxSysPll1Pfd0Div2 = 1U,
801 kCLOCK_ENETTSTMR1_ClockRoot_MuxSysPll1Pfd1Div2 = 2U,
802 kCLOCK_ENETTSTMR1_ClockRoot_MuxVideoPll1Out = 3U,
803
804 /* Enet Timer2 */
805 kCLOCK_ENETTSTMR2_ClockRoot_MuxOsc24M = 0U,
806 kCLOCK_ENETTSTMR2_ClockRoot_MuxSysPll1Pfd0Div2 = 1U,
807 kCLOCK_ENETTSTMR2_ClockRoot_MuxSysPll1Pfd1Div2 = 2U,
808 kCLOCK_ENETTSTMR2_ClockRoot_MuxVideoPll1Out = 3U,
809
810 /* Enet Ref */
811 kCLOCK_ENETREF_ClockRoot_MuxOsc24M = 0U,
812 kCLOCK_ENETREF_ClockRoot_MuxSysPll1Pfd0Div2 = 1U,
813 kCLOCK_ENETREF_ClockRoot_MuxSysPll1Pfd1Div2 = 2U,
814 kCLOCK_ENETREF_ClockRoot_MuxSysPll1Pfd2Div2 = 3U,
815
816 /* Enet Ref Phy */
817 kCLOCK_ENETREFPHY_ClockRoot_MuxOsc24M = 0U,
818 kCLOCK_ENETREFPHY_ClockRoot_MuxSysPll1Pfd0Div2 = 1U,
819 kCLOCK_ENETREFPHY_ClockRoot_MuxSysPll1Pfd1Div2 = 2U,
820 kCLOCK_ENETREFPHY_ClockRoot_MuxVideoPll1Out = 3U,
821
822 /* I3c1 Slow */
823 kCLOCK_I3C1SLOW_ClockRoot_MuxOsc24M = 0U,
824 kCLOCK_I3C1SLOW_ClockRoot_MuxSysPll1Pfd0Div2 = 1U,
825 kCLOCK_I3C1SLOW_ClockRoot_MuxSysPll1Pfd1Div2 = 2U,
826 kCLOCK_I3C1SLOW_ClockRoot_MuxVideoPll1Out = 3U,
827
828 /* I3c2 Slow */
829 kCLOCK_I3C2SLOW_ClockRoot_MuxOsc24M = 0U,
830 kCLOCK_I3C2SLOW_ClockRoot_MuxSysPll1Pfd0Div2 = 1U,
831 kCLOCK_I3C2SLOW_ClockRoot_MuxSysPll1Pfd1Div2 = 2U,
832 kCLOCK_I3C2SLOW_ClockRoot_MuxVideoPll1Out = 3U,
833
834 /* Usb Phy Burunin */
835 kCLOCK_USBPHYBURUNIN_ClockRoot_MuxOsc24M = 0U,
836 kCLOCK_USBPHYBURUNIN_ClockRoot_MuxSysPll1Pfd0Div2 = 1U,
837 kCLOCK_USBPHYBURUNIN_ClockRoot_MuxSysPll1Pfd1Div2 = 2U,
838 kCLOCK_USBPHYBURUNIN_ClockRoot_MuxVideoPll1Out = 3U,
839
840 /* Pal Came Scan */
841 kCLOCK_PALCAMESCAN_ClockRoot_MuxOsc24M = 0U,
842 kCLOCK_PALCAMESCAN_ClockRoot_MuxAudioPll1Out = 1U,
843 kCLOCK_PALCAMESCAN_ClockRoot_MuxVideoPll1Out = 2U,
844 kCLOCK_PALCAMESCAN_ClockRoot_MuxSysPll1Pfd2 = 3U,
845 } clock_root_mux_source_t;
846
847 /*******************************************************************************
848 * Clock Gate Definitions
849 ******************************************************************************/
850
851 /*! @brief Clock gate value */
852 typedef enum _clock_gate_value
853 {
854 kCLOCK_Off = CCM_LPCG_LPM_SETTING_0,
855 kCLOCK_On = CCM_LPCG_LPM_SETTING_4,
856 } clock_gate_value_t;
857
858 /*!
859 * @brief Clock LPCG index (Clock Gating Channel)
860 */
861 typedef enum _clock_lpcg
862 {
863 kCLOCK_A55 = 0,
864 kCLOCK_Cm33 = 1,
865 kCLOCK_Arm_Trout = 2,
866 kCLOCK_Sentinel = 3,
867 kCLOCK_Sim_Wakeup = 4,
868 kCLOCK_Sim_Aon = 5,
869 kCLOCK_Sim_Mega = 6,
870 kCLOCK_Anadig = 7,
871 kCLOCK_Src = 8,
872 kCLOCK_Ccm = 9,
873 kCLOCK_Gpc = 10,
874 kCLOCK_Adc1 = 11,
875 kCLOCK_Wdog1 = 12,
876 kCLOCK_Wdog2 = 13,
877 kCLOCK_Wdog3 = 14,
878 kCLOCK_Wdog4 = 15,
879 kCLOCK_Wdog5 = 16,
880 kCLOCK_Sema1 = 17,
881 kCLOCK_Sema2 = 18,
882 kCLOCK_Mu_A = 19,
883 kCLOCK_Mu_B = 20,
884 kCLOCK_Edma1 = 21,
885 kCLOCK_Edma2 = 22,
886 kCLOCK_Romcp_A55 = 23,
887 kCLOCK_Romcp_M33 = 24,
888 kCLOCK_Flexspi1 = 25,
889 kCLOCK_Aon_Trdc = 26,
890 kCLOCK_Wkup_Trdc = 27,
891 kCLOCK_Ocotp = 28,
892 kCLOCK_Bbsm_Hp = 29,
893 kCLOCK_Bbsm = 30,
894 kCLOCK_Cstrace = 31,
895 kCLOCK_Csswo = 32,
896 kCLOCK_Iomuxc = 33,
897 kCLOCK_Gpio1 = 34,
898 kCLOCK_Gpio2 = 35,
899 kCLOCK_Gpio3 = 36,
900 kCLOCK_Gpio4 = 37,
901 kCLOCK_Flexio1 = 38,
902 kCLOCK_Flexio2 = 39,
903 kCLOCK_Lpit1 = 40,
904 kCLOCK_Lpit2 = 41,
905 kCLOCK_Lptmr1 = 42,
906 kCLOCK_Lptmr2 = 43,
907 kCLOCK_Tpm1 = 44,
908 kCLOCK_Tpm2 = 45,
909 kCLOCK_Tpm3 = 46,
910 kCLOCK_Tpm4 = 47,
911 kCLOCK_Tpm5 = 48,
912 kCLOCK_Tpm6 = 49,
913 kCLOCK_Can1 = 50,
914 kCLOCK_Can2 = 51,
915 kCLOCK_Lpuart1 = 52,
916 kCLOCK_Lpuart2 = 53,
917 kCLOCK_Lpuart3 = 54,
918 kCLOCK_Lpuart4 = 55,
919 kCLOCK_Lpuart5 = 56,
920 kCLOCK_Lpuart6 = 57,
921 kCLOCK_Lpuart7 = 58,
922 kCLOCK_Lpuart8 = 59,
923 kCLOCK_Lpi2c1 = 60,
924 kCLOCK_Lpi2c2 = 61,
925 kCLOCK_Lpi2c3 = 62,
926 kCLOCK_Lpi2c4 = 63,
927 kCLOCK_Lpi2c5 = 64,
928 kCLOCK_Lpi2c6 = 65,
929 kCLOCK_Lpi2c7 = 66,
930 kCLOCK_Lpi2c8 = 67,
931 kCLOCK_Lpspi1 = 68,
932 kCLOCK_Lpspi2 = 69,
933 kCLOCK_Lpspi3 = 70,
934 kCLOCK_Lpspi4 = 71,
935 kCLOCK_Lpspi5 = 72,
936 kCLOCK_Lpspi6 = 73,
937 kCLOCK_Lpspi7 = 74,
938 kCLOCK_Lpspi8 = 75,
939 kCLOCK_I3c1 = 76,
940 kCLOCK_I3c2 = 77,
941 kCLOCK_Usdhc1 = 78,
942 kCLOCK_Usdhc2 = 79,
943 kCLOCK_Usdhc3 = 80,
944 kCLOCK_Sai1 = 81,
945 kCLOCK_Sai2 = 82,
946 kCLOCK_Sai3 = 83,
947 kCLOCK_Ssi_W2ao = 84,
948 kCLOCK_Ssi_Ao2w = 85,
949 kCLOCK_Mipi_Csi = 86,
950 kCLOCK_Mipi_Dsi = 87,
951 kCLOCK_Lvds = 88,
952 kCLOCK_Lcdif = 89,
953 kCLOCK_Pxp = 90,
954 kCLOCK_Isi = 91,
955 kCLOCK_Nic_Media = 92,
956 kCLOCK_Ddr_Dfi = 93,
957 kCLOCK_Ddr_Ctl = 94,
958 kCLOCK_Ddr_Dfi_Ctl = 95,
959 kCLOCK_Ddr_Ssi = 96,
960 kCLOCK_Ddr_Bypass = 97,
961 kCLOCK_Ddr_Apb = 98,
962 kCLOCK_Ddr_Drampll = 99,
963 kCLOCK_Ddr_Clk_Ctl = 100,
964 kCLOCK_Nic_Central = 101,
965 kCLOCK_Gic600 = 102,
966 kCLOCK_Nic_Apb = 103,
967 kCLOCK_Usb_Controller = 104,
968 kCLOCK_Usb_Test_60m = 105,
969 kCLOCK_Hsio_Trout_24m = 106,
970 kCLOCK_Pdm = 107,
971 kCLOCK_Mqs1 = 108,
972 kCLOCK_Mqs2 = 109,
973 kCLOCK_Aud_Xcvr = 110,
974 kCLOCK_Nicmix_Mecc = 111,
975 kCLOCK_Spdif = 112,
976 kCLOCK_Ssi_Ml2nic = 113,
977 kCLOCK_Ssi_Med2nic = 114,
978 kCLOCK_Ssi_Hsio2nic = 115,
979 kCLOCK_Ssi_W2nic = 116,
980 kCLOCK_Ssi_Nic2w = 117,
981 kCLOCK_Ssi_Nic2ddr = 118,
982 kCLOCK_Hsio_32k = 119,
983 kCLOCK_Enet1 = 120,
984 kCLOCK_Enet_Qos = 121,
985 kCLOCK_Sys_Cnt = 122,
986 kCLOCK_Tstmr1 = 123,
987 kCLOCK_Tstmr2 = 124,
988 kCLOCK_Tmc = 125,
989 kCLOCK_Pmro = 126,
990 kCLOCK_IpInvalid,
991 } clock_lpcg_t;
992
993 #define clock_ip_name_t clock_lpcg_t
994
995 /*! @brief Clock ip name array for EDMA. */
996 #define EDMA_CLOCKS \
997 { \
998 kCLOCK_Edma1, kCLOCK_Edma2 \
999 }
1000
1001 /*
1002 * ! @brief Clock ip name array for MU.
1003 * clock of MU1_MUA, MU2_MUA is enabled by same LPCG42(Gate signal is clk_enable_mu_a)
1004 */
1005 #define MU_CLOCKS \
1006 { \
1007 kCLOCK_Mu_A, kCLOCK_Mu_A \
1008 }
1009
1010 /*! @brief Clock ip name array for LCDIFV3. */
1011 #define LCDIFV3_CLOCKS \
1012 { \
1013 kCLOCK_IpInvalid, kCLOCK_Lcdif \
1014 }
1015
1016 /*! @brief Clock ip name array for LPI2C. */
1017 #define LPI2C_CLOCKS \
1018 { \
1019 kCLOCK_IpInvalid, kCLOCK_Lpi2c1, kCLOCK_Lpi2c2, kCLOCK_Lpi2c3, kCLOCK_Lpi2c4, kCLOCK_Lpi2c5, kCLOCK_Lpi2c6, \
1020 kCLOCK_Lpi2c7, kCLOCK_Lpi2c8 \
1021 }
1022
1023 /*! @brief Clock ip name array for LPIT. */
1024 #define LPIT_CLOCKS \
1025 { \
1026 kCLOCK_IpInvalid, kCLOCK_Lpit1, kCLOCK_Lpit2 \
1027 }
1028
1029 /*! @brief Clock ip name array for LPSPI. */
1030 #define LPSPI_CLOCKS \
1031 { \
1032 kCLOCK_IpInvalid, kCLOCK_Lpspi1, kCLOCK_Lpspi2, kCLOCK_Lpspi3, kCLOCK_Lpspi4, kCLOCK_Lpspi5, kCLOCK_Lpspi6, \
1033 kCLOCK_Lpspi7, kCLOCK_Lpspi8 \
1034 }
1035
1036 /*! @brief Clock ip name array for TPM. */
1037 #define TPM_CLOCKS \
1038 { \
1039 kCLOCK_Tpm1, kCLOCK_Tpm2, kCLOCK_Tpm3, kCLOCK_Tpm4, kCLOCK_Tpm5, kCLOCK_Tpm6, \
1040 }
1041
1042 /*! @brief Clock ip name array for FLEXIO. */
1043 #define FLEXIO_CLOCKS \
1044 { \
1045 kCLOCK_IpInvalid, kCLOCK_Flexio1, kCLOCK_Flexio2 \
1046 }
1047
1048 /*! @brief Clock ip name array for FLEXSPI. */
1049 #define FLEXSPI_CLOCKS \
1050 { \
1051 kCLOCK_IpInvalid, kCLOCK_Flexspi1 \
1052 }
1053
1054 /*! @brief Clock ip name array for TMU. */
1055 #define TMU_CLOCKS \
1056 { \
1057 kCLOCK_Tmc, \
1058 }
1059
1060 /*! @brief Clock ip name array for FLEXCAN. */
1061 #define FLEXCAN_CLOCKS \
1062 { \
1063 kCLOCK_IpInvalid, kCLOCK_Can1, kCLOCK_Can2, \
1064 }
1065
1066 /*! @brief Clock ip name array for LPUART. */
1067 #define LPUART_CLOCKS \
1068 { \
1069 kCLOCK_IpInvalid, kCLOCK_Lpuart1, kCLOCK_Lpuart2, kCLOCK_Lpuart3, kCLOCK_Lpuart4, kCLOCK_Lpuart5, \
1070 kCLOCK_Lpuart6, kCLOCK_Lpuart7, kCLOCK_Lpuart8 \
1071 }
1072
1073 /*! @brief Clock ip name array for SAI. */
1074 #define SAI_CLOCKS \
1075 { \
1076 kCLOCK_IpInvalid, kCLOCK_Sai1, kCLOCK_Sai2, kCLOCK_Sai3, \
1077 }
1078
1079 /*! @brief Clock ip name array for PDM. */
1080 #define PDM_CLOCKS \
1081 { \
1082 kCLOCK_Pdm \
1083 }
1084
1085 /*! @brief Clock ip name array for ENET QOS. */
1086 #define ENETQOS_CLOCKS \
1087 { \
1088 kCLOCK_Enet_Qos \
1089 }
1090
1091 /*! @brief Clock ip name array for ENET. */
1092 #define ENET_CLOCKS \
1093 { \
1094 kCLOCK_Enet1 \
1095 }
1096
1097 /*! @brief Clock ip name array for I3C. */
1098 #define I3C_CLOCKS \
1099 { \
1100 kCLOCK_IpInvalid, kCLOCK_I3c1, kCLOCK_I3c2 \
1101 }
1102
1103 /*! @brief Clock ip name array for SEMA42. */
1104 #define SEMA42_CLOCKS \
1105 { \
1106 kCLOCK_IpInvalid, kCLOCK_Sema1, kCLOCK_Sema2 \
1107 }
1108
1109 /*******************************************************************************
1110 * Clock Root APIs
1111 ******************************************************************************/
1112
1113 /*!
1114 * @brief Set CCM Root Clock MUX node to certain value.
1115 *
1116 * @param root Which root clock node to set, see \ref clock_root_t.
1117 * @param src Clock mux value to set, different mux has different value range. See \ref clock_root_mux_source_t.
1118 */
CLOCK_SetRootClockMux(clock_root_t root,uint8_t src)1119 static inline void CLOCK_SetRootClockMux(clock_root_t root, uint8_t src)
1120 {
1121 assert(src < 8U);
1122 CCM_CTRL->CLOCK_ROOT[root].CLOCK_ROOT_CONTROL.RW =
1123 (CCM_CTRL->CLOCK_ROOT[root].CLOCK_ROOT_CONTROL.RW & ~(CCM_CLOCK_ROOT_MUX_MASK)) | CCM_CLOCK_ROOT_MUX(src);
1124 __DSB();
1125 __ISB();
1126 }
1127
1128 /*!
1129 * @brief Get CCM Root Clock MUX value.
1130 *
1131 * @param root Which root clock node to get, see \ref clock_root_t.
1132 * @return Clock mux value.
1133 */
CLOCK_GetRootClockMux(clock_root_t root)1134 static inline uint32_t CLOCK_GetRootClockMux(clock_root_t root)
1135 {
1136 return (CCM_CTRL->CLOCK_ROOT[root].CLOCK_ROOT_CONTROL.RW & CCM_CLOCK_ROOT_MUX_MASK) >> CCM_CLOCK_ROOT_MUX_SHIFT;
1137 }
1138
1139 /*!
1140 * @brief Get CCM Root Clock Source.
1141 *
1142 * @param root Which root clock node to get, see \ref clock_root_t.
1143 * @param src Clock mux value to get, see \ref clock_root_mux_source_t.
1144 * @return Clock source
1145 */
CLOCK_GetRootClockSource(clock_root_t root,uint32_t src)1146 static inline clock_name_t CLOCK_GetRootClockSource(clock_root_t root, uint32_t src)
1147 {
1148 return s_clockSourceName[root][src];
1149 }
1150
1151 /*!
1152 * @brief Set CCM Root Clock DIV certain value.
1153 *
1154 * @param root Which root clock to set, see \ref clock_root_t.
1155 * @param div Clock div value to set, different divider has different value range.
1156 */
CLOCK_SetRootClockDiv(clock_root_t root,uint8_t div)1157 static inline void CLOCK_SetRootClockDiv(clock_root_t root, uint8_t div)
1158 {
1159 assert(div);
1160 CCM_CTRL->CLOCK_ROOT[root].CLOCK_ROOT_CONTROL.RW =
1161 (CCM_CTRL->CLOCK_ROOT[root].CLOCK_ROOT_CONTROL.RW & ~CCM_CLOCK_ROOT_DIV_MASK) |
1162 CCM_CLOCK_ROOT_DIV((uint32_t)div - 1UL);
1163 __DSB();
1164 __ISB();
1165 }
1166
1167 /*!
1168 * @brief Get CCM DIV node value.
1169 *
1170 * @param root Which root clock node to get, see \ref clock_root_t.
1171 * @return divider set for this root
1172 */
CLOCK_GetRootClockDiv(clock_root_t root)1173 static inline uint32_t CLOCK_GetRootClockDiv(clock_root_t root)
1174 {
1175 return ((CCM_CTRL->CLOCK_ROOT[root].CLOCK_ROOT_CONTROL.RW & CCM_CLOCK_ROOT_DIV_MASK) >> CCM_CLOCK_ROOT_DIV_SHIFT) +
1176 1UL;
1177 }
1178
1179 /*!
1180 * @brief Power Off Root Clock
1181 *
1182 * @param root Which root clock node to set, see \ref clock_root_t.
1183 */
CLOCK_PowerOffRootClock(clock_root_t root)1184 static inline void CLOCK_PowerOffRootClock(clock_root_t root)
1185 {
1186 if (0UL == (CCM_CTRL->CLOCK_ROOT[root].CLOCK_ROOT_CONTROL.RW & CCM_CLOCK_ROOT_OFF_MASK))
1187 {
1188 CCM_CTRL->CLOCK_ROOT[root].CLOCK_ROOT_CONTROL.SET = CCM_CLOCK_ROOT_OFF_MASK;
1189 __DSB();
1190 __ISB();
1191 }
1192 }
1193
1194 /*!
1195 * @brief Power On Root Clock
1196 *
1197 * @param root Which root clock node to set, see \ref clock_root_t.
1198 */
CLOCK_PowerOnRootClock(clock_root_t root)1199 static inline void CLOCK_PowerOnRootClock(clock_root_t root)
1200 {
1201 CCM_CTRL->CLOCK_ROOT[root].CLOCK_ROOT_CONTROL.CLR = CCM_CLOCK_ROOT_OFF_MASK;
1202 __DSB();
1203 __ISB();
1204 }
1205
1206 /*!
1207 * @brief Configure Root Clock
1208 *
1209 * @param root Which root clock node to set, see \ref clock_root_t.
1210 * @param config root clock config, see \ref clock_root_config_t
1211 */
CLOCK_SetRootClock(clock_root_t root,const clock_root_config_t * config)1212 static inline void CLOCK_SetRootClock(clock_root_t root, const clock_root_config_t *config)
1213 {
1214 assert(config);
1215 CCM_CTRL->CLOCK_ROOT[root].CLOCK_ROOT_CONTROL.RW = CCM_CLOCK_ROOT_MUX(config->mux) |
1216 CCM_CLOCK_ROOT_DIV((uint32_t)config->div - 1UL) |
1217 (config->clockOff ? CCM_CLOCK_ROOT_OFF(config->clockOff) : 0UL);
1218 __DSB();
1219 __ISB();
1220 }
1221
1222 /*******************************************************************************
1223 * Clock Gate APIs
1224 ******************************************************************************/
1225
1226 /*!
1227 * @brief Control the clock gate for specific IP.
1228 *
1229 * @param name Which clock to enable, see \ref clock_lpcg_t.
1230 * @param value Clock gate value to set, see \ref clock_gate_value_t.
1231 */
CLOCK_ControlGate(clock_ip_name_t name,clock_gate_value_t value)1232 static inline void CLOCK_ControlGate(clock_ip_name_t name, clock_gate_value_t value)
1233 {
1234 CCM_CTRL->LPCG[name].AUTHEN |= CCM_LPCG_AUTHEN_CPULPM_MODE(1U);
1235 CCM_CTRL->LPCG[name].LPM_CUR = CCM_LPCG_LPM_CUR_LPM_SETTING_CUR(value);
1236 __DSB();
1237 __ISB();
1238 }
1239
1240 /*!
1241 * @brief Enable the clock for specific IP.
1242 *
1243 * @param name Which clock to enable, see \ref clock_lpcg_t.
1244 */
CLOCK_EnableClock(clock_ip_name_t name)1245 static inline void CLOCK_EnableClock(clock_ip_name_t name)
1246 {
1247 CLOCK_ControlGate(name, kCLOCK_On);
1248 }
1249
1250 /*!
1251 * @brief Disable the clock for specific IP.
1252 *
1253 * @param name Which clock to disable, see \ref clock_lpcg_t.
1254 */
CLOCK_DisableClock(clock_ip_name_t name)1255 static inline void CLOCK_DisableClock(clock_ip_name_t name)
1256 {
1257 CLOCK_ControlGate(name, kCLOCK_Off);
1258 }
1259
1260 /*******************************************************************************
1261 * Other APIs
1262 ******************************************************************************/
1263
1264 /*
1265 * Setup a variable for clock source frequencies
1266 */
1267 extern volatile uint32_t g_clockSourceFreq[kCLOCK_Ext + 1];
1268
1269 /*!
1270 * @brief Gets the clock frequency for a specific IP module.
1271 *
1272 * This function gets the IP module clock frequency.
1273 *
1274 * @param name Which root clock to get, see \ref clock_root_t.
1275 * @return Clock frequency value in hertz
1276 */
1277 uint32_t CLOCK_GetIpFreq(clock_root_t name);
1278
1279 #endif
1280
