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Searched refs:CLOCK_SetClkDiv (Results 1 – 25 of 165) sorted by relevance

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/hal_nxp-latest/mcux/mcux-sdk/boards/frdmrw612/
Dclock_config.c145 CLOCK_SetClkDiv(kCLOCK_DivSysCpuAhbClk, 1); in BOARD_BootClockRUN()
161 CLOCK_SetClkDiv(kCLOCK_DivAudioPllClk, 1U); /* Set .AUDIOPLLCLKDIV divider to value 1 */ in BOARD_BootClockRUN()
162 CLOCK_SetClkDiv(kCLOCK_DivPllFrgClk, 13U); /* Set .FRGPLLCLKDIV divider to value 13 */ in BOARD_BootClockRUN()
163 CLOCK_SetClkDiv(kCLOCK_DivMainPllClk, 1U); /* Set .MAINPLLCLKDIV divider to value 1 */ in BOARD_BootClockRUN()
164 CLOCK_SetClkDiv(kCLOCK_DivAux0PllClk, 1U); /* Set .AUX0PLLCLKDIV divider to value 1 */ in BOARD_BootClockRUN()
165 CLOCK_SetClkDiv(kCLOCK_DivSystickClk, 1U); /* Set .SYSTICKFCLKDIV divider to value 1 */ in BOARD_BootClockRUN()
166 CLOCK_SetClkDiv(kCLOCK_DivPmuFclk, 5U); /* Set .PMUFCLKDIV divider to value 5 */ in BOARD_BootClockRUN()
252 CLOCK_SetClkDiv(kCLOCK_DivSysCpuAhbClk, 1); in BOARD_BootClockLPR()
262 CLOCK_SetClkDiv(kCLOCK_DivPllFrgClk, 13U); /* Set .FRGPLLCLKDIV divider to value 13 */ in BOARD_BootClockLPR()
263 CLOCK_SetClkDiv(kCLOCK_DivMainPllClk, 1U); /* Set .MAINPLLCLKDIV divider to value 1 */ in BOARD_BootClockLPR()
[all …]
/hal_nxp-latest/mcux/mcux-sdk/boards/rdrw612bga/
Dclock_config.c145 CLOCK_SetClkDiv(kCLOCK_DivSysCpuAhbClk, 1); in BOARD_BootClockRUN()
161 CLOCK_SetClkDiv(kCLOCK_DivAudioPllClk, 1U); /* Set .AUDIOPLLCLKDIV divider to value 1 */ in BOARD_BootClockRUN()
162 CLOCK_SetClkDiv(kCLOCK_DivPllFrgClk, 13U); /* Set .FRGPLLCLKDIV divider to value 13 */ in BOARD_BootClockRUN()
163 CLOCK_SetClkDiv(kCLOCK_DivMainPllClk, 1U); /* Set .MAINPLLCLKDIV divider to value 1 */ in BOARD_BootClockRUN()
164 CLOCK_SetClkDiv(kCLOCK_DivAux0PllClk, 1U); /* Set .AUX0PLLCLKDIV divider to value 1 */ in BOARD_BootClockRUN()
165 CLOCK_SetClkDiv(kCLOCK_DivSystickClk, 1U); /* Set .SYSTICKFCLKDIV divider to value 1 */ in BOARD_BootClockRUN()
166 CLOCK_SetClkDiv(kCLOCK_DivPmuFclk, 5U); /* Set .PMUFCLKDIV divider to value 5 */ in BOARD_BootClockRUN()
252 CLOCK_SetClkDiv(kCLOCK_DivSysCpuAhbClk, 1); in BOARD_BootClockLPR()
262 CLOCK_SetClkDiv(kCLOCK_DivPllFrgClk, 13U); /* Set .FRGPLLCLKDIV divider to value 13 */ in BOARD_BootClockLPR()
263 CLOCK_SetClkDiv(kCLOCK_DivMainPllClk, 1U); /* Set .MAINPLLCLKDIV divider to value 1 */ in BOARD_BootClockLPR()
[all …]
/hal_nxp-latest/mcux/mcux-sdk/boards/evkmimxrt595/
Dclock_config.c205 CLOCK_SetClkDiv(kCLOCK_DivSysCpuAhbClk, 2); in BOARD_BootClockRUN()
223 CLOCK_SetClkDiv(kCLOCK_DivSysCpuAhbClk, 2U); /* Set SYSCPUAHBCLKDIV divider to value 2 */ in BOARD_BootClockRUN()
231 CLOCK_SetClkDiv(kCLOCK_DivAudioPllClk, 15U); /* Set AUDIOPLLCLKDIV divider to value 15 */ in BOARD_BootClockRUN()
232 CLOCK_SetClkDiv(kCLOCK_DivPLLFRGClk, 11U); /* Set FRGPLLCLKDIV divider to value 11 */ in BOARD_BootClockRUN()
233 CLOCK_SetClkDiv(kCLOCK_DivSystickClk, 2U); /* Set SYSTICKFCLKDIV divider to value 2 */ in BOARD_BootClockRUN()
234 CLOCK_SetClkDiv(kCLOCK_DivPfc0Clk, 2U); /* Set PFC0DIV divider to value 2 */ in BOARD_BootClockRUN()
235 CLOCK_SetClkDiv(kCLOCK_DivPfc1Clk, 4U); /* Set PFC1DIV divider to value 4 */ in BOARD_BootClockRUN()
236 CLOCK_SetClkDiv(kCLOCK_DivClockOut, 100U); /* Set CLKOUTFCLKDIV divider to value 100 */ in BOARD_BootClockRUN()
/hal_nxp-latest/mcux/mcux-sdk/boards/mimxrt700evk/project_template/cm33_core0/
Dclock_config.c110 CLOCK_SetClkDiv(kCLOCK_DivCmptMainClk, 1U); in BOARD_BootClockRUN()
112 CLOCK_SetClkDiv(kCLOCK_DivComputeRamClk, 1U); in BOARD_BootClockRUN()
115 CLOCK_SetClkDiv(kCLOCK_DivCommonVddnClk, 1U); in BOARD_BootClockRUN()
135 CLOCK_SetClkDiv(kCLOCK_DivCmptMainClk, 2U); in BOARD_BootClockRUN()
138 CLOCK_SetClkDiv(kCLOCK_DivMediaMainClk, 2U); in BOARD_BootClockRUN()
141 CLOCK_SetClkDiv(kCLOCK_DivMediaVddnClk, 2U); in BOARD_BootClockRUN()
144 CLOCK_SetClkDiv(kCLOCK_DivComputeRamClk, 2U); in BOARD_BootClockRUN()
147 CLOCK_SetClkDiv(kCLOCK_DivCommonVddnClk, 2U); in BOARD_BootClockRUN()
/hal_nxp-latest/mcux/mcux-sdk/boards/lpcxpresso54628/
Dclock_config.c99 …CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false); /*!< Reset divider counter and set … in BOARD_BootClockFRO12M()
145 …CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false); /*!< Reset divider counter and set … in BOARD_BootClockFROHF48M()
193 …CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false); /*!< Reset divider counter and set … in BOARD_BootClockFROHF96M()
256 …CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false); /*!< Reset divider counter and set … in BOARD_BootClockPLL180M()
325 …CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false); /*!< Reset divider counter and set … in BOARD_BootClockPLL220M()
326 …CLOCK_SetClkDiv(kCLOCK_DivUsb0Clk, 0U, true); /*!< Reset USB0CLKDIV divider count… in BOARD_BootClockPLL220M()
327 …CLOCK_SetClkDiv(kCLOCK_DivUsb0Clk, 2U, false); /*!< Set USB0CLKDIV divider to val… in BOARD_BootClockPLL220M()
/hal_nxp-latest/mcux/mcux-sdk/boards/lpcxpresso54s018/
Dclock_config.c97 …CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false); /*!< Reset divider counter and set … in BOARD_BootClockFRO12M()
141 …CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false); /*!< Reset divider counter and set … in BOARD_BootClockFROHF48M()
187 …CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false); /*!< Reset divider counter and set … in BOARD_BootClockFROHF96M()
256 …CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false); /*!< Reset divider counter and set … in BOARD_BootClockPLL180M()
257 …CLOCK_SetClkDiv(kCLOCK_DivUsb0Clk, 0U, true); /*!< Reset USB0CLKDIV divider count… in BOARD_BootClockPLL180M()
258 …CLOCK_SetClkDiv(kCLOCK_DivUsb0Clk, 2U, false); /*!< Set USB0CLKDIV divider to val… in BOARD_BootClockPLL180M()
/hal_nxp-latest/mcux/mcux-sdk/boards/lpcxpresso55s36/
Dclock_config.c91 CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false); /*!< Set AHBCLKDIV divider to value 1 */ in BOARD_BootClockFRO12M()
141 CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false); /*!< Set AHBCLKDIV divider to value 1 */ in BOARD_BootClockFROHF96M()
216 CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false); /*!< Set AHBCLKDIV divider to value 1 */ in BOARD_BootClockPLL100M()
288 CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false); /*!< Set AHBCLKDIV divider to value 1 */ in BOARD_BootClockPLL150M()
358 CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false); /*!< Set AHBCLKDIV divider to value 1 */ in BOARD_BootClockPLL1_150M()
/hal_nxp-latest/mcux/mcux-sdk/boards/lpcxpresso55s16/
Dclock_config.c96 CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false); /*!< Set AHBCLKDIV divider to value 1 */ in BOARD_BootClockFRO12M()
145 CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false); /*!< Set AHBCLKDIV divider to value 1 */ in BOARD_BootClockFROHF96M()
223 CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false); /*!< Set AHBCLKDIV divider to value 1 */ in BOARD_BootClockPLL100M()
298 CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false); /*!< Set AHBCLKDIV divider to value 1 */ in BOARD_BootClockPLL150M()
371 CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false); /*!< Set AHBCLKDIV divider to value 1 */ in BOARD_BootClockPLL1_150M()
/hal_nxp-latest/mcux/mcux-sdk/boards/lpcxpresso55s28/
Dclock_config.c94 CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false); /*!< Set AHBCLKDIV divider to value 1 */ in BOARD_BootClockFRO12M()
142 CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false); /*!< Set AHBCLKDIV divider to value 1 */ in BOARD_BootClockFROHF96M()
219 CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false); /*!< Set AHBCLKDIV divider to value 1 */ in BOARD_BootClockPLL100M()
293 CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false); /*!< Set AHBCLKDIV divider to value 1 */ in BOARD_BootClockPLL150M()
365 CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false); /*!< Set AHBCLKDIV divider to value 1 */ in BOARD_BootClockPLL1_150M()
/hal_nxp-latest/mcux/mcux-sdk/boards/lpcxpresso55s69/
Dclock_config.c94 CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false); /*!< Set AHBCLKDIV divider to value 1 */ in BOARD_BootClockFRO12M()
142 CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false); /*!< Set AHBCLKDIV divider to value 1 */ in BOARD_BootClockFROHF96M()
219 CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false); /*!< Set AHBCLKDIV divider to value 1 */ in BOARD_BootClockPLL100M()
293 CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false); /*!< Set AHBCLKDIV divider to value 1 */ in BOARD_BootClockPLL150M()
365 CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false); /*!< Set AHBCLKDIV divider to value 1 */ in BOARD_BootClockPLL1_150M()
/hal_nxp-latest/mcux/mcux-sdk/boards/mcxn5xxevk/
Dclock_config.c121 CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U); /*!< Set AHBCLKDIV divider to value 1 */ in BOARD_BootClockFRO12M()
190 CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U); /*!< Set AHBCLKDIV divider to value 1 */ in BOARD_BootClockFROHF48M()
263 CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U); /*!< Set AHBCLKDIV divider to value 1 */ in BOARD_BootClockFROHF144M()
352 CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U); /*!< Set AHBCLKDIV divider to value 1 */ in BOARD_BootClockPLL150M()
446 CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U); /*!< Set AHBCLKDIV divider to value 1 */ in BOARD_BootClockPLL100M()
/hal_nxp-latest/mcux/mcux-sdk/boards/frdmmcxn236/
Dclock_config.c121 CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U); /*!< Set AHBCLKDIV divider to value 1 */ in BOARD_BootClockFRO12M()
189 CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U); /*!< Set AHBCLKDIV divider to value 1 */ in BOARD_BootClockFROHF48M()
261 CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U); /*!< Set AHBCLKDIV divider to value 1 */ in BOARD_BootClockFROHF144M()
349 CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U); /*!< Set AHBCLKDIV divider to value 1 */ in BOARD_BootClockPLL150M()
443 CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U); /*!< Set AHBCLKDIV divider to value 1 */ in BOARD_BootClockPLL100M()
/hal_nxp-latest/mcux/mcux-sdk/boards/frdmmcxn947/
Dclock_config.c121 CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U); /*!< Set AHBCLKDIV divider to value 1 */ in BOARD_BootClockFRO12M()
190 CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U); /*!< Set AHBCLKDIV divider to value 1 */ in BOARD_BootClockFROHF48M()
263 CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U); /*!< Set AHBCLKDIV divider to value 1 */ in BOARD_BootClockFROHF144M()
352 CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U); /*!< Set AHBCLKDIV divider to value 1 */ in BOARD_BootClockPLL150M()
446 CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U); /*!< Set AHBCLKDIV divider to value 1 */ in BOARD_BootClockPLL100M()
/hal_nxp-latest/mcux/mcux-sdk/boards/mcxn9xxevk/
Dclock_config.c121 CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U); /*!< Set AHBCLKDIV divider to value 1 */ in BOARD_BootClockFRO12M()
190 CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U); /*!< Set AHBCLKDIV divider to value 1 */ in BOARD_BootClockFROHF48M()
263 CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U); /*!< Set AHBCLKDIV divider to value 1 */ in BOARD_BootClockFROHF144M()
352 CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U); /*!< Set AHBCLKDIV divider to value 1 */ in BOARD_BootClockPLL150M()
446 CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U); /*!< Set AHBCLKDIV divider to value 1 */ in BOARD_BootClockPLL100M()
/hal_nxp-latest/mcux/mcux-sdk/boards/evkmimxrt685/
Dclock_config.c189 CLOCK_SetClkDiv(kCLOCK_DivSysCpuAhbClk, 2U); /* Set SYSCPUAHBCLKDIV divider to value 2 */ in BOARD_BootClockRUN()
195 CLOCK_SetClkDiv(kCLOCK_DivAudioPllClk, 15U); /* Set AUDIOPLLCLKDIV divider to value 15 */ in BOARD_BootClockRUN()
196 CLOCK_SetClkDiv(kCLOCK_DivPfc0Clk, 2U); /* Set PFC0DIV divider to value 2 */ in BOARD_BootClockRUN()
197 CLOCK_SetClkDiv(kCLOCK_DivPllFrgClk, 12U); /* Set FRGPLLCLKDIV divider to value 12 */ in BOARD_BootClockRUN()
/hal_nxp-latest/mcux/mcux-sdk/boards/lpcxpresso54s018m/
Dclock_config.c96 …CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false); /*!< Reset divider counter and set … in BOARD_BootClockFRO12M()
140 …CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false); /*!< Reset divider counter and set … in BOARD_BootClockFROHF48M()
187 …CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false); /*!< Reset divider counter and set … in BOARD_BootClockFROHF96M()
248 …CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false); /*!< Reset divider counter and set … in BOARD_BootClockPLL180M()
/hal_nxp-latest/mcux/mcux-sdk/boards/lpcxpresso54114/
Dclock_config.c92 CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false); /*!< Set AHBCLKDIV divider to value 1 */ in BOARD_BootClockFRO12M()
137 CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false); /*!< Set AHBCLKDIV divider to value 1 */ in BOARD_BootClockFROHF48M()
184 CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false); /*!< Set AHBCLKDIV divider to value 1 */ in BOARD_BootClockFROHF96M()
247 CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false); /*!< Set AHBCLKDIV divider to value 1 */ in BOARD_BootClockPLL150M()
/hal_nxp-latest/mcux/mcux-sdk/boards/mimxrt685audevk/
Dclock_config.c189 CLOCK_SetClkDiv(kCLOCK_DivSysCpuAhbClk, 2U); /* Set SYSCPUAHBCLKDIV divider to value 2 */ in BOARD_BootClockRUN()
195 CLOCK_SetClkDiv(kCLOCK_DivAudioPllClk, 15U); /* Set AUDIOPLLCLKDIV divider to value 15 */ in BOARD_BootClockRUN()
196 CLOCK_SetClkDiv(kCLOCK_DivPfc0Clk, 2U); /* Set PFC0DIV divider to value 2 */ in BOARD_BootClockRUN()
197 CLOCK_SetClkDiv(kCLOCK_DivPllFrgClk, 12U); /* Set FRGPLLCLKDIV divider to value 12 */ in BOARD_BootClockRUN()
/hal_nxp-latest/mcux/mcux-sdk/boards/lpcxpresso51u68/
Dclock_config.c83 …CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false); /*!< Set AHBCLKDIV divider to value… in BOARD_BootClockFRO12M()
123 …CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false); /*!< Set AHBCLKDIV divider to value… in BOARD_BootClockFROHF48M()
165 …CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false); /*!< Set AHBCLKDIV divider to value… in BOARD_BootClockFROHF96M()
230 …CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false); /*!< Set AHBCLKDIV divider to value… in BOARD_BootClockPLL150M()
/hal_nxp-latest/mcux/mcux-sdk/boards/lpcxpresso55s06cp/
Dclock_config.c95 CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false); /*!< Set AHBCLKDIV divider to value 1 */ in BOARD_BootClockFRO12M()
145 CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false); /*!< Set AHBCLKDIV divider to value 1 */ in BOARD_BootClockFROHF96M()
219 CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false); /*!< Set AHBCLKDIV divider to value 1 */ in BOARD_BootClockPLL96M()
284 CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false); /*!< Set AHBCLKDIV divider to value 1 */ in BOARD_BootClockPLL150M()
/hal_nxp-latest/mcux/mcux-sdk/boards/lpcxpresso55s06/
Dclock_config.c93 CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false); /*!< Set AHBCLKDIV divider to value 1 */ in BOARD_BootClockFRO12M()
143 CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false); /*!< Set AHBCLKDIV divider to value 1 */ in BOARD_BootClockFROHF96M()
217 CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false); /*!< Set AHBCLKDIV divider to value 1 */ in BOARD_BootClockPLL96M()
/hal_nxp-latest/mcux/mcux-sdk/devices/LPC54606/drivers/
Dfsl_clock.c244 void CLOCK_SetClkDiv(clock_div_name_t div_name, uint32_t divided_by_value, bool reset) in CLOCK_SetClkDiv() function
2634 … CLOCK_SetClkDiv(kCLOCK_DivUsb0Clk, 2, false); /*!< Div by 2 to get 48MHz, no divider reset */ in CLOCK_EnableUsbfs0DeviceClock()
2638 … CLOCK_SetClkDiv(kCLOCK_DivUsb0Clk, 1, false); /*!< Div by 1 to get 48MHz, no divider reset */ in CLOCK_EnableUsbfs0DeviceClock()
2659 CLOCK_SetClkDiv(kCLOCK_DivUsb0Clk, 1U, false); in CLOCK_EnableUsbfs0DeviceClock()
2687 … CLOCK_SetClkDiv(kCLOCK_DivUsb0Clk, 2, false); /*!< Div by 2 to get 48MHz, no divider reset */ in CLOCK_EnableUsbfs0HostClock()
2691 … CLOCK_SetClkDiv(kCLOCK_DivUsb0Clk, 1, false); /*!< Div by 1 to get 48MHz, no divider reset */ in CLOCK_EnableUsbfs0HostClock()
2712 CLOCK_SetClkDiv(kCLOCK_DivUsb0Clk, 1U, false); in CLOCK_EnableUsbfs0HostClock()
2740 … CLOCK_SetClkDiv(kCLOCK_DivUsb1Clk, 2, false); /*!< Div by 2 to get 48MHz, no divider reset */ in CLOCK_EnableUsbhs0DeviceClock()
2744 … CLOCK_SetClkDiv(kCLOCK_DivUsb1Clk, 1, false); /*!< Div by 1 to get 48MHz, no divider reset */ in CLOCK_EnableUsbhs0DeviceClock()
2765 CLOCK_SetClkDiv(kCLOCK_DivUsb1Clk, 1U, false); in CLOCK_EnableUsbhs0DeviceClock()
[all …]
/hal_nxp-latest/mcux/mcux-sdk/devices/LPC54S018M/drivers/
Dfsl_clock.c317 void CLOCK_SetClkDiv(clock_div_name_t div_name, uint32_t divided_by_value, bool reset) in CLOCK_SetClkDiv() function
2632 … CLOCK_SetClkDiv(kCLOCK_DivUsb0Clk, 2U, false); /*!< Div by 2 to get 48MHz, no divider reset */ in CLOCK_EnableUsbfs0DeviceClock()
2636 … CLOCK_SetClkDiv(kCLOCK_DivUsb0Clk, 1U, false); /*!< Div by 1 to get 48MHz, no divider reset */ in CLOCK_EnableUsbfs0DeviceClock()
2657 CLOCK_SetClkDiv(kCLOCK_DivUsb0Clk, 1U, false); in CLOCK_EnableUsbfs0DeviceClock()
2685 … CLOCK_SetClkDiv(kCLOCK_DivUsb0Clk, 2U, false); /*!< Div by 2 to get 48MHz, no divider reset */ in CLOCK_EnableUsbfs0HostClock()
2689 … CLOCK_SetClkDiv(kCLOCK_DivUsb0Clk, 1U, false); /*!< Div by 1 to get 48MHz, no divider reset */ in CLOCK_EnableUsbfs0HostClock()
2710 CLOCK_SetClkDiv(kCLOCK_DivUsb0Clk, 1U, false); in CLOCK_EnableUsbfs0HostClock()
2738 … CLOCK_SetClkDiv(kCLOCK_DivUsb1Clk, 2U, false); /*!< Div by 2 to get 48MHz, no divider reset */ in CLOCK_EnableUsbhs0DeviceClock()
2742 … CLOCK_SetClkDiv(kCLOCK_DivUsb1Clk, 1U, false); /*!< Div by 1 to get 48MHz, no divider reset */ in CLOCK_EnableUsbhs0DeviceClock()
2763 CLOCK_SetClkDiv(kCLOCK_DivUsb1Clk, 1U, false); in CLOCK_EnableUsbhs0DeviceClock()
[all …]
/hal_nxp-latest/mcux/mcux-sdk/devices/LPC54018/drivers/
Dfsl_clock.c317 void CLOCK_SetClkDiv(clock_div_name_t div_name, uint32_t divided_by_value, bool reset) in CLOCK_SetClkDiv() function
2632 … CLOCK_SetClkDiv(kCLOCK_DivUsb0Clk, 2U, false); /*!< Div by 2 to get 48MHz, no divider reset */ in CLOCK_EnableUsbfs0DeviceClock()
2636 … CLOCK_SetClkDiv(kCLOCK_DivUsb0Clk, 1U, false); /*!< Div by 1 to get 48MHz, no divider reset */ in CLOCK_EnableUsbfs0DeviceClock()
2657 CLOCK_SetClkDiv(kCLOCK_DivUsb0Clk, 1U, false); in CLOCK_EnableUsbfs0DeviceClock()
2685 … CLOCK_SetClkDiv(kCLOCK_DivUsb0Clk, 2U, false); /*!< Div by 2 to get 48MHz, no divider reset */ in CLOCK_EnableUsbfs0HostClock()
2689 … CLOCK_SetClkDiv(kCLOCK_DivUsb0Clk, 1U, false); /*!< Div by 1 to get 48MHz, no divider reset */ in CLOCK_EnableUsbfs0HostClock()
2710 CLOCK_SetClkDiv(kCLOCK_DivUsb0Clk, 1U, false); in CLOCK_EnableUsbfs0HostClock()
2738 … CLOCK_SetClkDiv(kCLOCK_DivUsb1Clk, 2U, false); /*!< Div by 2 to get 48MHz, no divider reset */ in CLOCK_EnableUsbhs0DeviceClock()
2742 … CLOCK_SetClkDiv(kCLOCK_DivUsb1Clk, 1U, false); /*!< Div by 1 to get 48MHz, no divider reset */ in CLOCK_EnableUsbhs0DeviceClock()
2763 CLOCK_SetClkDiv(kCLOCK_DivUsb1Clk, 1U, false); in CLOCK_EnableUsbhs0DeviceClock()
[all …]
/hal_nxp-latest/mcux/mcux-sdk/devices/LPC54S016/drivers/
Dfsl_clock.c316 void CLOCK_SetClkDiv(clock_div_name_t div_name, uint32_t divided_by_value, bool reset) in CLOCK_SetClkDiv() function
2623 … CLOCK_SetClkDiv(kCLOCK_DivUsb0Clk, 2U, false); /*!< Div by 2 to get 48MHz, no divider reset */ in CLOCK_EnableUsbfs0DeviceClock()
2627 … CLOCK_SetClkDiv(kCLOCK_DivUsb0Clk, 1U, false); /*!< Div by 1 to get 48MHz, no divider reset */ in CLOCK_EnableUsbfs0DeviceClock()
2648 CLOCK_SetClkDiv(kCLOCK_DivUsb0Clk, 1U, false); in CLOCK_EnableUsbfs0DeviceClock()
2676 … CLOCK_SetClkDiv(kCLOCK_DivUsb0Clk, 2U, false); /*!< Div by 2 to get 48MHz, no divider reset */ in CLOCK_EnableUsbfs0HostClock()
2680 … CLOCK_SetClkDiv(kCLOCK_DivUsb0Clk, 1U, false); /*!< Div by 1 to get 48MHz, no divider reset */ in CLOCK_EnableUsbfs0HostClock()
2701 CLOCK_SetClkDiv(kCLOCK_DivUsb0Clk, 1U, false); in CLOCK_EnableUsbfs0HostClock()
2729 … CLOCK_SetClkDiv(kCLOCK_DivUsb1Clk, 2U, false); /*!< Div by 2 to get 48MHz, no divider reset */ in CLOCK_EnableUsbhs0DeviceClock()
2733 … CLOCK_SetClkDiv(kCLOCK_DivUsb1Clk, 1U, false); /*!< Div by 1 to get 48MHz, no divider reset */ in CLOCK_EnableUsbhs0DeviceClock()
2754 CLOCK_SetClkDiv(kCLOCK_DivUsb1Clk, 1U, false); in CLOCK_EnableUsbhs0DeviceClock()
[all …]

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