Lines Matching refs:CLOCK_SetClkDiv

145     CLOCK_SetClkDiv(kCLOCK_DivSysCpuAhbClk, 1);  in BOARD_BootClockRUN()
161     CLOCK_SetClkDiv(kCLOCK_DivAudioPllClk, 1U);         /* Set .AUDIOPLLCLKDIV divider to value 1 */  in BOARD_BootClockRUN()
162     CLOCK_SetClkDiv(kCLOCK_DivPllFrgClk, 13U);         /* Set .FRGPLLCLKDIV divider to value 13 */  in BOARD_BootClockRUN()
163     CLOCK_SetClkDiv(kCLOCK_DivMainPllClk, 1U);         /* Set .MAINPLLCLKDIV divider to value 1 */  in BOARD_BootClockRUN()
164     CLOCK_SetClkDiv(kCLOCK_DivAux0PllClk, 1U);         /* Set .AUX0PLLCLKDIV divider to value 1 */  in BOARD_BootClockRUN()
165     CLOCK_SetClkDiv(kCLOCK_DivSystickClk, 1U);         /* Set .SYSTICKFCLKDIV divider to value 1 */  in BOARD_BootClockRUN()
166     CLOCK_SetClkDiv(kCLOCK_DivPmuFclk, 5U);         /* Set .PMUFCLKDIV divider to value 5 */  in BOARD_BootClockRUN()
252     CLOCK_SetClkDiv(kCLOCK_DivSysCpuAhbClk, 1);  in BOARD_BootClockLPR()
262     CLOCK_SetClkDiv(kCLOCK_DivPllFrgClk, 13U);         /* Set .FRGPLLCLKDIV divider to value 13 */  in BOARD_BootClockLPR()
263     CLOCK_SetClkDiv(kCLOCK_DivMainPllClk, 1U);         /* Set .MAINPLLCLKDIV divider to value 1 */  in BOARD_BootClockLPR()
264     CLOCK_SetClkDiv(kCLOCK_DivAux0PllClk, 1U);         /* Set .AUX0PLLCLKDIV divider to value 1 */  in BOARD_BootClockLPR()
265     CLOCK_SetClkDiv(kCLOCK_DivSystickClk, 1U);         /* Set .SYSTICKFCLKDIV divider to value 1 */  in BOARD_BootClockLPR()
266     CLOCK_SetClkDiv(kCLOCK_DivPmuFclk, 5U);         /* Set .PMUFCLKDIV divider to value 5 */  in BOARD_BootClockLPR()