1 /*
2 * Copyright 2017-2019 ,2021 NXP
3 * All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7
8 /***********************************************************************************************************************
9 * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
10 * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
11 **********************************************************************************************************************/
12 /*
13 * How to set up clock using clock driver functions:
14 *
15 * 1. Setup clock sources.
16 *
17 * 2. Set up wait states of the flash.
18 *
19 * 3. Set up all dividers.
20 *
21 * 4. Set up all selectors to provide selected clocks.
22 */
23
24 /* clang-format off */
25 /* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
26 !!GlobalInfo
27 product: Clocks v7.0
28 processor: LPC55S69
29 package_id: LPC55S69JBD100
30 mcu_data: ksdk2_0
31 processor_version: 9.0.0
32 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
33 /* clang-format on */
34
35 #include "fsl_power.h"
36 #include "fsl_clock.h"
37 #include "clock_config.h"
38
39 /*******************************************************************************
40 * Definitions
41 ******************************************************************************/
42
43 /*******************************************************************************
44 * Variables
45 ******************************************************************************/
46 /* System clock frequency. */
47 extern uint32_t SystemCoreClock;
48
49 /*******************************************************************************
50 ************************ BOARD_InitBootClocks function ************************
51 ******************************************************************************/
BOARD_InitBootClocks(void)52 void BOARD_InitBootClocks(void)
53 {
54 BOARD_BootClockPLL150M();
55 }
56
57 /*******************************************************************************
58 ******************** Configuration BOARD_BootClockFRO12M **********************
59 ******************************************************************************/
60 /* clang-format off */
61 /* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
62 !!Configuration
63 name: BOARD_BootClockFRO12M
64 outputs:
65 - {id: System_clock.outFreq, value: 12 MHz}
66 settings:
67 - {id: ANALOG_CONTROL_FRO192M_CTRL_ENDI_FRO_96M_CFG, value: Enable}
68 sources:
69 - {id: ANACTRL.fro_hf.outFreq, value: 96 MHz}
70 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
71 /* clang-format on */
72
73 /*******************************************************************************
74 * Variables for BOARD_BootClockFRO12M configuration
75 ******************************************************************************/
76 /*******************************************************************************
77 * Code for BOARD_BootClockFRO12M configuration
78 ******************************************************************************/
BOARD_BootClockFRO12M(void)79 void BOARD_BootClockFRO12M(void)
80 {
81 #ifndef SDK_SECONDARY_CORE
82 /*!< Set up the clock sources */
83 /*!< Configure FRO192M */
84 POWER_DisablePD(kPDRUNCFG_PD_FRO192M); /*!< Ensure FRO is on */
85 CLOCK_SetupFROClocking(12000000U); /*!< Set up FRO to the 12 MHz, just for sure */
86 CLOCK_AttachClk(kFRO12M_to_MAIN_CLK); /*!< Switch to FRO 12MHz first to ensure we can change the clock setting */
87
88 CLOCK_SetupFROClocking(96000000U); /* Enable FRO HF(96MHz) output */
89
90 POWER_SetVoltageForFreq(12000000U); /*!< Set voltage for the one of the fastest clock outputs: System clock output */
91 CLOCK_SetFLASHAccessCyclesForFreq(12000000U); /*!< Set FLASH wait states for core */
92
93 /*!< Set up dividers */
94 CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false); /*!< Set AHBCLKDIV divider to value 1 */
95
96 /*!< Set up clock selectors - Attach clocks to the peripheries */
97 CLOCK_AttachClk(kFRO12M_to_MAIN_CLK); /*!< Switch MAIN_CLK to FRO12M */
98
99 /*< Set SystemCoreClock variable. */
100 SystemCoreClock = BOARD_BOOTCLOCKFRO12M_CORE_CLOCK;
101 #endif
102 }
103
104 /*******************************************************************************
105 ******************* Configuration BOARD_BootClockFROHF96M *********************
106 ******************************************************************************/
107 /* clang-format off */
108 /* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
109 !!Configuration
110 name: BOARD_BootClockFROHF96M
111 outputs:
112 - {id: System_clock.outFreq, value: 96 MHz}
113 settings:
114 - {id: ANALOG_CONTROL_FRO192M_CTRL_ENDI_FRO_96M_CFG, value: Enable}
115 - {id: SYSCON.MAINCLKSELA.sel, value: ANACTRL.fro_hf_clk}
116 sources:
117 - {id: ANACTRL.fro_hf.outFreq, value: 96 MHz}
118 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
119 /* clang-format on */
120
121 /*******************************************************************************
122 * Variables for BOARD_BootClockFROHF96M configuration
123 ******************************************************************************/
124 /*******************************************************************************
125 * Code for BOARD_BootClockFROHF96M configuration
126 ******************************************************************************/
BOARD_BootClockFROHF96M(void)127 void BOARD_BootClockFROHF96M(void)
128 {
129 #ifndef SDK_SECONDARY_CORE
130 /*!< Set up the clock sources */
131 /*!< Configure FRO192M */
132 POWER_DisablePD(kPDRUNCFG_PD_FRO192M); /*!< Ensure FRO is on */
133 CLOCK_SetupFROClocking(12000000U); /*!< Set up FRO to the 12 MHz, just for sure */
134 CLOCK_AttachClk(kFRO12M_to_MAIN_CLK); /*!< Switch to FRO 12MHz first to ensure we can change the clock setting */
135
136 CLOCK_SetupFROClocking(96000000U); /* Enable FRO HF(96MHz) output */
137
138 POWER_SetVoltageForFreq(96000000U); /*!< Set voltage for the one of the fastest clock outputs: System clock output */
139 CLOCK_SetFLASHAccessCyclesForFreq(96000000U); /*!< Set FLASH wait states for core */
140
141 /*!< Set up dividers */
142 CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false); /*!< Set AHBCLKDIV divider to value 1 */
143
144 /*!< Set up clock selectors - Attach clocks to the peripheries */
145 CLOCK_AttachClk(kFRO_HF_to_MAIN_CLK); /*!< Switch MAIN_CLK to FRO_HF */
146
147 /*< Set SystemCoreClock variable. */
148 SystemCoreClock = BOARD_BOOTCLOCKFROHF96M_CORE_CLOCK;
149 #endif
150 }
151
152 /*******************************************************************************
153 ******************** Configuration BOARD_BootClockPLL100M *********************
154 ******************************************************************************/
155 /* clang-format off */
156 /* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
157 !!Configuration
158 name: BOARD_BootClockPLL100M
159 outputs:
160 - {id: System_clock.outFreq, value: 100 MHz}
161 settings:
162 - {id: PLL0_Mode, value: Normal}
163 - {id: ANALOG_CONTROL_FRO192M_CTRL_ENDI_FRO_96M_CFG, value: Enable}
164 - {id: ENABLE_CLKIN_ENA, value: Enabled}
165 - {id: ENABLE_SYSTEM_CLK_OUT, value: Enabled}
166 - {id: SYSCON.MAINCLKSELB.sel, value: SYSCON.PLL0_BYPASS}
167 - {id: SYSCON.PLL0CLKSEL.sel, value: SYSCON.CLK_IN_EN}
168 - {id: SYSCON.PLL0M_MULT.scale, value: '100', locked: true}
169 - {id: SYSCON.PLL0N_DIV.scale, value: '4', locked: true}
170 - {id: SYSCON.PLL0_PDEC.scale, value: '4', locked: true}
171 sources:
172 - {id: ANACTRL.fro_hf.outFreq, value: 96 MHz}
173 - {id: SYSCON.XTAL32M.outFreq, value: 16 MHz, enabled: true}
174 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
175 /* clang-format on */
176
177 /*******************************************************************************
178 * Variables for BOARD_BootClockPLL100M configuration
179 ******************************************************************************/
180 /*******************************************************************************
181 * Code for BOARD_BootClockPLL100M configuration
182 ******************************************************************************/
BOARD_BootClockPLL100M(void)183 void BOARD_BootClockPLL100M(void)
184 {
185 #ifndef SDK_SECONDARY_CORE
186 /*!< Set up the clock sources */
187 /*!< Configure FRO192M */
188 POWER_DisablePD(kPDRUNCFG_PD_FRO192M); /*!< Ensure FRO is on */
189 CLOCK_SetupFROClocking(12000000U); /*!< Set up FRO to the 12 MHz, just for sure */
190 CLOCK_AttachClk(kFRO12M_to_MAIN_CLK); /*!< Switch to FRO 12MHz first to ensure we can change the clock setting */
191
192 CLOCK_SetupFROClocking(96000000U); /* Enable FRO HF(96MHz) output */
193
194 /*!< Configure XTAL32M */
195 POWER_DisablePD(kPDRUNCFG_PD_XTAL32M); /* Ensure XTAL32M is powered */
196 POWER_DisablePD(kPDRUNCFG_PD_LDOXO32M); /* Ensure XTAL32M is powered */
197 CLOCK_SetupExtClocking(16000000U); /* Enable clk_in clock */
198 SYSCON->CLOCK_CTRL |= SYSCON_CLOCK_CTRL_CLKIN_ENA_MASK; /* Enable clk_in from XTAL32M clock */
199 ANACTRL->XO32M_CTRL |= ANACTRL_XO32M_CTRL_ENABLE_SYSTEM_CLK_OUT_MASK; /* Enable clk_in to system */
200
201 POWER_SetVoltageForFreq(100000000U); /*!< Set voltage for the one of the fastest clock outputs: System clock output */
202 CLOCK_SetFLASHAccessCyclesForFreq(100000000U); /*!< Set FLASH wait states for core */
203
204 /*!< Set up PLL */
205 CLOCK_AttachClk(kEXT_CLK_to_PLL0); /*!< Switch PLL0CLKSEL to EXT_CLK */
206 POWER_DisablePD(kPDRUNCFG_PD_PLL0); /* Ensure PLL is on */
207 POWER_DisablePD(kPDRUNCFG_PD_PLL0_SSCG);
208 const pll_setup_t pll0Setup = {
209 .pllctrl = SYSCON_PLL0CTRL_CLKEN_MASK | SYSCON_PLL0CTRL_SELI(53U) | SYSCON_PLL0CTRL_SELP(26U),
210 .pllndec = SYSCON_PLL0NDEC_NDIV(4U),
211 .pllpdec = SYSCON_PLL0PDEC_PDIV(2U),
212 .pllsscg = {0x0U,(SYSCON_PLL0SSCG1_MDIV_EXT(100U) | SYSCON_PLL0SSCG1_SEL_EXT_MASK)},
213 .pllRate = 100000000U,
214 .flags = PLL_SETUPFLAG_WAITLOCK
215 };
216 CLOCK_SetPLL0Freq(&pll0Setup); /*!< Configure PLL0 to the desired values */
217
218 /*!< Set up dividers */
219 CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false); /*!< Set AHBCLKDIV divider to value 1 */
220
221 /*!< Set up clock selectors - Attach clocks to the peripheries */
222 CLOCK_AttachClk(kPLL0_to_MAIN_CLK); /*!< Switch MAIN_CLK to PLL0 */
223
224 /*< Set SystemCoreClock variable. */
225 SystemCoreClock = BOARD_BOOTCLOCKPLL100M_CORE_CLOCK;
226 #endif
227 }
228
229 /*******************************************************************************
230 ******************** Configuration BOARD_BootClockPLL150M *********************
231 ******************************************************************************/
232 /* clang-format off */
233 /* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
234 !!Configuration
235 name: BOARD_BootClockPLL150M
236 called_from_default_init: true
237 outputs:
238 - {id: System_clock.outFreq, value: 150 MHz}
239 settings:
240 - {id: PLL0_Mode, value: Normal}
241 - {id: ENABLE_CLKIN_ENA, value: Enabled}
242 - {id: ENABLE_SYSTEM_CLK_OUT, value: Enabled}
243 - {id: SYSCON.MAINCLKSELB.sel, value: SYSCON.PLL0_BYPASS}
244 - {id: SYSCON.PLL0CLKSEL.sel, value: SYSCON.CLK_IN_EN}
245 - {id: SYSCON.PLL0M_MULT.scale, value: '150', locked: true}
246 - {id: SYSCON.PLL0N_DIV.scale, value: '8', locked: true}
247 - {id: SYSCON.PLL0_PDEC.scale, value: '2', locked: true}
248 sources:
249 - {id: SYSCON.XTAL32M.outFreq, value: 16 MHz, enabled: true}
250 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
251 /* clang-format on */
252
253 /*******************************************************************************
254 * Variables for BOARD_BootClockPLL150M configuration
255 ******************************************************************************/
256 /*******************************************************************************
257 * Code for BOARD_BootClockPLL150M configuration
258 ******************************************************************************/
BOARD_BootClockPLL150M(void)259 void BOARD_BootClockPLL150M(void)
260 {
261 #ifndef SDK_SECONDARY_CORE
262 /*!< Set up the clock sources */
263 /*!< Configure FRO192M */
264 POWER_DisablePD(kPDRUNCFG_PD_FRO192M); /*!< Ensure FRO is on */
265 CLOCK_SetupFROClocking(12000000U); /*!< Set up FRO to the 12 MHz, just for sure */
266 CLOCK_AttachClk(kFRO12M_to_MAIN_CLK); /*!< Switch to FRO 12MHz first to ensure we can change the clock setting */
267
268 /*!< Configure XTAL32M */
269 POWER_DisablePD(kPDRUNCFG_PD_XTAL32M); /* Ensure XTAL32M is powered */
270 POWER_DisablePD(kPDRUNCFG_PD_LDOXO32M); /* Ensure XTAL32M is powered */
271 CLOCK_SetupExtClocking(16000000U); /* Enable clk_in clock */
272 SYSCON->CLOCK_CTRL |= SYSCON_CLOCK_CTRL_CLKIN_ENA_MASK; /* Enable clk_in from XTAL32M clock */
273 ANACTRL->XO32M_CTRL |= ANACTRL_XO32M_CTRL_ENABLE_SYSTEM_CLK_OUT_MASK; /* Enable clk_in to system */
274
275 POWER_SetVoltageForFreq(150000000U); /*!< Set voltage for the one of the fastest clock outputs: System clock output */
276 CLOCK_SetFLASHAccessCyclesForFreq(150000000U); /*!< Set FLASH wait states for core */
277
278 /*!< Set up PLL */
279 CLOCK_AttachClk(kEXT_CLK_to_PLL0); /*!< Switch PLL0CLKSEL to EXT_CLK */
280 POWER_DisablePD(kPDRUNCFG_PD_PLL0); /* Ensure PLL is on */
281 POWER_DisablePD(kPDRUNCFG_PD_PLL0_SSCG);
282 const pll_setup_t pll0Setup = {
283 .pllctrl = SYSCON_PLL0CTRL_CLKEN_MASK | SYSCON_PLL0CTRL_SELI(53U) | SYSCON_PLL0CTRL_SELP(31U),
284 .pllndec = SYSCON_PLL0NDEC_NDIV(8U),
285 .pllpdec = SYSCON_PLL0PDEC_PDIV(1U),
286 .pllsscg = {0x0U,(SYSCON_PLL0SSCG1_MDIV_EXT(150U) | SYSCON_PLL0SSCG1_SEL_EXT_MASK)},
287 .pllRate = 150000000U,
288 .flags = PLL_SETUPFLAG_WAITLOCK
289 };
290 CLOCK_SetPLL0Freq(&pll0Setup); /*!< Configure PLL0 to the desired values */
291
292 /*!< Set up dividers */
293 CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false); /*!< Set AHBCLKDIV divider to value 1 */
294
295 /*!< Set up clock selectors - Attach clocks to the peripheries */
296 CLOCK_AttachClk(kPLL0_to_MAIN_CLK); /*!< Switch MAIN_CLK to PLL0 */
297
298 /*< Set SystemCoreClock variable. */
299 SystemCoreClock = BOARD_BOOTCLOCKPLL150M_CORE_CLOCK;
300 #endif
301 }
302
303 /*******************************************************************************
304 ******************* Configuration BOARD_BootClockPLL1_150M ********************
305 ******************************************************************************/
306 /* clang-format off */
307 /* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
308 !!Configuration
309 name: BOARD_BootClockPLL1_150M
310 outputs:
311 - {id: System_clock.outFreq, value: 150 MHz}
312 settings:
313 - {id: PLL1_Mode, value: Normal}
314 - {id: ENABLE_CLKIN_ENA, value: Enabled}
315 - {id: ENABLE_SYSTEM_CLK_OUT, value: Enabled}
316 - {id: SYSCON.MAINCLKSELB.sel, value: SYSCON.PLL1_BYPASS}
317 - {id: SYSCON.PLL1CLKSEL.sel, value: SYSCON.CLK_IN_EN}
318 - {id: SYSCON.PLL1M_MULT.scale, value: '150', locked: true}
319 - {id: SYSCON.PLL1N_DIV.scale, value: '8', locked: true}
320 - {id: SYSCON.PLL1_PDEC.scale, value: '2', locked: true}
321 sources:
322 - {id: SYSCON.XTAL32M.outFreq, value: 16 MHz, enabled: true}
323 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
324 /* clang-format on */
325
326 /*******************************************************************************
327 * Variables for BOARD_BootClockPLL1_150M configuration
328 ******************************************************************************/
329 /*******************************************************************************
330 * Code for BOARD_BootClockPLL1_150M configuration
331 ******************************************************************************/
BOARD_BootClockPLL1_150M(void)332 void BOARD_BootClockPLL1_150M(void)
333 {
334 #ifndef SDK_SECONDARY_CORE
335 /*!< Set up the clock sources */
336 /*!< Configure FRO192M */
337 POWER_DisablePD(kPDRUNCFG_PD_FRO192M); /*!< Ensure FRO is on */
338 CLOCK_SetupFROClocking(12000000U); /*!< Set up FRO to the 12 MHz, just for sure */
339 CLOCK_AttachClk(kFRO12M_to_MAIN_CLK); /*!< Switch to FRO 12MHz first to ensure we can change the clock setting */
340
341 /*!< Configure XTAL32M */
342 POWER_DisablePD(kPDRUNCFG_PD_XTAL32M); /* Ensure XTAL32M is powered */
343 POWER_DisablePD(kPDRUNCFG_PD_LDOXO32M); /* Ensure XTAL32M is powered */
344 CLOCK_SetupExtClocking(16000000U); /* Enable clk_in clock */
345 SYSCON->CLOCK_CTRL |= SYSCON_CLOCK_CTRL_CLKIN_ENA_MASK; /* Enable clk_in from XTAL32M clock */
346 ANACTRL->XO32M_CTRL |= ANACTRL_XO32M_CTRL_ENABLE_SYSTEM_CLK_OUT_MASK; /* Enable clk_in to system */
347
348 POWER_SetVoltageForFreq(150000000U); /*!< Set voltage for the one of the fastest clock outputs: System clock output */
349 CLOCK_SetFLASHAccessCyclesForFreq(150000000U); /*!< Set FLASH wait states for core */
350
351 /*!< Set up PLL1 */
352 CLOCK_AttachClk(kEXT_CLK_to_PLL1); /*!< Switch PLL1CLKSEL to EXT_CLK */
353 POWER_DisablePD(kPDRUNCFG_PD_PLL1); /* Ensure PLL is on */
354 const pll_setup_t pll1Setup = {
355 .pllctrl = SYSCON_PLL1CTRL_CLKEN_MASK | SYSCON_PLL1CTRL_SELI(53U) | SYSCON_PLL1CTRL_SELP(31U),
356 .pllndec = SYSCON_PLL1NDEC_NDIV(8U),
357 .pllpdec = SYSCON_PLL1PDEC_PDIV(1U),
358 .pllmdec = SYSCON_PLL1MDEC_MDIV(150U),
359 .pllRate = 150000000U,
360 .flags = PLL_SETUPFLAG_WAITLOCK
361 };
362 CLOCK_SetPLL1Freq(&pll1Setup); /*!< Configure PLL1 to the desired values */
363
364 /*!< Set up dividers */
365 CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false); /*!< Set AHBCLKDIV divider to value 1 */
366
367 /*!< Set up clock selectors - Attach clocks to the peripheries */
368 CLOCK_AttachClk(kPLL1_to_MAIN_CLK); /*!< Switch MAIN_CLK to PLL1 */
369
370 /*< Set SystemCoreClock variable. */
371 SystemCoreClock = BOARD_BOOTCLOCKPLL1_150M_CORE_CLOCK;
372 #endif
373 }
374
375
