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Searched refs:CCR (Results 1 – 25 of 355) sorted by relevance

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/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT735S/
Dsystem_MIMXRT735S_cm33_core0.c82 …if ((XCACHE1->CCR & XCACHE_CCR_ENCACHE_MASK) == 0U) /* set XCACHE if not configured for code bus.*/ in SystemInit()
85 XCACHE1->CCR = XCACHE_CCR_INVW1_MASK | XCACHE_CCR_INVW0_MASK; in SystemInit()
86 XCACHE1->CCR |= XCACHE_CCR_GO_MASK; in SystemInit()
88 while ((XCACHE1->CCR & XCACHE_CCR_GO_MASK) != 0U) in SystemInit()
92 XCACHE1->CCR = XCACHE_CCR_ENCACHE_MASK; in SystemInit()
99 if ((CACHE64_CTRL0->CCR & CACHE64_CTRL_CCR_ENCACHE_MASK) == 0U) in SystemInit()
105 CACHE64_CTRL0->CCR = CACHE64_CTRL_CCR_INVW0_MASK | CACHE64_CTRL_CCR_INVW1_MASK; in SystemInit()
106 CACHE64_CTRL0->CCR |= CACHE64_CTRL_CCR_GO_MASK; in SystemInit()
107 while ((CACHE64_CTRL0->CCR & CACHE64_CTRL_CCR_GO_MASK) != 0U) in SystemInit()
110 CACHE64_CTRL0->CCR = CACHE64_CTRL_CCR_ENCACHE_MASK; in SystemInit()
[all …]
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT798S/
Dsystem_MIMXRT798S_cm33_core0.c82 …if ((XCACHE1->CCR & XCACHE_CCR_ENCACHE_MASK) == 0U) /* set XCACHE if not configured for code bus.*/ in SystemInit()
85 XCACHE1->CCR = XCACHE_CCR_INVW1_MASK | XCACHE_CCR_INVW0_MASK; in SystemInit()
86 XCACHE1->CCR |= XCACHE_CCR_GO_MASK; in SystemInit()
88 while ((XCACHE1->CCR & XCACHE_CCR_GO_MASK) != 0U) in SystemInit()
92 XCACHE1->CCR = XCACHE_CCR_ENCACHE_MASK; in SystemInit()
99 if ((CACHE64_CTRL0->CCR & CACHE64_CTRL_CCR_ENCACHE_MASK) == 0U) in SystemInit()
105 CACHE64_CTRL0->CCR = CACHE64_CTRL_CCR_INVW0_MASK | CACHE64_CTRL_CCR_INVW1_MASK; in SystemInit()
106 CACHE64_CTRL0->CCR |= CACHE64_CTRL_CCR_GO_MASK; in SystemInit()
107 while ((CACHE64_CTRL0->CCR & CACHE64_CTRL_CCR_GO_MASK) != 0U) in SystemInit()
110 CACHE64_CTRL0->CCR = CACHE64_CTRL_CCR_ENCACHE_MASK; in SystemInit()
[all …]
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT758S/
Dsystem_MIMXRT758S_cm33_core0.c82 …if ((XCACHE1->CCR & XCACHE_CCR_ENCACHE_MASK) == 0U) /* set XCACHE if not configured for code bus.*/ in SystemInit()
85 XCACHE1->CCR = XCACHE_CCR_INVW1_MASK | XCACHE_CCR_INVW0_MASK; in SystemInit()
86 XCACHE1->CCR |= XCACHE_CCR_GO_MASK; in SystemInit()
88 while ((XCACHE1->CCR & XCACHE_CCR_GO_MASK) != 0U) in SystemInit()
92 XCACHE1->CCR = XCACHE_CCR_ENCACHE_MASK; in SystemInit()
99 if ((CACHE64_CTRL0->CCR & CACHE64_CTRL_CCR_ENCACHE_MASK) == 0U) in SystemInit()
105 CACHE64_CTRL0->CCR = CACHE64_CTRL_CCR_INVW0_MASK | CACHE64_CTRL_CCR_INVW1_MASK; in SystemInit()
106 CACHE64_CTRL0->CCR |= CACHE64_CTRL_CCR_GO_MASK; in SystemInit()
107 while ((CACHE64_CTRL0->CCR & CACHE64_CTRL_CCR_GO_MASK) != 0U) in SystemInit()
110 CACHE64_CTRL0->CCR = CACHE64_CTRL_CCR_ENCACHE_MASK; in SystemInit()
[all …]
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1181/drivers/cm33/
Dfsl_cache.c69 if ((base->CCR & XCACHE_CCR_ENCACHE_MASK) == 0x00U) in XCACHE_EnableCache()
75 base->CCR |= XCACHE_CCR_ENCACHE_MASK; in XCACHE_EnableCache()
85 if (XCACHE_CCR_ENCACHE_MASK == (XCACHE_CCR_ENCACHE_MASK & base->CCR)) in XCACHE_DisableCache()
91 base->CCR &= ~XCACHE_CCR_ENCACHE_MASK; in XCACHE_DisableCache()
102 base->CCR |= XCACHE_CCR_INVW0_MASK | XCACHE_CCR_INVW1_MASK | XCACHE_CCR_GO_MASK; in XCACHE_InvalidateCache()
105 while ((base->CCR & XCACHE_CCR_GO_MASK) != 0x00U) in XCACHE_InvalidateCache()
110 base->CCR &= ~(XCACHE_CCR_INVW0_MASK | XCACHE_CCR_INVW1_MASK); in XCACHE_InvalidateCache()
169 base->CCR |= XCACHE_CCR_PUSHW0_MASK | XCACHE_CCR_PUSHW1_MASK | XCACHE_CCR_GO_MASK; in XCACHE_CleanCache()
172 while ((base->CCR & XCACHE_CCR_GO_MASK) != 0x00U) in XCACHE_CleanCache()
177 base->CCR &= ~(XCACHE_CCR_PUSHW0_MASK | XCACHE_CCR_PUSHW1_MASK); in XCACHE_CleanCache()
[all …]
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1189/drivers/cm33/
Dfsl_cache.c69 if ((base->CCR & XCACHE_CCR_ENCACHE_MASK) == 0x00U) in XCACHE_EnableCache()
75 base->CCR |= XCACHE_CCR_ENCACHE_MASK; in XCACHE_EnableCache()
85 if (XCACHE_CCR_ENCACHE_MASK == (XCACHE_CCR_ENCACHE_MASK & base->CCR)) in XCACHE_DisableCache()
91 base->CCR &= ~XCACHE_CCR_ENCACHE_MASK; in XCACHE_DisableCache()
102 base->CCR |= XCACHE_CCR_INVW0_MASK | XCACHE_CCR_INVW1_MASK | XCACHE_CCR_GO_MASK; in XCACHE_InvalidateCache()
105 while ((base->CCR & XCACHE_CCR_GO_MASK) != 0x00U) in XCACHE_InvalidateCache()
110 base->CCR &= ~(XCACHE_CCR_INVW0_MASK | XCACHE_CCR_INVW1_MASK); in XCACHE_InvalidateCache()
169 base->CCR |= XCACHE_CCR_PUSHW0_MASK | XCACHE_CCR_PUSHW1_MASK | XCACHE_CCR_GO_MASK; in XCACHE_CleanCache()
172 while ((base->CCR & XCACHE_CCR_GO_MASK) != 0x00U) in XCACHE_CleanCache()
177 base->CCR &= ~(XCACHE_CCR_PUSHW0_MASK | XCACHE_CCR_PUSHW1_MASK); in XCACHE_CleanCache()
[all …]
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1182/drivers/cm33/
Dfsl_cache.c69 if ((base->CCR & XCACHE_CCR_ENCACHE_MASK) == 0x00U) in XCACHE_EnableCache()
75 base->CCR |= XCACHE_CCR_ENCACHE_MASK; in XCACHE_EnableCache()
85 if (XCACHE_CCR_ENCACHE_MASK == (XCACHE_CCR_ENCACHE_MASK & base->CCR)) in XCACHE_DisableCache()
91 base->CCR &= ~XCACHE_CCR_ENCACHE_MASK; in XCACHE_DisableCache()
102 base->CCR |= XCACHE_CCR_INVW0_MASK | XCACHE_CCR_INVW1_MASK | XCACHE_CCR_GO_MASK; in XCACHE_InvalidateCache()
105 while ((base->CCR & XCACHE_CCR_GO_MASK) != 0x00U) in XCACHE_InvalidateCache()
110 base->CCR &= ~(XCACHE_CCR_INVW0_MASK | XCACHE_CCR_INVW1_MASK); in XCACHE_InvalidateCache()
169 base->CCR |= XCACHE_CCR_PUSHW0_MASK | XCACHE_CCR_PUSHW1_MASK | XCACHE_CCR_GO_MASK; in XCACHE_CleanCache()
172 while ((base->CCR & XCACHE_CCR_GO_MASK) != 0x00U) in XCACHE_CleanCache()
177 base->CCR &= ~(XCACHE_CCR_PUSHW0_MASK | XCACHE_CCR_PUSHW1_MASK); in XCACHE_CleanCache()
[all …]
/hal_nxp-latest/mcux/mcux-sdk/drivers/cache/xcache/
Dfsl_cache.c69 if ((base->CCR & XCACHE_CCR_ENCACHE_MASK) == 0x00U) in XCACHE_EnableCache()
75 base->CCR |= XCACHE_CCR_ENCACHE_MASK; in XCACHE_EnableCache()
85 if (XCACHE_CCR_ENCACHE_MASK == (XCACHE_CCR_ENCACHE_MASK & base->CCR)) in XCACHE_DisableCache()
91 base->CCR &= ~XCACHE_CCR_ENCACHE_MASK; in XCACHE_DisableCache()
102 base->CCR |= XCACHE_CCR_INVW0_MASK | XCACHE_CCR_INVW1_MASK | XCACHE_CCR_GO_MASK; in XCACHE_InvalidateCache()
105 while ((base->CCR & XCACHE_CCR_GO_MASK) != 0x00U) in XCACHE_InvalidateCache()
110 base->CCR &= ~(XCACHE_CCR_INVW0_MASK | XCACHE_CCR_INVW1_MASK); in XCACHE_InvalidateCache()
169 base->CCR |= XCACHE_CCR_PUSHW0_MASK | XCACHE_CCR_PUSHW1_MASK | XCACHE_CCR_GO_MASK; in XCACHE_CleanCache()
172 while ((base->CCR & XCACHE_CCR_GO_MASK) != 0x00U) in XCACHE_CleanCache()
177 base->CCR &= ~(XCACHE_CCR_PUSHW0_MASK | XCACHE_CCR_PUSHW1_MASK); in XCACHE_CleanCache()
[all …]
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1187/drivers/cm33/
Dfsl_cache.c69 if ((base->CCR & XCACHE_CCR_ENCACHE_MASK) == 0x00U) in XCACHE_EnableCache()
75 base->CCR |= XCACHE_CCR_ENCACHE_MASK; in XCACHE_EnableCache()
85 if (XCACHE_CCR_ENCACHE_MASK == (XCACHE_CCR_ENCACHE_MASK & base->CCR)) in XCACHE_DisableCache()
91 base->CCR &= ~XCACHE_CCR_ENCACHE_MASK; in XCACHE_DisableCache()
102 base->CCR |= XCACHE_CCR_INVW0_MASK | XCACHE_CCR_INVW1_MASK | XCACHE_CCR_GO_MASK; in XCACHE_InvalidateCache()
105 while ((base->CCR & XCACHE_CCR_GO_MASK) != 0x00U) in XCACHE_InvalidateCache()
110 base->CCR &= ~(XCACHE_CCR_INVW0_MASK | XCACHE_CCR_INVW1_MASK); in XCACHE_InvalidateCache()
169 base->CCR |= XCACHE_CCR_PUSHW0_MASK | XCACHE_CCR_PUSHW1_MASK | XCACHE_CCR_GO_MASK; in XCACHE_CleanCache()
172 while ((base->CCR & XCACHE_CCR_GO_MASK) != 0x00U) in XCACHE_CleanCache()
177 base->CCR &= ~(XCACHE_CCR_PUSHW0_MASK | XCACHE_CCR_PUSHW1_MASK); in XCACHE_CleanCache()
[all …]
/hal_nxp-latest/mcux/mcux-sdk/drivers/cache/cache64/
Dfsl_cache.c183 if ((base->CCR & CACHE64_CTRL_CCR_ENCACHE_MASK) == 0x00U) in CACHE64_EnableCache()
189 base->CCR |= CACHE64_CTRL_CCR_ENCACHE_MASK; in CACHE64_EnableCache()
200 if ((base->CCR & CACHE64_CTRL_CCR_ENCACHE_MASK) != 0x00U) in CACHE64_DisableCache()
206 base->CCR &= ~CACHE64_CTRL_CCR_ENCACHE_MASK; in CACHE64_DisableCache()
217 … base->CCR |= CACHE64_CTRL_CCR_INVW0_MASK | CACHE64_CTRL_CCR_INVW1_MASK | CACHE64_CTRL_CCR_GO_MASK; in CACHE64_InvalidateCache()
220 while ((base->CCR & CACHE64_CTRL_CCR_GO_MASK) != 0x00U) in CACHE64_InvalidateCache()
225 base->CCR &= ~(CACHE64_CTRL_CCR_INVW0_MASK | CACHE64_CTRL_CCR_INVW1_MASK); in CACHE64_InvalidateCache()
287 …base->CCR |= CACHE64_CTRL_CCR_PUSHW0_MASK | CACHE64_CTRL_CCR_PUSHW1_MASK | CACHE64_CTRL_CCR_GO_MAS… in CACHE64_CleanCache()
290 while ((base->CCR & CACHE64_CTRL_CCR_GO_MASK) != 0x00U) in CACHE64_CleanCache()
295 base->CCR &= ~(CACHE64_CTRL_CCR_PUSHW0_MASK | CACHE64_CTRL_CCR_PUSHW1_MASK); in CACHE64_CleanCache()
[all …]
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1181/
Dsystem_MIMXRT1181.c140 if ((XCACHE_PC->CCR & XCACHE_CCR_ENCACHE_MASK) == 0U) /* set XCACHE if not configured */ in SystemInit()
143 XCACHE_PC->CCR = XCACHE_CCR_INVW1_MASK | XCACHE_CCR_INVW0_MASK; in SystemInit()
144 XCACHE_PC->CCR |= XCACHE_CCR_GO_MASK; in SystemInit()
146 while ((XCACHE_PC->CCR & XCACHE_CCR_GO_MASK) != 0U) in SystemInit()
150 XCACHE_PC->CCR = XCACHE_CCR_ENCACHE_MASK; in SystemInit()
157 SCB->CCR |= SCB_CCR_DIV_0_TRP_Msk; in SystemInit()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1182/
Dsystem_MIMXRT1182.c140 if ((XCACHE_PC->CCR & XCACHE_CCR_ENCACHE_MASK) == 0U) /* set XCACHE if not configured */ in SystemInit()
143 XCACHE_PC->CCR = XCACHE_CCR_INVW1_MASK | XCACHE_CCR_INVW0_MASK; in SystemInit()
144 XCACHE_PC->CCR |= XCACHE_CCR_GO_MASK; in SystemInit()
146 while ((XCACHE_PC->CCR & XCACHE_CCR_GO_MASK) != 0U) in SystemInit()
150 XCACHE_PC->CCR = XCACHE_CCR_ENCACHE_MASK; in SystemInit()
157 SCB->CCR |= SCB_CCR_DIV_0_TRP_Msk; in SystemInit()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT798S/drivers/
Dfsl_power.c738 …cache->CCR |= CACHE64_CTRL_CCR_INVW0_MASK | CACHE64_CTRL_CCR_INVW1_MASK | CACHE64_CTRL_CCR_GO_MASK; in AT_QUICKACCESS_SECTION_CODE()
739 while ((cache->CCR & CACHE64_CTRL_CCR_GO_MASK) != 0x00U) in AT_QUICKACCESS_SECTION_CODE()
743 cache->CCR &= ~(CACHE64_CTRL_CCR_INVW0_MASK | CACHE64_CTRL_CCR_INVW1_MASK); in AT_QUICKACCESS_SECTION_CODE()
745 cache->CCR |= CACHE64_CTRL_CCR_ENCACHE_MASK; in AT_QUICKACCESS_SECTION_CODE()
751 …cache->CCR |= CACHE64_CTRL_CCR_PUSHW0_MASK | CACHE64_CTRL_CCR_PUSHW1_MASK | CACHE64_CTRL_CCR_GO_MA… in AT_QUICKACCESS_SECTION_CODE()
752 while ((cache->CCR & CACHE64_CTRL_CCR_GO_MASK) != 0x00U) in AT_QUICKACCESS_SECTION_CODE()
756 cache->CCR &= ~(CACHE64_CTRL_CCR_PUSHW0_MASK | CACHE64_CTRL_CCR_PUSHW1_MASK); in AT_QUICKACCESS_SECTION_CODE()
759 cache->CCR &= ~CACHE64_CTRL_CCR_ENCACHE_MASK; in AT_QUICKACCESS_SECTION_CODE()
772 if ((cache->CCR & CACHE64_CTRL_CCR_ENCACHE_MASK) != 0x00U) in AT_QUICKACCESS_SECTION_CODE()
938 base->CCR |= XCACHE_CCR_PUSHW0_MASK | XCACHE_CCR_PUSHW1_MASK | XCACHE_CCR_GO_MASK; in AT_QUICKACCESS_SECTION_CODE()
[all …]
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT735S/drivers/
Dfsl_power.c738 …cache->CCR |= CACHE64_CTRL_CCR_INVW0_MASK | CACHE64_CTRL_CCR_INVW1_MASK | CACHE64_CTRL_CCR_GO_MASK; in AT_QUICKACCESS_SECTION_CODE()
739 while ((cache->CCR & CACHE64_CTRL_CCR_GO_MASK) != 0x00U) in AT_QUICKACCESS_SECTION_CODE()
743 cache->CCR &= ~(CACHE64_CTRL_CCR_INVW0_MASK | CACHE64_CTRL_CCR_INVW1_MASK); in AT_QUICKACCESS_SECTION_CODE()
745 cache->CCR |= CACHE64_CTRL_CCR_ENCACHE_MASK; in AT_QUICKACCESS_SECTION_CODE()
751 …cache->CCR |= CACHE64_CTRL_CCR_PUSHW0_MASK | CACHE64_CTRL_CCR_PUSHW1_MASK | CACHE64_CTRL_CCR_GO_MA… in AT_QUICKACCESS_SECTION_CODE()
752 while ((cache->CCR & CACHE64_CTRL_CCR_GO_MASK) != 0x00U) in AT_QUICKACCESS_SECTION_CODE()
756 cache->CCR &= ~(CACHE64_CTRL_CCR_PUSHW0_MASK | CACHE64_CTRL_CCR_PUSHW1_MASK); in AT_QUICKACCESS_SECTION_CODE()
759 cache->CCR &= ~CACHE64_CTRL_CCR_ENCACHE_MASK; in AT_QUICKACCESS_SECTION_CODE()
772 if ((cache->CCR & CACHE64_CTRL_CCR_ENCACHE_MASK) != 0x00U) in AT_QUICKACCESS_SECTION_CODE()
938 base->CCR |= XCACHE_CCR_PUSHW0_MASK | XCACHE_CCR_PUSHW1_MASK | XCACHE_CCR_GO_MASK; in AT_QUICKACCESS_SECTION_CODE()
[all …]
/hal_nxp-latest/mcux/mcux-sdk/drivers/sinc/
Dfsl_sinc.h1118 base->CHANNEL[(uint8_t)chId].CCR |= SINC_CCR_FIFOEN_MASK; in SINC_EnableChannelFIFO()
1122 base->CHANNEL[(uint8_t)chId].CCR &= ~SINC_CCR_FIFOEN_MASK; in SINC_EnableChannelFIFO()
1152 base->CHANNEL[(uint8_t)chId].CCR |= SINC_CCR_CHEN_MASK; in SINC_EnableChannel()
1156 base->CHANNEL[(uint8_t)chId].CCR &= ~SINC_CCR_CHEN_MASK; in SINC_EnableChannel()
1173 base->CHANNEL[(uint8_t)chId].CCR |= SINC_CCR_DMAEN_MASK; in SINC_EnableChannelPrimaryDma()
1177 base->CHANNEL[(uint8_t)chId].CCR &= ~SINC_CCR_DMAEN_MASK; in SINC_EnableChannelPrimaryDma()
1427 base->CHANNEL[(uint8_t)chId].CCR |= SINC_CCR_PFEN_MASK; in SINC_EnableChannelPrimaryFilter()
1431 base->CHANNEL[(uint8_t)chId].CCR &= ~SINC_CCR_PFEN_MASK; in SINC_EnableChannelPrimaryFilter()
1596 base->CHANNEL[(uint8_t)chId].CCR &= ~SINC_CCR_LMTEN_MASK; in SINC_SetChannelLimitDetectorMode()
1602 base->CHANNEL[(uint8_t)chId].CCR |= SINC_CCR_LMTEN_MASK; in SINC_SetChannelLimitDetectorMode()
[all …]
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT758S/drivers/
Dfsl_power.c738 …cache->CCR |= CACHE64_CTRL_CCR_INVW0_MASK | CACHE64_CTRL_CCR_INVW1_MASK | CACHE64_CTRL_CCR_GO_MASK; in AT_QUICKACCESS_SECTION_CODE()
739 while ((cache->CCR & CACHE64_CTRL_CCR_GO_MASK) != 0x00U) in AT_QUICKACCESS_SECTION_CODE()
743 cache->CCR &= ~(CACHE64_CTRL_CCR_INVW0_MASK | CACHE64_CTRL_CCR_INVW1_MASK); in AT_QUICKACCESS_SECTION_CODE()
745 cache->CCR |= CACHE64_CTRL_CCR_ENCACHE_MASK; in AT_QUICKACCESS_SECTION_CODE()
751 …cache->CCR |= CACHE64_CTRL_CCR_PUSHW0_MASK | CACHE64_CTRL_CCR_PUSHW1_MASK | CACHE64_CTRL_CCR_GO_MA… in AT_QUICKACCESS_SECTION_CODE()
752 while ((cache->CCR & CACHE64_CTRL_CCR_GO_MASK) != 0x00U) in AT_QUICKACCESS_SECTION_CODE()
756 cache->CCR &= ~(CACHE64_CTRL_CCR_PUSHW0_MASK | CACHE64_CTRL_CCR_PUSHW1_MASK); in AT_QUICKACCESS_SECTION_CODE()
759 cache->CCR &= ~CACHE64_CTRL_CCR_ENCACHE_MASK; in AT_QUICKACCESS_SECTION_CODE()
772 if ((cache->CCR & CACHE64_CTRL_CCR_ENCACHE_MASK) != 0x00U) in AT_QUICKACCESS_SECTION_CODE()
938 base->CCR |= XCACHE_CCR_PUSHW0_MASK | XCACHE_CCR_PUSHW1_MASK | XCACHE_CCR_GO_MASK; in AT_QUICKACCESS_SECTION_CODE()
[all …]
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1189/
Dsystem_MIMXRT1189_cm33.c140 if ((XCACHE_PC->CCR & XCACHE_CCR_ENCACHE_MASK) == 0U) /* set XCACHE if not configured */ in SystemInit()
143 XCACHE_PC->CCR = XCACHE_CCR_INVW1_MASK | XCACHE_CCR_INVW0_MASK; in SystemInit()
144 XCACHE_PC->CCR |= XCACHE_CCR_GO_MASK; in SystemInit()
146 while ((XCACHE_PC->CCR & XCACHE_CCR_GO_MASK) != 0U) in SystemInit()
150 XCACHE_PC->CCR = XCACHE_CCR_ENCACHE_MASK; in SystemInit()
157 SCB->CCR |= SCB_CCR_DIV_0_TRP_Msk; in SystemInit()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1187/
Dsystem_MIMXRT1187_cm33.c141 if ((XCACHE_PC->CCR & XCACHE_CCR_ENCACHE_MASK) == 0U) /* set XCACHE if not configured */ in SystemInit()
144 XCACHE_PC->CCR = XCACHE_CCR_INVW1_MASK | XCACHE_CCR_INVW0_MASK; in SystemInit()
145 XCACHE_PC->CCR |= XCACHE_CCR_GO_MASK; in SystemInit()
147 while ((XCACHE_PC->CCR & XCACHE_CCR_GO_MASK) != 0U) in SystemInit()
151 XCACHE_PC->CCR = XCACHE_CCR_ENCACHE_MASK; in SystemInit()
158 SCB->CCR |= SCB_CCR_DIV_0_TRP_Msk; in SystemInit()
/hal_nxp-latest/mcux/mcux-sdk/boards/evkmimxrt1180/
Dboard.c615 if (SCB_CCR_IC_Msk == (SCB_CCR_IC_Msk & SCB->CCR)) in BOARD_DeinitFlash()
622 if ((XCACHE_PC->CCR & XCACHE_CCR_ENCACHE_MASK) == 1U) /* disabled if enabled */ in BOARD_DeinitFlash()
625 XCACHE_PC->CCR |= XCACHE_CCR_PUSHW0_MASK | XCACHE_CCR_PUSHW1_MASK | XCACHE_CCR_GO_MASK; in BOARD_DeinitFlash()
627 while ((XCACHE_PC->CCR & XCACHE_CCR_GO_MASK) != 0x00U) in BOARD_DeinitFlash()
631 XCACHE_PC->CCR &= ~(XCACHE_CCR_PUSHW0_MASK | XCACHE_CCR_PUSHW1_MASK); in BOARD_DeinitFlash()
632 XCACHE_PC->CCR &= ~XCACHE_CCR_ENCACHE_MASK; in BOARD_DeinitFlash()
706 if ((XCACHE_PC->CCR & XCACHE_CCR_ENCACHE_MASK) == 0U) in BOARD_InitFlash()
709 XCACHE_PC->CCR = XCACHE_CCR_INVW1_MASK | XCACHE_CCR_INVW0_MASK; in BOARD_InitFlash()
710 XCACHE_PC->CCR |= XCACHE_CCR_GO_MASK; in BOARD_InitFlash()
712 while ((XCACHE_PC->CCR & XCACHE_CCR_GO_MASK) != 0U) in BOARD_InitFlash()
[all …]
/hal_nxp-latest/mcux/mcux-sdk/drivers/ctimer/
Dfsl_ctimer.h386 base->CCR |= mask & (CTIMER_CCR_CAP0I_MASK | CTIMER_CCR_CAP1I_MASK in CTIMER_EnableInterrupts()
411 base->CCR &= ~(mask & (CTIMER_CCR_CAP0I_MASK | CTIMER_CCR_CAP1I_MASK in CTIMER_DisableInterrupts()
440 enabledIntrs |= base->CCR & (CTIMER_CCR_CAP0I_MASK | CTIMER_CCR_CAP1I_MASK in CTIMER_GetEnabledInterrupts()
633 base->CCR |= (1UL << (CTIMER_CCR_CAP0RE_SHIFT + ((uint32_t)capture * 3U))); in CTIMER_EnableRisingEdgeCapture()
637 base->CCR &= ~(1UL << (CTIMER_CCR_CAP0RE_SHIFT + ((uint32_t)capture * 3U))); in CTIMER_EnableRisingEdgeCapture()
654 base->CCR |= (1UL << (CTIMER_CCR_CAP0FE_SHIFT + ((uint32_t)capture * 3U))); in CTIMER_EnableFallingEdgeCapture()
658 base->CCR &= ~(1UL << (CTIMER_CCR_CAP0FE_SHIFT + ((uint32_t)capture * 3U))); in CTIMER_EnableFallingEdgeCapture()
/hal_nxp-latest/mcux/mcux-sdk/boards/mimxrt700evk/project_template/
Dboard.c71 …cache->CCR |= CACHE64_CTRL_CCR_INVW0_MASK | CACHE64_CTRL_CCR_INVW1_MASK | CACHE64_CTRL_CCR_GO_MASK; in AT_QUICKACCESS_SECTION_CODE()
72 while ((cache->CCR & CACHE64_CTRL_CCR_GO_MASK) != 0x00U) in AT_QUICKACCESS_SECTION_CODE()
76 cache->CCR &= ~(CACHE64_CTRL_CCR_INVW0_MASK | CACHE64_CTRL_CCR_INVW1_MASK); in AT_QUICKACCESS_SECTION_CODE()
78 cache->CCR |= CACHE64_CTRL_CCR_ENCACHE_MASK; in AT_QUICKACCESS_SECTION_CODE()
84 …cache->CCR |= CACHE64_CTRL_CCR_PUSHW0_MASK | CACHE64_CTRL_CCR_PUSHW1_MASK | CACHE64_CTRL_CCR_GO_MA… in AT_QUICKACCESS_SECTION_CODE()
85 while ((cache->CCR & CACHE64_CTRL_CCR_GO_MASK) != 0x00U) in AT_QUICKACCESS_SECTION_CODE()
89 cache->CCR &= ~(CACHE64_CTRL_CCR_PUSHW0_MASK | CACHE64_CTRL_CCR_PUSHW1_MASK); in AT_QUICKACCESS_SECTION_CODE()
92 cache->CCR &= ~CACHE64_CTRL_CCR_ENCACHE_MASK; in AT_QUICKACCESS_SECTION_CODE()
187 if ((cache->CCR & CACHE64_CTRL_CCR_ENCACHE_MASK) != 0x00U) in BOARD_DeinitXspi()
241 if ((cache->CCR & CACHE64_CTRL_CCR_ENCACHE_MASK) == 0x00U) in BOARD_InitXspi()
/hal_nxp-latest/mcux/mcux-sdk/CMSIS/Core/Include/
Dcachel1_armv7.h60 if (SCB->CCR & SCB_CCR_IC_Msk) return; /* return if ICache is already enabled */ in SCB_EnableICache()
67 SCB->CCR |= (uint32_t)SCB_CCR_IC_Msk; /* enable I-Cache */ in SCB_EnableICache()
83 SCB->CCR &= ~(uint32_t)SCB_CCR_IC_Msk; /* disable I-Cache */ in SCB_DisableICache()
148 if (SCB->CCR & SCB_CCR_DC_Msk) return; /* return if DCache is already enabled */ in SCB_EnableDCache()
169 SCB->CCR |= (uint32_t)SCB_CCR_DC_Msk; /* enable D-Cache */ in SCB_EnableDCache()
191 SCB->CCR &= ~(uint32_t)SCB_CCR_DC_Msk; /* disable D-Cache */ in SCB_DisableDCache()
/hal_nxp-latest/mcux/mcux-sdk/components/internal_flash/hyper_flash/
Dfsl_adapter_flexspi_hyper_nor_flash.c283 if (SCB_CCR_IC_Msk == (SCB_CCR_IC_Msk & SCB->CCR)) in flexspi_nor_hyperbus_read()
292 if (SCB_CCR_DC_Msk == (SCB_CCR_DC_Msk & SCB->CCR)) in flexspi_nor_hyperbus_read()
336 if (SCB_CCR_IC_Msk == (SCB_CCR_IC_Msk & SCB->CCR)) in flexspi_nor_hyperbus_write()
345 if (SCB_CCR_DC_Msk == (SCB_CCR_DC_Msk & SCB->CCR)) in flexspi_nor_hyperbus_write()
494 if (SCB_CCR_IC_Msk == (SCB_CCR_IC_Msk & SCB->CCR)) in HAL_FlashInit()
503 if (SCB_CCR_DC_Msk == (SCB_CCR_DC_Msk & SCB->CCR)) in HAL_FlashInit()
660 if (SCB_CCR_IC_Msk == (SCB_CCR_IC_Msk & SCB->CCR)) in HAL_FlashProgram()
670 if (SCB_CCR_DC_Msk == (SCB_CCR_DC_Msk & SCB->CCR)) in HAL_FlashProgram()
845 if (SCB_CCR_IC_Msk == (SCB_CCR_IC_Msk & SCB->CCR)) in HAL_FlashEraseSector()
939 if (SCB_CCR_DC_Msk == (SCB_CCR_DC_Msk & SCB->CCR)) in HAL_FlashRead()
/hal_nxp-latest/mcux/mcux-sdk/drivers/mu/
Dfsl_mu.c223 uint32_t reg = base->CCR; in MU_BootCoreB()
227 base->CCR = reg; in MU_BootCoreB()
301 uint32_t ccr = base->CCR & ~(MU_CCR_HR_MASK | MU_CCR_RSTH_MASK | MU_CCR_BOOT_MASK); in MU_HardwareResetOtherCore()
314 base->CCR = ccr | MU_CCR_HR_MASK; in MU_HardwareResetOtherCore()
328 base->CCR = ccr; in MU_HardwareResetOtherCore()
/hal_nxp-latest/mcux/mcux-sdk/drivers/lpflexcomm/lpspi/
Dfsl_lpspi.c553 …base->CCR = base->CCR | LPSPI_CCR_DBT((base->CCR1 & LPSPI_CCR1_SCKSCK_MASK) >> LPSPI_CCR1_SCKSCK_S… in LPSPI_MasterSetBaudRate()
556 base->CCR = (base->CCR & ~LPSPI_CCR_SCKDIV_MASK) | LPSPI_CCR_SCKDIV(bestScaler); in LPSPI_MasterSetBaudRate()
601 …base->CCR = (base->CCR & (~LPSPI_CCR_PCSSCK_MASK)) | LPSPI_CCR_PCSSCK(scaler) | LPSPI_CCR_DBT(dbt)…
606 …base->CCR = (base->CCR & (~LPSPI_CCR_SCKPCS_MASK)) | LPSPI_CCR_SCKPCS(scaler) | LPSPI_CCR_DBT(dbt)…
611 base->CCR = base->CCR | LPSPI_CCR_DBT(scaler) | LPSPI_CCR_SCKDIV(sckdiv);
616 base->CCR = (base->CCR & (~LPSPI_CCR_PCSSCK_MASK)) | LPSPI_CCR_PCSSCK(scaler);
620 base->CCR = (base->CCR & (~LPSPI_CCR_SCKPCS_MASK)) | LPSPI_CCR_SCKPCS(scaler);
624 base->CCR = (base->CCR & (~LPSPI_CCR_DBT_MASK)) | LPSPI_CCR_DBT(scaler);
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT685S/
Dsystem_MIMXRT685S_cm33.c118 CACHE64->CCR = CACHE64_CTRL_CCR_INVW1_MASK | CACHE64_CTRL_CCR_INVW0_MASK; in SystemInit()
119 CACHE64->CCR |= CACHE64_CTRL_CCR_GO_MASK; in SystemInit()
121 while ((CACHE64->CCR & CACHE64_CTRL_CCR_GO_MASK) != 0U) in SystemInit()
125 CACHE64->CCR = (CACHE64_CTRL_CCR_ENWRBUF_MASK | CACHE64_CTRL_CCR_ENCACHE_MASK); in SystemInit()

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