1 /*
2 ** ###################################################################
3 **     Processors:          MIMXRT685SFAWBR_cm33
4 **                          MIMXRT685SFFOB_cm33
5 **                          MIMXRT685SFVKB_cm33
6 **
7 **     Compilers:           GNU C Compiler
8 **                          IAR ANSI C/C++ Compiler for ARM
9 **                          Keil ARM C/C++ Compiler
10 **                          MCUXpresso Compiler
11 **
12 **     Reference manual:    MIMXRT685 User manual Rev. 0.95 11 November 2019
13 **     Version:             rev. 2.0, 2019-11-12
14 **     Build:               b201016
15 **
16 **     Abstract:
17 **         Provides a system configuration function and a global variable that
18 **         contains the system frequency. It configures the device and initializes
19 **         the oscillator (PLL) that is part of the microcontroller device.
20 **
21 **     Copyright 2016 Freescale Semiconductor, Inc.
22 **     Copyright 2016-2020 NXP
23 **     All rights reserved.
24 **
25 **     SPDX-License-Identifier: BSD-3-Clause
26 **
27 **     http:                 www.nxp.com
28 **     mail:                 support@nxp.com
29 **
30 **     Revisions:
31 **     - rev. 1.0 (2018-06-19)
32 **         Initial version.
33 **     - rev. 2.0 (2019-11-12)
34 **         Base on rev 0.95 RM (B0 Header)
35 **
36 ** ###################################################################
37 */
38 
39 /*!
40  * @file MIMXRT685S_cm33
41  * @version 2.0
42  * @date 2019-11-12
43  * @brief Device specific configuration file for MIMXRT685S_cm33 (implementation
44  *        file)
45  *
46  * Provides a system configuration function and a global variable that contains
47  * the system frequency. It configures the device and initializes the oscillator
48  * (PLL) that is part of the microcontroller device.
49  */
50 
51 #include <stdint.h>
52 #include "fsl_device_registers.h"
53 
54 
55 #define SYSTEM_IS_XIP_FLEXSPI()                                                                               \
56     ((((uint32_t)SystemCoreClockUpdate >= 0x08000000U) && ((uint32_t)SystemCoreClockUpdate < 0x10000000U)) || \
57      (((uint32_t)SystemCoreClockUpdate >= 0x18000000U) && ((uint32_t)SystemCoreClockUpdate < 0x20000000U)))
58 
59 /* Get OSC clock from SYSOSC_BYPASS */
getOscClk(void)60 static uint32_t getOscClk(void)
61 {
62   return (CLKCTL0->SYSOSCBYPASS == 0U) ? CLK_XTAL_OSC_CLK : ((CLKCTL0->SYSOSCBYPASS == 1U) ? CLK_EXT_CLKIN : 0U);
63 }
64 
65 /* Get FFRO clock from FFROCTL0 setting */
getFFroFreq(void)66 static uint32_t getFFroFreq(void)
67 {
68   uint32_t freq = 0U;
69 
70   switch (CLKCTL0->FFROCTL0 & CLKCTL0_FFROCTL0_TRIM_RANGE_MASK)
71   {
72     case CLKCTL0_FFROCTL0_TRIM_RANGE(0):
73       freq = CLK_FRO_48MHZ;
74       break;
75     case CLKCTL0_FFROCTL0_TRIM_RANGE(3):
76       freq = CLK_FRO_60MHZ;
77       break;
78     default:
79       freq = 0U;
80       break;
81   }
82   return freq;
83 }
84 
85 
86 
87 /* ----------------------------------------------------------------------------
88    -- Core clock
89    ---------------------------------------------------------------------------- */
90 
91 uint32_t SystemCoreClock = DEFAULT_SYSTEM_CLOCK;
92 
93 /* ----------------------------------------------------------------------------
94    -- SystemInit()
95    ---------------------------------------------------------------------------- */
96 
SystemInit(void)97 __attribute__ ((weak)) void SystemInit (void) {
98 #if ((__FPU_PRESENT == 1) && (__FPU_USED == 1))
99   SCB->CPACR |= ((3UL << 10*2) | (3UL << 11*2));    /* set CP10, CP11 Full Access in Secure mode */
100   #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
101   SCB_NS->CPACR |= ((3UL << 10*2) | (3UL << 11*2));    /* set CP10, CP11 Full Access in Non-secure mode */
102   #endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
103 #endif /* ((__FPU_PRESENT == 1) && (__FPU_USED == 1)) */
104 
105   SCB->CPACR |= ((3UL << 0*2) | (3UL << 1*2));    /* set CP0, CP1 Full Access in Secure mode (enable PowerQuad) */
106 
107 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
108   SCB_NS->CPACR |= ((3UL << 0*2) | (3UL << 1*2));    /* set CP0, CP1 Full Access in Non-secure mode (enable PowerQuad) */
109 #endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
110 
111   SCB->NSACR |= ((3UL << 0) | (3UL << 10));   /* enable CP0, CP1, CP10, CP11 Non-secure Access */
112 
113   SYSCTL0->DSPSTALL = SYSCTL0_DSPSTALL_DSPSTALL_MASK;
114 
115   if (SYSTEM_IS_XIP_FLEXSPI() && (CACHE64_POLSEL->POLSEL == 0U)) /* Enable cache to accelerate boot. */
116   {
117     /* set command to invalidate all ways and write GO bit to initiate command */
118     CACHE64->CCR = CACHE64_CTRL_CCR_INVW1_MASK | CACHE64_CTRL_CCR_INVW0_MASK;
119     CACHE64->CCR |= CACHE64_CTRL_CCR_GO_MASK;
120     /* Wait until the command completes */
121     while ((CACHE64->CCR & CACHE64_CTRL_CCR_GO_MASK) != 0U)
122     {
123     }
124     /* Enable cache, enable write buffer */
125     CACHE64->CCR = (CACHE64_CTRL_CCR_ENWRBUF_MASK | CACHE64_CTRL_CCR_ENCACHE_MASK);
126 
127     /* Set whole FlexSPI0 space to write through. */
128     CACHE64_POLSEL->REG0_TOP = 0x07FFFC00U;
129     CACHE64_POLSEL->REG1_TOP = 0x0U;
130     CACHE64_POLSEL->POLSEL = 0x1U;
131 
132     __ISB();
133     __DSB();
134   }
135 
136   SystemInitHook();
137 }
138 
139 /* ----------------------------------------------------------------------------
140    -- SystemCoreClockUpdate()
141    ---------------------------------------------------------------------------- */
142 
SystemCoreClockUpdate(void)143 void SystemCoreClockUpdate (void) {
144 
145   /* iMXRT6xx systemCoreClockUpdate */
146   uint32_t freq = 0U;
147   uint64_t freqTmp = 0U;
148 
149   switch ((CLKCTL0->MAINCLKSELB) & CLKCTL0_MAINCLKSELB_SEL_MASK)
150   {
151     case CLKCTL0_MAINCLKSELB_SEL(0): /* MAINCLKSELA clock */
152       switch ((CLKCTL0->MAINCLKSELA) & CLKCTL0_MAINCLKSELA_SEL_MASK)
153       {
154         case CLKCTL0_MAINCLKSELA_SEL(0): /* FFRO clock (48/60m_irc) divider by 4 */
155           freq = getFFroFreq() / 4U;
156           break;
157         case CLKCTL0_MAINCLKSELA_SEL(1): /* OSC clock (clk_in) */
158           freq = getOscClk();
159           break;
160         case CLKCTL0_MAINCLKSELA_SEL(2): /* Low Power Oscillator Clock (1m_lposc) */
161           freq = CLK_LPOSC_1MHZ;
162           break;
163         case CLKCTL0_MAINCLKSELA_SEL(3): /* FFRO clock */
164           freq = getFFroFreq();
165           break;
166         default:
167           freq = 0U;
168           break;
169       }
170       break;
171     case CLKCTL0_MAINCLKSELB_SEL(1): /* SFRO clock */
172       freq = CLK_FRO_16MHZ;
173       break;
174     case CLKCTL0_MAINCLKSELB_SEL(2): /* Main System PLL clock */
175       switch ((CLKCTL0->SYSPLL0CLKSEL) & CLKCTL0_SYSPLL0CLKSEL_SEL_MASK)
176       {
177         case CLKCTL0_SYSPLL0CLKSEL_SEL(0): /* SFRO clock */
178           freq = CLK_FRO_16MHZ;
179           break;
180         case CLKCTL0_SYSPLL0CLKSEL_SEL(1): /* OSC clock (clk_in) */
181           freq = getOscClk();
182           break;
183         case CLKCTL0_SYSPLL0CLKSEL_SEL(2): /* FFRO clock (48/60m_irc) divider by 2 */
184           freq = getFFroFreq() / 2U;
185           break;
186         default:
187           freq = 0U;
188           break;
189       }
190 
191       if (((CLKCTL0->SYSPLL0CTL0) & CLKCTL0_SYSPLL0CTL0_BYPASS_MASK) == 0U)
192       {
193         /* PLL output frequency = Fref * (DIV_SELECT + NUM/DENOM). */
194         freqTmp = ((uint64_t)freq * ((uint64_t)(CLKCTL0->SYSPLL0NUM))) / ((uint64_t)(CLKCTL0->SYSPLL0DENOM));
195         freq *= ((CLKCTL0->SYSPLL0CTL0) & CLKCTL0_SYSPLL0CTL0_MULT_MASK) >> CLKCTL0_SYSPLL0CTL0_MULT_SHIFT;
196         freq += (uint32_t)freqTmp;
197         freq = (uint32_t)((uint64_t)freq * 18U /
198                ((CLKCTL0->SYSPLL0PFD & CLKCTL0_SYSPLL0PFD_PFD0_MASK) >> CLKCTL0_SYSPLL0PFD_PFD0_SHIFT));
199       }
200       freq = freq / ((CLKCTL0->MAINPLLCLKDIV & CLKCTL0_MAINPLLCLKDIV_DIV_MASK) + 1U);
201       break;
202 
203     case CLKCTL0_MAINCLKSELB_SEL(3): /* RTC 32KHz clock */
204         freq = CLK_RTC_32K_CLK;
205         break;
206 
207     default:
208         freq = 0U;
209         break;
210   }
211 
212   SystemCoreClock = freq / ((CLKCTL0->SYSCPUAHBCLKDIV & 0xffU) + 1U);
213 
214 }
215 
216 /* ----------------------------------------------------------------------------
217    -- SystemInitHook()
218    ---------------------------------------------------------------------------- */
219 
SystemInitHook(void)220 __attribute__ ((weak)) void SystemInitHook (void) {
221   /* Void implementation of the weak function. */
222 }
223