1 /*
2 * Copyright 2021-2024 NXP
3 * All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7
8 #include "fsl_common.h"
9 #include "fsl_debug_console.h"
10 #include "board.h"
11 #if defined(SDK_I2C_BASED_COMPONENT_USED) && SDK_I2C_BASED_COMPONENT_USED
12 #include "fsl_lpi2c.h"
13 #endif /* SDK_I2C_BASED_COMPONENT_USED */
14 #if defined(SDK_NETC_USED) && SDK_NETC_USED
15 #include "fsl_netc_soc.h"
16 #include "fsl_netc_ierb.h"
17 #endif /* SDK_NETC_USED */
18 #include "fsl_iomuxc.h"
19 #include "fsl_cache.h"
20 #include "fsl_ele_base_api.h"
21 #include "fsl_dcdc.h"
22
23 /*******************************************************************************
24 * Definitions
25 ******************************************************************************/
26 #define BOARD_FLEXSPI_DLL_LOCK_RETRY (10)
27
28 /*******************************************************************************
29 * Variables
30 ******************************************************************************/
31
32 /*******************************************************************************
33 * Code
34 ******************************************************************************/
35
36 /* Get debug console frequency. */
BOARD_DebugConsoleSrcFreq(void)37 uint32_t BOARD_DebugConsoleSrcFreq(void)
38 {
39 return CLOCK_GetRootClockFreq(BOARD_DEBUG_UART_CLK_ROOT);
40 }
41
42 /* Initialize debug console. */
BOARD_InitDebugConsole(void)43 void BOARD_InitDebugConsole(void)
44 {
45 uint32_t uartClkSrcFreq = BOARD_DebugConsoleSrcFreq();
46 DbgConsole_Init(BOARD_DEBUG_UART_INSTANCE, BOARD_DEBUG_UART_BAUDRATE, BOARD_DEBUG_UART_TYPE, uartClkSrcFreq);
47 }
48
49 #if defined(SDK_I2C_BASED_COMPONENT_USED) && SDK_I2C_BASED_COMPONENT_USED
BOARD_LPI2C_Init(LPI2C_Type * base,uint32_t clkSrc_Hz)50 void BOARD_LPI2C_Init(LPI2C_Type *base, uint32_t clkSrc_Hz)
51 {
52 lpi2c_master_config_t lpi2cConfig = {0};
53
54 /*
55 * lpi2cConfig.debugEnable = false;
56 * lpi2cConfig.ignoreAck = false;
57 * lpi2cConfig.pinConfig = kLPI2C_2PinOpenDrain;
58 * lpi2cConfig.baudRate_Hz = 100000U;
59 * lpi2cConfig.busIdleTimeout_ns = 0;
60 * lpi2cConfig.pinLowTimeout_ns = 0;
61 * lpi2cConfig.sdaGlitchFilterWidth_ns = 0;
62 * lpi2cConfig.sclGlitchFilterWidth_ns = 0;
63 */
64 LPI2C_MasterGetDefaultConfig(&lpi2cConfig);
65 LPI2C_MasterInit(base, &lpi2cConfig, clkSrc_Hz);
66 }
67
BOARD_LPI2C_Send(LPI2C_Type * base,uint8_t deviceAddress,uint32_t subAddress,uint8_t subAddressSize,uint8_t * txBuff,uint8_t txBuffSize)68 status_t BOARD_LPI2C_Send(LPI2C_Type *base,
69 uint8_t deviceAddress,
70 uint32_t subAddress,
71 uint8_t subAddressSize,
72 uint8_t *txBuff,
73 uint8_t txBuffSize)
74 {
75 lpi2c_master_transfer_t xfer;
76
77 xfer.flags = kLPI2C_TransferDefaultFlag;
78 xfer.slaveAddress = deviceAddress;
79 xfer.direction = kLPI2C_Write;
80 xfer.subaddress = subAddress;
81 xfer.subaddressSize = subAddressSize;
82 xfer.data = txBuff;
83 xfer.dataSize = txBuffSize;
84
85 return LPI2C_MasterTransferBlocking(base, &xfer);
86 }
87
BOARD_LPI2C_Receive(LPI2C_Type * base,uint8_t deviceAddress,uint32_t subAddress,uint8_t subAddressSize,uint8_t * rxBuff,uint8_t rxBuffSize)88 status_t BOARD_LPI2C_Receive(LPI2C_Type *base,
89 uint8_t deviceAddress,
90 uint32_t subAddress,
91 uint8_t subAddressSize,
92 uint8_t *rxBuff,
93 uint8_t rxBuffSize)
94 {
95 lpi2c_master_transfer_t xfer;
96
97 xfer.flags = kLPI2C_TransferDefaultFlag;
98 xfer.slaveAddress = deviceAddress;
99 xfer.direction = kLPI2C_Read;
100 xfer.subaddress = subAddress;
101 xfer.subaddressSize = subAddressSize;
102 xfer.data = rxBuff;
103 xfer.dataSize = rxBuffSize;
104
105 return LPI2C_MasterTransferBlocking(base, &xfer);
106 }
107
BOARD_LPI2C_SendSCCB(LPI2C_Type * base,uint8_t deviceAddress,uint32_t subAddress,uint8_t subAddressSize,uint8_t * txBuff,uint8_t txBuffSize)108 status_t BOARD_LPI2C_SendSCCB(LPI2C_Type *base,
109 uint8_t deviceAddress,
110 uint32_t subAddress,
111 uint8_t subAddressSize,
112 uint8_t *txBuff,
113 uint8_t txBuffSize)
114 {
115 lpi2c_master_transfer_t xfer;
116
117 xfer.flags = kLPI2C_TransferDefaultFlag;
118 xfer.slaveAddress = deviceAddress;
119 xfer.direction = kLPI2C_Write;
120 xfer.subaddress = subAddress;
121 xfer.subaddressSize = subAddressSize;
122 xfer.data = txBuff;
123 xfer.dataSize = txBuffSize;
124
125 return LPI2C_MasterTransferBlocking(base, &xfer);
126 }
127
BOARD_LPI2C_ReceiveSCCB(LPI2C_Type * base,uint8_t deviceAddress,uint32_t subAddress,uint8_t subAddressSize,uint8_t * rxBuff,uint8_t rxBuffSize)128 status_t BOARD_LPI2C_ReceiveSCCB(LPI2C_Type *base,
129 uint8_t deviceAddress,
130 uint32_t subAddress,
131 uint8_t subAddressSize,
132 uint8_t *rxBuff,
133 uint8_t rxBuffSize)
134 {
135 status_t status;
136 lpi2c_master_transfer_t xfer;
137
138 xfer.flags = kLPI2C_TransferDefaultFlag;
139 xfer.slaveAddress = deviceAddress;
140 xfer.direction = kLPI2C_Write;
141 xfer.subaddress = subAddress;
142 xfer.subaddressSize = subAddressSize;
143 xfer.data = NULL;
144 xfer.dataSize = 0;
145
146 status = LPI2C_MasterTransferBlocking(base, &xfer);
147
148 if (kStatus_Success == status)
149 {
150 xfer.subaddressSize = 0;
151 xfer.direction = kLPI2C_Read;
152 xfer.data = rxBuff;
153 xfer.dataSize = rxBuffSize;
154
155 status = LPI2C_MasterTransferBlocking(base, &xfer);
156 }
157
158 return status;
159 }
160
BOARD_Accel_I2C_Init(void)161 void BOARD_Accel_I2C_Init(void)
162 {
163 BOARD_LPI2C_Init(BOARD_ACCEL_I2C_BASEADDR, BOARD_ACCEL_I2C_CLOCK_FREQ);
164 }
165
BOARD_Accel_I2C_Send(uint8_t deviceAddress,uint32_t subAddress,uint8_t subaddressSize,uint32_t txBuff)166 status_t BOARD_Accel_I2C_Send(uint8_t deviceAddress, uint32_t subAddress, uint8_t subaddressSize, uint32_t txBuff)
167 {
168 uint8_t data = (uint8_t)txBuff;
169
170 return BOARD_LPI2C_Send(BOARD_ACCEL_I2C_BASEADDR, deviceAddress, subAddress, subaddressSize, &data, 1);
171 }
172
BOARD_Accel_I2C_Receive(uint8_t deviceAddress,uint32_t subAddress,uint8_t subaddressSize,uint8_t * rxBuff,uint8_t rxBuffSize)173 status_t BOARD_Accel_I2C_Receive(
174 uint8_t deviceAddress, uint32_t subAddress, uint8_t subaddressSize, uint8_t *rxBuff, uint8_t rxBuffSize)
175 {
176 return BOARD_LPI2C_Receive(BOARD_ACCEL_I2C_BASEADDR, deviceAddress, subAddress, subaddressSize, rxBuff, rxBuffSize);
177 }
178
BOARD_Codec_I2C_Init(void)179 void BOARD_Codec_I2C_Init(void)
180 {
181 BOARD_LPI2C_Init(BOARD_CODEC_I2C_BASEADDR, BOARD_CODEC_I2C_CLOCK_FREQ);
182 }
183
BOARD_Codec_I2C_Send(uint8_t deviceAddress,uint32_t subAddress,uint8_t subAddressSize,const uint8_t * txBuff,uint8_t txBuffSize)184 status_t BOARD_Codec_I2C_Send(
185 uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, const uint8_t *txBuff, uint8_t txBuffSize)
186 {
187 return BOARD_LPI2C_Send(BOARD_CODEC_I2C_BASEADDR, deviceAddress, subAddress, subAddressSize, (uint8_t *)txBuff,
188 txBuffSize);
189 }
190
BOARD_Codec_I2C_Receive(uint8_t deviceAddress,uint32_t subAddress,uint8_t subAddressSize,uint8_t * rxBuff,uint8_t rxBuffSize)191 status_t BOARD_Codec_I2C_Receive(
192 uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, uint8_t *rxBuff, uint8_t rxBuffSize)
193 {
194 return BOARD_LPI2C_Receive(BOARD_CODEC_I2C_BASEADDR, deviceAddress, subAddress, subAddressSize, rxBuff, rxBuffSize);
195 }
196 #endif /* SDK_I2C_BASED_COMPONENT_USED */
197
198 /* MPU configuration. */
199 #if __CORTEX_M == 7
BOARD_ConfigMPU(void)200 void BOARD_ConfigMPU(void)
201 {
202 #if defined(__CC_ARM) || defined(__ARMCC_VERSION)
203 extern uint32_t Image$$RW_m_ncache$$Base[];
204 /* RW_m_ncache_aux is a auxiliary region which is used to get the whole size of noncache section */
205 extern uint32_t Image$$RW_m_ncache_aux$$Base[];
206 uint32_t nonCacheStart = (uint32_t)Image$$RW_m_ncache$$Base;
207 uint32_t nonCacheSize = ((uint32_t)Image$$RW_m_ncache_aux$$Base) - nonCacheStart;
208 #elif defined(__MCUXPRESSO)
209 extern uint32_t __base_NCACHE_REGION;
210 extern uint32_t __top_NCACHE_REGION;
211 uint32_t nonCacheStart = (uint32_t)(&__base_NCACHE_REGION);
212 uint32_t nonCacheSize = (uint32_t)(&__top_NCACHE_REGION) - nonCacheStart;
213 #elif defined(__ICCARM__) || defined(__GNUC__)
214 extern uint32_t __NCACHE_REGION_START[];
215 extern uint32_t __NCACHE_REGION_SIZE[];
216 uint32_t nonCacheStart = (uint32_t)__NCACHE_REGION_START;
217 uint32_t nonCacheSize = (uint32_t)__NCACHE_REGION_SIZE;
218 #endif
219 #if defined(__USE_SHMEM)
220 #if defined(__CC_ARM) || defined(__ARMCC_VERSION)
221 extern uint32_t Image$$RPMSG_SH_MEM$$Base[];
222 /* RPMSG_SH_MEM_aux is a auxiliary region which is used to get the whole size of RPMSG_SH_MEM section */
223 extern uint32_t Image$$RPMSG_SH_MEM_aux$$Base[];
224 uint32_t rpmsgShmemStart = (uint32_t)Image$$RPMSG_SH_MEM$$Base;
225 uint32_t rpmsgShmemSize = ((uint32_t)Image$$RPMSG_SH_MEM_aux$$Base) - rpmsgShmemStart;
226 #elif defined(__MCUXPRESSO)
227 extern uint32_t __base_SHMEM_REGION;
228 extern uint32_t __top_SHMEM_REGION;
229 uint32_t rpmsgShmemStart = (uint32_t)(&__base_SHMEM_REGION);
230 uint32_t rpmsgShmemSize = (uint32_t)(&__top_SHMEM_REGION) - rpmsgShmemStart;
231 #elif defined(__ICCARM__) || defined(__GNUC__)
232 extern uint32_t __RPMSG_SH_MEM_START[];
233 extern uint32_t __RPMSG_SH_MEM_SIZE[];
234 uint32_t rpmsgShmemStart = (uint32_t)__RPMSG_SH_MEM_START;
235 uint32_t rpmsgShmemSize = (uint32_t)__RPMSG_SH_MEM_SIZE;
236 #endif
237 #endif
238 volatile uint32_t i;
239
240 /* Disable I cache and D cache */
241 L1CACHE_DisableICache();
242 L1CACHE_DisableDCache();
243
244 /* Disable MPU */
245 ARM_MPU_Disable();
246
247 /* clang-format off */
248
249 /* MPU configure:
250 * Use ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable, SubRegionDisable, Size)
251 * API in mpu_armv7.h.
252 * param DisableExec Instruction access (XN) disable bit,0=instruction fetches enabled, 1=instruction fetches disabled.
253 * param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode.
254 * Use MACROS defined in mpu_armv7.h:
255 * ARM_MPU_AP_NONE/ARM_MPU_AP_PRIV/ARM_MPU_AP_URO/ARM_MPU_AP_FULL/ARM_MPU_AP_PRO/ARM_MPU_AP_RO
256 *
257 * Combine TypeExtField/IsShareable/IsCacheable/IsBufferable to configure MPU memory access attributes.
258 * TypeExtField IsShareable IsCacheable IsBufferable Memory Attribute Shareability Cache
259 * 0 x 0 0 Strongly Ordered shareable
260 * 0 x 0 1 Device shareable
261 * 0 0 1 0 Normal not shareable Outer and inner write
262 * through no write allocate
263 * 0 0 1 1 Normal not shareable Outer and inner write
264 * back no write allocate
265 * 0 1 1 0 Normal shareable Outer and inner write
266 * through no write allocate
267 * 0 1 1 1 Normal shareable Outer and inner write
268 * back no write allocate
269 * 1 0 0 0 Normal not shareable outer and inner
270 * noncache
271 * 1 1 0 0 Normal shareable outer and inner
272 * noncache
273 * 1 0 1 1 Normal not shareable outer and inner write
274 * back write/read acllocate
275 * 1 1 1 1 Normal shareable outer and inner write
276 * back write/read acllocate
277 * 2 x 0 0 Device not shareable
278 * Above are normal use settings, if your want to see more details or want to config different inner/outer cache
279 * policy, please refer to Table 4-55 /4-56 in arm cortex-M7 generic user guide <dui0646b_cortex_m7_dgug.pdf>
280 *
281 * param SubRegionDisable Sub-region disable field. 0=sub-region is enabled, 1=sub-region is disabled.
282 * param Size Region size of the region to be configured. use ARM_MPU_REGION_SIZE_xxx MACRO in mpu_armv7.h.
283 */
284
285 /* clang-format on */
286
287 /*
288 * Add default region to deny access to whole address space to workaround speculative prefetch.
289 * Refer to Arm errata 1013783-B for more details.
290 */
291
292 /* Region 0 setting: Instruction access disabled, No data access permission. */
293 MPU->RBAR = ARM_MPU_RBAR(0, 0x00000000U);
294 MPU->RASR = ARM_MPU_RASR(1, ARM_MPU_AP_NONE, 0, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_4GB);
295
296 /* Region 1 setting: Memory with Device type, not shareable, non-cacheable. */
297 MPU->RBAR = ARM_MPU_RBAR(1, 0x80000000U);
298 MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_512MB);
299
300 /* Region 3 setting: Memory with Device type, not shareable, non-cacheable. */
301 MPU->RBAR = ARM_MPU_RBAR(3, 0x00000000U);
302 MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_2GB);
303
304 /* Region 4 setting: Memory with Normal type, not shareable, outer/inner write back */ /*ITCM*/
305 MPU->RBAR = ARM_MPU_RBAR(4, 0x00000000U);
306 MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_256KB);
307
308 /* Region 5 setting: Memory with Normal type, not shareable, outer/inner write back */ /*DTCM*/
309 MPU->RBAR = ARM_MPU_RBAR(5, 0x20000000U);
310 MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_256KB);
311
312 MPU->RBAR = ARM_MPU_RBAR(6, 0x20480000U);
313 #if defined(CACHE_MODE_WRITE_THROUGH)
314 /* Region 6 setting: Memory with Normal type, not shareable, outer/inner write through */ /*OCRAM1*/
315 MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 0, 0, ARM_MPU_REGION_SIZE_512KB);
316 #else
317 /* Region 6 setting: Memory with Normal type, not shareable, outer/inner write back */ /*OCRAM1*/
318 MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_512KB);
319 #endif
320
321 MPU->RBAR = ARM_MPU_RBAR(7, 0x20500000U);
322 #if defined(CACHE_MODE_WRITE_THROUGH)
323 /* Region 7 setting: Memory with Normal type, not shareable, outer/inner write through */ /*OCRAM2*/
324 MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 0, 0, ARM_MPU_REGION_SIZE_256KB);
325 #else
326 /* Region 7 setting: Memory with Normal type, not shareable, outer/inner write back */ /*OCRAM2*/
327 MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_256KB);
328 #endif
329
330 #if defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1)
331 /* Region 8 setting: Memory with Normal type, not shareable, outer/inner write back. */ /*FSPI1*/
332 MPU->RBAR = ARM_MPU_RBAR(8, 0x28000000U);
333 MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_RO, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_16MB);
334 #endif
335
336 #if defined(USE_HYPERRAM)
337 MPU->RBAR = ARM_MPU_RBAR(9, 0x04000000U);
338 #if defined(CACHE_MODE_WRITE_THROUGH)
339 /* Region 9 setting: Memory with Normal type, not shareable, outer/inner write through. */ /*FSPI2*/
340 MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 0, 0, ARM_MPU_REGION_SIZE_8MB);
341 #else
342 /* Region 9 setting: Memory with Normal type, not shareable, outer/inner write back. */ /*FSPI2*/
343 MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_8MB);
344 #endif
345 #endif
346
347 #if defined(USE_SDRAM)
348 MPU->RBAR = ARM_MPU_RBAR(10, 0x80000000U);
349 #if defined(CACHE_MODE_WRITE_THROUGH)
350 /* Region 10 setting: Memory with Normal type, not shareable, outer/inner write through */
351 MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 0, 0, ARM_MPU_REGION_SIZE_64MB);
352 #else
353 /* Region 10 setting: Memory with Normal type, not shareable, outer/inner write back */
354 MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_64MB);
355 #endif
356 #endif
357
358 i = 0;
359 while ((nonCacheSize >> i) > 0x1U)
360 {
361 i++;
362 }
363
364 if (i != 0)
365 {
366 /* The MPU region size should be 2^N, 5<=N<=32, region base should be multiples of size. */
367 assert(!(nonCacheStart % nonCacheSize));
368 assert(nonCacheSize == (uint32_t)(1 << i));
369 assert(i >= 5);
370
371 /* Region 11 setting: Memory with Normal type, not shareable, non-cacheable */
372 MPU->RBAR = ARM_MPU_RBAR(11, nonCacheStart);
373 MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 1, 0, 0, 0, 0, i - 1);
374 }
375
376 #if defined(__USE_SHMEM)
377 i = 0;
378 while ((rpmsgShmemSize >> i) > 0x1U)
379 {
380 i++;
381 }
382
383 if (i != 0)
384 {
385 /* The MPU region size should be 2^N, 5<=N<=32, region base should be multiples of size. */
386 assert(!(rpmsgShmemStart % rpmsgShmemSize));
387 assert(rpmsgShmemSize == (uint32_t)(1 << i));
388 assert(i >= 5);
389
390 /* Region 12 setting: Memory with Normal type, not shareable, non-cacheable */
391 MPU->RBAR = ARM_MPU_RBAR(12, rpmsgShmemStart);
392 MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 1, 0, 0, 0, 0, i - 1);
393 }
394 #endif
395
396 /* Enable MPU */
397 ARM_MPU_Enable(MPU_CTRL_PRIVDEFENA_Msk | MPU_CTRL_HFNMIENA_Msk);
398
399 /* Enable I cache and D cache */
400 L1CACHE_EnableDCache();
401 L1CACHE_EnableICache();
402 }
403 #elif __CORTEX_M == 33
BOARD_ConfigMPU(void)404 void BOARD_ConfigMPU(void)
405 {
406 #if defined(__CC_ARM) || defined(__ARMCC_VERSION)
407 extern uint32_t Image$$RW_m_ncache$$Base[];
408 /* RW_m_ncache_aux is a auxiliary region which is used to get the whole size of noncache section */
409 extern uint32_t Image$$RW_m_ncache_aux$$Base[];
410 uint32_t nonCacheStart = (uint32_t)Image$$RW_m_ncache$$Base;
411 uint32_t nonCacheSize = ((uint32_t)Image$$RW_m_ncache_aux$$Base) - nonCacheStart;
412 #elif defined(__MCUXPRESSO)
413 extern uint32_t __base_NCACHE_REGION;
414 extern uint32_t __top_NCACHE_REGION;
415 uint32_t nonCacheStart = (uint32_t)(&__base_NCACHE_REGION);
416 uint32_t nonCacheSize = (uint32_t)(&__top_NCACHE_REGION) - nonCacheStart;
417 #elif defined(__ICCARM__) || defined(__GNUC__)
418 extern uint32_t __NCACHE_REGION_START[];
419 extern uint32_t __NCACHE_REGION_SIZE[];
420 uint32_t nonCacheStart = (uint32_t)__NCACHE_REGION_START;
421 uint32_t nonCacheSize = (uint32_t)__NCACHE_REGION_SIZE;
422 #endif
423 #if defined(__USE_SHMEM)
424 #if defined(__CC_ARM) || defined(__ARMCC_VERSION)
425 extern uint32_t Image$$RPMSG_SH_MEM$$Base[];
426 /* RPMSG_SH_MEM_aux is a auxiliary region which is used to get the whole size of RPMSG_SH_MEM section */
427 extern uint32_t Image$$RPMSG_SH_MEM_aux$$Base[];
428 uint32_t rpmsgShmemStart = (uint32_t)Image$$RPMSG_SH_MEM$$Base;
429 uint32_t rpmsgShmemSize = (uint32_t)Image$$RPMSG_SH_MEM_aux$$Base - rpmsgShmemStart;
430 #elif defined(__MCUXPRESSO)
431 extern uint32_t __base_SHMEM_REGION;
432 extern uint32_t __top_SHMEM_REGION;
433 uint32_t rpmsgShmemStart = (uint32_t)(&__base_SHMEM_REGION);
434 uint32_t rpmsgShmemSize = (uint32_t)(&__top_SHMEM_REGION) - rpmsgShmemStart;
435 #elif defined(__ICCARM__) || defined(__GNUC__)
436 extern uint32_t __RPMSG_SH_MEM_START[];
437 extern uint32_t __RPMSG_SH_MEM_SIZE[];
438 uint32_t rpmsgShmemStart = (uint32_t)__RPMSG_SH_MEM_START;
439 uint32_t rpmsgShmemSize = (uint32_t)__RPMSG_SH_MEM_SIZE;
440 #endif
441 #endif
442 uint32_t i;
443 uint8_t attr;
444
445 /* Disable code & system cache */
446 XCACHE_DisableCache(XCACHE_PC);
447 XCACHE_DisableCache(XCACHE_PS);
448
449 /* Disable MPU */
450 ARM_MPU_Disable();
451
452 /* Attr0: device. */
453 ARM_MPU_SetMemAttr(0U, ARM_MPU_ATTR(ARM_MPU_ATTR_DEVICE, ARM_MPU_ATTR_DEVICE));
454
455 /* Attr1: non cacheable. */
456 ARM_MPU_SetMemAttr(1U, ARM_MPU_ATTR(ARM_MPU_ATTR_NON_CACHEABLE, ARM_MPU_ATTR_NON_CACHEABLE));
457
458 /* Attr2: non transient, write through, read allocate. */
459 attr = ARM_MPU_ATTR_MEMORY_(0U, 0U, 1U, 0U);
460 ARM_MPU_SetMemAttr(2U, ARM_MPU_ATTR(attr, attr));
461
462 /* Attr3: non transient, write back, read/write allocate. */
463 attr = ARM_MPU_ATTR_MEMORY_(0U, 1U, 1U, 1U);
464 ARM_MPU_SetMemAttr(3U, ARM_MPU_ATTR(attr, attr));
465
466 /* NOTE:
467 * 1. When memory regions overlap, the processor generates a fault if a core access hits the overlapping regions
468 */
469
470 #if defined(USE_HYPERRAM)
471 /*
472 The default attribute of the background system address map for this address space:
473 normal, write through, read allocate, non-shareable, read/write in privilege and non-privilege, executable
474 */
475
476 /* Region 0 (FlexSPI2, Hyperram): [0x04000000, 0x047FFFFFF, 8M] */
477 #if !defined(CACHE_MODE_WRITE_THROUGH)
478 /* non-shareable, read/write in privilege and non-privilege, executable. Attr 3 */
479 ARM_MPU_SetRegion(0U, ARM_MPU_RBAR(0x04000000, ARM_MPU_SH_NON, 0U, 1U, 0U), ARM_MPU_RLAR(0x047FFFFF, 3U));
480 #endif
481 #endif
482
483 /* Region 1 (Code TCM): [0x0FFE0000, 0x0FFFFFFF, 128K] */
484 /* non-shareable, read/write in privilege and non-privilege, executable. Attr 2 */
485 ARM_MPU_SetRegion(1U, ARM_MPU_RBAR(0x0FFE0000, ARM_MPU_SH_NON, 0U, 1U, 0U), ARM_MPU_RLAR(0x0FFFFFFF, 2U));
486
487 /* Region 2 (System TCM): [0x20000000, 0x2001FFFF, 128K] */
488 /* non-shareable, read/write in privilege and non-privilege, executable. Attr 3 */
489 ARM_MPU_SetRegion(2U, ARM_MPU_RBAR(0x20000000, ARM_MPU_SH_NON, 0U, 1U, 0U), ARM_MPU_RLAR(0x2001FFFF, 3U));
490
491 /* Region 3 (CM7 I/D TCM): [0x203C0000, 0x2043FFFF, 512K] */
492 /* non-shareable, read/write in privilege and non-privilege, execute-never. Attr 1 (non cacheable). */
493 ARM_MPU_SetRegion(3U, ARM_MPU_RBAR(0x203C0000, ARM_MPU_SH_NON, 0U, 1U, 1U), ARM_MPU_RLAR(0x2043FFFF, 1U));
494
495 /* Region 4 (CM7 I/D TCM): [0x303C0000, 0x3043FFFF, 512K] */
496 /* non-shareable, read/write in privilege and non-privilege, execute-never. Attr 1 (non cacheable). */
497 ARM_MPU_SetRegion(4U, ARM_MPU_RBAR(0x303C0000, ARM_MPU_SH_NON, 0U, 1U, 1U), ARM_MPU_RLAR(0x3043FFFF, 1U));
498
499 /*
500 As common setting, not set this region to avoid potential overlapping setting with NCACHE(region 8)
501 and SHMEM(region 9) for specific build configuration, but use the default attribute of the background
502 system address map.
503 The default attribute of the background system address map for this address space:
504 normal, write back, write/read allocate, non-shareable, read/write in privilege and non-privilege, executable
505
506 If application needs to fine tune MPU settings, here is an example:
507 // Region 11 (OCRAM1): [0x20480000, 0x204FFFFF, 512K]
508 // non-shareable, read/write in privilege and non-privilege, executable. Attr 3
509 ARM_MPU_SetRegion(11U, ARM_MPU_RBAR(0x20480000, ARM_MPU_SH_NON, 0U, 1U, 0U), ARM_MPU_RLAR(0x204FFFFF, 3U));
510
511 // Region 12 (OCRAM2): [0x20500000, 0x2053FFFF, 256K]
512 // non-shareable, read/write in privilege and non-privilege, executable. Attr 3
513 ARM_MPU_SetRegion(12U, ARM_MPU_RBAR(0x20500000, ARM_MPU_SH_NON, 0U, 1U, 0U), ARM_MPU_RLAR(0x2053FFFF, 3U));
514 */
515
516 /* Region 5 (FlexSPI1, Nor Flash): [0x28000000, 0x28FFFFFF, 16M] */
517 /* non-shareable, read only in privilege and non-privileged, executable. Attr 2 */
518 ARM_MPU_SetRegion(5U, ARM_MPU_RBAR(0x28000000, ARM_MPU_SH_NON, 1U, 1U, 0U), ARM_MPU_RLAR(0x28FFFFFF, 2U));
519
520 /* Region 6 (Peripherals): [0x40000000, 0x7FFFFFFF, 1G ] */
521 /* non-shareable, read/write in privilege and non-privileged, execute-never. Attr 0 (device). */
522 ARM_MPU_SetRegion(6U, ARM_MPU_RBAR(0x40000000, ARM_MPU_SH_NON, 0U, 1U, 1U), ARM_MPU_RLAR(0x7FFFFFFF, 0U));
523
524 #if defined(USE_SDRAM)
525 /*
526 As common setting, not set this region to avoid potential overlapping setting with NCACHE(region 8)
527 and SHMEM(region 9) for specific build configuration, but use the default attribute of the background
528 system address map.
529 The default attribute of the background system address map for this address space:
530 normal, write through, read allocate, non-shareable, read/write in privilege and non-privilege, executable
531
532 If application needs to fine tune MPU settings, here is an example:
533 // Region 7 (SEMC, SDRAM): [0x80000000, 0x81FFFFFF, 32M]
534 // non-shareable, read/write in privilege and non-privilege, executable. Attr 3
535 ARM_MPU_SetRegion(7U, ARM_MPU_RBAR(0x80000000, ARM_MPU_SH_NON, 0U, 1U, 0U), ARM_MPU_RLAR(0x81FFFFFF, 3U));
536 */
537 #endif
538
539 i = 0;
540 while ((nonCacheSize >> i) > 0x1U)
541 {
542 i++;
543 }
544
545 if (i != 0)
546 {
547 /* The MPU region size should be 2^N, 5<=N<=32 */
548 assert(nonCacheSize == (uint32_t)(1 << i));
549 assert(i >= 5);
550
551 /* Region 8: non-shareable, read/write in privilege and non-privilege, executable. Attr 1(non-cacheable) */
552 ARM_MPU_SetRegion(8U, ARM_MPU_RBAR(nonCacheStart, ARM_MPU_SH_NON, 0U, 1U, 0U),
553 ARM_MPU_RLAR(nonCacheStart + nonCacheSize - 1, 1U));
554 }
555
556 #if defined(__USE_SHMEM)
557 i = 0;
558 while ((rpmsgShmemSize >> i) > 0x1U)
559 {
560 i++;
561 }
562
563 if (i != 0)
564 {
565 /* The MPU region size should be 2^N, 5<=N<=32, region base should be multiples of size. */
566 assert(!(rpmsgShmemStart % rpmsgShmemSize));
567 assert(rpmsgShmemSize == (uint32_t)(1 << i));
568 assert(i >= 5);
569
570 /* Region 9: non-shareable, read/write in privilege and non-privilege, executable. Attr 1(non-cacheable) */
571 ARM_MPU_SetRegion(9U, ARM_MPU_RBAR(rpmsgShmemStart, ARM_MPU_SH_NON, 0U, 1U, 0U),
572 ARM_MPU_RLAR(rpmsgShmemStart + rpmsgShmemSize - 1, 1U));
573 }
574 #endif
575
576 #if defined(CACHE_MODE_WRITE_THROUGH)
577 /*
578 * CM33 MPU settings can't overlay, so the common MPU settings for CM33 can't handle the
579 * CACHE_MODE_WRITE_THROUGH, otherwise it may conflict(overlay) with NCACHE and SHMEN.
580 *
581 * Assume the NCACHE/SHMEM region are located in OCRAM.
582 * This is a workaround that disable the cache of OCRAM1 and OCRAM 2, based on current link settings.
583 * It impacts the performance, application may fine tune MPU according to its own linkage.
584 */
585
586 // Region 8 (OCRAM1): [0x20480000, 0x204FFFFF, 512K]
587 // non-shareable, read/write in privilege and non-privilege, executable. Attr 1
588 ARM_MPU_SetRegion(8U, ARM_MPU_RBAR(0x20480000, ARM_MPU_SH_NON, 0U, 1U, 0U), ARM_MPU_RLAR(0x204FFFFF, 1U));
589
590 // Region 9 (OCRAM2): [0x20500000, 0x2053FFFF, 256K]
591 // non-shareable, read/write in privilege and non-privilege, executable. Attr 1
592 ARM_MPU_SetRegion(9U, ARM_MPU_RBAR(0x20500000, ARM_MPU_SH_NON, 0U, 1U, 0U), ARM_MPU_RLAR(0x2053FFFF, 1U));
593 #endif
594
595 /* Enable MPU */
596 ARM_MPU_Enable(MPU_CTRL_PRIVDEFENA_Msk);
597
598 /* Enable code & system cache */
599 XCACHE_EnableCache(XCACHE_PS);
600 XCACHE_EnableCache(XCACHE_PC);
601 }
602 #endif
603
BOARD_SD_Pin_Config(uint32_t speed,uint32_t strength)604 void BOARD_SD_Pin_Config(uint32_t speed, uint32_t strength)
605 {
606 }
607
BOARD_MMC_Pin_Config(uint32_t speed,uint32_t strength)608 void BOARD_MMC_Pin_Config(uint32_t speed, uint32_t strength)
609 {
610 }
611
BOARD_DeinitFlash(FLEXSPI_Type * base)612 void BOARD_DeinitFlash(FLEXSPI_Type *base)
613 {
614 #if (__CORTEX_M == 7)
615 if (SCB_CCR_IC_Msk == (SCB_CCR_IC_Msk & SCB->CCR))
616 {
617 SCB_DisableICache();
618 }
619 #endif
620
621 #if (__CORTEX_M == 33)
622 if ((XCACHE_PC->CCR & XCACHE_CCR_ENCACHE_MASK) == 1U) /* disabled if enabled */
623 {
624 /* Enable the to push all modified lines. */
625 XCACHE_PC->CCR |= XCACHE_CCR_PUSHW0_MASK | XCACHE_CCR_PUSHW1_MASK | XCACHE_CCR_GO_MASK;
626 /* Wait until the cache command completes. */
627 while ((XCACHE_PC->CCR & XCACHE_CCR_GO_MASK) != 0x00U)
628 {
629 }
630 /* As a precaution clear the bits to avoid inadvertently re-running this command. */
631 XCACHE_PC->CCR &= ~(XCACHE_CCR_PUSHW0_MASK | XCACHE_CCR_PUSHW1_MASK);
632 XCACHE_PC->CCR &= ~XCACHE_CCR_ENCACHE_MASK;
633 __ISB();
634 __DSB();
635 }
636 #endif
637
638 /* Enable FLEXSPI module */
639 base->MCR0 &= ~FLEXSPI_MCR0_MDIS_MASK;
640
641 /* Wait until FLEXSPI is not busy */
642 while (!((base->STS0 & FLEXSPI_STS0_ARBIDLE_MASK) && (base->STS0 & FLEXSPI_STS0_SEQIDLE_MASK)))
643 {
644 }
645 /* Disable module during the reset procedure */
646 base->MCR0 |= FLEXSPI_MCR0_MDIS_MASK;
647 }
648
BOARD_InitFlash(FLEXSPI_Type * base)649 void BOARD_InitFlash(FLEXSPI_Type *base)
650 {
651 uint32_t status;
652 uint32_t lastStatus;
653 uint32_t retry;
654
655 /* If serial root clock is >= 100 MHz, DLLEN set to 1, OVRDEN set to 0, then SLVDLYTARGET setting of 0x0 is
656 * recommended. */
657 base->DLLCR[0] = 0x1U;
658
659 /* Enable FLEXSPI module */
660 base->MCR0 &= ~FLEXSPI_MCR0_MDIS_MASK;
661
662 base->MCR0 |= FLEXSPI_MCR0_SWRESET_MASK;
663 while (base->MCR0 & FLEXSPI_MCR0_SWRESET_MASK)
664 {
665 }
666
667 /* Need to wait DLL locked if DLL enabled */
668 if (0U != (base->DLLCR[0] & FLEXSPI_DLLCR_DLLEN_MASK))
669 {
670 lastStatus = base->STS2;
671 retry = BOARD_FLEXSPI_DLL_LOCK_RETRY;
672 /* Wait slave delay line locked and slave reference delay line locked. */
673 do
674 {
675 status = base->STS2;
676 if ((status & (FLEXSPI_STS2_AREFLOCK_MASK | FLEXSPI_STS2_ASLVLOCK_MASK)) ==
677 (FLEXSPI_STS2_AREFLOCK_MASK | FLEXSPI_STS2_ASLVLOCK_MASK))
678 {
679 /* Locked */
680 retry = 100;
681 break;
682 }
683 else if (status == lastStatus)
684 {
685 /* Same delay cell number in calibration */
686 retry--;
687 }
688 else
689 {
690 retry = BOARD_FLEXSPI_DLL_LOCK_RETRY;
691 lastStatus = status;
692 }
693 } while (retry > 0);
694 /* According to ERR011377, need to delay at least 100 NOPs to ensure the DLL is locked. */
695 for (; retry > 0U; retry--)
696 {
697 __NOP();
698 }
699 }
700
701 #if (__CORTEX_M == 7)
702 SCB_EnableICache();
703 #endif
704
705 #if (__CORTEX_M == 33)
706 if ((XCACHE_PC->CCR & XCACHE_CCR_ENCACHE_MASK) == 0U)
707 {
708 /* set command to invalidate all ways and write GO bit to initiate command */
709 XCACHE_PC->CCR = XCACHE_CCR_INVW1_MASK | XCACHE_CCR_INVW0_MASK;
710 XCACHE_PC->CCR |= XCACHE_CCR_GO_MASK;
711 /* Wait until the command completes */
712 while ((XCACHE_PC->CCR & XCACHE_CCR_GO_MASK) != 0U)
713 {
714 }
715 /* Enable cache */
716 XCACHE_PC->CCR = XCACHE_CCR_ENCACHE_MASK;
717 __ISB();
718 __DSB();
719 }
720 #endif
721 }
722
723 /* BOARD_SetFlexspiClock run in RAM used to configure FlexSPI clock source and divider when XIP. */
BOARD_SetFlexspiClock(FLEXSPI_Type * base,uint8_t src,uint32_t divider)724 void BOARD_SetFlexspiClock(FLEXSPI_Type *base, uint8_t src, uint32_t divider)
725 {
726 clock_root_t root;
727 clock_lpcg_t lpcg;
728
729 if (base == FLEXSPI1)
730 {
731 root = kCLOCK_Root_Flexspi1;
732 lpcg = kCLOCK_Flexspi1;
733 }
734 else if (base == FLEXSPI2)
735 {
736 root = kCLOCK_Root_Flexspi2;
737 lpcg = kCLOCK_Flexspi2;
738 }
739 else
740 {
741 return;
742 }
743
744 if (((CCM->CLOCK_ROOT[root].CONTROL & CCM_CLOCK_ROOT_CONTROL_MUX_MASK) != CCM_CLOCK_ROOT_CONTROL_MUX(src)) ||
745 ((CCM->CLOCK_ROOT[root].CONTROL & CCM_CLOCK_ROOT_CONTROL_DIV_MASK) != CCM_CLOCK_ROOT_CONTROL_DIV(divider - 1)))
746 {
747 /* Always deinit FLEXSPI and init FLEXSPI for the flash to make sure the flash works correctly after the
748 FLEXSPI root clock changed as the default FLEXSPI configuration may does not work for the new root clock
749 frequency. */
750 BOARD_DeinitFlash(base);
751
752 /* Disable clock before changing clock source */
753 CCM->LPCG[lpcg].DIRECT &= ~CCM_LPCG_DIRECT_ON_MASK;
754 __DSB();
755 __ISB();
756 while (CCM->LPCG[lpcg].STATUS0 & CCM_LPCG_STATUS0_ON_MASK)
757 {
758 }
759
760 /* Update flexspi clock. */
761 CCM->CLOCK_ROOT[root].CONTROL = CCM_CLOCK_ROOT_CONTROL_MUX(src) | CCM_CLOCK_ROOT_CONTROL_DIV(divider - 1);
762 __DSB();
763 __ISB();
764 (void)CCM->CLOCK_ROOT[root].CONTROL;
765
766 /* Enable FLEXSPI clock again */
767 CCM->LPCG[lpcg].DIRECT |= CCM_LPCG_DIRECT_ON_MASK;
768 __DSB();
769 __ISB();
770 while (!(CCM->LPCG[lpcg].STATUS0 & CCM_LPCG_STATUS0_ON_MASK))
771 {
772 }
773
774 BOARD_InitFlash(base);
775 }
776 }
777
778 /* This function is used to change FlexSPI clock to a stable source before clock sources(Such as PLL and Main clock)
779 * updating in case XIP(execute code on FLEXSPI memory.) */
BOARD_FlexspiClockSafeConfig(void)780 void BOARD_FlexspiClockSafeConfig(void)
781 {
782 /* Move FLEXSPI clock source to OSC_RC_24M to avoid instruction/data fetch issue in XIP when updating PLL. */
783 BOARD_SetFlexspiClock(FLEXSPI1, 0U, 1U);
784 }
785
786 /* This function is used to set EdgeLock clock via safe method */
EdgeLock_SetClock(uint8_t mux,uint8_t div)787 void EdgeLock_SetClock(uint8_t mux, uint8_t div)
788 {
789 if ((CLOCK_GetRootClockDiv(kCLOCK_Root_Edgelock) != (uint32_t)div) ||
790 (CLOCK_GetRootClockMux(kCLOCK_Root_Edgelock) != (uint32_t)mux))
791 {
792 status_t sts;
793 uint32_t ele_clk_mhz;
794
795 clock_root_config_t rootCfg = {
796 .div = div,
797 .mux = mux,
798 .clockOff = false,
799 };
800
801 do
802 {
803 sts = ELE_BaseAPI_ClockChangeStart(MU_RT_S3MUA);
804 } while (sts != kStatus_Success);
805
806 CLOCK_SetRootClock(kCLOCK_Root_Edgelock, &rootCfg);
807
808 ele_clk_mhz = CLOCK_GetRootClockFreq(kCLOCK_Root_Edgelock) / 1000000UL;
809 do
810 {
811 sts = ELE_BaseAPI_ClockChangeFinish(MU_RT_S3MUA, ele_clk_mhz, 0);
812 } while (sts != kStatus_Success);
813 }
814 }
815
816 /* This function is used to set DCDC output voltage via safe method */
DCDC_SetVoltage(uint8_t core,uint8_t targetVoltage)817 void DCDC_SetVoltage(uint8_t core, uint8_t targetVoltage)
818 {
819 /*
820 * When GDET is enabled, it is required to work with special ELE FW, which
821 * support ELE API VOLTAGE_CHANGE_START and VOLTAGE_CHANGE_FINISH, and
822 * DCDC voltage setting must be guarded with VOLTAGE_CHANGE_START and
823 * VOLTAGE_CHANGE_FINISH.
824 *
825 * For those ELE FW or ELE ROM, which doesn't support ELE API VOLTAGE_CHANGE_START
826 * and VOLTAGE_CHANGE_FINISH, there is no side effect to send such API command,
827 * since ELE just responde with ERROR and ingore the API command.
828 */
829 ELE_BaseAPI_VoltageChangeStart(MU_RT_S3MUA);
830
831 DCDC_SetVDD1P0BuckModeTargetVoltage(DCDC, (dcdc_core_slice_t)core, (dcdc_1P0_target_vol_t)targetVoltage);
832
833 ELE_BaseAPI_VoltageChangeFinish(MU_RT_S3MUA);
834 }
835
836 #if defined(SDK_NETC_USED) && SDK_NETC_USED
BOARD_NETC_Init(void)837 void BOARD_NETC_Init(void)
838 {
839 /* EP and Switch port 0 use RMII interface. */
840 NETC_SocSetMiiMode(kNETC_SocLinkEp0, kNETC_RmiiMode);
841 NETC_SocSetMiiMode(kNETC_SocLinkSwitchPort0, kNETC_RmiiMode);
842
843 /* Switch port 1~3 use RGMII interface. */
844 NETC_SocSetMiiMode(kNETC_SocLinkSwitchPort1, kNETC_RgmiiMode);
845 NETC_SocSetMiiMode(kNETC_SocLinkSwitchPort2, kNETC_RgmiiMode);
846 NETC_SocSetMiiMode(kNETC_SocLinkSwitchPort3, kNETC_RgmiiMode);
847
848 /* Output reference clock for RMII interface. */
849 NETC_SocSetRmiiRefClk(kNETC_SocLinkEp0, true);
850 NETC_SocSetRmiiRefClk(kNETC_SocLinkSwitchPort0, true);
851
852 /* Unlock the IERB. It will warm reset whole NETC. */
853 if (NETC_IERBUnlock() == kStatus_Success)
854 {
855 while (!NETC_IERBIsUnlockOver())
856 {
857 }
858 }
859
860 /* Set the access attribute, otherwise MSIX access will be blocked. */
861 NETC_IERB->ARRAY_NUM_RC[0].RCMSIAMQR &= ~(7U << 27);
862 NETC_IERB->ARRAY_NUM_RC[0].RCMSIAMQR |= (1U << 27);
863
864 /* Set PHY address in IERB to use MAC port MDIO, otherwise the access will be blocked. */
865 NETC_SocSetLinkAddr(kNETC_SocLinkEp0, BOARD_EP0_PHY_ADDR);
866 NETC_SocSetLinkAddr(kNETC_SocLinkSwitchPort0, BOARD_SWT_PORT0_PHY_ADDR);
867 NETC_SocSetLinkAddr(kNETC_SocLinkSwitchPort1, BOARD_SWT_PORT1_PHY_ADDR);
868 NETC_SocSetLinkAddr(kNETC_SocLinkSwitchPort2, BOARD_SWT_PORT2_PHY_ADDR);
869 NETC_SocSetLinkAddr(kNETC_SocLinkSwitchPort3, BOARD_SWT_PORT3_PHY_ADDR);
870
871 /* Lock the IERB. */
872 assert(NETC_IERBLock() == kStatus_Success);
873 while (!NETC_IERBIsLockOver())
874 {
875 }
876 }
877 #endif /* SDK_NETC_USED */
878
