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Searched refs:mcg_pll_config_t (Results 1 – 25 of 50) sorted by relevance

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/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MKM14ZA5/drivers/
Dfsl_clock.h654 } mcg_pll_config_t; typedef
687 mcg_pll_config_t pll0Config; /*!< MCGPLL0CLK configuration. */
690 mcg_pll_config_t pll1Config; /*!< MCGPLL1CLK configuration. */
1031 void CLOCK_EnablePll0(mcg_pll_config_t const *config);
1076 void CLOCK_EnablePll1(mcg_pll_config_t const *config);
1534 status_t CLOCK_SetPbeMode(mcg_pll_clk_select_t pllcs, mcg_pll_config_t const *config);
1686 status_t CLOCK_BootToPeeMode(mcg_oscsel_t oscsel, mcg_pll_clk_select_t pllcs, mcg_pll_config_t cons…
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MKM33ZA5/drivers/
Dfsl_clock.h654 } mcg_pll_config_t; typedef
687 mcg_pll_config_t pll0Config; /*!< MCGPLL0CLK configuration. */
690 mcg_pll_config_t pll1Config; /*!< MCGPLL1CLK configuration. */
1031 void CLOCK_EnablePll0(mcg_pll_config_t const *config);
1076 void CLOCK_EnablePll1(mcg_pll_config_t const *config);
1534 status_t CLOCK_SetPbeMode(mcg_pll_clk_select_t pllcs, mcg_pll_config_t const *config);
1686 status_t CLOCK_BootToPeeMode(mcg_oscsel_t oscsel, mcg_pll_clk_select_t pllcs, mcg_pll_config_t cons…
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MKL25Z4/drivers/
Dfsl_clock.h539 } mcg_pll_config_t; typedef
567 mcg_pll_config_t pll0Config; /*!< MCGPLL0CLK configuration. */
886 void CLOCK_EnablePll0(mcg_pll_config_t const *config);
1240 status_t CLOCK_SetPbeMode(mcg_pll_clk_select_t pllcs, mcg_pll_config_t const *config);
1368 status_t CLOCK_BootToPeeMode(mcg_oscsel_t oscsel, mcg_pll_clk_select_t pllcs, mcg_pll_config_t cons…
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MK22F25612/drivers/
Dfsl_clock.h572 } mcg_pll_config_t; typedef
601 mcg_pll_config_t pll0Config; /*!< MCGPLL0CLK configuration. */
965 void CLOCK_EnablePll0(mcg_pll_config_t const *config);
1350 status_t CLOCK_SetPbeMode(mcg_pll_clk_select_t pllcs, mcg_pll_config_t const *config);
1478 status_t CLOCK_BootToPeeMode(mcg_oscsel_t oscsel, mcg_pll_clk_select_t pllcs, mcg_pll_config_t cons…
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MKM34ZA5/drivers/
Dfsl_clock.h575 } mcg_pll_config_t; typedef
604 mcg_pll_config_t pll0Config; /*!< MCGPLL0CLK configuration. */
900 void CLOCK_EnablePll0(mcg_pll_config_t const *config);
1266 status_t CLOCK_SetPbeMode(mcg_pll_clk_select_t pllcs, mcg_pll_config_t const *config);
1414 status_t CLOCK_BootToPeeMode(mcg_oscsel_t oscsel, mcg_pll_clk_select_t pllcs, mcg_pll_config_t cons…
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MKV31F25612/drivers/
Dfsl_clock.h546 } mcg_pll_config_t; typedef
575 mcg_pll_config_t pll0Config; /*!< MCGPLL0CLK configuration. */
903 void CLOCK_EnablePll0(mcg_pll_config_t const *config);
1279 status_t CLOCK_SetPbeMode(mcg_pll_clk_select_t pllcs, mcg_pll_config_t const *config);
1407 status_t CLOCK_BootToPeeMode(mcg_oscsel_t oscsel, mcg_pll_clk_select_t pllcs, mcg_pll_config_t cons…
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MKW22D5/drivers/
Dfsl_clock.h569 } mcg_pll_config_t; typedef
598 mcg_pll_config_t pll0Config; /*!< MCGPLL0CLK configuration. */
938 void CLOCK_EnablePll0(mcg_pll_config_t const *config);
1301 status_t CLOCK_SetPbeMode(mcg_pll_clk_select_t pllcs, mcg_pll_config_t const *config);
1429 status_t CLOCK_BootToPeeMode(mcg_oscsel_t oscsel, mcg_pll_clk_select_t pllcs, mcg_pll_config_t cons…
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MKW24D5/drivers/
Dfsl_clock.h569 } mcg_pll_config_t; typedef
598 mcg_pll_config_t pll0Config; /*!< MCGPLL0CLK configuration. */
938 void CLOCK_EnablePll0(mcg_pll_config_t const *config);
1301 status_t CLOCK_SetPbeMode(mcg_pll_clk_select_t pllcs, mcg_pll_config_t const *config);
1429 status_t CLOCK_BootToPeeMode(mcg_oscsel_t oscsel, mcg_pll_clk_select_t pllcs, mcg_pll_config_t cons…
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MKV31F51212/drivers/
Dfsl_clock.h556 } mcg_pll_config_t; typedef
585 mcg_pll_config_t pll0Config; /*!< MCGPLL0CLK configuration. */
930 void CLOCK_EnablePll0(mcg_pll_config_t const *config);
1306 status_t CLOCK_SetPbeMode(mcg_pll_clk_select_t pllcs, mcg_pll_config_t const *config);
1434 status_t CLOCK_BootToPeeMode(mcg_oscsel_t oscsel, mcg_pll_clk_select_t pllcs, mcg_pll_config_t cons…
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MK24F12/drivers/
Dfsl_clock.h614 } mcg_pll_config_t; typedef
643 mcg_pll_config_t pll0Config; /*!< MCGPLL0CLK configuration. */
996 void CLOCK_EnablePll0(mcg_pll_config_t const *config);
1379 status_t CLOCK_SetPbeMode(mcg_pll_clk_select_t pllcs, mcg_pll_config_t const *config);
1507 status_t CLOCK_BootToPeeMode(mcg_oscsel_t oscsel, mcg_pll_clk_select_t pllcs, mcg_pll_config_t cons…
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MKM34Z7/drivers/
Dfsl_clock.h583 } mcg_pll_config_t; typedef
612 mcg_pll_config_t pll0Config; /*!< MCGPLL0CLK configuration. */
961 void CLOCK_EnablePll0(mcg_pll_config_t const *config);
1327 status_t CLOCK_SetPbeMode(mcg_pll_clk_select_t pllcs, mcg_pll_config_t const *config);
1475 status_t CLOCK_BootToPeeMode(mcg_oscsel_t oscsel, mcg_pll_clk_select_t pllcs, mcg_pll_config_t cons…
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MK22F51212/drivers/
Dfsl_clock.h581 } mcg_pll_config_t; typedef
610 mcg_pll_config_t pll0Config; /*!< MCGPLL0CLK configuration. */
983 void CLOCK_EnablePll0(mcg_pll_config_t const *config);
1368 status_t CLOCK_SetPbeMode(mcg_pll_clk_select_t pllcs, mcg_pll_config_t const *config);
1496 status_t CLOCK_BootToPeeMode(mcg_oscsel_t oscsel, mcg_pll_clk_select_t pllcs, mcg_pll_config_t cons…
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MK22F12/drivers/
Dfsl_clock.h600 } mcg_pll_config_t; typedef
629 mcg_pll_config_t pll0Config; /*!< MCGPLL0CLK configuration. */
989 void CLOCK_EnablePll0(mcg_pll_config_t const *config);
1372 status_t CLOCK_SetPbeMode(mcg_pll_clk_select_t pllcs, mcg_pll_config_t const *config);
1500 status_t CLOCK_BootToPeeMode(mcg_oscsel_t oscsel, mcg_pll_clk_select_t pllcs, mcg_pll_config_t cons…
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MKM35Z7/drivers/
Dfsl_clock.h586 } mcg_pll_config_t; typedef
615 mcg_pll_config_t pll0Config; /*!< MCGPLL0CLK configuration. */
964 void CLOCK_EnablePll0(mcg_pll_config_t const *config);
1330 status_t CLOCK_SetPbeMode(mcg_pll_clk_select_t pllcs, mcg_pll_config_t const *config);
1478 status_t CLOCK_BootToPeeMode(mcg_oscsel_t oscsel, mcg_pll_clk_select_t pllcs, mcg_pll_config_t cons…
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MKV58F24/drivers/
Dfsl_clock.h627 } mcg_pll_config_t; typedef
655 mcg_pll_config_t pll0Config; /*!< MCGPLL0CLK configuration. */
1003 void CLOCK_EnablePll0(mcg_pll_config_t const *config);
1379 status_t CLOCK_SetPbeMode(mcg_pll_clk_select_t pllcs, mcg_pll_config_t const *config);
1507 status_t CLOCK_BootToPeeMode(mcg_oscsel_t oscsel, mcg_pll_clk_select_t pllcs, mcg_pll_config_t cons…
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MKV56F24/drivers/
Dfsl_clock.h627 } mcg_pll_config_t; typedef
655 mcg_pll_config_t pll0Config; /*!< MCGPLL0CLK configuration. */
1002 void CLOCK_EnablePll0(mcg_pll_config_t const *config);
1378 status_t CLOCK_SetPbeMode(mcg_pll_clk_select_t pllcs, mcg_pll_config_t const *config);
1506 status_t CLOCK_BootToPeeMode(mcg_oscsel_t oscsel, mcg_pll_clk_select_t pllcs, mcg_pll_config_t cons…
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MK63F12/drivers/
Dfsl_clock.h622 } mcg_pll_config_t; typedef
651 mcg_pll_config_t pll0Config; /*!< MCGPLL0CLK configuration. */
1024 void CLOCK_EnablePll0(mcg_pll_config_t const *config);
1407 status_t CLOCK_SetPbeMode(mcg_pll_clk_select_t pllcs, mcg_pll_config_t const *config);
1535 status_t CLOCK_BootToPeeMode(mcg_oscsel_t oscsel, mcg_pll_clk_select_t pllcs, mcg_pll_config_t cons…
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MK64F12/drivers/
Dfsl_clock.h622 } mcg_pll_config_t; typedef
651 mcg_pll_config_t pll0Config; /*!< MCGPLL0CLK configuration. */
1030 void CLOCK_EnablePll0(mcg_pll_config_t const *config);
1413 status_t CLOCK_SetPbeMode(mcg_pll_clk_select_t pllcs, mcg_pll_config_t const *config);
1541 status_t CLOCK_BootToPeeMode(mcg_oscsel_t oscsel, mcg_pll_clk_select_t pllcs, mcg_pll_config_t cons…
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MK26F18/drivers/
Dfsl_clock.h671 } mcg_pll_config_t; typedef
700 mcg_pll_config_t pll0Config; /*!< MCGPLL0CLK configuration. */
1180 void CLOCK_EnablePll0(mcg_pll_config_t const *config);
1585 status_t CLOCK_SetPbeMode(mcg_pll_clk_select_t pllcs, mcg_pll_config_t const *config);
1713 status_t CLOCK_BootToPeeMode(mcg_oscsel_t oscsel, mcg_pll_clk_select_t pllcs, mcg_pll_config_t cons…
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MK27FA15/drivers/
Dfsl_clock.h681 } mcg_pll_config_t; typedef
710 mcg_pll_config_t pll0Config; /*!< MCGPLL0CLK configuration. */
1193 void CLOCK_EnablePll0(mcg_pll_config_t const *config);
1598 status_t CLOCK_SetPbeMode(mcg_pll_clk_select_t pllcs, mcg_pll_config_t const *config);
1726 status_t CLOCK_BootToPeeMode(mcg_oscsel_t oscsel, mcg_pll_clk_select_t pllcs, mcg_pll_config_t cons…
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MK28FA15/drivers/
Dfsl_clock.h681 } mcg_pll_config_t; typedef
710 mcg_pll_config_t pll0Config; /*!< MCGPLL0CLK configuration. */
1195 void CLOCK_EnablePll0(mcg_pll_config_t const *config);
1600 status_t CLOCK_SetPbeMode(mcg_pll_clk_select_t pllcs, mcg_pll_config_t const *config);
1728 status_t CLOCK_BootToPeeMode(mcg_oscsel_t oscsel, mcg_pll_clk_select_t pllcs, mcg_pll_config_t cons…
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MK80F25615/drivers/
Dfsl_clock.h647 } mcg_pll_config_t; typedef
676 mcg_pll_config_t pll0Config; /*!< MCGPLL0CLK configuration. */
1094 void CLOCK_EnablePll0(mcg_pll_config_t const *config);
1479 status_t CLOCK_SetPbeMode(mcg_pll_clk_select_t pllcs, mcg_pll_config_t const *config);
1607 status_t CLOCK_BootToPeeMode(mcg_oscsel_t oscsel, mcg_pll_clk_select_t pllcs, mcg_pll_config_t cons…
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MK82F25615/drivers/
Dfsl_clock.h654 } mcg_pll_config_t; typedef
683 mcg_pll_config_t pll0Config; /*!< MCGPLL0CLK configuration. */
1101 void CLOCK_EnablePll0(mcg_pll_config_t const *config);
1486 status_t CLOCK_SetPbeMode(mcg_pll_clk_select_t pllcs, mcg_pll_config_t const *config);
1614 status_t CLOCK_BootToPeeMode(mcg_oscsel_t oscsel, mcg_pll_clk_select_t pllcs, mcg_pll_config_t cons…
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MK65F18/drivers/
Dfsl_clock.h678 } mcg_pll_config_t; typedef
707 mcg_pll_config_t pll0Config; /*!< MCGPLL0CLK configuration. */
1208 void CLOCK_EnablePll0(mcg_pll_config_t const *config);
1613 status_t CLOCK_SetPbeMode(mcg_pll_clk_select_t pllcs, mcg_pll_config_t const *config);
1741 status_t CLOCK_BootToPeeMode(mcg_oscsel_t oscsel, mcg_pll_clk_select_t pllcs, mcg_pll_config_t cons…
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MK66F18/drivers/
Dfsl_clock.h677 } mcg_pll_config_t; typedef
706 mcg_pll_config_t pll0Config; /*!< MCGPLL0CLK configuration. */
1207 void CLOCK_EnablePll0(mcg_pll_config_t const *config);
1612 status_t CLOCK_SetPbeMode(mcg_pll_clk_select_t pllcs, mcg_pll_config_t const *config);
1740 status_t CLOCK_BootToPeeMode(mcg_oscsel_t oscsel, mcg_pll_clk_select_t pllcs, mcg_pll_config_t cons…

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