1 /*
2 * Copyright (c) 2015, Freescale Semiconductor, Inc.
3 * Copyright 2016 - 2020, 2022 NXP
4 * All rights reserved.
5 *
6 * SPDX-License-Identifier: BSD-3-Clause
7 */
8
9 #ifndef _FSL_CLOCK_H_
10 #define _FSL_CLOCK_H_
11
12 #include "fsl_common.h"
13
14 /*! @addtogroup clock */
15 /*! @{ */
16
17 /*! @file */
18
19 /*******************************************************************************
20 * Configurations
21 ******************************************************************************/
22
23 /*! @brief Configures whether to check a parameter in a function.
24 *
25 * Some MCG settings must be changed with conditions, for example:
26 * 1. MCGIRCLK settings, such as the source, divider, and the trim value should not change when
27 * MCGIRCLK is used as a system clock source.
28 * 2. MCG_C7[OSCSEL] should not be changed when the external reference clock is used
29 * as a system clock source. For example, in FBE/BLPE/PBE modes.
30 * 3. The users should only switch between the supported clock modes.
31 *
32 * MCG functions check the parameter and MCG status before setting, if not allowed
33 * to change, the functions return error. The parameter checking increases code size,
34 * if code size is a critical requirement, change #MCG_CONFIG_CHECK_PARAM to 0 to
35 * disable parameter checking.
36 */
37 #ifndef MCG_CONFIG_CHECK_PARAM
38 #define MCG_CONFIG_CHECK_PARAM 0U
39 #endif
40
41 /*! @brief Configure whether driver controls clock
42 *
43 * When set to 0, peripheral drivers will enable clock in initialize function
44 * and disable clock in de-initialize function. When set to 1, peripheral
45 * driver will not control the clock, application could control the clock out of
46 * the driver.
47 *
48 * @note All drivers share this feature switcher. If it is set to 1, application
49 * should handle clock enable and disable for all drivers.
50 */
51 #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL))
52 #define FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL 0
53 #endif
54
55 /*******************************************************************************
56 * Definitions
57 ******************************************************************************/
58
59 /*! @name Driver version */
60 /*@{*/
61 /*! @brief CLOCK driver version 2.6.1. */
62 #define FSL_CLOCK_DRIVER_VERSION (MAKE_VERSION(2, 6, 1))
63 /*@}*/
64
65 /*! @brief External XTAL0 (OSC0) clock frequency.
66 *
67 * The XTAL0/EXTAL0 (OSC0) clock frequency in Hz. When the clock is set up, use the
68 * function CLOCK_SetXtal0Freq to set the value in the clock driver. For example,
69 * if XTAL0 is 8 MHz:
70 * @code
71 * Set up the OSC0
72 * CLOCK_InitOsc0(...);
73 * Set the XTAL0 value to the clock driver.
74 * CLOCK_SetXtal0Freq(80000000);
75 * @endcode
76 *
77 * This is important for the multicore platforms where only one core needs to set up the
78 * OSC0 using the CLOCK_InitOsc0. All other cores need to call the CLOCK_SetXtal0Freq
79 * to get a valid clock frequency.
80 */
81 extern volatile uint32_t g_xtal0Freq;
82
83 /*! @brief External XTAL32/EXTAL32/RTC_CLKIN clock frequency.
84 *
85 * The XTAL32/EXTAL32/RTC_CLKIN clock frequency in Hz. When the clock is set up, use the
86 * function CLOCK_SetXtal32Freq to set the value in the clock driver.
87 *
88 * This is important for the multicore platforms where only one core needs to set up
89 * the clock. All other cores need to call the CLOCK_SetXtal32Freq
90 * to get a valid clock frequency.
91 */
92 extern volatile uint32_t g_xtal32Freq;
93
94 #if (defined(OSC) && !(defined(OSC0)))
95 #define OSC0 OSC
96 #endif
97
98 /* Definition for delay API in clock driver, users can redefine it to the real application. */
99 #ifndef SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY
100 #define SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY (120000000UL)
101 #endif
102
103 /*! @brief Clock ip name array for DMAMUX. */
104 #define DMAMUX_CLOCKS \
105 { \
106 kCLOCK_Dmamux0 \
107 }
108
109 /*! @brief Clock ip name array for RTC. */
110 #define RTC_CLOCKS \
111 { \
112 kCLOCK_Rtc0 \
113 }
114
115 /*! @brief Clock ip name array for SAI. */
116 #define SAI_CLOCKS \
117 { \
118 kCLOCK_Sai0 \
119 }
120
121 /*! @brief Clock ip name array for PORT. */
122 #define PORT_CLOCKS \
123 { \
124 kCLOCK_PortA, kCLOCK_PortB, kCLOCK_PortC, kCLOCK_PortD, kCLOCK_PortE \
125 }
126
127 /*! @brief Clock ip name array for FLEXBUS. */
128 #define FLEXBUS_CLOCKS \
129 { \
130 kCLOCK_Flexbus0 \
131 }
132
133 /*! @brief Clock ip name array for EWM. */
134 #define EWM_CLOCKS \
135 { \
136 kCLOCK_Ewm0 \
137 }
138
139 /*! @brief Clock ip name array for PIT. */
140 #define PIT_CLOCKS \
141 { \
142 kCLOCK_Pit0 \
143 }
144
145 /*! @brief Clock ip name array for SDHC. */
146 #define SDHC_CLOCKS \
147 { \
148 kCLOCK_Sdhc0 \
149 }
150
151 /*! @brief Clock ip name array for DSPI. */
152 #define DSPI_CLOCKS \
153 { \
154 kCLOCK_Spi0, kCLOCK_Spi1, kCLOCK_Spi2 \
155 }
156
157 /*! @brief Clock ip name array for LPTMR. */
158 #define LPTMR_CLOCKS \
159 { \
160 kCLOCK_Lptmr0 \
161 }
162
163 /*! @brief Clock ip name array for FTM. */
164 #define FTM_CLOCKS \
165 { \
166 kCLOCK_Ftm0, kCLOCK_Ftm1, kCLOCK_Ftm2, kCLOCK_Ftm3 \
167 }
168
169 /*! @brief Clock ip name array for EDMA. */
170 #define EDMA_CLOCKS \
171 { \
172 kCLOCK_Dma0 \
173 }
174
175 /*! @brief Clock ip name array for DAC. */
176 #define DAC_CLOCKS \
177 { \
178 kCLOCK_Dac0, kCLOCK_Dac1 \
179 }
180
181 /*! @brief Clock ip name array for ADC16. */
182 #define ADC16_CLOCKS \
183 { \
184 kCLOCK_Adc0, kCLOCK_Adc1 \
185 }
186
187 /*! @brief Clock ip name array for VREF. */
188 #define VREF_CLOCKS \
189 { \
190 kCLOCK_Vref0 \
191 }
192
193 /*! @brief Clock ip name array for UART. */
194 #define UART_CLOCKS \
195 { \
196 kCLOCK_Uart0, kCLOCK_Uart1, kCLOCK_Uart2, kCLOCK_Uart3, kCLOCK_Uart4, kCLOCK_Uart5 \
197 }
198
199 /*! @brief Clock ip name array for CRC. */
200 #define CRC_CLOCKS \
201 { \
202 kCLOCK_Crc0 \
203 }
204
205 /*! @brief Clock ip name array for I2C. */
206 #define I2C_CLOCKS \
207 { \
208 kCLOCK_I2c0, kCLOCK_I2c1, kCLOCK_I2c2 \
209 }
210
211 /*! @brief Clock ip name array for FTF. */
212 #define FTF_CLOCKS \
213 { \
214 kCLOCK_Ftf0 \
215 }
216
217 /*! @brief Clock ip name array for PDB. */
218 #define PDB_CLOCKS \
219 { \
220 kCLOCK_Pdb0 \
221 }
222
223 /*! @brief Clock ip name array for FLEXCAN. */
224 #define FLEXCAN_CLOCKS \
225 { \
226 kCLOCK_Flexcan0 \
227 }
228
229 /*! @brief Clock ip name array for CMT. */
230 #define CMT_CLOCKS \
231 { \
232 kCLOCK_Cmt0 \
233 }
234
235 /*! @brief Clock ip name array for MPU. */
236 #define SYSMPU_CLOCKS \
237 { \
238 kCLOCK_Sysmpu0 \
239 }
240
241 /*! @brief Clock ip name array for CMP. */
242 #define CMP_CLOCKS \
243 { \
244 kCLOCK_Cmp0, kCLOCK_Cmp1, kCLOCK_Cmp2 \
245 }
246
247 /*!
248 * @brief LPO clock frequency.
249 */
250 #define LPO_CLK_FREQ 1000U
251
252 /*! @brief Peripherals clock source definition. */
253 #define SYS_CLK kCLOCK_CoreSysClk
254 #define BUS_CLK kCLOCK_BusClk
255 #define FAST_CLK kCLOCK_FastPeriphClk
256
257 #define I2C0_CLK_SRC BUS_CLK
258 #define I2C1_CLK_SRC BUS_CLK
259 #define DSPI0_CLK_SRC BUS_CLK
260 #define DSPI1_CLK_SRC BUS_CLK
261 #define UART0_CLK_SRC SYS_CLK
262 #define UART1_CLK_SRC SYS_CLK
263 #define UART2_CLK_SRC BUS_CLK
264
265 /*! @brief Clock name used to get clock frequency. */
266 typedef enum _clock_name
267 {
268
269 /* ----------------------------- System layer clock -------------------------------*/
270 kCLOCK_CoreSysClk, /*!< Core/system clock */
271 kCLOCK_PlatClk, /*!< Platform clock */
272 kCLOCK_BusClk, /*!< Bus clock */
273 kCLOCK_FlexBusClk, /*!< FlexBus clock */
274 kCLOCK_FlashClk, /*!< Flash clock */
275 kCLOCK_FastPeriphClk, /*!< Fast peripheral clock */
276 kCLOCK_PllFllSelClk, /*!< The clock after SIM[PLLFLLSEL]. */
277
278 /* ---------------------------------- OSC clock -----------------------------------*/
279 kCLOCK_Er32kClk, /*!< External reference 32K clock (ERCLK32K) */
280 kCLOCK_Osc0ErClk, /*!< OSC0 external reference clock (OSC0ERCLK) */
281 kCLOCK_Osc1ErClk, /*!< OSC1 external reference clock (OSC1ERCLK) */
282 kCLOCK_Osc0ErClkUndiv, /*!< OSC0 external reference undivided clock(OSC0ERCLK_UNDIV). */
283
284 /* ----------------------------- MCG and MCG-Lite clock ---------------------------*/
285 kCLOCK_McgFixedFreqClk, /*!< MCG fixed frequency clock (MCGFFCLK) */
286 kCLOCK_McgInternalRefClk, /*!< MCG internal reference clock (MCGIRCLK) */
287 kCLOCK_McgFllClk, /*!< MCGFLLCLK */
288 kCLOCK_McgPll0Clk, /*!< MCGPLL0CLK */
289 kCLOCK_McgPll1Clk, /*!< MCGPLL1CLK */
290 kCLOCK_McgExtPllClk, /*!< EXT_PLLCLK */
291 kCLOCK_McgPeriphClk, /*!< MCG peripheral clock (MCGPCLK) */
292 kCLOCK_McgIrc48MClk, /*!< MCG IRC48M clock */
293
294 /* --------------------------------- Other clock ----------------------------------*/
295 kCLOCK_LpoClk, /*!< LPO clock */
296
297 } clock_name_t;
298
299 /*! @brief USB clock source definition. */
300 typedef enum _clock_usb_src
301 {
302 kCLOCK_UsbSrcPll0 = SIM_SOPT2_USBSRC(1U) | SIM_SOPT2_PLLFLLSEL(1U), /*!< Use PLL0. */
303 kCLOCK_UsbSrcIrc48M = SIM_SOPT2_USBSRC(1U) | SIM_SOPT2_PLLFLLSEL(3U), /*!< Use IRC48M. */
304 kCLOCK_UsbSrcExt = SIM_SOPT2_USBSRC(0U) /*!< Use USB_CLKIN. */
305 } clock_usb_src_t;
306 /*------------------------------------------------------------------------------
307
308 clock_gate_t definition:
309
310 31 16 0
311 -----------------------------------------------------------------
312 | SIM_SCGC register offset | control bit offset in SCGC |
313 -----------------------------------------------------------------
314
315 For example, the SDHC clock gate is controlled by SIM_SCGC3[17], the
316 SIM_SCGC3 offset in SIM is 0x1030, then kCLOCK_GateSdhc0 is defined as
317
318 kCLOCK_GateSdhc0 = (0x1030 << 16) | 17;
319
320 ------------------------------------------------------------------------------*/
321
322 #define CLK_GATE_REG_OFFSET_SHIFT 16U
323 #define CLK_GATE_REG_OFFSET_MASK 0xFFFF0000U
324 #define CLK_GATE_BIT_SHIFT_SHIFT 0U
325 #define CLK_GATE_BIT_SHIFT_MASK 0x0000FFFFU
326
327 #define CLK_GATE_DEFINE(reg_offset, bit_shift) \
328 ((((reg_offset) << CLK_GATE_REG_OFFSET_SHIFT) & CLK_GATE_REG_OFFSET_MASK) | \
329 (((bit_shift) << CLK_GATE_BIT_SHIFT_SHIFT) & CLK_GATE_BIT_SHIFT_MASK))
330
331 #define CLK_GATE_ABSTRACT_REG_OFFSET(x) (((x)&CLK_GATE_REG_OFFSET_MASK) >> CLK_GATE_REG_OFFSET_SHIFT)
332 #define CLK_GATE_ABSTRACT_BITS_SHIFT(x) (((x)&CLK_GATE_BIT_SHIFT_MASK) >> CLK_GATE_BIT_SHIFT_SHIFT)
333
334 /*! @brief Clock gate name used for CLOCK_EnableClock/CLOCK_DisableClock. */
335 typedef enum _clock_ip_name
336 {
337 kCLOCK_IpInvalid = 0U,
338
339 kCLOCK_I2c2 = CLK_GATE_DEFINE(0x1028U, 6U),
340 kCLOCK_Uart4 = CLK_GATE_DEFINE(0x1028U, 10U),
341 kCLOCK_Uart5 = CLK_GATE_DEFINE(0x1028U, 11U),
342
343 kCLOCK_Dac0 = CLK_GATE_DEFINE(0x102CU, 12U),
344 kCLOCK_Dac1 = CLK_GATE_DEFINE(0x102CU, 13U),
345
346 kCLOCK_Spi2 = CLK_GATE_DEFINE(0x1030U, 12U),
347 kCLOCK_Sdhc0 = CLK_GATE_DEFINE(0x1030U, 17U),
348 kCLOCK_Ftm2 = CLK_GATE_DEFINE(0x1030U, 24U),
349 kCLOCK_Ftm3 = CLK_GATE_DEFINE(0x1030U, 25U),
350 kCLOCK_Adc1 = CLK_GATE_DEFINE(0x1030U, 27U),
351
352 kCLOCK_Ewm0 = CLK_GATE_DEFINE(0x1034U, 1U),
353 kCLOCK_Cmt0 = CLK_GATE_DEFINE(0x1034U, 2U),
354 kCLOCK_I2c0 = CLK_GATE_DEFINE(0x1034U, 6U),
355 kCLOCK_I2c1 = CLK_GATE_DEFINE(0x1034U, 7U),
356 kCLOCK_Uart0 = CLK_GATE_DEFINE(0x1034U, 10U),
357 kCLOCK_Uart1 = CLK_GATE_DEFINE(0x1034U, 11U),
358 kCLOCK_Uart2 = CLK_GATE_DEFINE(0x1034U, 12U),
359 kCLOCK_Uart3 = CLK_GATE_DEFINE(0x1034U, 13U),
360 kCLOCK_Usbfs0 = CLK_GATE_DEFINE(0x1034U, 18U),
361 kCLOCK_Cmp0 = CLK_GATE_DEFINE(0x1034U, 19U),
362 kCLOCK_Cmp1 = CLK_GATE_DEFINE(0x1034U, 19U),
363 kCLOCK_Cmp2 = CLK_GATE_DEFINE(0x1034U, 19U),
364 kCLOCK_Vref0 = CLK_GATE_DEFINE(0x1034U, 20U),
365
366 kCLOCK_Lptmr0 = CLK_GATE_DEFINE(0x1038U, 0U),
367 kCLOCK_PortA = CLK_GATE_DEFINE(0x1038U, 9U),
368 kCLOCK_PortB = CLK_GATE_DEFINE(0x1038U, 10U),
369 kCLOCK_PortC = CLK_GATE_DEFINE(0x1038U, 11U),
370 kCLOCK_PortD = CLK_GATE_DEFINE(0x1038U, 12U),
371 kCLOCK_PortE = CLK_GATE_DEFINE(0x1038U, 13U),
372
373 kCLOCK_Ftf0 = CLK_GATE_DEFINE(0x103CU, 0U),
374 kCLOCK_Dmamux0 = CLK_GATE_DEFINE(0x103CU, 1U),
375 kCLOCK_Flexcan0 = CLK_GATE_DEFINE(0x103CU, 4U),
376 kCLOCK_Spi0 = CLK_GATE_DEFINE(0x103CU, 12U),
377 kCLOCK_Spi1 = CLK_GATE_DEFINE(0x103CU, 13U),
378 kCLOCK_Sai0 = CLK_GATE_DEFINE(0x103CU, 15U),
379 kCLOCK_Crc0 = CLK_GATE_DEFINE(0x103CU, 18U),
380 kCLOCK_Usbdcd0 = CLK_GATE_DEFINE(0x103CU, 21U),
381 kCLOCK_Pdb0 = CLK_GATE_DEFINE(0x103CU, 22U),
382 kCLOCK_Pit0 = CLK_GATE_DEFINE(0x103CU, 23U),
383 kCLOCK_Ftm0 = CLK_GATE_DEFINE(0x103CU, 24U),
384 kCLOCK_Ftm1 = CLK_GATE_DEFINE(0x103CU, 25U),
385 kCLOCK_Adc0 = CLK_GATE_DEFINE(0x103CU, 27U),
386 kCLOCK_Rtc0 = CLK_GATE_DEFINE(0x103CU, 29U),
387
388 kCLOCK_Flexbus0 = CLK_GATE_DEFINE(0x1040U, 0U),
389 kCLOCK_Dma0 = CLK_GATE_DEFINE(0x1040U, 1U),
390 kCLOCK_Sysmpu0 = CLK_GATE_DEFINE(0x1040U, 2U),
391 } clock_ip_name_t;
392
393 /*!@brief SIM configuration structure for clock setting. */
394 typedef struct _sim_clock_config
395 {
396 uint8_t pllFllSel; /*!< PLL/FLL/IRC48M selection. */
397 uint8_t er32kSrc; /*!< ERCLK32K source selection. */
398 uint32_t clkdiv1; /*!< SIM_CLKDIV1. */
399 } sim_clock_config_t;
400
401 /*! @brief OSC work mode. */
402 typedef enum _osc_mode
403 {
404 kOSC_ModeExt = 0U, /*!< Use an external clock. */
405 #if (defined(MCG_C2_EREFS_MASK) && !(defined(MCG_C2_EREFS0_MASK)))
406 kOSC_ModeOscLowPower = MCG_C2_EREFS_MASK, /*!< Oscillator low power. */
407 #else
408 kOSC_ModeOscLowPower = MCG_C2_EREFS0_MASK, /*!< Oscillator low power. */
409 #endif
410 kOSC_ModeOscHighGain = 0U
411 #if (defined(MCG_C2_EREFS_MASK) && !(defined(MCG_C2_EREFS0_MASK)))
412 | MCG_C2_EREFS_MASK
413 #else
414 | MCG_C2_EREFS0_MASK
415 #endif
416 #if (defined(MCG_C2_HGO_MASK) && !(defined(MCG_C2_HGO0_MASK)))
417 | MCG_C2_HGO_MASK, /*!< Oscillator high gain. */
418 #else
419 | MCG_C2_HGO0_MASK, /*!< Oscillator high gain. */
420 #endif
421 } osc_mode_t;
422
423 /*! @brief Oscillator capacitor load setting.*/
424 enum _osc_cap_load
425 {
426 kOSC_Cap2P = OSC_CR_SC2P_MASK, /*!< 2 pF capacitor load */
427 kOSC_Cap4P = OSC_CR_SC4P_MASK, /*!< 4 pF capacitor load */
428 kOSC_Cap8P = OSC_CR_SC8P_MASK, /*!< 8 pF capacitor load */
429 kOSC_Cap16P = OSC_CR_SC16P_MASK /*!< 16 pF capacitor load */
430 };
431
432 /*! @brief OSCERCLK enable mode. */
433 enum _oscer_enable_mode
434 {
435 kOSC_ErClkEnable = OSC_CR_ERCLKEN_MASK, /*!< Enable. */
436 kOSC_ErClkEnableInStop = OSC_CR_EREFSTEN_MASK /*!< Enable in stop mode. */
437 };
438
439 /*! @brief OSC configuration for OSCERCLK. */
440 typedef struct _oscer_config
441 {
442 uint8_t enableMode; /*!< OSCERCLK enable mode. OR'ed value of @ref _oscer_enable_mode. */
443
444 } oscer_config_t;
445
446 /*!
447 * @brief OSC Initialization Configuration Structure
448 *
449 * Defines the configuration data structure to initialize the OSC.
450 * When porting to a new board, set the following members
451 * according to the board setting:
452 * 1. freq: The external frequency.
453 * 2. workMode: The OSC module mode.
454 */
455 typedef struct _osc_config
456 {
457 uint32_t freq; /*!< External clock frequency. */
458 uint8_t capLoad; /*!< Capacitor load setting. */
459 osc_mode_t workMode; /*!< OSC work mode setting. */
460 oscer_config_t oscerConfig; /*!< Configuration for OSCERCLK. */
461 } osc_config_t;
462
463 /*! @brief MCG FLL reference clock source select. */
464 typedef enum _mcg_fll_src
465 {
466 kMCG_FllSrcExternal, /*!< External reference clock is selected */
467 kMCG_FllSrcInternal /*!< The slow internal reference clock is selected */
468 } mcg_fll_src_t;
469
470 /*! @brief MCG internal reference clock select */
471 typedef enum _mcg_irc_mode
472 {
473 kMCG_IrcSlow, /*!< Slow internal reference clock selected */
474 kMCG_IrcFast /*!< Fast internal reference clock selected */
475 } mcg_irc_mode_t;
476
477 /*! @brief MCG DCO Maximum Frequency with 32.768 kHz Reference */
478 typedef enum _mcg_dmx32
479 {
480 kMCG_Dmx32Default, /*!< DCO has a default range of 25% */
481 kMCG_Dmx32Fine /*!< DCO is fine-tuned for maximum frequency with 32.768 kHz reference */
482 } mcg_dmx32_t;
483
484 /*! @brief MCG DCO range select */
485 typedef enum _mcg_drs
486 {
487 kMCG_DrsLow, /*!< Low frequency range */
488 kMCG_DrsMid, /*!< Mid frequency range */
489 kMCG_DrsMidHigh, /*!< Mid-High frequency range */
490 kMCG_DrsHigh /*!< High frequency range */
491 } mcg_drs_t;
492
493 /*! @brief MCG PLL reference clock select */
494 typedef enum _mcg_pll_ref_src
495 {
496 kMCG_PllRefOsc0, /*!< Selects OSC0 as PLL reference clock */
497 kMCG_PllRefOsc1 /*!< Selects OSC1 as PLL reference clock */
498 } mcg_pll_ref_src_t;
499
500 /*! @brief MCGOUT clock source. */
501 typedef enum _mcg_clkout_src
502 {
503 kMCG_ClkOutSrcOut, /*!< Output of the FLL is selected (reset default) */
504 kMCG_ClkOutSrcInternal, /*!< Internal reference clock is selected */
505 kMCG_ClkOutSrcExternal, /*!< External reference clock is selected */
506 } mcg_clkout_src_t;
507
508 /*! @brief MCG Automatic Trim Machine Select */
509 typedef enum _mcg_atm_select
510 {
511 kMCG_AtmSel32k, /*!< 32 kHz Internal Reference Clock selected */
512 kMCG_AtmSel4m /*!< 4 MHz Internal Reference Clock selected */
513 } mcg_atm_select_t;
514
515 /*! @brief MCG OSC Clock Select */
516 typedef enum _mcg_oscsel
517 {
518 kMCG_OscselOsc, /*!< Selects System Oscillator (OSCCLK) */
519 kMCG_OscselRtc, /*!< Selects 32 kHz RTC Oscillator */
520 } mcg_oscsel_t;
521
522 /*! @brief MCG PLLCS select */
523 typedef enum _mcg_pll_clk_select
524 {
525 kMCG_PllClkSelPll0, /*!< PLL0 output clock is selected */
526 kMCG_PllClkSelPll1 /* PLL1 output clock is selected */
527 } mcg_pll_clk_select_t;
528
529 /*! @brief MCG clock monitor mode. */
530 typedef enum _mcg_monitor_mode
531 {
532 kMCG_MonitorNone, /*!< Clock monitor is disabled. */
533 kMCG_MonitorInt, /*!< Trigger interrupt when clock lost. */
534 kMCG_MonitorReset /*!< System reset when clock lost. */
535 } mcg_monitor_mode_t;
536
537 /*! @brief MCG status. Enumeration _mcg_status */
538 enum
539 {
540 kStatus_MCG_ModeUnreachable = MAKE_STATUS(kStatusGroup_MCG, 0U), /*!< Can't switch to target mode. */
541 kStatus_MCG_ModeInvalid = MAKE_STATUS(kStatusGroup_MCG, 1U), /*!< Current mode invalid for the specific
542 function. */
543 kStatus_MCG_AtmBusClockInvalid = MAKE_STATUS(kStatusGroup_MCG, 2U), /*!< Invalid bus clock for ATM. */
544 kStatus_MCG_AtmDesiredFreqInvalid = MAKE_STATUS(kStatusGroup_MCG, 3U), /*!< Invalid desired frequency for ATM. */
545 kStatus_MCG_AtmIrcUsed = MAKE_STATUS(kStatusGroup_MCG, 4U), /*!< IRC is used when using ATM. */
546 kStatus_MCG_AtmHardwareFail = MAKE_STATUS(kStatusGroup_MCG, 5U), /*!< Hardware fail occurs during ATM. */
547 kStatus_MCG_SourceUsed = MAKE_STATUS(kStatusGroup_MCG, 6U) /*!< Can't change the clock source because
548 it is in use. */
549 };
550
551 /*! @brief MCG status flags. Enumeration _mcg_status_flags_t */
552 enum
553 {
554 kMCG_Osc0LostFlag = (1U << 0U), /*!< OSC0 lost. */
555 kMCG_Osc0InitFlag = (1U << 1U), /*!< OSC0 crystal initialized. */
556 kMCG_RtcOscLostFlag = (1U << 4U), /*!< RTC OSC lost. */
557 kMCG_Pll0LostFlag = (1U << 5U), /*!< PLL0 lost. */
558 kMCG_Pll0LockFlag = (1U << 6U), /*!< PLL0 locked. */
559 };
560
561 /*! @brief MCG internal reference clock (MCGIRCLK) enable mode definition. Enumeration _mcg_irclk_enable_mode */
562 enum
563 {
564 kMCG_IrclkEnable = MCG_C1_IRCLKEN_MASK, /*!< MCGIRCLK enable. */
565 kMCG_IrclkEnableInStop = MCG_C1_IREFSTEN_MASK /*!< MCGIRCLK enable in stop mode. */
566 };
567
568 /*! @brief MCG PLL clock enable mode definition. Enumeration _mcg_pll_enable_mode */
569 enum
570 {
571 kMCG_PllEnableIndependent = MCG_C5_PLLCLKEN0_MASK, /*!< MCGPLLCLK enable independent of the
572 MCG clock mode. Generally, the PLL
573 is disabled in FLL modes
574 (FEI/FBI/FEE/FBE). Setting the PLL clock
575 enable independent, enables the
576 PLL in the FLL modes. */
577 kMCG_PllEnableInStop = MCG_C5_PLLSTEN0_MASK /*!< MCGPLLCLK enable in STOP mode. */
578 };
579
580 /*! @brief MCG mode definitions */
581 typedef enum _mcg_mode
582 {
583 kMCG_ModeFEI = 0U, /*!< FEI - FLL Engaged Internal */
584 kMCG_ModeFBI, /*!< FBI - FLL Bypassed Internal */
585 kMCG_ModeBLPI, /*!< BLPI - Bypassed Low Power Internal */
586 kMCG_ModeFEE, /*!< FEE - FLL Engaged External */
587 kMCG_ModeFBE, /*!< FBE - FLL Bypassed External */
588 kMCG_ModeBLPE, /*!< BLPE - Bypassed Low Power External */
589 kMCG_ModePBE, /*!< PBE - PLL Bypassed External */
590 kMCG_ModePEE, /*!< PEE - PLL Engaged External */
591 kMCG_ModeError /*!< Unknown mode */
592 } mcg_mode_t;
593
594 /*! @brief MCG PLL configuration. */
595 typedef struct _mcg_pll_config
596 {
597 uint8_t enableMode; /*!< Enable mode. OR'ed value of enumeration _mcg_pll_enable_mode. */
598 uint8_t prdiv; /*!< Reference divider PRDIV. */
599 uint8_t vdiv; /*!< VCO divider VDIV. */
600 } mcg_pll_config_t;
601
602 /*! @brief MCG mode change configuration structure
603 *
604 * When porting to a new board, set the following members
605 * according to the board setting:
606 * 1. frdiv: If the FLL uses the external reference clock, set this
607 * value to ensure that the external reference clock divided by frdiv is
608 * in the 31.25 kHz to 39.0625 kHz range.
609 * 2. The PLL reference clock divider PRDIV: PLL reference clock frequency after
610 * PRDIV should be in the FSL_FEATURE_MCG_PLL_REF_MIN to
611 * FSL_FEATURE_MCG_PLL_REF_MAX range.
612 */
613 typedef struct _mcg_config
614 {
615 mcg_mode_t mcgMode; /*!< MCG mode. */
616
617 /* ----------------------- MCGIRCCLK settings ------------------------ */
618 uint8_t irclkEnableMode; /*!< MCGIRCLK enable mode. */
619 mcg_irc_mode_t ircs; /*!< Source, MCG_C2[IRCS]. */
620 uint8_t fcrdiv; /*!< Divider, MCG_SC[FCRDIV]. */
621
622 /* ------------------------ MCG FLL settings ------------------------- */
623 uint8_t frdiv; /*!< Divider MCG_C1[FRDIV]. */
624 mcg_drs_t drs; /*!< DCO range MCG_C4[DRST_DRS]. */
625 mcg_dmx32_t dmx32; /*!< MCG_C4[DMX32]. */
626 mcg_oscsel_t oscsel; /*!< OSC select MCG_C7[OSCSEL]. */
627
628 /* ------------------------ MCG PLL settings ------------------------- */
629 mcg_pll_config_t pll0Config; /*!< MCGPLL0CLK configuration. */
630
631 } mcg_config_t;
632
633 /*******************************************************************************
634 * API
635 ******************************************************************************/
636
637 #if defined(__cplusplus)
638 extern "C" {
639 #endif /* __cplusplus */
640
641 /*!
642 * @brief Enable the clock for specific IP.
643 *
644 * @param name Which clock to enable, see \ref clock_ip_name_t.
645 */
CLOCK_EnableClock(clock_ip_name_t name)646 static inline void CLOCK_EnableClock(clock_ip_name_t name)
647 {
648 uint32_t regAddr = SIM_BASE + CLK_GATE_ABSTRACT_REG_OFFSET((uint32_t)name);
649 (*(volatile uint32_t *)regAddr) |= (1U << CLK_GATE_ABSTRACT_BITS_SHIFT((uint32_t)name));
650 }
651
652 /*!
653 * @brief Disable the clock for specific IP.
654 *
655 * @param name Which clock to disable, see \ref clock_ip_name_t.
656 */
CLOCK_DisableClock(clock_ip_name_t name)657 static inline void CLOCK_DisableClock(clock_ip_name_t name)
658 {
659 uint32_t regAddr = SIM_BASE + CLK_GATE_ABSTRACT_REG_OFFSET((uint32_t)name);
660 (*(volatile uint32_t *)regAddr) &= ~(1U << CLK_GATE_ABSTRACT_BITS_SHIFT((uint32_t)name));
661 }
662
663 /*!
664 * @brief Set SDHC0 clock source.
665 *
666 * @param src The value to set SDHC0 clock source.
667 */
CLOCK_SetSdhc0Clock(uint32_t src)668 static inline void CLOCK_SetSdhc0Clock(uint32_t src)
669 {
670 SIM->SOPT2 = ((SIM->SOPT2 & ~SIM_SOPT2_SDHCSRC_MASK) | SIM_SOPT2_SDHCSRC(src));
671 }
672
673 /*!
674 * @brief Set ERCLK32K source.
675 *
676 * @param src The value to set ERCLK32K clock source.
677 */
CLOCK_SetEr32kClock(uint32_t src)678 static inline void CLOCK_SetEr32kClock(uint32_t src)
679 {
680 SIM->SOPT1 = ((SIM->SOPT1 & ~SIM_SOPT1_OSC32KSEL_MASK) | SIM_SOPT1_OSC32KSEL(src));
681 }
682
683 /*!
684 * @brief Set debug trace clock source.
685 *
686 * @param src The value to set debug trace clock source.
687 */
CLOCK_SetTraceClock(uint32_t src)688 static inline void CLOCK_SetTraceClock(uint32_t src)
689 {
690 SIM->SOPT2 = ((SIM->SOPT2 & ~SIM_SOPT2_TRACECLKSEL_MASK) | SIM_SOPT2_TRACECLKSEL(src));
691 }
692
693 /*!
694 * @brief Set PLLFLLSEL clock source.
695 *
696 * @param src The value to set PLLFLLSEL clock source.
697 */
CLOCK_SetPllFllSelClock(uint32_t src)698 static inline void CLOCK_SetPllFllSelClock(uint32_t src)
699 {
700 SIM->SOPT2 = ((SIM->SOPT2 & ~SIM_SOPT2_PLLFLLSEL_MASK) | SIM_SOPT2_PLLFLLSEL(src));
701 }
702
703 /*!
704 * @brief Set CLKOUT source.
705 *
706 * @param src The value to set CLKOUT source.
707 */
CLOCK_SetClkOutClock(uint32_t src)708 static inline void CLOCK_SetClkOutClock(uint32_t src)
709 {
710 SIM->SOPT2 = ((SIM->SOPT2 & ~SIM_SOPT2_CLKOUTSEL_MASK) | SIM_SOPT2_CLKOUTSEL(src));
711 }
712
713 /*!
714 * @brief Set RTC_CLKOUT source.
715 *
716 * @param src The value to set RTC_CLKOUT source.
717 */
CLOCK_SetRtcClkOutClock(uint32_t src)718 static inline void CLOCK_SetRtcClkOutClock(uint32_t src)
719 {
720 SIM->SOPT2 = ((SIM->SOPT2 & ~SIM_SOPT2_RTCCLKOUTSEL_MASK) | SIM_SOPT2_RTCCLKOUTSEL(src));
721 }
722
723 /*! @brief Enable USB FS clock.
724 *
725 * @param src USB FS clock source.
726 * @param freq The frequency specified by src.
727 * @retval true The clock is set successfully.
728 * @retval false The clock source is invalid to get proper USB FS clock.
729 */
730 bool CLOCK_EnableUsbfs0Clock(clock_usb_src_t src, uint32_t freq);
731
732 /*! @brief Disable USB FS clock.
733 *
734 * Disable USB FS clock.
735 */
CLOCK_DisableUsbfs0Clock(void)736 static inline void CLOCK_DisableUsbfs0Clock(void)
737 {
738 CLOCK_DisableClock(kCLOCK_Usbfs0);
739 }
740
741 /*!
742 * @brief System clock divider
743 *
744 * Set the SIM_CLKDIV1[OUTDIV1], SIM_CLKDIV1[OUTDIV2], SIM_CLKDIV1[OUTDIV3], SIM_CLKDIV1[OUTDIV4].
745 *
746 * @param outdiv1 Clock 1 output divider value.
747 *
748 * @param outdiv2 Clock 2 output divider value.
749 *
750 * @param outdiv3 Clock 3 output divider value.
751 *
752 * @param outdiv4 Clock 4 output divider value.
753 */
CLOCK_SetOutDiv(uint32_t outdiv1,uint32_t outdiv2,uint32_t outdiv3,uint32_t outdiv4)754 static inline void CLOCK_SetOutDiv(uint32_t outdiv1, uint32_t outdiv2, uint32_t outdiv3, uint32_t outdiv4)
755 {
756 SIM->CLKDIV1 = SIM_CLKDIV1_OUTDIV1(outdiv1) | SIM_CLKDIV1_OUTDIV2(outdiv2) | SIM_CLKDIV1_OUTDIV3(outdiv3) |
757 SIM_CLKDIV1_OUTDIV4(outdiv4);
758 }
759
760 /*!
761 * @brief Gets the clock frequency for a specific clock name.
762 *
763 * This function checks the current clock configurations and then calculates
764 * the clock frequency for a specific clock name defined in clock_name_t.
765 * The MCG must be properly configured before using this function.
766 *
767 * @param clockName Clock names defined in clock_name_t
768 * @return Clock frequency value in Hertz
769 */
770 uint32_t CLOCK_GetFreq(clock_name_t clockName);
771
772 /*!
773 * @brief Get the core clock or system clock frequency.
774 *
775 * @return Clock frequency in Hz.
776 */
777 uint32_t CLOCK_GetCoreSysClkFreq(void);
778
779 /*!
780 * @brief Get the platform clock frequency.
781 *
782 * @return Clock frequency in Hz.
783 */
784 uint32_t CLOCK_GetPlatClkFreq(void);
785
786 /*!
787 * @brief Get the bus clock frequency.
788 *
789 * @return Clock frequency in Hz.
790 */
791 uint32_t CLOCK_GetBusClkFreq(void);
792
793 /*!
794 * @brief Get the flexbus clock frequency.
795 *
796 * @return Clock frequency in Hz.
797 */
798 uint32_t CLOCK_GetFlexBusClkFreq(void);
799
800 /*!
801 * @brief Get the flash clock frequency.
802 *
803 * @return Clock frequency in Hz.
804 */
805 uint32_t CLOCK_GetFlashClkFreq(void);
806
807 /*!
808 * @brief Get the output clock frequency selected by SIM[PLLFLLSEL].
809 *
810 * @return Clock frequency in Hz.
811 */
812 uint32_t CLOCK_GetPllFllSelClkFreq(void);
813
814 /*!
815 * @brief Get the external reference 32K clock frequency (ERCLK32K).
816 *
817 * @return Clock frequency in Hz.
818 */
819 uint32_t CLOCK_GetEr32kClkFreq(void);
820
821 /*!
822 * @brief Get the OSC0 external reference clock frequency (OSC0ERCLK).
823 *
824 * @return Clock frequency in Hz.
825 */
826 uint32_t CLOCK_GetOsc0ErClkFreq(void);
827
828 /*!
829 * @brief Set the clock configure in SIM module.
830 *
831 * This function sets system layer clock settings in SIM module.
832 *
833 * @param config Pointer to the configure structure.
834 */
835 void CLOCK_SetSimConfig(sim_clock_config_t const *config);
836
837 /*!
838 * @brief Set the system clock dividers in SIM to safe value.
839 *
840 * The system level clocks (core clock, bus clock, flexbus clock and flash clock)
841 * must be in allowed ranges. During MCG clock mode switch, the MCG output clock
842 * changes then the system level clocks may be out of range. This function could
843 * be used before MCG mode change, to make sure system level clocks are in allowed
844 * range.
845 *
846 * @param config Pointer to the configure structure.
847 */
CLOCK_SetSimSafeDivs(void)848 static inline void CLOCK_SetSimSafeDivs(void)
849 {
850 SIM->CLKDIV1 = 0x13070000U;
851 }
852
853 /*! @name MCG frequency functions. */
854 /*@{*/
855
856 /*!
857 * @brief Gets the MCG output clock (MCGOUTCLK) frequency.
858 *
859 * This function gets the MCG output clock frequency in Hz based on the current MCG
860 * register value.
861 *
862 * @return The frequency of MCGOUTCLK.
863 */
864 uint32_t CLOCK_GetOutClkFreq(void);
865
866 /*!
867 * @brief Gets the MCG FLL clock (MCGFLLCLK) frequency.
868 *
869 * This function gets the MCG FLL clock frequency in Hz based on the current MCG
870 * register value. The FLL is enabled in FEI/FBI/FEE/FBE mode and
871 * disabled in low power state in other modes.
872 *
873 * @return The frequency of MCGFLLCLK.
874 */
875 uint32_t CLOCK_GetFllFreq(void);
876
877 /*!
878 * @brief Gets the MCG internal reference clock (MCGIRCLK) frequency.
879 *
880 * This function gets the MCG internal reference clock frequency in Hz based
881 * on the current MCG register value.
882 *
883 * @return The frequency of MCGIRCLK.
884 */
885 uint32_t CLOCK_GetInternalRefClkFreq(void);
886
887 /*!
888 * @brief Gets the MCG fixed frequency clock (MCGFFCLK) frequency.
889 *
890 * This function gets the MCG fixed frequency clock frequency in Hz based
891 * on the current MCG register value.
892 *
893 * @return The frequency of MCGFFCLK.
894 */
895 uint32_t CLOCK_GetFixedFreqClkFreq(void);
896
897 /*!
898 * @brief Gets the MCG PLL0 clock (MCGPLL0CLK) frequency.
899 *
900 * This function gets the MCG PLL0 clock frequency in Hz based on the current MCG
901 * register value.
902 *
903 * @return The frequency of MCGPLL0CLK.
904 */
905 uint32_t CLOCK_GetPll0Freq(void);
906
907 /*@}*/
908
909 /*! @name MCG clock configuration. */
910 /*@{*/
911
912 /*!
913 * @brief Enables or disables the MCG low power.
914 *
915 * Enabling the MCG low power disables the PLL and FLL in bypass modes. In other words,
916 * in FBE and PBE modes, enabling low power sets the MCG to BLPE mode. In FBI and
917 * PBI modes, enabling low power sets the MCG to BLPI mode.
918 * When disabling the MCG low power, the PLL or FLL are enabled based on MCG settings.
919 *
920 * @param enable True to enable MCG low power, false to disable MCG low power.
921 */
CLOCK_SetLowPowerEnable(bool enable)922 static inline void CLOCK_SetLowPowerEnable(bool enable)
923 {
924 if (enable)
925 {
926 MCG->C2 |= MCG_C2_LP_MASK;
927 }
928 else
929 {
930 MCG->C2 &= ~(uint8_t)MCG_C2_LP_MASK;
931 }
932 }
933
934 /*!
935 * @brief Configures the Internal Reference clock (MCGIRCLK).
936 *
937 * This function sets the \c MCGIRCLK base on parameters. It also selects the IRC
938 * source. If the fast IRC is used, this function sets the fast IRC divider.
939 * This function also sets whether the \c MCGIRCLK is enabled in stop mode.
940 * Calling this function in FBI/PBI/BLPI modes may change the system clock. As a result,
941 * using the function in these modes it is not allowed.
942 *
943 * @param enableMode MCGIRCLK enable mode, OR'ed value of the enumeration _mcg_irclk_enable_mode.
944 * @param ircs MCGIRCLK clock source, choose fast or slow.
945 * @param fcrdiv Fast IRC divider setting (\c FCRDIV).
946 * @retval kStatus_MCG_SourceUsed Because the internal reference clock is used as a clock source,
947 * the configuration should not be changed. Otherwise, a glitch occurs.
948 * @retval kStatus_Success MCGIRCLK configuration finished successfully.
949 */
950 status_t CLOCK_SetInternalRefClkConfig(uint8_t enableMode, mcg_irc_mode_t ircs, uint8_t fcrdiv);
951
952 /*!
953 * @brief Selects the MCG external reference clock.
954 *
955 * Selects the MCG external reference clock source, changes the MCG_C7[OSCSEL],
956 * and waits for the clock source to be stable. Because the external reference
957 * clock should not be changed in FEE/FBE/BLPE/PBE/PEE modes, do not call this function in these modes.
958 *
959 * @param oscsel MCG external reference clock source, MCG_C7[OSCSEL].
960 * @retval kStatus_MCG_SourceUsed Because the external reference clock is used as a clock source,
961 * the configuration should not be changed. Otherwise, a glitch occurs.
962 * @retval kStatus_Success External reference clock set successfully.
963 */
964 status_t CLOCK_SetExternalRefClkConfig(mcg_oscsel_t oscsel);
965
966 /*!
967 * @brief Set the FLL external reference clock divider value.
968 *
969 * Sets the FLL external reference clock divider value, the register MCG_C1[FRDIV].
970 *
971 * @param frdiv The FLL external reference clock divider value, MCG_C1[FRDIV].
972 */
CLOCK_SetFllExtRefDiv(uint8_t frdiv)973 static inline void CLOCK_SetFllExtRefDiv(uint8_t frdiv)
974 {
975 MCG->C1 = (uint8_t)((MCG->C1 & ~MCG_C1_FRDIV_MASK) | MCG_C1_FRDIV(frdiv));
976 }
977
978 /*!
979 * @brief Enables the PLL0 in FLL mode.
980 *
981 * This function sets us the PLL0 in FLL mode and reconfigures
982 * the PLL0. Ensure that the PLL reference
983 * clock is enabled before calling this function and that the PLL0 is not used as a clock source.
984 * The function CLOCK_CalcPllDiv gets the correct PLL
985 * divider values.
986 *
987 * @param config Pointer to the configuration structure.
988 */
989 void CLOCK_EnablePll0(mcg_pll_config_t const *config);
990
991 /*!
992 * @brief Disables the PLL0 in FLL mode.
993 *
994 * This function disables the PLL0 in FLL mode. It should be used together with the
995 * @ref CLOCK_EnablePll0.
996 */
CLOCK_DisablePll0(void)997 static inline void CLOCK_DisablePll0(void)
998 {
999 MCG->C5 &= (uint8_t)(~(MCG_C5_PLLCLKEN0_MASK | MCG_C5_PLLSTEN0_MASK));
1000 }
1001
1002 /*!
1003 * @brief Calculates the PLL divider setting for a desired output frequency.
1004 *
1005 * This function calculates the correct reference clock divider (\c PRDIV) and
1006 * VCO divider (\c VDIV) to generate a desired PLL output frequency. It returns the
1007 * closest frequency match with the corresponding \c PRDIV/VDIV
1008 * returned from parameters. If a desired frequency is not valid, this function
1009 * returns 0.
1010 *
1011 * @param refFreq PLL reference clock frequency.
1012 * @param desireFreq Desired PLL output frequency.
1013 * @param prdiv PRDIV value to generate desired PLL frequency.
1014 * @param vdiv VDIV value to generate desired PLL frequency.
1015 * @return Closest frequency match that the PLL was able generate.
1016 */
1017 uint32_t CLOCK_CalcPllDiv(uint32_t refFreq, uint32_t desireFreq, uint8_t *prdiv, uint8_t *vdiv);
1018
1019 /*@}*/
1020
1021 /*! @name MCG clock lock monitor functions. */
1022 /*@{*/
1023
1024 /*!
1025 * @brief Sets the OSC0 clock monitor mode.
1026 *
1027 * This function sets the OSC0 clock monitor mode. See @ref mcg_monitor_mode_t for details.
1028 *
1029 * @param mode Monitor mode to set.
1030 */
1031 void CLOCK_SetOsc0MonitorMode(mcg_monitor_mode_t mode);
1032
1033 /*!
1034 * @brief Sets the RTC OSC clock monitor mode.
1035 *
1036 * This function sets the RTC OSC clock monitor mode. See @ref mcg_monitor_mode_t for details.
1037 *
1038 * @param mode Monitor mode to set.
1039 */
1040 void CLOCK_SetRtcOscMonitorMode(mcg_monitor_mode_t mode);
1041
1042 /*!
1043 * @brief Sets the PLL0 clock monitor mode.
1044 *
1045 * This function sets the PLL0 clock monitor mode. See @ref mcg_monitor_mode_t for details.
1046 *
1047 * @param mode Monitor mode to set.
1048 */
1049 void CLOCK_SetPll0MonitorMode(mcg_monitor_mode_t mode);
1050
1051 /*!
1052 * @brief Gets the MCG status flags.
1053 *
1054 * This function gets the MCG clock status flags. All status flags are
1055 * returned as a logical OR of the enumeration refer to _mcg_status_flags_t. To
1056 * check a specific flag, compare the return value with the flag.
1057 *
1058 * Example:
1059 * @code
1060 * To check the clock lost lock status of OSC0 and PLL0.
1061 * uint32_t mcgFlags;
1062 *
1063 * mcgFlags = CLOCK_GetStatusFlags();
1064 *
1065 * if (mcgFlags & kMCG_Osc0LostFlag)
1066 * {
1067 * OSC0 clock lock lost. Do something.
1068 * }
1069 * if (mcgFlags & kMCG_Pll0LostFlag)
1070 * {
1071 * PLL0 clock lock lost. Do something.
1072 * }
1073 * @endcode
1074 *
1075 * @return Logical OR value of the enumeration _mcg_status_flags_t.
1076 */
1077 uint32_t CLOCK_GetStatusFlags(void);
1078
1079 /*!
1080 * @brief Clears the MCG status flags.
1081 *
1082 * This function clears the MCG clock lock lost status. The parameter is a logical
1083 * OR value of the flags to clear. See the enumeration _mcg_status_flags_t.
1084 *
1085 * Example:
1086 * @code
1087 * To clear the clock lost lock status flags of OSC0 and PLL0.
1088 *
1089 * CLOCK_ClearStatusFlags(kMCG_Osc0LostFlag | kMCG_Pll0LostFlag);
1090 * @endcode
1091 *
1092 * @param mask The status flags to clear. This is a logical OR of members of the
1093 * enumeration _mcg_status_flags_t.
1094 */
1095 void CLOCK_ClearStatusFlags(uint32_t mask);
1096
1097 /*@}*/
1098
1099 /*!
1100 * @name OSC configuration
1101 * @{
1102 */
1103
1104 /*!
1105 * @brief Configures the OSC external reference clock (OSCERCLK).
1106 *
1107 * This function configures the OSC external reference clock (OSCERCLK).
1108 * This is an example to enable the OSCERCLK in normal and stop modes and also set
1109 * the output divider to 1:
1110 *
1111 @code
1112 oscer_config_t config =
1113 {
1114 .enableMode = kOSC_ErClkEnable | kOSC_ErClkEnableInStop,
1115 .erclkDiv = 1U,
1116 };
1117
1118 OSC_SetExtRefClkConfig(OSC, &config);
1119 @endcode
1120 *
1121 * @param base OSC peripheral address.
1122 * @param config Pointer to the configuration structure.
1123 */
OSC_SetExtRefClkConfig(OSC_Type * base,oscer_config_t const * config)1124 static inline void OSC_SetExtRefClkConfig(OSC_Type *base, oscer_config_t const *config)
1125 {
1126 uint8_t reg = base->CR;
1127
1128 reg &= (uint8_t)(~(OSC_CR_ERCLKEN_MASK | OSC_CR_EREFSTEN_MASK));
1129 reg |= config->enableMode;
1130
1131 base->CR = reg;
1132 }
1133
1134 /*!
1135 * @brief Sets the capacitor load configuration for the oscillator.
1136 *
1137 * This function sets the specified capacitors configuration for the oscillator.
1138 * This should be done in the early system level initialization function call
1139 * based on the system configuration.
1140 *
1141 * @param base OSC peripheral address.
1142 * @param capLoad OR'ed value for the capacitor load option, see \ref _osc_cap_load.
1143 *
1144 * Example:
1145 @code
1146 To enable only 2 pF and 8 pF capacitor load, please use like this.
1147 OSC_SetCapLoad(OSC, kOSC_Cap2P | kOSC_Cap8P);
1148 @endcode
1149 */
OSC_SetCapLoad(OSC_Type * base,uint8_t capLoad)1150 static inline void OSC_SetCapLoad(OSC_Type *base, uint8_t capLoad)
1151 {
1152 uint8_t reg = base->CR;
1153
1154 reg &= (uint8_t)(~(OSC_CR_SC2P_MASK | OSC_CR_SC4P_MASK | OSC_CR_SC8P_MASK | OSC_CR_SC16P_MASK));
1155 reg |= capLoad;
1156
1157 base->CR = reg;
1158 }
1159
1160 /*!
1161 * @brief Initializes the OSC0.
1162 *
1163 * This function initializes the OSC0 according to the board configuration.
1164 *
1165 * @param config Pointer to the OSC0 configuration structure.
1166 */
1167 void CLOCK_InitOsc0(osc_config_t const *config);
1168
1169 /*!
1170 * @brief Deinitializes the OSC0.
1171 *
1172 * This function deinitializes the OSC0.
1173 */
1174 void CLOCK_DeinitOsc0(void);
1175
1176 /* @} */
1177
1178 /*!
1179 * @name External clock frequency
1180 * @{
1181 */
1182
1183 /*!
1184 * @brief Sets the XTAL0 frequency based on board settings.
1185 *
1186 * @param freq The XTAL0/EXTAL0 input clock frequency in Hz.
1187 */
CLOCK_SetXtal0Freq(uint32_t freq)1188 static inline void CLOCK_SetXtal0Freq(uint32_t freq)
1189 {
1190 g_xtal0Freq = freq;
1191 }
1192
1193 /*!
1194 * @brief Sets the XTAL32/RTC_CLKIN frequency based on board settings.
1195 *
1196 * @param freq The XTAL32/EXTAL32/RTC_CLKIN input clock frequency in Hz.
1197 */
CLOCK_SetXtal32Freq(uint32_t freq)1198 static inline void CLOCK_SetXtal32Freq(uint32_t freq)
1199 {
1200 g_xtal32Freq = freq;
1201 }
1202 /* @} */
1203
1204 /*!
1205 * @name IRCs frequency
1206 * @{
1207 */
1208
1209 /*!
1210 * @brief Set the Slow IRC frequency based on the trimmed value
1211 *
1212 * @param freq The Slow IRC frequency input clock frequency in Hz.
1213 */
1214 void CLOCK_SetSlowIrcFreq(uint32_t freq);
1215
1216 /*!
1217 * @brief Set the Fast IRC frequency based on the trimmed value
1218 *
1219 * @param freq The Fast IRC frequency input clock frequency in Hz.
1220 */
1221 void CLOCK_SetFastIrcFreq(uint32_t freq);
1222 /* @} */
1223
1224 /*!
1225 * @name MCG auto-trim machine.
1226 * @{
1227 */
1228
1229 /*!
1230 * @brief Auto trims the internal reference clock.
1231 *
1232 * This function trims the internal reference clock by using the external clock. If
1233 * successful, it returns the kStatus_Success and the frequency after
1234 * trimming is received in the parameter @p actualFreq. If an error occurs,
1235 * the error code is returned.
1236 *
1237 * @param extFreq External clock frequency, which should be a bus clock.
1238 * @param desireFreq Frequency to trim to.
1239 * @param actualFreq Actual frequency after trimming.
1240 * @param atms Trim fast or slow internal reference clock.
1241 * @retval kStatus_Success ATM success.
1242 * @retval kStatus_MCG_AtmBusClockInvalid The bus clock is not in allowed range for the ATM.
1243 * @retval kStatus_MCG_AtmDesiredFreqInvalid MCGIRCLK could not be trimmed to the desired frequency.
1244 * @retval kStatus_MCG_AtmIrcUsed Could not trim because MCGIRCLK is used as a bus clock source.
1245 * @retval kStatus_MCG_AtmHardwareFail Hardware fails while trimming.
1246 */
1247 status_t CLOCK_TrimInternalRefClk(uint32_t extFreq, uint32_t desireFreq, uint32_t *actualFreq, mcg_atm_select_t atms);
1248 /* @} */
1249
1250 /*! @name MCG mode functions. */
1251 /*@{*/
1252
1253 /*!
1254 * @brief Gets the current MCG mode.
1255 *
1256 * This function checks the MCG registers and determines the current MCG mode.
1257 *
1258 * @return Current MCG mode or error code; See @ref mcg_mode_t.
1259 */
1260 mcg_mode_t CLOCK_GetMode(void);
1261
1262 /*!
1263 * @brief Sets the MCG to FEI mode.
1264 *
1265 * This function sets the MCG to FEI mode. If setting to FEI mode fails
1266 * from the current mode, this function returns an error.
1267 *
1268 * @param dmx32 DMX32 in FEI mode.
1269 * @param drs The DCO range selection.
1270 * @param fllStableDelay Delay function to ensure that the FLL is stable. Passing
1271 * NULL does not cause a delay.
1272 * @retval kStatus_MCG_ModeUnreachable Could not switch to the target mode.
1273 * @retval kStatus_Success Switched to the target mode successfully.
1274 * @note If @p dmx32 is set to kMCG_Dmx32Fine, the slow IRC must not be trimmed
1275 * to a frequency above 32768 Hz.
1276 */
1277 status_t CLOCK_SetFeiMode(mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDelay)(void));
1278
1279 /*!
1280 * @brief Sets the MCG to FEE mode.
1281 *
1282 * This function sets the MCG to FEE mode. If setting to FEE mode fails
1283 * from the current mode, this function returns an error.
1284 *
1285 * @param frdiv FLL reference clock divider setting, FRDIV.
1286 * @param dmx32 DMX32 in FEE mode.
1287 * @param drs The DCO range selection.
1288 * @param fllStableDelay Delay function to make sure FLL is stable. Passing
1289 * NULL does not cause a delay.
1290 *
1291 * @retval kStatus_MCG_ModeUnreachable Could not switch to the target mode.
1292 * @retval kStatus_Success Switched to the target mode successfully.
1293 */
1294 status_t CLOCK_SetFeeMode(uint8_t frdiv, mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDelay)(void));
1295
1296 /*!
1297 * @brief Sets the MCG to FBI mode.
1298 *
1299 * This function sets the MCG to FBI mode. If setting to FBI mode fails
1300 * from the current mode, this function returns an error.
1301 *
1302 * @param dmx32 DMX32 in FBI mode.
1303 * @param drs The DCO range selection.
1304 * @param fllStableDelay Delay function to make sure FLL is stable. If the FLL
1305 * is not used in FBI mode, this parameter can be NULL. Passing
1306 * NULL does not cause a delay.
1307 * @retval kStatus_MCG_ModeUnreachable Could not switch to the target mode.
1308 * @retval kStatus_Success Switched to the target mode successfully.
1309 * @note If @p dmx32 is set to kMCG_Dmx32Fine, the slow IRC must not be trimmed
1310 * to frequency above 32768 Hz.
1311 */
1312 status_t CLOCK_SetFbiMode(mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDelay)(void));
1313
1314 /*!
1315 * @brief Sets the MCG to FBE mode.
1316 *
1317 * This function sets the MCG to FBE mode. If setting to FBE mode fails
1318 * from the current mode, this function returns an error.
1319 *
1320 * @param frdiv FLL reference clock divider setting, FRDIV.
1321 * @param dmx32 DMX32 in FBE mode.
1322 * @param drs The DCO range selection.
1323 * @param fllStableDelay Delay function to make sure FLL is stable. If the FLL
1324 * is not used in FBE mode, this parameter can be NULL. Passing NULL
1325 * does not cause a delay.
1326 * @retval kStatus_MCG_ModeUnreachable Could not switch to the target mode.
1327 * @retval kStatus_Success Switched to the target mode successfully.
1328 */
1329 status_t CLOCK_SetFbeMode(uint8_t frdiv, mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDelay)(void));
1330
1331 /*!
1332 * @brief Sets the MCG to BLPI mode.
1333 *
1334 * This function sets the MCG to BLPI mode. If setting to BLPI mode fails
1335 * from the current mode, this function returns an error.
1336 *
1337 * @retval kStatus_MCG_ModeUnreachable Could not switch to the target mode.
1338 * @retval kStatus_Success Switched to the target mode successfully.
1339 */
1340 status_t CLOCK_SetBlpiMode(void);
1341
1342 /*!
1343 * @brief Sets the MCG to BLPE mode.
1344 *
1345 * This function sets the MCG to BLPE mode. If setting to BLPE mode fails
1346 * from the current mode, this function returns an error.
1347 *
1348 * @retval kStatus_MCG_ModeUnreachable Could not switch to the target mode.
1349 * @retval kStatus_Success Switched to the target mode successfully.
1350 */
1351 status_t CLOCK_SetBlpeMode(void);
1352
1353 /*!
1354 * @brief Sets the MCG to PBE mode.
1355 *
1356 * This function sets the MCG to PBE mode. If setting to PBE mode fails
1357 * from the current mode, this function returns an error.
1358 *
1359 * @param pllcs The PLL selection, PLLCS.
1360 * @param config Pointer to the PLL configuration.
1361 * @retval kStatus_MCG_ModeUnreachable Could not switch to the target mode.
1362 * @retval kStatus_Success Switched to the target mode successfully.
1363 *
1364 * @note
1365 * 1. The parameter \c pllcs selects the PLL. For platforms with
1366 * only one PLL, the parameter pllcs is kept for interface compatibility.
1367 * 2. The parameter \c config is the PLL configuration structure. On some
1368 * platforms, it is possible to choose the external PLL directly, which renders the
1369 * configuration structure not necessary. In this case, pass in NULL.
1370 * For example: CLOCK_SetPbeMode(kMCG_OscselOsc, kMCG_PllClkSelExtPll, NULL);
1371 */
1372 status_t CLOCK_SetPbeMode(mcg_pll_clk_select_t pllcs, mcg_pll_config_t const *config);
1373
1374 /*!
1375 * @brief Sets the MCG to PEE mode.
1376 *
1377 * This function sets the MCG to PEE mode.
1378 *
1379 * @retval kStatus_MCG_ModeUnreachable Could not switch to the target mode.
1380 * @retval kStatus_Success Switched to the target mode successfully.
1381 *
1382 * @note This function only changes the CLKS to use the PLL/FLL output. If the
1383 * PRDIV/VDIV are different than in the PBE mode, set them up
1384 * in PBE mode and wait. When the clock is stable, switch to PEE mode.
1385 */
1386 status_t CLOCK_SetPeeMode(void);
1387
1388 /*!
1389 * @brief Switches the MCG to FBE mode from the external mode.
1390 *
1391 * This function switches the MCG from external modes (PEE/PBE/BLPE/FEE) to the FBE mode quickly.
1392 * The external clock is used as the system clock source and PLL is disabled. However,
1393 * the FLL settings are not configured. This is a lite function with a small code size, which is useful
1394 * during the mode switch. For example, to switch from PEE mode to FEI mode:
1395 *
1396 * @code
1397 * CLOCK_ExternalModeToFbeModeQuick();
1398 * CLOCK_SetFeiMode(...);
1399 * @endcode
1400 *
1401 * @retval kStatus_Success Switched successfully.
1402 * @retval kStatus_MCG_ModeInvalid If the current mode is not an external mode, do not call this function.
1403 */
1404 status_t CLOCK_ExternalModeToFbeModeQuick(void);
1405
1406 /*!
1407 * @brief Switches the MCG to FBI mode from internal modes.
1408 *
1409 * This function switches the MCG from internal modes (PEI/PBI/BLPI/FEI) to the FBI mode quickly.
1410 * The MCGIRCLK is used as the system clock source and PLL is disabled. However,
1411 * FLL settings are not configured. This is a lite function with a small code size, which is useful
1412 * during the mode switch. For example, to switch from PEI mode to FEE mode:
1413 *
1414 * @code
1415 * CLOCK_InternalModeToFbiModeQuick();
1416 * CLOCK_SetFeeMode(...);
1417 * @endcode
1418 *
1419 * @retval kStatus_Success Switched successfully.
1420 * @retval kStatus_MCG_ModeInvalid If the current mode is not an internal mode, do not call this function.
1421 */
1422 status_t CLOCK_InternalModeToFbiModeQuick(void);
1423
1424 /*!
1425 * @brief Sets the MCG to FEI mode during system boot up.
1426 *
1427 * This function sets the MCG to FEI mode from the reset mode. It can also be used to
1428 * set up MCG during system boot up.
1429 *
1430 * @param dmx32 DMX32 in FEI mode.
1431 * @param drs The DCO range selection.
1432 * @param fllStableDelay Delay function to ensure that the FLL is stable.
1433 *
1434 * @retval kStatus_MCG_ModeUnreachable Could not switch to the target mode.
1435 * @retval kStatus_Success Switched to the target mode successfully.
1436 * @note If @p dmx32 is set to kMCG_Dmx32Fine, the slow IRC must not be trimmed
1437 * to frequency above 32768 Hz.
1438 */
1439 status_t CLOCK_BootToFeiMode(mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDelay)(void));
1440
1441 /*!
1442 * @brief Sets the MCG to FEE mode during system bootup.
1443 *
1444 * This function sets MCG to FEE mode from the reset mode. It can also be used to
1445 * set up the MCG during system boot up.
1446 *
1447 * @param oscsel OSC clock select, OSCSEL.
1448 * @param frdiv FLL reference clock divider setting, FRDIV.
1449 * @param dmx32 DMX32 in FEE mode.
1450 * @param drs The DCO range selection.
1451 * @param fllStableDelay Delay function to ensure that the FLL is stable.
1452 *
1453 * @retval kStatus_MCG_ModeUnreachable Could not switch to the target mode.
1454 * @retval kStatus_Success Switched to the target mode successfully.
1455 */
1456 status_t CLOCK_BootToFeeMode(
1457 mcg_oscsel_t oscsel, uint8_t frdiv, mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDelay)(void));
1458
1459 /*!
1460 * @brief Sets the MCG to BLPI mode during system boot up.
1461 *
1462 * This function sets the MCG to BLPI mode from the reset mode. It can also be used to
1463 * set up the MCG during system boot up.
1464 *
1465 * @param fcrdiv Fast IRC divider, FCRDIV.
1466 * @param ircs The internal reference clock to select, IRCS.
1467 * @param ircEnableMode The MCGIRCLK enable mode, OR'ed value of the enumeration _mcg_irclk_enable_mode.
1468 *
1469 * @retval kStatus_MCG_SourceUsed Could not change MCGIRCLK setting.
1470 * @retval kStatus_Success Switched to the target mode successfully.
1471 */
1472 status_t CLOCK_BootToBlpiMode(uint8_t fcrdiv, mcg_irc_mode_t ircs, uint8_t ircEnableMode);
1473
1474 /*!
1475 * @brief Sets the MCG to BLPE mode during system boot up.
1476 *
1477 * This function sets the MCG to BLPE mode from the reset mode. It can also be used to
1478 * set up the MCG during system boot up.
1479 *
1480 * @param oscsel OSC clock select, MCG_C7[OSCSEL].
1481 *
1482 * @retval kStatus_MCG_ModeUnreachable Could not switch to the target mode.
1483 * @retval kStatus_Success Switched to the target mode successfully.
1484 */
1485 status_t CLOCK_BootToBlpeMode(mcg_oscsel_t oscsel);
1486
1487 /*!
1488 * @brief Sets the MCG to PEE mode during system boot up.
1489 *
1490 * This function sets the MCG to PEE mode from reset mode. It can also be used to
1491 * set up the MCG during system boot up.
1492 *
1493 * @param oscsel OSC clock select, MCG_C7[OSCSEL].
1494 * @param pllcs The PLL selection, PLLCS.
1495 * @param config Pointer to the PLL configuration.
1496 *
1497 * @retval kStatus_MCG_ModeUnreachable Could not switch to the target mode.
1498 * @retval kStatus_Success Switched to the target mode successfully.
1499 */
1500 status_t CLOCK_BootToPeeMode(mcg_oscsel_t oscsel, mcg_pll_clk_select_t pllcs, mcg_pll_config_t const *config);
1501
1502 /*!
1503 * @brief Sets the MCG to a target mode.
1504 *
1505 * This function sets MCG to a target mode defined by the configuration
1506 * structure. If switching to the target mode fails, this function
1507 * chooses the correct path.
1508 *
1509 * @param config Pointer to the target MCG mode configuration structure.
1510 * @return Return kStatus_Success if switched successfully; Otherwise, it returns an error code _mcg_status.
1511 *
1512 * @note If the external clock is used in the target mode, ensure that it is
1513 * enabled. For example, if the OSC0 is used, set up OSC0 correctly before calling this
1514 * function.
1515 */
1516 status_t CLOCK_SetMcgConfig(mcg_config_t const *config);
1517
1518 /*@}*/
1519
1520 #if defined(__cplusplus)
1521 }
1522 #endif /* __cplusplus */
1523
1524 /*! @} */
1525
1526 #endif /* _FSL_CLOCK_H_ */
1527
