1 /*
2 * Copyright (c) 2015, Freescale Semiconductor, Inc.
3 * Copyright 2016 - 2019, NXP
4 * All rights reserved.
5 *
6 * SPDX-License-Identifier: BSD-3-Clause
7 */
8
9 #ifndef _FSL_CLOCK_H_
10 #define _FSL_CLOCK_H_
11
12 #include "fsl_common.h"
13
14 /*! @addtogroup clock */
15 /*! @{ */
16
17 /*! @file */
18
19 /*******************************************************************************
20 * Configurations
21 ******************************************************************************/
22
23 /*! @brief Configures whether to check a parameter in a function.
24 *
25 * Some MCG settings must be changed with conditions, for example:
26 * 1. MCGIRCLK settings, such as the source, divider, and the trim value should not change when
27 * MCGIRCLK is used as a system clock source.
28 * 2. MCG_C7[OSCSEL] should not be changed when the external reference clock is used
29 * as a system clock source. For example, in FBE/BLPE/PBE modes.
30 * 3. The users should only switch between the supported clock modes.
31 *
32 * MCG functions check the parameter and MCG status before setting, if not allowed
33 * to change, the functions return error. The parameter checking increases code size,
34 * if code size is a critical requirement, change #MCG_CONFIG_CHECK_PARAM to 0 to
35 * disable parameter checking.
36 */
37 #ifndef MCG_CONFIG_CHECK_PARAM
38 #define MCG_CONFIG_CHECK_PARAM 0U
39 #endif
40
41 /*! @brief Configure whether driver controls clock
42 *
43 * When set to 0, peripheral drivers will enable clock in initialize function
44 * and disable clock in de-initialize function. When set to 1, peripheral
45 * driver will not control the clock, application could control the clock out of
46 * the driver.
47 *
48 * @note All drivers share this feature switcher. If it is set to 1, application
49 * should handle clock enable and disable for all drivers.
50 */
51 #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL))
52 #define FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL 0
53 #endif
54
55 /*******************************************************************************
56 * Definitions
57 ******************************************************************************/
58
59 /*! @name Driver version */
60 /*@{*/
61 /*! @brief CLOCK driver version 2.5.1. */
62 #define FSL_CLOCK_DRIVER_VERSION (MAKE_VERSION(2, 5, 1))
63 /*@}*/
64
65 /*! @brief External XTAL0 (OSC0) clock frequency.
66 *
67 * The XTAL0/EXTAL0 (OSC0) clock frequency in Hz. When the clock is set up, use the
68 * function CLOCK_SetXtal0Freq to set the value in the clock driver. For example,
69 * if XTAL0 is 8 MHz:
70 * @code
71 * Set up the OSC0
72 * CLOCK_InitOsc0(...);
73 * Set the XTAL0 value to the clock driver.
74 * CLOCK_SetXtal0Freq(80000000);
75 * @endcode
76 *
77 * This is important for the multicore platforms where only one core needs to set up the
78 * OSC0 using the CLOCK_InitOsc0. All other cores need to call the CLOCK_SetXtal0Freq
79 * to get a valid clock frequency.
80 */
81 extern volatile uint32_t g_xtal0Freq;
82
83 /*! @brief External XTAL32/EXTAL32/RTC_CLKIN clock frequency.
84 *
85 * The XTAL32/EXTAL32/RTC_CLKIN clock frequency in Hz. When the clock is set up, use the
86 * function CLOCK_SetXtal32Freq to set the value in the clock driver.
87 *
88 * This is important for the multicore platforms where only one core needs to set up
89 * the clock. All other cores need to call the CLOCK_SetXtal32Freq
90 * to get a valid clock frequency.
91 */
92 extern volatile uint32_t g_xtal32Freq;
93
94 /*! @brief IRC48M clock frequency in Hz. */
95 #define MCG_INTERNAL_IRC_48M 48000000U
96
97 #if (defined(OSC) && !(defined(OSC0)))
98 #define OSC0 OSC
99 #endif
100
101 /* Definition for delay API in clock driver, users can redefine it to the real application. */
102 #ifndef SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY
103 #define SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY (120000000UL)
104 #endif
105 /*! @brief Clock ip name array for DMAMUX. */
106 #define DMAMUX_CLOCKS \
107 { \
108 kCLOCK_Dmamux0 \
109 }
110
111 /*! @brief Clock ip name array for PORT. */
112 #define PORT_CLOCKS \
113 { \
114 kCLOCK_PortA, kCLOCK_PortB, kCLOCK_PortC, kCLOCK_PortD, kCLOCK_PortE \
115 }
116
117 /*! @brief Clock ip name array for EWM. */
118 #define EWM_CLOCKS \
119 { \
120 kCLOCK_Ewm0 \
121 }
122
123 /*! @brief Clock ip name array for PIT. */
124 #define PIT_CLOCKS \
125 { \
126 kCLOCK_Pit0 \
127 }
128
129 /*! @brief Clock ip name array for DSPI. */
130 #define DSPI_CLOCKS \
131 { \
132 kCLOCK_Spi0, kCLOCK_Spi1 \
133 }
134
135 /*! @brief Clock ip name array for LPTMR. */
136 #define LPTMR_CLOCKS \
137 { \
138 kCLOCK_Lptmr0 \
139 }
140
141 /*! @brief Clock ip name array for FTM. */
142 #define FTM_CLOCKS \
143 { \
144 kCLOCK_Ftm0, kCLOCK_Ftm1, kCLOCK_Ftm2 \
145 }
146
147 /*! @brief Clock ip name array for EDMA. */
148 #define EDMA_CLOCKS \
149 { \
150 kCLOCK_Dma0 \
151 }
152
153 /*! @brief Clock ip name array for LPUART. */
154 #define LPUART_CLOCKS \
155 { \
156 kCLOCK_Lpuart0 \
157 }
158
159 /*! @brief Clock ip name array for DAC. */
160 #define DAC_CLOCKS \
161 { \
162 kCLOCK_Dac0 \
163 }
164
165 /*! @brief Clock ip name array for ADC16. */
166 #define ADC16_CLOCKS \
167 { \
168 kCLOCK_Adc0, kCLOCK_Adc1 \
169 }
170
171 /*! @brief Clock ip name array for VREF. */
172 #define VREF_CLOCKS \
173 { \
174 kCLOCK_Vref0 \
175 }
176
177 /*! @brief Clock ip name array for UART. */
178 #define UART_CLOCKS \
179 { \
180 kCLOCK_Uart0, kCLOCK_Uart1, kCLOCK_Uart2 \
181 }
182
183 /*! @brief Clock ip name array for RNGA. */
184 #define RNGA_CLOCKS \
185 { \
186 kCLOCK_Rnga0 \
187 }
188
189 /*! @brief Clock ip name array for CRC. */
190 #define CRC_CLOCKS \
191 { \
192 kCLOCK_Crc0 \
193 }
194
195 /*! @brief Clock ip name array for I2C. */
196 #define I2C_CLOCKS \
197 { \
198 kCLOCK_I2c0, kCLOCK_I2c1 \
199 }
200
201 /*! @brief Clock ip name array for PDB. */
202 #define PDB_CLOCKS \
203 { \
204 kCLOCK_Pdb0 \
205 }
206
207 /*! @brief Clock ip name array for CMP. */
208 #define CMP_CLOCKS \
209 { \
210 kCLOCK_Cmp0, kCLOCK_Cmp1 \
211 }
212
213 /*! @brief Clock ip name array for FTF. */
214 #define FTF_CLOCKS \
215 { \
216 kCLOCK_Ftf0 \
217 }
218
219 /*!
220 * @brief LPO clock frequency.
221 */
222 #define LPO_CLK_FREQ 1000U
223
224 /*! @brief Peripherals clock source definition. */
225 #define SYS_CLK kCLOCK_CoreSysClk
226 #define BUS_CLK kCLOCK_BusClk
227 #define FAST_CLK kCLOCK_FastPeriphClk
228
229 #define I2C0_CLK_SRC BUS_CLK
230 #define I2C1_CLK_SRC BUS_CLK
231 #define DSPI0_CLK_SRC BUS_CLK
232 #define DSPI1_CLK_SRC BUS_CLK
233 #define UART0_CLK_SRC SYS_CLK
234 #define UART1_CLK_SRC SYS_CLK
235 #define UART2_CLK_SRC BUS_CLK
236
237 /*! @brief Clock name used to get clock frequency. */
238 typedef enum _clock_name
239 {
240 /* ----------------------------- System layer clock -------------------------------*/
241 kCLOCK_CoreSysClk, /*!< Core/system clock */
242 kCLOCK_PlatClk, /*!< Platform clock */
243 kCLOCK_BusClk, /*!< Bus clock */
244 kCLOCK_FlashClk, /*!< Flash clock */
245 kCLOCK_FastPeriphClk, /*!< Fast peripheral clock */
246 kCLOCK_PllFllSelClk, /*!< The clock after SIM[PLLFLLSEL]. */
247
248 /* ---------------------------------- OSC clock -----------------------------------*/
249 kCLOCK_Er32kClk, /*!< External reference 32K clock (ERCLK32K) */
250 kCLOCK_Osc0ErClk, /*!< OSC0 external reference clock (OSC0ERCLK) */
251 kCLOCK_Osc1ErClk, /*!< OSC1 external reference clock (OSC1ERCLK) */
252 kCLOCK_Osc0ErClkUndiv, /*!< OSC0 external reference undivided clock(OSC0ERCLK_UNDIV). */
253
254 /* ----------------------------- MCG and MCG-Lite clock ---------------------------*/
255 kCLOCK_McgFixedFreqClk, /*!< MCG fixed frequency clock (MCGFFCLK) */
256 kCLOCK_McgInternalRefClk, /*!< MCG internal reference clock (MCGIRCLK) */
257 kCLOCK_McgFllClk, /*!< MCGFLLCLK */
258 kCLOCK_McgPll0Clk, /*!< MCGPLL0CLK */
259 kCLOCK_McgPll1Clk, /*!< MCGPLL1CLK */
260 kCLOCK_McgExtPllClk, /*!< EXT_PLLCLK */
261 kCLOCK_McgPeriphClk, /*!< MCG peripheral clock (MCGPCLK) */
262 kCLOCK_McgIrc48MClk, /*!< MCG IRC48M clock */
263
264 /* --------------------------------- Other clock ----------------------------------*/
265 kCLOCK_LpoClk, /*!< LPO clock */
266
267 } clock_name_t;
268
269 /*------------------------------------------------------------------------------
270
271 clock_gate_t definition:
272
273 31 16 0
274 -----------------------------------------------------------------
275 | SIM_SCGC register offset | control bit offset in SCGC |
276 -----------------------------------------------------------------
277
278 For example, the SDHC clock gate is controlled by SIM_SCGC3[17], the
279 SIM_SCGC3 offset in SIM is 0x1030, then kCLOCK_GateSdhc0 is defined as
280
281 kCLOCK_GateSdhc0 = (0x1030 << 16) | 17;
282
283 ------------------------------------------------------------------------------*/
284
285 #define CLK_GATE_REG_OFFSET_SHIFT 16U
286 #define CLK_GATE_REG_OFFSET_MASK 0xFFFF0000U
287 #define CLK_GATE_BIT_SHIFT_SHIFT 0U
288 #define CLK_GATE_BIT_SHIFT_MASK 0x0000FFFFU
289
290 #define CLK_GATE_DEFINE(reg_offset, bit_shift) \
291 ((((reg_offset) << CLK_GATE_REG_OFFSET_SHIFT) & CLK_GATE_REG_OFFSET_MASK) | \
292 (((bit_shift) << CLK_GATE_BIT_SHIFT_SHIFT) & CLK_GATE_BIT_SHIFT_MASK))
293
294 #define CLK_GATE_ABSTRACT_REG_OFFSET(x) (((x)&CLK_GATE_REG_OFFSET_MASK) >> CLK_GATE_REG_OFFSET_SHIFT)
295 #define CLK_GATE_ABSTRACT_BITS_SHIFT(x) (((x)&CLK_GATE_BIT_SHIFT_MASK) >> CLK_GATE_BIT_SHIFT_SHIFT)
296
297 /*! @brief Clock gate name used for CLOCK_EnableClock/CLOCK_DisableClock. */
298 typedef enum _clock_ip_name
299 {
300 kCLOCK_IpInvalid = 0U,
301
302 kCLOCK_Ewm0 = CLK_GATE_DEFINE(0x1034U, 1U),
303 kCLOCK_I2c0 = CLK_GATE_DEFINE(0x1034U, 6U),
304 kCLOCK_I2c1 = CLK_GATE_DEFINE(0x1034U, 7U),
305 kCLOCK_Uart0 = CLK_GATE_DEFINE(0x1034U, 10U),
306 kCLOCK_Uart1 = CLK_GATE_DEFINE(0x1034U, 11U),
307 kCLOCK_Uart2 = CLK_GATE_DEFINE(0x1034U, 12U),
308 kCLOCK_Cmp0 = CLK_GATE_DEFINE(0x1034U, 19U),
309 kCLOCK_Cmp1 = CLK_GATE_DEFINE(0x1034U, 19U),
310 kCLOCK_Vref0 = CLK_GATE_DEFINE(0x1034U, 20U),
311
312 kCLOCK_Lptmr0 = CLK_GATE_DEFINE(0x1038U, 0U),
313 kCLOCK_PortA = CLK_GATE_DEFINE(0x1038U, 9U),
314 kCLOCK_PortB = CLK_GATE_DEFINE(0x1038U, 10U),
315 kCLOCK_PortC = CLK_GATE_DEFINE(0x1038U, 11U),
316 kCLOCK_PortD = CLK_GATE_DEFINE(0x1038U, 12U),
317 kCLOCK_PortE = CLK_GATE_DEFINE(0x1038U, 13U),
318
319 kCLOCK_Ftf0 = CLK_GATE_DEFINE(0x103CU, 0U),
320 kCLOCK_Dmamux0 = CLK_GATE_DEFINE(0x103CU, 1U),
321 kCLOCK_Adc1 = CLK_GATE_DEFINE(0x103CU, 7U),
322 kCLOCK_Rnga0 = CLK_GATE_DEFINE(0x103CU, 9U),
323 kCLOCK_Lpuart0 = CLK_GATE_DEFINE(0x103CU, 10U),
324 kCLOCK_Spi0 = CLK_GATE_DEFINE(0x103CU, 12U),
325 kCLOCK_Spi1 = CLK_GATE_DEFINE(0x103CU, 13U),
326 kCLOCK_Crc0 = CLK_GATE_DEFINE(0x103CU, 18U),
327 kCLOCK_Pdb0 = CLK_GATE_DEFINE(0x103CU, 22U),
328 kCLOCK_Pit0 = CLK_GATE_DEFINE(0x103CU, 23U),
329 kCLOCK_Ftm0 = CLK_GATE_DEFINE(0x103CU, 24U),
330 kCLOCK_Ftm1 = CLK_GATE_DEFINE(0x103CU, 25U),
331 kCLOCK_Ftm2 = CLK_GATE_DEFINE(0x103CU, 26U),
332 kCLOCK_Adc0 = CLK_GATE_DEFINE(0x103CU, 27U),
333 kCLOCK_Dac0 = CLK_GATE_DEFINE(0x103CU, 31U),
334
335 kCLOCK_Dma0 = CLK_GATE_DEFINE(0x1040U, 1U),
336 } clock_ip_name_t;
337
338 /*!@brief SIM configuration structure for clock setting. */
339 typedef struct _sim_clock_config
340 {
341 uint8_t pllFllSel; /*!< PLL/FLL/IRC48M selection. */
342 uint8_t er32kSrc; /*!< ERCLK32K source selection. */
343 uint32_t clkdiv1; /*!< SIM_CLKDIV1. */
344 } sim_clock_config_t;
345
346 /*! @brief OSC work mode. */
347 typedef enum _osc_mode
348 {
349 kOSC_ModeExt = 0U, /*!< Use an external clock. */
350 #if (defined(MCG_C2_EREFS_MASK) && !(defined(MCG_C2_EREFS0_MASK)))
351 kOSC_ModeOscLowPower = MCG_C2_EREFS_MASK, /*!< Oscillator low power. */
352 #else
353 kOSC_ModeOscLowPower = MCG_C2_EREFS0_MASK, /*!< Oscillator low power. */
354 #endif
355 kOSC_ModeOscHighGain = 0U
356 #if (defined(MCG_C2_EREFS_MASK) && !(defined(MCG_C2_EREFS0_MASK)))
357 | MCG_C2_EREFS_MASK
358 #else
359 | MCG_C2_EREFS0_MASK
360 #endif
361 #if (defined(MCG_C2_HGO_MASK) && !(defined(MCG_C2_HGO0_MASK)))
362 | MCG_C2_HGO_MASK, /*!< Oscillator high gain. */
363 #else
364 | MCG_C2_HGO0_MASK, /*!< Oscillator high gain. */
365 #endif
366 } osc_mode_t;
367
368 /*! @brief Oscillator capacitor load setting.*/
369 enum _osc_cap_load
370 {
371 kOSC_Cap2P = OSC_CR_SC2P_MASK, /*!< 2 pF capacitor load */
372 kOSC_Cap4P = OSC_CR_SC4P_MASK, /*!< 4 pF capacitor load */
373 kOSC_Cap8P = OSC_CR_SC8P_MASK, /*!< 8 pF capacitor load */
374 kOSC_Cap16P = OSC_CR_SC16P_MASK /*!< 16 pF capacitor load */
375 };
376
377 /*! @brief OSCERCLK enable mode. */
378 enum _oscer_enable_mode
379 {
380 kOSC_ErClkEnable = OSC_CR_ERCLKEN_MASK, /*!< Enable. */
381 kOSC_ErClkEnableInStop = OSC_CR_EREFSTEN_MASK /*!< Enable in stop mode. */
382 };
383
384 /*! @brief OSC configuration for OSCERCLK. */
385 typedef struct _oscer_config
386 {
387 uint8_t enableMode; /*!< OSCERCLK enable mode. OR'ed value of @ref _oscer_enable_mode. */
388
389 uint8_t erclkDiv; /*!< Divider for OSCERCLK.*/
390 } oscer_config_t;
391
392 /*!
393 * @brief OSC Initialization Configuration Structure
394 *
395 * Defines the configuration data structure to initialize the OSC.
396 * When porting to a new board, set the following members
397 * according to the board setting:
398 * 1. freq: The external frequency.
399 * 2. workMode: The OSC module mode.
400 */
401 typedef struct _osc_config
402 {
403 uint32_t freq; /*!< External clock frequency. */
404 uint8_t capLoad; /*!< Capacitor load setting. */
405 osc_mode_t workMode; /*!< OSC work mode setting. */
406 oscer_config_t oscerConfig; /*!< Configuration for OSCERCLK. */
407 } osc_config_t;
408
409 /*! @brief MCG FLL reference clock source select. */
410 typedef enum _mcg_fll_src
411 {
412 kMCG_FllSrcExternal, /*!< External reference clock is selected */
413 kMCG_FllSrcInternal /*!< The slow internal reference clock is selected */
414 } mcg_fll_src_t;
415
416 /*! @brief MCG internal reference clock select */
417 typedef enum _mcg_irc_mode
418 {
419 kMCG_IrcSlow, /*!< Slow internal reference clock selected */
420 kMCG_IrcFast /*!< Fast internal reference clock selected */
421 } mcg_irc_mode_t;
422
423 /*! @brief MCG DCO Maximum Frequency with 32.768 kHz Reference */
424 typedef enum _mcg_dmx32
425 {
426 kMCG_Dmx32Default, /*!< DCO has a default range of 25% */
427 kMCG_Dmx32Fine /*!< DCO is fine-tuned for maximum frequency with 32.768 kHz reference */
428 } mcg_dmx32_t;
429
430 /*! @brief MCG DCO range select */
431 typedef enum _mcg_drs
432 {
433 kMCG_DrsLow, /*!< Low frequency range */
434 kMCG_DrsMid, /*!< Mid frequency range */
435 kMCG_DrsMidHigh, /*!< Mid-High frequency range */
436 kMCG_DrsHigh /*!< High frequency range */
437 } mcg_drs_t;
438
439 /*! @brief MCG PLL reference clock select */
440 typedef enum _mcg_pll_ref_src
441 {
442 kMCG_PllRefOsc0, /*!< Selects OSC0 as PLL reference clock */
443 kMCG_PllRefOsc1 /*!< Selects OSC1 as PLL reference clock */
444 } mcg_pll_ref_src_t;
445
446 /*! @brief MCGOUT clock source. */
447 typedef enum _mcg_clkout_src
448 {
449 kMCG_ClkOutSrcOut, /*!< Output of the FLL is selected (reset default) */
450 kMCG_ClkOutSrcInternal, /*!< Internal reference clock is selected */
451 kMCG_ClkOutSrcExternal, /*!< External reference clock is selected */
452 } mcg_clkout_src_t;
453
454 /*! @brief MCG Automatic Trim Machine Select */
455 typedef enum _mcg_atm_select
456 {
457 kMCG_AtmSel32k, /*!< 32 kHz Internal Reference Clock selected */
458 kMCG_AtmSel4m /*!< 4 MHz Internal Reference Clock selected */
459 } mcg_atm_select_t;
460
461 /*! @brief MCG OSC Clock Select */
462 typedef enum _mcg_oscsel
463 {
464 kMCG_OscselOsc, /*!< Selects System Oscillator (OSCCLK) */
465 kMCG_OscselRtc, /*!< Selects 32 kHz RTC Oscillator */
466 kMCG_OscselIrc /*!< Selects 48 MHz IRC Oscillator */
467 } mcg_oscsel_t;
468
469 /*! @brief MCG PLLCS select */
470 typedef enum _mcg_pll_clk_select
471 {
472 kMCG_PllClkSelPll0, /*!< PLL0 output clock is selected */
473 kMCG_PllClkSelPll1 /* PLL1 output clock is selected */
474 } mcg_pll_clk_select_t;
475
476 /*! @brief MCG clock monitor mode. */
477 typedef enum _mcg_monitor_mode
478 {
479 kMCG_MonitorNone, /*!< Clock monitor is disabled. */
480 kMCG_MonitorInt, /*!< Trigger interrupt when clock lost. */
481 kMCG_MonitorReset /*!< System reset when clock lost. */
482 } mcg_monitor_mode_t;
483
484 /*! @brief MCG status. */
485 enum
486 {
487 kStatus_MCG_ModeUnreachable = MAKE_STATUS(kStatusGroup_MCG, 0U), /*!< Can't switch to target mode. */
488 kStatus_MCG_ModeInvalid = MAKE_STATUS(kStatusGroup_MCG, 1U), /*!< Current mode invalid for the specific
489 function. */
490 kStatus_MCG_AtmBusClockInvalid = MAKE_STATUS(kStatusGroup_MCG, 2U), /*!< Invalid bus clock for ATM. */
491 kStatus_MCG_AtmDesiredFreqInvalid = MAKE_STATUS(kStatusGroup_MCG, 3U), /*!< Invalid desired frequency for ATM. */
492 kStatus_MCG_AtmIrcUsed = MAKE_STATUS(kStatusGroup_MCG, 4U), /*!< IRC is used when using ATM. */
493 kStatus_MCG_AtmHardwareFail = MAKE_STATUS(kStatusGroup_MCG, 5U), /*!< Hardware fail occurs during ATM. */
494 kStatus_MCG_SourceUsed = MAKE_STATUS(kStatusGroup_MCG, 6U) /*!< Can't change the clock source because
495 it is in use. */
496 };
497
498 /*! @brief MCG status flags. */
499 enum
500 {
501 kMCG_Osc0LostFlag = (1U << 0U), /*!< OSC0 lost. */
502 kMCG_Osc0InitFlag = (1U << 1U), /*!< OSC0 crystal initialized. */
503 kMCG_Pll0LostFlag = (1U << 5U), /*!< PLL0 lost. */
504 kMCG_Pll0LockFlag = (1U << 6U), /*!< PLL0 locked. */
505 };
506
507 /*! @brief MCG internal reference clock (MCGIRCLK) enable mode definition. */
508 enum
509 {
510 kMCG_IrclkEnable = MCG_C1_IRCLKEN_MASK, /*!< MCGIRCLK enable. */
511 kMCG_IrclkEnableInStop = MCG_C1_IREFSTEN_MASK /*!< MCGIRCLK enable in stop mode. */
512 };
513
514 /*! @brief MCG PLL clock enable mode definition. */
515 enum
516 {
517 kMCG_PllEnableIndependent = MCG_C5_PLLCLKEN0_MASK, /*!< MCGPLLCLK enable independent of the
518 MCG clock mode. Generally, the PLL
519 is disabled in FLL modes
520 (FEI/FBI/FEE/FBE). Setting the PLL clock
521 enable independent, enables the
522 PLL in the FLL modes. */
523 kMCG_PllEnableInStop = MCG_C5_PLLSTEN0_MASK /*!< MCGPLLCLK enable in STOP mode. */
524 };
525
526 /*! @brief MCG mode definitions */
527 typedef enum _mcg_mode
528 {
529 kMCG_ModeFEI = 0U, /*!< FEI - FLL Engaged Internal */
530 kMCG_ModeFBI, /*!< FBI - FLL Bypassed Internal */
531 kMCG_ModeBLPI, /*!< BLPI - Bypassed Low Power Internal */
532 kMCG_ModeFEE, /*!< FEE - FLL Engaged External */
533 kMCG_ModeFBE, /*!< FBE - FLL Bypassed External */
534 kMCG_ModeBLPE, /*!< BLPE - Bypassed Low Power External */
535 kMCG_ModePBE, /*!< PBE - PLL Bypassed External */
536 kMCG_ModePEE, /*!< PEE - PLL Engaged External */
537 kMCG_ModeError /*!< Unknown mode */
538 } mcg_mode_t;
539
540 /*! @brief MCG PLL configuration. */
541 typedef struct _mcg_pll_config
542 {
543 uint8_t enableMode; /*!< Enable mode. OR'ed value of @ref _mcg_pll_enable_mode. */
544 uint8_t prdiv; /*!< Reference divider PRDIV. */
545 uint8_t vdiv; /*!< VCO divider VDIV. */
546 } mcg_pll_config_t;
547
548 /*! @brief MCG mode change configuration structure
549 *
550 * When porting to a new board, set the following members
551 * according to the board setting:
552 * 1. frdiv: If the FLL uses the external reference clock, set this
553 * value to ensure that the external reference clock divided by frdiv is
554 * in the 31.25 kHz to 39.0625 kHz range.
555 * 2. The PLL reference clock divider PRDIV: PLL reference clock frequency after
556 * PRDIV should be in the FSL_FEATURE_MCG_PLL_REF_MIN to
557 * FSL_FEATURE_MCG_PLL_REF_MAX range.
558 */
559 typedef struct _mcg_config
560 {
561 mcg_mode_t mcgMode; /*!< MCG mode. */
562
563 /* ----------------------- MCGIRCCLK settings ------------------------ */
564 uint8_t irclkEnableMode; /*!< MCGIRCLK enable mode. */
565 mcg_irc_mode_t ircs; /*!< Source, MCG_C2[IRCS]. */
566 uint8_t fcrdiv; /*!< Divider, MCG_SC[FCRDIV]. */
567
568 /* ------------------------ MCG FLL settings ------------------------- */
569 uint8_t frdiv; /*!< Divider MCG_C1[FRDIV]. */
570 mcg_drs_t drs; /*!< DCO range MCG_C4[DRST_DRS]. */
571 mcg_dmx32_t dmx32; /*!< MCG_C4[DMX32]. */
572 mcg_oscsel_t oscsel; /*!< OSC select MCG_C7[OSCSEL]. */
573
574 /* ------------------------ MCG PLL settings ------------------------- */
575 mcg_pll_config_t pll0Config; /*!< MCGPLL0CLK configuration. */
576
577 } mcg_config_t;
578
579 /*******************************************************************************
580 * API
581 ******************************************************************************/
582
583 #if defined(__cplusplus)
584 extern "C" {
585 #endif /* __cplusplus */
586
587 /*!
588 * @brief Enable the clock for specific IP.
589 *
590 * @param name Which clock to enable, see \ref clock_ip_name_t.
591 */
CLOCK_EnableClock(clock_ip_name_t name)592 static inline void CLOCK_EnableClock(clock_ip_name_t name)
593 {
594 uint32_t regAddr = SIM_BASE + CLK_GATE_ABSTRACT_REG_OFFSET((uint32_t)name);
595 (*(volatile uint32_t *)regAddr) |= (1UL << CLK_GATE_ABSTRACT_BITS_SHIFT((uint32_t)name));
596 }
597
598 /*!
599 * @brief Disable the clock for specific IP.
600 *
601 * @param name Which clock to disable, see \ref clock_ip_name_t.
602 */
CLOCK_DisableClock(clock_ip_name_t name)603 static inline void CLOCK_DisableClock(clock_ip_name_t name)
604 {
605 uint32_t regAddr = SIM_BASE + CLK_GATE_ABSTRACT_REG_OFFSET((uint32_t)name);
606 (*(volatile uint32_t *)regAddr) &= ~(1UL << CLK_GATE_ABSTRACT_BITS_SHIFT((uint32_t)name));
607 }
608
609 /*!
610 * @brief Set ERCLK32K source.
611 *
612 * @param src The value to set ERCLK32K clock source.
613 */
CLOCK_SetEr32kClock(uint32_t src)614 static inline void CLOCK_SetEr32kClock(uint32_t src)
615 {
616 SIM->SOPT1 = ((SIM->SOPT1 & ~SIM_SOPT1_OSC32KSEL_MASK) | SIM_SOPT1_OSC32KSEL(src));
617 }
618
619 /*!
620 * @brief Set debug trace clock source.
621 *
622 * @param src The value to set debug trace clock source.
623 */
CLOCK_SetTraceClock(uint32_t src)624 static inline void CLOCK_SetTraceClock(uint32_t src)
625 {
626 SIM->SOPT2 = ((SIM->SOPT2 & ~SIM_SOPT2_TRACECLKSEL_MASK) | SIM_SOPT2_TRACECLKSEL(src));
627 }
628
629 /*!
630 * @brief Set PLLFLLSEL clock source.
631 *
632 * @param src The value to set PLLFLLSEL clock source.
633 */
CLOCK_SetPllFllSelClock(uint32_t src)634 static inline void CLOCK_SetPllFllSelClock(uint32_t src)
635 {
636 SIM->SOPT2 = ((SIM->SOPT2 & ~SIM_SOPT2_PLLFLLSEL_MASK) | SIM_SOPT2_PLLFLLSEL(src));
637 }
638
639 /*!
640 * @brief Set CLKOUT source.
641 *
642 * @param src The value to set CLKOUT select.
643 */
CLOCK_SetClkOutClock(uint32_t src)644 static inline void CLOCK_SetClkOutClock(uint32_t src)
645 {
646 SIM->SOPT2 = ((SIM->SOPT2 & ~SIM_SOPT2_CLKOUTSEL_MASK) | SIM_SOPT2_CLKOUTSEL(src));
647 }
648
649 /*!
650 * @brief System clock divider
651 *
652 * Set the SIM_CLKDIV1[OUTDIV1], SIM_CLKDIV1[OUTDIV2], SIM_CLKDIV1[OUTDIV3], SIM_CLKDIV1[OUTDIV4].
653 *
654 * @param outdiv1 Clock 1 output divider value.
655 *
656 * @param outdiv2 Clock 2 output divider value.
657 *
658 * @param outdiv3 Clock 3 output divider value.
659 *
660 * @param outdiv4 Clock 4 output divider value.
661 */
CLOCK_SetOutDiv(uint32_t outdiv1,uint32_t outdiv2,uint32_t outdiv4)662 static inline void CLOCK_SetOutDiv(uint32_t outdiv1, uint32_t outdiv2, uint32_t outdiv4)
663 {
664 SIM->CLKDIV1 = SIM_CLKDIV1_OUTDIV1(outdiv1) | SIM_CLKDIV1_OUTDIV2(outdiv2) | SIM_CLKDIV1_OUTDIV4(outdiv4);
665 }
666
667 /*!
668 * @brief Gets the clock frequency for a specific clock name.
669 *
670 * This function checks the current clock configurations and then calculates
671 * the clock frequency for a specific clock name defined in clock_name_t.
672 * The MCG must be properly configured before using this function.
673 *
674 * @param clockName Clock names defined in clock_name_t
675 * @return Clock frequency value in Hertz
676 */
677 uint32_t CLOCK_GetFreq(clock_name_t clockName);
678
679 /*!
680 * @brief Get the core clock or system clock frequency.
681 *
682 * @return Clock frequency in Hz.
683 */
684 uint32_t CLOCK_GetCoreSysClkFreq(void);
685
686 /*!
687 * @brief Get the platform clock frequency.
688 *
689 * @return Clock frequency in Hz.
690 */
691 uint32_t CLOCK_GetPlatClkFreq(void);
692
693 /*!
694 * @brief Get the bus clock frequency.
695 *
696 * @return Clock frequency in Hz.
697 */
698 uint32_t CLOCK_GetBusClkFreq(void);
699
700 /*!
701 * @brief Get the flash clock frequency.
702 *
703 * @return Clock frequency in Hz.
704 */
705 uint32_t CLOCK_GetFlashClkFreq(void);
706
707 /*!
708 * @brief Get the output clock frequency selected by SIM[PLLFLLSEL].
709 *
710 * @return Clock frequency in Hz.
711 */
712 uint32_t CLOCK_GetPllFllSelClkFreq(void);
713
714 /*!
715 * @brief Get the external reference 32K clock frequency (ERCLK32K).
716 *
717 * @return Clock frequency in Hz.
718 */
719 uint32_t CLOCK_GetEr32kClkFreq(void);
720
721 /*!
722 * @brief Get the OSC0 external reference undivided clock frequency (OSC0ERCLK_UNDIV).
723 *
724 * @return Clock frequency in Hz.
725 */
726 uint32_t CLOCK_GetOsc0ErClkUndivFreq(void);
727
728 /*!
729 * @brief Get the OSC0 external reference clock frequency (OSC0ERCLK).
730 *
731 * @return Clock frequency in Hz.
732 */
733 uint32_t CLOCK_GetOsc0ErClkFreq(void);
734
735 /*!
736 * @brief Get the OSC0 external reference divided clock frequency.
737 *
738 * @return Clock frequency in Hz.
739 */
740 uint32_t CLOCK_GetOsc0ErClkDivFreq(void);
741
742 /*!
743 * @brief Set the clock configure in SIM module.
744 *
745 * This function sets system layer clock settings in SIM module.
746 *
747 * @param config Pointer to the configure structure.
748 */
749 void CLOCK_SetSimConfig(sim_clock_config_t const *config);
750
751 /*!
752 * @brief Set the system clock dividers in SIM to safe value.
753 *
754 * The system level clocks (core clock, bus clock, flexbus clock and flash clock)
755 * must be in allowed ranges. During MCG clock mode switch, the MCG output clock
756 * changes then the system level clocks may be out of range. This function could
757 * be used before MCG mode change, to make sure system level clocks are in allowed
758 * range.
759 *
760 * @param config Pointer to the configure structure.
761 */
CLOCK_SetSimSafeDivs(void)762 static inline void CLOCK_SetSimSafeDivs(void)
763 {
764 SIM->CLKDIV1 = 0x01230000U;
765 }
766
767 /*! @name MCG frequency functions. */
768 /*@{*/
769
770 /*!
771 * @brief Gets the MCG output clock (MCGOUTCLK) frequency.
772 *
773 * This function gets the MCG output clock frequency in Hz based on the current MCG
774 * register value.
775 *
776 * @return The frequency of MCGOUTCLK.
777 */
778 uint32_t CLOCK_GetOutClkFreq(void);
779
780 /*!
781 * @brief Gets the MCG FLL clock (MCGFLLCLK) frequency.
782 *
783 * This function gets the MCG FLL clock frequency in Hz based on the current MCG
784 * register value. The FLL is enabled in FEI/FBI/FEE/FBE mode and
785 * disabled in low power state in other modes.
786 *
787 * @return The frequency of MCGFLLCLK.
788 */
789 uint32_t CLOCK_GetFllFreq(void);
790
791 /*!
792 * @brief Gets the MCG internal reference clock (MCGIRCLK) frequency.
793 *
794 * This function gets the MCG internal reference clock frequency in Hz based
795 * on the current MCG register value.
796 *
797 * @return The frequency of MCGIRCLK.
798 */
799 uint32_t CLOCK_GetInternalRefClkFreq(void);
800
801 /*!
802 * @brief Gets the MCG fixed frequency clock (MCGFFCLK) frequency.
803 *
804 * This function gets the MCG fixed frequency clock frequency in Hz based
805 * on the current MCG register value.
806 *
807 * @return The frequency of MCGFFCLK.
808 */
809 uint32_t CLOCK_GetFixedFreqClkFreq(void);
810
811 /*!
812 * @brief Gets the MCG PLL0 clock (MCGPLL0CLK) frequency.
813 *
814 * This function gets the MCG PLL0 clock frequency in Hz based on the current MCG
815 * register value.
816 *
817 * @return The frequency of MCGPLL0CLK.
818 */
819 uint32_t CLOCK_GetPll0Freq(void);
820
821 /*@}*/
822
823 /*! @name MCG clock configuration. */
824 /*@{*/
825
826 /*!
827 * @brief Enables or disables the MCG low power.
828 *
829 * Enabling the MCG low power disables the PLL and FLL in bypass modes. In other words,
830 * in FBE and PBE modes, enabling low power sets the MCG to BLPE mode. In FBI and
831 * PBI modes, enabling low power sets the MCG to BLPI mode.
832 * When disabling the MCG low power, the PLL or FLL are enabled based on MCG settings.
833 *
834 * @param enable True to enable MCG low power, false to disable MCG low power.
835 */
CLOCK_SetLowPowerEnable(bool enable)836 static inline void CLOCK_SetLowPowerEnable(bool enable)
837 {
838 if (enable)
839 {
840 MCG->C2 |= MCG_C2_LP_MASK;
841 }
842 else
843 {
844 MCG->C2 &= ~(uint8_t)MCG_C2_LP_MASK;
845 }
846 }
847
848 /*!
849 * @brief Configures the Internal Reference clock (MCGIRCLK).
850 *
851 * This function sets the \c MCGIRCLK base on parameters. It also selects the IRC
852 * source. If the fast IRC is used, this function sets the fast IRC divider.
853 * This function also sets whether the \c MCGIRCLK is enabled in stop mode.
854 * Calling this function in FBI/PBI/BLPI modes may change the system clock. As a result,
855 * using the function in these modes it is not allowed.
856 *
857 * @param enableMode MCGIRCLK enable mode, OR'ed value of @ref _mcg_irclk_enable_mode.
858 * @param ircs MCGIRCLK clock source, choose fast or slow.
859 * @param fcrdiv Fast IRC divider setting (\c FCRDIV).
860 * @retval kStatus_MCG_SourceUsed Because the internal reference clock is used as a clock source,
861 * the configuration should not be changed. Otherwise, a glitch occurs.
862 * @retval kStatus_Success MCGIRCLK configuration finished successfully.
863 */
864 status_t CLOCK_SetInternalRefClkConfig(uint8_t enableMode, mcg_irc_mode_t ircs, uint8_t fcrdiv);
865
866 /*!
867 * @brief Selects the MCG external reference clock.
868 *
869 * Selects the MCG external reference clock source, changes the MCG_C7[OSCSEL],
870 * and waits for the clock source to be stable. Because the external reference
871 * clock should not be changed in FEE/FBE/BLPE/PBE/PEE modes, do not call this function in these modes.
872 *
873 * @param oscsel MCG external reference clock source, MCG_C7[OSCSEL].
874 * @retval kStatus_MCG_SourceUsed Because the external reference clock is used as a clock source,
875 * the configuration should not be changed. Otherwise, a glitch occurs.
876 * @retval kStatus_Success External reference clock set successfully.
877 */
878 status_t CLOCK_SetExternalRefClkConfig(mcg_oscsel_t oscsel);
879
880 /*!
881 * @brief Set the FLL external reference clock divider value.
882 *
883 * Sets the FLL external reference clock divider value, the register MCG_C1[FRDIV].
884 *
885 * @param frdiv The FLL external reference clock divider value, MCG_C1[FRDIV].
886 */
CLOCK_SetFllExtRefDiv(uint8_t frdiv)887 static inline void CLOCK_SetFllExtRefDiv(uint8_t frdiv)
888 {
889 MCG->C1 = (uint8_t)((MCG->C1 & ~MCG_C1_FRDIV_MASK) | MCG_C1_FRDIV(frdiv));
890 }
891
892 /*!
893 * @brief Enables the PLL0 in FLL mode.
894 *
895 * This function sets us the PLL0 in FLL mode and reconfigures
896 * the PLL0. Ensure that the PLL reference
897 * clock is enabled before calling this function and that the PLL0 is not used as a clock source.
898 * The function CLOCK_CalcPllDiv gets the correct PLL
899 * divider values.
900 *
901 * @param config Pointer to the configuration structure.
902 */
903 void CLOCK_EnablePll0(mcg_pll_config_t const *config);
904
905 /*!
906 * @brief Disables the PLL0 in FLL mode.
907 *
908 * This function disables the PLL0 in FLL mode. It should be used together with the
909 * @ref CLOCK_EnablePll0.
910 */
CLOCK_DisablePll0(void)911 static inline void CLOCK_DisablePll0(void)
912 {
913 MCG->C5 &= (uint8_t)(~(MCG_C5_PLLCLKEN0_MASK | MCG_C5_PLLSTEN0_MASK));
914 }
915
916 /*!
917 * @brief Calculates the PLL divider setting for a desired output frequency.
918 *
919 * This function calculates the correct reference clock divider (\c PRDIV) and
920 * VCO divider (\c VDIV) to generate a desired PLL output frequency. It returns the
921 * closest frequency match with the corresponding \c PRDIV/VDIV
922 * returned from parameters. If a desired frequency is not valid, this function
923 * returns 0.
924 *
925 * @param refFreq PLL reference clock frequency.
926 * @param desireFreq Desired PLL output frequency.
927 * @param prdiv PRDIV value to generate desired PLL frequency.
928 * @param vdiv VDIV value to generate desired PLL frequency.
929 * @return Closest frequency match that the PLL was able generate.
930 */
931 uint32_t CLOCK_CalcPllDiv(uint32_t refFreq, uint32_t desireFreq, uint8_t *prdiv, uint8_t *vdiv);
932
933 /*@}*/
934
935 /*! @name MCG clock lock monitor functions. */
936 /*@{*/
937
938 /*!
939 * @brief Sets the OSC0 clock monitor mode.
940 *
941 * This function sets the OSC0 clock monitor mode. See @ref mcg_monitor_mode_t for details.
942 *
943 * @param mode Monitor mode to set.
944 */
945 void CLOCK_SetOsc0MonitorMode(mcg_monitor_mode_t mode);
946
947 /*!
948 * @brief Sets the PLL0 clock monitor mode.
949 *
950 * This function sets the PLL0 clock monitor mode. See @ref mcg_monitor_mode_t for details.
951 *
952 * @param mode Monitor mode to set.
953 */
954 void CLOCK_SetPll0MonitorMode(mcg_monitor_mode_t mode);
955
956 /*!
957 * @brief Gets the MCG status flags.
958 *
959 * This function gets the MCG clock status flags. All status flags are
960 * returned as a logical OR of the enumeration @ref _mcg_status_flags_t. To
961 * check a specific flag, compare the return value with the flag.
962 *
963 * Example:
964 * @code
965 * To check the clock lost lock status of OSC0 and PLL0.
966 * uint32_t mcgFlags;
967 *
968 * mcgFlags = CLOCK_GetStatusFlags();
969 *
970 * if (mcgFlags & kMCG_Osc0LostFlag)
971 * {
972 * OSC0 clock lock lost. Do something.
973 * }
974 * if (mcgFlags & kMCG_Pll0LostFlag)
975 * {
976 * PLL0 clock lock lost. Do something.
977 * }
978 * @endcode
979 *
980 * @return Logical OR value of the @ref _mcg_status_flags_t.
981 */
982 uint32_t CLOCK_GetStatusFlags(void);
983
984 /*!
985 * @brief Clears the MCG status flags.
986 *
987 * This function clears the MCG clock lock lost status. The parameter is a logical
988 * OR value of the flags to clear. See @ref _mcg_status_flags_t.
989 *
990 * Example:
991 * @code
992 * To clear the clock lost lock status flags of OSC0 and PLL0.
993 *
994 * CLOCK_ClearStatusFlags(kMCG_Osc0LostFlag | kMCG_Pll0LostFlag);
995 * @endcode
996 *
997 * @param mask The status flags to clear. This is a logical OR of members of the
998 * enumeration @ref _mcg_status_flags_t.
999 */
1000 void CLOCK_ClearStatusFlags(uint32_t mask);
1001
1002 /*@}*/
1003
1004 /*!
1005 * @name OSC configuration
1006 * @{
1007 */
1008
1009 /*!
1010 * @brief Configures the OSC external reference clock (OSCERCLK).
1011 *
1012 * This function configures the OSC external reference clock (OSCERCLK).
1013 * This is an example to enable the OSCERCLK in normal and stop modes and also set
1014 * the output divider to 1:
1015 *
1016 @code
1017 oscer_config_t config =
1018 {
1019 .enableMode = kOSC_ErClkEnable | kOSC_ErClkEnableInStop,
1020 .erclkDiv = 1U,
1021 };
1022
1023 OSC_SetExtRefClkConfig(OSC, &config);
1024 @endcode
1025 *
1026 * @param base OSC peripheral address.
1027 * @param config Pointer to the configuration structure.
1028 */
OSC_SetExtRefClkConfig(OSC_Type * base,oscer_config_t const * config)1029 static inline void OSC_SetExtRefClkConfig(OSC_Type *base, oscer_config_t const *config)
1030 {
1031 uint8_t reg = base->CR;
1032
1033 reg &= (uint8_t)(~(OSC_CR_ERCLKEN_MASK | OSC_CR_EREFSTEN_MASK));
1034 reg |= config->enableMode;
1035
1036 base->CR = reg;
1037
1038 base->DIV = OSC_DIV_ERPS(config->erclkDiv);
1039 }
1040
1041 /*!
1042 * @brief Sets the capacitor load configuration for the oscillator.
1043 *
1044 * This function sets the specified capacitors configuration for the oscillator.
1045 * This should be done in the early system level initialization function call
1046 * based on the system configuration.
1047 *
1048 * @param base OSC peripheral address.
1049 * @param capLoad OR'ed value for the capacitor load option, see \ref _osc_cap_load.
1050 *
1051 * Example:
1052 @code
1053 To enable only 2 pF and 8 pF capacitor load, please use like this.
1054 OSC_SetCapLoad(OSC, kOSC_Cap2P | kOSC_Cap8P);
1055 @endcode
1056 */
OSC_SetCapLoad(OSC_Type * base,uint8_t capLoad)1057 static inline void OSC_SetCapLoad(OSC_Type *base, uint8_t capLoad)
1058 {
1059 uint8_t reg = base->CR;
1060
1061 reg &= (uint8_t)(~(OSC_CR_SC2P_MASK | OSC_CR_SC4P_MASK | OSC_CR_SC8P_MASK | OSC_CR_SC16P_MASK));
1062 reg |= capLoad;
1063
1064 base->CR = reg;
1065 }
1066
1067 /*!
1068 * @brief Initializes the OSC0.
1069 *
1070 * This function initializes the OSC0 according to the board configuration.
1071 *
1072 * @param config Pointer to the OSC0 configuration structure.
1073 */
1074 void CLOCK_InitOsc0(osc_config_t const *config);
1075
1076 /*!
1077 * @brief Deinitializes the OSC0.
1078 *
1079 * This function deinitializes the OSC0.
1080 */
1081 void CLOCK_DeinitOsc0(void);
1082
1083 /* @} */
1084
1085 /*!
1086 * @name External clock frequency
1087 * @{
1088 */
1089
1090 /*!
1091 * @brief Sets the XTAL0 frequency based on board settings.
1092 *
1093 * @param freq The XTAL0/EXTAL0 input clock frequency in Hz.
1094 */
CLOCK_SetXtal0Freq(uint32_t freq)1095 static inline void CLOCK_SetXtal0Freq(uint32_t freq)
1096 {
1097 g_xtal0Freq = freq;
1098 }
1099
1100 /*!
1101 * @brief Sets the XTAL32/RTC_CLKIN frequency based on board settings.
1102 *
1103 * @param freq The XTAL32/EXTAL32/RTC_CLKIN input clock frequency in Hz.
1104 */
CLOCK_SetXtal32Freq(uint32_t freq)1105 static inline void CLOCK_SetXtal32Freq(uint32_t freq)
1106 {
1107 g_xtal32Freq = freq;
1108 }
1109 /* @} */
1110
1111 /*!
1112 * @name IRCs frequency
1113 * @{
1114 */
1115
1116 /*!
1117 * @brief Set the Slow IRC frequency based on the trimmed value
1118 *
1119 * @param freq The Slow IRC frequency input clock frequency in Hz.
1120 */
1121 void CLOCK_SetSlowIrcFreq(uint32_t freq);
1122
1123 /*!
1124 * @brief Set the Fast IRC frequency based on the trimmed value
1125 *
1126 * @param freq The Fast IRC frequency input clock frequency in Hz.
1127 */
1128 void CLOCK_SetFastIrcFreq(uint32_t freq);
1129 /* @} */
1130
1131 /*!
1132 * @name MCG auto-trim machine.
1133 * @{
1134 */
1135
1136 /*!
1137 * @brief Auto trims the internal reference clock.
1138 *
1139 * This function trims the internal reference clock by using the external clock. If
1140 * successful, it returns the kStatus_Success and the frequency after
1141 * trimming is received in the parameter @p actualFreq. If an error occurs,
1142 * the error code is returned.
1143 *
1144 * @param extFreq External clock frequency, which should be a bus clock.
1145 * @param desireFreq Frequency to trim to.
1146 * @param actualFreq Actual frequency after trimming.
1147 * @param atms Trim fast or slow internal reference clock.
1148 * @retval kStatus_Success ATM success.
1149 * @retval kStatus_MCG_AtmBusClockInvalid The bus clock is not in allowed range for the ATM.
1150 * @retval kStatus_MCG_AtmDesiredFreqInvalid MCGIRCLK could not be trimmed to the desired frequency.
1151 * @retval kStatus_MCG_AtmIrcUsed Could not trim because MCGIRCLK is used as a bus clock source.
1152 * @retval kStatus_MCG_AtmHardwareFail Hardware fails while trimming.
1153 */
1154 status_t CLOCK_TrimInternalRefClk(uint32_t extFreq, uint32_t desireFreq, uint32_t *actualFreq, mcg_atm_select_t atms);
1155 /* @} */
1156
1157 /*! @name MCG mode functions. */
1158 /*@{*/
1159
1160 /*!
1161 * @brief Gets the current MCG mode.
1162 *
1163 * This function checks the MCG registers and determines the current MCG mode.
1164 *
1165 * @return Current MCG mode or error code; See @ref mcg_mode_t.
1166 */
1167 mcg_mode_t CLOCK_GetMode(void);
1168
1169 /*!
1170 * @brief Sets the MCG to FEI mode.
1171 *
1172 * This function sets the MCG to FEI mode. If setting to FEI mode fails
1173 * from the current mode, this function returns an error.
1174 *
1175 * @param dmx32 DMX32 in FEI mode.
1176 * @param drs The DCO range selection.
1177 * @param fllStableDelay Delay function to ensure that the FLL is stable. Passing
1178 * NULL does not cause a delay.
1179 * @retval kStatus_MCG_ModeUnreachable Could not switch to the target mode.
1180 * @retval kStatus_Success Switched to the target mode successfully.
1181 * @note If @p dmx32 is set to kMCG_Dmx32Fine, the slow IRC must not be trimmed
1182 * to a frequency above 32768 Hz.
1183 */
1184 status_t CLOCK_SetFeiMode(mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDelay)(void));
1185
1186 /*!
1187 * @brief Sets the MCG to FEE mode.
1188 *
1189 * This function sets the MCG to FEE mode. If setting to FEE mode fails
1190 * from the current mode, this function returns an error.
1191 *
1192 * @param frdiv FLL reference clock divider setting, FRDIV.
1193 * @param dmx32 DMX32 in FEE mode.
1194 * @param drs The DCO range selection.
1195 * @param fllStableDelay Delay function to make sure FLL is stable. Passing
1196 * NULL does not cause a delay.
1197 *
1198 * @retval kStatus_MCG_ModeUnreachable Could not switch to the target mode.
1199 * @retval kStatus_Success Switched to the target mode successfully.
1200 */
1201 status_t CLOCK_SetFeeMode(uint8_t frdiv, mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDelay)(void));
1202
1203 /*!
1204 * @brief Sets the MCG to FBI mode.
1205 *
1206 * This function sets the MCG to FBI mode. If setting to FBI mode fails
1207 * from the current mode, this function returns an error.
1208 *
1209 * @param dmx32 DMX32 in FBI mode.
1210 * @param drs The DCO range selection.
1211 * @param fllStableDelay Delay function to make sure FLL is stable. If the FLL
1212 * is not used in FBI mode, this parameter can be NULL. Passing
1213 * NULL does not cause a delay.
1214 * @retval kStatus_MCG_ModeUnreachable Could not switch to the target mode.
1215 * @retval kStatus_Success Switched to the target mode successfully.
1216 * @note If @p dmx32 is set to kMCG_Dmx32Fine, the slow IRC must not be trimmed
1217 * to frequency above 32768 Hz.
1218 */
1219 status_t CLOCK_SetFbiMode(mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDelay)(void));
1220
1221 /*!
1222 * @brief Sets the MCG to FBE mode.
1223 *
1224 * This function sets the MCG to FBE mode. If setting to FBE mode fails
1225 * from the current mode, this function returns an error.
1226 *
1227 * @param frdiv FLL reference clock divider setting, FRDIV.
1228 * @param dmx32 DMX32 in FBE mode.
1229 * @param drs The DCO range selection.
1230 * @param fllStableDelay Delay function to make sure FLL is stable. If the FLL
1231 * is not used in FBE mode, this parameter can be NULL. Passing NULL
1232 * does not cause a delay.
1233 * @retval kStatus_MCG_ModeUnreachable Could not switch to the target mode.
1234 * @retval kStatus_Success Switched to the target mode successfully.
1235 */
1236 status_t CLOCK_SetFbeMode(uint8_t frdiv, mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDelay)(void));
1237
1238 /*!
1239 * @brief Sets the MCG to BLPI mode.
1240 *
1241 * This function sets the MCG to BLPI mode. If setting to BLPI mode fails
1242 * from the current mode, this function returns an error.
1243 *
1244 * @retval kStatus_MCG_ModeUnreachable Could not switch to the target mode.
1245 * @retval kStatus_Success Switched to the target mode successfully.
1246 */
1247 status_t CLOCK_SetBlpiMode(void);
1248
1249 /*!
1250 * @brief Sets the MCG to BLPE mode.
1251 *
1252 * This function sets the MCG to BLPE mode. If setting to BLPE mode fails
1253 * from the current mode, this function returns an error.
1254 *
1255 * @retval kStatus_MCG_ModeUnreachable Could not switch to the target mode.
1256 * @retval kStatus_Success Switched to the target mode successfully.
1257 */
1258 status_t CLOCK_SetBlpeMode(void);
1259
1260 /*!
1261 * @brief Sets the MCG to PBE mode.
1262 *
1263 * This function sets the MCG to PBE mode. If setting to PBE mode fails
1264 * from the current mode, this function returns an error.
1265 *
1266 * @param pllcs The PLL selection, PLLCS.
1267 * @param config Pointer to the PLL configuration.
1268 * @retval kStatus_MCG_ModeUnreachable Could not switch to the target mode.
1269 * @retval kStatus_Success Switched to the target mode successfully.
1270 *
1271 * @note
1272 * 1. The parameter \c pllcs selects the PLL. For platforms with
1273 * only one PLL, the parameter pllcs is kept for interface compatibility.
1274 * 2. The parameter \c config is the PLL configuration structure. On some
1275 * platforms, it is possible to choose the external PLL directly, which renders the
1276 * configuration structure not necessary. In this case, pass in NULL.
1277 * For example: CLOCK_SetPbeMode(kMCG_OscselOsc, kMCG_PllClkSelExtPll, NULL);
1278 */
1279 status_t CLOCK_SetPbeMode(mcg_pll_clk_select_t pllcs, mcg_pll_config_t const *config);
1280
1281 /*!
1282 * @brief Sets the MCG to PEE mode.
1283 *
1284 * This function sets the MCG to PEE mode.
1285 *
1286 * @retval kStatus_MCG_ModeUnreachable Could not switch to the target mode.
1287 * @retval kStatus_Success Switched to the target mode successfully.
1288 *
1289 * @note This function only changes the CLKS to use the PLL/FLL output. If the
1290 * PRDIV/VDIV are different than in the PBE mode, set them up
1291 * in PBE mode and wait. When the clock is stable, switch to PEE mode.
1292 */
1293 status_t CLOCK_SetPeeMode(void);
1294
1295 /*!
1296 * @brief Switches the MCG to FBE mode from the external mode.
1297 *
1298 * This function switches the MCG from external modes (PEE/PBE/BLPE/FEE) to the FBE mode quickly.
1299 * The external clock is used as the system clock source and PLL is disabled. However,
1300 * the FLL settings are not configured. This is a lite function with a small code size, which is useful
1301 * during the mode switch. For example, to switch from PEE mode to FEI mode:
1302 *
1303 * @code
1304 * CLOCK_ExternalModeToFbeModeQuick();
1305 * CLOCK_SetFeiMode(...);
1306 * @endcode
1307 *
1308 * @retval kStatus_Success Switched successfully.
1309 * @retval kStatus_MCG_ModeInvalid If the current mode is not an external mode, do not call this function.
1310 */
1311 status_t CLOCK_ExternalModeToFbeModeQuick(void);
1312
1313 /*!
1314 * @brief Switches the MCG to FBI mode from internal modes.
1315 *
1316 * This function switches the MCG from internal modes (PEI/PBI/BLPI/FEI) to the FBI mode quickly.
1317 * The MCGIRCLK is used as the system clock source and PLL is disabled. However,
1318 * FLL settings are not configured. This is a lite function with a small code size, which is useful
1319 * during the mode switch. For example, to switch from PEI mode to FEE mode:
1320 *
1321 * @code
1322 * CLOCK_InternalModeToFbiModeQuick();
1323 * CLOCK_SetFeeMode(...);
1324 * @endcode
1325 *
1326 * @retval kStatus_Success Switched successfully.
1327 * @retval kStatus_MCG_ModeInvalid If the current mode is not an internal mode, do not call this function.
1328 */
1329 status_t CLOCK_InternalModeToFbiModeQuick(void);
1330
1331 /*!
1332 * @brief Sets the MCG to FEI mode during system boot up.
1333 *
1334 * This function sets the MCG to FEI mode from the reset mode. It can also be used to
1335 * set up MCG during system boot up.
1336 *
1337 * @param dmx32 DMX32 in FEI mode.
1338 * @param drs The DCO range selection.
1339 * @param fllStableDelay Delay function to ensure that the FLL is stable.
1340 *
1341 * @retval kStatus_MCG_ModeUnreachable Could not switch to the target mode.
1342 * @retval kStatus_Success Switched to the target mode successfully.
1343 * @note If @p dmx32 is set to kMCG_Dmx32Fine, the slow IRC must not be trimmed
1344 * to frequency above 32768 Hz.
1345 */
1346 status_t CLOCK_BootToFeiMode(mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDelay)(void));
1347
1348 /*!
1349 * @brief Sets the MCG to FEE mode during system bootup.
1350 *
1351 * This function sets MCG to FEE mode from the reset mode. It can also be used to
1352 * set up the MCG during system boot up.
1353 *
1354 * @param oscsel OSC clock select, OSCSEL.
1355 * @param frdiv FLL reference clock divider setting, FRDIV.
1356 * @param dmx32 DMX32 in FEE mode.
1357 * @param drs The DCO range selection.
1358 * @param fllStableDelay Delay function to ensure that the FLL is stable.
1359 *
1360 * @retval kStatus_MCG_ModeUnreachable Could not switch to the target mode.
1361 * @retval kStatus_Success Switched to the target mode successfully.
1362 */
1363 status_t CLOCK_BootToFeeMode(
1364 mcg_oscsel_t oscsel, uint8_t frdiv, mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDelay)(void));
1365
1366 /*!
1367 * @brief Sets the MCG to BLPI mode during system boot up.
1368 *
1369 * This function sets the MCG to BLPI mode from the reset mode. It can also be used to
1370 * set up the MCG during system boot up.
1371 *
1372 * @param fcrdiv Fast IRC divider, FCRDIV.
1373 * @param ircs The internal reference clock to select, IRCS.
1374 * @param ircEnableMode The MCGIRCLK enable mode, OR'ed value of @ref _mcg_irclk_enable_mode.
1375 *
1376 * @retval kStatus_MCG_SourceUsed Could not change MCGIRCLK setting.
1377 * @retval kStatus_Success Switched to the target mode successfully.
1378 */
1379 status_t CLOCK_BootToBlpiMode(uint8_t fcrdiv, mcg_irc_mode_t ircs, uint8_t ircEnableMode);
1380
1381 /*!
1382 * @brief Sets the MCG to BLPE mode during system boot up.
1383 *
1384 * This function sets the MCG to BLPE mode from the reset mode. It can also be used to
1385 * set up the MCG during system boot up.
1386 *
1387 * @param oscsel OSC clock select, MCG_C7[OSCSEL].
1388 *
1389 * @retval kStatus_MCG_ModeUnreachable Could not switch to the target mode.
1390 * @retval kStatus_Success Switched to the target mode successfully.
1391 */
1392 status_t CLOCK_BootToBlpeMode(mcg_oscsel_t oscsel);
1393
1394 /*!
1395 * @brief Sets the MCG to PEE mode during system boot up.
1396 *
1397 * This function sets the MCG to PEE mode from reset mode. It can also be used to
1398 * set up the MCG during system boot up.
1399 *
1400 * @param oscsel OSC clock select, MCG_C7[OSCSEL].
1401 * @param pllcs The PLL selection, PLLCS.
1402 * @param config Pointer to the PLL configuration.
1403 *
1404 * @retval kStatus_MCG_ModeUnreachable Could not switch to the target mode.
1405 * @retval kStatus_Success Switched to the target mode successfully.
1406 */
1407 status_t CLOCK_BootToPeeMode(mcg_oscsel_t oscsel, mcg_pll_clk_select_t pllcs, mcg_pll_config_t const *config);
1408
1409 /*!
1410 * @brief Sets the MCG to a target mode.
1411 *
1412 * This function sets MCG to a target mode defined by the configuration
1413 * structure. If switching to the target mode fails, this function
1414 * chooses the correct path.
1415 *
1416 * @param config Pointer to the target MCG mode configuration structure.
1417 * @return Return kStatus_Success if switched successfully; Otherwise, it returns an error code #_mcg_status.
1418 *
1419 * @note If the external clock is used in the target mode, ensure that it is
1420 * enabled. For example, if the OSC0 is used, set up OSC0 correctly before calling this
1421 * function.
1422 */
1423 status_t CLOCK_SetMcgConfig(mcg_config_t const *config);
1424
1425 /*@}*/
1426
1427 #if defined(__cplusplus)
1428 }
1429 #endif /* __cplusplus */
1430
1431 /*! @} */
1432
1433 #endif /* _FSL_CLOCK_H_ */
1434
