1 /*
2 * Copyright (c) 2015, Freescale Semiconductor, Inc.
3 * Copyright 2016 - 2019, NXP
4 * All rights reserved.
5 *
6 * SPDX-License-Identifier: BSD-3-Clause
7 */
8
9 #ifndef _FSL_CLOCK_H_
10 #define _FSL_CLOCK_H_
11
12 #include "fsl_common.h"
13
14 /*! @addtogroup clock */
15 /*! @{ */
16
17 /*! @file */
18
19 /*******************************************************************************
20 * Configurations
21 ******************************************************************************/
22
23 /*! @brief Configures whether to check a parameter in a function.
24 *
25 * Some MCG settings must be changed with conditions, for example:
26 * 1. MCGIRCLK settings, such as the source, divider, and the trim value should not change when
27 * MCGIRCLK is used as a system clock source.
28 * 2. MCG_C7[OSCSEL] should not be changed when the external reference clock is used
29 * as a system clock source. For example, in FBE/BLPE/PBE modes.
30 * 3. The users should only switch between the supported clock modes.
31 *
32 * MCG functions check the parameter and MCG status before setting, if not allowed
33 * to change, the functions return error. The parameter checking increases code size,
34 * if code size is a critical requirement, change #MCG_CONFIG_CHECK_PARAM to 0 to
35 * disable parameter checking.
36 */
37 #ifndef MCG_CONFIG_CHECK_PARAM
38 #define MCG_CONFIG_CHECK_PARAM 0U
39 #endif
40
41 /*! @brief Configure whether driver controls clock
42 *
43 * When set to 0, peripheral drivers will enable clock in initialize function
44 * and disable clock in de-initialize function. When set to 1, peripheral
45 * driver will not control the clock, application could control the clock out of
46 * the driver.
47 *
48 * @note All drivers share this feature switcher. If it is set to 1, application
49 * should handle clock enable and disable for all drivers.
50 */
51 #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL))
52 #define FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL 0
53 #endif
54
55 /*******************************************************************************
56 * Definitions
57 ******************************************************************************/
58
59 /*! @name Driver version */
60 /*@{*/
61 /*! @brief CLOCK driver version 2.5.1. */
62 #define FSL_CLOCK_DRIVER_VERSION (MAKE_VERSION(2, 5, 1))
63 /*@}*/
64
65 /*! @brief External XTAL0 (OSC0) clock frequency.
66 *
67 * The XTAL0/EXTAL0 (OSC0) clock frequency in Hz. When the clock is set up, use the
68 * function CLOCK_SetXtal0Freq to set the value in the clock driver. For example,
69 * if XTAL0 is 8 MHz:
70 * @code
71 * Set up the OSC0
72 * CLOCK_InitOsc0(...);
73 * Set the XTAL0 value to the clock driver.
74 * CLOCK_SetXtal0Freq(80000000);
75 * @endcode
76 *
77 * This is important for the multicore platforms where only one core needs to set up the
78 * OSC0 using the CLOCK_InitOsc0. All other cores need to call the CLOCK_SetXtal0Freq
79 * to get a valid clock frequency.
80 */
81 extern volatile uint32_t g_xtal0Freq;
82
83 /*! @brief External XTAL32/EXTAL32/RTC_CLKIN clock frequency.
84 *
85 * The XTAL32/EXTAL32/RTC_CLKIN clock frequency in Hz. When the clock is set up, use the
86 * function CLOCK_SetXtal32Freq to set the value in the clock driver.
87 *
88 * This is important for the multicore platforms where only one core needs to set up
89 * the clock. All other cores need to call the CLOCK_SetXtal32Freq
90 * to get a valid clock frequency.
91 */
92 extern volatile uint32_t g_xtal32Freq;
93
94 /*! @brief IRC48M clock frequency in Hz. */
95 #define MCG_INTERNAL_IRC_48M 48000000U
96
97 #if (defined(OSC) && !(defined(OSC0)))
98 #define OSC0 OSC
99 #endif
100
101 /* Definition for delay API in clock driver, users can redefine it to the real application. */
102 #ifndef SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY
103 #define SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY (120000000UL)
104 #endif
105
106 /*! @brief Clock ip name array for DMAMUX. */
107 #define DMAMUX_CLOCKS \
108 { \
109 kCLOCK_Dmamux0 \
110 }
111
112 /*! @brief Clock ip name array for RTC. */
113 #define RTC_CLOCKS \
114 { \
115 kCLOCK_Rtc0 \
116 }
117
118 /*! @brief Clock ip name array for SAI. */
119 #define SAI_CLOCKS \
120 { \
121 kCLOCK_Sai0 \
122 }
123
124 /*! @brief Clock ip name array for FLEXBUS. */
125 #define FLEXBUS_CLOCKS \
126 { \
127 kCLOCK_Flexbus0 \
128 }
129
130 /*! @brief Clock ip name array for PORT. */
131 #define PORT_CLOCKS \
132 { \
133 kCLOCK_PortA, kCLOCK_PortB, kCLOCK_PortC, kCLOCK_PortD, kCLOCK_PortE \
134 }
135
136 /*! @brief Clock ip name array for EWM. */
137 #define EWM_CLOCKS \
138 { \
139 kCLOCK_Ewm0 \
140 }
141
142 /*! @brief Clock ip name array for PIT. */
143 #define PIT_CLOCKS \
144 { \
145 kCLOCK_Pit0 \
146 }
147
148 /*! @brief Clock ip name array for SDHC. */
149 #define SDHC_CLOCKS \
150 { \
151 kCLOCK_Sdhc0 \
152 }
153
154 /*! @brief Clock ip name array for DSPI. */
155 #define DSPI_CLOCKS \
156 { \
157 kCLOCK_Spi0, kCLOCK_Spi1, kCLOCK_Spi2 \
158 }
159
160 /*! @brief Clock ip name array for LPTMR. */
161 #define LPTMR_CLOCKS \
162 { \
163 kCLOCK_Lptmr0 \
164 }
165
166 /*! @brief Clock ip name array for FTM. */
167 #define FTM_CLOCKS \
168 { \
169 kCLOCK_Ftm0, kCLOCK_Ftm1, kCLOCK_Ftm2, kCLOCK_Ftm3 \
170 }
171
172 /*! @brief Clock ip name array for EDMA. */
173 #define EDMA_CLOCKS \
174 { \
175 kCLOCK_Dma0 \
176 }
177
178 /*! @brief Clock ip name array for MPU. */
179 #define SYSMPU_CLOCKS \
180 { \
181 kCLOCK_Sysmpu0 \
182 }
183
184 /*! @brief Clock ip name array for DAC. */
185 #define DAC_CLOCKS \
186 { \
187 kCLOCK_Dac0, kCLOCK_Dac1 \
188 }
189
190 /*! @brief Clock ip name array for ADC16. */
191 #define ADC16_CLOCKS \
192 { \
193 kCLOCK_Adc0, kCLOCK_Adc1 \
194 }
195
196 /*! @brief Clock ip name array for VREF. */
197 #define VREF_CLOCKS \
198 { \
199 kCLOCK_Vref0 \
200 }
201
202 /*! @brief Clock ip name array for CMT. */
203 #define CMT_CLOCKS \
204 { \
205 kCLOCK_Cmt0 \
206 }
207
208 /*! @brief Clock ip name array for UART. */
209 #define UART_CLOCKS \
210 { \
211 kCLOCK_Uart0, kCLOCK_Uart1, kCLOCK_Uart2, kCLOCK_Uart3, kCLOCK_Uart4, kCLOCK_Uart5 \
212 }
213
214 /*! @brief Clock ip name array for RNGA. */
215 #define RNGA_CLOCKS \
216 { \
217 kCLOCK_Rnga0 \
218 }
219
220 /*! @brief Clock ip name array for CRC. */
221 #define CRC_CLOCKS \
222 { \
223 kCLOCK_Crc0 \
224 }
225
226 /*! @brief Clock ip name array for I2C. */
227 #define I2C_CLOCKS \
228 { \
229 kCLOCK_I2c0, kCLOCK_I2c1, kCLOCK_I2c2 \
230 }
231
232 /*! @brief Clock ip name array for PDB. */
233 #define PDB_CLOCKS \
234 { \
235 kCLOCK_Pdb0 \
236 }
237
238 /*! @brief Clock ip name array for FLEXCAN. */
239 #define FLEXCAN_CLOCKS \
240 { \
241 kCLOCK_Flexcan0 \
242 }
243
244 /*! @brief Clock ip name array for FTF. */
245 #define FTF_CLOCKS \
246 { \
247 kCLOCK_Ftf0 \
248 }
249
250 /*! @brief Clock ip name array for CMP. */
251 #define CMP_CLOCKS \
252 { \
253 kCLOCK_Cmp0, kCLOCK_Cmp1, kCLOCK_Cmp2 \
254 }
255
256 /*!
257 * @brief LPO clock frequency.
258 */
259 #define LPO_CLK_FREQ 1000U
260
261 /*! @brief Peripherals clock source definition. */
262 #define SYS_CLK kCLOCK_CoreSysClk
263 #define BUS_CLK kCLOCK_BusClk
264
265 #define I2C0_CLK_SRC BUS_CLK
266 #define I2C1_CLK_SRC BUS_CLK
267 #define I2C2_CLK_SRC BUS_CLK
268 #define DSPI0_CLK_SRC BUS_CLK
269 #define DSPI1_CLK_SRC BUS_CLK
270 #define DSPI2_CLK_SRC BUS_CLK
271 #define UART0_CLK_SRC SYS_CLK
272 #define UART1_CLK_SRC SYS_CLK
273 #define UART2_CLK_SRC BUS_CLK
274 #define UART3_CLK_SRC BUS_CLK
275 #define UART4_CLK_SRC BUS_CLK
276 #define UART5_CLK_SRC BUS_CLK
277
278 /*! @brief Clock name used to get clock frequency. */
279 typedef enum _clock_name
280 {
281
282 /* ----------------------------- System layer clock -------------------------------*/
283 kCLOCK_CoreSysClk, /*!< Core/system clock */
284 kCLOCK_PlatClk, /*!< Platform clock */
285 kCLOCK_BusClk, /*!< Bus clock */
286 kCLOCK_FlexBusClk, /*!< FlexBus clock */
287 kCLOCK_FlashClk, /*!< Flash clock */
288 kCLOCK_FastPeriphClk, /*!< Fast peripheral clock */
289 kCLOCK_PllFllSelClk, /*!< The clock after SIM[PLLFLLSEL]. */
290
291 /* ---------------------------------- OSC clock -----------------------------------*/
292 kCLOCK_Er32kClk, /*!< External reference 32K clock (ERCLK32K) */
293 kCLOCK_Osc0ErClk, /*!< OSC0 external reference clock (OSC0ERCLK) */
294 kCLOCK_Osc1ErClk, /*!< OSC1 external reference clock (OSC1ERCLK) */
295 kCLOCK_Osc0ErClkUndiv, /*!< OSC0 external reference undivided clock(OSC0ERCLK_UNDIV). */
296
297 /* ----------------------------- MCG and MCG-Lite clock ---------------------------*/
298 kCLOCK_McgFixedFreqClk, /*!< MCG fixed frequency clock (MCGFFCLK) */
299 kCLOCK_McgInternalRefClk, /*!< MCG internal reference clock (MCGIRCLK) */
300 kCLOCK_McgFllClk, /*!< MCGFLLCLK */
301 kCLOCK_McgPll0Clk, /*!< MCGPLL0CLK */
302 kCLOCK_McgPll1Clk, /*!< MCGPLL1CLK */
303 kCLOCK_McgExtPllClk, /*!< EXT_PLLCLK */
304 kCLOCK_McgPeriphClk, /*!< MCG peripheral clock (MCGPCLK) */
305 kCLOCK_McgIrc48MClk, /*!< MCG IRC48M clock */
306
307 /* --------------------------------- Other clock ----------------------------------*/
308 kCLOCK_LpoClk, /*!< LPO clock */
309
310 } clock_name_t;
311
312 /*! @brief USB clock source definition. */
313 typedef enum _clock_usb_src
314 {
315 kCLOCK_UsbSrcPll0 = SIM_SOPT2_USBSRC(1U) | SIM_SOPT2_PLLFLLSEL(1U), /*!< Use PLL0. */
316 kCLOCK_UsbSrcIrc48M = SIM_SOPT2_USBSRC(1U) | SIM_SOPT2_PLLFLLSEL(3U), /*!< Use IRC48M. */
317 kCLOCK_UsbSrcExt = SIM_SOPT2_USBSRC(0U) /*!< Use USB_CLKIN. */
318 } clock_usb_src_t;
319 /*------------------------------------------------------------------------------
320
321 clock_gate_t definition:
322
323 31 16 0
324 -----------------------------------------------------------------
325 | SIM_SCGC register offset | control bit offset in SCGC |
326 -----------------------------------------------------------------
327
328 For example, the SDHC clock gate is controlled by SIM_SCGC3[17], the
329 SIM_SCGC3 offset in SIM is 0x1030, then kCLOCK_GateSdhc0 is defined as
330
331 kCLOCK_GateSdhc0 = (0x1030 << 16) | 17;
332
333 ------------------------------------------------------------------------------*/
334
335 #define CLK_GATE_REG_OFFSET_SHIFT 16U
336 #define CLK_GATE_REG_OFFSET_MASK 0xFFFF0000U
337 #define CLK_GATE_BIT_SHIFT_SHIFT 0U
338 #define CLK_GATE_BIT_SHIFT_MASK 0x0000FFFFU
339
340 #define CLK_GATE_DEFINE(reg_offset, bit_shift) \
341 ((((reg_offset) << CLK_GATE_REG_OFFSET_SHIFT) & CLK_GATE_REG_OFFSET_MASK) | \
342 (((bit_shift) << CLK_GATE_BIT_SHIFT_SHIFT) & CLK_GATE_BIT_SHIFT_MASK))
343
344 #define CLK_GATE_ABSTRACT_REG_OFFSET(x) (((x)&CLK_GATE_REG_OFFSET_MASK) >> CLK_GATE_REG_OFFSET_SHIFT)
345 #define CLK_GATE_ABSTRACT_BITS_SHIFT(x) (((x)&CLK_GATE_BIT_SHIFT_MASK) >> CLK_GATE_BIT_SHIFT_SHIFT)
346
347 /*! @brief Clock gate name used for CLOCK_EnableClock/CLOCK_DisableClock. */
348 typedef enum _clock_ip_name
349 {
350 kCLOCK_IpInvalid = 0U,
351 kCLOCK_I2c2 = CLK_GATE_DEFINE(0x1028U, 6U),
352 kCLOCK_Uart4 = CLK_GATE_DEFINE(0x1028U, 10U),
353 kCLOCK_Uart5 = CLK_GATE_DEFINE(0x1028U, 11U),
354
355 kCLOCK_Dac0 = CLK_GATE_DEFINE(0x102CU, 12U),
356 kCLOCK_Dac1 = CLK_GATE_DEFINE(0x102CU, 13U),
357
358 kCLOCK_Spi2 = CLK_GATE_DEFINE(0x1030U, 12U),
359 kCLOCK_Sdhc0 = CLK_GATE_DEFINE(0x1030U, 17U),
360 kCLOCK_Ftm3 = CLK_GATE_DEFINE(0x1030U, 25U),
361 kCLOCK_Adc1 = CLK_GATE_DEFINE(0x1030U, 27U),
362
363 kCLOCK_Ewm0 = CLK_GATE_DEFINE(0x1034U, 1U),
364 kCLOCK_Cmt0 = CLK_GATE_DEFINE(0x1034U, 2U),
365 kCLOCK_I2c0 = CLK_GATE_DEFINE(0x1034U, 6U),
366 kCLOCK_I2c1 = CLK_GATE_DEFINE(0x1034U, 7U),
367 kCLOCK_Uart0 = CLK_GATE_DEFINE(0x1034U, 10U),
368 kCLOCK_Uart1 = CLK_GATE_DEFINE(0x1034U, 11U),
369 kCLOCK_Uart2 = CLK_GATE_DEFINE(0x1034U, 12U),
370 kCLOCK_Uart3 = CLK_GATE_DEFINE(0x1034U, 13U),
371 kCLOCK_Usbfs0 = CLK_GATE_DEFINE(0x1034U, 18U),
372 kCLOCK_Cmp0 = CLK_GATE_DEFINE(0x1034U, 19U),
373 kCLOCK_Cmp1 = CLK_GATE_DEFINE(0x1034U, 19U),
374 kCLOCK_Cmp2 = CLK_GATE_DEFINE(0x1034U, 19U),
375 kCLOCK_Vref0 = CLK_GATE_DEFINE(0x1034U, 20U),
376
377 kCLOCK_Lptmr0 = CLK_GATE_DEFINE(0x1038U, 0U),
378 kCLOCK_PortA = CLK_GATE_DEFINE(0x1038U, 9U),
379 kCLOCK_PortB = CLK_GATE_DEFINE(0x1038U, 10U),
380 kCLOCK_PortC = CLK_GATE_DEFINE(0x1038U, 11U),
381 kCLOCK_PortD = CLK_GATE_DEFINE(0x1038U, 12U),
382 kCLOCK_PortE = CLK_GATE_DEFINE(0x1038U, 13U),
383
384 kCLOCK_Ftf0 = CLK_GATE_DEFINE(0x103CU, 0U),
385 kCLOCK_Dmamux0 = CLK_GATE_DEFINE(0x103CU, 1U),
386 kCLOCK_Flexcan0 = CLK_GATE_DEFINE(0x103CU, 4U),
387 kCLOCK_Rnga0 = CLK_GATE_DEFINE(0x103CU, 9U),
388 kCLOCK_Spi0 = CLK_GATE_DEFINE(0x103CU, 12U),
389 kCLOCK_Spi1 = CLK_GATE_DEFINE(0x103CU, 13U),
390 kCLOCK_Sai0 = CLK_GATE_DEFINE(0x103CU, 15U),
391 kCLOCK_Crc0 = CLK_GATE_DEFINE(0x103CU, 18U),
392 kCLOCK_Usbdcd0 = CLK_GATE_DEFINE(0x103CU, 21U),
393 kCLOCK_Pdb0 = CLK_GATE_DEFINE(0x103CU, 22U),
394 kCLOCK_Pit0 = CLK_GATE_DEFINE(0x103CU, 23U),
395 kCLOCK_Ftm0 = CLK_GATE_DEFINE(0x103CU, 24U),
396 kCLOCK_Ftm1 = CLK_GATE_DEFINE(0x103CU, 25U),
397 kCLOCK_Ftm2 = CLK_GATE_DEFINE(0x103CU, 26U),
398 kCLOCK_Adc0 = CLK_GATE_DEFINE(0x103CU, 27U),
399 kCLOCK_Rtc0 = CLK_GATE_DEFINE(0x103CU, 29U),
400
401 kCLOCK_Flexbus0 = CLK_GATE_DEFINE(0x1040U, 0U),
402 kCLOCK_Dma0 = CLK_GATE_DEFINE(0x1040U, 1U),
403 kCLOCK_Sysmpu0 = CLK_GATE_DEFINE(0x1040U, 2U),
404 } clock_ip_name_t;
405
406 /*!@brief SIM configuration structure for clock setting. */
407 typedef struct _sim_clock_config
408 {
409 uint8_t pllFllSel; /*!< PLL/FLL/IRC48M selection. */
410 uint8_t er32kSrc; /*!< ERCLK32K source selection. */
411 uint32_t clkdiv1; /*!< SIM_CLKDIV1. */
412 } sim_clock_config_t;
413
414 /*! @brief OSC work mode. */
415 typedef enum _osc_mode
416 {
417 kOSC_ModeExt = 0U, /*!< Use an external clock. */
418 #if (defined(MCG_C2_EREFS_MASK) && !(defined(MCG_C2_EREFS0_MASK)))
419 kOSC_ModeOscLowPower = MCG_C2_EREFS_MASK, /*!< Oscillator low power. */
420 #else
421 kOSC_ModeOscLowPower = MCG_C2_EREFS0_MASK, /*!< Oscillator low power. */
422 #endif
423 kOSC_ModeOscHighGain = 0U
424 #if (defined(MCG_C2_EREFS_MASK) && !(defined(MCG_C2_EREFS0_MASK)))
425 | MCG_C2_EREFS_MASK
426 #else
427 | MCG_C2_EREFS0_MASK
428 #endif
429 #if (defined(MCG_C2_HGO_MASK) && !(defined(MCG_C2_HGO0_MASK)))
430 | MCG_C2_HGO_MASK, /*!< Oscillator high gain. */
431 #else
432 | MCG_C2_HGO0_MASK, /*!< Oscillator high gain. */
433 #endif
434 } osc_mode_t;
435
436 /*! @brief Oscillator capacitor load setting.*/
437 enum _osc_cap_load
438 {
439 kOSC_Cap2P = OSC_CR_SC2P_MASK, /*!< 2 pF capacitor load */
440 kOSC_Cap4P = OSC_CR_SC4P_MASK, /*!< 4 pF capacitor load */
441 kOSC_Cap8P = OSC_CR_SC8P_MASK, /*!< 8 pF capacitor load */
442 kOSC_Cap16P = OSC_CR_SC16P_MASK /*!< 16 pF capacitor load */
443 };
444
445 /*! @brief OSCERCLK enable mode. */
446 enum _oscer_enable_mode
447 {
448 kOSC_ErClkEnable = OSC_CR_ERCLKEN_MASK, /*!< Enable. */
449 kOSC_ErClkEnableInStop = OSC_CR_EREFSTEN_MASK /*!< Enable in stop mode. */
450 };
451
452 /*! @brief OSC configuration for OSCERCLK. */
453 typedef struct _oscer_config
454 {
455 uint8_t enableMode; /*!< OSCERCLK enable mode. OR'ed value of @ref _oscer_enable_mode. */
456
457 } oscer_config_t;
458
459 /*!
460 * @brief OSC Initialization Configuration Structure
461 *
462 * Defines the configuration data structure to initialize the OSC.
463 * When porting to a new board, set the following members
464 * according to the board setting:
465 * 1. freq: The external frequency.
466 * 2. workMode: The OSC module mode.
467 */
468 typedef struct _osc_config
469 {
470 uint32_t freq; /*!< External clock frequency. */
471 uint8_t capLoad; /*!< Capacitor load setting. */
472 osc_mode_t workMode; /*!< OSC work mode setting. */
473 oscer_config_t oscerConfig; /*!< Configuration for OSCERCLK. */
474 } osc_config_t;
475
476 /*! @brief MCG FLL reference clock source select. */
477 typedef enum _mcg_fll_src
478 {
479 kMCG_FllSrcExternal, /*!< External reference clock is selected */
480 kMCG_FllSrcInternal /*!< The slow internal reference clock is selected */
481 } mcg_fll_src_t;
482
483 /*! @brief MCG internal reference clock select */
484 typedef enum _mcg_irc_mode
485 {
486 kMCG_IrcSlow, /*!< Slow internal reference clock selected */
487 kMCG_IrcFast /*!< Fast internal reference clock selected */
488 } mcg_irc_mode_t;
489
490 /*! @brief MCG DCO Maximum Frequency with 32.768 kHz Reference */
491 typedef enum _mcg_dmx32
492 {
493 kMCG_Dmx32Default, /*!< DCO has a default range of 25% */
494 kMCG_Dmx32Fine /*!< DCO is fine-tuned for maximum frequency with 32.768 kHz reference */
495 } mcg_dmx32_t;
496
497 /*! @brief MCG DCO range select */
498 typedef enum _mcg_drs
499 {
500 kMCG_DrsLow, /*!< Low frequency range */
501 kMCG_DrsMid, /*!< Mid frequency range */
502 kMCG_DrsMidHigh, /*!< Mid-High frequency range */
503 kMCG_DrsHigh /*!< High frequency range */
504 } mcg_drs_t;
505
506 /*! @brief MCG PLL reference clock select */
507 typedef enum _mcg_pll_ref_src
508 {
509 kMCG_PllRefOsc0, /*!< Selects OSC0 as PLL reference clock */
510 kMCG_PllRefOsc1 /*!< Selects OSC1 as PLL reference clock */
511 } mcg_pll_ref_src_t;
512
513 /*! @brief MCGOUT clock source. */
514 typedef enum _mcg_clkout_src
515 {
516 kMCG_ClkOutSrcOut, /*!< Output of the FLL is selected (reset default) */
517 kMCG_ClkOutSrcInternal, /*!< Internal reference clock is selected */
518 kMCG_ClkOutSrcExternal, /*!< External reference clock is selected */
519 } mcg_clkout_src_t;
520
521 /*! @brief MCG Automatic Trim Machine Select */
522 typedef enum _mcg_atm_select
523 {
524 kMCG_AtmSel32k, /*!< 32 kHz Internal Reference Clock selected */
525 kMCG_AtmSel4m /*!< 4 MHz Internal Reference Clock selected */
526 } mcg_atm_select_t;
527
528 /*! @brief MCG OSC Clock Select */
529 typedef enum _mcg_oscsel
530 {
531 kMCG_OscselOsc, /*!< Selects System Oscillator (OSCCLK) */
532 kMCG_OscselRtc, /*!< Selects 32 kHz RTC Oscillator */
533 kMCG_OscselIrc /*!< Selects 48 MHz IRC Oscillator */
534 } mcg_oscsel_t;
535
536 /*! @brief MCG PLLCS select */
537 typedef enum _mcg_pll_clk_select
538 {
539 kMCG_PllClkSelPll0, /*!< PLL0 output clock is selected */
540 kMCG_PllClkSelPll1 /* PLL1 output clock is selected */
541 } mcg_pll_clk_select_t;
542
543 /*! @brief MCG clock monitor mode. */
544 typedef enum _mcg_monitor_mode
545 {
546 kMCG_MonitorNone, /*!< Clock monitor is disabled. */
547 kMCG_MonitorInt, /*!< Trigger interrupt when clock lost. */
548 kMCG_MonitorReset /*!< System reset when clock lost. */
549 } mcg_monitor_mode_t;
550
551 /*! @brief MCG status. */
552 enum
553 {
554 kStatus_MCG_ModeUnreachable = MAKE_STATUS(kStatusGroup_MCG, 0U), /*!< Can't switch to target mode. */
555 kStatus_MCG_ModeInvalid = MAKE_STATUS(kStatusGroup_MCG, 1U), /*!< Current mode invalid for the specific
556 function. */
557 kStatus_MCG_AtmBusClockInvalid = MAKE_STATUS(kStatusGroup_MCG, 2U), /*!< Invalid bus clock for ATM. */
558 kStatus_MCG_AtmDesiredFreqInvalid = MAKE_STATUS(kStatusGroup_MCG, 3U), /*!< Invalid desired frequency for ATM. */
559 kStatus_MCG_AtmIrcUsed = MAKE_STATUS(kStatusGroup_MCG, 4U), /*!< IRC is used when using ATM. */
560 kStatus_MCG_AtmHardwareFail = MAKE_STATUS(kStatusGroup_MCG, 5U), /*!< Hardware fail occurs during ATM. */
561 kStatus_MCG_SourceUsed = MAKE_STATUS(kStatusGroup_MCG, 6U) /*!< Can't change the clock source because
562 it is in use. */
563 };
564
565 /*! @brief MCG status flags. */
566 enum
567 {
568 kMCG_Osc0LostFlag = (1U << 0U), /*!< OSC0 lost. */
569 kMCG_Osc0InitFlag = (1U << 1U), /*!< OSC0 crystal initialized. */
570 kMCG_RtcOscLostFlag = (1U << 4U), /*!< RTC OSC lost. */
571 kMCG_Pll0LostFlag = (1U << 5U), /*!< PLL0 lost. */
572 kMCG_Pll0LockFlag = (1U << 6U), /*!< PLL0 locked. */
573 };
574
575 /*! @brief MCG internal reference clock (MCGIRCLK) enable mode definition. */
576 enum
577 {
578 kMCG_IrclkEnable = MCG_C1_IRCLKEN_MASK, /*!< MCGIRCLK enable. */
579 kMCG_IrclkEnableInStop = MCG_C1_IREFSTEN_MASK /*!< MCGIRCLK enable in stop mode. */
580 };
581
582 /*! @brief MCG PLL clock enable mode definition. */
583 enum
584 {
585 kMCG_PllEnableIndependent = MCG_C5_PLLCLKEN0_MASK, /*!< MCGPLLCLK enable independent of the
586 MCG clock mode. Generally, the PLL
587 is disabled in FLL modes
588 (FEI/FBI/FEE/FBE). Setting the PLL clock
589 enable independent, enables the
590 PLL in the FLL modes. */
591 kMCG_PllEnableInStop = MCG_C5_PLLSTEN0_MASK /*!< MCGPLLCLK enable in STOP mode. */
592 };
593
594 /*! @brief MCG mode definitions */
595 typedef enum _mcg_mode
596 {
597 kMCG_ModeFEI = 0U, /*!< FEI - FLL Engaged Internal */
598 kMCG_ModeFBI, /*!< FBI - FLL Bypassed Internal */
599 kMCG_ModeBLPI, /*!< BLPI - Bypassed Low Power Internal */
600 kMCG_ModeFEE, /*!< FEE - FLL Engaged External */
601 kMCG_ModeFBE, /*!< FBE - FLL Bypassed External */
602 kMCG_ModeBLPE, /*!< BLPE - Bypassed Low Power External */
603 kMCG_ModePBE, /*!< PBE - PLL Bypassed External */
604 kMCG_ModePEE, /*!< PEE - PLL Engaged External */
605 kMCG_ModeError /*!< Unknown mode */
606 } mcg_mode_t;
607
608 /*! @brief MCG PLL configuration. */
609 typedef struct _mcg_pll_config
610 {
611 uint8_t enableMode; /*!< Enable mode. OR'ed value of @ref _mcg_pll_enable_mode. */
612 uint8_t prdiv; /*!< Reference divider PRDIV. */
613 uint8_t vdiv; /*!< VCO divider VDIV. */
614 } mcg_pll_config_t;
615
616 /*! @brief MCG mode change configuration structure
617 *
618 * When porting to a new board, set the following members
619 * according to the board setting:
620 * 1. frdiv: If the FLL uses the external reference clock, set this
621 * value to ensure that the external reference clock divided by frdiv is
622 * in the 31.25 kHz to 39.0625 kHz range.
623 * 2. The PLL reference clock divider PRDIV: PLL reference clock frequency after
624 * PRDIV should be in the FSL_FEATURE_MCG_PLL_REF_MIN to
625 * FSL_FEATURE_MCG_PLL_REF_MAX range.
626 */
627 typedef struct _mcg_config
628 {
629 mcg_mode_t mcgMode; /*!< MCG mode. */
630
631 /* ----------------------- MCGIRCCLK settings ------------------------ */
632 uint8_t irclkEnableMode; /*!< MCGIRCLK enable mode. */
633 mcg_irc_mode_t ircs; /*!< Source, MCG_C2[IRCS]. */
634 uint8_t fcrdiv; /*!< Divider, MCG_SC[FCRDIV]. */
635
636 /* ------------------------ MCG FLL settings ------------------------- */
637 uint8_t frdiv; /*!< Divider MCG_C1[FRDIV]. */
638 mcg_drs_t drs; /*!< DCO range MCG_C4[DRST_DRS]. */
639 mcg_dmx32_t dmx32; /*!< MCG_C4[DMX32]. */
640 mcg_oscsel_t oscsel; /*!< OSC select MCG_C7[OSCSEL]. */
641
642 /* ------------------------ MCG PLL settings ------------------------- */
643 mcg_pll_config_t pll0Config; /*!< MCGPLL0CLK configuration. */
644
645 } mcg_config_t;
646
647 /*******************************************************************************
648 * API
649 ******************************************************************************/
650
651 #if defined(__cplusplus)
652 extern "C" {
653 #endif /* __cplusplus */
654
655 /*!
656 * @brief Enable the clock for specific IP.
657 *
658 * @param name Which clock to enable, see \ref clock_ip_name_t.
659 */
CLOCK_EnableClock(clock_ip_name_t name)660 static inline void CLOCK_EnableClock(clock_ip_name_t name)
661 {
662 uint32_t regAddr = SIM_BASE + CLK_GATE_ABSTRACT_REG_OFFSET((uint32_t)name);
663 (*(volatile uint32_t *)regAddr) |= (1UL << CLK_GATE_ABSTRACT_BITS_SHIFT((uint32_t)name));
664 }
665
666 /*!
667 * @brief Disable the clock for specific IP.
668 *
669 * @param name Which clock to disable, see \ref clock_ip_name_t.
670 */
CLOCK_DisableClock(clock_ip_name_t name)671 static inline void CLOCK_DisableClock(clock_ip_name_t name)
672 {
673 uint32_t regAddr = SIM_BASE + CLK_GATE_ABSTRACT_REG_OFFSET((uint32_t)name);
674 (*(volatile uint32_t *)regAddr) &= ~(1UL << CLK_GATE_ABSTRACT_BITS_SHIFT((uint32_t)name));
675 }
676
677 /*!
678 * @brief Set ERCLK32K source.
679 *
680 * @param src The value to set ERCLK32K clock source.
681 */
CLOCK_SetEr32kClock(uint32_t src)682 static inline void CLOCK_SetEr32kClock(uint32_t src)
683 {
684 SIM->SOPT1 = ((SIM->SOPT1 & ~SIM_SOPT1_OSC32KSEL_MASK) | SIM_SOPT1_OSC32KSEL(src));
685 }
686
687 /*!
688 * @brief Set debug trace clock source.
689 *
690 * @param src The value to set debug trace clock source.
691 */
CLOCK_SetTraceClock(uint32_t src)692 static inline void CLOCK_SetTraceClock(uint32_t src)
693 {
694 SIM->SOPT2 = ((SIM->SOPT2 & ~SIM_SOPT2_TRACECLKSEL_MASK) | SIM_SOPT2_TRACECLKSEL(src));
695 }
696
697 /*!
698 * @brief Set SDHC0 clock source.
699 *
700 * @param src The value to set SDHC0 clock source.
701 */
CLOCK_SetSdhc0Clock(uint32_t src)702 static inline void CLOCK_SetSdhc0Clock(uint32_t src)
703 {
704 SIM->SOPT2 = ((SIM->SOPT2 & ~SIM_SOPT2_SDHCSRC_MASK) | SIM_SOPT2_SDHCSRC(src));
705 }
706
707 /*!
708 * @brief Set PLLFLLSEL clock source.
709 *
710 * @param src The value to set PLLFLLSEL clock source.
711 */
CLOCK_SetPllFllSelClock(uint32_t src)712 static inline void CLOCK_SetPllFllSelClock(uint32_t src)
713 {
714 SIM->SOPT2 = ((SIM->SOPT2 & ~SIM_SOPT2_PLLFLLSEL_MASK) | SIM_SOPT2_PLLFLLSEL(src));
715 }
716
717 /*!
718 * @brief Set CLKOUT source.
719 *
720 * @param src The value to set CLKOUT source.
721 */
CLOCK_SetClkOutClock(uint32_t src)722 static inline void CLOCK_SetClkOutClock(uint32_t src)
723 {
724 SIM->SOPT2 = ((SIM->SOPT2 & ~SIM_SOPT2_CLKOUTSEL_MASK) | SIM_SOPT2_CLKOUTSEL(src));
725 }
726
727 /*!
728 * @brief Set RTC_CLKOUT source.
729 *
730 * @param src The value to set RTC_CLKOUT source.
731 */
CLOCK_SetRtcClkOutClock(uint32_t src)732 static inline void CLOCK_SetRtcClkOutClock(uint32_t src)
733 {
734 SIM->SOPT2 = ((SIM->SOPT2 & ~SIM_SOPT2_RTCCLKOUTSEL_MASK) | SIM_SOPT2_RTCCLKOUTSEL(src));
735 }
736
737 /*! @brief Enable USB FS clock.
738 *
739 * @param src USB FS clock source.
740 * @param freq The frequency specified by src.
741 * @retval true The clock is set successfully.
742 * @retval false The clock source is invalid to get proper USB FS clock.
743 */
744 bool CLOCK_EnableUsbfs0Clock(clock_usb_src_t src, uint32_t freq);
745
746 /*! @brief Disable USB FS clock.
747 *
748 * Disable USB FS clock.
749 */
CLOCK_DisableUsbfs0Clock(void)750 static inline void CLOCK_DisableUsbfs0Clock(void)
751 {
752 CLOCK_DisableClock(kCLOCK_Usbfs0);
753 }
754
755 /*!
756 * @brief System clock divider
757 *
758 * Set the SIM_CLKDIV1[OUTDIV1], SIM_CLKDIV1[OUTDIV2], SIM_CLKDIV1[OUTDIV3], SIM_CLKDIV1[OUTDIV4].
759 *
760 * @param outdiv1 Clock 1 output divider value.
761 *
762 * @param outdiv2 Clock 2 output divider value.
763 *
764 * @param outdiv3 Clock 3 output divider value.
765 *
766 * @param outdiv4 Clock 4 output divider value.
767 */
CLOCK_SetOutDiv(uint32_t outdiv1,uint32_t outdiv2,uint32_t outdiv3,uint32_t outdiv4)768 static inline void CLOCK_SetOutDiv(uint32_t outdiv1, uint32_t outdiv2, uint32_t outdiv3, uint32_t outdiv4)
769 {
770 SIM->CLKDIV1 = SIM_CLKDIV1_OUTDIV1(outdiv1) | SIM_CLKDIV1_OUTDIV2(outdiv2) | SIM_CLKDIV1_OUTDIV3(outdiv3) |
771 SIM_CLKDIV1_OUTDIV4(outdiv4);
772 }
773
774 /*!
775 * @brief Gets the clock frequency for a specific clock name.
776 *
777 * This function checks the current clock configurations and then calculates
778 * the clock frequency for a specific clock name defined in clock_name_t.
779 * The MCG must be properly configured before using this function.
780 *
781 * @param clockName Clock names defined in clock_name_t
782 * @return Clock frequency value in Hertz
783 */
784 uint32_t CLOCK_GetFreq(clock_name_t clockName);
785
786 /*!
787 * @brief Get the core clock or system clock frequency.
788 *
789 * @return Clock frequency in Hz.
790 */
791 uint32_t CLOCK_GetCoreSysClkFreq(void);
792
793 /*!
794 * @brief Get the bus clock frequency.
795 *
796 * @return Clock frequency in Hz.
797 */
798 uint32_t CLOCK_GetBusClkFreq(void);
799
800 /*!
801 * @brief Get the flexbus clock frequency.
802 *
803 * @return Clock frequency in Hz.
804 */
805 uint32_t CLOCK_GetFlexBusClkFreq(void);
806
807 /*!
808 * @brief Get the flash clock frequency.
809 *
810 * @return Clock frequency in Hz.
811 */
812 uint32_t CLOCK_GetFlashClkFreq(void);
813
814 /*!
815 * @brief Get the output clock frequency selected by SIM[PLLFLLSEL].
816 *
817 * @return Clock frequency in Hz.
818 */
819 uint32_t CLOCK_GetPllFllSelClkFreq(void);
820
821 /*!
822 * @brief Get the external reference 32K clock frequency (ERCLK32K).
823 *
824 * @return Clock frequency in Hz.
825 */
826 uint32_t CLOCK_GetEr32kClkFreq(void);
827
828 /*!
829 * @brief Get the OSC0 external reference clock frequency (OSC0ERCLK).
830 *
831 * @return Clock frequency in Hz.
832 */
833 uint32_t CLOCK_GetOsc0ErClkFreq(void);
834
835 /*!
836 * @brief Set the clock configure in SIM module.
837 *
838 * This function sets system layer clock settings in SIM module.
839 *
840 * @param config Pointer to the configure structure.
841 */
842 void CLOCK_SetSimConfig(sim_clock_config_t const *config);
843
844 /*!
845 * @brief Set the system clock dividers in SIM to safe value.
846 *
847 * The system level clocks (core clock, bus clock, flexbus clock and flash clock)
848 * must be in allowed ranges. During MCG clock mode switch, the MCG output clock
849 * changes then the system level clocks may be out of range. This function could
850 * be used before MCG mode change, to make sure system level clocks are in allowed
851 * range.
852 *
853 * @param config Pointer to the configure structure.
854 */
CLOCK_SetSimSafeDivs(void)855 static inline void CLOCK_SetSimSafeDivs(void)
856 {
857 SIM->CLKDIV1 = 0x01040000U;
858 }
859
860 /*! @name MCG frequency functions. */
861 /*@{*/
862
863 /*!
864 * @brief Gets the MCG output clock (MCGOUTCLK) frequency.
865 *
866 * This function gets the MCG output clock frequency in Hz based on the current MCG
867 * register value.
868 *
869 * @return The frequency of MCGOUTCLK.
870 */
871 uint32_t CLOCK_GetOutClkFreq(void);
872
873 /*!
874 * @brief Gets the MCG FLL clock (MCGFLLCLK) frequency.
875 *
876 * This function gets the MCG FLL clock frequency in Hz based on the current MCG
877 * register value. The FLL is enabled in FEI/FBI/FEE/FBE mode and
878 * disabled in low power state in other modes.
879 *
880 * @return The frequency of MCGFLLCLK.
881 */
882 uint32_t CLOCK_GetFllFreq(void);
883
884 /*!
885 * @brief Gets the MCG internal reference clock (MCGIRCLK) frequency.
886 *
887 * This function gets the MCG internal reference clock frequency in Hz based
888 * on the current MCG register value.
889 *
890 * @return The frequency of MCGIRCLK.
891 */
892 uint32_t CLOCK_GetInternalRefClkFreq(void);
893
894 /*!
895 * @brief Gets the MCG fixed frequency clock (MCGFFCLK) frequency.
896 *
897 * This function gets the MCG fixed frequency clock frequency in Hz based
898 * on the current MCG register value.
899 *
900 * @return The frequency of MCGFFCLK.
901 */
902 uint32_t CLOCK_GetFixedFreqClkFreq(void);
903
904 /*!
905 * @brief Gets the MCG PLL0 clock (MCGPLL0CLK) frequency.
906 *
907 * This function gets the MCG PLL0 clock frequency in Hz based on the current MCG
908 * register value.
909 *
910 * @return The frequency of MCGPLL0CLK.
911 */
912 uint32_t CLOCK_GetPll0Freq(void);
913
914 /*@}*/
915
916 /*! @name MCG clock configuration. */
917 /*@{*/
918
919 /*!
920 * @brief Enables or disables the MCG low power.
921 *
922 * Enabling the MCG low power disables the PLL and FLL in bypass modes. In other words,
923 * in FBE and PBE modes, enabling low power sets the MCG to BLPE mode. In FBI and
924 * PBI modes, enabling low power sets the MCG to BLPI mode.
925 * When disabling the MCG low power, the PLL or FLL are enabled based on MCG settings.
926 *
927 * @param enable True to enable MCG low power, false to disable MCG low power.
928 */
CLOCK_SetLowPowerEnable(bool enable)929 static inline void CLOCK_SetLowPowerEnable(bool enable)
930 {
931 if (enable)
932 {
933 MCG->C2 |= MCG_C2_LP_MASK;
934 }
935 else
936 {
937 MCG->C2 &= ~(uint8_t)MCG_C2_LP_MASK;
938 }
939 }
940
941 /*!
942 * @brief Configures the Internal Reference clock (MCGIRCLK).
943 *
944 * This function sets the \c MCGIRCLK base on parameters. It also selects the IRC
945 * source. If the fast IRC is used, this function sets the fast IRC divider.
946 * This function also sets whether the \c MCGIRCLK is enabled in stop mode.
947 * Calling this function in FBI/PBI/BLPI modes may change the system clock. As a result,
948 * using the function in these modes it is not allowed.
949 *
950 * @param enableMode MCGIRCLK enable mode, OR'ed value of @ref _mcg_irclk_enable_mode.
951 * @param ircs MCGIRCLK clock source, choose fast or slow.
952 * @param fcrdiv Fast IRC divider setting (\c FCRDIV).
953 * @retval kStatus_MCG_SourceUsed Because the internal reference clock is used as a clock source,
954 * the configuration should not be changed. Otherwise, a glitch occurs.
955 * @retval kStatus_Success MCGIRCLK configuration finished successfully.
956 */
957 status_t CLOCK_SetInternalRefClkConfig(uint8_t enableMode, mcg_irc_mode_t ircs, uint8_t fcrdiv);
958
959 /*!
960 * @brief Selects the MCG external reference clock.
961 *
962 * Selects the MCG external reference clock source, changes the MCG_C7[OSCSEL],
963 * and waits for the clock source to be stable. Because the external reference
964 * clock should not be changed in FEE/FBE/BLPE/PBE/PEE modes, do not call this function in these modes.
965 *
966 * @param oscsel MCG external reference clock source, MCG_C7[OSCSEL].
967 * @retval kStatus_MCG_SourceUsed Because the external reference clock is used as a clock source,
968 * the configuration should not be changed. Otherwise, a glitch occurs.
969 * @retval kStatus_Success External reference clock set successfully.
970 */
971 status_t CLOCK_SetExternalRefClkConfig(mcg_oscsel_t oscsel);
972
973 /*!
974 * @brief Set the FLL external reference clock divider value.
975 *
976 * Sets the FLL external reference clock divider value, the register MCG_C1[FRDIV].
977 *
978 * @param frdiv The FLL external reference clock divider value, MCG_C1[FRDIV].
979 */
CLOCK_SetFllExtRefDiv(uint8_t frdiv)980 static inline void CLOCK_SetFllExtRefDiv(uint8_t frdiv)
981 {
982 MCG->C1 = (uint8_t)((MCG->C1 & ~MCG_C1_FRDIV_MASK) | MCG_C1_FRDIV(frdiv));
983 }
984
985 /*!
986 * @brief Enables the PLL0 in FLL mode.
987 *
988 * This function sets us the PLL0 in FLL mode and reconfigures
989 * the PLL0. Ensure that the PLL reference
990 * clock is enabled before calling this function and that the PLL0 is not used as a clock source.
991 * The function CLOCK_CalcPllDiv gets the correct PLL
992 * divider values.
993 *
994 * @param config Pointer to the configuration structure.
995 */
996 void CLOCK_EnablePll0(mcg_pll_config_t const *config);
997
998 /*!
999 * @brief Disables the PLL0 in FLL mode.
1000 *
1001 * This function disables the PLL0 in FLL mode. It should be used together with the
1002 * @ref CLOCK_EnablePll0.
1003 */
CLOCK_DisablePll0(void)1004 static inline void CLOCK_DisablePll0(void)
1005 {
1006 MCG->C5 &= (uint8_t)(~(MCG_C5_PLLCLKEN0_MASK | MCG_C5_PLLSTEN0_MASK));
1007 }
1008
1009 /*!
1010 * @brief Calculates the PLL divider setting for a desired output frequency.
1011 *
1012 * This function calculates the correct reference clock divider (\c PRDIV) and
1013 * VCO divider (\c VDIV) to generate a desired PLL output frequency. It returns the
1014 * closest frequency match with the corresponding \c PRDIV/VDIV
1015 * returned from parameters. If a desired frequency is not valid, this function
1016 * returns 0.
1017 *
1018 * @param refFreq PLL reference clock frequency.
1019 * @param desireFreq Desired PLL output frequency.
1020 * @param prdiv PRDIV value to generate desired PLL frequency.
1021 * @param vdiv VDIV value to generate desired PLL frequency.
1022 * @return Closest frequency match that the PLL was able generate.
1023 */
1024 uint32_t CLOCK_CalcPllDiv(uint32_t refFreq, uint32_t desireFreq, uint8_t *prdiv, uint8_t *vdiv);
1025
1026 /*@}*/
1027
1028 /*! @name MCG clock lock monitor functions. */
1029 /*@{*/
1030
1031 /*!
1032 * @brief Sets the OSC0 clock monitor mode.
1033 *
1034 * This function sets the OSC0 clock monitor mode. See @ref mcg_monitor_mode_t for details.
1035 *
1036 * @param mode Monitor mode to set.
1037 */
1038 void CLOCK_SetOsc0MonitorMode(mcg_monitor_mode_t mode);
1039
1040 /*!
1041 * @brief Sets the RTC OSC clock monitor mode.
1042 *
1043 * This function sets the RTC OSC clock monitor mode. See @ref mcg_monitor_mode_t for details.
1044 *
1045 * @param mode Monitor mode to set.
1046 */
1047 void CLOCK_SetRtcOscMonitorMode(mcg_monitor_mode_t mode);
1048
1049 /*!
1050 * @brief Sets the PLL0 clock monitor mode.
1051 *
1052 * This function sets the PLL0 clock monitor mode. See @ref mcg_monitor_mode_t for details.
1053 *
1054 * @param mode Monitor mode to set.
1055 */
1056 void CLOCK_SetPll0MonitorMode(mcg_monitor_mode_t mode);
1057
1058 /*!
1059 * @brief Gets the MCG status flags.
1060 *
1061 * This function gets the MCG clock status flags. All status flags are
1062 * returned as a logical OR of the enumeration @ref _mcg_status_flags_t. To
1063 * check a specific flag, compare the return value with the flag.
1064 *
1065 * Example:
1066 * @code
1067 * To check the clock lost lock status of OSC0 and PLL0.
1068 * uint32_t mcgFlags;
1069 *
1070 * mcgFlags = CLOCK_GetStatusFlags();
1071 *
1072 * if (mcgFlags & kMCG_Osc0LostFlag)
1073 * {
1074 * OSC0 clock lock lost. Do something.
1075 * }
1076 * if (mcgFlags & kMCG_Pll0LostFlag)
1077 * {
1078 * PLL0 clock lock lost. Do something.
1079 * }
1080 * @endcode
1081 *
1082 * @return Logical OR value of the @ref _mcg_status_flags_t.
1083 */
1084 uint32_t CLOCK_GetStatusFlags(void);
1085
1086 /*!
1087 * @brief Clears the MCG status flags.
1088 *
1089 * This function clears the MCG clock lock lost status. The parameter is a logical
1090 * OR value of the flags to clear. See @ref _mcg_status_flags_t.
1091 *
1092 * Example:
1093 * @code
1094 * To clear the clock lost lock status flags of OSC0 and PLL0.
1095 *
1096 * CLOCK_ClearStatusFlags(kMCG_Osc0LostFlag | kMCG_Pll0LostFlag);
1097 * @endcode
1098 *
1099 * @param mask The status flags to clear. This is a logical OR of members of the
1100 * enumeration @ref _mcg_status_flags_t.
1101 */
1102 void CLOCK_ClearStatusFlags(uint32_t mask);
1103
1104 /*@}*/
1105
1106 /*!
1107 * @name OSC configuration
1108 * @{
1109 */
1110
1111 /*!
1112 * @brief Configures the OSC external reference clock (OSCERCLK).
1113 *
1114 * This function configures the OSC external reference clock (OSCERCLK).
1115 * This is an example to enable the OSCERCLK in normal and stop modes and also set
1116 * the output divider to 1:
1117 *
1118 @code
1119 oscer_config_t config =
1120 {
1121 .enableMode = kOSC_ErClkEnable | kOSC_ErClkEnableInStop,
1122 .erclkDiv = 1U,
1123 };
1124
1125 OSC_SetExtRefClkConfig(OSC, &config);
1126 @endcode
1127 *
1128 * @param base OSC peripheral address.
1129 * @param config Pointer to the configuration structure.
1130 */
OSC_SetExtRefClkConfig(OSC_Type * base,oscer_config_t const * config)1131 static inline void OSC_SetExtRefClkConfig(OSC_Type *base, oscer_config_t const *config)
1132 {
1133 uint8_t reg = base->CR;
1134
1135 reg &= (uint8_t)(~(OSC_CR_ERCLKEN_MASK | OSC_CR_EREFSTEN_MASK));
1136 reg |= config->enableMode;
1137
1138 base->CR = reg;
1139 }
1140
1141 /*!
1142 * @brief Sets the capacitor load configuration for the oscillator.
1143 *
1144 * This function sets the specified capacitors configuration for the oscillator.
1145 * This should be done in the early system level initialization function call
1146 * based on the system configuration.
1147 *
1148 * @param base OSC peripheral address.
1149 * @param capLoad OR'ed value for the capacitor load option, see \ref _osc_cap_load.
1150 *
1151 * Example:
1152 @code
1153 To enable only 2 pF and 8 pF capacitor load, please use like this.
1154 OSC_SetCapLoad(OSC, kOSC_Cap2P | kOSC_Cap8P);
1155 @endcode
1156 */
OSC_SetCapLoad(OSC_Type * base,uint8_t capLoad)1157 static inline void OSC_SetCapLoad(OSC_Type *base, uint8_t capLoad)
1158 {
1159 uint8_t reg = base->CR;
1160
1161 reg &= (uint8_t)(~(OSC_CR_SC2P_MASK | OSC_CR_SC4P_MASK | OSC_CR_SC8P_MASK | OSC_CR_SC16P_MASK));
1162 reg |= capLoad;
1163
1164 base->CR = reg;
1165 }
1166
1167 /*!
1168 * @brief Initializes the OSC0.
1169 *
1170 * This function initializes the OSC0 according to the board configuration.
1171 *
1172 * @param config Pointer to the OSC0 configuration structure.
1173 */
1174 void CLOCK_InitOsc0(osc_config_t const *config);
1175
1176 /*!
1177 * @brief Deinitializes the OSC0.
1178 *
1179 * This function deinitializes the OSC0.
1180 */
1181 void CLOCK_DeinitOsc0(void);
1182
1183 /* @} */
1184
1185 /*!
1186 * @name External clock frequency
1187 * @{
1188 */
1189
1190 /*!
1191 * @brief Sets the XTAL0 frequency based on board settings.
1192 *
1193 * @param freq The XTAL0/EXTAL0 input clock frequency in Hz.
1194 */
CLOCK_SetXtal0Freq(uint32_t freq)1195 static inline void CLOCK_SetXtal0Freq(uint32_t freq)
1196 {
1197 g_xtal0Freq = freq;
1198 }
1199
1200 /*!
1201 * @brief Sets the XTAL32/RTC_CLKIN frequency based on board settings.
1202 *
1203 * @param freq The XTAL32/EXTAL32/RTC_CLKIN input clock frequency in Hz.
1204 */
CLOCK_SetXtal32Freq(uint32_t freq)1205 static inline void CLOCK_SetXtal32Freq(uint32_t freq)
1206 {
1207 g_xtal32Freq = freq;
1208 }
1209 /* @} */
1210
1211 /*!
1212 * @name IRCs frequency
1213 * @{
1214 */
1215
1216 /*!
1217 * @brief Set the Slow IRC frequency based on the trimmed value
1218 *
1219 * @param freq The Slow IRC frequency input clock frequency in Hz.
1220 */
1221 void CLOCK_SetSlowIrcFreq(uint32_t freq);
1222
1223 /*!
1224 * @brief Set the Fast IRC frequency based on the trimmed value
1225 *
1226 * @param freq The Fast IRC frequency input clock frequency in Hz.
1227 */
1228 void CLOCK_SetFastIrcFreq(uint32_t freq);
1229 /* @} */
1230
1231 /*!
1232 * @name MCG auto-trim machine.
1233 * @{
1234 */
1235
1236 /*!
1237 * @brief Auto trims the internal reference clock.
1238 *
1239 * This function trims the internal reference clock by using the external clock. If
1240 * successful, it returns the kStatus_Success and the frequency after
1241 * trimming is received in the parameter @p actualFreq. If an error occurs,
1242 * the error code is returned.
1243 *
1244 * @param extFreq External clock frequency, which should be a bus clock.
1245 * @param desireFreq Frequency to trim to.
1246 * @param actualFreq Actual frequency after trimming.
1247 * @param atms Trim fast or slow internal reference clock.
1248 * @retval kStatus_Success ATM success.
1249 * @retval kStatus_MCG_AtmBusClockInvalid The bus clock is not in allowed range for the ATM.
1250 * @retval kStatus_MCG_AtmDesiredFreqInvalid MCGIRCLK could not be trimmed to the desired frequency.
1251 * @retval kStatus_MCG_AtmIrcUsed Could not trim because MCGIRCLK is used as a bus clock source.
1252 * @retval kStatus_MCG_AtmHardwareFail Hardware fails while trimming.
1253 */
1254 status_t CLOCK_TrimInternalRefClk(uint32_t extFreq, uint32_t desireFreq, uint32_t *actualFreq, mcg_atm_select_t atms);
1255 /* @} */
1256
1257 /*! @name MCG mode functions. */
1258 /*@{*/
1259
1260 /*!
1261 * @brief Gets the current MCG mode.
1262 *
1263 * This function checks the MCG registers and determines the current MCG mode.
1264 *
1265 * @return Current MCG mode or error code; See @ref mcg_mode_t.
1266 */
1267 mcg_mode_t CLOCK_GetMode(void);
1268
1269 /*!
1270 * @brief Sets the MCG to FEI mode.
1271 *
1272 * This function sets the MCG to FEI mode. If setting to FEI mode fails
1273 * from the current mode, this function returns an error.
1274 *
1275 * @param dmx32 DMX32 in FEI mode.
1276 * @param drs The DCO range selection.
1277 * @param fllStableDelay Delay function to ensure that the FLL is stable. Passing
1278 * NULL does not cause a delay.
1279 * @retval kStatus_MCG_ModeUnreachable Could not switch to the target mode.
1280 * @retval kStatus_Success Switched to the target mode successfully.
1281 * @note If @p dmx32 is set to kMCG_Dmx32Fine, the slow IRC must not be trimmed
1282 * to a frequency above 32768 Hz.
1283 */
1284 status_t CLOCK_SetFeiMode(mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDelay)(void));
1285
1286 /*!
1287 * @brief Sets the MCG to FEE mode.
1288 *
1289 * This function sets the MCG to FEE mode. If setting to FEE mode fails
1290 * from the current mode, this function returns an error.
1291 *
1292 * @param frdiv FLL reference clock divider setting, FRDIV.
1293 * @param dmx32 DMX32 in FEE mode.
1294 * @param drs The DCO range selection.
1295 * @param fllStableDelay Delay function to make sure FLL is stable. Passing
1296 * NULL does not cause a delay.
1297 *
1298 * @retval kStatus_MCG_ModeUnreachable Could not switch to the target mode.
1299 * @retval kStatus_Success Switched to the target mode successfully.
1300 */
1301 status_t CLOCK_SetFeeMode(uint8_t frdiv, mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDelay)(void));
1302
1303 /*!
1304 * @brief Sets the MCG to FBI mode.
1305 *
1306 * This function sets the MCG to FBI mode. If setting to FBI mode fails
1307 * from the current mode, this function returns an error.
1308 *
1309 * @param dmx32 DMX32 in FBI mode.
1310 * @param drs The DCO range selection.
1311 * @param fllStableDelay Delay function to make sure FLL is stable. If the FLL
1312 * is not used in FBI mode, this parameter can be NULL. Passing
1313 * NULL does not cause a delay.
1314 * @retval kStatus_MCG_ModeUnreachable Could not switch to the target mode.
1315 * @retval kStatus_Success Switched to the target mode successfully.
1316 * @note If @p dmx32 is set to kMCG_Dmx32Fine, the slow IRC must not be trimmed
1317 * to frequency above 32768 Hz.
1318 */
1319 status_t CLOCK_SetFbiMode(mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDelay)(void));
1320
1321 /*!
1322 * @brief Sets the MCG to FBE mode.
1323 *
1324 * This function sets the MCG to FBE mode. If setting to FBE mode fails
1325 * from the current mode, this function returns an error.
1326 *
1327 * @param frdiv FLL reference clock divider setting, FRDIV.
1328 * @param dmx32 DMX32 in FBE mode.
1329 * @param drs The DCO range selection.
1330 * @param fllStableDelay Delay function to make sure FLL is stable. If the FLL
1331 * is not used in FBE mode, this parameter can be NULL. Passing NULL
1332 * does not cause a delay.
1333 * @retval kStatus_MCG_ModeUnreachable Could not switch to the target mode.
1334 * @retval kStatus_Success Switched to the target mode successfully.
1335 */
1336 status_t CLOCK_SetFbeMode(uint8_t frdiv, mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDelay)(void));
1337
1338 /*!
1339 * @brief Sets the MCG to BLPI mode.
1340 *
1341 * This function sets the MCG to BLPI mode. If setting to BLPI mode fails
1342 * from the current mode, this function returns an error.
1343 *
1344 * @retval kStatus_MCG_ModeUnreachable Could not switch to the target mode.
1345 * @retval kStatus_Success Switched to the target mode successfully.
1346 */
1347 status_t CLOCK_SetBlpiMode(void);
1348
1349 /*!
1350 * @brief Sets the MCG to BLPE mode.
1351 *
1352 * This function sets the MCG to BLPE mode. If setting to BLPE mode fails
1353 * from the current mode, this function returns an error.
1354 *
1355 * @retval kStatus_MCG_ModeUnreachable Could not switch to the target mode.
1356 * @retval kStatus_Success Switched to the target mode successfully.
1357 */
1358 status_t CLOCK_SetBlpeMode(void);
1359
1360 /*!
1361 * @brief Sets the MCG to PBE mode.
1362 *
1363 * This function sets the MCG to PBE mode. If setting to PBE mode fails
1364 * from the current mode, this function returns an error.
1365 *
1366 * @param pllcs The PLL selection, PLLCS.
1367 * @param config Pointer to the PLL configuration.
1368 * @retval kStatus_MCG_ModeUnreachable Could not switch to the target mode.
1369 * @retval kStatus_Success Switched to the target mode successfully.
1370 *
1371 * @note
1372 * 1. The parameter \c pllcs selects the PLL. For platforms with
1373 * only one PLL, the parameter pllcs is kept for interface compatibility.
1374 * 2. The parameter \c config is the PLL configuration structure. On some
1375 * platforms, it is possible to choose the external PLL directly, which renders the
1376 * configuration structure not necessary. In this case, pass in NULL.
1377 * For example: CLOCK_SetPbeMode(kMCG_OscselOsc, kMCG_PllClkSelExtPll, NULL);
1378 */
1379 status_t CLOCK_SetPbeMode(mcg_pll_clk_select_t pllcs, mcg_pll_config_t const *config);
1380
1381 /*!
1382 * @brief Sets the MCG to PEE mode.
1383 *
1384 * This function sets the MCG to PEE mode.
1385 *
1386 * @retval kStatus_MCG_ModeUnreachable Could not switch to the target mode.
1387 * @retval kStatus_Success Switched to the target mode successfully.
1388 *
1389 * @note This function only changes the CLKS to use the PLL/FLL output. If the
1390 * PRDIV/VDIV are different than in the PBE mode, set them up
1391 * in PBE mode and wait. When the clock is stable, switch to PEE mode.
1392 */
1393 status_t CLOCK_SetPeeMode(void);
1394
1395 /*!
1396 * @brief Switches the MCG to FBE mode from the external mode.
1397 *
1398 * This function switches the MCG from external modes (PEE/PBE/BLPE/FEE) to the FBE mode quickly.
1399 * The external clock is used as the system clock source and PLL is disabled. However,
1400 * the FLL settings are not configured. This is a lite function with a small code size, which is useful
1401 * during the mode switch. For example, to switch from PEE mode to FEI mode:
1402 *
1403 * @code
1404 * CLOCK_ExternalModeToFbeModeQuick();
1405 * CLOCK_SetFeiMode(...);
1406 * @endcode
1407 *
1408 * @retval kStatus_Success Switched successfully.
1409 * @retval kStatus_MCG_ModeInvalid If the current mode is not an external mode, do not call this function.
1410 */
1411 status_t CLOCK_ExternalModeToFbeModeQuick(void);
1412
1413 /*!
1414 * @brief Switches the MCG to FBI mode from internal modes.
1415 *
1416 * This function switches the MCG from internal modes (PEI/PBI/BLPI/FEI) to the FBI mode quickly.
1417 * The MCGIRCLK is used as the system clock source and PLL is disabled. However,
1418 * FLL settings are not configured. This is a lite function with a small code size, which is useful
1419 * during the mode switch. For example, to switch from PEI mode to FEE mode:
1420 *
1421 * @code
1422 * CLOCK_InternalModeToFbiModeQuick();
1423 * CLOCK_SetFeeMode(...);
1424 * @endcode
1425 *
1426 * @retval kStatus_Success Switched successfully.
1427 * @retval kStatus_MCG_ModeInvalid If the current mode is not an internal mode, do not call this function.
1428 */
1429 status_t CLOCK_InternalModeToFbiModeQuick(void);
1430
1431 /*!
1432 * @brief Sets the MCG to FEI mode during system boot up.
1433 *
1434 * This function sets the MCG to FEI mode from the reset mode. It can also be used to
1435 * set up MCG during system boot up.
1436 *
1437 * @param dmx32 DMX32 in FEI mode.
1438 * @param drs The DCO range selection.
1439 * @param fllStableDelay Delay function to ensure that the FLL is stable.
1440 *
1441 * @retval kStatus_MCG_ModeUnreachable Could not switch to the target mode.
1442 * @retval kStatus_Success Switched to the target mode successfully.
1443 * @note If @p dmx32 is set to kMCG_Dmx32Fine, the slow IRC must not be trimmed
1444 * to frequency above 32768 Hz.
1445 */
1446 status_t CLOCK_BootToFeiMode(mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDelay)(void));
1447
1448 /*!
1449 * @brief Sets the MCG to FEE mode during system bootup.
1450 *
1451 * This function sets MCG to FEE mode from the reset mode. It can also be used to
1452 * set up the MCG during system boot up.
1453 *
1454 * @param oscsel OSC clock select, OSCSEL.
1455 * @param frdiv FLL reference clock divider setting, FRDIV.
1456 * @param dmx32 DMX32 in FEE mode.
1457 * @param drs The DCO range selection.
1458 * @param fllStableDelay Delay function to ensure that the FLL is stable.
1459 *
1460 * @retval kStatus_MCG_ModeUnreachable Could not switch to the target mode.
1461 * @retval kStatus_Success Switched to the target mode successfully.
1462 */
1463 status_t CLOCK_BootToFeeMode(
1464 mcg_oscsel_t oscsel, uint8_t frdiv, mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDelay)(void));
1465
1466 /*!
1467 * @brief Sets the MCG to BLPI mode during system boot up.
1468 *
1469 * This function sets the MCG to BLPI mode from the reset mode. It can also be used to
1470 * set up the MCG during system boot up.
1471 *
1472 * @param fcrdiv Fast IRC divider, FCRDIV.
1473 * @param ircs The internal reference clock to select, IRCS.
1474 * @param ircEnableMode The MCGIRCLK enable mode, OR'ed value of @ref _mcg_irclk_enable_mode.
1475 *
1476 * @retval kStatus_MCG_SourceUsed Could not change MCGIRCLK setting.
1477 * @retval kStatus_Success Switched to the target mode successfully.
1478 */
1479 status_t CLOCK_BootToBlpiMode(uint8_t fcrdiv, mcg_irc_mode_t ircs, uint8_t ircEnableMode);
1480
1481 /*!
1482 * @brief Sets the MCG to BLPE mode during system boot up.
1483 *
1484 * This function sets the MCG to BLPE mode from the reset mode. It can also be used to
1485 * set up the MCG during system boot up.
1486 *
1487 * @param oscsel OSC clock select, MCG_C7[OSCSEL].
1488 *
1489 * @retval kStatus_MCG_ModeUnreachable Could not switch to the target mode.
1490 * @retval kStatus_Success Switched to the target mode successfully.
1491 */
1492 status_t CLOCK_BootToBlpeMode(mcg_oscsel_t oscsel);
1493
1494 /*!
1495 * @brief Sets the MCG to PEE mode during system boot up.
1496 *
1497 * This function sets the MCG to PEE mode from reset mode. It can also be used to
1498 * set up the MCG during system boot up.
1499 *
1500 * @param oscsel OSC clock select, MCG_C7[OSCSEL].
1501 * @param pllcs The PLL selection, PLLCS.
1502 * @param config Pointer to the PLL configuration.
1503 *
1504 * @retval kStatus_MCG_ModeUnreachable Could not switch to the target mode.
1505 * @retval kStatus_Success Switched to the target mode successfully.
1506 */
1507 status_t CLOCK_BootToPeeMode(mcg_oscsel_t oscsel, mcg_pll_clk_select_t pllcs, mcg_pll_config_t const *config);
1508
1509 /*!
1510 * @brief Sets the MCG to a target mode.
1511 *
1512 * This function sets MCG to a target mode defined by the configuration
1513 * structure. If switching to the target mode fails, this function
1514 * chooses the correct path.
1515 *
1516 * @param config Pointer to the target MCG mode configuration structure.
1517 * @return Return kStatus_Success if switched successfully; Otherwise, it returns an error code #_mcg_status.
1518 *
1519 * @note If the external clock is used in the target mode, ensure that it is
1520 * enabled. For example, if the OSC0 is used, set up OSC0 correctly before calling this
1521 * function.
1522 */
1523 status_t CLOCK_SetMcgConfig(mcg_config_t const *config);
1524
1525 /*@}*/
1526
1527 #if defined(__cplusplus)
1528 }
1529 #endif /* __cplusplus */
1530
1531 /*! @} */
1532
1533 #endif /* _FSL_CLOCK_H_ */
1534
