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Searched refs:FTM_QDCTRL_PHAFLTREN_MASK (Results 1 – 25 of 63) sorted by relevance

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/hal_nxp-3.6.0/s32/drivers/s32k1/BaseNXP/header/
DS32K146_FTM.h989 #define FTM_QDCTRL_PHAFLTREN_MASK (0x80U) macro
992 … (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_PHAFLTREN_SHIFT)) & FTM_QDCTRL_PHAFLTREN_MASK)
DS32K144W_FTM.h981 #define FTM_QDCTRL_PHAFLTREN_MASK (0x80U) macro
984 … (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_PHAFLTREN_SHIFT)) & FTM_QDCTRL_PHAFLTREN_MASK)
DS32K144_FTM.h977 #define FTM_QDCTRL_PHAFLTREN_MASK (0x80U) macro
980 … (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_PHAFLTREN_SHIFT)) & FTM_QDCTRL_PHAFLTREN_MASK)
DS32K118_FTM.h973 #define FTM_QDCTRL_PHAFLTREN_MASK (0x80U) macro
976 … (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_PHAFLTREN_SHIFT)) & FTM_QDCTRL_PHAFLTREN_MASK)
DS32K116_FTM.h973 #define FTM_QDCTRL_PHAFLTREN_MASK (0x80U) macro
976 … (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_PHAFLTREN_SHIFT)) & FTM_QDCTRL_PHAFLTREN_MASK)
DS32K142W_FTM.h981 #define FTM_QDCTRL_PHAFLTREN_MASK (0x80U) macro
984 … (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_PHAFLTREN_SHIFT)) & FTM_QDCTRL_PHAFLTREN_MASK)
DS32K142_FTM.h981 #define FTM_QDCTRL_PHAFLTREN_MASK (0x80U) macro
984 … (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_PHAFLTREN_SHIFT)) & FTM_QDCTRL_PHAFLTREN_MASK)
DS32K148_FTM.h997 #define FTM_QDCTRL_PHAFLTREN_MASK (0x80U) macro
1000 … (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_PHAFLTREN_SHIFT)) & FTM_QDCTRL_PHAFLTREN_MASK)
/hal_nxp-3.6.0/mcux/mcux-sdk/drivers/ftm/
Dfsl_ftm.c1005 …reg &= ~(FTM_QDCTRL_QUADMODE_MASK | FTM_QDCTRL_PHAFLTREN_MASK | FTM_QDCTRL_PHBFLTREN_MASK | FTM_QD… in FTM_SetupQuadDecode()
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MK02F12810/
DMK02F12810.h4618 #define FTM_QDCTRL_PHAFLTREN_MASK (0x80U) macro
4624 … (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_PHAFLTREN_SHIFT)) & FTM_QDCTRL_PHAFLTREN_MASK)
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MKE14Z4/
DMKE14Z4.h2931 #define FTM_QDCTRL_PHAFLTREN_MASK (0x80U) macro
2937 … (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_PHAFLTREN_SHIFT)) & FTM_QDCTRL_PHAFLTREN_MASK)
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MKV30F12810/
DMKV30F12810.h4623 #define FTM_QDCTRL_PHAFLTREN_MASK (0x80U) macro
4629 … (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_PHAFLTREN_SHIFT)) & FTM_QDCTRL_PHAFLTREN_MASK)
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MKV10Z7/
DMKV10Z7.h4049 #define FTM_QDCTRL_PHAFLTREN_MASK (0x80U) macro
4055 … (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_PHAFLTREN_SHIFT)) & FTM_QDCTRL_PHAFLTREN_MASK)
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MKV10Z1287/
DMKV10Z1287.h4525 #define FTM_QDCTRL_PHAFLTREN_MASK (0x80U) macro
4531 … (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_PHAFLTREN_SHIFT)) & FTM_QDCTRL_PHAFLTREN_MASK)
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MKV31F12810/
DMKV31F12810.h4650 #define FTM_QDCTRL_PHAFLTREN_MASK (0x80U) macro
4656 … (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_PHAFLTREN_SHIFT)) & FTM_QDCTRL_PHAFLTREN_MASK)
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MKE15Z4/
DMKE15Z4.h2932 #define FTM_QDCTRL_PHAFLTREN_MASK (0x80U) macro
2938 … (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_PHAFLTREN_SHIFT)) & FTM_QDCTRL_PHAFLTREN_MASK)
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MKE16Z4/
DMKE16Z4.h2930 #define FTM_QDCTRL_PHAFLTREN_MASK (0x80U) macro
2936 … (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_PHAFLTREN_SHIFT)) & FTM_QDCTRL_PHAFLTREN_MASK)
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MKV11Z7/
DMKV11Z7.h5313 #define FTM_QDCTRL_PHAFLTREN_MASK (0x80U) macro
5319 … (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_PHAFLTREN_SHIFT)) & FTM_QDCTRL_PHAFLTREN_MASK)
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MKV31F25612/
DMKV31F25612.h5413 #define FTM_QDCTRL_PHAFLTREN_MASK (0x80U) macro
5419 … (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_PHAFLTREN_SHIFT)) & FTM_QDCTRL_PHAFLTREN_MASK)
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MKV31F51212/
DMKV31F51212.h5655 #define FTM_QDCTRL_PHAFLTREN_MASK (0x80U) macro
5661 … (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_PHAFLTREN_SHIFT)) & FTM_QDCTRL_PHAFLTREN_MASK)
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MK22F12810/
DMK22F12810.h4654 #define FTM_QDCTRL_PHAFLTREN_MASK (0x80U) macro
4660 … (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_PHAFLTREN_SHIFT)) & FTM_QDCTRL_PHAFLTREN_MASK)
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MKE15Z7/
DMKE15Z7.h5440 #define FTM_QDCTRL_PHAFLTREN_MASK (0x80U) macro
5446 … (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_PHAFLTREN_SHIFT)) & FTM_QDCTRL_PHAFLTREN_MASK)
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MKE14Z7/
DMKE14Z7.h5438 #define FTM_QDCTRL_PHAFLTREN_MASK (0x80U) macro
5444 … (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_PHAFLTREN_SHIFT)) & FTM_QDCTRL_PHAFLTREN_MASK)
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MK22F25612/
DMK22F25612.h5421 #define FTM_QDCTRL_PHAFLTREN_MASK (0x80U) macro
5427 … (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_PHAFLTREN_SHIFT)) & FTM_QDCTRL_PHAFLTREN_MASK)
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MK22F51212/
DMK22F51212.h5673 #define FTM_QDCTRL_PHAFLTREN_MASK (0x80U) macro
5679 … (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_PHAFLTREN_SHIFT)) & FTM_QDCTRL_PHAFLTREN_MASK)

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