/hal_nxp-3.6.0/s32/drivers/s32k1/BaseNXP/header/ |
D | S32K146_FTM.h | 989 #define FTM_QDCTRL_PHAFLTREN_MASK (0x80U) macro 992 … (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_PHAFLTREN_SHIFT)) & FTM_QDCTRL_PHAFLTREN_MASK)
|
D | S32K144W_FTM.h | 981 #define FTM_QDCTRL_PHAFLTREN_MASK (0x80U) macro 984 … (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_PHAFLTREN_SHIFT)) & FTM_QDCTRL_PHAFLTREN_MASK)
|
D | S32K144_FTM.h | 977 #define FTM_QDCTRL_PHAFLTREN_MASK (0x80U) macro 980 … (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_PHAFLTREN_SHIFT)) & FTM_QDCTRL_PHAFLTREN_MASK)
|
D | S32K118_FTM.h | 973 #define FTM_QDCTRL_PHAFLTREN_MASK (0x80U) macro 976 … (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_PHAFLTREN_SHIFT)) & FTM_QDCTRL_PHAFLTREN_MASK)
|
D | S32K116_FTM.h | 973 #define FTM_QDCTRL_PHAFLTREN_MASK (0x80U) macro 976 … (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_PHAFLTREN_SHIFT)) & FTM_QDCTRL_PHAFLTREN_MASK)
|
D | S32K142W_FTM.h | 981 #define FTM_QDCTRL_PHAFLTREN_MASK (0x80U) macro 984 … (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_PHAFLTREN_SHIFT)) & FTM_QDCTRL_PHAFLTREN_MASK)
|
D | S32K142_FTM.h | 981 #define FTM_QDCTRL_PHAFLTREN_MASK (0x80U) macro 984 … (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_PHAFLTREN_SHIFT)) & FTM_QDCTRL_PHAFLTREN_MASK)
|
D | S32K148_FTM.h | 997 #define FTM_QDCTRL_PHAFLTREN_MASK (0x80U) macro 1000 … (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_PHAFLTREN_SHIFT)) & FTM_QDCTRL_PHAFLTREN_MASK)
|
/hal_nxp-3.6.0/mcux/mcux-sdk/drivers/ftm/ |
D | fsl_ftm.c | 1005 …reg &= ~(FTM_QDCTRL_QUADMODE_MASK | FTM_QDCTRL_PHAFLTREN_MASK | FTM_QDCTRL_PHBFLTREN_MASK | FTM_QD… in FTM_SetupQuadDecode()
|
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MK02F12810/ |
D | MK02F12810.h | 4618 #define FTM_QDCTRL_PHAFLTREN_MASK (0x80U) macro 4624 … (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_PHAFLTREN_SHIFT)) & FTM_QDCTRL_PHAFLTREN_MASK)
|
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MKE14Z4/ |
D | MKE14Z4.h | 2931 #define FTM_QDCTRL_PHAFLTREN_MASK (0x80U) macro 2937 … (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_PHAFLTREN_SHIFT)) & FTM_QDCTRL_PHAFLTREN_MASK)
|
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MKV30F12810/ |
D | MKV30F12810.h | 4623 #define FTM_QDCTRL_PHAFLTREN_MASK (0x80U) macro 4629 … (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_PHAFLTREN_SHIFT)) & FTM_QDCTRL_PHAFLTREN_MASK)
|
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MKV10Z7/ |
D | MKV10Z7.h | 4049 #define FTM_QDCTRL_PHAFLTREN_MASK (0x80U) macro 4055 … (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_PHAFLTREN_SHIFT)) & FTM_QDCTRL_PHAFLTREN_MASK)
|
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MKV10Z1287/ |
D | MKV10Z1287.h | 4525 #define FTM_QDCTRL_PHAFLTREN_MASK (0x80U) macro 4531 … (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_PHAFLTREN_SHIFT)) & FTM_QDCTRL_PHAFLTREN_MASK)
|
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MKV31F12810/ |
D | MKV31F12810.h | 4650 #define FTM_QDCTRL_PHAFLTREN_MASK (0x80U) macro 4656 … (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_PHAFLTREN_SHIFT)) & FTM_QDCTRL_PHAFLTREN_MASK)
|
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MKE15Z4/ |
D | MKE15Z4.h | 2932 #define FTM_QDCTRL_PHAFLTREN_MASK (0x80U) macro 2938 … (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_PHAFLTREN_SHIFT)) & FTM_QDCTRL_PHAFLTREN_MASK)
|
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MKE16Z4/ |
D | MKE16Z4.h | 2930 #define FTM_QDCTRL_PHAFLTREN_MASK (0x80U) macro 2936 … (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_PHAFLTREN_SHIFT)) & FTM_QDCTRL_PHAFLTREN_MASK)
|
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MKV11Z7/ |
D | MKV11Z7.h | 5313 #define FTM_QDCTRL_PHAFLTREN_MASK (0x80U) macro 5319 … (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_PHAFLTREN_SHIFT)) & FTM_QDCTRL_PHAFLTREN_MASK)
|
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MKV31F25612/ |
D | MKV31F25612.h | 5413 #define FTM_QDCTRL_PHAFLTREN_MASK (0x80U) macro 5419 … (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_PHAFLTREN_SHIFT)) & FTM_QDCTRL_PHAFLTREN_MASK)
|
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MKV31F51212/ |
D | MKV31F51212.h | 5655 #define FTM_QDCTRL_PHAFLTREN_MASK (0x80U) macro 5661 … (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_PHAFLTREN_SHIFT)) & FTM_QDCTRL_PHAFLTREN_MASK)
|
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MK22F12810/ |
D | MK22F12810.h | 4654 #define FTM_QDCTRL_PHAFLTREN_MASK (0x80U) macro 4660 … (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_PHAFLTREN_SHIFT)) & FTM_QDCTRL_PHAFLTREN_MASK)
|
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MKE15Z7/ |
D | MKE15Z7.h | 5440 #define FTM_QDCTRL_PHAFLTREN_MASK (0x80U) macro 5446 … (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_PHAFLTREN_SHIFT)) & FTM_QDCTRL_PHAFLTREN_MASK)
|
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MKE14Z7/ |
D | MKE14Z7.h | 5438 #define FTM_QDCTRL_PHAFLTREN_MASK (0x80U) macro 5444 … (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_PHAFLTREN_SHIFT)) & FTM_QDCTRL_PHAFLTREN_MASK)
|
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MK22F25612/ |
D | MK22F25612.h | 5421 #define FTM_QDCTRL_PHAFLTREN_MASK (0x80U) macro 5427 … (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_PHAFLTREN_SHIFT)) & FTM_QDCTRL_PHAFLTREN_MASK)
|
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MK22F51212/ |
D | MK22F51212.h | 5673 #define FTM_QDCTRL_PHAFLTREN_MASK (0x80U) macro 5679 … (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_PHAFLTREN_SHIFT)) & FTM_QDCTRL_PHAFLTREN_MASK)
|