1 /* 2 ** ################################################################### 3 ** Processors: MKV11Z128VFM7 4 ** MKV11Z128VLC7 5 ** MKV11Z128VLF7 6 ** MKV11Z128VLH7 7 ** MKV11Z64VFM7 8 ** MKV11Z64VLC7 9 ** MKV11Z64VLF7 10 ** MKV11Z64VLH7 11 ** 12 ** Compilers: Keil ARM C/C++ Compiler 13 ** Freescale C/C++ for Embedded ARM 14 ** GNU C Compiler 15 ** IAR ANSI C/C++ Compiler for ARM 16 ** MCUXpresso Compiler 17 ** 18 ** Reference manual: KV11P64M75RM Rev.2, April 2015 19 ** Version: rev. 1.1, 2017-03-22 20 ** Build: b180801 21 ** 22 ** Abstract: 23 ** CMSIS Peripheral Access Layer for MKV11Z7 24 ** 25 ** Copyright 1997-2016 Freescale Semiconductor, Inc. 26 ** Copyright 2016-2018 NXP 27 ** 28 ** SPDX-License-Identifier: BSD-3-Clause 29 ** 30 ** http: www.nxp.com 31 ** mail: support@nxp.com 32 ** 33 ** Revisions: 34 ** - rev. 1.0 (2014-12-14) 35 ** Initial version. 36 ** - rev. 1.1 (2017-03-22) 37 ** Corrected missing CAN0Rx DMA request. 38 ** 39 ** ################################################################### 40 */ 41 42 /*! 43 * @file MKV11Z7.h 44 * @version 1.1 45 * @date 2017-03-22 46 * @brief CMSIS Peripheral Access Layer for MKV11Z7 47 * 48 * CMSIS Peripheral Access Layer for MKV11Z7 49 */ 50 51 #ifndef _MKV11Z7_H_ 52 #define _MKV11Z7_H_ /**< Symbol preventing repeated inclusion */ 53 54 /** Memory map major version (memory maps with equal major version number are 55 * compatible) */ 56 #define MCU_MEM_MAP_VERSION 0x0100U 57 /** Memory map minor version */ 58 #define MCU_MEM_MAP_VERSION_MINOR 0x0001U 59 60 61 /* ---------------------------------------------------------------------------- 62 -- Interrupt vector numbers 63 ---------------------------------------------------------------------------- */ 64 65 /*! 66 * @addtogroup Interrupt_vector_numbers Interrupt vector numbers 67 * @{ 68 */ 69 70 /** Interrupt Number Definitions */ 71 #define NUMBER_OF_INT_VECTORS 48 /**< Number of interrupts in the Vector table */ 72 73 typedef enum IRQn { 74 /* Auxiliary constants */ 75 NotAvail_IRQn = -128, /**< Not available device specific interrupt */ 76 77 /* Core interrupts */ 78 NonMaskableInt_IRQn = -14, /**< Non Maskable Interrupt */ 79 HardFault_IRQn = -13, /**< Cortex-M0 SV Hard Fault Interrupt */ 80 SVCall_IRQn = -5, /**< Cortex-M0 SV Call Interrupt */ 81 PendSV_IRQn = -2, /**< Cortex-M0 Pend SV Interrupt */ 82 SysTick_IRQn = -1, /**< Cortex-M0 System Tick Interrupt */ 83 84 /* Device specific interrupts */ 85 DMA0_DMA4_IRQn = 0, /**< DMA channel 0 and 4 transfer complete */ 86 DMA1_DMA5_IRQn = 1, /**< DMA channel 1 and 5 transfer complete */ 87 DMA2_DMA6_IRQn = 2, /**< DMA channel 2 and 6 transfer complete */ 88 DMA3_DMA7_IRQn = 3, /**< DMA channel 2 and 7 transfer complete */ 89 DMA_Error_IRQn = 4, /**< DMA error interrupt channels 0-7 */ 90 FTFA_IRQn = 5, /**< FTFA command complete and read collision */ 91 LVD_LVW_IRQn = 6, /**< Low-voltage detect, low-voltage warning */ 92 LLWU_IRQn = 7, /**< Low Leakage Wakeup */ 93 I2C0_IRQn = 8, /**< I2C0 interrupt */ 94 Reserved25_IRQn = 9, /**< Reserved interrupt */ 95 SPI0_IRQn = 10, /**< SPI0 single interrupt vector for all sources */ 96 Reserved27_IRQn = 11, /**< Reserved interrupt */ 97 UART0_IRQn = 12, /**< UART0 status and error */ 98 UART1_IRQn = 13, /**< UART1 status and error */ 99 CAN0_IRQn = 14, /**< CAN0 interrupt */ 100 ADC0_IRQn = 15, /**< ADC0 interrupt */ 101 ADC1_IRQn = 16, /**< ADC1 interrupt */ 102 FTM0_IRQn = 17, /**< FTM0 single interrupt vector for all sources */ 103 FTM1_IRQn = 18, /**< FTM1 single interrupt vector for all sources */ 104 FTM2_IRQn = 19, /**< FTM2 single interrupt vector for all sources */ 105 CMP0_IRQn = 20, /**< CMP0 interrupt */ 106 CMP1_IRQn = 21, /**< CMP1 interrupt */ 107 FTM3_IRQn = 22, /**< FTM3 single interrupt vector for all sources */ 108 WDOG_EWM_IRQn = 23, /**< Single interrupt vector for WDOG and EWM */ 109 FTM4_IRQn = 24, /**< FTM4 single interrupt vector for all sources */ 110 DAC0_IRQn = 25, /**< DAC0 interrupt */ 111 FTM5_IRQn = 26, /**< FTM5 single interrupt vector for all sources */ 112 MCG_IRQn = 27, /**< MCG interrupt */ 113 LPTMR0_IRQn = 28, /**< LPTMR0 interrupt */ 114 PDB0_PDB1_IRQn = 29, /**< Single interrupt vector for PDB0 and PDB1 */ 115 PORTA_IRQn = 30, /**< PORTA pin detect */ 116 PORTB_PORTC_PORTD_PORTE_IRQn = 31 /**< Single interrupt vector for PORTB, PORTC, PORTD and PORTE pin detect */ 117 } IRQn_Type; 118 119 /*! 120 * @} 121 */ /* end of group Interrupt_vector_numbers */ 122 123 124 /* ---------------------------------------------------------------------------- 125 -- Cortex M0 Core Configuration 126 ---------------------------------------------------------------------------- */ 127 128 /*! 129 * @addtogroup Cortex_Core_Configuration Cortex M0 Core Configuration 130 * @{ 131 */ 132 133 #define __CM0PLUS_REV 0x0000 /**< Core revision r0p0 */ 134 #define __MPU_PRESENT 0 /**< Defines if an MPU is present or not */ 135 #define __VTOR_PRESENT 1 /**< Defines if VTOR is present or not */ 136 #define __NVIC_PRIO_BITS 2 /**< Number of priority bits implemented in the NVIC */ 137 #define __Vendor_SysTickConfig 0 /**< Vendor specific implementation of SysTickConfig is defined */ 138 139 #include "core_cm0plus.h" /* Core Peripheral Access Layer */ 140 #include "system_MKV11Z7.h" /* Device specific configuration file */ 141 142 /*! 143 * @} 144 */ /* end of group Cortex_Core_Configuration */ 145 146 147 /* ---------------------------------------------------------------------------- 148 -- Mapping Information 149 ---------------------------------------------------------------------------- */ 150 151 /*! 152 * @addtogroup Mapping_Information Mapping Information 153 * @{ 154 */ 155 156 /** Mapping Information */ 157 /*! 158 * @addtogroup edma_request 159 * @{ 160 */ 161 162 /******************************************************************************* 163 * Definitions 164 ******************************************************************************/ 165 166 /*! 167 * @brief Structure for the DMA hardware request 168 * 169 * Defines the structure for the DMA hardware request collections. The user can configure the 170 * hardware request into DMAMUX to trigger the DMA transfer accordingly. The index 171 * of the hardware request varies according to the to SoC. 172 */ 173 typedef enum _dma_request_source 174 { 175 kDmaRequestMux0Disable = 0|0x100U, /**< DMAMUX TriggerDisabled. */ 176 kDmaRequestMux0Reserved1 = 1|0x100U, /**< Reserved1 */ 177 kDmaRequestMux0UART0Rx = 2|0x100U, /**< UART 0 receive complete */ 178 kDmaRequestMux0UART0Tx = 3|0x100U, /**< UART 0 transmit complete */ 179 kDmaRequestMux0UART1Rx = 4|0x100U, /**< UART 1 receive complete */ 180 kDmaRequestMux0UART1Tx = 5|0x100U, /**< UART 1 transmit complete */ 181 kDmaRequestMux0Reserved6 = 6|0x100U, /**< Reserved6 */ 182 kDmaRequestMux0Reserved7 = 7|0x100U, /**< Reserved7 */ 183 kDmaRequestMux0Reserved8 = 8|0x100U, /**< Reserved8 */ 184 kDmaRequestMux0Reserved9 = 9|0x100U, /**< Reserved9 */ 185 kDmaRequestMux0Reserved10 = 10|0x100U, /**< Reserved10 */ 186 kDmaRequestMux0Reserved11 = 11|0x100U, /**< Reserved11 */ 187 kDmaRequestMux0Reserved12 = 12|0x100U, /**< Reserved12 */ 188 kDmaRequestMux0Reserved13 = 13|0x100U, /**< Reserved13 */ 189 kDmaRequestMux0CAN0Rx = 14|0x100U, /**< FlexCAN0 Receive buffer full */ 190 kDmaRequestMux0Reserved15 = 15|0x100U, /**< Reserved15 */ 191 kDmaRequestMux0SPI0Rx = 16|0x100U, /**< SPI0 receive complete */ 192 kDmaRequestMux0SPI0Tx = 17|0x100U, /**< SPI0 transmit complete */ 193 kDmaRequestMux0Reserved18 = 18|0x100U, /**< Reserved18 */ 194 kDmaRequestMux0Reserved19 = 19|0x100U, /**< Reserved19 */ 195 kDmaRequestMux0Reserved20 = 20|0x100U, /**< Reserved20 */ 196 kDmaRequestMux0Reserved21 = 21|0x100U, /**< Reserved21 */ 197 kDmaRequestMux0I2C0 = 22|0x100U, /**< I2C0 transmission complete */ 198 kDmaRequestMux0Reserved23 = 23|0x100U, /**< Reserved23 */ 199 kDmaRequestMux0FTM0Channel0 = 24|0x100U, /**< FTM0 channel 0 event (CMP or CAP) */ 200 kDmaRequestMux0FTM0Channel1 = 25|0x100U, /**< FTM0 channel 1 event (CMP or CAP) */ 201 kDmaRequestMux0FTM0Channel2 = 26|0x100U, /**< FTM0 channel 2 event (CMP or CAP) */ 202 kDmaRequestMux0FTM0Channel3 = 27|0x100U, /**< FTM0 channel 3 event (CMP or CAP) */ 203 kDmaRequestMux0FTM0Channel4 = 28|0x100U, /**< FTM0 channel 4 event (CMP or CAP) */ 204 kDmaRequestMux0FTM0Channel5 = 29|0x100U, /**< FTM0 channel 5 event (CMP or CAP) */ 205 kDmaRequestMux0FTM4Channel0 = 30|0x100U, /**< FTM4 channel 0 event (CMP or CAP) */ 206 kDmaRequestMux0FTM4Channel1 = 31|0x100U, /**< FTM4 channel 1 event (CMP or CAP) */ 207 kDmaRequestMux0FTM1Channel0 = 32|0x100U, /**< FTM1 channel 0 event (CMP or CAP) */ 208 kDmaRequestMux0FTM1Channel1 = 33|0x100U, /**< FTM1 channel 1 event (CMP or CAP) */ 209 kDmaRequestMux0FTM2Channel0 = 34|0x100U, /**< FTM2 channel 0 event (CMP or CAP) */ 210 kDmaRequestMux0FTM2Channel1 = 35|0x100U, /**< FTM2 channel 1 event (CMP or CAP) */ 211 kDmaRequestMux0FTM3Channel0 = 36|0x100U, /**< FTM3 channel 0 event (CMP or CAP) */ 212 kDmaRequestMux0FTM3Channel1 = 37|0x100U, /**< FTM3 channel 1 event (CMP or CAP) */ 213 kDmaRequestMux0FTM3Channel2 = 38|0x100U, /**< FTM3 channel 2 event (CMP or CAP) */ 214 kDmaRequestMux0FTM3Channel3 = 39|0x100U, /**< FTM3 channel 3 event (CMP or CAP) */ 215 kDmaRequestMux0ADC0 = 40|0x100U, /**< ADC 0 conversion complete */ 216 kDmaRequestMux0ADC1 = 41|0x100U, /**< ADC 1 conversion complete */ 217 kDmaRequestMux0CMP0 = 42|0x100U, /**< CMP0 Output */ 218 kDmaRequestMux0CMP1 = 43|0x100U, /**< CMP1 Output */ 219 kDmaRequestMux0Reserved44 = 44|0x100U, /**< Reserved44 */ 220 kDmaRequestMux0DAC0 = 45|0x100U, /**< DAC0 buffer pointer reaches upper or lower limit */ 221 kDmaRequestMux0Reserved46 = 46|0x100U, /**< Reserved46 */ 222 kDmaRequestMux0PDB1 = 47|0x100U, /**< PDB1 programmable interrupt delay event */ 223 kDmaRequestMux0PDB0 = 48|0x100U, /**< PDB0 programmable interrupt delay event */ 224 kDmaRequestMux0PortA = 49|0x100U, /**< PORTA rising, falling or both edges */ 225 kDmaRequestMux0PortB = 50|0x100U, /**< PORTB rising, falling or both edges */ 226 kDmaRequestMux0PortC = 51|0x100U, /**< PORTC rising, falling or both edges */ 227 kDmaRequestMux0PortD = 52|0x100U, /**< PORTD rising, falling or both edges */ 228 kDmaRequestMux0PortE = 53|0x100U, /**< PORTE rising, falling or both edges */ 229 kDmaRequestMux0FTM3Channel4 = 54|0x100U, /**< FTM3 channel 4 event (CMP or CAP) */ 230 kDmaRequestMux0FTM3Channel5 = 55|0x100U, /**< FTM3 channel 5 event (CMP or CAP) */ 231 kDmaRequestMux0FTM5Channel0 = 56|0x100U, /**< FTM5 channel 0 event (CMP or CAP) */ 232 kDmaRequestMux0FTM5Channel1 = 57|0x100U, /**< FTM5 channel 1 event (CMP or CAP) */ 233 kDmaRequestMux0AlwaysOn58 = 58|0x100U, /**< DMAMUX Always Enabled slot. */ 234 kDmaRequestMux0AlwaysOn59 = 59|0x100U, /**< DMAMUX Always Enabled slot. */ 235 kDmaRequestMux0AlwaysOn60 = 60|0x100U, /**< DMAMUX Always Enabled slot. */ 236 kDmaRequestMux0AlwaysOn61 = 61|0x100U, /**< DMAMUX Always Enabled slot. */ 237 kDmaRequestMux0AlwaysOn62 = 62|0x100U, /**< DMAMUX Always Enabled slot. */ 238 kDmaRequestMux0AlwaysOn63 = 63|0x100U, /**< DMAMUX Always Enabled slot. */ 239 } dma_request_source_t; 240 241 /* @} */ 242 243 244 /*! 245 * @} 246 */ /* end of group Mapping_Information */ 247 248 249 /* ---------------------------------------------------------------------------- 250 -- Device Peripheral Access Layer 251 ---------------------------------------------------------------------------- */ 252 253 /*! 254 * @addtogroup Peripheral_access_layer Device Peripheral Access Layer 255 * @{ 256 */ 257 258 259 /* 260 ** Start of section using anonymous unions 261 */ 262 263 #if defined(__ARMCC_VERSION) 264 #if (__ARMCC_VERSION >= 6010050) 265 #pragma clang diagnostic push 266 #else 267 #pragma push 268 #pragma anon_unions 269 #endif 270 #elif defined(__CWCC__) 271 #pragma push 272 #pragma cpp_extensions on 273 #elif defined(__GNUC__) 274 /* anonymous unions are enabled by default */ 275 #elif defined(__IAR_SYSTEMS_ICC__) 276 #pragma language=extended 277 #else 278 #error Not supported compiler type 279 #endif 280 281 /* ---------------------------------------------------------------------------- 282 -- ADC Peripheral Access Layer 283 ---------------------------------------------------------------------------- */ 284 285 /*! 286 * @addtogroup ADC_Peripheral_Access_Layer ADC Peripheral Access Layer 287 * @{ 288 */ 289 290 /** ADC - Register Layout Typedef */ 291 typedef struct { 292 __IO uint32_t SC1[2]; /**< ADC Status and Control Registers 1, array offset: 0x0, array step: 0x4 */ 293 __IO uint32_t CFG1; /**< ADC Configuration Register 1, offset: 0x8 */ 294 __IO uint32_t CFG2; /**< ADC Configuration Register 2, offset: 0xC */ 295 __I uint32_t R[2]; /**< ADC Data Result Register, array offset: 0x10, array step: 0x4 */ 296 __IO uint32_t CV1; /**< Compare Value Registers, offset: 0x18 */ 297 __IO uint32_t CV2; /**< Compare Value Registers, offset: 0x1C */ 298 __IO uint32_t SC2; /**< Status and Control Register 2, offset: 0x20 */ 299 __IO uint32_t SC3; /**< Status and Control Register 3, offset: 0x24 */ 300 __IO uint32_t OFS; /**< ADC Offset Correction Register, offset: 0x28 */ 301 __IO uint32_t PG; /**< ADC Plus-Side Gain Register, offset: 0x2C */ 302 __IO uint32_t MG; /**< ADC Minus-Side Gain Register, offset: 0x30 */ 303 __IO uint32_t CLPD; /**< ADC Plus-Side General Calibration Value Register, offset: 0x34 */ 304 __IO uint32_t CLPS; /**< ADC Plus-Side General Calibration Value Register, offset: 0x38 */ 305 __IO uint32_t CLP4; /**< ADC Plus-Side General Calibration Value Register, offset: 0x3C */ 306 __IO uint32_t CLP3; /**< ADC Plus-Side General Calibration Value Register, offset: 0x40 */ 307 __IO uint32_t CLP2; /**< ADC Plus-Side General Calibration Value Register, offset: 0x44 */ 308 __IO uint32_t CLP1; /**< ADC Plus-Side General Calibration Value Register, offset: 0x48 */ 309 __IO uint32_t CLP0; /**< ADC Plus-Side General Calibration Value Register, offset: 0x4C */ 310 uint8_t RESERVED_0[4]; 311 __IO uint32_t CLMD; /**< ADC Minus-Side General Calibration Value Register, offset: 0x54 */ 312 __IO uint32_t CLMS; /**< ADC Minus-Side General Calibration Value Register, offset: 0x58 */ 313 __IO uint32_t CLM4; /**< ADC Minus-Side General Calibration Value Register, offset: 0x5C */ 314 __IO uint32_t CLM3; /**< ADC Minus-Side General Calibration Value Register, offset: 0x60 */ 315 __IO uint32_t CLM2; /**< ADC Minus-Side General Calibration Value Register, offset: 0x64 */ 316 __IO uint32_t CLM1; /**< ADC Minus-Side General Calibration Value Register, offset: 0x68 */ 317 __IO uint32_t CLM0; /**< ADC Minus-Side General Calibration Value Register, offset: 0x6C */ 318 } ADC_Type; 319 320 /* ---------------------------------------------------------------------------- 321 -- ADC Register Masks 322 ---------------------------------------------------------------------------- */ 323 324 /*! 325 * @addtogroup ADC_Register_Masks ADC Register Masks 326 * @{ 327 */ 328 329 /*! @name SC1 - ADC Status and Control Registers 1 */ 330 /*! @{ */ 331 #define ADC_SC1_ADCH_MASK (0x1FU) 332 #define ADC_SC1_ADCH_SHIFT (0U) 333 /*! ADCH - Input channel select 334 * 0b00000..When DIFF=0, DADP0 is selected as input; when DIFF=1, DAD0 is selected as input. 335 * 0b00001..When DIFF=0, DADP1 is selected as input; when DIFF=1, DAD1 is selected as input. 336 * 0b00010..When DIFF=0, DADP2 is selected as input; when DIFF=1, DAD2 is selected as input. 337 * 0b00011..When DIFF=0, DADP3 is selected as input; when DIFF=1, DAD3 is selected as input. 338 * 0b00100..When DIFF=0, AD4 is selected as input; when DIFF=1, it is reserved. 339 * 0b00101..When DIFF=0, AD5 is selected as input; when DIFF=1, it is reserved. 340 * 0b00110..When DIFF=0, AD6 is selected as input; when DIFF=1, it is reserved. 341 * 0b00111..When DIFF=0, AD7 is selected as input; when DIFF=1, it is reserved. 342 * 0b01000..When DIFF=0, AD8 is selected as input; when DIFF=1, it is reserved. 343 * 0b01001..When DIFF=0, AD9 is selected as input; when DIFF=1, it is reserved. 344 * 0b01010..When DIFF=0, AD10 is selected as input; when DIFF=1, it is reserved. 345 * 0b01011..When DIFF=0, AD11 is selected as input; when DIFF=1, it is reserved. 346 * 0b01100..When DIFF=0, AD12 is selected as input; when DIFF=1, it is reserved. 347 * 0b01101..When DIFF=0, AD13 is selected as input; when DIFF=1, it is reserved. 348 * 0b01110..When DIFF=0, AD14 is selected as input; when DIFF=1, it is reserved. 349 * 0b01111..When DIFF=0, AD15 is selected as input; when DIFF=1, it is reserved. 350 * 0b10000..When DIFF=0, AD16 is selected as input; when DIFF=1, it is reserved. 351 * 0b10001..When DIFF=0, AD17 is selected as input; when DIFF=1, it is reserved. 352 * 0b10010..When DIFF=0, AD18 is selected as input; when DIFF=1, it is reserved. 353 * 0b10011..When DIFF=0, AD19 is selected as input; when DIFF=1, it is reserved. 354 * 0b10100..When DIFF=0, AD20 is selected as input; when DIFF=1, it is reserved. 355 * 0b10101..When DIFF=0, AD21 is selected as input; when DIFF=1, it is reserved. 356 * 0b10110..When DIFF=0, AD22 is selected as input; when DIFF=1, it is reserved. 357 * 0b10111..When DIFF=0, AD23 is selected as input; when DIFF=1, it is reserved. 358 * 0b11000..Reserved. 359 * 0b11001..Reserved. 360 * 0b11010..When DIFF=0, Temp Sensor (single-ended) is selected as input; when DIFF=1, Temp Sensor (differential) is selected as input. 361 * 0b11011..When DIFF=0, Bandgap (single-ended) is selected as input; when DIFF=1, Bandgap (differential) is selected as input. 362 * 0b11100..Reserved. 363 * 0b11101..When DIFF=0,VREFSH is selected as input; when DIFF=1, -VREFSH (differential) is selected as input. Voltage reference selected is determined by SC2[REFSEL]. 364 * 0b11110..When DIFF=0,VREFSL is selected as input; when DIFF=1, it is reserved. Voltage reference selected is determined by SC2[REFSEL]. 365 * 0b11111..Module is disabled. 366 */ 367 #define ADC_SC1_ADCH(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC1_ADCH_SHIFT)) & ADC_SC1_ADCH_MASK) 368 #define ADC_SC1_DIFF_MASK (0x20U) 369 #define ADC_SC1_DIFF_SHIFT (5U) 370 /*! DIFF - Differential Mode Enable 371 * 0b0..Single-ended conversions and input channels are selected. 372 * 0b1..Differential conversions and input channels are selected. 373 */ 374 #define ADC_SC1_DIFF(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC1_DIFF_SHIFT)) & ADC_SC1_DIFF_MASK) 375 #define ADC_SC1_AIEN_MASK (0x40U) 376 #define ADC_SC1_AIEN_SHIFT (6U) 377 /*! AIEN - Interrupt Enable 378 * 0b0..Conversion complete interrupt is disabled. 379 * 0b1..Conversion complete interrupt is enabled. 380 */ 381 #define ADC_SC1_AIEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC1_AIEN_SHIFT)) & ADC_SC1_AIEN_MASK) 382 #define ADC_SC1_COCO_MASK (0x80U) 383 #define ADC_SC1_COCO_SHIFT (7U) 384 /*! COCO - Conversion Complete Flag 385 * 0b0..Conversion is not completed. 386 * 0b1..Conversion is completed. 387 */ 388 #define ADC_SC1_COCO(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC1_COCO_SHIFT)) & ADC_SC1_COCO_MASK) 389 /*! @} */ 390 391 /* The count of ADC_SC1 */ 392 #define ADC_SC1_COUNT (2U) 393 394 /*! @name CFG1 - ADC Configuration Register 1 */ 395 /*! @{ */ 396 #define ADC_CFG1_ADICLK_MASK (0x3U) 397 #define ADC_CFG1_ADICLK_SHIFT (0U) 398 /*! ADICLK - Input Clock Select 399 * 0b00..Bus clock 400 * 0b01..Bus clock divided by 2(BUSCLK/2) 401 * 0b10..Alternate clock (ALTCLK) 402 * 0b11..Asynchronous clock (ADACK) 403 */ 404 #define ADC_CFG1_ADICLK(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG1_ADICLK_SHIFT)) & ADC_CFG1_ADICLK_MASK) 405 #define ADC_CFG1_MODE_MASK (0xCU) 406 #define ADC_CFG1_MODE_SHIFT (2U) 407 /*! MODE - Conversion mode selection 408 * 0b00..When DIFF=0:It is single-ended 8-bit conversion; when DIFF=1, it is differential 9-bit conversion with 2's complement output. 409 * 0b01..When DIFF=0:It is single-ended 12-bit conversion ; when DIFF=1, it is differential 13-bit conversion with 2's complement output. 410 * 0b10..When DIFF=0:It is single-ended 10-bit conversion. ; when DIFF=1, it is differential 11-bit conversion with 2's complement output 411 * 0b11..When DIFF=0:It is single-ended 16-bit conversion..; when DIFF=1, it is differential 16-bit conversion with 2's complement output 412 */ 413 #define ADC_CFG1_MODE(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG1_MODE_SHIFT)) & ADC_CFG1_MODE_MASK) 414 #define ADC_CFG1_ADLSMP_MASK (0x10U) 415 #define ADC_CFG1_ADLSMP_SHIFT (4U) 416 /*! ADLSMP - Sample Time Configuration 417 * 0b0..Short sample time. 418 * 0b1..Long sample time. 419 */ 420 #define ADC_CFG1_ADLSMP(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG1_ADLSMP_SHIFT)) & ADC_CFG1_ADLSMP_MASK) 421 #define ADC_CFG1_ADIV_MASK (0x60U) 422 #define ADC_CFG1_ADIV_SHIFT (5U) 423 /*! ADIV - Clock Divide Select 424 * 0b00..The divide ratio is 1 and the clock rate is input clock. 425 * 0b01..The divide ratio is 2 and the clock rate is (input clock)/2. 426 * 0b10..The divide ratio is 4 and the clock rate is (input clock)/4. 427 * 0b11..The divide ratio is 8 and the clock rate is (input clock)/8. 428 */ 429 #define ADC_CFG1_ADIV(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG1_ADIV_SHIFT)) & ADC_CFG1_ADIV_MASK) 430 #define ADC_CFG1_ADLPC_MASK (0x80U) 431 #define ADC_CFG1_ADLPC_SHIFT (7U) 432 /*! ADLPC - Low-Power Configuration 433 * 0b0..Normal power configuration. 434 * 0b1..Low-power configuration. The power is reduced at the expense of maximum clock speed. 435 */ 436 #define ADC_CFG1_ADLPC(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG1_ADLPC_SHIFT)) & ADC_CFG1_ADLPC_MASK) 437 /*! @} */ 438 439 /*! @name CFG2 - ADC Configuration Register 2 */ 440 /*! @{ */ 441 #define ADC_CFG2_ADLSTS_MASK (0x3U) 442 #define ADC_CFG2_ADLSTS_SHIFT (0U) 443 /*! ADLSTS - Long Sample Time Select 444 * 0b00..Default longest sample time; 20 extra ADCK cycles; 24 ADCK cycles total. 445 * 0b01..12 extra ADCK cycles; 16 ADCK cycles total sample time. 446 * 0b10..6 extra ADCK cycles; 10 ADCK cycles total sample time. 447 * 0b11..2 extra ADCK cycles; 6 ADCK cycles total sample time. 448 */ 449 #define ADC_CFG2_ADLSTS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG2_ADLSTS_SHIFT)) & ADC_CFG2_ADLSTS_MASK) 450 #define ADC_CFG2_ADHSC_MASK (0x4U) 451 #define ADC_CFG2_ADHSC_SHIFT (2U) 452 /*! ADHSC - High-Speed Configuration 453 * 0b0..Normal conversion sequence selected. 454 * 0b1..High-speed conversion sequence selected with 2 additional ADCK cycles to total conversion time. 455 */ 456 #define ADC_CFG2_ADHSC(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG2_ADHSC_SHIFT)) & ADC_CFG2_ADHSC_MASK) 457 #define ADC_CFG2_ADACKEN_MASK (0x8U) 458 #define ADC_CFG2_ADACKEN_SHIFT (3U) 459 /*! ADACKEN - Asynchronous Clock Output Enable 460 * 0b0..Asynchronous clock output disabled; Asynchronous clock is enabled only if selected by ADICLK and a conversion is active. 461 * 0b1..Asynchronous clock and clock output is enabled regardless of the state of the ADC. 462 */ 463 #define ADC_CFG2_ADACKEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG2_ADACKEN_SHIFT)) & ADC_CFG2_ADACKEN_MASK) 464 /*! @} */ 465 466 /*! @name R - ADC Data Result Register */ 467 /*! @{ */ 468 #define ADC_R_D_MASK (0xFFFFU) 469 #define ADC_R_D_SHIFT (0U) 470 #define ADC_R_D(x) (((uint32_t)(((uint32_t)(x)) << ADC_R_D_SHIFT)) & ADC_R_D_MASK) 471 /*! @} */ 472 473 /* The count of ADC_R */ 474 #define ADC_R_COUNT (2U) 475 476 /*! @name CV1 - Compare Value Registers */ 477 /*! @{ */ 478 #define ADC_CV1_CV_MASK (0xFFFFU) 479 #define ADC_CV1_CV_SHIFT (0U) 480 #define ADC_CV1_CV(x) (((uint32_t)(((uint32_t)(x)) << ADC_CV1_CV_SHIFT)) & ADC_CV1_CV_MASK) 481 /*! @} */ 482 483 /*! @name CV2 - Compare Value Registers */ 484 /*! @{ */ 485 #define ADC_CV2_CV_MASK (0xFFFFU) 486 #define ADC_CV2_CV_SHIFT (0U) 487 #define ADC_CV2_CV(x) (((uint32_t)(((uint32_t)(x)) << ADC_CV2_CV_SHIFT)) & ADC_CV2_CV_MASK) 488 /*! @} */ 489 490 /*! @name SC2 - Status and Control Register 2 */ 491 /*! @{ */ 492 #define ADC_SC2_REFSEL_MASK (0x3U) 493 #define ADC_SC2_REFSEL_SHIFT (0U) 494 /*! REFSEL - Voltage Reference Selection 495 * 0b00..Default voltage reference pin pair, that is, external pins VREFH and VREFL 496 * 0b01..Alternate reference pair, that is, VALTH and VALTL . This pair may be additional external pins or internal sources depending on the MCU configuration. See the chip configuration information for details specific to this MCU 497 * 0b10..Reserved 498 * 0b11..Reserved 499 */ 500 #define ADC_SC2_REFSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_REFSEL_SHIFT)) & ADC_SC2_REFSEL_MASK) 501 #define ADC_SC2_DMAEN_MASK (0x4U) 502 #define ADC_SC2_DMAEN_SHIFT (2U) 503 /*! DMAEN - DMA Enable 504 * 0b0..DMA is disabled. 505 * 0b1..DMA is enabled and will assert the ADC DMA request during an ADC conversion complete event noted when any of the SC1n[COCO] flags is asserted. 506 */ 507 #define ADC_SC2_DMAEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_DMAEN_SHIFT)) & ADC_SC2_DMAEN_MASK) 508 #define ADC_SC2_ACREN_MASK (0x8U) 509 #define ADC_SC2_ACREN_SHIFT (3U) 510 /*! ACREN - Compare Function Range Enable 511 * 0b0..Range function disabled. Only CV1 is compared. 512 * 0b1..Range function enabled. Both CV1 and CV2 are compared. 513 */ 514 #define ADC_SC2_ACREN(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_ACREN_SHIFT)) & ADC_SC2_ACREN_MASK) 515 #define ADC_SC2_ACFGT_MASK (0x10U) 516 #define ADC_SC2_ACFGT_SHIFT (4U) 517 /*! ACFGT - Compare Function Greater Than Enable 518 * 0b0..Configures less than threshold, outside range not inclusive and inside range not inclusive; functionality based on the values placed in CV1 and CV2. 519 * 0b1..Configures greater than or equal to threshold, outside and inside ranges inclusive; functionality based on the values placed in CV1 and CV2. 520 */ 521 #define ADC_SC2_ACFGT(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_ACFGT_SHIFT)) & ADC_SC2_ACFGT_MASK) 522 #define ADC_SC2_ACFE_MASK (0x20U) 523 #define ADC_SC2_ACFE_SHIFT (5U) 524 /*! ACFE - Compare Function Enable 525 * 0b0..Compare function disabled. 526 * 0b1..Compare function enabled. 527 */ 528 #define ADC_SC2_ACFE(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_ACFE_SHIFT)) & ADC_SC2_ACFE_MASK) 529 #define ADC_SC2_ADTRG_MASK (0x40U) 530 #define ADC_SC2_ADTRG_SHIFT (6U) 531 /*! ADTRG - Conversion Trigger Select 532 * 0b0..Software trigger selected. 533 * 0b1..Hardware trigger selected. 534 */ 535 #define ADC_SC2_ADTRG(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_ADTRG_SHIFT)) & ADC_SC2_ADTRG_MASK) 536 #define ADC_SC2_ADACT_MASK (0x80U) 537 #define ADC_SC2_ADACT_SHIFT (7U) 538 /*! ADACT - Conversion Active 539 * 0b0..Conversion not in progress. 540 * 0b1..Conversion in progress. 541 */ 542 #define ADC_SC2_ADACT(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_ADACT_SHIFT)) & ADC_SC2_ADACT_MASK) 543 /*! @} */ 544 545 /*! @name SC3 - Status and Control Register 3 */ 546 /*! @{ */ 547 #define ADC_SC3_AVGS_MASK (0x3U) 548 #define ADC_SC3_AVGS_SHIFT (0U) 549 /*! AVGS - Hardware Average Select 550 * 0b00..4 samples averaged. 551 * 0b01..8 samples averaged. 552 * 0b10..16 samples averaged. 553 * 0b11..32 samples averaged. 554 */ 555 #define ADC_SC3_AVGS(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC3_AVGS_SHIFT)) & ADC_SC3_AVGS_MASK) 556 #define ADC_SC3_AVGE_MASK (0x4U) 557 #define ADC_SC3_AVGE_SHIFT (2U) 558 /*! AVGE - Hardware Average Enable 559 * 0b0..Hardware average function disabled. 560 * 0b1..Hardware average function enabled. 561 */ 562 #define ADC_SC3_AVGE(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC3_AVGE_SHIFT)) & ADC_SC3_AVGE_MASK) 563 #define ADC_SC3_ADCO_MASK (0x8U) 564 #define ADC_SC3_ADCO_SHIFT (3U) 565 /*! ADCO - Continuous Conversion Enable 566 * 0b0..One conversion or one set of conversions if the hardware average function is enabled, that is, AVGE=1, after initiating a conversion. 567 * 0b1..Continuous conversions or sets of conversions if the hardware average function is enabled, that is, AVGE=1, after initiating a conversion. 568 */ 569 #define ADC_SC3_ADCO(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC3_ADCO_SHIFT)) & ADC_SC3_ADCO_MASK) 570 #define ADC_SC3_CALF_MASK (0x40U) 571 #define ADC_SC3_CALF_SHIFT (6U) 572 /*! CALF - Calibration Failed Flag 573 * 0b0..Calibration completed normally. 574 * 0b1..Calibration failed. ADC accuracy specifications are not guaranteed. 575 */ 576 #define ADC_SC3_CALF(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC3_CALF_SHIFT)) & ADC_SC3_CALF_MASK) 577 #define ADC_SC3_CAL_MASK (0x80U) 578 #define ADC_SC3_CAL_SHIFT (7U) 579 #define ADC_SC3_CAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC3_CAL_SHIFT)) & ADC_SC3_CAL_MASK) 580 /*! @} */ 581 582 /*! @name OFS - ADC Offset Correction Register */ 583 /*! @{ */ 584 #define ADC_OFS_OFS_MASK (0xFFFFU) 585 #define ADC_OFS_OFS_SHIFT (0U) 586 #define ADC_OFS_OFS(x) (((uint32_t)(((uint32_t)(x)) << ADC_OFS_OFS_SHIFT)) & ADC_OFS_OFS_MASK) 587 /*! @} */ 588 589 /*! @name PG - ADC Plus-Side Gain Register */ 590 /*! @{ */ 591 #define ADC_PG_PG_MASK (0xFFFFU) 592 #define ADC_PG_PG_SHIFT (0U) 593 #define ADC_PG_PG(x) (((uint32_t)(((uint32_t)(x)) << ADC_PG_PG_SHIFT)) & ADC_PG_PG_MASK) 594 /*! @} */ 595 596 /*! @name MG - ADC Minus-Side Gain Register */ 597 /*! @{ */ 598 #define ADC_MG_MG_MASK (0xFFFFU) 599 #define ADC_MG_MG_SHIFT (0U) 600 #define ADC_MG_MG(x) (((uint32_t)(((uint32_t)(x)) << ADC_MG_MG_SHIFT)) & ADC_MG_MG_MASK) 601 /*! @} */ 602 603 /*! @name CLPD - ADC Plus-Side General Calibration Value Register */ 604 /*! @{ */ 605 #define ADC_CLPD_CLPD_MASK (0x3FU) 606 #define ADC_CLPD_CLPD_SHIFT (0U) 607 #define ADC_CLPD_CLPD(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLPD_CLPD_SHIFT)) & ADC_CLPD_CLPD_MASK) 608 /*! @} */ 609 610 /*! @name CLPS - ADC Plus-Side General Calibration Value Register */ 611 /*! @{ */ 612 #define ADC_CLPS_CLPS_MASK (0x3FU) 613 #define ADC_CLPS_CLPS_SHIFT (0U) 614 #define ADC_CLPS_CLPS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLPS_CLPS_SHIFT)) & ADC_CLPS_CLPS_MASK) 615 /*! @} */ 616 617 /*! @name CLP4 - ADC Plus-Side General Calibration Value Register */ 618 /*! @{ */ 619 #define ADC_CLP4_CLP4_MASK (0x3FFU) 620 #define ADC_CLP4_CLP4_SHIFT (0U) 621 #define ADC_CLP4_CLP4(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLP4_CLP4_SHIFT)) & ADC_CLP4_CLP4_MASK) 622 /*! @} */ 623 624 /*! @name CLP3 - ADC Plus-Side General Calibration Value Register */ 625 /*! @{ */ 626 #define ADC_CLP3_CLP3_MASK (0x1FFU) 627 #define ADC_CLP3_CLP3_SHIFT (0U) 628 #define ADC_CLP3_CLP3(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLP3_CLP3_SHIFT)) & ADC_CLP3_CLP3_MASK) 629 /*! @} */ 630 631 /*! @name CLP2 - ADC Plus-Side General Calibration Value Register */ 632 /*! @{ */ 633 #define ADC_CLP2_CLP2_MASK (0xFFU) 634 #define ADC_CLP2_CLP2_SHIFT (0U) 635 #define ADC_CLP2_CLP2(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLP2_CLP2_SHIFT)) & ADC_CLP2_CLP2_MASK) 636 /*! @} */ 637 638 /*! @name CLP1 - ADC Plus-Side General Calibration Value Register */ 639 /*! @{ */ 640 #define ADC_CLP1_CLP1_MASK (0x7FU) 641 #define ADC_CLP1_CLP1_SHIFT (0U) 642 #define ADC_CLP1_CLP1(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLP1_CLP1_SHIFT)) & ADC_CLP1_CLP1_MASK) 643 /*! @} */ 644 645 /*! @name CLP0 - ADC Plus-Side General Calibration Value Register */ 646 /*! @{ */ 647 #define ADC_CLP0_CLP0_MASK (0x3FU) 648 #define ADC_CLP0_CLP0_SHIFT (0U) 649 #define ADC_CLP0_CLP0(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLP0_CLP0_SHIFT)) & ADC_CLP0_CLP0_MASK) 650 /*! @} */ 651 652 /*! @name CLMD - ADC Minus-Side General Calibration Value Register */ 653 /*! @{ */ 654 #define ADC_CLMD_CLMD_MASK (0x3FU) 655 #define ADC_CLMD_CLMD_SHIFT (0U) 656 #define ADC_CLMD_CLMD(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLMD_CLMD_SHIFT)) & ADC_CLMD_CLMD_MASK) 657 /*! @} */ 658 659 /*! @name CLMS - ADC Minus-Side General Calibration Value Register */ 660 /*! @{ */ 661 #define ADC_CLMS_CLMS_MASK (0x3FU) 662 #define ADC_CLMS_CLMS_SHIFT (0U) 663 #define ADC_CLMS_CLMS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLMS_CLMS_SHIFT)) & ADC_CLMS_CLMS_MASK) 664 /*! @} */ 665 666 /*! @name CLM4 - ADC Minus-Side General Calibration Value Register */ 667 /*! @{ */ 668 #define ADC_CLM4_CLM4_MASK (0x3FFU) 669 #define ADC_CLM4_CLM4_SHIFT (0U) 670 #define ADC_CLM4_CLM4(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLM4_CLM4_SHIFT)) & ADC_CLM4_CLM4_MASK) 671 /*! @} */ 672 673 /*! @name CLM3 - ADC Minus-Side General Calibration Value Register */ 674 /*! @{ */ 675 #define ADC_CLM3_CLM3_MASK (0x1FFU) 676 #define ADC_CLM3_CLM3_SHIFT (0U) 677 #define ADC_CLM3_CLM3(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLM3_CLM3_SHIFT)) & ADC_CLM3_CLM3_MASK) 678 /*! @} */ 679 680 /*! @name CLM2 - ADC Minus-Side General Calibration Value Register */ 681 /*! @{ */ 682 #define ADC_CLM2_CLM2_MASK (0xFFU) 683 #define ADC_CLM2_CLM2_SHIFT (0U) 684 #define ADC_CLM2_CLM2(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLM2_CLM2_SHIFT)) & ADC_CLM2_CLM2_MASK) 685 /*! @} */ 686 687 /*! @name CLM1 - ADC Minus-Side General Calibration Value Register */ 688 /*! @{ */ 689 #define ADC_CLM1_CLM1_MASK (0x7FU) 690 #define ADC_CLM1_CLM1_SHIFT (0U) 691 #define ADC_CLM1_CLM1(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLM1_CLM1_SHIFT)) & ADC_CLM1_CLM1_MASK) 692 /*! @} */ 693 694 /*! @name CLM0 - ADC Minus-Side General Calibration Value Register */ 695 /*! @{ */ 696 #define ADC_CLM0_CLM0_MASK (0x3FU) 697 #define ADC_CLM0_CLM0_SHIFT (0U) 698 #define ADC_CLM0_CLM0(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLM0_CLM0_SHIFT)) & ADC_CLM0_CLM0_MASK) 699 /*! @} */ 700 701 702 /*! 703 * @} 704 */ /* end of group ADC_Register_Masks */ 705 706 707 /* ADC - Peripheral instance base addresses */ 708 /** Peripheral ADC0 base address */ 709 #define ADC0_BASE (0x4003B000u) 710 /** Peripheral ADC0 base pointer */ 711 #define ADC0 ((ADC_Type *)ADC0_BASE) 712 /** Peripheral ADC1 base address */ 713 #define ADC1_BASE (0x4003C000u) 714 /** Peripheral ADC1 base pointer */ 715 #define ADC1 ((ADC_Type *)ADC1_BASE) 716 /** Array initializer of ADC peripheral base addresses */ 717 #define ADC_BASE_ADDRS { ADC0_BASE, ADC1_BASE } 718 /** Array initializer of ADC peripheral base pointers */ 719 #define ADC_BASE_PTRS { ADC0, ADC1 } 720 /** Interrupt vectors for the ADC peripheral type */ 721 #define ADC_IRQS { ADC0_IRQn, ADC1_IRQn } 722 723 /*! 724 * @} 725 */ /* end of group ADC_Peripheral_Access_Layer */ 726 727 728 /* ---------------------------------------------------------------------------- 729 -- CAN Peripheral Access Layer 730 ---------------------------------------------------------------------------- */ 731 732 /*! 733 * @addtogroup CAN_Peripheral_Access_Layer CAN Peripheral Access Layer 734 * @{ 735 */ 736 737 /** CAN - Register Layout Typedef */ 738 typedef struct { 739 __IO uint32_t MCR; /**< Module Configuration Register, offset: 0x0 */ 740 __IO uint32_t CTRL1; /**< Control 1 register, offset: 0x4 */ 741 __IO uint32_t TIMER; /**< Free Running Timer, offset: 0x8 */ 742 uint8_t RESERVED_0[4]; 743 __IO uint32_t RXMGMASK; /**< Rx Mailboxes Global Mask Register, offset: 0x10 */ 744 __IO uint32_t RX14MASK; /**< Rx 14 Mask register, offset: 0x14 */ 745 __IO uint32_t RX15MASK; /**< Rx 15 Mask register, offset: 0x18 */ 746 __IO uint32_t ECR; /**< Error Counter, offset: 0x1C */ 747 __IO uint32_t ESR1; /**< Error and Status 1 register, offset: 0x20 */ 748 uint8_t RESERVED_1[4]; 749 __IO uint32_t IMASK1; /**< Interrupt Masks 1 register, offset: 0x28 */ 750 uint8_t RESERVED_2[4]; 751 __IO uint32_t IFLAG1; /**< Interrupt Flags 1 register, offset: 0x30 */ 752 __IO uint32_t CTRL2; /**< Control 2 register, offset: 0x34 */ 753 __I uint32_t ESR2; /**< Error and Status 2 register, offset: 0x38 */ 754 uint8_t RESERVED_3[8]; 755 __I uint32_t CRCR; /**< CRC Register, offset: 0x44 */ 756 __IO uint32_t RXFGMASK; /**< Rx FIFO Global Mask register, offset: 0x48 */ 757 __I uint32_t RXFIR; /**< Rx FIFO Information Register, offset: 0x4C */ 758 __IO uint32_t CBT; /**< CAN Bit Timing Register, offset: 0x50 */ 759 uint8_t RESERVED_4[44]; 760 struct { /* offset: 0x80, array step: 0x10 */ 761 __IO uint32_t CS; /**< Message Buffer 0 CS Register..Message Buffer 15 CS Register, array offset: 0x80, array step: 0x10 */ 762 __IO uint32_t ID; /**< Message Buffer 0 ID Register..Message Buffer 15 ID Register, array offset: 0x84, array step: 0x10 */ 763 __IO uint32_t WORD0; /**< Message Buffer 0 WORD0 Register..Message Buffer 15 WORD0 Register, array offset: 0x88, array step: 0x10 */ 764 __IO uint32_t WORD1; /**< Message Buffer 0 WORD1 Register..Message Buffer 15 WORD1 Register, array offset: 0x8C, array step: 0x10 */ 765 } MB[16]; 766 uint8_t RESERVED_5[1792]; 767 __IO uint32_t RXIMR[16]; /**< Rx Individual Mask Registers, array offset: 0x880, array step: 0x4 */ 768 } CAN_Type; 769 770 /* ---------------------------------------------------------------------------- 771 -- CAN Register Masks 772 ---------------------------------------------------------------------------- */ 773 774 /*! 775 * @addtogroup CAN_Register_Masks CAN Register Masks 776 * @{ 777 */ 778 779 /*! @name MCR - Module Configuration Register */ 780 /*! @{ */ 781 #define CAN_MCR_MAXMB_MASK (0x7FU) 782 #define CAN_MCR_MAXMB_SHIFT (0U) 783 #define CAN_MCR_MAXMB(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_MAXMB_SHIFT)) & CAN_MCR_MAXMB_MASK) 784 #define CAN_MCR_IDAM_MASK (0x300U) 785 #define CAN_MCR_IDAM_SHIFT (8U) 786 /*! IDAM - ID Acceptance Mode 787 * 0b00..Format A: One full ID (standard and extended) per ID Filter Table element. 788 * 0b01..Format B: Two full standard IDs or two partial 14-bit (standard and extended) IDs per ID Filter Table element. 789 * 0b10..Format C: Four partial 8-bit Standard IDs per ID Filter Table element. 790 * 0b11..Format D: All frames rejected. 791 */ 792 #define CAN_MCR_IDAM(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_IDAM_SHIFT)) & CAN_MCR_IDAM_MASK) 793 #define CAN_MCR_AEN_MASK (0x1000U) 794 #define CAN_MCR_AEN_SHIFT (12U) 795 /*! AEN - Abort Enable 796 * 0b0..Abort disabled. 797 * 0b1..Abort enabled. 798 */ 799 #define CAN_MCR_AEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_AEN_SHIFT)) & CAN_MCR_AEN_MASK) 800 #define CAN_MCR_LPRIOEN_MASK (0x2000U) 801 #define CAN_MCR_LPRIOEN_SHIFT (13U) 802 /*! LPRIOEN - Local Priority Enable 803 * 0b0..Local Priority disabled. 804 * 0b1..Local Priority enabled. 805 */ 806 #define CAN_MCR_LPRIOEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_LPRIOEN_SHIFT)) & CAN_MCR_LPRIOEN_MASK) 807 #define CAN_MCR_DMA_MASK (0x8000U) 808 #define CAN_MCR_DMA_SHIFT (15U) 809 /*! DMA - DMA Enable 810 * 0b0..DMA feature for RX FIFO disabled. 811 * 0b1..DMA feature for RX FIFO enabled. 812 */ 813 #define CAN_MCR_DMA(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_DMA_SHIFT)) & CAN_MCR_DMA_MASK) 814 #define CAN_MCR_IRMQ_MASK (0x10000U) 815 #define CAN_MCR_IRMQ_SHIFT (16U) 816 /*! IRMQ - Individual Rx Masking And Queue Enable 817 * 0b0..Individual Rx masking and queue feature are disabled. For backward compatibility with legacy applications, the reading of C/S word locks the MB even if it is EMPTY. 818 * 0b1..Individual Rx masking and queue feature are enabled. 819 */ 820 #define CAN_MCR_IRMQ(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_IRMQ_SHIFT)) & CAN_MCR_IRMQ_MASK) 821 #define CAN_MCR_SRXDIS_MASK (0x20000U) 822 #define CAN_MCR_SRXDIS_SHIFT (17U) 823 /*! SRXDIS - Self Reception Disable 824 * 0b0..Self reception enabled. 825 * 0b1..Self reception disabled. 826 */ 827 #define CAN_MCR_SRXDIS(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SRXDIS_SHIFT)) & CAN_MCR_SRXDIS_MASK) 828 #define CAN_MCR_DOZE_MASK (0x40000U) 829 #define CAN_MCR_DOZE_SHIFT (18U) 830 /*! DOZE - Doze Mode Enable 831 * 0b0..FlexCAN is not enabled to enter low-power mode when Doze mode is requested. 832 * 0b1..FlexCAN is enabled to enter low-power mode when Doze mode is requested. 833 */ 834 #define CAN_MCR_DOZE(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_DOZE_SHIFT)) & CAN_MCR_DOZE_MASK) 835 #define CAN_MCR_WAKSRC_MASK (0x80000U) 836 #define CAN_MCR_WAKSRC_SHIFT (19U) 837 /*! WAKSRC - Wake Up Source 838 * 0b0..FlexCAN uses the unfiltered Rx input to detect recessive to dominant edges on the CAN bus. 839 * 0b1..FlexCAN uses the filtered Rx input to detect recessive to dominant edges on the CAN bus. 840 */ 841 #define CAN_MCR_WAKSRC(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_WAKSRC_SHIFT)) & CAN_MCR_WAKSRC_MASK) 842 #define CAN_MCR_LPMACK_MASK (0x100000U) 843 #define CAN_MCR_LPMACK_SHIFT (20U) 844 /*! LPMACK - Low-Power Mode Acknowledge 845 * 0b0..FlexCAN is not in a low-power mode. 846 * 0b1..FlexCAN is in a low-power mode. 847 */ 848 #define CAN_MCR_LPMACK(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_LPMACK_SHIFT)) & CAN_MCR_LPMACK_MASK) 849 #define CAN_MCR_WRNEN_MASK (0x200000U) 850 #define CAN_MCR_WRNEN_SHIFT (21U) 851 /*! WRNEN - Warning Interrupt Enable 852 * 0b0..TWRNINT and RWRNINT bits are zero, independent of the values in the error counters. 853 * 0b1..TWRNINT and RWRNINT bits are set when the respective error counter transitions from less than 96 to greater than or equal to 96. 854 */ 855 #define CAN_MCR_WRNEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_WRNEN_SHIFT)) & CAN_MCR_WRNEN_MASK) 856 #define CAN_MCR_SLFWAK_MASK (0x400000U) 857 #define CAN_MCR_SLFWAK_SHIFT (22U) 858 /*! SLFWAK - Self Wake Up 859 * 0b0..FlexCAN Self Wake Up feature is disabled. 860 * 0b1..FlexCAN Self Wake Up feature is enabled. 861 */ 862 #define CAN_MCR_SLFWAK(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SLFWAK_SHIFT)) & CAN_MCR_SLFWAK_MASK) 863 #define CAN_MCR_SUPV_MASK (0x800000U) 864 #define CAN_MCR_SUPV_SHIFT (23U) 865 /*! SUPV - Supervisor Mode 866 * 0b0..FlexCAN is in User mode. Affected registers allow both Supervisor and Unrestricted accesses. 867 * 0b1..FlexCAN is in Supervisor mode. Affected registers allow only Supervisor access. Unrestricted access behaves as though the access was done to an unimplemented register location. 868 */ 869 #define CAN_MCR_SUPV(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SUPV_SHIFT)) & CAN_MCR_SUPV_MASK) 870 #define CAN_MCR_FRZACK_MASK (0x1000000U) 871 #define CAN_MCR_FRZACK_SHIFT (24U) 872 /*! FRZACK - Freeze Mode Acknowledge 873 * 0b0..FlexCAN not in Freeze mode, prescaler running. 874 * 0b1..FlexCAN in Freeze mode, prescaler stopped. 875 */ 876 #define CAN_MCR_FRZACK(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_FRZACK_SHIFT)) & CAN_MCR_FRZACK_MASK) 877 #define CAN_MCR_SOFTRST_MASK (0x2000000U) 878 #define CAN_MCR_SOFTRST_SHIFT (25U) 879 /*! SOFTRST - Soft Reset 880 * 0b0..No reset request. 881 * 0b1..Resets the registers affected by soft reset. 882 */ 883 #define CAN_MCR_SOFTRST(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SOFTRST_SHIFT)) & CAN_MCR_SOFTRST_MASK) 884 #define CAN_MCR_WAKMSK_MASK (0x4000000U) 885 #define CAN_MCR_WAKMSK_SHIFT (26U) 886 /*! WAKMSK - Wake Up Interrupt Mask 887 * 0b0..Wake Up Interrupt is disabled. 888 * 0b1..Wake Up Interrupt is enabled. 889 */ 890 #define CAN_MCR_WAKMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_WAKMSK_SHIFT)) & CAN_MCR_WAKMSK_MASK) 891 #define CAN_MCR_NOTRDY_MASK (0x8000000U) 892 #define CAN_MCR_NOTRDY_SHIFT (27U) 893 /*! NOTRDY - FlexCAN Not Ready 894 * 0b0..FlexCAN module is either in Normal mode, Listen-Only mode or Loop-Back mode. 895 * 0b1..FlexCAN module is either in Disable mode, Doze mode , Stop mode or Freeze mode. 896 */ 897 #define CAN_MCR_NOTRDY(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_NOTRDY_SHIFT)) & CAN_MCR_NOTRDY_MASK) 898 #define CAN_MCR_HALT_MASK (0x10000000U) 899 #define CAN_MCR_HALT_SHIFT (28U) 900 /*! HALT - Halt FlexCAN 901 * 0b0..No Freeze mode request. 902 * 0b1..Enters Freeze mode if the FRZ bit is asserted. 903 */ 904 #define CAN_MCR_HALT(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_HALT_SHIFT)) & CAN_MCR_HALT_MASK) 905 #define CAN_MCR_RFEN_MASK (0x20000000U) 906 #define CAN_MCR_RFEN_SHIFT (29U) 907 /*! RFEN - Rx FIFO Enable 908 * 0b0..Rx FIFO not enabled. 909 * 0b1..Rx FIFO enabled. 910 */ 911 #define CAN_MCR_RFEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_RFEN_SHIFT)) & CAN_MCR_RFEN_MASK) 912 #define CAN_MCR_FRZ_MASK (0x40000000U) 913 #define CAN_MCR_FRZ_SHIFT (30U) 914 /*! FRZ - Freeze Enable 915 * 0b0..Not enabled to enter Freeze mode. 916 * 0b1..Enabled to enter Freeze mode. 917 */ 918 #define CAN_MCR_FRZ(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_FRZ_SHIFT)) & CAN_MCR_FRZ_MASK) 919 #define CAN_MCR_MDIS_MASK (0x80000000U) 920 #define CAN_MCR_MDIS_SHIFT (31U) 921 /*! MDIS - Module Disable 922 * 0b0..Enable the FlexCAN module. 923 * 0b1..Disable the FlexCAN module. 924 */ 925 #define CAN_MCR_MDIS(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_MDIS_SHIFT)) & CAN_MCR_MDIS_MASK) 926 /*! @} */ 927 928 /*! @name CTRL1 - Control 1 register */ 929 /*! @{ */ 930 #define CAN_CTRL1_PROPSEG_MASK (0x7U) 931 #define CAN_CTRL1_PROPSEG_SHIFT (0U) 932 #define CAN_CTRL1_PROPSEG(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PROPSEG_SHIFT)) & CAN_CTRL1_PROPSEG_MASK) 933 #define CAN_CTRL1_LOM_MASK (0x8U) 934 #define CAN_CTRL1_LOM_SHIFT (3U) 935 /*! LOM - Listen-Only Mode 936 * 0b0..Listen-Only mode is deactivated. 937 * 0b1..FlexCAN module operates in Listen-Only mode. 938 */ 939 #define CAN_CTRL1_LOM(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_LOM_SHIFT)) & CAN_CTRL1_LOM_MASK) 940 #define CAN_CTRL1_LBUF_MASK (0x10U) 941 #define CAN_CTRL1_LBUF_SHIFT (4U) 942 /*! LBUF - Lowest Buffer Transmitted First 943 * 0b0..Buffer with highest priority is transmitted first. 944 * 0b1..Lowest number buffer is transmitted first. 945 */ 946 #define CAN_CTRL1_LBUF(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_LBUF_SHIFT)) & CAN_CTRL1_LBUF_MASK) 947 #define CAN_CTRL1_TSYN_MASK (0x20U) 948 #define CAN_CTRL1_TSYN_SHIFT (5U) 949 /*! TSYN - Timer Sync 950 * 0b0..Timer Sync feature disabled 951 * 0b1..Timer Sync feature enabled 952 */ 953 #define CAN_CTRL1_TSYN(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_TSYN_SHIFT)) & CAN_CTRL1_TSYN_MASK) 954 #define CAN_CTRL1_BOFFREC_MASK (0x40U) 955 #define CAN_CTRL1_BOFFREC_SHIFT (6U) 956 /*! BOFFREC - Bus Off Recovery 957 * 0b0..Automatic recovering from Bus Off state enabled. 958 * 0b1..Automatic recovering from Bus Off state disabled. 959 */ 960 #define CAN_CTRL1_BOFFREC(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_BOFFREC_SHIFT)) & CAN_CTRL1_BOFFREC_MASK) 961 #define CAN_CTRL1_SMP_MASK (0x80U) 962 #define CAN_CTRL1_SMP_SHIFT (7U) 963 /*! SMP - CAN Bit Sampling 964 * 0b0..Just one sample is used to determine the bit value. 965 * 0b1..Three samples are used to determine the value of the received bit: the regular one (sample point) and 2 preceding samples; a majority rule is used. 966 */ 967 #define CAN_CTRL1_SMP(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_SMP_SHIFT)) & CAN_CTRL1_SMP_MASK) 968 #define CAN_CTRL1_RWRNMSK_MASK (0x400U) 969 #define CAN_CTRL1_RWRNMSK_SHIFT (10U) 970 /*! RWRNMSK - Rx Warning Interrupt Mask 971 * 0b0..Rx Warning Interrupt disabled. 972 * 0b1..Rx Warning Interrupt enabled. 973 */ 974 #define CAN_CTRL1_RWRNMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_RWRNMSK_SHIFT)) & CAN_CTRL1_RWRNMSK_MASK) 975 #define CAN_CTRL1_TWRNMSK_MASK (0x800U) 976 #define CAN_CTRL1_TWRNMSK_SHIFT (11U) 977 /*! TWRNMSK - Tx Warning Interrupt Mask 978 * 0b0..Tx Warning Interrupt disabled. 979 * 0b1..Tx Warning Interrupt enabled. 980 */ 981 #define CAN_CTRL1_TWRNMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_TWRNMSK_SHIFT)) & CAN_CTRL1_TWRNMSK_MASK) 982 #define CAN_CTRL1_LPB_MASK (0x1000U) 983 #define CAN_CTRL1_LPB_SHIFT (12U) 984 /*! LPB - Loop Back Mode 985 * 0b0..Loop Back disabled. 986 * 0b1..Loop Back enabled. 987 */ 988 #define CAN_CTRL1_LPB(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_LPB_SHIFT)) & CAN_CTRL1_LPB_MASK) 989 #define CAN_CTRL1_CLKSRC_MASK (0x2000U) 990 #define CAN_CTRL1_CLKSRC_SHIFT (13U) 991 /*! CLKSRC - CAN Engine Clock Source 992 * 0b0..The CAN engine clock source is the oscillator clock. Under this condition, the oscillator clock frequency must be lower than the bus clock. 993 * 0b1..The CAN engine clock source is the peripheral clock. 994 */ 995 #define CAN_CTRL1_CLKSRC(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_CLKSRC_SHIFT)) & CAN_CTRL1_CLKSRC_MASK) 996 #define CAN_CTRL1_ERRMSK_MASK (0x4000U) 997 #define CAN_CTRL1_ERRMSK_SHIFT (14U) 998 /*! ERRMSK - Error Interrupt Mask 999 * 0b0..Error interrupt disabled. 1000 * 0b1..Error interrupt enabled. 1001 */ 1002 #define CAN_CTRL1_ERRMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_ERRMSK_SHIFT)) & CAN_CTRL1_ERRMSK_MASK) 1003 #define CAN_CTRL1_BOFFMSK_MASK (0x8000U) 1004 #define CAN_CTRL1_BOFFMSK_SHIFT (15U) 1005 /*! BOFFMSK - Bus Off Interrupt Mask 1006 * 0b0..Bus Off interrupt disabled. 1007 * 0b1..Bus Off interrupt enabled. 1008 */ 1009 #define CAN_CTRL1_BOFFMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_BOFFMSK_SHIFT)) & CAN_CTRL1_BOFFMSK_MASK) 1010 #define CAN_CTRL1_PSEG2_MASK (0x70000U) 1011 #define CAN_CTRL1_PSEG2_SHIFT (16U) 1012 #define CAN_CTRL1_PSEG2(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PSEG2_SHIFT)) & CAN_CTRL1_PSEG2_MASK) 1013 #define CAN_CTRL1_PSEG1_MASK (0x380000U) 1014 #define CAN_CTRL1_PSEG1_SHIFT (19U) 1015 #define CAN_CTRL1_PSEG1(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PSEG1_SHIFT)) & CAN_CTRL1_PSEG1_MASK) 1016 #define CAN_CTRL1_RJW_MASK (0xC00000U) 1017 #define CAN_CTRL1_RJW_SHIFT (22U) 1018 #define CAN_CTRL1_RJW(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_RJW_SHIFT)) & CAN_CTRL1_RJW_MASK) 1019 #define CAN_CTRL1_PRESDIV_MASK (0xFF000000U) 1020 #define CAN_CTRL1_PRESDIV_SHIFT (24U) 1021 #define CAN_CTRL1_PRESDIV(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PRESDIV_SHIFT)) & CAN_CTRL1_PRESDIV_MASK) 1022 /*! @} */ 1023 1024 /*! @name TIMER - Free Running Timer */ 1025 /*! @{ */ 1026 #define CAN_TIMER_TIMER_MASK (0xFFFFU) 1027 #define CAN_TIMER_TIMER_SHIFT (0U) 1028 #define CAN_TIMER_TIMER(x) (((uint32_t)(((uint32_t)(x)) << CAN_TIMER_TIMER_SHIFT)) & CAN_TIMER_TIMER_MASK) 1029 /*! @} */ 1030 1031 /*! @name RXMGMASK - Rx Mailboxes Global Mask Register */ 1032 /*! @{ */ 1033 #define CAN_RXMGMASK_MG_MASK (0xFFFFFFFFU) 1034 #define CAN_RXMGMASK_MG_SHIFT (0U) 1035 /*! MG - Rx Mailboxes Global Mask Bits 1036 * 0b00000000000000000000000000000000..The corresponding bit in the filter is "don't care." 1037 * 0b00000000000000000000000000000001..The corresponding bit in the filter is checked. 1038 */ 1039 #define CAN_RXMGMASK_MG(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXMGMASK_MG_SHIFT)) & CAN_RXMGMASK_MG_MASK) 1040 /*! @} */ 1041 1042 /*! @name RX14MASK - Rx 14 Mask register */ 1043 /*! @{ */ 1044 #define CAN_RX14MASK_RX14M_MASK (0xFFFFFFFFU) 1045 #define CAN_RX14MASK_RX14M_SHIFT (0U) 1046 /*! RX14M - Rx Buffer 14 Mask Bits 1047 * 0b00000000000000000000000000000000..The corresponding bit in the filter is "don't care." 1048 * 0b00000000000000000000000000000001..The corresponding bit in the filter is checked. 1049 */ 1050 #define CAN_RX14MASK_RX14M(x) (((uint32_t)(((uint32_t)(x)) << CAN_RX14MASK_RX14M_SHIFT)) & CAN_RX14MASK_RX14M_MASK) 1051 /*! @} */ 1052 1053 /*! @name RX15MASK - Rx 15 Mask register */ 1054 /*! @{ */ 1055 #define CAN_RX15MASK_RX15M_MASK (0xFFFFFFFFU) 1056 #define CAN_RX15MASK_RX15M_SHIFT (0U) 1057 /*! RX15M - Rx Buffer 15 Mask Bits 1058 * 0b00000000000000000000000000000000..The corresponding bit in the filter is "don't care." 1059 * 0b00000000000000000000000000000001..The corresponding bit in the filter is checked. 1060 */ 1061 #define CAN_RX15MASK_RX15M(x) (((uint32_t)(((uint32_t)(x)) << CAN_RX15MASK_RX15M_SHIFT)) & CAN_RX15MASK_RX15M_MASK) 1062 /*! @} */ 1063 1064 /*! @name ECR - Error Counter */ 1065 /*! @{ */ 1066 #define CAN_ECR_TXERRCNT_MASK (0xFFU) 1067 #define CAN_ECR_TXERRCNT_SHIFT (0U) 1068 #define CAN_ECR_TXERRCNT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ECR_TXERRCNT_SHIFT)) & CAN_ECR_TXERRCNT_MASK) 1069 #define CAN_ECR_RXERRCNT_MASK (0xFF00U) 1070 #define CAN_ECR_RXERRCNT_SHIFT (8U) 1071 #define CAN_ECR_RXERRCNT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ECR_RXERRCNT_SHIFT)) & CAN_ECR_RXERRCNT_MASK) 1072 /*! @} */ 1073 1074 /*! @name ESR1 - Error and Status 1 register */ 1075 /*! @{ */ 1076 #define CAN_ESR1_WAKINT_MASK (0x1U) 1077 #define CAN_ESR1_WAKINT_SHIFT (0U) 1078 /*! WAKINT - Wake-Up Interrupt 1079 * 0b0..No such occurrence. 1080 * 0b1..Indicates a recessive to dominant transition was received on the CAN bus. 1081 */ 1082 #define CAN_ESR1_WAKINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_WAKINT_SHIFT)) & CAN_ESR1_WAKINT_MASK) 1083 #define CAN_ESR1_ERRINT_MASK (0x2U) 1084 #define CAN_ESR1_ERRINT_SHIFT (1U) 1085 /*! ERRINT - Error Interrupt 1086 * 0b0..No such occurrence. 1087 * 0b1..Indicates setting of any Error Bit in the Error and Status Register. 1088 */ 1089 #define CAN_ESR1_ERRINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_ERRINT_SHIFT)) & CAN_ESR1_ERRINT_MASK) 1090 #define CAN_ESR1_BOFFINT_MASK (0x4U) 1091 #define CAN_ESR1_BOFFINT_SHIFT (2U) 1092 /*! BOFFINT - Bus Off Interrupt 1093 * 0b0..No such occurrence. 1094 * 0b1..FlexCAN module entered Bus Off state. 1095 */ 1096 #define CAN_ESR1_BOFFINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BOFFINT_SHIFT)) & CAN_ESR1_BOFFINT_MASK) 1097 #define CAN_ESR1_RX_MASK (0x8U) 1098 #define CAN_ESR1_RX_SHIFT (3U) 1099 /*! RX - FlexCAN In Reception 1100 * 0b0..FlexCAN is not receiving a message. 1101 * 0b1..FlexCAN is receiving a message. 1102 */ 1103 #define CAN_ESR1_RX(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_RX_SHIFT)) & CAN_ESR1_RX_MASK) 1104 #define CAN_ESR1_FLTCONF_MASK (0x30U) 1105 #define CAN_ESR1_FLTCONF_SHIFT (4U) 1106 /*! FLTCONF - Fault Confinement State 1107 * 0b00..Error Active 1108 * 0b01..Error Passive 1109 * 0b1x..Bus Off 1110 */ 1111 #define CAN_ESR1_FLTCONF(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_FLTCONF_SHIFT)) & CAN_ESR1_FLTCONF_MASK) 1112 #define CAN_ESR1_TX_MASK (0x40U) 1113 #define CAN_ESR1_TX_SHIFT (6U) 1114 /*! TX - FlexCAN In Transmission 1115 * 0b0..FlexCAN is not transmitting a message. 1116 * 0b1..FlexCAN is transmitting a message. 1117 */ 1118 #define CAN_ESR1_TX(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_TX_SHIFT)) & CAN_ESR1_TX_MASK) 1119 #define CAN_ESR1_IDLE_MASK (0x80U) 1120 #define CAN_ESR1_IDLE_SHIFT (7U) 1121 /*! IDLE 1122 * 0b0..No such occurrence. 1123 * 0b1..CAN bus is now IDLE. 1124 */ 1125 #define CAN_ESR1_IDLE(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_IDLE_SHIFT)) & CAN_ESR1_IDLE_MASK) 1126 #define CAN_ESR1_RXWRN_MASK (0x100U) 1127 #define CAN_ESR1_RXWRN_SHIFT (8U) 1128 /*! RXWRN - Rx Error Warning 1129 * 0b0..No such occurrence. 1130 * 0b1..RXERRCNT is greater than or equal to 96. 1131 */ 1132 #define CAN_ESR1_RXWRN(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_RXWRN_SHIFT)) & CAN_ESR1_RXWRN_MASK) 1133 #define CAN_ESR1_TXWRN_MASK (0x200U) 1134 #define CAN_ESR1_TXWRN_SHIFT (9U) 1135 /*! TXWRN - TX Error Warning 1136 * 0b0..No such occurrence. 1137 * 0b1..TXERRCNT is greater than or equal to 96. 1138 */ 1139 #define CAN_ESR1_TXWRN(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_TXWRN_SHIFT)) & CAN_ESR1_TXWRN_MASK) 1140 #define CAN_ESR1_STFERR_MASK (0x400U) 1141 #define CAN_ESR1_STFERR_SHIFT (10U) 1142 /*! STFERR - Stuffing Error 1143 * 0b0..No such occurrence. 1144 * 0b1..A Stuffing Error occurred since last read of this register. 1145 */ 1146 #define CAN_ESR1_STFERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_STFERR_SHIFT)) & CAN_ESR1_STFERR_MASK) 1147 #define CAN_ESR1_FRMERR_MASK (0x800U) 1148 #define CAN_ESR1_FRMERR_SHIFT (11U) 1149 /*! FRMERR - Form Error 1150 * 0b0..No such occurrence. 1151 * 0b1..A Form Error occurred since last read of this register. 1152 */ 1153 #define CAN_ESR1_FRMERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_FRMERR_SHIFT)) & CAN_ESR1_FRMERR_MASK) 1154 #define CAN_ESR1_CRCERR_MASK (0x1000U) 1155 #define CAN_ESR1_CRCERR_SHIFT (12U) 1156 /*! CRCERR - Cyclic Redundancy Check Error 1157 * 0b0..No such occurrence. 1158 * 0b1..A CRC error occurred since last read of this register. 1159 */ 1160 #define CAN_ESR1_CRCERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_CRCERR_SHIFT)) & CAN_ESR1_CRCERR_MASK) 1161 #define CAN_ESR1_ACKERR_MASK (0x2000U) 1162 #define CAN_ESR1_ACKERR_SHIFT (13U) 1163 /*! ACKERR - Acknowledge Error 1164 * 0b0..No such occurrence. 1165 * 0b1..An ACK error occurred since last read of this register. 1166 */ 1167 #define CAN_ESR1_ACKERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_ACKERR_SHIFT)) & CAN_ESR1_ACKERR_MASK) 1168 #define CAN_ESR1_BIT0ERR_MASK (0x4000U) 1169 #define CAN_ESR1_BIT0ERR_SHIFT (14U) 1170 /*! BIT0ERR - Bit0 Error 1171 * 0b0..No such occurrence. 1172 * 0b1..At least one bit sent as dominant is received as recessive. 1173 */ 1174 #define CAN_ESR1_BIT0ERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BIT0ERR_SHIFT)) & CAN_ESR1_BIT0ERR_MASK) 1175 #define CAN_ESR1_BIT1ERR_MASK (0x8000U) 1176 #define CAN_ESR1_BIT1ERR_SHIFT (15U) 1177 /*! BIT1ERR - Bit1 Error 1178 * 0b0..No such occurrence. 1179 * 0b1..At least one bit sent as recessive is received as dominant. 1180 */ 1181 #define CAN_ESR1_BIT1ERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BIT1ERR_SHIFT)) & CAN_ESR1_BIT1ERR_MASK) 1182 #define CAN_ESR1_RWRNINT_MASK (0x10000U) 1183 #define CAN_ESR1_RWRNINT_SHIFT (16U) 1184 /*! RWRNINT - Rx Warning Interrupt Flag 1185 * 0b0..No such occurrence. 1186 * 0b1..The Rx error counter transitioned from less than 96 to greater than or equal to 96. 1187 */ 1188 #define CAN_ESR1_RWRNINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_RWRNINT_SHIFT)) & CAN_ESR1_RWRNINT_MASK) 1189 #define CAN_ESR1_TWRNINT_MASK (0x20000U) 1190 #define CAN_ESR1_TWRNINT_SHIFT (17U) 1191 /*! TWRNINT - Tx Warning Interrupt Flag 1192 * 0b0..No such occurrence. 1193 * 0b1..The Tx error counter transitioned from less than 96 to greater than or equal to 96. 1194 */ 1195 #define CAN_ESR1_TWRNINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_TWRNINT_SHIFT)) & CAN_ESR1_TWRNINT_MASK) 1196 #define CAN_ESR1_SYNCH_MASK (0x40000U) 1197 #define CAN_ESR1_SYNCH_SHIFT (18U) 1198 /*! SYNCH - CAN Synchronization Status 1199 * 0b0..FlexCAN is not synchronized to the CAN bus. 1200 * 0b1..FlexCAN is synchronized to the CAN bus. 1201 */ 1202 #define CAN_ESR1_SYNCH(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_SYNCH_SHIFT)) & CAN_ESR1_SYNCH_MASK) 1203 #define CAN_ESR1_BOFFDONEINT_MASK (0x80000U) 1204 #define CAN_ESR1_BOFFDONEINT_SHIFT (19U) 1205 /*! BOFFDONEINT - Bus Off Done Interrupt 1206 * 0b0..No such occurrence. 1207 * 0b1..FlexCAN module has completed Bus Off process. 1208 */ 1209 #define CAN_ESR1_BOFFDONEINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BOFFDONEINT_SHIFT)) & CAN_ESR1_BOFFDONEINT_MASK) 1210 #define CAN_ESR1_ERROVR_MASK (0x200000U) 1211 #define CAN_ESR1_ERROVR_SHIFT (21U) 1212 /*! ERROVR - Error Overrun bit 1213 * 0b0..Overrun has not occurred. 1214 * 0b1..Overrun has occured. 1215 */ 1216 #define CAN_ESR1_ERROVR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_ERROVR_SHIFT)) & CAN_ESR1_ERROVR_MASK) 1217 /*! @} */ 1218 1219 /*! @name IMASK1 - Interrupt Masks 1 register */ 1220 /*! @{ */ 1221 #define CAN_IMASK1_BUF31TO0M_MASK (0xFFFFFFFFU) 1222 #define CAN_IMASK1_BUF31TO0M_SHIFT (0U) 1223 /*! BUF31TO0M - Buffer MB i Mask 1224 * 0b00000000000000000000000000000000..The corresponding buffer Interrupt is disabled. 1225 * 0b00000000000000000000000000000001..The corresponding buffer Interrupt is enabled. 1226 */ 1227 #define CAN_IMASK1_BUF31TO0M(x) (((uint32_t)(((uint32_t)(x)) << CAN_IMASK1_BUF31TO0M_SHIFT)) & CAN_IMASK1_BUF31TO0M_MASK) 1228 /*! @} */ 1229 1230 /*! @name IFLAG1 - Interrupt Flags 1 register */ 1231 /*! @{ */ 1232 #define CAN_IFLAG1_BUF0I_MASK (0x1U) 1233 #define CAN_IFLAG1_BUF0I_SHIFT (0U) 1234 /*! BUF0I - Buffer MB0 Interrupt Or Clear FIFO bit 1235 * 0b0..The corresponding buffer has no occurrence of successfully completed transmission or reception when MCR[RFEN]=0. 1236 * 0b1..The corresponding buffer has successfully completed transmission or reception when MCR[RFEN]=0. 1237 */ 1238 #define CAN_IFLAG1_BUF0I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF0I_SHIFT)) & CAN_IFLAG1_BUF0I_MASK) 1239 #define CAN_IFLAG1_BUF4TO1I_MASK (0x1EU) 1240 #define CAN_IFLAG1_BUF4TO1I_SHIFT (1U) 1241 /*! BUF4TO1I - Buffer MB i Interrupt Or "reserved" 1242 * 0b0000..The corresponding buffer has no occurrence of successfully completed transmission or reception when MCR[RFEN]=0. 1243 * 0b0001..The corresponding buffer has successfully completed transmission or reception when MCR[RFEN]=0. 1244 */ 1245 #define CAN_IFLAG1_BUF4TO1I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF4TO1I_SHIFT)) & CAN_IFLAG1_BUF4TO1I_MASK) 1246 #define CAN_IFLAG1_BUF5I_MASK (0x20U) 1247 #define CAN_IFLAG1_BUF5I_SHIFT (5U) 1248 /*! BUF5I - Buffer MB5 Interrupt Or "Frames available in Rx FIFO" 1249 * 0b0..No occurrence of MB5 completing transmission/reception when MCR[RFEN]=0, or of frame(s) available in the FIFO, when MCR[RFEN]=1 1250 * 0b1..MB5 completed transmission/reception when MCR[RFEN]=0, or frame(s) available in the Rx FIFO when MCR[RFEN]=1. It generates a DMA request in case of MCR[RFEN] and MCR[DMA] are enabled. 1251 */ 1252 #define CAN_IFLAG1_BUF5I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF5I_SHIFT)) & CAN_IFLAG1_BUF5I_MASK) 1253 #define CAN_IFLAG1_BUF6I_MASK (0x40U) 1254 #define CAN_IFLAG1_BUF6I_SHIFT (6U) 1255 /*! BUF6I - Buffer MB6 Interrupt Or "Rx FIFO Warning" 1256 * 0b0..No occurrence of MB6 completing transmission/reception when MCR[RFEN]=0, or of Rx FIFO almost full when MCR[RFEN]=1 1257 * 0b1..MB6 completed transmission/reception when MCR[RFEN]=0, or Rx FIFO almost full when MCR[RFEN]=1 1258 */ 1259 #define CAN_IFLAG1_BUF6I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF6I_SHIFT)) & CAN_IFLAG1_BUF6I_MASK) 1260 #define CAN_IFLAG1_BUF7I_MASK (0x80U) 1261 #define CAN_IFLAG1_BUF7I_SHIFT (7U) 1262 /*! BUF7I - Buffer MB7 Interrupt Or "Rx FIFO Overflow" 1263 * 0b0..No occurrence of MB7 completing transmission/reception when MCR[RFEN]=0, or of Rx FIFO overflow when MCR[RFEN]=1 1264 * 0b1..MB7 completed transmission/reception when MCR[RFEN]=0, or Rx FIFO overflow when MCR[RFEN]=1 1265 */ 1266 #define CAN_IFLAG1_BUF7I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF7I_SHIFT)) & CAN_IFLAG1_BUF7I_MASK) 1267 #define CAN_IFLAG1_BUF31TO8I_MASK (0xFFFFFF00U) 1268 #define CAN_IFLAG1_BUF31TO8I_SHIFT (8U) 1269 /*! BUF31TO8I - Buffer MBi Interrupt 1270 * 0b000000000000000000000000..The corresponding buffer has no occurrence of successfully completed transmission or reception. 1271 * 0b000000000000000000000001..The corresponding buffer has successfully completed transmission or reception. 1272 */ 1273 #define CAN_IFLAG1_BUF31TO8I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF31TO8I_SHIFT)) & CAN_IFLAG1_BUF31TO8I_MASK) 1274 /*! @} */ 1275 1276 /*! @name CTRL2 - Control 2 register */ 1277 /*! @{ */ 1278 #define CAN_CTRL2_EACEN_MASK (0x10000U) 1279 #define CAN_CTRL2_EACEN_SHIFT (16U) 1280 /*! EACEN - Entire Frame Arbitration Field Comparison Enable For Rx Mailboxes 1281 * 0b0..Rx Mailbox filter's IDE bit is always compared and RTR is never compared despite mask bits. 1282 * 0b1..Enables the comparison of both Rx Mailbox filter's IDE and RTR bit with their corresponding bits within the incoming frame. Mask bits do apply. 1283 */ 1284 #define CAN_CTRL2_EACEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_EACEN_SHIFT)) & CAN_CTRL2_EACEN_MASK) 1285 #define CAN_CTRL2_RRS_MASK (0x20000U) 1286 #define CAN_CTRL2_RRS_SHIFT (17U) 1287 /*! RRS - Remote Request Storing 1288 * 0b0..Remote Response Frame is generated. 1289 * 0b1..Remote Request Frame is stored. 1290 */ 1291 #define CAN_CTRL2_RRS(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_RRS_SHIFT)) & CAN_CTRL2_RRS_MASK) 1292 #define CAN_CTRL2_MRP_MASK (0x40000U) 1293 #define CAN_CTRL2_MRP_SHIFT (18U) 1294 /*! MRP - Mailboxes Reception Priority 1295 * 0b0..Matching starts from Rx FIFO and continues on Mailboxes. 1296 * 0b1..Matching starts from Mailboxes and continues on Rx FIFO. 1297 */ 1298 #define CAN_CTRL2_MRP(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_MRP_SHIFT)) & CAN_CTRL2_MRP_MASK) 1299 #define CAN_CTRL2_TASD_MASK (0xF80000U) 1300 #define CAN_CTRL2_TASD_SHIFT (19U) 1301 #define CAN_CTRL2_TASD(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_TASD_SHIFT)) & CAN_CTRL2_TASD_MASK) 1302 #define CAN_CTRL2_RFFN_MASK (0xF000000U) 1303 #define CAN_CTRL2_RFFN_SHIFT (24U) 1304 #define CAN_CTRL2_RFFN(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_RFFN_SHIFT)) & CAN_CTRL2_RFFN_MASK) 1305 #define CAN_CTRL2_BOFFDONEMSK_MASK (0x40000000U) 1306 #define CAN_CTRL2_BOFFDONEMSK_SHIFT (30U) 1307 /*! BOFFDONEMSK - Bus Off Done Interrupt Mask 1308 * 0b0..Bus Off Done interrupt disabled. 1309 * 0b1..Bus Off Done interrupt enabled. 1310 */ 1311 #define CAN_CTRL2_BOFFDONEMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_BOFFDONEMSK_SHIFT)) & CAN_CTRL2_BOFFDONEMSK_MASK) 1312 /*! @} */ 1313 1314 /*! @name ESR2 - Error and Status 2 register */ 1315 /*! @{ */ 1316 #define CAN_ESR2_IMB_MASK (0x2000U) 1317 #define CAN_ESR2_IMB_SHIFT (13U) 1318 /*! IMB - Inactive Mailbox 1319 * 0b0..If ESR2[VPS] is asserted, the ESR2[LPTM] is not an inactive Mailbox. 1320 * 0b1..If ESR2[VPS] is asserted, there is at least one inactive Mailbox. LPTM content is the number of the first one. 1321 */ 1322 #define CAN_ESR2_IMB(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR2_IMB_SHIFT)) & CAN_ESR2_IMB_MASK) 1323 #define CAN_ESR2_VPS_MASK (0x4000U) 1324 #define CAN_ESR2_VPS_SHIFT (14U) 1325 /*! VPS - Valid Priority Status 1326 * 0b0..Contents of IMB and LPTM are invalid. 1327 * 0b1..Contents of IMB and LPTM are valid. 1328 */ 1329 #define CAN_ESR2_VPS(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR2_VPS_SHIFT)) & CAN_ESR2_VPS_MASK) 1330 #define CAN_ESR2_LPTM_MASK (0x7F0000U) 1331 #define CAN_ESR2_LPTM_SHIFT (16U) 1332 #define CAN_ESR2_LPTM(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR2_LPTM_SHIFT)) & CAN_ESR2_LPTM_MASK) 1333 /*! @} */ 1334 1335 /*! @name CRCR - CRC Register */ 1336 /*! @{ */ 1337 #define CAN_CRCR_TXCRC_MASK (0x7FFFU) 1338 #define CAN_CRCR_TXCRC_SHIFT (0U) 1339 #define CAN_CRCR_TXCRC(x) (((uint32_t)(((uint32_t)(x)) << CAN_CRCR_TXCRC_SHIFT)) & CAN_CRCR_TXCRC_MASK) 1340 #define CAN_CRCR_MBCRC_MASK (0x7F0000U) 1341 #define CAN_CRCR_MBCRC_SHIFT (16U) 1342 #define CAN_CRCR_MBCRC(x) (((uint32_t)(((uint32_t)(x)) << CAN_CRCR_MBCRC_SHIFT)) & CAN_CRCR_MBCRC_MASK) 1343 /*! @} */ 1344 1345 /*! @name RXFGMASK - Rx FIFO Global Mask register */ 1346 /*! @{ */ 1347 #define CAN_RXFGMASK_FGM_MASK (0xFFFFFFFFU) 1348 #define CAN_RXFGMASK_FGM_SHIFT (0U) 1349 /*! FGM - Rx FIFO Global Mask Bits 1350 * 0b00000000000000000000000000000000..The corresponding bit in the filter is "don't care." 1351 * 0b00000000000000000000000000000001..The corresponding bit in the filter is checked. 1352 */ 1353 #define CAN_RXFGMASK_FGM(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXFGMASK_FGM_SHIFT)) & CAN_RXFGMASK_FGM_MASK) 1354 /*! @} */ 1355 1356 /*! @name RXFIR - Rx FIFO Information Register */ 1357 /*! @{ */ 1358 #define CAN_RXFIR_IDHIT_MASK (0x1FFU) 1359 #define CAN_RXFIR_IDHIT_SHIFT (0U) 1360 #define CAN_RXFIR_IDHIT(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXFIR_IDHIT_SHIFT)) & CAN_RXFIR_IDHIT_MASK) 1361 /*! @} */ 1362 1363 /*! @name CBT - CAN Bit Timing Register */ 1364 /*! @{ */ 1365 #define CAN_CBT_EPSEG2_MASK (0x1FU) 1366 #define CAN_CBT_EPSEG2_SHIFT (0U) 1367 #define CAN_CBT_EPSEG2(x) (((uint32_t)(((uint32_t)(x)) << CAN_CBT_EPSEG2_SHIFT)) & CAN_CBT_EPSEG2_MASK) 1368 #define CAN_CBT_EPSEG1_MASK (0x3E0U) 1369 #define CAN_CBT_EPSEG1_SHIFT (5U) 1370 #define CAN_CBT_EPSEG1(x) (((uint32_t)(((uint32_t)(x)) << CAN_CBT_EPSEG1_SHIFT)) & CAN_CBT_EPSEG1_MASK) 1371 #define CAN_CBT_EPROPSEG_MASK (0xFC00U) 1372 #define CAN_CBT_EPROPSEG_SHIFT (10U) 1373 #define CAN_CBT_EPROPSEG(x) (((uint32_t)(((uint32_t)(x)) << CAN_CBT_EPROPSEG_SHIFT)) & CAN_CBT_EPROPSEG_MASK) 1374 #define CAN_CBT_ERJW_MASK (0xF0000U) 1375 #define CAN_CBT_ERJW_SHIFT (16U) 1376 #define CAN_CBT_ERJW(x) (((uint32_t)(((uint32_t)(x)) << CAN_CBT_ERJW_SHIFT)) & CAN_CBT_ERJW_MASK) 1377 #define CAN_CBT_EPRESDIV_MASK (0x7FE00000U) 1378 #define CAN_CBT_EPRESDIV_SHIFT (21U) 1379 #define CAN_CBT_EPRESDIV(x) (((uint32_t)(((uint32_t)(x)) << CAN_CBT_EPRESDIV_SHIFT)) & CAN_CBT_EPRESDIV_MASK) 1380 #define CAN_CBT_BTF_MASK (0x80000000U) 1381 #define CAN_CBT_BTF_SHIFT (31U) 1382 /*! BTF - Bit Timing Format Enable 1383 * 0b0..Extended bit time definitions disabled. 1384 * 0b1..Extended bit time definitions enabled. 1385 */ 1386 #define CAN_CBT_BTF(x) (((uint32_t)(((uint32_t)(x)) << CAN_CBT_BTF_SHIFT)) & CAN_CBT_BTF_MASK) 1387 /*! @} */ 1388 1389 /*! @name CS - Message Buffer 0 CS Register..Message Buffer 15 CS Register */ 1390 /*! @{ */ 1391 #define CAN_CS_TIME_STAMP_MASK (0xFFFFU) 1392 #define CAN_CS_TIME_STAMP_SHIFT (0U) 1393 #define CAN_CS_TIME_STAMP(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_TIME_STAMP_SHIFT)) & CAN_CS_TIME_STAMP_MASK) 1394 #define CAN_CS_DLC_MASK (0xF0000U) 1395 #define CAN_CS_DLC_SHIFT (16U) 1396 #define CAN_CS_DLC(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_DLC_SHIFT)) & CAN_CS_DLC_MASK) 1397 #define CAN_CS_RTR_MASK (0x100000U) 1398 #define CAN_CS_RTR_SHIFT (20U) 1399 #define CAN_CS_RTR(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_RTR_SHIFT)) & CAN_CS_RTR_MASK) 1400 #define CAN_CS_IDE_MASK (0x200000U) 1401 #define CAN_CS_IDE_SHIFT (21U) 1402 #define CAN_CS_IDE(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_IDE_SHIFT)) & CAN_CS_IDE_MASK) 1403 #define CAN_CS_SRR_MASK (0x400000U) 1404 #define CAN_CS_SRR_SHIFT (22U) 1405 #define CAN_CS_SRR(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_SRR_SHIFT)) & CAN_CS_SRR_MASK) 1406 #define CAN_CS_CODE_MASK (0xF000000U) 1407 #define CAN_CS_CODE_SHIFT (24U) 1408 #define CAN_CS_CODE(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_CODE_SHIFT)) & CAN_CS_CODE_MASK) 1409 /*! @} */ 1410 1411 /* The count of CAN_CS */ 1412 #define CAN_CS_COUNT (16U) 1413 1414 /*! @name ID - Message Buffer 0 ID Register..Message Buffer 15 ID Register */ 1415 /*! @{ */ 1416 #define CAN_ID_EXT_MASK (0x3FFFFU) 1417 #define CAN_ID_EXT_SHIFT (0U) 1418 #define CAN_ID_EXT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ID_EXT_SHIFT)) & CAN_ID_EXT_MASK) 1419 #define CAN_ID_STD_MASK (0x1FFC0000U) 1420 #define CAN_ID_STD_SHIFT (18U) 1421 #define CAN_ID_STD(x) (((uint32_t)(((uint32_t)(x)) << CAN_ID_STD_SHIFT)) & CAN_ID_STD_MASK) 1422 #define CAN_ID_PRIO_MASK (0xE0000000U) 1423 #define CAN_ID_PRIO_SHIFT (29U) 1424 #define CAN_ID_PRIO(x) (((uint32_t)(((uint32_t)(x)) << CAN_ID_PRIO_SHIFT)) & CAN_ID_PRIO_MASK) 1425 /*! @} */ 1426 1427 /* The count of CAN_ID */ 1428 #define CAN_ID_COUNT (16U) 1429 1430 /*! @name WORD0 - Message Buffer 0 WORD0 Register..Message Buffer 15 WORD0 Register */ 1431 /*! @{ */ 1432 #define CAN_WORD0_DATA_BYTE_3_MASK (0xFFU) 1433 #define CAN_WORD0_DATA_BYTE_3_SHIFT (0U) 1434 #define CAN_WORD0_DATA_BYTE_3(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD0_DATA_BYTE_3_SHIFT)) & CAN_WORD0_DATA_BYTE_3_MASK) 1435 #define CAN_WORD0_DATA_BYTE_2_MASK (0xFF00U) 1436 #define CAN_WORD0_DATA_BYTE_2_SHIFT (8U) 1437 #define CAN_WORD0_DATA_BYTE_2(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD0_DATA_BYTE_2_SHIFT)) & CAN_WORD0_DATA_BYTE_2_MASK) 1438 #define CAN_WORD0_DATA_BYTE_1_MASK (0xFF0000U) 1439 #define CAN_WORD0_DATA_BYTE_1_SHIFT (16U) 1440 #define CAN_WORD0_DATA_BYTE_1(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD0_DATA_BYTE_1_SHIFT)) & CAN_WORD0_DATA_BYTE_1_MASK) 1441 #define CAN_WORD0_DATA_BYTE_0_MASK (0xFF000000U) 1442 #define CAN_WORD0_DATA_BYTE_0_SHIFT (24U) 1443 #define CAN_WORD0_DATA_BYTE_0(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD0_DATA_BYTE_0_SHIFT)) & CAN_WORD0_DATA_BYTE_0_MASK) 1444 /*! @} */ 1445 1446 /* The count of CAN_WORD0 */ 1447 #define CAN_WORD0_COUNT (16U) 1448 1449 /*! @name WORD1 - Message Buffer 0 WORD1 Register..Message Buffer 15 WORD1 Register */ 1450 /*! @{ */ 1451 #define CAN_WORD1_DATA_BYTE_7_MASK (0xFFU) 1452 #define CAN_WORD1_DATA_BYTE_7_SHIFT (0U) 1453 #define CAN_WORD1_DATA_BYTE_7(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD1_DATA_BYTE_7_SHIFT)) & CAN_WORD1_DATA_BYTE_7_MASK) 1454 #define CAN_WORD1_DATA_BYTE_6_MASK (0xFF00U) 1455 #define CAN_WORD1_DATA_BYTE_6_SHIFT (8U) 1456 #define CAN_WORD1_DATA_BYTE_6(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD1_DATA_BYTE_6_SHIFT)) & CAN_WORD1_DATA_BYTE_6_MASK) 1457 #define CAN_WORD1_DATA_BYTE_5_MASK (0xFF0000U) 1458 #define CAN_WORD1_DATA_BYTE_5_SHIFT (16U) 1459 #define CAN_WORD1_DATA_BYTE_5(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD1_DATA_BYTE_5_SHIFT)) & CAN_WORD1_DATA_BYTE_5_MASK) 1460 #define CAN_WORD1_DATA_BYTE_4_MASK (0xFF000000U) 1461 #define CAN_WORD1_DATA_BYTE_4_SHIFT (24U) 1462 #define CAN_WORD1_DATA_BYTE_4(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD1_DATA_BYTE_4_SHIFT)) & CAN_WORD1_DATA_BYTE_4_MASK) 1463 /*! @} */ 1464 1465 /* The count of CAN_WORD1 */ 1466 #define CAN_WORD1_COUNT (16U) 1467 1468 /*! @name RXIMR - Rx Individual Mask Registers */ 1469 /*! @{ */ 1470 #define CAN_RXIMR_MI_MASK (0xFFFFFFFFU) 1471 #define CAN_RXIMR_MI_SHIFT (0U) 1472 /*! MI - Individual Mask Bits 1473 * 0b00000000000000000000000000000000..The corresponding bit in the filter is "don't care." 1474 * 0b00000000000000000000000000000001..The corresponding bit in the filter is checked. 1475 */ 1476 #define CAN_RXIMR_MI(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXIMR_MI_SHIFT)) & CAN_RXIMR_MI_MASK) 1477 /*! @} */ 1478 1479 /* The count of CAN_RXIMR */ 1480 #define CAN_RXIMR_COUNT (16U) 1481 1482 1483 /*! 1484 * @} 1485 */ /* end of group CAN_Register_Masks */ 1486 1487 1488 /* CAN - Peripheral instance base addresses */ 1489 /** Peripheral CAN0 base address */ 1490 #define CAN0_BASE (0x40024000u) 1491 /** Peripheral CAN0 base pointer */ 1492 #define CAN0 ((CAN_Type *)CAN0_BASE) 1493 /** Array initializer of CAN peripheral base addresses */ 1494 #define CAN_BASE_ADDRS { CAN0_BASE } 1495 /** Array initializer of CAN peripheral base pointers */ 1496 #define CAN_BASE_PTRS { CAN0 } 1497 /** Interrupt vectors for the CAN peripheral type */ 1498 #define CAN_Rx_Warning_IRQS { CAN0_IRQn } 1499 #define CAN_Tx_Warning_IRQS { CAN0_IRQn } 1500 #define CAN_Wake_Up_IRQS { CAN0_IRQn } 1501 #define CAN_Error_IRQS { CAN0_IRQn } 1502 #define CAN_Bus_Off_IRQS { CAN0_IRQn } 1503 #define CAN_ORed_Message_buffer_IRQS { CAN0_IRQn } 1504 #define CAN_IMASK1_BUFLM_MASK CAN_IMASK1_BUF31TO0M_MASK 1505 #define CAN_IMASK1_BUFLM_SHIFT CAN_IMASK1_BUF31TO0M_SHIFT 1506 #define CAN_IMASK1_BUFLM_WIDTH CAN_IMASK1_BUF31TO0M_WIDTH 1507 #define CAN_IMASK1_BUFLM(x) CAN_IMASK1_BUF31TO0M(x) 1508 1509 1510 /*! 1511 * @} 1512 */ /* end of group CAN_Peripheral_Access_Layer */ 1513 1514 1515 /* ---------------------------------------------------------------------------- 1516 -- CMP Peripheral Access Layer 1517 ---------------------------------------------------------------------------- */ 1518 1519 /*! 1520 * @addtogroup CMP_Peripheral_Access_Layer CMP Peripheral Access Layer 1521 * @{ 1522 */ 1523 1524 /** CMP - Register Layout Typedef */ 1525 typedef struct { 1526 __IO uint8_t CR0; /**< CMP Control Register 0, offset: 0x0 */ 1527 __IO uint8_t CR1; /**< CMP Control Register 1, offset: 0x1 */ 1528 __IO uint8_t FPR; /**< CMP Filter Period Register, offset: 0x2 */ 1529 __IO uint8_t SCR; /**< CMP Status and Control Register, offset: 0x3 */ 1530 __IO uint8_t DACCR; /**< DAC Control Register, offset: 0x4 */ 1531 __IO uint8_t MUXCR; /**< MUX Control Register, offset: 0x5 */ 1532 } CMP_Type; 1533 1534 /* ---------------------------------------------------------------------------- 1535 -- CMP Register Masks 1536 ---------------------------------------------------------------------------- */ 1537 1538 /*! 1539 * @addtogroup CMP_Register_Masks CMP Register Masks 1540 * @{ 1541 */ 1542 1543 /*! @name CR0 - CMP Control Register 0 */ 1544 /*! @{ */ 1545 #define CMP_CR0_HYSTCTR_MASK (0x3U) 1546 #define CMP_CR0_HYSTCTR_SHIFT (0U) 1547 /*! HYSTCTR - Comparator hard block hysteresis control 1548 * 0b00..Level 0 1549 * 0b01..Level 1 1550 * 0b10..Level 2 1551 * 0b11..Level 3 1552 */ 1553 #define CMP_CR0_HYSTCTR(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR0_HYSTCTR_SHIFT)) & CMP_CR0_HYSTCTR_MASK) 1554 #define CMP_CR0_FILTER_CNT_MASK (0x70U) 1555 #define CMP_CR0_FILTER_CNT_SHIFT (4U) 1556 /*! FILTER_CNT - Filter Sample Count 1557 * 0b000..Filter is disabled. If SE = 1, then COUT is a logic 0. This is not a legal state, and is not recommended. If SE = 0, COUT = COUTA. 1558 * 0b001..One sample must agree. The comparator output is simply sampled. 1559 * 0b010..2 consecutive samples must agree. 1560 * 0b011..3 consecutive samples must agree. 1561 * 0b100..4 consecutive samples must agree. 1562 * 0b101..5 consecutive samples must agree. 1563 * 0b110..6 consecutive samples must agree. 1564 * 0b111..7 consecutive samples must agree. 1565 */ 1566 #define CMP_CR0_FILTER_CNT(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR0_FILTER_CNT_SHIFT)) & CMP_CR0_FILTER_CNT_MASK) 1567 /*! @} */ 1568 1569 /*! @name CR1 - CMP Control Register 1 */ 1570 /*! @{ */ 1571 #define CMP_CR1_EN_MASK (0x1U) 1572 #define CMP_CR1_EN_SHIFT (0U) 1573 /*! EN - Comparator Module Enable 1574 * 0b0..Analog Comparator is disabled. 1575 * 0b1..Analog Comparator is enabled. 1576 */ 1577 #define CMP_CR1_EN(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_EN_SHIFT)) & CMP_CR1_EN_MASK) 1578 #define CMP_CR1_OPE_MASK (0x2U) 1579 #define CMP_CR1_OPE_SHIFT (1U) 1580 /*! OPE - Comparator Output Pin Enable 1581 * 0b0..CMPO is not available on the associated CMPO output pin. If the comparator does not own the pin, this field has no effect. 1582 * 0b1..CMPO is available on the associated CMPO output pin. The comparator output (CMPO) is driven out on the associated CMPO output pin if the comparator owns the pin. If the comparator does not own the field, this bit has no effect. 1583 */ 1584 #define CMP_CR1_OPE(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_OPE_SHIFT)) & CMP_CR1_OPE_MASK) 1585 #define CMP_CR1_COS_MASK (0x4U) 1586 #define CMP_CR1_COS_SHIFT (2U) 1587 /*! COS - Comparator Output Select 1588 * 0b0..Set the filtered comparator output (CMPO) to equal COUT. 1589 * 0b1..Set the unfiltered comparator output (CMPO) to equal COUTA. 1590 */ 1591 #define CMP_CR1_COS(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_COS_SHIFT)) & CMP_CR1_COS_MASK) 1592 #define CMP_CR1_INV_MASK (0x8U) 1593 #define CMP_CR1_INV_SHIFT (3U) 1594 /*! INV - Comparator INVERT 1595 * 0b0..Does not invert the comparator output. 1596 * 0b1..Inverts the comparator output. 1597 */ 1598 #define CMP_CR1_INV(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_INV_SHIFT)) & CMP_CR1_INV_MASK) 1599 #define CMP_CR1_PMODE_MASK (0x10U) 1600 #define CMP_CR1_PMODE_SHIFT (4U) 1601 /*! PMODE - Power Mode Select 1602 * 0b0..Low-Speed (LS) Comparison mode selected. In this mode, CMP has slower output propagation delay and lower current consumption. 1603 * 0b1..High-Speed (HS) Comparison mode selected. In this mode, CMP has faster output propagation delay and higher current consumption. 1604 */ 1605 #define CMP_CR1_PMODE(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_PMODE_SHIFT)) & CMP_CR1_PMODE_MASK) 1606 #define CMP_CR1_TRIGM_MASK (0x20U) 1607 #define CMP_CR1_TRIGM_SHIFT (5U) 1608 /*! TRIGM - Trigger Mode Enable 1609 * 0b0..Trigger mode is disabled. 1610 * 0b1..Trigger mode is enabled. 1611 */ 1612 #define CMP_CR1_TRIGM(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_TRIGM_SHIFT)) & CMP_CR1_TRIGM_MASK) 1613 #define CMP_CR1_WE_MASK (0x40U) 1614 #define CMP_CR1_WE_SHIFT (6U) 1615 /*! WE - Windowing Enable 1616 * 0b0..Windowing mode is not selected. 1617 * 0b1..Windowing mode is selected. 1618 */ 1619 #define CMP_CR1_WE(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_WE_SHIFT)) & CMP_CR1_WE_MASK) 1620 #define CMP_CR1_SE_MASK (0x80U) 1621 #define CMP_CR1_SE_SHIFT (7U) 1622 /*! SE - Sample Enable 1623 * 0b0..Sampling mode is not selected. 1624 * 0b1..Sampling mode is selected. 1625 */ 1626 #define CMP_CR1_SE(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_SE_SHIFT)) & CMP_CR1_SE_MASK) 1627 /*! @} */ 1628 1629 /*! @name FPR - CMP Filter Period Register */ 1630 /*! @{ */ 1631 #define CMP_FPR_FILT_PER_MASK (0xFFU) 1632 #define CMP_FPR_FILT_PER_SHIFT (0U) 1633 #define CMP_FPR_FILT_PER(x) (((uint8_t)(((uint8_t)(x)) << CMP_FPR_FILT_PER_SHIFT)) & CMP_FPR_FILT_PER_MASK) 1634 /*! @} */ 1635 1636 /*! @name SCR - CMP Status and Control Register */ 1637 /*! @{ */ 1638 #define CMP_SCR_COUT_MASK (0x1U) 1639 #define CMP_SCR_COUT_SHIFT (0U) 1640 #define CMP_SCR_COUT(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_COUT_SHIFT)) & CMP_SCR_COUT_MASK) 1641 #define CMP_SCR_CFF_MASK (0x2U) 1642 #define CMP_SCR_CFF_SHIFT (1U) 1643 /*! CFF - Analog Comparator Flag Falling 1644 * 0b0..Falling-edge on COUT has not been detected. 1645 * 0b1..Falling-edge on COUT has occurred. 1646 */ 1647 #define CMP_SCR_CFF(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_CFF_SHIFT)) & CMP_SCR_CFF_MASK) 1648 #define CMP_SCR_CFR_MASK (0x4U) 1649 #define CMP_SCR_CFR_SHIFT (2U) 1650 /*! CFR - Analog Comparator Flag Rising 1651 * 0b0..Rising-edge on COUT has not been detected. 1652 * 0b1..Rising-edge on COUT has occurred. 1653 */ 1654 #define CMP_SCR_CFR(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_CFR_SHIFT)) & CMP_SCR_CFR_MASK) 1655 #define CMP_SCR_IEF_MASK (0x8U) 1656 #define CMP_SCR_IEF_SHIFT (3U) 1657 /*! IEF - Comparator Interrupt Enable Falling 1658 * 0b0..Interrupt is disabled. 1659 * 0b1..Interrupt is enabled. 1660 */ 1661 #define CMP_SCR_IEF(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_IEF_SHIFT)) & CMP_SCR_IEF_MASK) 1662 #define CMP_SCR_IER_MASK (0x10U) 1663 #define CMP_SCR_IER_SHIFT (4U) 1664 /*! IER - Comparator Interrupt Enable Rising 1665 * 0b0..Interrupt is disabled. 1666 * 0b1..Interrupt is enabled. 1667 */ 1668 #define CMP_SCR_IER(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_IER_SHIFT)) & CMP_SCR_IER_MASK) 1669 #define CMP_SCR_DMAEN_MASK (0x40U) 1670 #define CMP_SCR_DMAEN_SHIFT (6U) 1671 /*! DMAEN - DMA Enable Control 1672 * 0b0..DMA is disabled. 1673 * 0b1..DMA is enabled. 1674 */ 1675 #define CMP_SCR_DMAEN(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_DMAEN_SHIFT)) & CMP_SCR_DMAEN_MASK) 1676 /*! @} */ 1677 1678 /*! @name DACCR - DAC Control Register */ 1679 /*! @{ */ 1680 #define CMP_DACCR_VOSEL_MASK (0x3FU) 1681 #define CMP_DACCR_VOSEL_SHIFT (0U) 1682 #define CMP_DACCR_VOSEL(x) (((uint8_t)(((uint8_t)(x)) << CMP_DACCR_VOSEL_SHIFT)) & CMP_DACCR_VOSEL_MASK) 1683 #define CMP_DACCR_VRSEL_MASK (0x40U) 1684 #define CMP_DACCR_VRSEL_SHIFT (6U) 1685 /*! VRSEL - Supply Voltage Reference Source Select 1686 * 0b0..Vin1 is selected as resistor ladder network supply reference. 1687 * 0b1..Vin2 is selected as resistor ladder network supply reference. 1688 */ 1689 #define CMP_DACCR_VRSEL(x) (((uint8_t)(((uint8_t)(x)) << CMP_DACCR_VRSEL_SHIFT)) & CMP_DACCR_VRSEL_MASK) 1690 #define CMP_DACCR_DACEN_MASK (0x80U) 1691 #define CMP_DACCR_DACEN_SHIFT (7U) 1692 /*! DACEN - DAC Enable 1693 * 0b0..DAC is disabled. 1694 * 0b1..DAC is enabled. 1695 */ 1696 #define CMP_DACCR_DACEN(x) (((uint8_t)(((uint8_t)(x)) << CMP_DACCR_DACEN_SHIFT)) & CMP_DACCR_DACEN_MASK) 1697 /*! @} */ 1698 1699 /*! @name MUXCR - MUX Control Register */ 1700 /*! @{ */ 1701 #define CMP_MUXCR_MSEL_MASK (0x7U) 1702 #define CMP_MUXCR_MSEL_SHIFT (0U) 1703 /*! MSEL - Minus Input Mux Control 1704 * 0b000..IN0 1705 * 0b001..IN1 1706 * 0b010..IN2 1707 * 0b011..IN3 1708 * 0b100..IN4 1709 * 0b101..IN5 1710 * 0b110..IN6 1711 * 0b111..IN7 1712 */ 1713 #define CMP_MUXCR_MSEL(x) (((uint8_t)(((uint8_t)(x)) << CMP_MUXCR_MSEL_SHIFT)) & CMP_MUXCR_MSEL_MASK) 1714 #define CMP_MUXCR_PSEL_MASK (0x38U) 1715 #define CMP_MUXCR_PSEL_SHIFT (3U) 1716 /*! PSEL - Plus Input Mux Control 1717 * 0b000..IN0 1718 * 0b001..IN1 1719 * 0b010..IN2 1720 * 0b011..IN3 1721 * 0b100..IN4 1722 * 0b101..IN5 1723 * 0b110..IN6 1724 * 0b111..IN7 1725 */ 1726 #define CMP_MUXCR_PSEL(x) (((uint8_t)(((uint8_t)(x)) << CMP_MUXCR_PSEL_SHIFT)) & CMP_MUXCR_PSEL_MASK) 1727 /*! @} */ 1728 1729 1730 /*! 1731 * @} 1732 */ /* end of group CMP_Register_Masks */ 1733 1734 1735 /* CMP - Peripheral instance base addresses */ 1736 /** Peripheral CMP0 base address */ 1737 #define CMP0_BASE (0x40073000u) 1738 /** Peripheral CMP0 base pointer */ 1739 #define CMP0 ((CMP_Type *)CMP0_BASE) 1740 /** Peripheral CMP1 base address */ 1741 #define CMP1_BASE (0x40073008u) 1742 /** Peripheral CMP1 base pointer */ 1743 #define CMP1 ((CMP_Type *)CMP1_BASE) 1744 /** Array initializer of CMP peripheral base addresses */ 1745 #define CMP_BASE_ADDRS { CMP0_BASE, CMP1_BASE } 1746 /** Array initializer of CMP peripheral base pointers */ 1747 #define CMP_BASE_PTRS { CMP0, CMP1 } 1748 /** Interrupt vectors for the CMP peripheral type */ 1749 #define CMP_IRQS { CMP0_IRQn, CMP1_IRQn } 1750 1751 /*! 1752 * @} 1753 */ /* end of group CMP_Peripheral_Access_Layer */ 1754 1755 1756 /* ---------------------------------------------------------------------------- 1757 -- CRC Peripheral Access Layer 1758 ---------------------------------------------------------------------------- */ 1759 1760 /*! 1761 * @addtogroup CRC_Peripheral_Access_Layer CRC Peripheral Access Layer 1762 * @{ 1763 */ 1764 1765 /** CRC - Register Layout Typedef */ 1766 typedef struct { 1767 union { /* offset: 0x0 */ 1768 struct { /* offset: 0x0 */ 1769 __IO uint16_t DATAL; /**< CRC_DATAL register., offset: 0x0 */ 1770 __IO uint16_t DATAH; /**< CRC_DATAH register., offset: 0x2 */ 1771 } ACCESS16BIT; 1772 __IO uint32_t DATA; /**< CRC Data register, offset: 0x0 */ 1773 struct { /* offset: 0x0 */ 1774 __IO uint8_t DATALL; /**< CRC_DATALL register., offset: 0x0 */ 1775 __IO uint8_t DATALU; /**< CRC_DATALU register., offset: 0x1 */ 1776 __IO uint8_t DATAHL; /**< CRC_DATAHL register., offset: 0x2 */ 1777 __IO uint8_t DATAHU; /**< CRC_DATAHU register., offset: 0x3 */ 1778 } ACCESS8BIT; 1779 }; 1780 union { /* offset: 0x4 */ 1781 struct { /* offset: 0x4 */ 1782 __IO uint16_t GPOLYL; /**< CRC_GPOLYL register., offset: 0x4 */ 1783 __IO uint16_t GPOLYH; /**< CRC_GPOLYH register., offset: 0x6 */ 1784 } GPOLY_ACCESS16BIT; 1785 __IO uint32_t GPOLY; /**< CRC Polynomial register, offset: 0x4 */ 1786 struct { /* offset: 0x4 */ 1787 __IO uint8_t GPOLYLL; /**< CRC_GPOLYLL register., offset: 0x4 */ 1788 __IO uint8_t GPOLYLU; /**< CRC_GPOLYLU register., offset: 0x5 */ 1789 __IO uint8_t GPOLYHL; /**< CRC_GPOLYHL register., offset: 0x6 */ 1790 __IO uint8_t GPOLYHU; /**< CRC_GPOLYHU register., offset: 0x7 */ 1791 } GPOLY_ACCESS8BIT; 1792 }; 1793 union { /* offset: 0x8 */ 1794 __IO uint32_t CTRL; /**< CRC Control register, offset: 0x8 */ 1795 struct { /* offset: 0x8 */ 1796 uint8_t RESERVED_0[3]; 1797 __IO uint8_t CTRLHU; /**< CRC_CTRLHU register., offset: 0xB */ 1798 } CTRL_ACCESS8BIT; 1799 }; 1800 } CRC_Type; 1801 1802 /* ---------------------------------------------------------------------------- 1803 -- CRC Register Masks 1804 ---------------------------------------------------------------------------- */ 1805 1806 /*! 1807 * @addtogroup CRC_Register_Masks CRC Register Masks 1808 * @{ 1809 */ 1810 1811 /*! @name DATAL - CRC_DATAL register. */ 1812 /*! @{ */ 1813 #define CRC_DATAL_DATAL_MASK (0xFFFFU) 1814 #define CRC_DATAL_DATAL_SHIFT (0U) 1815 #define CRC_DATAL_DATAL(x) (((uint16_t)(((uint16_t)(x)) << CRC_DATAL_DATAL_SHIFT)) & CRC_DATAL_DATAL_MASK) 1816 /*! @} */ 1817 1818 /*! @name DATAH - CRC_DATAH register. */ 1819 /*! @{ */ 1820 #define CRC_DATAH_DATAH_MASK (0xFFFFU) 1821 #define CRC_DATAH_DATAH_SHIFT (0U) 1822 #define CRC_DATAH_DATAH(x) (((uint16_t)(((uint16_t)(x)) << CRC_DATAH_DATAH_SHIFT)) & CRC_DATAH_DATAH_MASK) 1823 /*! @} */ 1824 1825 /*! @name DATA - CRC Data register */ 1826 /*! @{ */ 1827 #define CRC_DATA_LL_MASK (0xFFU) 1828 #define CRC_DATA_LL_SHIFT (0U) 1829 #define CRC_DATA_LL(x) (((uint32_t)(((uint32_t)(x)) << CRC_DATA_LL_SHIFT)) & CRC_DATA_LL_MASK) 1830 #define CRC_DATA_LU_MASK (0xFF00U) 1831 #define CRC_DATA_LU_SHIFT (8U) 1832 #define CRC_DATA_LU(x) (((uint32_t)(((uint32_t)(x)) << CRC_DATA_LU_SHIFT)) & CRC_DATA_LU_MASK) 1833 #define CRC_DATA_HL_MASK (0xFF0000U) 1834 #define CRC_DATA_HL_SHIFT (16U) 1835 #define CRC_DATA_HL(x) (((uint32_t)(((uint32_t)(x)) << CRC_DATA_HL_SHIFT)) & CRC_DATA_HL_MASK) 1836 #define CRC_DATA_HU_MASK (0xFF000000U) 1837 #define CRC_DATA_HU_SHIFT (24U) 1838 #define CRC_DATA_HU(x) (((uint32_t)(((uint32_t)(x)) << CRC_DATA_HU_SHIFT)) & CRC_DATA_HU_MASK) 1839 /*! @} */ 1840 1841 /*! @name DATALL - CRC_DATALL register. */ 1842 /*! @{ */ 1843 #define CRC_DATALL_DATALL_MASK (0xFFU) 1844 #define CRC_DATALL_DATALL_SHIFT (0U) 1845 #define CRC_DATALL_DATALL(x) (((uint8_t)(((uint8_t)(x)) << CRC_DATALL_DATALL_SHIFT)) & CRC_DATALL_DATALL_MASK) 1846 /*! @} */ 1847 1848 /*! @name DATALU - CRC_DATALU register. */ 1849 /*! @{ */ 1850 #define CRC_DATALU_DATALU_MASK (0xFFU) 1851 #define CRC_DATALU_DATALU_SHIFT (0U) 1852 #define CRC_DATALU_DATALU(x) (((uint8_t)(((uint8_t)(x)) << CRC_DATALU_DATALU_SHIFT)) & CRC_DATALU_DATALU_MASK) 1853 /*! @} */ 1854 1855 /*! @name DATAHL - CRC_DATAHL register. */ 1856 /*! @{ */ 1857 #define CRC_DATAHL_DATAHL_MASK (0xFFU) 1858 #define CRC_DATAHL_DATAHL_SHIFT (0U) 1859 #define CRC_DATAHL_DATAHL(x) (((uint8_t)(((uint8_t)(x)) << CRC_DATAHL_DATAHL_SHIFT)) & CRC_DATAHL_DATAHL_MASK) 1860 /*! @} */ 1861 1862 /*! @name DATAHU - CRC_DATAHU register. */ 1863 /*! @{ */ 1864 #define CRC_DATAHU_DATAHU_MASK (0xFFU) 1865 #define CRC_DATAHU_DATAHU_SHIFT (0U) 1866 #define CRC_DATAHU_DATAHU(x) (((uint8_t)(((uint8_t)(x)) << CRC_DATAHU_DATAHU_SHIFT)) & CRC_DATAHU_DATAHU_MASK) 1867 /*! @} */ 1868 1869 /*! @name GPOLYL - CRC_GPOLYL register. */ 1870 /*! @{ */ 1871 #define CRC_GPOLYL_GPOLYL_MASK (0xFFFFU) 1872 #define CRC_GPOLYL_GPOLYL_SHIFT (0U) 1873 #define CRC_GPOLYL_GPOLYL(x) (((uint16_t)(((uint16_t)(x)) << CRC_GPOLYL_GPOLYL_SHIFT)) & CRC_GPOLYL_GPOLYL_MASK) 1874 /*! @} */ 1875 1876 /*! @name GPOLYH - CRC_GPOLYH register. */ 1877 /*! @{ */ 1878 #define CRC_GPOLYH_GPOLYH_MASK (0xFFFFU) 1879 #define CRC_GPOLYH_GPOLYH_SHIFT (0U) 1880 #define CRC_GPOLYH_GPOLYH(x) (((uint16_t)(((uint16_t)(x)) << CRC_GPOLYH_GPOLYH_SHIFT)) & CRC_GPOLYH_GPOLYH_MASK) 1881 /*! @} */ 1882 1883 /*! @name GPOLY - CRC Polynomial register */ 1884 /*! @{ */ 1885 #define CRC_GPOLY_LOW_MASK (0xFFFFU) 1886 #define CRC_GPOLY_LOW_SHIFT (0U) 1887 #define CRC_GPOLY_LOW(x) (((uint32_t)(((uint32_t)(x)) << CRC_GPOLY_LOW_SHIFT)) & CRC_GPOLY_LOW_MASK) 1888 #define CRC_GPOLY_HIGH_MASK (0xFFFF0000U) 1889 #define CRC_GPOLY_HIGH_SHIFT (16U) 1890 #define CRC_GPOLY_HIGH(x) (((uint32_t)(((uint32_t)(x)) << CRC_GPOLY_HIGH_SHIFT)) & CRC_GPOLY_HIGH_MASK) 1891 /*! @} */ 1892 1893 /*! @name GPOLYLL - CRC_GPOLYLL register. */ 1894 /*! @{ */ 1895 #define CRC_GPOLYLL_GPOLYLL_MASK (0xFFU) 1896 #define CRC_GPOLYLL_GPOLYLL_SHIFT (0U) 1897 #define CRC_GPOLYLL_GPOLYLL(x) (((uint8_t)(((uint8_t)(x)) << CRC_GPOLYLL_GPOLYLL_SHIFT)) & CRC_GPOLYLL_GPOLYLL_MASK) 1898 /*! @} */ 1899 1900 /*! @name GPOLYLU - CRC_GPOLYLU register. */ 1901 /*! @{ */ 1902 #define CRC_GPOLYLU_GPOLYLU_MASK (0xFFU) 1903 #define CRC_GPOLYLU_GPOLYLU_SHIFT (0U) 1904 #define CRC_GPOLYLU_GPOLYLU(x) (((uint8_t)(((uint8_t)(x)) << CRC_GPOLYLU_GPOLYLU_SHIFT)) & CRC_GPOLYLU_GPOLYLU_MASK) 1905 /*! @} */ 1906 1907 /*! @name GPOLYHL - CRC_GPOLYHL register. */ 1908 /*! @{ */ 1909 #define CRC_GPOLYHL_GPOLYHL_MASK (0xFFU) 1910 #define CRC_GPOLYHL_GPOLYHL_SHIFT (0U) 1911 #define CRC_GPOLYHL_GPOLYHL(x) (((uint8_t)(((uint8_t)(x)) << CRC_GPOLYHL_GPOLYHL_SHIFT)) & CRC_GPOLYHL_GPOLYHL_MASK) 1912 /*! @} */ 1913 1914 /*! @name GPOLYHU - CRC_GPOLYHU register. */ 1915 /*! @{ */ 1916 #define CRC_GPOLYHU_GPOLYHU_MASK (0xFFU) 1917 #define CRC_GPOLYHU_GPOLYHU_SHIFT (0U) 1918 #define CRC_GPOLYHU_GPOLYHU(x) (((uint8_t)(((uint8_t)(x)) << CRC_GPOLYHU_GPOLYHU_SHIFT)) & CRC_GPOLYHU_GPOLYHU_MASK) 1919 /*! @} */ 1920 1921 /*! @name CTRL - CRC Control register */ 1922 /*! @{ */ 1923 #define CRC_CTRL_TCRC_MASK (0x1000000U) 1924 #define CRC_CTRL_TCRC_SHIFT (24U) 1925 /*! TCRC 1926 * 0b0..16-bit CRC protocol. 1927 * 0b1..32-bit CRC protocol. 1928 */ 1929 #define CRC_CTRL_TCRC(x) (((uint32_t)(((uint32_t)(x)) << CRC_CTRL_TCRC_SHIFT)) & CRC_CTRL_TCRC_MASK) 1930 #define CRC_CTRL_WAS_MASK (0x2000000U) 1931 #define CRC_CTRL_WAS_SHIFT (25U) 1932 /*! WAS - Write CRC Data Register As Seed 1933 * 0b0..Writes to the CRC data register are data values. 1934 * 0b1..Writes to the CRC data register are seed values. 1935 */ 1936 #define CRC_CTRL_WAS(x) (((uint32_t)(((uint32_t)(x)) << CRC_CTRL_WAS_SHIFT)) & CRC_CTRL_WAS_MASK) 1937 #define CRC_CTRL_FXOR_MASK (0x4000000U) 1938 #define CRC_CTRL_FXOR_SHIFT (26U) 1939 /*! FXOR - Complement Read Of CRC Data Register 1940 * 0b0..No XOR on reading. 1941 * 0b1..Invert or complement the read value of the CRC Data register. 1942 */ 1943 #define CRC_CTRL_FXOR(x) (((uint32_t)(((uint32_t)(x)) << CRC_CTRL_FXOR_SHIFT)) & CRC_CTRL_FXOR_MASK) 1944 #define CRC_CTRL_TOTR_MASK (0x30000000U) 1945 #define CRC_CTRL_TOTR_SHIFT (28U) 1946 /*! TOTR - Type Of Transpose For Read 1947 * 0b00..No transposition. 1948 * 0b01..Bits in bytes are transposed; bytes are not transposed. 1949 * 0b10..Both bits in bytes and bytes are transposed. 1950 * 0b11..Only bytes are transposed; no bits in a byte are transposed. 1951 */ 1952 #define CRC_CTRL_TOTR(x) (((uint32_t)(((uint32_t)(x)) << CRC_CTRL_TOTR_SHIFT)) & CRC_CTRL_TOTR_MASK) 1953 #define CRC_CTRL_TOT_MASK (0xC0000000U) 1954 #define CRC_CTRL_TOT_SHIFT (30U) 1955 /*! TOT - Type Of Transpose For Writes 1956 * 0b00..No transposition. 1957 * 0b01..Bits in bytes are transposed; bytes are not transposed. 1958 * 0b10..Both bits in bytes and bytes are transposed. 1959 * 0b11..Only bytes are transposed; no bits in a byte are transposed. 1960 */ 1961 #define CRC_CTRL_TOT(x) (((uint32_t)(((uint32_t)(x)) << CRC_CTRL_TOT_SHIFT)) & CRC_CTRL_TOT_MASK) 1962 /*! @} */ 1963 1964 /*! @name CTRLHU - CRC_CTRLHU register. */ 1965 /*! @{ */ 1966 #define CRC_CTRLHU_TCRC_MASK (0x1U) 1967 #define CRC_CTRLHU_TCRC_SHIFT (0U) 1968 /*! TCRC 1969 * 0b0..16-bit CRC protocol. 1970 * 0b1..32-bit CRC protocol. 1971 */ 1972 #define CRC_CTRLHU_TCRC(x) (((uint8_t)(((uint8_t)(x)) << CRC_CTRLHU_TCRC_SHIFT)) & CRC_CTRLHU_TCRC_MASK) 1973 #define CRC_CTRLHU_WAS_MASK (0x2U) 1974 #define CRC_CTRLHU_WAS_SHIFT (1U) 1975 /*! WAS 1976 * 0b0..Writes to CRC data register are data values. 1977 * 0b1..Writes to CRC data reguster are seed values. 1978 */ 1979 #define CRC_CTRLHU_WAS(x) (((uint8_t)(((uint8_t)(x)) << CRC_CTRLHU_WAS_SHIFT)) & CRC_CTRLHU_WAS_MASK) 1980 #define CRC_CTRLHU_FXOR_MASK (0x4U) 1981 #define CRC_CTRLHU_FXOR_SHIFT (2U) 1982 /*! FXOR 1983 * 0b0..No XOR on reading. 1984 * 0b1..Invert or complement the read value of CRC data register. 1985 */ 1986 #define CRC_CTRLHU_FXOR(x) (((uint8_t)(((uint8_t)(x)) << CRC_CTRLHU_FXOR_SHIFT)) & CRC_CTRLHU_FXOR_MASK) 1987 #define CRC_CTRLHU_TOTR_MASK (0x30U) 1988 #define CRC_CTRLHU_TOTR_SHIFT (4U) 1989 /*! TOTR 1990 * 0b00..No Transposition. 1991 * 0b01..Bits in bytes are transposed, bytes are not transposed. 1992 * 0b10..Both bits in bytes and bytes are transposed. 1993 * 0b11..Only bytes are transposed; no bits in a byte are transposed. 1994 */ 1995 #define CRC_CTRLHU_TOTR(x) (((uint8_t)(((uint8_t)(x)) << CRC_CTRLHU_TOTR_SHIFT)) & CRC_CTRLHU_TOTR_MASK) 1996 #define CRC_CTRLHU_TOT_MASK (0xC0U) 1997 #define CRC_CTRLHU_TOT_SHIFT (6U) 1998 /*! TOT 1999 * 0b00..No Transposition. 2000 * 0b01..Bits in bytes are transposed, bytes are not transposed. 2001 * 0b10..Both bits in bytes and bytes are transposed. 2002 * 0b11..Only bytes are transposed; no bits in a byte are transposed. 2003 */ 2004 #define CRC_CTRLHU_TOT(x) (((uint8_t)(((uint8_t)(x)) << CRC_CTRLHU_TOT_SHIFT)) & CRC_CTRLHU_TOT_MASK) 2005 /*! @} */ 2006 2007 2008 /*! 2009 * @} 2010 */ /* end of group CRC_Register_Masks */ 2011 2012 2013 /* CRC - Peripheral instance base addresses */ 2014 /** Peripheral CRC base address */ 2015 #define CRC_BASE (0x40032000u) 2016 /** Peripheral CRC base pointer */ 2017 #define CRC0 ((CRC_Type *)CRC_BASE) 2018 /** Array initializer of CRC peripheral base addresses */ 2019 #define CRC_BASE_ADDRS { CRC_BASE } 2020 /** Array initializer of CRC peripheral base pointers */ 2021 #define CRC_BASE_PTRS { CRC0 } 2022 2023 /*! 2024 * @} 2025 */ /* end of group CRC_Peripheral_Access_Layer */ 2026 2027 2028 /* ---------------------------------------------------------------------------- 2029 -- DAC Peripheral Access Layer 2030 ---------------------------------------------------------------------------- */ 2031 2032 /*! 2033 * @addtogroup DAC_Peripheral_Access_Layer DAC Peripheral Access Layer 2034 * @{ 2035 */ 2036 2037 /** DAC - Register Layout Typedef */ 2038 typedef struct { 2039 struct { /* offset: 0x0, array step: 0x2 */ 2040 __IO uint8_t DATL; /**< DAC Data Low Register, array offset: 0x0, array step: 0x2 */ 2041 __IO uint8_t DATH; /**< DAC Data High Register, array offset: 0x1, array step: 0x2 */ 2042 } DAT[2]; 2043 uint8_t RESERVED_0[28]; 2044 __IO uint8_t SR; /**< DAC Status Register, offset: 0x20 */ 2045 __IO uint8_t C0; /**< DAC Control Register, offset: 0x21 */ 2046 __IO uint8_t C1; /**< DAC Control Register 1, offset: 0x22 */ 2047 __IO uint8_t C2; /**< DAC Control Register 2, offset: 0x23 */ 2048 } DAC_Type; 2049 2050 /* ---------------------------------------------------------------------------- 2051 -- DAC Register Masks 2052 ---------------------------------------------------------------------------- */ 2053 2054 /*! 2055 * @addtogroup DAC_Register_Masks DAC Register Masks 2056 * @{ 2057 */ 2058 2059 /*! @name DATL - DAC Data Low Register */ 2060 /*! @{ */ 2061 #define DAC_DATL_DATA0_MASK (0xFFU) 2062 #define DAC_DATL_DATA0_SHIFT (0U) 2063 #define DAC_DATL_DATA0(x) (((uint8_t)(((uint8_t)(x)) << DAC_DATL_DATA0_SHIFT)) & DAC_DATL_DATA0_MASK) 2064 /*! @} */ 2065 2066 /* The count of DAC_DATL */ 2067 #define DAC_DATL_COUNT (2U) 2068 2069 /*! @name DATH - DAC Data High Register */ 2070 /*! @{ */ 2071 #define DAC_DATH_DATA1_MASK (0xFU) 2072 #define DAC_DATH_DATA1_SHIFT (0U) 2073 #define DAC_DATH_DATA1(x) (((uint8_t)(((uint8_t)(x)) << DAC_DATH_DATA1_SHIFT)) & DAC_DATH_DATA1_MASK) 2074 /*! @} */ 2075 2076 /* The count of DAC_DATH */ 2077 #define DAC_DATH_COUNT (2U) 2078 2079 /*! @name SR - DAC Status Register */ 2080 /*! @{ */ 2081 #define DAC_SR_DACBFRPBF_MASK (0x1U) 2082 #define DAC_SR_DACBFRPBF_SHIFT (0U) 2083 /*! DACBFRPBF - DAC Buffer Read Pointer Bottom Position Flag 2084 * 0b0..The DAC buffer read pointer is not equal to C2[DACBFUP]. 2085 * 0b1..The DAC buffer read pointer is equal to C2[DACBFUP]. 2086 */ 2087 #define DAC_SR_DACBFRPBF(x) (((uint8_t)(((uint8_t)(x)) << DAC_SR_DACBFRPBF_SHIFT)) & DAC_SR_DACBFRPBF_MASK) 2088 #define DAC_SR_DACBFRPTF_MASK (0x2U) 2089 #define DAC_SR_DACBFRPTF_SHIFT (1U) 2090 /*! DACBFRPTF - DAC Buffer Read Pointer Top Position Flag 2091 * 0b0..The DAC buffer read pointer is not zero. 2092 * 0b1..The DAC buffer read pointer is zero. 2093 */ 2094 #define DAC_SR_DACBFRPTF(x) (((uint8_t)(((uint8_t)(x)) << DAC_SR_DACBFRPTF_SHIFT)) & DAC_SR_DACBFRPTF_MASK) 2095 #define DAC_SR_DACBFWMF_MASK (0x4U) 2096 #define DAC_SR_DACBFWMF_SHIFT (2U) 2097 /*! DACBFWMF - DAC Buffer Watermark Flag 2098 * 0b0..The DAC buffer read pointer has not reached the watermark level. 2099 * 0b1..The DAC buffer read pointer has reached the watermark level. 2100 */ 2101 #define DAC_SR_DACBFWMF(x) (((uint8_t)(((uint8_t)(x)) << DAC_SR_DACBFWMF_SHIFT)) & DAC_SR_DACBFWMF_MASK) 2102 /*! @} */ 2103 2104 /*! @name C0 - DAC Control Register */ 2105 /*! @{ */ 2106 #define DAC_C0_DACBBIEN_MASK (0x1U) 2107 #define DAC_C0_DACBBIEN_SHIFT (0U) 2108 /*! DACBBIEN - DAC Buffer Read Pointer Bottom Flag Interrupt Enable 2109 * 0b0..The DAC buffer read pointer bottom flag interrupt is disabled. 2110 * 0b1..The DAC buffer read pointer bottom flag interrupt is enabled. 2111 */ 2112 #define DAC_C0_DACBBIEN(x) (((uint8_t)(((uint8_t)(x)) << DAC_C0_DACBBIEN_SHIFT)) & DAC_C0_DACBBIEN_MASK) 2113 #define DAC_C0_DACBTIEN_MASK (0x2U) 2114 #define DAC_C0_DACBTIEN_SHIFT (1U) 2115 /*! DACBTIEN - DAC Buffer Read Pointer Top Flag Interrupt Enable 2116 * 0b0..The DAC buffer read pointer top flag interrupt is disabled. 2117 * 0b1..The DAC buffer read pointer top flag interrupt is enabled. 2118 */ 2119 #define DAC_C0_DACBTIEN(x) (((uint8_t)(((uint8_t)(x)) << DAC_C0_DACBTIEN_SHIFT)) & DAC_C0_DACBTIEN_MASK) 2120 #define DAC_C0_DACBWIEN_MASK (0x4U) 2121 #define DAC_C0_DACBWIEN_SHIFT (2U) 2122 /*! DACBWIEN - DAC Buffer Watermark Interrupt Enable 2123 * 0b0..The DAC buffer watermark interrupt is disabled. 2124 * 0b1..The DAC buffer watermark interrupt is enabled. 2125 */ 2126 #define DAC_C0_DACBWIEN(x) (((uint8_t)(((uint8_t)(x)) << DAC_C0_DACBWIEN_SHIFT)) & DAC_C0_DACBWIEN_MASK) 2127 #define DAC_C0_LPEN_MASK (0x8U) 2128 #define DAC_C0_LPEN_SHIFT (3U) 2129 /*! LPEN - DAC Low Power Control 2130 * 0b0..High-Power mode 2131 * 0b1..Low-Power mode 2132 */ 2133 #define DAC_C0_LPEN(x) (((uint8_t)(((uint8_t)(x)) << DAC_C0_LPEN_SHIFT)) & DAC_C0_LPEN_MASK) 2134 #define DAC_C0_DACSWTRG_MASK (0x10U) 2135 #define DAC_C0_DACSWTRG_SHIFT (4U) 2136 /*! DACSWTRG - DAC Software Trigger 2137 * 0b0..The DAC soft trigger is not valid. 2138 * 0b1..The DAC soft trigger is valid. 2139 */ 2140 #define DAC_C0_DACSWTRG(x) (((uint8_t)(((uint8_t)(x)) << DAC_C0_DACSWTRG_SHIFT)) & DAC_C0_DACSWTRG_MASK) 2141 #define DAC_C0_DACTRGSEL_MASK (0x20U) 2142 #define DAC_C0_DACTRGSEL_SHIFT (5U) 2143 /*! DACTRGSEL - DAC Trigger Select 2144 * 0b0..The DAC hardware trigger is selected. 2145 * 0b1..The DAC software trigger is selected. 2146 */ 2147 #define DAC_C0_DACTRGSEL(x) (((uint8_t)(((uint8_t)(x)) << DAC_C0_DACTRGSEL_SHIFT)) & DAC_C0_DACTRGSEL_MASK) 2148 #define DAC_C0_DACRFS_MASK (0x40U) 2149 #define DAC_C0_DACRFS_SHIFT (6U) 2150 /*! DACRFS - DAC Reference Select 2151 * 0b0..The DAC selects DACREF_1 as the reference voltage. 2152 * 0b1..The DAC selects DACREF_2 as the reference voltage. 2153 */ 2154 #define DAC_C0_DACRFS(x) (((uint8_t)(((uint8_t)(x)) << DAC_C0_DACRFS_SHIFT)) & DAC_C0_DACRFS_MASK) 2155 #define DAC_C0_DACEN_MASK (0x80U) 2156 #define DAC_C0_DACEN_SHIFT (7U) 2157 /*! DACEN - DAC Enable 2158 * 0b0..The DAC system is disabled. 2159 * 0b1..The DAC system is enabled. 2160 */ 2161 #define DAC_C0_DACEN(x) (((uint8_t)(((uint8_t)(x)) << DAC_C0_DACEN_SHIFT)) & DAC_C0_DACEN_MASK) 2162 /*! @} */ 2163 2164 /*! @name C1 - DAC Control Register 1 */ 2165 /*! @{ */ 2166 #define DAC_C1_DACBFEN_MASK (0x1U) 2167 #define DAC_C1_DACBFEN_SHIFT (0U) 2168 /*! DACBFEN - DAC Buffer Enable 2169 * 0b0..Buffer read pointer is disabled. The converted data is always the first word of the buffer. 2170 * 0b1..Buffer read pointer is enabled. The converted data is the word that the read pointer points to. It means converted data can be from any word of the buffer. 2171 */ 2172 #define DAC_C1_DACBFEN(x) (((uint8_t)(((uint8_t)(x)) << DAC_C1_DACBFEN_SHIFT)) & DAC_C1_DACBFEN_MASK) 2173 #define DAC_C1_DACBFMD_MASK (0x4U) 2174 #define DAC_C1_DACBFMD_SHIFT (2U) 2175 /*! DACBFMD - DAC Buffer Work Mode Select 2176 * 0b0..Normal mode 2177 * 0b1..One-Time Scan mode 2178 */ 2179 #define DAC_C1_DACBFMD(x) (((uint8_t)(((uint8_t)(x)) << DAC_C1_DACBFMD_SHIFT)) & DAC_C1_DACBFMD_MASK) 2180 #define DAC_C1_DMAEN_MASK (0x80U) 2181 #define DAC_C1_DMAEN_SHIFT (7U) 2182 /*! DMAEN - DMA Enable Select 2183 * 0b0..DMA is disabled. 2184 * 0b1..DMA is enabled. When DMA is enabled, the DMA request will be generated by original interrupts. The interrupts will not be presented on this module at the same time. 2185 */ 2186 #define DAC_C1_DMAEN(x) (((uint8_t)(((uint8_t)(x)) << DAC_C1_DMAEN_SHIFT)) & DAC_C1_DMAEN_MASK) 2187 /*! @} */ 2188 2189 /*! @name C2 - DAC Control Register 2 */ 2190 /*! @{ */ 2191 #define DAC_C2_DACBFUP_MASK (0x1U) 2192 #define DAC_C2_DACBFUP_SHIFT (0U) 2193 #define DAC_C2_DACBFUP(x) (((uint8_t)(((uint8_t)(x)) << DAC_C2_DACBFUP_SHIFT)) & DAC_C2_DACBFUP_MASK) 2194 #define DAC_C2_DACBFRP_MASK (0x10U) 2195 #define DAC_C2_DACBFRP_SHIFT (4U) 2196 #define DAC_C2_DACBFRP(x) (((uint8_t)(((uint8_t)(x)) << DAC_C2_DACBFRP_SHIFT)) & DAC_C2_DACBFRP_MASK) 2197 /*! @} */ 2198 2199 2200 /*! 2201 * @} 2202 */ /* end of group DAC_Register_Masks */ 2203 2204 2205 /* DAC - Peripheral instance base addresses */ 2206 /** Peripheral DAC0 base address */ 2207 #define DAC0_BASE (0x4003F000u) 2208 /** Peripheral DAC0 base pointer */ 2209 #define DAC0 ((DAC_Type *)DAC0_BASE) 2210 /** Array initializer of DAC peripheral base addresses */ 2211 #define DAC_BASE_ADDRS { DAC0_BASE } 2212 /** Array initializer of DAC peripheral base pointers */ 2213 #define DAC_BASE_PTRS { DAC0 } 2214 /** Interrupt vectors for the DAC peripheral type */ 2215 #define DAC_IRQS { DAC0_IRQn } 2216 2217 /*! 2218 * @} 2219 */ /* end of group DAC_Peripheral_Access_Layer */ 2220 2221 2222 /* ---------------------------------------------------------------------------- 2223 -- DMA Peripheral Access Layer 2224 ---------------------------------------------------------------------------- */ 2225 2226 /*! 2227 * @addtogroup DMA_Peripheral_Access_Layer DMA Peripheral Access Layer 2228 * @{ 2229 */ 2230 2231 /** DMA - Register Layout Typedef */ 2232 typedef struct { 2233 __IO uint32_t CR; /**< Control Register, offset: 0x0 */ 2234 __I uint32_t ES; /**< Error Status Register, offset: 0x4 */ 2235 uint8_t RESERVED_0[4]; 2236 __IO uint32_t ERQ; /**< Enable Request Register, offset: 0xC */ 2237 uint8_t RESERVED_1[4]; 2238 __IO uint32_t EEI; /**< Enable Error Interrupt Register, offset: 0x14 */ 2239 __O uint8_t CEEI; /**< Clear Enable Error Interrupt Register, offset: 0x18 */ 2240 __O uint8_t SEEI; /**< Set Enable Error Interrupt Register, offset: 0x19 */ 2241 __O uint8_t CERQ; /**< Clear Enable Request Register, offset: 0x1A */ 2242 __O uint8_t SERQ; /**< Set Enable Request Register, offset: 0x1B */ 2243 __O uint8_t CDNE; /**< Clear DONE Status Bit Register, offset: 0x1C */ 2244 __O uint8_t SSRT; /**< Set START Bit Register, offset: 0x1D */ 2245 __O uint8_t CERR; /**< Clear Error Register, offset: 0x1E */ 2246 __O uint8_t CINT; /**< Clear Interrupt Request Register, offset: 0x1F */ 2247 uint8_t RESERVED_2[4]; 2248 __IO uint32_t INT; /**< Interrupt Request Register, offset: 0x24 */ 2249 uint8_t RESERVED_3[4]; 2250 __IO uint32_t ERR; /**< Error Register, offset: 0x2C */ 2251 uint8_t RESERVED_4[4]; 2252 __I uint32_t HRS; /**< Hardware Request Status Register, offset: 0x34 */ 2253 uint8_t RESERVED_5[12]; 2254 __IO uint32_t EARS; /**< Enable Asynchronous Request in Stop Register, offset: 0x44 */ 2255 uint8_t RESERVED_6[184]; 2256 __IO uint8_t DCHPRI3; /**< Channel n Priority Register, offset: 0x100 */ 2257 __IO uint8_t DCHPRI2; /**< Channel n Priority Register, offset: 0x101 */ 2258 __IO uint8_t DCHPRI1; /**< Channel n Priority Register, offset: 0x102 */ 2259 __IO uint8_t DCHPRI0; /**< Channel n Priority Register, offset: 0x103 */ 2260 __IO uint8_t DCHPRI7; /**< Channel n Priority Register, offset: 0x104 */ 2261 __IO uint8_t DCHPRI6; /**< Channel n Priority Register, offset: 0x105 */ 2262 __IO uint8_t DCHPRI5; /**< Channel n Priority Register, offset: 0x106 */ 2263 __IO uint8_t DCHPRI4; /**< Channel n Priority Register, offset: 0x107 */ 2264 uint8_t RESERVED_7[3832]; 2265 struct { /* offset: 0x1000, array step: 0x20 */ 2266 __IO uint32_t SADDR; /**< TCD Source Address, array offset: 0x1000, array step: 0x20 */ 2267 __IO uint16_t SOFF; /**< TCD Signed Source Address Offset, array offset: 0x1004, array step: 0x20 */ 2268 __IO uint16_t ATTR; /**< TCD Transfer Attributes, array offset: 0x1006, array step: 0x20 */ 2269 union { /* offset: 0x1008, array step: 0x20 */ 2270 __IO uint32_t NBYTES_MLNO; /**< TCD Minor Byte Count (Minor Loop Mapping Disabled), array offset: 0x1008, array step: 0x20 */ 2271 __IO uint32_t NBYTES_MLOFFNO; /**< TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled), array offset: 0x1008, array step: 0x20 */ 2272 __IO uint32_t NBYTES_MLOFFYES; /**< TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled), array offset: 0x1008, array step: 0x20 */ 2273 }; 2274 __IO int32_t SLAST; /**< TCD Last Source Address Adjustment, array offset: 0x100C, array step: 0x20 */ 2275 __IO uint32_t DADDR; /**< TCD Destination Address, array offset: 0x1010, array step: 0x20 */ 2276 __IO uint16_t DOFF; /**< TCD Signed Destination Address Offset, array offset: 0x1014, array step: 0x20 */ 2277 union { /* offset: 0x1016, array step: 0x20 */ 2278 __IO uint16_t CITER_ELINKNO; /**< TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled), array offset: 0x1016, array step: 0x20 */ 2279 __IO uint16_t CITER_ELINKYES; /**< TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled), array offset: 0x1016, array step: 0x20 */ 2280 }; 2281 __IO int32_t DLAST_SGA; /**< TCD Last Destination Address Adjustment/Scatter Gather Address, array offset: 0x1018, array step: 0x20 */ 2282 __IO uint16_t CSR; /**< TCD Control and Status, array offset: 0x101C, array step: 0x20 */ 2283 union { /* offset: 0x101E, array step: 0x20 */ 2284 __IO uint16_t BITER_ELINKNO; /**< TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled), array offset: 0x101E, array step: 0x20 */ 2285 __IO uint16_t BITER_ELINKYES; /**< TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled), array offset: 0x101E, array step: 0x20 */ 2286 }; 2287 } TCD[8]; 2288 } DMA_Type; 2289 2290 /* ---------------------------------------------------------------------------- 2291 -- DMA Register Masks 2292 ---------------------------------------------------------------------------- */ 2293 2294 /*! 2295 * @addtogroup DMA_Register_Masks DMA Register Masks 2296 * @{ 2297 */ 2298 2299 /*! @name CR - Control Register */ 2300 /*! @{ */ 2301 #define DMA_CR_EDBG_MASK (0x2U) 2302 #define DMA_CR_EDBG_SHIFT (1U) 2303 /*! EDBG - Enable Debug 2304 * 0b0..When in debug mode, the DMA continues to operate. 2305 * 0b1..When in debug mode, the DMA stalls the start of a new channel. Executing channels are allowed to complete. Channel execution resumes when the system exits debug mode or the EDBG bit is cleared. 2306 */ 2307 #define DMA_CR_EDBG(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_EDBG_SHIFT)) & DMA_CR_EDBG_MASK) 2308 #define DMA_CR_ERCA_MASK (0x4U) 2309 #define DMA_CR_ERCA_SHIFT (2U) 2310 /*! ERCA - Enable Round Robin Channel Arbitration 2311 * 0b0..Fixed priority arbitration is used for channel selection . 2312 * 0b1..Round robin arbitration is used for channel selection . 2313 */ 2314 #define DMA_CR_ERCA(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_ERCA_SHIFT)) & DMA_CR_ERCA_MASK) 2315 #define DMA_CR_HOE_MASK (0x10U) 2316 #define DMA_CR_HOE_SHIFT (4U) 2317 /*! HOE - Halt On Error 2318 * 0b0..Normal operation 2319 * 0b1..Any error causes the HALT bit to set. Subsequently, all service requests are ignored until the HALT bit is cleared. 2320 */ 2321 #define DMA_CR_HOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_HOE_SHIFT)) & DMA_CR_HOE_MASK) 2322 #define DMA_CR_HALT_MASK (0x20U) 2323 #define DMA_CR_HALT_SHIFT (5U) 2324 /*! HALT - Halt DMA Operations 2325 * 0b0..Normal operation 2326 * 0b1..Stall the start of any new channels. Executing channels are allowed to complete. Channel execution resumes when this bit is cleared. 2327 */ 2328 #define DMA_CR_HALT(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_HALT_SHIFT)) & DMA_CR_HALT_MASK) 2329 #define DMA_CR_CLM_MASK (0x40U) 2330 #define DMA_CR_CLM_SHIFT (6U) 2331 /*! CLM - Continuous Link Mode 2332 * 0b0..A minor loop channel link made to itself goes through channel arbitration before being activated again. 2333 * 0b1..A minor loop channel link made to itself does not go through channel arbitration before being activated again. Upon minor loop completion, the channel activates again if that channel has a minor loop channel link enabled and the link channel is itself. This effectively applies the minor loop offsets and restarts the next minor loop. 2334 */ 2335 #define DMA_CR_CLM(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_CLM_SHIFT)) & DMA_CR_CLM_MASK) 2336 #define DMA_CR_EMLM_MASK (0x80U) 2337 #define DMA_CR_EMLM_SHIFT (7U) 2338 /*! EMLM - Enable Minor Loop Mapping 2339 * 0b0..Disabled. TCDn.word2 is defined as a 32-bit NBYTES field. 2340 * 0b1..Enabled. TCDn.word2 is redefined to include individual enable fields, an offset field, and the NBYTES field. The individual enable fields allow the minor loop offset to be applied to the source address, the destination address, or both. The NBYTES field is reduced when either offset is enabled. 2341 */ 2342 #define DMA_CR_EMLM(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_EMLM_SHIFT)) & DMA_CR_EMLM_MASK) 2343 #define DMA_CR_ECX_MASK (0x10000U) 2344 #define DMA_CR_ECX_SHIFT (16U) 2345 /*! ECX - Error Cancel Transfer 2346 * 0b0..Normal operation 2347 * 0b1..Cancel the remaining data transfer in the same fashion as the CX bit. Stop the executing channel and force the minor loop to finish. The cancel takes effect after the last write of the current read/write sequence. The ECX bit clears itself after the cancel is honored. In addition to cancelling the transfer, ECX treats the cancel as an error condition, thus updating the Error Status register (DMAx_ES) and generating an optional error interrupt. 2348 */ 2349 #define DMA_CR_ECX(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_ECX_SHIFT)) & DMA_CR_ECX_MASK) 2350 #define DMA_CR_CX_MASK (0x20000U) 2351 #define DMA_CR_CX_SHIFT (17U) 2352 /*! CX - Cancel Transfer 2353 * 0b0..Normal operation 2354 * 0b1..Cancel the remaining data transfer. Stop the executing channel and force the minor loop to finish. The cancel takes effect after the last write of the current read/write sequence. The CX bit clears itself after the cancel has been honored. This cancel retires the channel normally as if the minor loop was completed. 2355 */ 2356 #define DMA_CR_CX(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_CX_SHIFT)) & DMA_CR_CX_MASK) 2357 #define DMA_CR_ACTIVE_MASK (0x80000000U) 2358 #define DMA_CR_ACTIVE_SHIFT (31U) 2359 /*! ACTIVE - DMA Active Status 2360 * 0b0..eDMA is idle. 2361 * 0b1..eDMA is executing a channel. 2362 */ 2363 #define DMA_CR_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_ACTIVE_SHIFT)) & DMA_CR_ACTIVE_MASK) 2364 /*! @} */ 2365 2366 /*! @name ES - Error Status Register */ 2367 /*! @{ */ 2368 #define DMA_ES_DBE_MASK (0x1U) 2369 #define DMA_ES_DBE_SHIFT (0U) 2370 /*! DBE - Destination Bus Error 2371 * 0b0..No destination bus error 2372 * 0b1..The last recorded error was a bus error on a destination write 2373 */ 2374 #define DMA_ES_DBE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_DBE_SHIFT)) & DMA_ES_DBE_MASK) 2375 #define DMA_ES_SBE_MASK (0x2U) 2376 #define DMA_ES_SBE_SHIFT (1U) 2377 /*! SBE - Source Bus Error 2378 * 0b0..No source bus error 2379 * 0b1..The last recorded error was a bus error on a source read 2380 */ 2381 #define DMA_ES_SBE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_SBE_SHIFT)) & DMA_ES_SBE_MASK) 2382 #define DMA_ES_SGE_MASK (0x4U) 2383 #define DMA_ES_SGE_SHIFT (2U) 2384 /*! SGE - Scatter/Gather Configuration Error 2385 * 0b0..No scatter/gather configuration error 2386 * 0b1..The last recorded error was a configuration error detected in the TCDn_DLASTSGA field. This field is checked at the beginning of a scatter/gather operation after major loop completion if TCDn_CSR[ESG] is enabled. TCDn_DLASTSGA is not on a 32 byte boundary. 2387 */ 2388 #define DMA_ES_SGE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_SGE_SHIFT)) & DMA_ES_SGE_MASK) 2389 #define DMA_ES_NCE_MASK (0x8U) 2390 #define DMA_ES_NCE_SHIFT (3U) 2391 /*! NCE - NBYTES/CITER Configuration Error 2392 * 0b0..No NBYTES/CITER configuration error 2393 * 0b1..The last recorded error was a configuration error detected in the TCDn_NBYTES or TCDn_CITER fields. TCDn_NBYTES is not a multiple of TCDn_ATTR[SSIZE] and TCDn_ATTR[DSIZE], or TCDn_CITER[CITER] is equal to zero, or TCDn_CITER[ELINK] is not equal to TCDn_BITER[ELINK] 2394 */ 2395 #define DMA_ES_NCE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_NCE_SHIFT)) & DMA_ES_NCE_MASK) 2396 #define DMA_ES_DOE_MASK (0x10U) 2397 #define DMA_ES_DOE_SHIFT (4U) 2398 /*! DOE - Destination Offset Error 2399 * 0b0..No destination offset configuration error 2400 * 0b1..The last recorded error was a configuration error detected in the TCDn_DOFF field. TCDn_DOFF is inconsistent with TCDn_ATTR[DSIZE]. 2401 */ 2402 #define DMA_ES_DOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_DOE_SHIFT)) & DMA_ES_DOE_MASK) 2403 #define DMA_ES_DAE_MASK (0x20U) 2404 #define DMA_ES_DAE_SHIFT (5U) 2405 /*! DAE - Destination Address Error 2406 * 0b0..No destination address configuration error 2407 * 0b1..The last recorded error was a configuration error detected in the TCDn_DADDR field. TCDn_DADDR is inconsistent with TCDn_ATTR[DSIZE]. 2408 */ 2409 #define DMA_ES_DAE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_DAE_SHIFT)) & DMA_ES_DAE_MASK) 2410 #define DMA_ES_SOE_MASK (0x40U) 2411 #define DMA_ES_SOE_SHIFT (6U) 2412 /*! SOE - Source Offset Error 2413 * 0b0..No source offset configuration error 2414 * 0b1..The last recorded error was a configuration error detected in the TCDn_SOFF field. TCDn_SOFF is inconsistent with TCDn_ATTR[SSIZE]. 2415 */ 2416 #define DMA_ES_SOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_SOE_SHIFT)) & DMA_ES_SOE_MASK) 2417 #define DMA_ES_SAE_MASK (0x80U) 2418 #define DMA_ES_SAE_SHIFT (7U) 2419 /*! SAE - Source Address Error 2420 * 0b0..No source address configuration error. 2421 * 0b1..The last recorded error was a configuration error detected in the TCDn_SADDR field. TCDn_SADDR is inconsistent with TCDn_ATTR[SSIZE]. 2422 */ 2423 #define DMA_ES_SAE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_SAE_SHIFT)) & DMA_ES_SAE_MASK) 2424 #define DMA_ES_ERRCHN_MASK (0x700U) 2425 #define DMA_ES_ERRCHN_SHIFT (8U) 2426 #define DMA_ES_ERRCHN(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_ERRCHN_SHIFT)) & DMA_ES_ERRCHN_MASK) 2427 #define DMA_ES_CPE_MASK (0x4000U) 2428 #define DMA_ES_CPE_SHIFT (14U) 2429 /*! CPE - Channel Priority Error 2430 * 0b0..No channel priority error 2431 * 0b1..The last recorded error was a configuration error in the channel priorities . Channel priorities are not unique. 2432 */ 2433 #define DMA_ES_CPE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_CPE_SHIFT)) & DMA_ES_CPE_MASK) 2434 #define DMA_ES_ECX_MASK (0x10000U) 2435 #define DMA_ES_ECX_SHIFT (16U) 2436 /*! ECX - Transfer Canceled 2437 * 0b0..No canceled transfers 2438 * 0b1..The last recorded entry was a canceled transfer by the error cancel transfer input 2439 */ 2440 #define DMA_ES_ECX(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_ECX_SHIFT)) & DMA_ES_ECX_MASK) 2441 #define DMA_ES_VLD_MASK (0x80000000U) 2442 #define DMA_ES_VLD_SHIFT (31U) 2443 /*! VLD 2444 * 0b0..No ERR bits are set. 2445 * 0b1..At least one ERR bit is set indicating a valid error exists that has not been cleared. 2446 */ 2447 #define DMA_ES_VLD(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_VLD_SHIFT)) & DMA_ES_VLD_MASK) 2448 /*! @} */ 2449 2450 /*! @name ERQ - Enable Request Register */ 2451 /*! @{ */ 2452 #define DMA_ERQ_ERQ0_MASK (0x1U) 2453 #define DMA_ERQ_ERQ0_SHIFT (0U) 2454 /*! ERQ0 - Enable DMA Request 0 2455 * 0b0..The DMA request signal for the corresponding channel is disabled 2456 * 0b1..The DMA request signal for the corresponding channel is enabled 2457 */ 2458 #define DMA_ERQ_ERQ0(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ0_SHIFT)) & DMA_ERQ_ERQ0_MASK) 2459 #define DMA_ERQ_ERQ1_MASK (0x2U) 2460 #define DMA_ERQ_ERQ1_SHIFT (1U) 2461 /*! ERQ1 - Enable DMA Request 1 2462 * 0b0..The DMA request signal for the corresponding channel is disabled 2463 * 0b1..The DMA request signal for the corresponding channel is enabled 2464 */ 2465 #define DMA_ERQ_ERQ1(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ1_SHIFT)) & DMA_ERQ_ERQ1_MASK) 2466 #define DMA_ERQ_ERQ2_MASK (0x4U) 2467 #define DMA_ERQ_ERQ2_SHIFT (2U) 2468 /*! ERQ2 - Enable DMA Request 2 2469 * 0b0..The DMA request signal for the corresponding channel is disabled 2470 * 0b1..The DMA request signal for the corresponding channel is enabled 2471 */ 2472 #define DMA_ERQ_ERQ2(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ2_SHIFT)) & DMA_ERQ_ERQ2_MASK) 2473 #define DMA_ERQ_ERQ3_MASK (0x8U) 2474 #define DMA_ERQ_ERQ3_SHIFT (3U) 2475 /*! ERQ3 - Enable DMA Request 3 2476 * 0b0..The DMA request signal for the corresponding channel is disabled 2477 * 0b1..The DMA request signal for the corresponding channel is enabled 2478 */ 2479 #define DMA_ERQ_ERQ3(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ3_SHIFT)) & DMA_ERQ_ERQ3_MASK) 2480 #define DMA_ERQ_ERQ4_MASK (0x10U) 2481 #define DMA_ERQ_ERQ4_SHIFT (4U) 2482 /*! ERQ4 - Enable DMA Request 4 2483 * 0b0..The DMA request signal for the corresponding channel is disabled 2484 * 0b1..The DMA request signal for the corresponding channel is enabled 2485 */ 2486 #define DMA_ERQ_ERQ4(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ4_SHIFT)) & DMA_ERQ_ERQ4_MASK) 2487 #define DMA_ERQ_ERQ5_MASK (0x20U) 2488 #define DMA_ERQ_ERQ5_SHIFT (5U) 2489 /*! ERQ5 - Enable DMA Request 5 2490 * 0b0..The DMA request signal for the corresponding channel is disabled 2491 * 0b1..The DMA request signal for the corresponding channel is enabled 2492 */ 2493 #define DMA_ERQ_ERQ5(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ5_SHIFT)) & DMA_ERQ_ERQ5_MASK) 2494 #define DMA_ERQ_ERQ6_MASK (0x40U) 2495 #define DMA_ERQ_ERQ6_SHIFT (6U) 2496 /*! ERQ6 - Enable DMA Request 6 2497 * 0b0..The DMA request signal for the corresponding channel is disabled 2498 * 0b1..The DMA request signal for the corresponding channel is enabled 2499 */ 2500 #define DMA_ERQ_ERQ6(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ6_SHIFT)) & DMA_ERQ_ERQ6_MASK) 2501 #define DMA_ERQ_ERQ7_MASK (0x80U) 2502 #define DMA_ERQ_ERQ7_SHIFT (7U) 2503 /*! ERQ7 - Enable DMA Request 7 2504 * 0b0..The DMA request signal for the corresponding channel is disabled 2505 * 0b1..The DMA request signal for the corresponding channel is enabled 2506 */ 2507 #define DMA_ERQ_ERQ7(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ7_SHIFT)) & DMA_ERQ_ERQ7_MASK) 2508 /*! @} */ 2509 2510 /*! @name EEI - Enable Error Interrupt Register */ 2511 /*! @{ */ 2512 #define DMA_EEI_EEI0_MASK (0x1U) 2513 #define DMA_EEI_EEI0_SHIFT (0U) 2514 /*! EEI0 - Enable Error Interrupt 0 2515 * 0b0..The error signal for corresponding channel does not generate an error interrupt 2516 * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request 2517 */ 2518 #define DMA_EEI_EEI0(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI0_SHIFT)) & DMA_EEI_EEI0_MASK) 2519 #define DMA_EEI_EEI1_MASK (0x2U) 2520 #define DMA_EEI_EEI1_SHIFT (1U) 2521 /*! EEI1 - Enable Error Interrupt 1 2522 * 0b0..The error signal for corresponding channel does not generate an error interrupt 2523 * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request 2524 */ 2525 #define DMA_EEI_EEI1(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI1_SHIFT)) & DMA_EEI_EEI1_MASK) 2526 #define DMA_EEI_EEI2_MASK (0x4U) 2527 #define DMA_EEI_EEI2_SHIFT (2U) 2528 /*! EEI2 - Enable Error Interrupt 2 2529 * 0b0..The error signal for corresponding channel does not generate an error interrupt 2530 * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request 2531 */ 2532 #define DMA_EEI_EEI2(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI2_SHIFT)) & DMA_EEI_EEI2_MASK) 2533 #define DMA_EEI_EEI3_MASK (0x8U) 2534 #define DMA_EEI_EEI3_SHIFT (3U) 2535 /*! EEI3 - Enable Error Interrupt 3 2536 * 0b0..The error signal for corresponding channel does not generate an error interrupt 2537 * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request 2538 */ 2539 #define DMA_EEI_EEI3(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI3_SHIFT)) & DMA_EEI_EEI3_MASK) 2540 #define DMA_EEI_EEI4_MASK (0x10U) 2541 #define DMA_EEI_EEI4_SHIFT (4U) 2542 /*! EEI4 - Enable Error Interrupt 4 2543 * 0b0..The error signal for corresponding channel does not generate an error interrupt 2544 * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request 2545 */ 2546 #define DMA_EEI_EEI4(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI4_SHIFT)) & DMA_EEI_EEI4_MASK) 2547 #define DMA_EEI_EEI5_MASK (0x20U) 2548 #define DMA_EEI_EEI5_SHIFT (5U) 2549 /*! EEI5 - Enable Error Interrupt 5 2550 * 0b0..The error signal for corresponding channel does not generate an error interrupt 2551 * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request 2552 */ 2553 #define DMA_EEI_EEI5(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI5_SHIFT)) & DMA_EEI_EEI5_MASK) 2554 #define DMA_EEI_EEI6_MASK (0x40U) 2555 #define DMA_EEI_EEI6_SHIFT (6U) 2556 /*! EEI6 - Enable Error Interrupt 6 2557 * 0b0..The error signal for corresponding channel does not generate an error interrupt 2558 * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request 2559 */ 2560 #define DMA_EEI_EEI6(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI6_SHIFT)) & DMA_EEI_EEI6_MASK) 2561 #define DMA_EEI_EEI7_MASK (0x80U) 2562 #define DMA_EEI_EEI7_SHIFT (7U) 2563 /*! EEI7 - Enable Error Interrupt 7 2564 * 0b0..The error signal for corresponding channel does not generate an error interrupt 2565 * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request 2566 */ 2567 #define DMA_EEI_EEI7(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI7_SHIFT)) & DMA_EEI_EEI7_MASK) 2568 /*! @} */ 2569 2570 /*! @name CEEI - Clear Enable Error Interrupt Register */ 2571 /*! @{ */ 2572 #define DMA_CEEI_CEEI_MASK (0x7U) 2573 #define DMA_CEEI_CEEI_SHIFT (0U) 2574 #define DMA_CEEI_CEEI(x) (((uint8_t)(((uint8_t)(x)) << DMA_CEEI_CEEI_SHIFT)) & DMA_CEEI_CEEI_MASK) 2575 #define DMA_CEEI_CAEE_MASK (0x40U) 2576 #define DMA_CEEI_CAEE_SHIFT (6U) 2577 /*! CAEE - Clear All Enable Error Interrupts 2578 * 0b0..Clear only the EEI bit specified in the CEEI field 2579 * 0b1..Clear all bits in EEI 2580 */ 2581 #define DMA_CEEI_CAEE(x) (((uint8_t)(((uint8_t)(x)) << DMA_CEEI_CAEE_SHIFT)) & DMA_CEEI_CAEE_MASK) 2582 #define DMA_CEEI_NOP_MASK (0x80U) 2583 #define DMA_CEEI_NOP_SHIFT (7U) 2584 /*! NOP - No Op enable 2585 * 0b0..Normal operation 2586 * 0b1..No operation, ignore the other bits in this register 2587 */ 2588 #define DMA_CEEI_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_CEEI_NOP_SHIFT)) & DMA_CEEI_NOP_MASK) 2589 /*! @} */ 2590 2591 /*! @name SEEI - Set Enable Error Interrupt Register */ 2592 /*! @{ */ 2593 #define DMA_SEEI_SEEI_MASK (0x7U) 2594 #define DMA_SEEI_SEEI_SHIFT (0U) 2595 #define DMA_SEEI_SEEI(x) (((uint8_t)(((uint8_t)(x)) << DMA_SEEI_SEEI_SHIFT)) & DMA_SEEI_SEEI_MASK) 2596 #define DMA_SEEI_SAEE_MASK (0x40U) 2597 #define DMA_SEEI_SAEE_SHIFT (6U) 2598 /*! SAEE - Sets All Enable Error Interrupts 2599 * 0b0..Set only the EEI bit specified in the SEEI field. 2600 * 0b1..Sets all bits in EEI 2601 */ 2602 #define DMA_SEEI_SAEE(x) (((uint8_t)(((uint8_t)(x)) << DMA_SEEI_SAEE_SHIFT)) & DMA_SEEI_SAEE_MASK) 2603 #define DMA_SEEI_NOP_MASK (0x80U) 2604 #define DMA_SEEI_NOP_SHIFT (7U) 2605 /*! NOP - No Op enable 2606 * 0b0..Normal operation 2607 * 0b1..No operation, ignore the other bits in this register 2608 */ 2609 #define DMA_SEEI_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_SEEI_NOP_SHIFT)) & DMA_SEEI_NOP_MASK) 2610 /*! @} */ 2611 2612 /*! @name CERQ - Clear Enable Request Register */ 2613 /*! @{ */ 2614 #define DMA_CERQ_CERQ_MASK (0x7U) 2615 #define DMA_CERQ_CERQ_SHIFT (0U) 2616 #define DMA_CERQ_CERQ(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERQ_CERQ_SHIFT)) & DMA_CERQ_CERQ_MASK) 2617 #define DMA_CERQ_CAER_MASK (0x40U) 2618 #define DMA_CERQ_CAER_SHIFT (6U) 2619 /*! CAER - Clear All Enable Requests 2620 * 0b0..Clear only the ERQ bit specified in the CERQ field 2621 * 0b1..Clear all bits in ERQ 2622 */ 2623 #define DMA_CERQ_CAER(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERQ_CAER_SHIFT)) & DMA_CERQ_CAER_MASK) 2624 #define DMA_CERQ_NOP_MASK (0x80U) 2625 #define DMA_CERQ_NOP_SHIFT (7U) 2626 /*! NOP - No Op enable 2627 * 0b0..Normal operation 2628 * 0b1..No operation, ignore the other bits in this register 2629 */ 2630 #define DMA_CERQ_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERQ_NOP_SHIFT)) & DMA_CERQ_NOP_MASK) 2631 /*! @} */ 2632 2633 /*! @name SERQ - Set Enable Request Register */ 2634 /*! @{ */ 2635 #define DMA_SERQ_SERQ_MASK (0x7U) 2636 #define DMA_SERQ_SERQ_SHIFT (0U) 2637 #define DMA_SERQ_SERQ(x) (((uint8_t)(((uint8_t)(x)) << DMA_SERQ_SERQ_SHIFT)) & DMA_SERQ_SERQ_MASK) 2638 #define DMA_SERQ_SAER_MASK (0x40U) 2639 #define DMA_SERQ_SAER_SHIFT (6U) 2640 /*! SAER - Set All Enable Requests 2641 * 0b0..Set only the ERQ bit specified in the SERQ field 2642 * 0b1..Set all bits in ERQ 2643 */ 2644 #define DMA_SERQ_SAER(x) (((uint8_t)(((uint8_t)(x)) << DMA_SERQ_SAER_SHIFT)) & DMA_SERQ_SAER_MASK) 2645 #define DMA_SERQ_NOP_MASK (0x80U) 2646 #define DMA_SERQ_NOP_SHIFT (7U) 2647 /*! NOP - No Op enable 2648 * 0b0..Normal operation 2649 * 0b1..No operation, ignore the other bits in this register 2650 */ 2651 #define DMA_SERQ_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_SERQ_NOP_SHIFT)) & DMA_SERQ_NOP_MASK) 2652 /*! @} */ 2653 2654 /*! @name CDNE - Clear DONE Status Bit Register */ 2655 /*! @{ */ 2656 #define DMA_CDNE_CDNE_MASK (0x7U) 2657 #define DMA_CDNE_CDNE_SHIFT (0U) 2658 #define DMA_CDNE_CDNE(x) (((uint8_t)(((uint8_t)(x)) << DMA_CDNE_CDNE_SHIFT)) & DMA_CDNE_CDNE_MASK) 2659 #define DMA_CDNE_CADN_MASK (0x40U) 2660 #define DMA_CDNE_CADN_SHIFT (6U) 2661 /*! CADN - Clears All DONE Bits 2662 * 0b0..Clears only the TCDn_CSR[DONE] bit specified in the CDNE field 2663 * 0b1..Clears all bits in TCDn_CSR[DONE] 2664 */ 2665 #define DMA_CDNE_CADN(x) (((uint8_t)(((uint8_t)(x)) << DMA_CDNE_CADN_SHIFT)) & DMA_CDNE_CADN_MASK) 2666 #define DMA_CDNE_NOP_MASK (0x80U) 2667 #define DMA_CDNE_NOP_SHIFT (7U) 2668 /*! NOP - No Op enable 2669 * 0b0..Normal operation 2670 * 0b1..No operation, ignore the other bits in this register 2671 */ 2672 #define DMA_CDNE_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_CDNE_NOP_SHIFT)) & DMA_CDNE_NOP_MASK) 2673 /*! @} */ 2674 2675 /*! @name SSRT - Set START Bit Register */ 2676 /*! @{ */ 2677 #define DMA_SSRT_SSRT_MASK (0x7U) 2678 #define DMA_SSRT_SSRT_SHIFT (0U) 2679 #define DMA_SSRT_SSRT(x) (((uint8_t)(((uint8_t)(x)) << DMA_SSRT_SSRT_SHIFT)) & DMA_SSRT_SSRT_MASK) 2680 #define DMA_SSRT_SAST_MASK (0x40U) 2681 #define DMA_SSRT_SAST_SHIFT (6U) 2682 /*! SAST - Set All START Bits (activates all channels) 2683 * 0b0..Set only the TCDn_CSR[START] bit specified in the SSRT field 2684 * 0b1..Set all bits in TCDn_CSR[START] 2685 */ 2686 #define DMA_SSRT_SAST(x) (((uint8_t)(((uint8_t)(x)) << DMA_SSRT_SAST_SHIFT)) & DMA_SSRT_SAST_MASK) 2687 #define DMA_SSRT_NOP_MASK (0x80U) 2688 #define DMA_SSRT_NOP_SHIFT (7U) 2689 /*! NOP - No Op enable 2690 * 0b0..Normal operation 2691 * 0b1..No operation, ignore the other bits in this register 2692 */ 2693 #define DMA_SSRT_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_SSRT_NOP_SHIFT)) & DMA_SSRT_NOP_MASK) 2694 /*! @} */ 2695 2696 /*! @name CERR - Clear Error Register */ 2697 /*! @{ */ 2698 #define DMA_CERR_CERR_MASK (0x7U) 2699 #define DMA_CERR_CERR_SHIFT (0U) 2700 #define DMA_CERR_CERR(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERR_CERR_SHIFT)) & DMA_CERR_CERR_MASK) 2701 #define DMA_CERR_CAEI_MASK (0x40U) 2702 #define DMA_CERR_CAEI_SHIFT (6U) 2703 /*! CAEI - Clear All Error Indicators 2704 * 0b0..Clear only the ERR bit specified in the CERR field 2705 * 0b1..Clear all bits in ERR 2706 */ 2707 #define DMA_CERR_CAEI(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERR_CAEI_SHIFT)) & DMA_CERR_CAEI_MASK) 2708 #define DMA_CERR_NOP_MASK (0x80U) 2709 #define DMA_CERR_NOP_SHIFT (7U) 2710 /*! NOP - No Op enable 2711 * 0b0..Normal operation 2712 * 0b1..No operation, ignore the other bits in this register 2713 */ 2714 #define DMA_CERR_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERR_NOP_SHIFT)) & DMA_CERR_NOP_MASK) 2715 /*! @} */ 2716 2717 /*! @name CINT - Clear Interrupt Request Register */ 2718 /*! @{ */ 2719 #define DMA_CINT_CINT_MASK (0x7U) 2720 #define DMA_CINT_CINT_SHIFT (0U) 2721 #define DMA_CINT_CINT(x) (((uint8_t)(((uint8_t)(x)) << DMA_CINT_CINT_SHIFT)) & DMA_CINT_CINT_MASK) 2722 #define DMA_CINT_CAIR_MASK (0x40U) 2723 #define DMA_CINT_CAIR_SHIFT (6U) 2724 /*! CAIR - Clear All Interrupt Requests 2725 * 0b0..Clear only the INT bit specified in the CINT field 2726 * 0b1..Clear all bits in INT 2727 */ 2728 #define DMA_CINT_CAIR(x) (((uint8_t)(((uint8_t)(x)) << DMA_CINT_CAIR_SHIFT)) & DMA_CINT_CAIR_MASK) 2729 #define DMA_CINT_NOP_MASK (0x80U) 2730 #define DMA_CINT_NOP_SHIFT (7U) 2731 /*! NOP - No Op enable 2732 * 0b0..Normal operation 2733 * 0b1..No operation, ignore the other bits in this register 2734 */ 2735 #define DMA_CINT_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_CINT_NOP_SHIFT)) & DMA_CINT_NOP_MASK) 2736 /*! @} */ 2737 2738 /*! @name INT - Interrupt Request Register */ 2739 /*! @{ */ 2740 #define DMA_INT_INT0_MASK (0x1U) 2741 #define DMA_INT_INT0_SHIFT (0U) 2742 /*! INT0 - Interrupt Request 0 2743 * 0b0..The interrupt request for corresponding channel is cleared 2744 * 0b1..The interrupt request for corresponding channel is active 2745 */ 2746 #define DMA_INT_INT0(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT0_SHIFT)) & DMA_INT_INT0_MASK) 2747 #define DMA_INT_INT1_MASK (0x2U) 2748 #define DMA_INT_INT1_SHIFT (1U) 2749 /*! INT1 - Interrupt Request 1 2750 * 0b0..The interrupt request for corresponding channel is cleared 2751 * 0b1..The interrupt request for corresponding channel is active 2752 */ 2753 #define DMA_INT_INT1(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT1_SHIFT)) & DMA_INT_INT1_MASK) 2754 #define DMA_INT_INT2_MASK (0x4U) 2755 #define DMA_INT_INT2_SHIFT (2U) 2756 /*! INT2 - Interrupt Request 2 2757 * 0b0..The interrupt request for corresponding channel is cleared 2758 * 0b1..The interrupt request for corresponding channel is active 2759 */ 2760 #define DMA_INT_INT2(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT2_SHIFT)) & DMA_INT_INT2_MASK) 2761 #define DMA_INT_INT3_MASK (0x8U) 2762 #define DMA_INT_INT3_SHIFT (3U) 2763 /*! INT3 - Interrupt Request 3 2764 * 0b0..The interrupt request for corresponding channel is cleared 2765 * 0b1..The interrupt request for corresponding channel is active 2766 */ 2767 #define DMA_INT_INT3(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT3_SHIFT)) & DMA_INT_INT3_MASK) 2768 #define DMA_INT_INT4_MASK (0x10U) 2769 #define DMA_INT_INT4_SHIFT (4U) 2770 /*! INT4 - Interrupt Request 4 2771 * 0b0..The interrupt request for corresponding channel is cleared 2772 * 0b1..The interrupt request for corresponding channel is active 2773 */ 2774 #define DMA_INT_INT4(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT4_SHIFT)) & DMA_INT_INT4_MASK) 2775 #define DMA_INT_INT5_MASK (0x20U) 2776 #define DMA_INT_INT5_SHIFT (5U) 2777 /*! INT5 - Interrupt Request 5 2778 * 0b0..The interrupt request for corresponding channel is cleared 2779 * 0b1..The interrupt request for corresponding channel is active 2780 */ 2781 #define DMA_INT_INT5(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT5_SHIFT)) & DMA_INT_INT5_MASK) 2782 #define DMA_INT_INT6_MASK (0x40U) 2783 #define DMA_INT_INT6_SHIFT (6U) 2784 /*! INT6 - Interrupt Request 6 2785 * 0b0..The interrupt request for corresponding channel is cleared 2786 * 0b1..The interrupt request for corresponding channel is active 2787 */ 2788 #define DMA_INT_INT6(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT6_SHIFT)) & DMA_INT_INT6_MASK) 2789 #define DMA_INT_INT7_MASK (0x80U) 2790 #define DMA_INT_INT7_SHIFT (7U) 2791 /*! INT7 - Interrupt Request 7 2792 * 0b0..The interrupt request for corresponding channel is cleared 2793 * 0b1..The interrupt request for corresponding channel is active 2794 */ 2795 #define DMA_INT_INT7(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT7_SHIFT)) & DMA_INT_INT7_MASK) 2796 /*! @} */ 2797 2798 /*! @name ERR - Error Register */ 2799 /*! @{ */ 2800 #define DMA_ERR_ERR0_MASK (0x1U) 2801 #define DMA_ERR_ERR0_SHIFT (0U) 2802 /*! ERR0 - Error In Channel 0 2803 * 0b0..An error in this channel has not occurred 2804 * 0b1..An error in this channel has occurred 2805 */ 2806 #define DMA_ERR_ERR0(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR0_SHIFT)) & DMA_ERR_ERR0_MASK) 2807 #define DMA_ERR_ERR1_MASK (0x2U) 2808 #define DMA_ERR_ERR1_SHIFT (1U) 2809 /*! ERR1 - Error In Channel 1 2810 * 0b0..An error in this channel has not occurred 2811 * 0b1..An error in this channel has occurred 2812 */ 2813 #define DMA_ERR_ERR1(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR1_SHIFT)) & DMA_ERR_ERR1_MASK) 2814 #define DMA_ERR_ERR2_MASK (0x4U) 2815 #define DMA_ERR_ERR2_SHIFT (2U) 2816 /*! ERR2 - Error In Channel 2 2817 * 0b0..An error in this channel has not occurred 2818 * 0b1..An error in this channel has occurred 2819 */ 2820 #define DMA_ERR_ERR2(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR2_SHIFT)) & DMA_ERR_ERR2_MASK) 2821 #define DMA_ERR_ERR3_MASK (0x8U) 2822 #define DMA_ERR_ERR3_SHIFT (3U) 2823 /*! ERR3 - Error In Channel 3 2824 * 0b0..An error in this channel has not occurred 2825 * 0b1..An error in this channel has occurred 2826 */ 2827 #define DMA_ERR_ERR3(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR3_SHIFT)) & DMA_ERR_ERR3_MASK) 2828 #define DMA_ERR_ERR4_MASK (0x10U) 2829 #define DMA_ERR_ERR4_SHIFT (4U) 2830 /*! ERR4 - Error In Channel 4 2831 * 0b0..An error in this channel has not occurred 2832 * 0b1..An error in this channel has occurred 2833 */ 2834 #define DMA_ERR_ERR4(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR4_SHIFT)) & DMA_ERR_ERR4_MASK) 2835 #define DMA_ERR_ERR5_MASK (0x20U) 2836 #define DMA_ERR_ERR5_SHIFT (5U) 2837 /*! ERR5 - Error In Channel 5 2838 * 0b0..An error in this channel has not occurred 2839 * 0b1..An error in this channel has occurred 2840 */ 2841 #define DMA_ERR_ERR5(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR5_SHIFT)) & DMA_ERR_ERR5_MASK) 2842 #define DMA_ERR_ERR6_MASK (0x40U) 2843 #define DMA_ERR_ERR6_SHIFT (6U) 2844 /*! ERR6 - Error In Channel 6 2845 * 0b0..An error in this channel has not occurred 2846 * 0b1..An error in this channel has occurred 2847 */ 2848 #define DMA_ERR_ERR6(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR6_SHIFT)) & DMA_ERR_ERR6_MASK) 2849 #define DMA_ERR_ERR7_MASK (0x80U) 2850 #define DMA_ERR_ERR7_SHIFT (7U) 2851 /*! ERR7 - Error In Channel 7 2852 * 0b0..An error in this channel has not occurred 2853 * 0b1..An error in this channel has occurred 2854 */ 2855 #define DMA_ERR_ERR7(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR7_SHIFT)) & DMA_ERR_ERR7_MASK) 2856 /*! @} */ 2857 2858 /*! @name HRS - Hardware Request Status Register */ 2859 /*! @{ */ 2860 #define DMA_HRS_HRS0_MASK (0x1U) 2861 #define DMA_HRS_HRS0_SHIFT (0U) 2862 /*! HRS0 - Hardware Request Status Channel 0 2863 * 0b0..A hardware service request for channel 0 is not present 2864 * 0b1..A hardware service request for channel 0 is present 2865 */ 2866 #define DMA_HRS_HRS0(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS0_SHIFT)) & DMA_HRS_HRS0_MASK) 2867 #define DMA_HRS_HRS1_MASK (0x2U) 2868 #define DMA_HRS_HRS1_SHIFT (1U) 2869 /*! HRS1 - Hardware Request Status Channel 1 2870 * 0b0..A hardware service request for channel 1 is not present 2871 * 0b1..A hardware service request for channel 1 is present 2872 */ 2873 #define DMA_HRS_HRS1(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS1_SHIFT)) & DMA_HRS_HRS1_MASK) 2874 #define DMA_HRS_HRS2_MASK (0x4U) 2875 #define DMA_HRS_HRS2_SHIFT (2U) 2876 /*! HRS2 - Hardware Request Status Channel 2 2877 * 0b0..A hardware service request for channel 2 is not present 2878 * 0b1..A hardware service request for channel 2 is present 2879 */ 2880 #define DMA_HRS_HRS2(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS2_SHIFT)) & DMA_HRS_HRS2_MASK) 2881 #define DMA_HRS_HRS3_MASK (0x8U) 2882 #define DMA_HRS_HRS3_SHIFT (3U) 2883 /*! HRS3 - Hardware Request Status Channel 3 2884 * 0b0..A hardware service request for channel 3 is not present 2885 * 0b1..A hardware service request for channel 3 is present 2886 */ 2887 #define DMA_HRS_HRS3(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS3_SHIFT)) & DMA_HRS_HRS3_MASK) 2888 #define DMA_HRS_HRS4_MASK (0x10U) 2889 #define DMA_HRS_HRS4_SHIFT (4U) 2890 /*! HRS4 - Hardware Request Status Channel 4 2891 * 0b0..A hardware service request for channel 4 is not present 2892 * 0b1..A hardware service request for channel 4 is present 2893 */ 2894 #define DMA_HRS_HRS4(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS4_SHIFT)) & DMA_HRS_HRS4_MASK) 2895 #define DMA_HRS_HRS5_MASK (0x20U) 2896 #define DMA_HRS_HRS5_SHIFT (5U) 2897 /*! HRS5 - Hardware Request Status Channel 5 2898 * 0b0..A hardware service request for channel 5 is not present 2899 * 0b1..A hardware service request for channel 5 is present 2900 */ 2901 #define DMA_HRS_HRS5(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS5_SHIFT)) & DMA_HRS_HRS5_MASK) 2902 #define DMA_HRS_HRS6_MASK (0x40U) 2903 #define DMA_HRS_HRS6_SHIFT (6U) 2904 /*! HRS6 - Hardware Request Status Channel 6 2905 * 0b0..A hardware service request for channel 6 is not present 2906 * 0b1..A hardware service request for channel 6 is present 2907 */ 2908 #define DMA_HRS_HRS6(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS6_SHIFT)) & DMA_HRS_HRS6_MASK) 2909 #define DMA_HRS_HRS7_MASK (0x80U) 2910 #define DMA_HRS_HRS7_SHIFT (7U) 2911 /*! HRS7 - Hardware Request Status Channel 7 2912 * 0b0..A hardware service request for channel 7 is not present 2913 * 0b1..A hardware service request for channel 7 is present 2914 */ 2915 #define DMA_HRS_HRS7(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS7_SHIFT)) & DMA_HRS_HRS7_MASK) 2916 /*! @} */ 2917 2918 /*! @name EARS - Enable Asynchronous Request in Stop Register */ 2919 /*! @{ */ 2920 #define DMA_EARS_EDREQ_0_MASK (0x1U) 2921 #define DMA_EARS_EDREQ_0_SHIFT (0U) 2922 /*! EDREQ_0 - Enable asynchronous DMA request in stop mode for channel 0. 2923 * 0b0..Disable asynchronous DMA request for channel 0. 2924 * 0b1..Enable asynchronous DMA request for channel 0. 2925 */ 2926 #define DMA_EARS_EDREQ_0(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_0_SHIFT)) & DMA_EARS_EDREQ_0_MASK) 2927 #define DMA_EARS_EDREQ_1_MASK (0x2U) 2928 #define DMA_EARS_EDREQ_1_SHIFT (1U) 2929 /*! EDREQ_1 - Enable asynchronous DMA request in stop mode for channel 1. 2930 * 0b0..Disable asynchronous DMA request for channel 1 2931 * 0b1..Enable asynchronous DMA request for channel 1. 2932 */ 2933 #define DMA_EARS_EDREQ_1(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_1_SHIFT)) & DMA_EARS_EDREQ_1_MASK) 2934 #define DMA_EARS_EDREQ_2_MASK (0x4U) 2935 #define DMA_EARS_EDREQ_2_SHIFT (2U) 2936 /*! EDREQ_2 - Enable asynchronous DMA request in stop mode for channel 2. 2937 * 0b0..Disable asynchronous DMA request for channel 2. 2938 * 0b1..Enable asynchronous DMA request for channel 2. 2939 */ 2940 #define DMA_EARS_EDREQ_2(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_2_SHIFT)) & DMA_EARS_EDREQ_2_MASK) 2941 #define DMA_EARS_EDREQ_3_MASK (0x8U) 2942 #define DMA_EARS_EDREQ_3_SHIFT (3U) 2943 /*! EDREQ_3 - Enable asynchronous DMA request in stop mode for channel 3. 2944 * 0b0..Disable asynchronous DMA request for channel 3. 2945 * 0b1..Enable asynchronous DMA request for channel 3. 2946 */ 2947 #define DMA_EARS_EDREQ_3(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_3_SHIFT)) & DMA_EARS_EDREQ_3_MASK) 2948 #define DMA_EARS_EDREQ_4_MASK (0x10U) 2949 #define DMA_EARS_EDREQ_4_SHIFT (4U) 2950 /*! EDREQ_4 - Enable asynchronous DMA request in stop mode for channel 4 2951 * 0b0..Disable asynchronous DMA request for channel 4. 2952 * 0b1..Enable asynchronous DMA request for channel 4. 2953 */ 2954 #define DMA_EARS_EDREQ_4(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_4_SHIFT)) & DMA_EARS_EDREQ_4_MASK) 2955 #define DMA_EARS_EDREQ_5_MASK (0x20U) 2956 #define DMA_EARS_EDREQ_5_SHIFT (5U) 2957 /*! EDREQ_5 - Enable asynchronous DMA request in stop mode for channel 5 2958 * 0b0..Disable asynchronous DMA request for channel 5. 2959 * 0b1..Enable asynchronous DMA request for channel 5. 2960 */ 2961 #define DMA_EARS_EDREQ_5(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_5_SHIFT)) & DMA_EARS_EDREQ_5_MASK) 2962 #define DMA_EARS_EDREQ_6_MASK (0x40U) 2963 #define DMA_EARS_EDREQ_6_SHIFT (6U) 2964 /*! EDREQ_6 - Enable asynchronous DMA request in stop mode for channel 6 2965 * 0b0..Disable asynchronous DMA request for channel 6. 2966 * 0b1..Enable asynchronous DMA request for channel 6. 2967 */ 2968 #define DMA_EARS_EDREQ_6(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_6_SHIFT)) & DMA_EARS_EDREQ_6_MASK) 2969 #define DMA_EARS_EDREQ_7_MASK (0x80U) 2970 #define DMA_EARS_EDREQ_7_SHIFT (7U) 2971 /*! EDREQ_7 - Enable asynchronous DMA request in stop mode for channel 7 2972 * 0b0..Disable asynchronous DMA request for channel 7. 2973 * 0b1..Enable asynchronous DMA request for channel 7. 2974 */ 2975 #define DMA_EARS_EDREQ_7(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_7_SHIFT)) & DMA_EARS_EDREQ_7_MASK) 2976 /*! @} */ 2977 2978 /*! @name DCHPRI3 - Channel n Priority Register */ 2979 /*! @{ */ 2980 #define DMA_DCHPRI3_CHPRI_MASK (0x7U) 2981 #define DMA_DCHPRI3_CHPRI_SHIFT (0U) 2982 #define DMA_DCHPRI3_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI3_CHPRI_SHIFT)) & DMA_DCHPRI3_CHPRI_MASK) 2983 #define DMA_DCHPRI3_DPA_MASK (0x40U) 2984 #define DMA_DCHPRI3_DPA_SHIFT (6U) 2985 /*! DPA - Disable Preempt Ability. 2986 * 0b0..Channel n can suspend a lower priority channel. 2987 * 0b1..Channel n cannot suspend any channel, regardless of channel priority. 2988 */ 2989 #define DMA_DCHPRI3_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI3_DPA_SHIFT)) & DMA_DCHPRI3_DPA_MASK) 2990 #define DMA_DCHPRI3_ECP_MASK (0x80U) 2991 #define DMA_DCHPRI3_ECP_SHIFT (7U) 2992 /*! ECP - Enable Channel Preemption. 2993 * 0b0..Channel n cannot be suspended by a higher priority channel's service request. 2994 * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel. 2995 */ 2996 #define DMA_DCHPRI3_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI3_ECP_SHIFT)) & DMA_DCHPRI3_ECP_MASK) 2997 /*! @} */ 2998 2999 /*! @name DCHPRI2 - Channel n Priority Register */ 3000 /*! @{ */ 3001 #define DMA_DCHPRI2_CHPRI_MASK (0x7U) 3002 #define DMA_DCHPRI2_CHPRI_SHIFT (0U) 3003 #define DMA_DCHPRI2_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI2_CHPRI_SHIFT)) & DMA_DCHPRI2_CHPRI_MASK) 3004 #define DMA_DCHPRI2_DPA_MASK (0x40U) 3005 #define DMA_DCHPRI2_DPA_SHIFT (6U) 3006 /*! DPA - Disable Preempt Ability. 3007 * 0b0..Channel n can suspend a lower priority channel. 3008 * 0b1..Channel n cannot suspend any channel, regardless of channel priority. 3009 */ 3010 #define DMA_DCHPRI2_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI2_DPA_SHIFT)) & DMA_DCHPRI2_DPA_MASK) 3011 #define DMA_DCHPRI2_ECP_MASK (0x80U) 3012 #define DMA_DCHPRI2_ECP_SHIFT (7U) 3013 /*! ECP - Enable Channel Preemption. 3014 * 0b0..Channel n cannot be suspended by a higher priority channel's service request. 3015 * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel. 3016 */ 3017 #define DMA_DCHPRI2_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI2_ECP_SHIFT)) & DMA_DCHPRI2_ECP_MASK) 3018 /*! @} */ 3019 3020 /*! @name DCHPRI1 - Channel n Priority Register */ 3021 /*! @{ */ 3022 #define DMA_DCHPRI1_CHPRI_MASK (0x7U) 3023 #define DMA_DCHPRI1_CHPRI_SHIFT (0U) 3024 #define DMA_DCHPRI1_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI1_CHPRI_SHIFT)) & DMA_DCHPRI1_CHPRI_MASK) 3025 #define DMA_DCHPRI1_DPA_MASK (0x40U) 3026 #define DMA_DCHPRI1_DPA_SHIFT (6U) 3027 /*! DPA - Disable Preempt Ability. 3028 * 0b0..Channel n can suspend a lower priority channel. 3029 * 0b1..Channel n cannot suspend any channel, regardless of channel priority. 3030 */ 3031 #define DMA_DCHPRI1_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI1_DPA_SHIFT)) & DMA_DCHPRI1_DPA_MASK) 3032 #define DMA_DCHPRI1_ECP_MASK (0x80U) 3033 #define DMA_DCHPRI1_ECP_SHIFT (7U) 3034 /*! ECP - Enable Channel Preemption. 3035 * 0b0..Channel n cannot be suspended by a higher priority channel's service request. 3036 * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel. 3037 */ 3038 #define DMA_DCHPRI1_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI1_ECP_SHIFT)) & DMA_DCHPRI1_ECP_MASK) 3039 /*! @} */ 3040 3041 /*! @name DCHPRI0 - Channel n Priority Register */ 3042 /*! @{ */ 3043 #define DMA_DCHPRI0_CHPRI_MASK (0x7U) 3044 #define DMA_DCHPRI0_CHPRI_SHIFT (0U) 3045 #define DMA_DCHPRI0_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI0_CHPRI_SHIFT)) & DMA_DCHPRI0_CHPRI_MASK) 3046 #define DMA_DCHPRI0_DPA_MASK (0x40U) 3047 #define DMA_DCHPRI0_DPA_SHIFT (6U) 3048 /*! DPA - Disable Preempt Ability. 3049 * 0b0..Channel n can suspend a lower priority channel. 3050 * 0b1..Channel n cannot suspend any channel, regardless of channel priority. 3051 */ 3052 #define DMA_DCHPRI0_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI0_DPA_SHIFT)) & DMA_DCHPRI0_DPA_MASK) 3053 #define DMA_DCHPRI0_ECP_MASK (0x80U) 3054 #define DMA_DCHPRI0_ECP_SHIFT (7U) 3055 /*! ECP - Enable Channel Preemption. 3056 * 0b0..Channel n cannot be suspended by a higher priority channel's service request. 3057 * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel. 3058 */ 3059 #define DMA_DCHPRI0_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI0_ECP_SHIFT)) & DMA_DCHPRI0_ECP_MASK) 3060 /*! @} */ 3061 3062 /*! @name DCHPRI7 - Channel n Priority Register */ 3063 /*! @{ */ 3064 #define DMA_DCHPRI7_CHPRI_MASK (0x7U) 3065 #define DMA_DCHPRI7_CHPRI_SHIFT (0U) 3066 #define DMA_DCHPRI7_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI7_CHPRI_SHIFT)) & DMA_DCHPRI7_CHPRI_MASK) 3067 #define DMA_DCHPRI7_DPA_MASK (0x40U) 3068 #define DMA_DCHPRI7_DPA_SHIFT (6U) 3069 /*! DPA - Disable Preempt Ability. 3070 * 0b0..Channel n can suspend a lower priority channel. 3071 * 0b1..Channel n cannot suspend any channel, regardless of channel priority. 3072 */ 3073 #define DMA_DCHPRI7_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI7_DPA_SHIFT)) & DMA_DCHPRI7_DPA_MASK) 3074 #define DMA_DCHPRI7_ECP_MASK (0x80U) 3075 #define DMA_DCHPRI7_ECP_SHIFT (7U) 3076 /*! ECP - Enable Channel Preemption. 3077 * 0b0..Channel n cannot be suspended by a higher priority channel's service request. 3078 * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel. 3079 */ 3080 #define DMA_DCHPRI7_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI7_ECP_SHIFT)) & DMA_DCHPRI7_ECP_MASK) 3081 /*! @} */ 3082 3083 /*! @name DCHPRI6 - Channel n Priority Register */ 3084 /*! @{ */ 3085 #define DMA_DCHPRI6_CHPRI_MASK (0x7U) 3086 #define DMA_DCHPRI6_CHPRI_SHIFT (0U) 3087 #define DMA_DCHPRI6_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI6_CHPRI_SHIFT)) & DMA_DCHPRI6_CHPRI_MASK) 3088 #define DMA_DCHPRI6_DPA_MASK (0x40U) 3089 #define DMA_DCHPRI6_DPA_SHIFT (6U) 3090 /*! DPA - Disable Preempt Ability. 3091 * 0b0..Channel n can suspend a lower priority channel. 3092 * 0b1..Channel n cannot suspend any channel, regardless of channel priority. 3093 */ 3094 #define DMA_DCHPRI6_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI6_DPA_SHIFT)) & DMA_DCHPRI6_DPA_MASK) 3095 #define DMA_DCHPRI6_ECP_MASK (0x80U) 3096 #define DMA_DCHPRI6_ECP_SHIFT (7U) 3097 /*! ECP - Enable Channel Preemption. 3098 * 0b0..Channel n cannot be suspended by a higher priority channel's service request. 3099 * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel. 3100 */ 3101 #define DMA_DCHPRI6_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI6_ECP_SHIFT)) & DMA_DCHPRI6_ECP_MASK) 3102 /*! @} */ 3103 3104 /*! @name DCHPRI5 - Channel n Priority Register */ 3105 /*! @{ */ 3106 #define DMA_DCHPRI5_CHPRI_MASK (0x7U) 3107 #define DMA_DCHPRI5_CHPRI_SHIFT (0U) 3108 #define DMA_DCHPRI5_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI5_CHPRI_SHIFT)) & DMA_DCHPRI5_CHPRI_MASK) 3109 #define DMA_DCHPRI5_DPA_MASK (0x40U) 3110 #define DMA_DCHPRI5_DPA_SHIFT (6U) 3111 /*! DPA - Disable Preempt Ability. 3112 * 0b0..Channel n can suspend a lower priority channel. 3113 * 0b1..Channel n cannot suspend any channel, regardless of channel priority. 3114 */ 3115 #define DMA_DCHPRI5_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI5_DPA_SHIFT)) & DMA_DCHPRI5_DPA_MASK) 3116 #define DMA_DCHPRI5_ECP_MASK (0x80U) 3117 #define DMA_DCHPRI5_ECP_SHIFT (7U) 3118 /*! ECP - Enable Channel Preemption. 3119 * 0b0..Channel n cannot be suspended by a higher priority channel's service request. 3120 * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel. 3121 */ 3122 #define DMA_DCHPRI5_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI5_ECP_SHIFT)) & DMA_DCHPRI5_ECP_MASK) 3123 /*! @} */ 3124 3125 /*! @name DCHPRI4 - Channel n Priority Register */ 3126 /*! @{ */ 3127 #define DMA_DCHPRI4_CHPRI_MASK (0x7U) 3128 #define DMA_DCHPRI4_CHPRI_SHIFT (0U) 3129 #define DMA_DCHPRI4_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI4_CHPRI_SHIFT)) & DMA_DCHPRI4_CHPRI_MASK) 3130 #define DMA_DCHPRI4_DPA_MASK (0x40U) 3131 #define DMA_DCHPRI4_DPA_SHIFT (6U) 3132 /*! DPA - Disable Preempt Ability. 3133 * 0b0..Channel n can suspend a lower priority channel. 3134 * 0b1..Channel n cannot suspend any channel, regardless of channel priority. 3135 */ 3136 #define DMA_DCHPRI4_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI4_DPA_SHIFT)) & DMA_DCHPRI4_DPA_MASK) 3137 #define DMA_DCHPRI4_ECP_MASK (0x80U) 3138 #define DMA_DCHPRI4_ECP_SHIFT (7U) 3139 /*! ECP - Enable Channel Preemption. 3140 * 0b0..Channel n cannot be suspended by a higher priority channel's service request. 3141 * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel. 3142 */ 3143 #define DMA_DCHPRI4_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI4_ECP_SHIFT)) & DMA_DCHPRI4_ECP_MASK) 3144 /*! @} */ 3145 3146 /*! @name SADDR - TCD Source Address */ 3147 /*! @{ */ 3148 #define DMA_SADDR_SADDR_MASK (0xFFFFFFFFU) 3149 #define DMA_SADDR_SADDR_SHIFT (0U) 3150 #define DMA_SADDR_SADDR(x) (((uint32_t)(((uint32_t)(x)) << DMA_SADDR_SADDR_SHIFT)) & DMA_SADDR_SADDR_MASK) 3151 /*! @} */ 3152 3153 /* The count of DMA_SADDR */ 3154 #define DMA_SADDR_COUNT (8U) 3155 3156 /*! @name SOFF - TCD Signed Source Address Offset */ 3157 /*! @{ */ 3158 #define DMA_SOFF_SOFF_MASK (0xFFFFU) 3159 #define DMA_SOFF_SOFF_SHIFT (0U) 3160 #define DMA_SOFF_SOFF(x) (((uint16_t)(((uint16_t)(x)) << DMA_SOFF_SOFF_SHIFT)) & DMA_SOFF_SOFF_MASK) 3161 /*! @} */ 3162 3163 /* The count of DMA_SOFF */ 3164 #define DMA_SOFF_COUNT (8U) 3165 3166 /*! @name ATTR - TCD Transfer Attributes */ 3167 /*! @{ */ 3168 #define DMA_ATTR_DSIZE_MASK (0x7U) 3169 #define DMA_ATTR_DSIZE_SHIFT (0U) 3170 #define DMA_ATTR_DSIZE(x) (((uint16_t)(((uint16_t)(x)) << DMA_ATTR_DSIZE_SHIFT)) & DMA_ATTR_DSIZE_MASK) 3171 #define DMA_ATTR_DMOD_MASK (0xF8U) 3172 #define DMA_ATTR_DMOD_SHIFT (3U) 3173 #define DMA_ATTR_DMOD(x) (((uint16_t)(((uint16_t)(x)) << DMA_ATTR_DMOD_SHIFT)) & DMA_ATTR_DMOD_MASK) 3174 #define DMA_ATTR_SSIZE_MASK (0x700U) 3175 #define DMA_ATTR_SSIZE_SHIFT (8U) 3176 /*! SSIZE - Source data transfer size 3177 * 0b000..8-bit 3178 * 0b001..16-bit 3179 * 0b010..32-bit 3180 * 0b011..Reserved 3181 * 0b100..16-byte 3182 * 0b101..32-byte 3183 * 0b110..Reserved 3184 * 0b111..Reserved 3185 */ 3186 #define DMA_ATTR_SSIZE(x) (((uint16_t)(((uint16_t)(x)) << DMA_ATTR_SSIZE_SHIFT)) & DMA_ATTR_SSIZE_MASK) 3187 #define DMA_ATTR_SMOD_MASK (0xF800U) 3188 #define DMA_ATTR_SMOD_SHIFT (11U) 3189 /*! SMOD - Source Address Modulo 3190 * 0b00000..Source address modulo feature is disabled 3191 */ 3192 #define DMA_ATTR_SMOD(x) (((uint16_t)(((uint16_t)(x)) << DMA_ATTR_SMOD_SHIFT)) & DMA_ATTR_SMOD_MASK) 3193 /*! @} */ 3194 3195 /* The count of DMA_ATTR */ 3196 #define DMA_ATTR_COUNT (8U) 3197 3198 /*! @name NBYTES_MLNO - TCD Minor Byte Count (Minor Loop Mapping Disabled) */ 3199 /*! @{ */ 3200 #define DMA_NBYTES_MLNO_NBYTES_MASK (0xFFFFFFFFU) 3201 #define DMA_NBYTES_MLNO_NBYTES_SHIFT (0U) 3202 #define DMA_NBYTES_MLNO_NBYTES(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLNO_NBYTES_SHIFT)) & DMA_NBYTES_MLNO_NBYTES_MASK) 3203 /*! @} */ 3204 3205 /* The count of DMA_NBYTES_MLNO */ 3206 #define DMA_NBYTES_MLNO_COUNT (8U) 3207 3208 /*! @name NBYTES_MLOFFNO - TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled) */ 3209 /*! @{ */ 3210 #define DMA_NBYTES_MLOFFNO_NBYTES_MASK (0x3FFFFFFFU) 3211 #define DMA_NBYTES_MLOFFNO_NBYTES_SHIFT (0U) 3212 #define DMA_NBYTES_MLOFFNO_NBYTES(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFNO_NBYTES_SHIFT)) & DMA_NBYTES_MLOFFNO_NBYTES_MASK) 3213 #define DMA_NBYTES_MLOFFNO_DMLOE_MASK (0x40000000U) 3214 #define DMA_NBYTES_MLOFFNO_DMLOE_SHIFT (30U) 3215 /*! DMLOE - Destination Minor Loop Offset enable 3216 * 0b0..The minor loop offset is not applied to the DADDR 3217 * 0b1..The minor loop offset is applied to the DADDR 3218 */ 3219 #define DMA_NBYTES_MLOFFNO_DMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFNO_DMLOE_SHIFT)) & DMA_NBYTES_MLOFFNO_DMLOE_MASK) 3220 #define DMA_NBYTES_MLOFFNO_SMLOE_MASK (0x80000000U) 3221 #define DMA_NBYTES_MLOFFNO_SMLOE_SHIFT (31U) 3222 /*! SMLOE - Source Minor Loop Offset Enable 3223 * 0b0..The minor loop offset is not applied to the SADDR 3224 * 0b1..The minor loop offset is applied to the SADDR 3225 */ 3226 #define DMA_NBYTES_MLOFFNO_SMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFNO_SMLOE_SHIFT)) & DMA_NBYTES_MLOFFNO_SMLOE_MASK) 3227 /*! @} */ 3228 3229 /* The count of DMA_NBYTES_MLOFFNO */ 3230 #define DMA_NBYTES_MLOFFNO_COUNT (8U) 3231 3232 /*! @name NBYTES_MLOFFYES - TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled) */ 3233 /*! @{ */ 3234 #define DMA_NBYTES_MLOFFYES_NBYTES_MASK (0x3FFU) 3235 #define DMA_NBYTES_MLOFFYES_NBYTES_SHIFT (0U) 3236 #define DMA_NBYTES_MLOFFYES_NBYTES(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFYES_NBYTES_SHIFT)) & DMA_NBYTES_MLOFFYES_NBYTES_MASK) 3237 #define DMA_NBYTES_MLOFFYES_MLOFF_MASK (0x3FFFFC00U) 3238 #define DMA_NBYTES_MLOFFYES_MLOFF_SHIFT (10U) 3239 #define DMA_NBYTES_MLOFFYES_MLOFF(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFYES_MLOFF_SHIFT)) & DMA_NBYTES_MLOFFYES_MLOFF_MASK) 3240 #define DMA_NBYTES_MLOFFYES_DMLOE_MASK (0x40000000U) 3241 #define DMA_NBYTES_MLOFFYES_DMLOE_SHIFT (30U) 3242 /*! DMLOE - Destination Minor Loop Offset enable 3243 * 0b0..The minor loop offset is not applied to the DADDR 3244 * 0b1..The minor loop offset is applied to the DADDR 3245 */ 3246 #define DMA_NBYTES_MLOFFYES_DMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFYES_DMLOE_SHIFT)) & DMA_NBYTES_MLOFFYES_DMLOE_MASK) 3247 #define DMA_NBYTES_MLOFFYES_SMLOE_MASK (0x80000000U) 3248 #define DMA_NBYTES_MLOFFYES_SMLOE_SHIFT (31U) 3249 /*! SMLOE - Source Minor Loop Offset Enable 3250 * 0b0..The minor loop offset is not applied to the SADDR 3251 * 0b1..The minor loop offset is applied to the SADDR 3252 */ 3253 #define DMA_NBYTES_MLOFFYES_SMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFYES_SMLOE_SHIFT)) & DMA_NBYTES_MLOFFYES_SMLOE_MASK) 3254 /*! @} */ 3255 3256 /* The count of DMA_NBYTES_MLOFFYES */ 3257 #define DMA_NBYTES_MLOFFYES_COUNT (8U) 3258 3259 /*! @name SLAST - TCD Last Source Address Adjustment */ 3260 /*! @{ */ 3261 #define DMA_SLAST_SLAST_MASK (0xFFFFFFFFU) 3262 #define DMA_SLAST_SLAST_SHIFT (0U) 3263 #define DMA_SLAST_SLAST(x) (((uint32_t)(((uint32_t)(x)) << DMA_SLAST_SLAST_SHIFT)) & DMA_SLAST_SLAST_MASK) 3264 /*! @} */ 3265 3266 /* The count of DMA_SLAST */ 3267 #define DMA_SLAST_COUNT (8U) 3268 3269 /*! @name DADDR - TCD Destination Address */ 3270 /*! @{ */ 3271 #define DMA_DADDR_DADDR_MASK (0xFFFFFFFFU) 3272 #define DMA_DADDR_DADDR_SHIFT (0U) 3273 #define DMA_DADDR_DADDR(x) (((uint32_t)(((uint32_t)(x)) << DMA_DADDR_DADDR_SHIFT)) & DMA_DADDR_DADDR_MASK) 3274 /*! @} */ 3275 3276 /* The count of DMA_DADDR */ 3277 #define DMA_DADDR_COUNT (8U) 3278 3279 /*! @name DOFF - TCD Signed Destination Address Offset */ 3280 /*! @{ */ 3281 #define DMA_DOFF_DOFF_MASK (0xFFFFU) 3282 #define DMA_DOFF_DOFF_SHIFT (0U) 3283 #define DMA_DOFF_DOFF(x) (((uint16_t)(((uint16_t)(x)) << DMA_DOFF_DOFF_SHIFT)) & DMA_DOFF_DOFF_MASK) 3284 /*! @} */ 3285 3286 /* The count of DMA_DOFF */ 3287 #define DMA_DOFF_COUNT (8U) 3288 3289 /*! @name CITER_ELINKNO - TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) */ 3290 /*! @{ */ 3291 #define DMA_CITER_ELINKNO_CITER_MASK (0x7FFFU) 3292 #define DMA_CITER_ELINKNO_CITER_SHIFT (0U) 3293 #define DMA_CITER_ELINKNO_CITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKNO_CITER_SHIFT)) & DMA_CITER_ELINKNO_CITER_MASK) 3294 #define DMA_CITER_ELINKNO_ELINK_MASK (0x8000U) 3295 #define DMA_CITER_ELINKNO_ELINK_SHIFT (15U) 3296 /*! ELINK - Enable channel-to-channel linking on minor-loop complete 3297 * 0b0..The channel-to-channel linking is disabled 3298 * 0b1..The channel-to-channel linking is enabled 3299 */ 3300 #define DMA_CITER_ELINKNO_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKNO_ELINK_SHIFT)) & DMA_CITER_ELINKNO_ELINK_MASK) 3301 /*! @} */ 3302 3303 /* The count of DMA_CITER_ELINKNO */ 3304 #define DMA_CITER_ELINKNO_COUNT (8U) 3305 3306 /*! @name CITER_ELINKYES - TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) */ 3307 /*! @{ */ 3308 #define DMA_CITER_ELINKYES_CITER_MASK (0x1FFU) 3309 #define DMA_CITER_ELINKYES_CITER_SHIFT (0U) 3310 #define DMA_CITER_ELINKYES_CITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKYES_CITER_SHIFT)) & DMA_CITER_ELINKYES_CITER_MASK) 3311 #define DMA_CITER_ELINKYES_LINKCH_MASK (0xE00U) 3312 #define DMA_CITER_ELINKYES_LINKCH_SHIFT (9U) 3313 #define DMA_CITER_ELINKYES_LINKCH(x) (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKYES_LINKCH_SHIFT)) & DMA_CITER_ELINKYES_LINKCH_MASK) 3314 #define DMA_CITER_ELINKYES_ELINK_MASK (0x8000U) 3315 #define DMA_CITER_ELINKYES_ELINK_SHIFT (15U) 3316 /*! ELINK - Enable channel-to-channel linking on minor-loop complete 3317 * 0b0..The channel-to-channel linking is disabled 3318 * 0b1..The channel-to-channel linking is enabled 3319 */ 3320 #define DMA_CITER_ELINKYES_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKYES_ELINK_SHIFT)) & DMA_CITER_ELINKYES_ELINK_MASK) 3321 /*! @} */ 3322 3323 /* The count of DMA_CITER_ELINKYES */ 3324 #define DMA_CITER_ELINKYES_COUNT (8U) 3325 3326 /*! @name DLAST_SGA - TCD Last Destination Address Adjustment/Scatter Gather Address */ 3327 /*! @{ */ 3328 #define DMA_DLAST_SGA_DLASTSGA_MASK (0xFFFFFFFFU) 3329 #define DMA_DLAST_SGA_DLASTSGA_SHIFT (0U) 3330 #define DMA_DLAST_SGA_DLASTSGA(x) (((uint32_t)(((uint32_t)(x)) << DMA_DLAST_SGA_DLASTSGA_SHIFT)) & DMA_DLAST_SGA_DLASTSGA_MASK) 3331 /*! @} */ 3332 3333 /* The count of DMA_DLAST_SGA */ 3334 #define DMA_DLAST_SGA_COUNT (8U) 3335 3336 /*! @name CSR - TCD Control and Status */ 3337 /*! @{ */ 3338 #define DMA_CSR_START_MASK (0x1U) 3339 #define DMA_CSR_START_SHIFT (0U) 3340 /*! START - Channel Start 3341 * 0b0..The channel is not explicitly started. 3342 * 0b1..The channel is explicitly started via a software initiated service request. 3343 */ 3344 #define DMA_CSR_START(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_START_SHIFT)) & DMA_CSR_START_MASK) 3345 #define DMA_CSR_INTMAJOR_MASK (0x2U) 3346 #define DMA_CSR_INTMAJOR_SHIFT (1U) 3347 /*! INTMAJOR - Enable an interrupt when major iteration count completes. 3348 * 0b0..The end-of-major loop interrupt is disabled. 3349 * 0b1..The end-of-major loop interrupt is enabled. 3350 */ 3351 #define DMA_CSR_INTMAJOR(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_INTMAJOR_SHIFT)) & DMA_CSR_INTMAJOR_MASK) 3352 #define DMA_CSR_INTHALF_MASK (0x4U) 3353 #define DMA_CSR_INTHALF_SHIFT (2U) 3354 /*! INTHALF - Enable an interrupt when major counter is half complete. 3355 * 0b0..The half-point interrupt is disabled. 3356 * 0b1..The half-point interrupt is enabled. 3357 */ 3358 #define DMA_CSR_INTHALF(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_INTHALF_SHIFT)) & DMA_CSR_INTHALF_MASK) 3359 #define DMA_CSR_DREQ_MASK (0x8U) 3360 #define DMA_CSR_DREQ_SHIFT (3U) 3361 /*! DREQ - Disable Request 3362 * 0b0..The channel's ERQ bit is not affected. 3363 * 0b1..The channel's ERQ bit is cleared when the major loop is complete. 3364 */ 3365 #define DMA_CSR_DREQ(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_DREQ_SHIFT)) & DMA_CSR_DREQ_MASK) 3366 #define DMA_CSR_ESG_MASK (0x10U) 3367 #define DMA_CSR_ESG_SHIFT (4U) 3368 /*! ESG - Enable Scatter/Gather Processing 3369 * 0b0..The current channel's TCD is normal format. 3370 * 0b1..The current channel's TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer to the next TCD to be loaded into this channel after the major loop completes its execution. 3371 */ 3372 #define DMA_CSR_ESG(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_ESG_SHIFT)) & DMA_CSR_ESG_MASK) 3373 #define DMA_CSR_MAJORELINK_MASK (0x20U) 3374 #define DMA_CSR_MAJORELINK_SHIFT (5U) 3375 /*! MAJORELINK - Enable channel-to-channel linking on major loop complete 3376 * 0b0..The channel-to-channel linking is disabled. 3377 * 0b1..The channel-to-channel linking is enabled. 3378 */ 3379 #define DMA_CSR_MAJORELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_MAJORELINK_SHIFT)) & DMA_CSR_MAJORELINK_MASK) 3380 #define DMA_CSR_ACTIVE_MASK (0x40U) 3381 #define DMA_CSR_ACTIVE_SHIFT (6U) 3382 #define DMA_CSR_ACTIVE(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_ACTIVE_SHIFT)) & DMA_CSR_ACTIVE_MASK) 3383 #define DMA_CSR_DONE_MASK (0x80U) 3384 #define DMA_CSR_DONE_SHIFT (7U) 3385 #define DMA_CSR_DONE(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_DONE_SHIFT)) & DMA_CSR_DONE_MASK) 3386 #define DMA_CSR_MAJORLINKCH_MASK (0x700U) 3387 #define DMA_CSR_MAJORLINKCH_SHIFT (8U) 3388 #define DMA_CSR_MAJORLINKCH(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_MAJORLINKCH_SHIFT)) & DMA_CSR_MAJORLINKCH_MASK) 3389 #define DMA_CSR_BWC_MASK (0xC000U) 3390 #define DMA_CSR_BWC_SHIFT (14U) 3391 /*! BWC - Bandwidth Control 3392 * 0b00..No eDMA engine stalls. 3393 * 0b01..Reserved 3394 * 0b10..eDMA engine stalls for 4 cycles after each R/W. 3395 * 0b11..eDMA engine stalls for 8 cycles after each R/W. 3396 */ 3397 #define DMA_CSR_BWC(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_BWC_SHIFT)) & DMA_CSR_BWC_MASK) 3398 /*! @} */ 3399 3400 /* The count of DMA_CSR */ 3401 #define DMA_CSR_COUNT (8U) 3402 3403 /*! @name BITER_ELINKNO - TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) */ 3404 /*! @{ */ 3405 #define DMA_BITER_ELINKNO_BITER_MASK (0x7FFFU) 3406 #define DMA_BITER_ELINKNO_BITER_SHIFT (0U) 3407 #define DMA_BITER_ELINKNO_BITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKNO_BITER_SHIFT)) & DMA_BITER_ELINKNO_BITER_MASK) 3408 #define DMA_BITER_ELINKNO_ELINK_MASK (0x8000U) 3409 #define DMA_BITER_ELINKNO_ELINK_SHIFT (15U) 3410 /*! ELINK - Enables channel-to-channel linking on minor loop complete 3411 * 0b0..The channel-to-channel linking is disabled 3412 * 0b1..The channel-to-channel linking is enabled 3413 */ 3414 #define DMA_BITER_ELINKNO_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKNO_ELINK_SHIFT)) & DMA_BITER_ELINKNO_ELINK_MASK) 3415 /*! @} */ 3416 3417 /* The count of DMA_BITER_ELINKNO */ 3418 #define DMA_BITER_ELINKNO_COUNT (8U) 3419 3420 /*! @name BITER_ELINKYES - TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) */ 3421 /*! @{ */ 3422 #define DMA_BITER_ELINKYES_BITER_MASK (0x1FFU) 3423 #define DMA_BITER_ELINKYES_BITER_SHIFT (0U) 3424 #define DMA_BITER_ELINKYES_BITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKYES_BITER_SHIFT)) & DMA_BITER_ELINKYES_BITER_MASK) 3425 #define DMA_BITER_ELINKYES_LINKCH_MASK (0xE00U) 3426 #define DMA_BITER_ELINKYES_LINKCH_SHIFT (9U) 3427 #define DMA_BITER_ELINKYES_LINKCH(x) (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKYES_LINKCH_SHIFT)) & DMA_BITER_ELINKYES_LINKCH_MASK) 3428 #define DMA_BITER_ELINKYES_ELINK_MASK (0x8000U) 3429 #define DMA_BITER_ELINKYES_ELINK_SHIFT (15U) 3430 /*! ELINK - Enables channel-to-channel linking on minor loop complete 3431 * 0b0..The channel-to-channel linking is disabled 3432 * 0b1..The channel-to-channel linking is enabled 3433 */ 3434 #define DMA_BITER_ELINKYES_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKYES_ELINK_SHIFT)) & DMA_BITER_ELINKYES_ELINK_MASK) 3435 /*! @} */ 3436 3437 /* The count of DMA_BITER_ELINKYES */ 3438 #define DMA_BITER_ELINKYES_COUNT (8U) 3439 3440 3441 /*! 3442 * @} 3443 */ /* end of group DMA_Register_Masks */ 3444 3445 3446 /* DMA - Peripheral instance base addresses */ 3447 /** Peripheral DMA base address */ 3448 #define DMA_BASE (0x40008000u) 3449 /** Peripheral DMA base pointer */ 3450 #define DMA0 ((DMA_Type *)DMA_BASE) 3451 /** Array initializer of DMA peripheral base addresses */ 3452 #define DMA_BASE_ADDRS { DMA_BASE } 3453 /** Array initializer of DMA peripheral base pointers */ 3454 #define DMA_BASE_PTRS { DMA0 } 3455 /** Interrupt vectors for the DMA peripheral type */ 3456 #define DMA_CHN_IRQS { { DMA0_DMA4_IRQn, DMA1_DMA5_IRQn, DMA2_DMA6_IRQn, DMA3_DMA7_IRQn, DMA0_DMA4_IRQn, DMA1_DMA5_IRQn, DMA2_DMA6_IRQn, DMA3_DMA7_IRQn } } 3457 #define DMA_ERROR_IRQS { DMA_Error_IRQn } 3458 3459 /*! 3460 * @} 3461 */ /* end of group DMA_Peripheral_Access_Layer */ 3462 3463 3464 /* ---------------------------------------------------------------------------- 3465 -- DMAMUX Peripheral Access Layer 3466 ---------------------------------------------------------------------------- */ 3467 3468 /*! 3469 * @addtogroup DMAMUX_Peripheral_Access_Layer DMAMUX Peripheral Access Layer 3470 * @{ 3471 */ 3472 3473 /** DMAMUX - Register Layout Typedef */ 3474 typedef struct { 3475 __IO uint8_t CHCFG[8]; /**< Channel Configuration register, array offset: 0x0, array step: 0x1 */ 3476 } DMAMUX_Type; 3477 3478 /* ---------------------------------------------------------------------------- 3479 -- DMAMUX Register Masks 3480 ---------------------------------------------------------------------------- */ 3481 3482 /*! 3483 * @addtogroup DMAMUX_Register_Masks DMAMUX Register Masks 3484 * @{ 3485 */ 3486 3487 /*! @name CHCFG - Channel Configuration register */ 3488 /*! @{ */ 3489 #define DMAMUX_CHCFG_SOURCE_MASK (0x3FU) 3490 #define DMAMUX_CHCFG_SOURCE_SHIFT (0U) 3491 /*! SOURCE - DMA Channel Source (Slot) 3492 * 0b000000..Disable 3493 * 0b000010..UART0_Receive_Complete 3494 * 0b000011..UART0_Transmit_Complete 3495 * 0b000100..UART1_Receive_Complete 3496 * 0b000101..UART1_Transmit_Complete 3497 * 0b001110..CAN0Rx 3498 * 0b010000..SPI0_Receive_Complete 3499 * 0b010001..SPI0_Transmit_Complete 3500 * 0b010110..I2C0_Transmission_Complete 3501 * 0b011000..FTM0_CH0_Event 3502 * 0b011001..FTM0_CH1_Event 3503 * 0b011010..FTM0_CH2_Event 3504 * 0b011011..FTM0_CH3_Event 3505 * 0b011100..FTM0_CH4_Event 3506 * 0b011101..FTM0_CH5_Event 3507 * 0b011110..FTM4_CH0_Event 3508 * 0b011111..FTM4_CH1_Event 3509 * 0b100000..FTM1_CH0_Event 3510 * 0b100001..FTM1_CH1_Event 3511 * 0b100010..FTM2_CH0_Event 3512 * 0b100011..FTM2_CH1_Event 3513 * 0b100100..FTM3_CH0_Event 3514 * 0b100101..FTM3_CH1_Event 3515 * 0b100110..FTM3_CH2_Event 3516 * 0b100111..FTM3_CH3_Event 3517 * 0b101000..ADC0_COCO 3518 * 0b101001..ADC1_COCO 3519 * 0b101010..CMP0_Output 3520 * 0b101011..CMP1_Output 3521 * 0b101101..DAC0_Buffer_Limit 3522 * 0b101111..PDB1_Programmable_Interrupt 3523 * 0b110000..PDB0_Programmable_Interrupt 3524 * 0b110001..PORTA_Rising_Falling_Edge 3525 * 0b110010..PORTB_Rising_Falling_Edge 3526 * 0b110011..PORTC_Rising_Falling_Edge 3527 * 0b110100..PORTD_Rising_Falling_Edge 3528 * 0b110101..PORTE_Rising_Falling_Edge 3529 * 0b110110..FTM3_CH4_Event 3530 * 0b110111..FTM3_CH5_Event 3531 * 0b111000..FTM5_CH0_Event 3532 * 0b111001..FTM5_CH1_Event 3533 * 0b111010..DMAMUX_Always_Enabled58 3534 * 0b111011..DMAMUX_Always_Enabled59 3535 * 0b111100..DMAMUX_Always_Enabled60 3536 * 0b111101..DMAMUX_Always_Enabled61 3537 * 0b111110..DMAMUX_Always_Enabled62 3538 * 0b111111..DMAMUX_Always_Enabled63 3539 */ 3540 #define DMAMUX_CHCFG_SOURCE(x) (((uint8_t)(((uint8_t)(x)) << DMAMUX_CHCFG_SOURCE_SHIFT)) & DMAMUX_CHCFG_SOURCE_MASK) 3541 #define DMAMUX_CHCFG_ENBL_MASK (0x80U) 3542 #define DMAMUX_CHCFG_ENBL_SHIFT (7U) 3543 /*! ENBL - DMA Channel Enable 3544 * 0b0..DMA channel is disabled. This mode is primarily used during configuration of the DMAMux. The DMA has separate channel enables/disables, which should be used to disable or reconfigure a DMA channel. 3545 * 0b1..DMA channel is enabled 3546 */ 3547 #define DMAMUX_CHCFG_ENBL(x) (((uint8_t)(((uint8_t)(x)) << DMAMUX_CHCFG_ENBL_SHIFT)) & DMAMUX_CHCFG_ENBL_MASK) 3548 /*! @} */ 3549 3550 /* The count of DMAMUX_CHCFG */ 3551 #define DMAMUX_CHCFG_COUNT (8U) 3552 3553 3554 /*! 3555 * @} 3556 */ /* end of group DMAMUX_Register_Masks */ 3557 3558 3559 /* DMAMUX - Peripheral instance base addresses */ 3560 /** Peripheral DMAMUX base address */ 3561 #define DMAMUX_BASE (0x40021000u) 3562 /** Peripheral DMAMUX base pointer */ 3563 #define DMAMUX ((DMAMUX_Type *)DMAMUX_BASE) 3564 /** Array initializer of DMAMUX peripheral base addresses */ 3565 #define DMAMUX_BASE_ADDRS { DMAMUX_BASE } 3566 /** Array initializer of DMAMUX peripheral base pointers */ 3567 #define DMAMUX_BASE_PTRS { DMAMUX } 3568 3569 /*! 3570 * @} 3571 */ /* end of group DMAMUX_Peripheral_Access_Layer */ 3572 3573 3574 /* ---------------------------------------------------------------------------- 3575 -- EWM Peripheral Access Layer 3576 ---------------------------------------------------------------------------- */ 3577 3578 /*! 3579 * @addtogroup EWM_Peripheral_Access_Layer EWM Peripheral Access Layer 3580 * @{ 3581 */ 3582 3583 /** EWM - Register Layout Typedef */ 3584 typedef struct { 3585 __IO uint8_t CTRL; /**< Control Register, offset: 0x0 */ 3586 __O uint8_t SERV; /**< Service Register, offset: 0x1 */ 3587 __IO uint8_t CMPL; /**< Compare Low Register, offset: 0x2 */ 3588 __IO uint8_t CMPH; /**< Compare High Register, offset: 0x3 */ 3589 __IO uint8_t CLKCTRL; /**< Clock Control Register, offset: 0x4 */ 3590 __IO uint8_t CLKPRESCALER; /**< Clock Prescaler Register, offset: 0x5 */ 3591 } EWM_Type; 3592 3593 /* ---------------------------------------------------------------------------- 3594 -- EWM Register Masks 3595 ---------------------------------------------------------------------------- */ 3596 3597 /*! 3598 * @addtogroup EWM_Register_Masks EWM Register Masks 3599 * @{ 3600 */ 3601 3602 /*! @name CTRL - Control Register */ 3603 /*! @{ */ 3604 #define EWM_CTRL_EWMEN_MASK (0x1U) 3605 #define EWM_CTRL_EWMEN_SHIFT (0U) 3606 #define EWM_CTRL_EWMEN(x) (((uint8_t)(((uint8_t)(x)) << EWM_CTRL_EWMEN_SHIFT)) & EWM_CTRL_EWMEN_MASK) 3607 #define EWM_CTRL_ASSIN_MASK (0x2U) 3608 #define EWM_CTRL_ASSIN_SHIFT (1U) 3609 #define EWM_CTRL_ASSIN(x) (((uint8_t)(((uint8_t)(x)) << EWM_CTRL_ASSIN_SHIFT)) & EWM_CTRL_ASSIN_MASK) 3610 #define EWM_CTRL_INEN_MASK (0x4U) 3611 #define EWM_CTRL_INEN_SHIFT (2U) 3612 #define EWM_CTRL_INEN(x) (((uint8_t)(((uint8_t)(x)) << EWM_CTRL_INEN_SHIFT)) & EWM_CTRL_INEN_MASK) 3613 #define EWM_CTRL_INTEN_MASK (0x8U) 3614 #define EWM_CTRL_INTEN_SHIFT (3U) 3615 #define EWM_CTRL_INTEN(x) (((uint8_t)(((uint8_t)(x)) << EWM_CTRL_INTEN_SHIFT)) & EWM_CTRL_INTEN_MASK) 3616 /*! @} */ 3617 3618 /*! @name SERV - Service Register */ 3619 /*! @{ */ 3620 #define EWM_SERV_SERVICE_MASK (0xFFU) 3621 #define EWM_SERV_SERVICE_SHIFT (0U) 3622 #define EWM_SERV_SERVICE(x) (((uint8_t)(((uint8_t)(x)) << EWM_SERV_SERVICE_SHIFT)) & EWM_SERV_SERVICE_MASK) 3623 /*! @} */ 3624 3625 /*! @name CMPL - Compare Low Register */ 3626 /*! @{ */ 3627 #define EWM_CMPL_COMPAREL_MASK (0xFFU) 3628 #define EWM_CMPL_COMPAREL_SHIFT (0U) 3629 #define EWM_CMPL_COMPAREL(x) (((uint8_t)(((uint8_t)(x)) << EWM_CMPL_COMPAREL_SHIFT)) & EWM_CMPL_COMPAREL_MASK) 3630 /*! @} */ 3631 3632 /*! @name CMPH - Compare High Register */ 3633 /*! @{ */ 3634 #define EWM_CMPH_COMPAREH_MASK (0xFFU) 3635 #define EWM_CMPH_COMPAREH_SHIFT (0U) 3636 #define EWM_CMPH_COMPAREH(x) (((uint8_t)(((uint8_t)(x)) << EWM_CMPH_COMPAREH_SHIFT)) & EWM_CMPH_COMPAREH_MASK) 3637 /*! @} */ 3638 3639 /*! @name CLKCTRL - Clock Control Register */ 3640 /*! @{ */ 3641 #define EWM_CLKCTRL_CLKSEL_MASK (0x3U) 3642 #define EWM_CLKCTRL_CLKSEL_SHIFT (0U) 3643 #define EWM_CLKCTRL_CLKSEL(x) (((uint8_t)(((uint8_t)(x)) << EWM_CLKCTRL_CLKSEL_SHIFT)) & EWM_CLKCTRL_CLKSEL_MASK) 3644 /*! @} */ 3645 3646 /*! @name CLKPRESCALER - Clock Prescaler Register */ 3647 /*! @{ */ 3648 #define EWM_CLKPRESCALER_CLK_DIV_MASK (0xFFU) 3649 #define EWM_CLKPRESCALER_CLK_DIV_SHIFT (0U) 3650 #define EWM_CLKPRESCALER_CLK_DIV(x) (((uint8_t)(((uint8_t)(x)) << EWM_CLKPRESCALER_CLK_DIV_SHIFT)) & EWM_CLKPRESCALER_CLK_DIV_MASK) 3651 /*! @} */ 3652 3653 3654 /*! 3655 * @} 3656 */ /* end of group EWM_Register_Masks */ 3657 3658 3659 /* EWM - Peripheral instance base addresses */ 3660 /** Peripheral EWM base address */ 3661 #define EWM_BASE (0x40061000u) 3662 /** Peripheral EWM base pointer */ 3663 #define EWM ((EWM_Type *)EWM_BASE) 3664 /** Array initializer of EWM peripheral base addresses */ 3665 #define EWM_BASE_ADDRS { EWM_BASE } 3666 /** Array initializer of EWM peripheral base pointers */ 3667 #define EWM_BASE_PTRS { EWM } 3668 /** Interrupt vectors for the EWM peripheral type */ 3669 #define EWM_IRQS { WDOG_EWM_IRQn } 3670 3671 /*! 3672 * @} 3673 */ /* end of group EWM_Peripheral_Access_Layer */ 3674 3675 3676 /* ---------------------------------------------------------------------------- 3677 -- FGPIO Peripheral Access Layer 3678 ---------------------------------------------------------------------------- */ 3679 3680 /*! 3681 * @addtogroup FGPIO_Peripheral_Access_Layer FGPIO Peripheral Access Layer 3682 * @{ 3683 */ 3684 3685 /** FGPIO - Register Layout Typedef */ 3686 typedef struct { 3687 __IO uint32_t PDOR; /**< Port Data Output Register, offset: 0x0 */ 3688 __O uint32_t PSOR; /**< Port Set Output Register, offset: 0x4 */ 3689 __O uint32_t PCOR; /**< Port Clear Output Register, offset: 0x8 */ 3690 __O uint32_t PTOR; /**< Port Toggle Output Register, offset: 0xC */ 3691 __I uint32_t PDIR; /**< Port Data Input Register, offset: 0x10 */ 3692 __IO uint32_t PDDR; /**< Port Data Direction Register, offset: 0x14 */ 3693 } FGPIO_Type; 3694 3695 /* ---------------------------------------------------------------------------- 3696 -- FGPIO Register Masks 3697 ---------------------------------------------------------------------------- */ 3698 3699 /*! 3700 * @addtogroup FGPIO_Register_Masks FGPIO Register Masks 3701 * @{ 3702 */ 3703 3704 /*! @name PDOR - Port Data Output Register */ 3705 /*! @{ */ 3706 #define FGPIO_PDOR_PDO_MASK (0xFFFFFFFFU) 3707 #define FGPIO_PDOR_PDO_SHIFT (0U) 3708 /*! PDO - Port Data Output 3709 * 0b00000000000000000000000000000000..Logic level 0 is driven on pin, provided pin is configured for general-purpose output. 3710 * 0b00000000000000000000000000000001..Logic level 1 is driven on pin, provided pin is configured for general-purpose output. 3711 */ 3712 #define FGPIO_PDOR_PDO(x) (((uint32_t)(((uint32_t)(x)) << FGPIO_PDOR_PDO_SHIFT)) & FGPIO_PDOR_PDO_MASK) 3713 /*! @} */ 3714 3715 /*! @name PSOR - Port Set Output Register */ 3716 /*! @{ */ 3717 #define FGPIO_PSOR_PTSO_MASK (0xFFFFFFFFU) 3718 #define FGPIO_PSOR_PTSO_SHIFT (0U) 3719 /*! PTSO - Port Set Output 3720 * 0b00000000000000000000000000000000..Corresponding bit in PDORn does not change. 3721 * 0b00000000000000000000000000000001..Corresponding bit in PDORn is set to logic 1. 3722 */ 3723 #define FGPIO_PSOR_PTSO(x) (((uint32_t)(((uint32_t)(x)) << FGPIO_PSOR_PTSO_SHIFT)) & FGPIO_PSOR_PTSO_MASK) 3724 /*! @} */ 3725 3726 /*! @name PCOR - Port Clear Output Register */ 3727 /*! @{ */ 3728 #define FGPIO_PCOR_PTCO_MASK (0xFFFFFFFFU) 3729 #define FGPIO_PCOR_PTCO_SHIFT (0U) 3730 /*! PTCO - Port Clear Output 3731 * 0b00000000000000000000000000000000..Corresponding bit in PDORn does not change. 3732 * 0b00000000000000000000000000000001..Corresponding bit in PDORn is cleared to logic 0. 3733 */ 3734 #define FGPIO_PCOR_PTCO(x) (((uint32_t)(((uint32_t)(x)) << FGPIO_PCOR_PTCO_SHIFT)) & FGPIO_PCOR_PTCO_MASK) 3735 /*! @} */ 3736 3737 /*! @name PTOR - Port Toggle Output Register */ 3738 /*! @{ */ 3739 #define FGPIO_PTOR_PTTO_MASK (0xFFFFFFFFU) 3740 #define FGPIO_PTOR_PTTO_SHIFT (0U) 3741 /*! PTTO - Port Toggle Output 3742 * 0b00000000000000000000000000000000..Corresponding bit in PDORn does not change. 3743 * 0b00000000000000000000000000000001..Corresponding bit in PDORn is set to the inverse of its existing logic state. 3744 */ 3745 #define FGPIO_PTOR_PTTO(x) (((uint32_t)(((uint32_t)(x)) << FGPIO_PTOR_PTTO_SHIFT)) & FGPIO_PTOR_PTTO_MASK) 3746 /*! @} */ 3747 3748 /*! @name PDIR - Port Data Input Register */ 3749 /*! @{ */ 3750 #define FGPIO_PDIR_PDI_MASK (0xFFFFFFFFU) 3751 #define FGPIO_PDIR_PDI_SHIFT (0U) 3752 /*! PDI - Port Data Input 3753 * 0b00000000000000000000000000000000..Pin logic level is logic 0, or is not configured for use by digital function. 3754 * 0b00000000000000000000000000000001..Pin logic level is logic 1. 3755 */ 3756 #define FGPIO_PDIR_PDI(x) (((uint32_t)(((uint32_t)(x)) << FGPIO_PDIR_PDI_SHIFT)) & FGPIO_PDIR_PDI_MASK) 3757 /*! @} */ 3758 3759 /*! @name PDDR - Port Data Direction Register */ 3760 /*! @{ */ 3761 #define FGPIO_PDDR_PDD_MASK (0xFFFFFFFFU) 3762 #define FGPIO_PDDR_PDD_SHIFT (0U) 3763 /*! PDD - Port Data Direction 3764 * 0b00000000000000000000000000000000..Pin is configured as general-purpose input, for the GPIO function. 3765 * 0b00000000000000000000000000000001..Pin is configured as general-purpose output, for the GPIO function. 3766 */ 3767 #define FGPIO_PDDR_PDD(x) (((uint32_t)(((uint32_t)(x)) << FGPIO_PDDR_PDD_SHIFT)) & FGPIO_PDDR_PDD_MASK) 3768 /*! @} */ 3769 3770 3771 /*! 3772 * @} 3773 */ /* end of group FGPIO_Register_Masks */ 3774 3775 3776 /* FGPIO - Peripheral instance base addresses */ 3777 /** Peripheral FGPIOA base address */ 3778 #define FGPIOA_BASE (0xF8000000u) 3779 /** Peripheral FGPIOA base pointer */ 3780 #define FGPIOA ((FGPIO_Type *)FGPIOA_BASE) 3781 /** Peripheral FGPIOB base address */ 3782 #define FGPIOB_BASE (0xF8000040u) 3783 /** Peripheral FGPIOB base pointer */ 3784 #define FGPIOB ((FGPIO_Type *)FGPIOB_BASE) 3785 /** Peripheral FGPIOC base address */ 3786 #define FGPIOC_BASE (0xF8000080u) 3787 /** Peripheral FGPIOC base pointer */ 3788 #define FGPIOC ((FGPIO_Type *)FGPIOC_BASE) 3789 /** Peripheral FGPIOD base address */ 3790 #define FGPIOD_BASE (0xF80000C0u) 3791 /** Peripheral FGPIOD base pointer */ 3792 #define FGPIOD ((FGPIO_Type *)FGPIOD_BASE) 3793 /** Peripheral FGPIOE base address */ 3794 #define FGPIOE_BASE (0xF8000100u) 3795 /** Peripheral FGPIOE base pointer */ 3796 #define FGPIOE ((FGPIO_Type *)FGPIOE_BASE) 3797 /** Array initializer of FGPIO peripheral base addresses */ 3798 #define FGPIO_BASE_ADDRS { FGPIOA_BASE, FGPIOB_BASE, FGPIOC_BASE, FGPIOD_BASE, FGPIOE_BASE } 3799 /** Array initializer of FGPIO peripheral base pointers */ 3800 #define FGPIO_BASE_PTRS { FGPIOA, FGPIOB, FGPIOC, FGPIOD, FGPIOE } 3801 3802 /*! 3803 * @} 3804 */ /* end of group FGPIO_Peripheral_Access_Layer */ 3805 3806 3807 /* ---------------------------------------------------------------------------- 3808 -- FTFA Peripheral Access Layer 3809 ---------------------------------------------------------------------------- */ 3810 3811 /*! 3812 * @addtogroup FTFA_Peripheral_Access_Layer FTFA Peripheral Access Layer 3813 * @{ 3814 */ 3815 3816 /** FTFA - Register Layout Typedef */ 3817 typedef struct { 3818 __IO uint8_t FSTAT; /**< Flash Status Register, offset: 0x0 */ 3819 __IO uint8_t FCNFG; /**< Flash Configuration Register, offset: 0x1 */ 3820 __I uint8_t FSEC; /**< Flash Security Register, offset: 0x2 */ 3821 __I uint8_t FOPT; /**< Flash Option Register, offset: 0x3 */ 3822 __IO uint8_t FCCOB3; /**< Flash Common Command Object Registers, offset: 0x4 */ 3823 __IO uint8_t FCCOB2; /**< Flash Common Command Object Registers, offset: 0x5 */ 3824 __IO uint8_t FCCOB1; /**< Flash Common Command Object Registers, offset: 0x6 */ 3825 __IO uint8_t FCCOB0; /**< Flash Common Command Object Registers, offset: 0x7 */ 3826 __IO uint8_t FCCOB7; /**< Flash Common Command Object Registers, offset: 0x8 */ 3827 __IO uint8_t FCCOB6; /**< Flash Common Command Object Registers, offset: 0x9 */ 3828 __IO uint8_t FCCOB5; /**< Flash Common Command Object Registers, offset: 0xA */ 3829 __IO uint8_t FCCOB4; /**< Flash Common Command Object Registers, offset: 0xB */ 3830 __IO uint8_t FCCOBB; /**< Flash Common Command Object Registers, offset: 0xC */ 3831 __IO uint8_t FCCOBA; /**< Flash Common Command Object Registers, offset: 0xD */ 3832 __IO uint8_t FCCOB9; /**< Flash Common Command Object Registers, offset: 0xE */ 3833 __IO uint8_t FCCOB8; /**< Flash Common Command Object Registers, offset: 0xF */ 3834 __IO uint8_t FPROT3; /**< Program Flash Protection Registers, offset: 0x10 */ 3835 __IO uint8_t FPROT2; /**< Program Flash Protection Registers, offset: 0x11 */ 3836 __IO uint8_t FPROT1; /**< Program Flash Protection Registers, offset: 0x12 */ 3837 __IO uint8_t FPROT0; /**< Program Flash Protection Registers, offset: 0x13 */ 3838 uint8_t RESERVED_0[4]; 3839 __I uint8_t XACCH3; /**< Execute-only Access Registers, offset: 0x18 */ 3840 __I uint8_t XACCH2; /**< Execute-only Access Registers, offset: 0x19 */ 3841 __I uint8_t XACCH1; /**< Execute-only Access Registers, offset: 0x1A */ 3842 __I uint8_t XACCH0; /**< Execute-only Access Registers, offset: 0x1B */ 3843 __I uint8_t XACCL3; /**< Execute-only Access Registers, offset: 0x1C */ 3844 __I uint8_t XACCL2; /**< Execute-only Access Registers, offset: 0x1D */ 3845 __I uint8_t XACCL1; /**< Execute-only Access Registers, offset: 0x1E */ 3846 __I uint8_t XACCL0; /**< Execute-only Access Registers, offset: 0x1F */ 3847 __I uint8_t SACCH3; /**< Supervisor-only Access Registers, offset: 0x20 */ 3848 __I uint8_t SACCH2; /**< Supervisor-only Access Registers, offset: 0x21 */ 3849 __I uint8_t SACCH1; /**< Supervisor-only Access Registers, offset: 0x22 */ 3850 __I uint8_t SACCH0; /**< Supervisor-only Access Registers, offset: 0x23 */ 3851 __I uint8_t SACCL3; /**< Supervisor-only Access Registers, offset: 0x24 */ 3852 __I uint8_t SACCL2; /**< Supervisor-only Access Registers, offset: 0x25 */ 3853 __I uint8_t SACCL1; /**< Supervisor-only Access Registers, offset: 0x26 */ 3854 __I uint8_t SACCL0; /**< Supervisor-only Access Registers, offset: 0x27 */ 3855 __I uint8_t FACSS; /**< Flash Access Segment Size Register, offset: 0x28 */ 3856 uint8_t RESERVED_1[2]; 3857 __I uint8_t FACSN; /**< Flash Access Segment Number Register, offset: 0x2B */ 3858 } FTFA_Type; 3859 3860 /* ---------------------------------------------------------------------------- 3861 -- FTFA Register Masks 3862 ---------------------------------------------------------------------------- */ 3863 3864 /*! 3865 * @addtogroup FTFA_Register_Masks FTFA Register Masks 3866 * @{ 3867 */ 3868 3869 /*! @name FSTAT - Flash Status Register */ 3870 /*! @{ */ 3871 #define FTFA_FSTAT_MGSTAT0_MASK (0x1U) 3872 #define FTFA_FSTAT_MGSTAT0_SHIFT (0U) 3873 #define FTFA_FSTAT_MGSTAT0(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FSTAT_MGSTAT0_SHIFT)) & FTFA_FSTAT_MGSTAT0_MASK) 3874 #define FTFA_FSTAT_FPVIOL_MASK (0x10U) 3875 #define FTFA_FSTAT_FPVIOL_SHIFT (4U) 3876 /*! FPVIOL - Flash Protection Violation Flag 3877 * 0b0..No protection violation detected 3878 * 0b1..Protection violation detected 3879 */ 3880 #define FTFA_FSTAT_FPVIOL(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FSTAT_FPVIOL_SHIFT)) & FTFA_FSTAT_FPVIOL_MASK) 3881 #define FTFA_FSTAT_ACCERR_MASK (0x20U) 3882 #define FTFA_FSTAT_ACCERR_SHIFT (5U) 3883 /*! ACCERR - Flash Access Error Flag 3884 * 0b0..No access error detected 3885 * 0b1..Access error detected 3886 */ 3887 #define FTFA_FSTAT_ACCERR(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FSTAT_ACCERR_SHIFT)) & FTFA_FSTAT_ACCERR_MASK) 3888 #define FTFA_FSTAT_RDCOLERR_MASK (0x40U) 3889 #define FTFA_FSTAT_RDCOLERR_SHIFT (6U) 3890 /*! RDCOLERR - Flash Read Collision Error Flag 3891 * 0b0..No collision error detected 3892 * 0b1..Collision error detected 3893 */ 3894 #define FTFA_FSTAT_RDCOLERR(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FSTAT_RDCOLERR_SHIFT)) & FTFA_FSTAT_RDCOLERR_MASK) 3895 #define FTFA_FSTAT_CCIF_MASK (0x80U) 3896 #define FTFA_FSTAT_CCIF_SHIFT (7U) 3897 /*! CCIF - Command Complete Interrupt Flag 3898 * 0b0..Flash command in progress 3899 * 0b1..Flash command has completed 3900 */ 3901 #define FTFA_FSTAT_CCIF(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FSTAT_CCIF_SHIFT)) & FTFA_FSTAT_CCIF_MASK) 3902 /*! @} */ 3903 3904 /*! @name FCNFG - Flash Configuration Register */ 3905 /*! @{ */ 3906 #define FTFA_FCNFG_ERSSUSP_MASK (0x10U) 3907 #define FTFA_FCNFG_ERSSUSP_SHIFT (4U) 3908 /*! ERSSUSP - Erase Suspend 3909 * 0b0..No suspend requested 3910 * 0b1..Suspend the current Erase Flash Sector command execution. 3911 */ 3912 #define FTFA_FCNFG_ERSSUSP(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCNFG_ERSSUSP_SHIFT)) & FTFA_FCNFG_ERSSUSP_MASK) 3913 #define FTFA_FCNFG_ERSAREQ_MASK (0x20U) 3914 #define FTFA_FCNFG_ERSAREQ_SHIFT (5U) 3915 /*! ERSAREQ - Erase All Request 3916 * 0b0..No request or request complete 3917 * 0b1..Request to: run the Erase All Blocks command, verify the erased state, program the security byte in the Flash Configuration Field to the unsecure state, and release MCU security by setting the FSEC[SEC] field to the unsecure state. 3918 */ 3919 #define FTFA_FCNFG_ERSAREQ(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCNFG_ERSAREQ_SHIFT)) & FTFA_FCNFG_ERSAREQ_MASK) 3920 #define FTFA_FCNFG_RDCOLLIE_MASK (0x40U) 3921 #define FTFA_FCNFG_RDCOLLIE_SHIFT (6U) 3922 /*! RDCOLLIE - Read Collision Error Interrupt Enable 3923 * 0b0..Read collision error interrupt disabled 3924 * 0b1..Read collision error interrupt enabled. An interrupt request is generated whenever a flash memory read collision error is detected (see the description of FSTAT[RDCOLERR]). 3925 */ 3926 #define FTFA_FCNFG_RDCOLLIE(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCNFG_RDCOLLIE_SHIFT)) & FTFA_FCNFG_RDCOLLIE_MASK) 3927 #define FTFA_FCNFG_CCIE_MASK (0x80U) 3928 #define FTFA_FCNFG_CCIE_SHIFT (7U) 3929 /*! CCIE - Command Complete Interrupt Enable 3930 * 0b0..Command complete interrupt disabled 3931 * 0b1..Command complete interrupt enabled. An interrupt request is generated whenever the FSTAT[CCIF] flag is set. 3932 */ 3933 #define FTFA_FCNFG_CCIE(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCNFG_CCIE_SHIFT)) & FTFA_FCNFG_CCIE_MASK) 3934 /*! @} */ 3935 3936 /*! @name FSEC - Flash Security Register */ 3937 /*! @{ */ 3938 #define FTFA_FSEC_SEC_MASK (0x3U) 3939 #define FTFA_FSEC_SEC_SHIFT (0U) 3940 /*! SEC - Flash Security 3941 * 0b00..MCU security status is secure. 3942 * 0b01..MCU security status is secure. 3943 * 0b10..MCU security status is unsecure. (The standard shipping condition of the flash memory module is unsecure.) 3944 * 0b11..MCU security status is secure. 3945 */ 3946 #define FTFA_FSEC_SEC(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FSEC_SEC_SHIFT)) & FTFA_FSEC_SEC_MASK) 3947 #define FTFA_FSEC_FSLACC_MASK (0xCU) 3948 #define FTFA_FSEC_FSLACC_SHIFT (2U) 3949 /*! FSLACC - Freescale Failure Analysis Access Code 3950 * 0b00..Freescale factory access granted 3951 * 0b01..Freescale factory access denied 3952 * 0b10..Freescale factory access denied 3953 * 0b11..Freescale factory access granted 3954 */ 3955 #define FTFA_FSEC_FSLACC(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FSEC_FSLACC_SHIFT)) & FTFA_FSEC_FSLACC_MASK) 3956 #define FTFA_FSEC_MEEN_MASK (0x30U) 3957 #define FTFA_FSEC_MEEN_SHIFT (4U) 3958 /*! MEEN - Mass Erase Enable 3959 * 0b00..Mass erase is enabled 3960 * 0b01..Mass erase is enabled 3961 * 0b10..Mass erase is disabled 3962 * 0b11..Mass erase is enabled 3963 */ 3964 #define FTFA_FSEC_MEEN(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FSEC_MEEN_SHIFT)) & FTFA_FSEC_MEEN_MASK) 3965 #define FTFA_FSEC_KEYEN_MASK (0xC0U) 3966 #define FTFA_FSEC_KEYEN_SHIFT (6U) 3967 /*! KEYEN - Backdoor Key Security Enable 3968 * 0b00..Backdoor key access disabled 3969 * 0b01..Backdoor key access disabled (preferred KEYEN state to disable backdoor key access) 3970 * 0b10..Backdoor key access enabled 3971 * 0b11..Backdoor key access disabled 3972 */ 3973 #define FTFA_FSEC_KEYEN(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FSEC_KEYEN_SHIFT)) & FTFA_FSEC_KEYEN_MASK) 3974 /*! @} */ 3975 3976 /*! @name FOPT - Flash Option Register */ 3977 /*! @{ */ 3978 #define FTFA_FOPT_OPT_MASK (0xFFU) 3979 #define FTFA_FOPT_OPT_SHIFT (0U) 3980 #define FTFA_FOPT_OPT(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FOPT_OPT_SHIFT)) & FTFA_FOPT_OPT_MASK) 3981 /*! @} */ 3982 3983 /*! @name FCCOB3 - Flash Common Command Object Registers */ 3984 /*! @{ */ 3985 #define FTFA_FCCOB3_CCOBn_MASK (0xFFU) 3986 #define FTFA_FCCOB3_CCOBn_SHIFT (0U) 3987 #define FTFA_FCCOB3_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOB3_CCOBn_SHIFT)) & FTFA_FCCOB3_CCOBn_MASK) 3988 /*! @} */ 3989 3990 /*! @name FCCOB2 - Flash Common Command Object Registers */ 3991 /*! @{ */ 3992 #define FTFA_FCCOB2_CCOBn_MASK (0xFFU) 3993 #define FTFA_FCCOB2_CCOBn_SHIFT (0U) 3994 #define FTFA_FCCOB2_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOB2_CCOBn_SHIFT)) & FTFA_FCCOB2_CCOBn_MASK) 3995 /*! @} */ 3996 3997 /*! @name FCCOB1 - Flash Common Command Object Registers */ 3998 /*! @{ */ 3999 #define FTFA_FCCOB1_CCOBn_MASK (0xFFU) 4000 #define FTFA_FCCOB1_CCOBn_SHIFT (0U) 4001 #define FTFA_FCCOB1_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOB1_CCOBn_SHIFT)) & FTFA_FCCOB1_CCOBn_MASK) 4002 /*! @} */ 4003 4004 /*! @name FCCOB0 - Flash Common Command Object Registers */ 4005 /*! @{ */ 4006 #define FTFA_FCCOB0_CCOBn_MASK (0xFFU) 4007 #define FTFA_FCCOB0_CCOBn_SHIFT (0U) 4008 #define FTFA_FCCOB0_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOB0_CCOBn_SHIFT)) & FTFA_FCCOB0_CCOBn_MASK) 4009 /*! @} */ 4010 4011 /*! @name FCCOB7 - Flash Common Command Object Registers */ 4012 /*! @{ */ 4013 #define FTFA_FCCOB7_CCOBn_MASK (0xFFU) 4014 #define FTFA_FCCOB7_CCOBn_SHIFT (0U) 4015 #define FTFA_FCCOB7_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOB7_CCOBn_SHIFT)) & FTFA_FCCOB7_CCOBn_MASK) 4016 /*! @} */ 4017 4018 /*! @name FCCOB6 - Flash Common Command Object Registers */ 4019 /*! @{ */ 4020 #define FTFA_FCCOB6_CCOBn_MASK (0xFFU) 4021 #define FTFA_FCCOB6_CCOBn_SHIFT (0U) 4022 #define FTFA_FCCOB6_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOB6_CCOBn_SHIFT)) & FTFA_FCCOB6_CCOBn_MASK) 4023 /*! @} */ 4024 4025 /*! @name FCCOB5 - Flash Common Command Object Registers */ 4026 /*! @{ */ 4027 #define FTFA_FCCOB5_CCOBn_MASK (0xFFU) 4028 #define FTFA_FCCOB5_CCOBn_SHIFT (0U) 4029 #define FTFA_FCCOB5_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOB5_CCOBn_SHIFT)) & FTFA_FCCOB5_CCOBn_MASK) 4030 /*! @} */ 4031 4032 /*! @name FCCOB4 - Flash Common Command Object Registers */ 4033 /*! @{ */ 4034 #define FTFA_FCCOB4_CCOBn_MASK (0xFFU) 4035 #define FTFA_FCCOB4_CCOBn_SHIFT (0U) 4036 #define FTFA_FCCOB4_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOB4_CCOBn_SHIFT)) & FTFA_FCCOB4_CCOBn_MASK) 4037 /*! @} */ 4038 4039 /*! @name FCCOBB - Flash Common Command Object Registers */ 4040 /*! @{ */ 4041 #define FTFA_FCCOBB_CCOBn_MASK (0xFFU) 4042 #define FTFA_FCCOBB_CCOBn_SHIFT (0U) 4043 #define FTFA_FCCOBB_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOBB_CCOBn_SHIFT)) & FTFA_FCCOBB_CCOBn_MASK) 4044 /*! @} */ 4045 4046 /*! @name FCCOBA - Flash Common Command Object Registers */ 4047 /*! @{ */ 4048 #define FTFA_FCCOBA_CCOBn_MASK (0xFFU) 4049 #define FTFA_FCCOBA_CCOBn_SHIFT (0U) 4050 #define FTFA_FCCOBA_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOBA_CCOBn_SHIFT)) & FTFA_FCCOBA_CCOBn_MASK) 4051 /*! @} */ 4052 4053 /*! @name FCCOB9 - Flash Common Command Object Registers */ 4054 /*! @{ */ 4055 #define FTFA_FCCOB9_CCOBn_MASK (0xFFU) 4056 #define FTFA_FCCOB9_CCOBn_SHIFT (0U) 4057 #define FTFA_FCCOB9_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOB9_CCOBn_SHIFT)) & FTFA_FCCOB9_CCOBn_MASK) 4058 /*! @} */ 4059 4060 /*! @name FCCOB8 - Flash Common Command Object Registers */ 4061 /*! @{ */ 4062 #define FTFA_FCCOB8_CCOBn_MASK (0xFFU) 4063 #define FTFA_FCCOB8_CCOBn_SHIFT (0U) 4064 #define FTFA_FCCOB8_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOB8_CCOBn_SHIFT)) & FTFA_FCCOB8_CCOBn_MASK) 4065 /*! @} */ 4066 4067 /*! @name FPROT3 - Program Flash Protection Registers */ 4068 /*! @{ */ 4069 #define FTFA_FPROT3_PROT_MASK (0xFFU) 4070 #define FTFA_FPROT3_PROT_SHIFT (0U) 4071 /*! PROT - Program Flash Region Protect 4072 * 0b00000000..Program flash region is protected. 4073 * 0b00000001..Program flash region is not protected 4074 */ 4075 #define FTFA_FPROT3_PROT(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FPROT3_PROT_SHIFT)) & FTFA_FPROT3_PROT_MASK) 4076 /*! @} */ 4077 4078 /*! @name FPROT2 - Program Flash Protection Registers */ 4079 /*! @{ */ 4080 #define FTFA_FPROT2_PROT_MASK (0xFFU) 4081 #define FTFA_FPROT2_PROT_SHIFT (0U) 4082 /*! PROT - Program Flash Region Protect 4083 * 0b00000000..Program flash region is protected. 4084 * 0b00000001..Program flash region is not protected 4085 */ 4086 #define FTFA_FPROT2_PROT(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FPROT2_PROT_SHIFT)) & FTFA_FPROT2_PROT_MASK) 4087 /*! @} */ 4088 4089 /*! @name FPROT1 - Program Flash Protection Registers */ 4090 /*! @{ */ 4091 #define FTFA_FPROT1_PROT_MASK (0xFFU) 4092 #define FTFA_FPROT1_PROT_SHIFT (0U) 4093 /*! PROT - Program Flash Region Protect 4094 * 0b00000000..Program flash region is protected. 4095 * 0b00000001..Program flash region is not protected 4096 */ 4097 #define FTFA_FPROT1_PROT(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FPROT1_PROT_SHIFT)) & FTFA_FPROT1_PROT_MASK) 4098 /*! @} */ 4099 4100 /*! @name FPROT0 - Program Flash Protection Registers */ 4101 /*! @{ */ 4102 #define FTFA_FPROT0_PROT_MASK (0xFFU) 4103 #define FTFA_FPROT0_PROT_SHIFT (0U) 4104 /*! PROT - Program Flash Region Protect 4105 * 0b00000000..Program flash region is protected. 4106 * 0b00000001..Program flash region is not protected 4107 */ 4108 #define FTFA_FPROT0_PROT(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FPROT0_PROT_SHIFT)) & FTFA_FPROT0_PROT_MASK) 4109 /*! @} */ 4110 4111 /*! @name XACCH3 - Execute-only Access Registers */ 4112 /*! @{ */ 4113 #define FTFA_XACCH3_XA_MASK (0xFFU) 4114 #define FTFA_XACCH3_XA_SHIFT (0U) 4115 /*! XA - Execute-only access control 4116 * 0b00000000..Associated segment is accessible in execute mode only (as an instruction fetch) 4117 * 0b00000001..Associated segment is accessible as data or in execute mode 4118 */ 4119 #define FTFA_XACCH3_XA(x) (((uint8_t)(((uint8_t)(x)) << FTFA_XACCH3_XA_SHIFT)) & FTFA_XACCH3_XA_MASK) 4120 /*! @} */ 4121 4122 /*! @name XACCH2 - Execute-only Access Registers */ 4123 /*! @{ */ 4124 #define FTFA_XACCH2_XA_MASK (0xFFU) 4125 #define FTFA_XACCH2_XA_SHIFT (0U) 4126 /*! XA - Execute-only access control 4127 * 0b00000000..Associated segment is accessible in execute mode only (as an instruction fetch) 4128 * 0b00000001..Associated segment is accessible as data or in execute mode 4129 */ 4130 #define FTFA_XACCH2_XA(x) (((uint8_t)(((uint8_t)(x)) << FTFA_XACCH2_XA_SHIFT)) & FTFA_XACCH2_XA_MASK) 4131 /*! @} */ 4132 4133 /*! @name XACCH1 - Execute-only Access Registers */ 4134 /*! @{ */ 4135 #define FTFA_XACCH1_XA_MASK (0xFFU) 4136 #define FTFA_XACCH1_XA_SHIFT (0U) 4137 /*! XA - Execute-only access control 4138 * 0b00000000..Associated segment is accessible in execute mode only (as an instruction fetch) 4139 * 0b00000001..Associated segment is accessible as data or in execute mode 4140 */ 4141 #define FTFA_XACCH1_XA(x) (((uint8_t)(((uint8_t)(x)) << FTFA_XACCH1_XA_SHIFT)) & FTFA_XACCH1_XA_MASK) 4142 /*! @} */ 4143 4144 /*! @name XACCH0 - Execute-only Access Registers */ 4145 /*! @{ */ 4146 #define FTFA_XACCH0_XA_MASK (0xFFU) 4147 #define FTFA_XACCH0_XA_SHIFT (0U) 4148 /*! XA - Execute-only access control 4149 * 0b00000000..Associated segment is accessible in execute mode only (as an instruction fetch) 4150 * 0b00000001..Associated segment is accessible as data or in execute mode 4151 */ 4152 #define FTFA_XACCH0_XA(x) (((uint8_t)(((uint8_t)(x)) << FTFA_XACCH0_XA_SHIFT)) & FTFA_XACCH0_XA_MASK) 4153 /*! @} */ 4154 4155 /*! @name XACCL3 - Execute-only Access Registers */ 4156 /*! @{ */ 4157 #define FTFA_XACCL3_XA_MASK (0xFFU) 4158 #define FTFA_XACCL3_XA_SHIFT (0U) 4159 /*! XA - Execute-only access control 4160 * 0b00000000..Associated segment is accessible in execute mode only (as an instruction fetch) 4161 * 0b00000001..Associated segment is accessible as data or in execute mode 4162 */ 4163 #define FTFA_XACCL3_XA(x) (((uint8_t)(((uint8_t)(x)) << FTFA_XACCL3_XA_SHIFT)) & FTFA_XACCL3_XA_MASK) 4164 /*! @} */ 4165 4166 /*! @name XACCL2 - Execute-only Access Registers */ 4167 /*! @{ */ 4168 #define FTFA_XACCL2_XA_MASK (0xFFU) 4169 #define FTFA_XACCL2_XA_SHIFT (0U) 4170 /*! XA - Execute-only access control 4171 * 0b00000000..Associated segment is accessible in execute mode only (as an instruction fetch) 4172 * 0b00000001..Associated segment is accessible as data or in execute mode 4173 */ 4174 #define FTFA_XACCL2_XA(x) (((uint8_t)(((uint8_t)(x)) << FTFA_XACCL2_XA_SHIFT)) & FTFA_XACCL2_XA_MASK) 4175 /*! @} */ 4176 4177 /*! @name XACCL1 - Execute-only Access Registers */ 4178 /*! @{ */ 4179 #define FTFA_XACCL1_XA_MASK (0xFFU) 4180 #define FTFA_XACCL1_XA_SHIFT (0U) 4181 /*! XA - Execute-only access control 4182 * 0b00000000..Associated segment is accessible in execute mode only (as an instruction fetch) 4183 * 0b00000001..Associated segment is accessible as data or in execute mode 4184 */ 4185 #define FTFA_XACCL1_XA(x) (((uint8_t)(((uint8_t)(x)) << FTFA_XACCL1_XA_SHIFT)) & FTFA_XACCL1_XA_MASK) 4186 /*! @} */ 4187 4188 /*! @name XACCL0 - Execute-only Access Registers */ 4189 /*! @{ */ 4190 #define FTFA_XACCL0_XA_MASK (0xFFU) 4191 #define FTFA_XACCL0_XA_SHIFT (0U) 4192 /*! XA - Execute-only access control 4193 * 0b00000000..Associated segment is accessible in execute mode only (as an instruction fetch) 4194 * 0b00000001..Associated segment is accessible as data or in execute mode 4195 */ 4196 #define FTFA_XACCL0_XA(x) (((uint8_t)(((uint8_t)(x)) << FTFA_XACCL0_XA_SHIFT)) & FTFA_XACCL0_XA_MASK) 4197 /*! @} */ 4198 4199 /*! @name SACCH3 - Supervisor-only Access Registers */ 4200 /*! @{ */ 4201 #define FTFA_SACCH3_SA_MASK (0xFFU) 4202 #define FTFA_SACCH3_SA_SHIFT (0U) 4203 /*! SA - Supervisor-only access control 4204 * 0b00000000..Associated segment is accessible in supervisor mode only 4205 * 0b00000001..Associated segment is accessible in user or supervisor mode 4206 */ 4207 #define FTFA_SACCH3_SA(x) (((uint8_t)(((uint8_t)(x)) << FTFA_SACCH3_SA_SHIFT)) & FTFA_SACCH3_SA_MASK) 4208 /*! @} */ 4209 4210 /*! @name SACCH2 - Supervisor-only Access Registers */ 4211 /*! @{ */ 4212 #define FTFA_SACCH2_SA_MASK (0xFFU) 4213 #define FTFA_SACCH2_SA_SHIFT (0U) 4214 /*! SA - Supervisor-only access control 4215 * 0b00000000..Associated segment is accessible in supervisor mode only 4216 * 0b00000001..Associated segment is accessible in user or supervisor mode 4217 */ 4218 #define FTFA_SACCH2_SA(x) (((uint8_t)(((uint8_t)(x)) << FTFA_SACCH2_SA_SHIFT)) & FTFA_SACCH2_SA_MASK) 4219 /*! @} */ 4220 4221 /*! @name SACCH1 - Supervisor-only Access Registers */ 4222 /*! @{ */ 4223 #define FTFA_SACCH1_SA_MASK (0xFFU) 4224 #define FTFA_SACCH1_SA_SHIFT (0U) 4225 /*! SA - Supervisor-only access control 4226 * 0b00000000..Associated segment is accessible in supervisor mode only 4227 * 0b00000001..Associated segment is accessible in user or supervisor mode 4228 */ 4229 #define FTFA_SACCH1_SA(x) (((uint8_t)(((uint8_t)(x)) << FTFA_SACCH1_SA_SHIFT)) & FTFA_SACCH1_SA_MASK) 4230 /*! @} */ 4231 4232 /*! @name SACCH0 - Supervisor-only Access Registers */ 4233 /*! @{ */ 4234 #define FTFA_SACCH0_SA_MASK (0xFFU) 4235 #define FTFA_SACCH0_SA_SHIFT (0U) 4236 /*! SA - Supervisor-only access control 4237 * 0b00000000..Associated segment is accessible in supervisor mode only 4238 * 0b00000001..Associated segment is accessible in user or supervisor mode 4239 */ 4240 #define FTFA_SACCH0_SA(x) (((uint8_t)(((uint8_t)(x)) << FTFA_SACCH0_SA_SHIFT)) & FTFA_SACCH0_SA_MASK) 4241 /*! @} */ 4242 4243 /*! @name SACCL3 - Supervisor-only Access Registers */ 4244 /*! @{ */ 4245 #define FTFA_SACCL3_SA_MASK (0xFFU) 4246 #define FTFA_SACCL3_SA_SHIFT (0U) 4247 /*! SA - Supervisor-only access control 4248 * 0b00000000..Associated segment is accessible in supervisor mode only 4249 * 0b00000001..Associated segment is accessible in user or supervisor mode 4250 */ 4251 #define FTFA_SACCL3_SA(x) (((uint8_t)(((uint8_t)(x)) << FTFA_SACCL3_SA_SHIFT)) & FTFA_SACCL3_SA_MASK) 4252 /*! @} */ 4253 4254 /*! @name SACCL2 - Supervisor-only Access Registers */ 4255 /*! @{ */ 4256 #define FTFA_SACCL2_SA_MASK (0xFFU) 4257 #define FTFA_SACCL2_SA_SHIFT (0U) 4258 /*! SA - Supervisor-only access control 4259 * 0b00000000..Associated segment is accessible in supervisor mode only 4260 * 0b00000001..Associated segment is accessible in user or supervisor mode 4261 */ 4262 #define FTFA_SACCL2_SA(x) (((uint8_t)(((uint8_t)(x)) << FTFA_SACCL2_SA_SHIFT)) & FTFA_SACCL2_SA_MASK) 4263 /*! @} */ 4264 4265 /*! @name SACCL1 - Supervisor-only Access Registers */ 4266 /*! @{ */ 4267 #define FTFA_SACCL1_SA_MASK (0xFFU) 4268 #define FTFA_SACCL1_SA_SHIFT (0U) 4269 /*! SA - Supervisor-only access control 4270 * 0b00000000..Associated segment is accessible in supervisor mode only 4271 * 0b00000001..Associated segment is accessible in user or supervisor mode 4272 */ 4273 #define FTFA_SACCL1_SA(x) (((uint8_t)(((uint8_t)(x)) << FTFA_SACCL1_SA_SHIFT)) & FTFA_SACCL1_SA_MASK) 4274 /*! @} */ 4275 4276 /*! @name SACCL0 - Supervisor-only Access Registers */ 4277 /*! @{ */ 4278 #define FTFA_SACCL0_SA_MASK (0xFFU) 4279 #define FTFA_SACCL0_SA_SHIFT (0U) 4280 /*! SA - Supervisor-only access control 4281 * 0b00000000..Associated segment is accessible in supervisor mode only 4282 * 0b00000001..Associated segment is accessible in user or supervisor mode 4283 */ 4284 #define FTFA_SACCL0_SA(x) (((uint8_t)(((uint8_t)(x)) << FTFA_SACCL0_SA_SHIFT)) & FTFA_SACCL0_SA_MASK) 4285 /*! @} */ 4286 4287 /*! @name FACSS - Flash Access Segment Size Register */ 4288 /*! @{ */ 4289 #define FTFA_FACSS_SGSIZE_MASK (0xFFU) 4290 #define FTFA_FACSS_SGSIZE_SHIFT (0U) 4291 #define FTFA_FACSS_SGSIZE(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FACSS_SGSIZE_SHIFT)) & FTFA_FACSS_SGSIZE_MASK) 4292 /*! @} */ 4293 4294 /*! @name FACSN - Flash Access Segment Number Register */ 4295 /*! @{ */ 4296 #define FTFA_FACSN_NUMSG_MASK (0xFFU) 4297 #define FTFA_FACSN_NUMSG_SHIFT (0U) 4298 /*! NUMSG - Number of Segments Indicator 4299 * 0b00100000..Program flash memory is divided into 32 segments (64 Kbytes, 128 Kbytes) 4300 * 0b00101000..Program flash memory is divided into 40 segments (160 Kbytes) 4301 * 0b01000000..Program flash memory is divided into 64 segments (256 Kbytes, 512 Kbytes) 4302 */ 4303 #define FTFA_FACSN_NUMSG(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FACSN_NUMSG_SHIFT)) & FTFA_FACSN_NUMSG_MASK) 4304 /*! @} */ 4305 4306 4307 /*! 4308 * @} 4309 */ /* end of group FTFA_Register_Masks */ 4310 4311 4312 /* FTFA - Peripheral instance base addresses */ 4313 /** Peripheral FTFA base address */ 4314 #define FTFA_BASE (0x40020000u) 4315 /** Peripheral FTFA base pointer */ 4316 #define FTFA ((FTFA_Type *)FTFA_BASE) 4317 /** Array initializer of FTFA peripheral base addresses */ 4318 #define FTFA_BASE_ADDRS { FTFA_BASE } 4319 /** Array initializer of FTFA peripheral base pointers */ 4320 #define FTFA_BASE_PTRS { FTFA } 4321 /** Interrupt vectors for the FTFA peripheral type */ 4322 #define FTFA_COMMAND_COMPLETE_IRQS { FTFA_IRQn } 4323 4324 /*! 4325 * @} 4326 */ /* end of group FTFA_Peripheral_Access_Layer */ 4327 4328 4329 /* ---------------------------------------------------------------------------- 4330 -- FTM Peripheral Access Layer 4331 ---------------------------------------------------------------------------- */ 4332 4333 /*! 4334 * @addtogroup FTM_Peripheral_Access_Layer FTM Peripheral Access Layer 4335 * @{ 4336 */ 4337 4338 /** FTM - Register Layout Typedef */ 4339 typedef struct { 4340 __IO uint32_t SC; /**< Status And Control, offset: 0x0 */ 4341 __IO uint32_t CNT; /**< Counter, offset: 0x4 */ 4342 __IO uint32_t MOD; /**< Modulo, offset: 0x8 */ 4343 struct { /* offset: 0xC, array step: 0x8 */ 4344 __IO uint32_t CnSC; /**< Channel (n) Status And Control, array offset: 0xC, array step: 0x8 */ 4345 __IO uint32_t CnV; /**< Channel (n) Value, array offset: 0x10, array step: 0x8 */ 4346 } CONTROLS[6]; 4347 uint8_t RESERVED_0[16]; 4348 __IO uint32_t CNTIN; /**< Counter Initial Value, offset: 0x4C */ 4349 __IO uint32_t STATUS; /**< Capture And Compare Status, offset: 0x50 */ 4350 __IO uint32_t MODE; /**< Features Mode Selection, offset: 0x54 */ 4351 __IO uint32_t SYNC; /**< Synchronization, offset: 0x58 */ 4352 __IO uint32_t OUTINIT; /**< Initial State For Channels Output, offset: 0x5C */ 4353 __IO uint32_t OUTMASK; /**< Output Mask, offset: 0x60 */ 4354 __IO uint32_t COMBINE; /**< Function For Linked Channels, offset: 0x64 */ 4355 __IO uint32_t DEADTIME; /**< Deadtime Insertion Control, offset: 0x68 */ 4356 __IO uint32_t EXTTRIG; /**< FTM External Trigger, offset: 0x6C */ 4357 __IO uint32_t POL; /**< Channels Polarity, offset: 0x70 */ 4358 __IO uint32_t FMS; /**< Fault Mode Status, offset: 0x74 */ 4359 __IO uint32_t FILTER; /**< Input Capture Filter Control, offset: 0x78 */ 4360 __IO uint32_t FLTCTRL; /**< Fault Control, offset: 0x7C */ 4361 __IO uint32_t QDCTRL; /**< Quadrature Decoder Control And Status, offset: 0x80 */ 4362 __IO uint32_t CONF; /**< Configuration, offset: 0x84 */ 4363 __IO uint32_t FLTPOL; /**< FTM Fault Input Polarity, offset: 0x88 */ 4364 __IO uint32_t SYNCONF; /**< Synchronization Configuration, offset: 0x8C */ 4365 __IO uint32_t INVCTRL; /**< FTM Inverting Control, offset: 0x90 */ 4366 __IO uint32_t SWOCTRL; /**< FTM Software Output Control, offset: 0x94 */ 4367 __IO uint32_t PWMLOAD; /**< FTM PWM Load, offset: 0x98 */ 4368 } FTM_Type; 4369 4370 /* ---------------------------------------------------------------------------- 4371 -- FTM Register Masks 4372 ---------------------------------------------------------------------------- */ 4373 4374 /*! 4375 * @addtogroup FTM_Register_Masks FTM Register Masks 4376 * @{ 4377 */ 4378 4379 /*! @name SC - Status And Control */ 4380 /*! @{ */ 4381 #define FTM_SC_PS_MASK (0x7U) 4382 #define FTM_SC_PS_SHIFT (0U) 4383 /*! PS - Prescale Factor Selection 4384 * 0b000..Divide by 1 4385 * 0b001..Divide by 2 4386 * 0b010..Divide by 4 4387 * 0b011..Divide by 8 4388 * 0b100..Divide by 16 4389 * 0b101..Divide by 32 4390 * 0b110..Divide by 64 4391 * 0b111..Divide by 128 4392 */ 4393 #define FTM_SC_PS(x) (((uint32_t)(((uint32_t)(x)) << FTM_SC_PS_SHIFT)) & FTM_SC_PS_MASK) 4394 #define FTM_SC_CLKS_MASK (0x18U) 4395 #define FTM_SC_CLKS_SHIFT (3U) 4396 /*! CLKS - Clock Source Selection 4397 * 0b00..No clock selected. This in effect disables the FTM counter. 4398 * 0b01..System clock 4399 * 0b10..Fixed frequency clock 4400 * 0b11..External clock 4401 */ 4402 #define FTM_SC_CLKS(x) (((uint32_t)(((uint32_t)(x)) << FTM_SC_CLKS_SHIFT)) & FTM_SC_CLKS_MASK) 4403 #define FTM_SC_CPWMS_MASK (0x20U) 4404 #define FTM_SC_CPWMS_SHIFT (5U) 4405 /*! CPWMS - Center-Aligned PWM Select 4406 * 0b0..FTM counter operates in Up Counting mode. 4407 * 0b1..FTM counter operates in Up-Down Counting mode. 4408 */ 4409 #define FTM_SC_CPWMS(x) (((uint32_t)(((uint32_t)(x)) << FTM_SC_CPWMS_SHIFT)) & FTM_SC_CPWMS_MASK) 4410 #define FTM_SC_TOIE_MASK (0x40U) 4411 #define FTM_SC_TOIE_SHIFT (6U) 4412 /*! TOIE - Timer Overflow Interrupt Enable 4413 * 0b0..Disable TOF interrupts. Use software polling. 4414 * 0b1..Enable TOF interrupts. An interrupt is generated when TOF equals one. 4415 */ 4416 #define FTM_SC_TOIE(x) (((uint32_t)(((uint32_t)(x)) << FTM_SC_TOIE_SHIFT)) & FTM_SC_TOIE_MASK) 4417 #define FTM_SC_TOF_MASK (0x80U) 4418 #define FTM_SC_TOF_SHIFT (7U) 4419 /*! TOF - Timer Overflow Flag 4420 * 0b0..FTM counter has not overflowed. 4421 * 0b1..FTM counter has overflowed. 4422 */ 4423 #define FTM_SC_TOF(x) (((uint32_t)(((uint32_t)(x)) << FTM_SC_TOF_SHIFT)) & FTM_SC_TOF_MASK) 4424 /*! @} */ 4425 4426 /*! @name CNT - Counter */ 4427 /*! @{ */ 4428 #define FTM_CNT_COUNT_MASK (0xFFFFU) 4429 #define FTM_CNT_COUNT_SHIFT (0U) 4430 #define FTM_CNT_COUNT(x) (((uint32_t)(((uint32_t)(x)) << FTM_CNT_COUNT_SHIFT)) & FTM_CNT_COUNT_MASK) 4431 /*! @} */ 4432 4433 /*! @name MOD - Modulo */ 4434 /*! @{ */ 4435 #define FTM_MOD_MOD_MASK (0xFFFFU) 4436 #define FTM_MOD_MOD_SHIFT (0U) 4437 #define FTM_MOD_MOD(x) (((uint32_t)(((uint32_t)(x)) << FTM_MOD_MOD_SHIFT)) & FTM_MOD_MOD_MASK) 4438 /*! @} */ 4439 4440 /*! @name CnSC - Channel (n) Status And Control */ 4441 /*! @{ */ 4442 #define FTM_CnSC_DMA_MASK (0x1U) 4443 #define FTM_CnSC_DMA_SHIFT (0U) 4444 /*! DMA - DMA Enable 4445 * 0b0..Disable DMA transfers. 4446 * 0b1..Enable DMA transfers. 4447 */ 4448 #define FTM_CnSC_DMA(x) (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_DMA_SHIFT)) & FTM_CnSC_DMA_MASK) 4449 #define FTM_CnSC_ICRST_MASK (0x2U) 4450 #define FTM_CnSC_ICRST_SHIFT (1U) 4451 /*! ICRST - FTM counter reset by the selected input capture event. 4452 * 0b0..FTM counter is not reset when the selected channel (n) input event is detected. 4453 * 0b1..FTM counter is reset when the selected channel (n) input event is detected. 4454 */ 4455 #define FTM_CnSC_ICRST(x) (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_ICRST_SHIFT)) & FTM_CnSC_ICRST_MASK) 4456 #define FTM_CnSC_ELSA_MASK (0x4U) 4457 #define FTM_CnSC_ELSA_SHIFT (2U) 4458 #define FTM_CnSC_ELSA(x) (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_ELSA_SHIFT)) & FTM_CnSC_ELSA_MASK) 4459 #define FTM_CnSC_ELSB_MASK (0x8U) 4460 #define FTM_CnSC_ELSB_SHIFT (3U) 4461 #define FTM_CnSC_ELSB(x) (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_ELSB_SHIFT)) & FTM_CnSC_ELSB_MASK) 4462 #define FTM_CnSC_MSA_MASK (0x10U) 4463 #define FTM_CnSC_MSA_SHIFT (4U) 4464 #define FTM_CnSC_MSA(x) (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_MSA_SHIFT)) & FTM_CnSC_MSA_MASK) 4465 #define FTM_CnSC_MSB_MASK (0x20U) 4466 #define FTM_CnSC_MSB_SHIFT (5U) 4467 #define FTM_CnSC_MSB(x) (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_MSB_SHIFT)) & FTM_CnSC_MSB_MASK) 4468 #define FTM_CnSC_CHIE_MASK (0x40U) 4469 #define FTM_CnSC_CHIE_SHIFT (6U) 4470 /*! CHIE - Channel Interrupt Enable 4471 * 0b0..Disable channel interrupts. Use software polling. 4472 * 0b1..Enable channel interrupts. 4473 */ 4474 #define FTM_CnSC_CHIE(x) (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_CHIE_SHIFT)) & FTM_CnSC_CHIE_MASK) 4475 #define FTM_CnSC_CHF_MASK (0x80U) 4476 #define FTM_CnSC_CHF_SHIFT (7U) 4477 /*! CHF - Channel Flag 4478 * 0b0..No channel event has occurred. 4479 * 0b1..A channel event has occurred. 4480 */ 4481 #define FTM_CnSC_CHF(x) (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_CHF_SHIFT)) & FTM_CnSC_CHF_MASK) 4482 /*! @} */ 4483 4484 /* The count of FTM_CnSC */ 4485 #define FTM_CnSC_COUNT (6U) 4486 4487 /*! @name CnV - Channel (n) Value */ 4488 /*! @{ */ 4489 #define FTM_CnV_VAL_MASK (0xFFFFU) 4490 #define FTM_CnV_VAL_SHIFT (0U) 4491 #define FTM_CnV_VAL(x) (((uint32_t)(((uint32_t)(x)) << FTM_CnV_VAL_SHIFT)) & FTM_CnV_VAL_MASK) 4492 /*! @} */ 4493 4494 /* The count of FTM_CnV */ 4495 #define FTM_CnV_COUNT (6U) 4496 4497 /*! @name CNTIN - Counter Initial Value */ 4498 /*! @{ */ 4499 #define FTM_CNTIN_INIT_MASK (0xFFFFU) 4500 #define FTM_CNTIN_INIT_SHIFT (0U) 4501 #define FTM_CNTIN_INIT(x) (((uint32_t)(((uint32_t)(x)) << FTM_CNTIN_INIT_SHIFT)) & FTM_CNTIN_INIT_MASK) 4502 /*! @} */ 4503 4504 /*! @name STATUS - Capture And Compare Status */ 4505 /*! @{ */ 4506 #define FTM_STATUS_CH0F_MASK (0x1U) 4507 #define FTM_STATUS_CH0F_SHIFT (0U) 4508 /*! CH0F - Channel 0 Flag 4509 * 0b0..No channel event has occurred. 4510 * 0b1..A channel event has occurred. 4511 */ 4512 #define FTM_STATUS_CH0F(x) (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH0F_SHIFT)) & FTM_STATUS_CH0F_MASK) 4513 #define FTM_STATUS_CH1F_MASK (0x2U) 4514 #define FTM_STATUS_CH1F_SHIFT (1U) 4515 /*! CH1F - Channel 1 Flag 4516 * 0b0..No channel event has occurred. 4517 * 0b1..A channel event has occurred. 4518 */ 4519 #define FTM_STATUS_CH1F(x) (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH1F_SHIFT)) & FTM_STATUS_CH1F_MASK) 4520 #define FTM_STATUS_CH2F_MASK (0x4U) 4521 #define FTM_STATUS_CH2F_SHIFT (2U) 4522 /*! CH2F - Channel 2 Flag 4523 * 0b0..No channel event has occurred. 4524 * 0b1..A channel event has occurred. 4525 */ 4526 #define FTM_STATUS_CH2F(x) (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH2F_SHIFT)) & FTM_STATUS_CH2F_MASK) 4527 #define FTM_STATUS_CH3F_MASK (0x8U) 4528 #define FTM_STATUS_CH3F_SHIFT (3U) 4529 /*! CH3F - Channel 3 Flag 4530 * 0b0..No channel event has occurred. 4531 * 0b1..A channel event has occurred. 4532 */ 4533 #define FTM_STATUS_CH3F(x) (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH3F_SHIFT)) & FTM_STATUS_CH3F_MASK) 4534 #define FTM_STATUS_CH4F_MASK (0x10U) 4535 #define FTM_STATUS_CH4F_SHIFT (4U) 4536 /*! CH4F - Channel 4 Flag 4537 * 0b0..No channel event has occurred. 4538 * 0b1..A channel event has occurred. 4539 */ 4540 #define FTM_STATUS_CH4F(x) (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH4F_SHIFT)) & FTM_STATUS_CH4F_MASK) 4541 #define FTM_STATUS_CH5F_MASK (0x20U) 4542 #define FTM_STATUS_CH5F_SHIFT (5U) 4543 /*! CH5F - Channel 5 Flag 4544 * 0b0..No channel event has occurred. 4545 * 0b1..A channel event has occurred. 4546 */ 4547 #define FTM_STATUS_CH5F(x) (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH5F_SHIFT)) & FTM_STATUS_CH5F_MASK) 4548 #define FTM_STATUS_CH6F_MASK (0x40U) 4549 #define FTM_STATUS_CH6F_SHIFT (6U) 4550 /*! CH6F - Channel 6 Flag 4551 * 0b0..No channel event has occurred. 4552 * 0b1..A channel event has occurred. 4553 */ 4554 #define FTM_STATUS_CH6F(x) (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH6F_SHIFT)) & FTM_STATUS_CH6F_MASK) 4555 #define FTM_STATUS_CH7F_MASK (0x80U) 4556 #define FTM_STATUS_CH7F_SHIFT (7U) 4557 /*! CH7F - Channel 7 Flag 4558 * 0b0..No channel event has occurred. 4559 * 0b1..A channel event has occurred. 4560 */ 4561 #define FTM_STATUS_CH7F(x) (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH7F_SHIFT)) & FTM_STATUS_CH7F_MASK) 4562 /*! @} */ 4563 4564 /*! @name MODE - Features Mode Selection */ 4565 /*! @{ */ 4566 #define FTM_MODE_FTMEN_MASK (0x1U) 4567 #define FTM_MODE_FTMEN_SHIFT (0U) 4568 /*! FTMEN - FTM Enable 4569 * 0b0..TPM compatibility. Free running counter and synchronization compatible with TPM. 4570 * 0b1..Free running counter and synchronization are different from TPM behavior. 4571 */ 4572 #define FTM_MODE_FTMEN(x) (((uint32_t)(((uint32_t)(x)) << FTM_MODE_FTMEN_SHIFT)) & FTM_MODE_FTMEN_MASK) 4573 #define FTM_MODE_INIT_MASK (0x2U) 4574 #define FTM_MODE_INIT_SHIFT (1U) 4575 #define FTM_MODE_INIT(x) (((uint32_t)(((uint32_t)(x)) << FTM_MODE_INIT_SHIFT)) & FTM_MODE_INIT_MASK) 4576 #define FTM_MODE_WPDIS_MASK (0x4U) 4577 #define FTM_MODE_WPDIS_SHIFT (2U) 4578 /*! WPDIS - Write Protection Disable 4579 * 0b0..Write protection is enabled. 4580 * 0b1..Write protection is disabled. 4581 */ 4582 #define FTM_MODE_WPDIS(x) (((uint32_t)(((uint32_t)(x)) << FTM_MODE_WPDIS_SHIFT)) & FTM_MODE_WPDIS_MASK) 4583 #define FTM_MODE_PWMSYNC_MASK (0x8U) 4584 #define FTM_MODE_PWMSYNC_SHIFT (3U) 4585 /*! PWMSYNC - PWM Synchronization Mode 4586 * 0b0..No restrictions. Software and hardware triggers can be used by MOD, CnV, OUTMASK, and FTM counter synchronization. 4587 * 0b1..Software trigger can only be used by MOD and CnV synchronization, and hardware triggers can only be used by OUTMASK and FTM counter synchronization. 4588 */ 4589 #define FTM_MODE_PWMSYNC(x) (((uint32_t)(((uint32_t)(x)) << FTM_MODE_PWMSYNC_SHIFT)) & FTM_MODE_PWMSYNC_MASK) 4590 #define FTM_MODE_CAPTEST_MASK (0x10U) 4591 #define FTM_MODE_CAPTEST_SHIFT (4U) 4592 /*! CAPTEST - Capture Test Mode Enable 4593 * 0b0..Capture test mode is disabled. 4594 * 0b1..Capture test mode is enabled. 4595 */ 4596 #define FTM_MODE_CAPTEST(x) (((uint32_t)(((uint32_t)(x)) << FTM_MODE_CAPTEST_SHIFT)) & FTM_MODE_CAPTEST_MASK) 4597 #define FTM_MODE_FAULTM_MASK (0x60U) 4598 #define FTM_MODE_FAULTM_SHIFT (5U) 4599 /*! FAULTM - Fault Control Mode 4600 * 0b00..Fault control is disabled for all channels. 4601 * 0b01..Fault control is enabled for even channels only (channels 0, 2, 4, and 6), and the selected mode is the manual fault clearing. 4602 * 0b10..Fault control is enabled for all channels, and the selected mode is the manual fault clearing. 4603 * 0b11..Fault control is enabled for all channels, and the selected mode is the automatic fault clearing. 4604 */ 4605 #define FTM_MODE_FAULTM(x) (((uint32_t)(((uint32_t)(x)) << FTM_MODE_FAULTM_SHIFT)) & FTM_MODE_FAULTM_MASK) 4606 #define FTM_MODE_FAULTIE_MASK (0x80U) 4607 #define FTM_MODE_FAULTIE_SHIFT (7U) 4608 /*! FAULTIE - Fault Interrupt Enable 4609 * 0b0..Fault control interrupt is disabled. 4610 * 0b1..Fault control interrupt is enabled. 4611 */ 4612 #define FTM_MODE_FAULTIE(x) (((uint32_t)(((uint32_t)(x)) << FTM_MODE_FAULTIE_SHIFT)) & FTM_MODE_FAULTIE_MASK) 4613 /*! @} */ 4614 4615 /*! @name SYNC - Synchronization */ 4616 /*! @{ */ 4617 #define FTM_SYNC_CNTMIN_MASK (0x1U) 4618 #define FTM_SYNC_CNTMIN_SHIFT (0U) 4619 /*! CNTMIN - Minimum Loading Point Enable 4620 * 0b0..The minimum loading point is disabled. 4621 * 0b1..The minimum loading point is enabled. 4622 */ 4623 #define FTM_SYNC_CNTMIN(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_CNTMIN_SHIFT)) & FTM_SYNC_CNTMIN_MASK) 4624 #define FTM_SYNC_CNTMAX_MASK (0x2U) 4625 #define FTM_SYNC_CNTMAX_SHIFT (1U) 4626 /*! CNTMAX - Maximum Loading Point Enable 4627 * 0b0..The maximum loading point is disabled. 4628 * 0b1..The maximum loading point is enabled. 4629 */ 4630 #define FTM_SYNC_CNTMAX(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_CNTMAX_SHIFT)) & FTM_SYNC_CNTMAX_MASK) 4631 #define FTM_SYNC_REINIT_MASK (0x4U) 4632 #define FTM_SYNC_REINIT_SHIFT (2U) 4633 /*! REINIT - FTM Counter Reinitialization By Synchronization (FTM counter synchronization) 4634 * 0b0..FTM counter continues to count normally. 4635 * 0b1..FTM counter is updated with its initial value when the selected trigger is detected. 4636 */ 4637 #define FTM_SYNC_REINIT(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_REINIT_SHIFT)) & FTM_SYNC_REINIT_MASK) 4638 #define FTM_SYNC_SYNCHOM_MASK (0x8U) 4639 #define FTM_SYNC_SYNCHOM_SHIFT (3U) 4640 /*! SYNCHOM - Output Mask Synchronization 4641 * 0b0..OUTMASK register is updated with the value of its buffer in all rising edges of the system clock. 4642 * 0b1..OUTMASK register is updated with the value of its buffer only by the PWM synchronization. 4643 */ 4644 #define FTM_SYNC_SYNCHOM(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_SYNCHOM_SHIFT)) & FTM_SYNC_SYNCHOM_MASK) 4645 #define FTM_SYNC_TRIG0_MASK (0x10U) 4646 #define FTM_SYNC_TRIG0_SHIFT (4U) 4647 /*! TRIG0 - PWM Synchronization Hardware Trigger 0 4648 * 0b0..Trigger is disabled. 4649 * 0b1..Trigger is enabled. 4650 */ 4651 #define FTM_SYNC_TRIG0(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_TRIG0_SHIFT)) & FTM_SYNC_TRIG0_MASK) 4652 #define FTM_SYNC_TRIG1_MASK (0x20U) 4653 #define FTM_SYNC_TRIG1_SHIFT (5U) 4654 /*! TRIG1 - PWM Synchronization Hardware Trigger 1 4655 * 0b0..Trigger is disabled. 4656 * 0b1..Trigger is enabled. 4657 */ 4658 #define FTM_SYNC_TRIG1(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_TRIG1_SHIFT)) & FTM_SYNC_TRIG1_MASK) 4659 #define FTM_SYNC_TRIG2_MASK (0x40U) 4660 #define FTM_SYNC_TRIG2_SHIFT (6U) 4661 /*! TRIG2 - PWM Synchronization Hardware Trigger 2 4662 * 0b0..Trigger is disabled. 4663 * 0b1..Trigger is enabled. 4664 */ 4665 #define FTM_SYNC_TRIG2(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_TRIG2_SHIFT)) & FTM_SYNC_TRIG2_MASK) 4666 #define FTM_SYNC_SWSYNC_MASK (0x80U) 4667 #define FTM_SYNC_SWSYNC_SHIFT (7U) 4668 /*! SWSYNC - PWM Synchronization Software Trigger 4669 * 0b0..Software trigger is not selected. 4670 * 0b1..Software trigger is selected. 4671 */ 4672 #define FTM_SYNC_SWSYNC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_SWSYNC_SHIFT)) & FTM_SYNC_SWSYNC_MASK) 4673 /*! @} */ 4674 4675 /*! @name OUTINIT - Initial State For Channels Output */ 4676 /*! @{ */ 4677 #define FTM_OUTINIT_CH0OI_MASK (0x1U) 4678 #define FTM_OUTINIT_CH0OI_SHIFT (0U) 4679 /*! CH0OI - Channel 0 Output Initialization Value 4680 * 0b0..The initialization value is 0. 4681 * 0b1..The initialization value is 1. 4682 */ 4683 #define FTM_OUTINIT_CH0OI(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH0OI_SHIFT)) & FTM_OUTINIT_CH0OI_MASK) 4684 #define FTM_OUTINIT_CH1OI_MASK (0x2U) 4685 #define FTM_OUTINIT_CH1OI_SHIFT (1U) 4686 /*! CH1OI - Channel 1 Output Initialization Value 4687 * 0b0..The initialization value is 0. 4688 * 0b1..The initialization value is 1. 4689 */ 4690 #define FTM_OUTINIT_CH1OI(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH1OI_SHIFT)) & FTM_OUTINIT_CH1OI_MASK) 4691 #define FTM_OUTINIT_CH2OI_MASK (0x4U) 4692 #define FTM_OUTINIT_CH2OI_SHIFT (2U) 4693 /*! CH2OI - Channel 2 Output Initialization Value 4694 * 0b0..The initialization value is 0. 4695 * 0b1..The initialization value is 1. 4696 */ 4697 #define FTM_OUTINIT_CH2OI(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH2OI_SHIFT)) & FTM_OUTINIT_CH2OI_MASK) 4698 #define FTM_OUTINIT_CH3OI_MASK (0x8U) 4699 #define FTM_OUTINIT_CH3OI_SHIFT (3U) 4700 /*! CH3OI - Channel 3 Output Initialization Value 4701 * 0b0..The initialization value is 0. 4702 * 0b1..The initialization value is 1. 4703 */ 4704 #define FTM_OUTINIT_CH3OI(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH3OI_SHIFT)) & FTM_OUTINIT_CH3OI_MASK) 4705 #define FTM_OUTINIT_CH4OI_MASK (0x10U) 4706 #define FTM_OUTINIT_CH4OI_SHIFT (4U) 4707 /*! CH4OI - Channel 4 Output Initialization Value 4708 * 0b0..The initialization value is 0. 4709 * 0b1..The initialization value is 1. 4710 */ 4711 #define FTM_OUTINIT_CH4OI(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH4OI_SHIFT)) & FTM_OUTINIT_CH4OI_MASK) 4712 #define FTM_OUTINIT_CH5OI_MASK (0x20U) 4713 #define FTM_OUTINIT_CH5OI_SHIFT (5U) 4714 /*! CH5OI - Channel 5 Output Initialization Value 4715 * 0b0..The initialization value is 0. 4716 * 0b1..The initialization value is 1. 4717 */ 4718 #define FTM_OUTINIT_CH5OI(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH5OI_SHIFT)) & FTM_OUTINIT_CH5OI_MASK) 4719 #define FTM_OUTINIT_CH6OI_MASK (0x40U) 4720 #define FTM_OUTINIT_CH6OI_SHIFT (6U) 4721 /*! CH6OI - Channel 6 Output Initialization Value 4722 * 0b0..The initialization value is 0. 4723 * 0b1..The initialization value is 1. 4724 */ 4725 #define FTM_OUTINIT_CH6OI(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH6OI_SHIFT)) & FTM_OUTINIT_CH6OI_MASK) 4726 #define FTM_OUTINIT_CH7OI_MASK (0x80U) 4727 #define FTM_OUTINIT_CH7OI_SHIFT (7U) 4728 /*! CH7OI - Channel 7 Output Initialization Value 4729 * 0b0..The initialization value is 0. 4730 * 0b1..The initialization value is 1. 4731 */ 4732 #define FTM_OUTINIT_CH7OI(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH7OI_SHIFT)) & FTM_OUTINIT_CH7OI_MASK) 4733 /*! @} */ 4734 4735 /*! @name OUTMASK - Output Mask */ 4736 /*! @{ */ 4737 #define FTM_OUTMASK_CH0OM_MASK (0x1U) 4738 #define FTM_OUTMASK_CH0OM_SHIFT (0U) 4739 /*! CH0OM - Channel 0 Output Mask 4740 * 0b0..Channel output is not masked. It continues to operate normally. 4741 * 0b1..Channel output is masked. It is forced to its inactive state. 4742 */ 4743 #define FTM_OUTMASK_CH0OM(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH0OM_SHIFT)) & FTM_OUTMASK_CH0OM_MASK) 4744 #define FTM_OUTMASK_CH1OM_MASK (0x2U) 4745 #define FTM_OUTMASK_CH1OM_SHIFT (1U) 4746 /*! CH1OM - Channel 1 Output Mask 4747 * 0b0..Channel output is not masked. It continues to operate normally. 4748 * 0b1..Channel output is masked. It is forced to its inactive state. 4749 */ 4750 #define FTM_OUTMASK_CH1OM(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH1OM_SHIFT)) & FTM_OUTMASK_CH1OM_MASK) 4751 #define FTM_OUTMASK_CH2OM_MASK (0x4U) 4752 #define FTM_OUTMASK_CH2OM_SHIFT (2U) 4753 /*! CH2OM - Channel 2 Output Mask 4754 * 0b0..Channel output is not masked. It continues to operate normally. 4755 * 0b1..Channel output is masked. It is forced to its inactive state. 4756 */ 4757 #define FTM_OUTMASK_CH2OM(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH2OM_SHIFT)) & FTM_OUTMASK_CH2OM_MASK) 4758 #define FTM_OUTMASK_CH3OM_MASK (0x8U) 4759 #define FTM_OUTMASK_CH3OM_SHIFT (3U) 4760 /*! CH3OM - Channel 3 Output Mask 4761 * 0b0..Channel output is not masked. It continues to operate normally. 4762 * 0b1..Channel output is masked. It is forced to its inactive state. 4763 */ 4764 #define FTM_OUTMASK_CH3OM(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH3OM_SHIFT)) & FTM_OUTMASK_CH3OM_MASK) 4765 #define FTM_OUTMASK_CH4OM_MASK (0x10U) 4766 #define FTM_OUTMASK_CH4OM_SHIFT (4U) 4767 /*! CH4OM - Channel 4 Output Mask 4768 * 0b0..Channel output is not masked. It continues to operate normally. 4769 * 0b1..Channel output is masked. It is forced to its inactive state. 4770 */ 4771 #define FTM_OUTMASK_CH4OM(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH4OM_SHIFT)) & FTM_OUTMASK_CH4OM_MASK) 4772 #define FTM_OUTMASK_CH5OM_MASK (0x20U) 4773 #define FTM_OUTMASK_CH5OM_SHIFT (5U) 4774 /*! CH5OM - Channel 5 Output Mask 4775 * 0b0..Channel output is not masked. It continues to operate normally. 4776 * 0b1..Channel output is masked. It is forced to its inactive state. 4777 */ 4778 #define FTM_OUTMASK_CH5OM(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH5OM_SHIFT)) & FTM_OUTMASK_CH5OM_MASK) 4779 #define FTM_OUTMASK_CH6OM_MASK (0x40U) 4780 #define FTM_OUTMASK_CH6OM_SHIFT (6U) 4781 /*! CH6OM - Channel 6 Output Mask 4782 * 0b0..Channel output is not masked. It continues to operate normally. 4783 * 0b1..Channel output is masked. It is forced to its inactive state. 4784 */ 4785 #define FTM_OUTMASK_CH6OM(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH6OM_SHIFT)) & FTM_OUTMASK_CH6OM_MASK) 4786 #define FTM_OUTMASK_CH7OM_MASK (0x80U) 4787 #define FTM_OUTMASK_CH7OM_SHIFT (7U) 4788 /*! CH7OM - Channel 7 Output Mask 4789 * 0b0..Channel output is not masked. It continues to operate normally. 4790 * 0b1..Channel output is masked. It is forced to its inactive state. 4791 */ 4792 #define FTM_OUTMASK_CH7OM(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH7OM_SHIFT)) & FTM_OUTMASK_CH7OM_MASK) 4793 /*! @} */ 4794 4795 /*! @name COMBINE - Function For Linked Channels */ 4796 /*! @{ */ 4797 #define FTM_COMBINE_COMBINE0_MASK (0x1U) 4798 #define FTM_COMBINE_COMBINE0_SHIFT (0U) 4799 /*! COMBINE0 - Combine Channels For n = 0 4800 * 0b0..Channels (n) and (n+1) are independent. 4801 * 0b1..Channels (n) and (n+1) are combined. 4802 */ 4803 #define FTM_COMBINE_COMBINE0(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMBINE0_SHIFT)) & FTM_COMBINE_COMBINE0_MASK) 4804 #define FTM_COMBINE_COMP0_MASK (0x2U) 4805 #define FTM_COMBINE_COMP0_SHIFT (1U) 4806 /*! COMP0 - Complement Of Channel (n) For n = 0 4807 * 0b0..The channel (n+1) output is the same as the channel (n) output. 4808 * 0b1..The channel (n+1) output is the complement of the channel (n) output. 4809 */ 4810 #define FTM_COMBINE_COMP0(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMP0_SHIFT)) & FTM_COMBINE_COMP0_MASK) 4811 #define FTM_COMBINE_DECAPEN0_MASK (0x4U) 4812 #define FTM_COMBINE_DECAPEN0_SHIFT (2U) 4813 /*! DECAPEN0 - Dual Edge Capture Mode Enable For n = 0 4814 * 0b0..The Dual Edge Capture mode in this pair of channels is disabled. 4815 * 0b1..The Dual Edge Capture mode in this pair of channels is enabled. 4816 */ 4817 #define FTM_COMBINE_DECAPEN0(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAPEN0_SHIFT)) & FTM_COMBINE_DECAPEN0_MASK) 4818 #define FTM_COMBINE_DECAP0_MASK (0x8U) 4819 #define FTM_COMBINE_DECAP0_SHIFT (3U) 4820 /*! DECAP0 - Dual Edge Capture Mode Captures For n = 0 4821 * 0b0..The dual edge captures are inactive. 4822 * 0b1..The dual edge captures are active. 4823 */ 4824 #define FTM_COMBINE_DECAP0(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAP0_SHIFT)) & FTM_COMBINE_DECAP0_MASK) 4825 #define FTM_COMBINE_DTEN0_MASK (0x10U) 4826 #define FTM_COMBINE_DTEN0_SHIFT (4U) 4827 /*! DTEN0 - Deadtime Enable For n = 0 4828 * 0b0..The deadtime insertion in this pair of channels is disabled. 4829 * 0b1..The deadtime insertion in this pair of channels is enabled. 4830 */ 4831 #define FTM_COMBINE_DTEN0(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DTEN0_SHIFT)) & FTM_COMBINE_DTEN0_MASK) 4832 #define FTM_COMBINE_SYNCEN0_MASK (0x20U) 4833 #define FTM_COMBINE_SYNCEN0_SHIFT (5U) 4834 /*! SYNCEN0 - Synchronization Enable For n = 0 4835 * 0b0..The PWM synchronization in this pair of channels is disabled. 4836 * 0b1..The PWM synchronization in this pair of channels is enabled. 4837 */ 4838 #define FTM_COMBINE_SYNCEN0(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_SYNCEN0_SHIFT)) & FTM_COMBINE_SYNCEN0_MASK) 4839 #define FTM_COMBINE_FAULTEN0_MASK (0x40U) 4840 #define FTM_COMBINE_FAULTEN0_SHIFT (6U) 4841 /*! FAULTEN0 - Fault Control Enable For n = 0 4842 * 0b0..The fault control in this pair of channels is disabled. 4843 * 0b1..The fault control in this pair of channels is enabled. 4844 */ 4845 #define FTM_COMBINE_FAULTEN0(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_FAULTEN0_SHIFT)) & FTM_COMBINE_FAULTEN0_MASK) 4846 #define FTM_COMBINE_COMBINE1_MASK (0x100U) 4847 #define FTM_COMBINE_COMBINE1_SHIFT (8U) 4848 /*! COMBINE1 - Combine Channels For n = 2 4849 * 0b0..Channels (n) and (n+1) are independent. 4850 * 0b1..Channels (n) and (n+1) are combined. 4851 */ 4852 #define FTM_COMBINE_COMBINE1(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMBINE1_SHIFT)) & FTM_COMBINE_COMBINE1_MASK) 4853 #define FTM_COMBINE_COMP1_MASK (0x200U) 4854 #define FTM_COMBINE_COMP1_SHIFT (9U) 4855 /*! COMP1 - Complement Of Channel (n) For n = 2 4856 * 0b0..The channel (n+1) output is the same as the channel (n) output. 4857 * 0b1..The channel (n+1) output is the complement of the channel (n) output. 4858 */ 4859 #define FTM_COMBINE_COMP1(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMP1_SHIFT)) & FTM_COMBINE_COMP1_MASK) 4860 #define FTM_COMBINE_DECAPEN1_MASK (0x400U) 4861 #define FTM_COMBINE_DECAPEN1_SHIFT (10U) 4862 /*! DECAPEN1 - Dual Edge Capture Mode Enable For n = 2 4863 * 0b0..The Dual Edge Capture mode in this pair of channels is disabled. 4864 * 0b1..The Dual Edge Capture mode in this pair of channels is enabled. 4865 */ 4866 #define FTM_COMBINE_DECAPEN1(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAPEN1_SHIFT)) & FTM_COMBINE_DECAPEN1_MASK) 4867 #define FTM_COMBINE_DECAP1_MASK (0x800U) 4868 #define FTM_COMBINE_DECAP1_SHIFT (11U) 4869 /*! DECAP1 - Dual Edge Capture Mode Captures For n = 2 4870 * 0b0..The dual edge captures are inactive. 4871 * 0b1..The dual edge captures are active. 4872 */ 4873 #define FTM_COMBINE_DECAP1(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAP1_SHIFT)) & FTM_COMBINE_DECAP1_MASK) 4874 #define FTM_COMBINE_DTEN1_MASK (0x1000U) 4875 #define FTM_COMBINE_DTEN1_SHIFT (12U) 4876 /*! DTEN1 - Deadtime Enable For n = 2 4877 * 0b0..The deadtime insertion in this pair of channels is disabled. 4878 * 0b1..The deadtime insertion in this pair of channels is enabled. 4879 */ 4880 #define FTM_COMBINE_DTEN1(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DTEN1_SHIFT)) & FTM_COMBINE_DTEN1_MASK) 4881 #define FTM_COMBINE_SYNCEN1_MASK (0x2000U) 4882 #define FTM_COMBINE_SYNCEN1_SHIFT (13U) 4883 /*! SYNCEN1 - Synchronization Enable For n = 2 4884 * 0b0..The PWM synchronization in this pair of channels is disabled. 4885 * 0b1..The PWM synchronization in this pair of channels is enabled. 4886 */ 4887 #define FTM_COMBINE_SYNCEN1(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_SYNCEN1_SHIFT)) & FTM_COMBINE_SYNCEN1_MASK) 4888 #define FTM_COMBINE_FAULTEN1_MASK (0x4000U) 4889 #define FTM_COMBINE_FAULTEN1_SHIFT (14U) 4890 /*! FAULTEN1 - Fault Control Enable For n = 2 4891 * 0b0..The fault control in this pair of channels is disabled. 4892 * 0b1..The fault control in this pair of channels is enabled. 4893 */ 4894 #define FTM_COMBINE_FAULTEN1(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_FAULTEN1_SHIFT)) & FTM_COMBINE_FAULTEN1_MASK) 4895 #define FTM_COMBINE_COMBINE2_MASK (0x10000U) 4896 #define FTM_COMBINE_COMBINE2_SHIFT (16U) 4897 /*! COMBINE2 - Combine Channels For n = 4 4898 * 0b0..Channels (n) and (n+1) are independent. 4899 * 0b1..Channels (n) and (n+1) are combined. 4900 */ 4901 #define FTM_COMBINE_COMBINE2(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMBINE2_SHIFT)) & FTM_COMBINE_COMBINE2_MASK) 4902 #define FTM_COMBINE_COMP2_MASK (0x20000U) 4903 #define FTM_COMBINE_COMP2_SHIFT (17U) 4904 /*! COMP2 - Complement Of Channel (n) For n = 4 4905 * 0b0..The channel (n+1) output is the same as the channel (n) output. 4906 * 0b1..The channel (n+1) output is the complement of the channel (n) output. 4907 */ 4908 #define FTM_COMBINE_COMP2(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMP2_SHIFT)) & FTM_COMBINE_COMP2_MASK) 4909 #define FTM_COMBINE_DECAPEN2_MASK (0x40000U) 4910 #define FTM_COMBINE_DECAPEN2_SHIFT (18U) 4911 /*! DECAPEN2 - Dual Edge Capture Mode Enable For n = 4 4912 * 0b0..The Dual Edge Capture mode in this pair of channels is disabled. 4913 * 0b1..The Dual Edge Capture mode in this pair of channels is enabled. 4914 */ 4915 #define FTM_COMBINE_DECAPEN2(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAPEN2_SHIFT)) & FTM_COMBINE_DECAPEN2_MASK) 4916 #define FTM_COMBINE_DECAP2_MASK (0x80000U) 4917 #define FTM_COMBINE_DECAP2_SHIFT (19U) 4918 /*! DECAP2 - Dual Edge Capture Mode Captures For n = 4 4919 * 0b0..The dual edge captures are inactive. 4920 * 0b1..The dual edge captures are active. 4921 */ 4922 #define FTM_COMBINE_DECAP2(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAP2_SHIFT)) & FTM_COMBINE_DECAP2_MASK) 4923 #define FTM_COMBINE_DTEN2_MASK (0x100000U) 4924 #define FTM_COMBINE_DTEN2_SHIFT (20U) 4925 /*! DTEN2 - Deadtime Enable For n = 4 4926 * 0b0..The deadtime insertion in this pair of channels is disabled. 4927 * 0b1..The deadtime insertion in this pair of channels is enabled. 4928 */ 4929 #define FTM_COMBINE_DTEN2(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DTEN2_SHIFT)) & FTM_COMBINE_DTEN2_MASK) 4930 #define FTM_COMBINE_SYNCEN2_MASK (0x200000U) 4931 #define FTM_COMBINE_SYNCEN2_SHIFT (21U) 4932 /*! SYNCEN2 - Synchronization Enable For n = 4 4933 * 0b0..The PWM synchronization in this pair of channels is disabled. 4934 * 0b1..The PWM synchronization in this pair of channels is enabled. 4935 */ 4936 #define FTM_COMBINE_SYNCEN2(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_SYNCEN2_SHIFT)) & FTM_COMBINE_SYNCEN2_MASK) 4937 #define FTM_COMBINE_FAULTEN2_MASK (0x400000U) 4938 #define FTM_COMBINE_FAULTEN2_SHIFT (22U) 4939 /*! FAULTEN2 - Fault Control Enable For n = 4 4940 * 0b0..The fault control in this pair of channels is disabled. 4941 * 0b1..The fault control in this pair of channels is enabled. 4942 */ 4943 #define FTM_COMBINE_FAULTEN2(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_FAULTEN2_SHIFT)) & FTM_COMBINE_FAULTEN2_MASK) 4944 #define FTM_COMBINE_COMBINE3_MASK (0x1000000U) 4945 #define FTM_COMBINE_COMBINE3_SHIFT (24U) 4946 /*! COMBINE3 - Combine Channels For n = 6 4947 * 0b0..Channels (n) and (n+1) are independent. 4948 * 0b1..Channels (n) and (n+1) are combined. 4949 */ 4950 #define FTM_COMBINE_COMBINE3(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMBINE3_SHIFT)) & FTM_COMBINE_COMBINE3_MASK) 4951 #define FTM_COMBINE_COMP3_MASK (0x2000000U) 4952 #define FTM_COMBINE_COMP3_SHIFT (25U) 4953 /*! COMP3 - Complement Of Channel (n) for n = 6 4954 * 0b0..The channel (n+1) output is the same as the channel (n) output. 4955 * 0b1..The channel (n+1) output is the complement of the channel (n) output. 4956 */ 4957 #define FTM_COMBINE_COMP3(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMP3_SHIFT)) & FTM_COMBINE_COMP3_MASK) 4958 #define FTM_COMBINE_DECAPEN3_MASK (0x4000000U) 4959 #define FTM_COMBINE_DECAPEN3_SHIFT (26U) 4960 /*! DECAPEN3 - Dual Edge Capture Mode Enable For n = 6 4961 * 0b0..The Dual Edge Capture mode in this pair of channels is disabled. 4962 * 0b1..The Dual Edge Capture mode in this pair of channels is enabled. 4963 */ 4964 #define FTM_COMBINE_DECAPEN3(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAPEN3_SHIFT)) & FTM_COMBINE_DECAPEN3_MASK) 4965 #define FTM_COMBINE_DECAP3_MASK (0x8000000U) 4966 #define FTM_COMBINE_DECAP3_SHIFT (27U) 4967 /*! DECAP3 - Dual Edge Capture Mode Captures For n = 6 4968 * 0b0..The dual edge captures are inactive. 4969 * 0b1..The dual edge captures are active. 4970 */ 4971 #define FTM_COMBINE_DECAP3(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAP3_SHIFT)) & FTM_COMBINE_DECAP3_MASK) 4972 #define FTM_COMBINE_DTEN3_MASK (0x10000000U) 4973 #define FTM_COMBINE_DTEN3_SHIFT (28U) 4974 /*! DTEN3 - Deadtime Enable For n = 6 4975 * 0b0..The deadtime insertion in this pair of channels is disabled. 4976 * 0b1..The deadtime insertion in this pair of channels is enabled. 4977 */ 4978 #define FTM_COMBINE_DTEN3(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DTEN3_SHIFT)) & FTM_COMBINE_DTEN3_MASK) 4979 #define FTM_COMBINE_SYNCEN3_MASK (0x20000000U) 4980 #define FTM_COMBINE_SYNCEN3_SHIFT (29U) 4981 /*! SYNCEN3 - Synchronization Enable For n = 6 4982 * 0b0..The PWM synchronization in this pair of channels is disabled. 4983 * 0b1..The PWM synchronization in this pair of channels is enabled. 4984 */ 4985 #define FTM_COMBINE_SYNCEN3(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_SYNCEN3_SHIFT)) & FTM_COMBINE_SYNCEN3_MASK) 4986 #define FTM_COMBINE_FAULTEN3_MASK (0x40000000U) 4987 #define FTM_COMBINE_FAULTEN3_SHIFT (30U) 4988 /*! FAULTEN3 - Fault Control Enable For n = 6 4989 * 0b0..The fault control in this pair of channels is disabled. 4990 * 0b1..The fault control in this pair of channels is enabled. 4991 */ 4992 #define FTM_COMBINE_FAULTEN3(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_FAULTEN3_SHIFT)) & FTM_COMBINE_FAULTEN3_MASK) 4993 /*! @} */ 4994 4995 /*! @name DEADTIME - Deadtime Insertion Control */ 4996 /*! @{ */ 4997 #define FTM_DEADTIME_DTVAL_MASK (0x3FU) 4998 #define FTM_DEADTIME_DTVAL_SHIFT (0U) 4999 #define FTM_DEADTIME_DTVAL(x) (((uint32_t)(((uint32_t)(x)) << FTM_DEADTIME_DTVAL_SHIFT)) & FTM_DEADTIME_DTVAL_MASK) 5000 #define FTM_DEADTIME_DTPS_MASK (0xC0U) 5001 #define FTM_DEADTIME_DTPS_SHIFT (6U) 5002 /*! DTPS - Deadtime Prescaler Value 5003 * 0b0x..Divide the system clock by 1. 5004 * 0b10..Divide the system clock by 4. 5005 * 0b11..Divide the system clock by 16. 5006 */ 5007 #define FTM_DEADTIME_DTPS(x) (((uint32_t)(((uint32_t)(x)) << FTM_DEADTIME_DTPS_SHIFT)) & FTM_DEADTIME_DTPS_MASK) 5008 /*! @} */ 5009 5010 /*! @name EXTTRIG - FTM External Trigger */ 5011 /*! @{ */ 5012 #define FTM_EXTTRIG_CH2TRIG_MASK (0x1U) 5013 #define FTM_EXTTRIG_CH2TRIG_SHIFT (0U) 5014 /*! CH2TRIG - Channel 2 Trigger Enable 5015 * 0b0..The generation of the channel trigger is disabled. 5016 * 0b1..The generation of the channel trigger is enabled. 5017 */ 5018 #define FTM_EXTTRIG_CH2TRIG(x) (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_CH2TRIG_SHIFT)) & FTM_EXTTRIG_CH2TRIG_MASK) 5019 #define FTM_EXTTRIG_CH3TRIG_MASK (0x2U) 5020 #define FTM_EXTTRIG_CH3TRIG_SHIFT (1U) 5021 /*! CH3TRIG - Channel 3 Trigger Enable 5022 * 0b0..The generation of the channel trigger is disabled. 5023 * 0b1..The generation of the channel trigger is enabled. 5024 */ 5025 #define FTM_EXTTRIG_CH3TRIG(x) (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_CH3TRIG_SHIFT)) & FTM_EXTTRIG_CH3TRIG_MASK) 5026 #define FTM_EXTTRIG_CH4TRIG_MASK (0x4U) 5027 #define FTM_EXTTRIG_CH4TRIG_SHIFT (2U) 5028 /*! CH4TRIG - Channel 4 Trigger Enable 5029 * 0b0..The generation of the channel trigger is disabled. 5030 * 0b1..The generation of the channel trigger is enabled. 5031 */ 5032 #define FTM_EXTTRIG_CH4TRIG(x) (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_CH4TRIG_SHIFT)) & FTM_EXTTRIG_CH4TRIG_MASK) 5033 #define FTM_EXTTRIG_CH5TRIG_MASK (0x8U) 5034 #define FTM_EXTTRIG_CH5TRIG_SHIFT (3U) 5035 /*! CH5TRIG - Channel 5 Trigger Enable 5036 * 0b0..The generation of the channel trigger is disabled. 5037 * 0b1..The generation of the channel trigger is enabled. 5038 */ 5039 #define FTM_EXTTRIG_CH5TRIG(x) (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_CH5TRIG_SHIFT)) & FTM_EXTTRIG_CH5TRIG_MASK) 5040 #define FTM_EXTTRIG_CH0TRIG_MASK (0x10U) 5041 #define FTM_EXTTRIG_CH0TRIG_SHIFT (4U) 5042 /*! CH0TRIG - Channel 0 Trigger Enable 5043 * 0b0..The generation of the channel trigger is disabled. 5044 * 0b1..The generation of the channel trigger is enabled. 5045 */ 5046 #define FTM_EXTTRIG_CH0TRIG(x) (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_CH0TRIG_SHIFT)) & FTM_EXTTRIG_CH0TRIG_MASK) 5047 #define FTM_EXTTRIG_CH1TRIG_MASK (0x20U) 5048 #define FTM_EXTTRIG_CH1TRIG_SHIFT (5U) 5049 /*! CH1TRIG - Channel 1 Trigger Enable 5050 * 0b0..The generation of the channel trigger is disabled. 5051 * 0b1..The generation of the channel trigger is enabled. 5052 */ 5053 #define FTM_EXTTRIG_CH1TRIG(x) (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_CH1TRIG_SHIFT)) & FTM_EXTTRIG_CH1TRIG_MASK) 5054 #define FTM_EXTTRIG_INITTRIGEN_MASK (0x40U) 5055 #define FTM_EXTTRIG_INITTRIGEN_SHIFT (6U) 5056 /*! INITTRIGEN - Initialization Trigger Enable 5057 * 0b0..The generation of initialization trigger is disabled. 5058 * 0b1..The generation of initialization trigger is enabled. 5059 */ 5060 #define FTM_EXTTRIG_INITTRIGEN(x) (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_INITTRIGEN_SHIFT)) & FTM_EXTTRIG_INITTRIGEN_MASK) 5061 #define FTM_EXTTRIG_TRIGF_MASK (0x80U) 5062 #define FTM_EXTTRIG_TRIGF_SHIFT (7U) 5063 /*! TRIGF - Channel Trigger Flag 5064 * 0b0..No channel trigger was generated. 5065 * 0b1..A channel trigger was generated. 5066 */ 5067 #define FTM_EXTTRIG_TRIGF(x) (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_TRIGF_SHIFT)) & FTM_EXTTRIG_TRIGF_MASK) 5068 /*! @} */ 5069 5070 /*! @name POL - Channels Polarity */ 5071 /*! @{ */ 5072 #define FTM_POL_POL0_MASK (0x1U) 5073 #define FTM_POL_POL0_SHIFT (0U) 5074 /*! POL0 - Channel 0 Polarity 5075 * 0b0..The channel polarity is active high. 5076 * 0b1..The channel polarity is active low. 5077 */ 5078 #define FTM_POL_POL0(x) (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL0_SHIFT)) & FTM_POL_POL0_MASK) 5079 #define FTM_POL_POL1_MASK (0x2U) 5080 #define FTM_POL_POL1_SHIFT (1U) 5081 /*! POL1 - Channel 1 Polarity 5082 * 0b0..The channel polarity is active high. 5083 * 0b1..The channel polarity is active low. 5084 */ 5085 #define FTM_POL_POL1(x) (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL1_SHIFT)) & FTM_POL_POL1_MASK) 5086 #define FTM_POL_POL2_MASK (0x4U) 5087 #define FTM_POL_POL2_SHIFT (2U) 5088 /*! POL2 - Channel 2 Polarity 5089 * 0b0..The channel polarity is active high. 5090 * 0b1..The channel polarity is active low. 5091 */ 5092 #define FTM_POL_POL2(x) (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL2_SHIFT)) & FTM_POL_POL2_MASK) 5093 #define FTM_POL_POL3_MASK (0x8U) 5094 #define FTM_POL_POL3_SHIFT (3U) 5095 /*! POL3 - Channel 3 Polarity 5096 * 0b0..The channel polarity is active high. 5097 * 0b1..The channel polarity is active low. 5098 */ 5099 #define FTM_POL_POL3(x) (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL3_SHIFT)) & FTM_POL_POL3_MASK) 5100 #define FTM_POL_POL4_MASK (0x10U) 5101 #define FTM_POL_POL4_SHIFT (4U) 5102 /*! POL4 - Channel 4 Polarity 5103 * 0b0..The channel polarity is active high. 5104 * 0b1..The channel polarity is active low. 5105 */ 5106 #define FTM_POL_POL4(x) (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL4_SHIFT)) & FTM_POL_POL4_MASK) 5107 #define FTM_POL_POL5_MASK (0x20U) 5108 #define FTM_POL_POL5_SHIFT (5U) 5109 /*! POL5 - Channel 5 Polarity 5110 * 0b0..The channel polarity is active high. 5111 * 0b1..The channel polarity is active low. 5112 */ 5113 #define FTM_POL_POL5(x) (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL5_SHIFT)) & FTM_POL_POL5_MASK) 5114 #define FTM_POL_POL6_MASK (0x40U) 5115 #define FTM_POL_POL6_SHIFT (6U) 5116 /*! POL6 - Channel 6 Polarity 5117 * 0b0..The channel polarity is active high. 5118 * 0b1..The channel polarity is active low. 5119 */ 5120 #define FTM_POL_POL6(x) (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL6_SHIFT)) & FTM_POL_POL6_MASK) 5121 #define FTM_POL_POL7_MASK (0x80U) 5122 #define FTM_POL_POL7_SHIFT (7U) 5123 /*! POL7 - Channel 7 Polarity 5124 * 0b0..The channel polarity is active high. 5125 * 0b1..The channel polarity is active low. 5126 */ 5127 #define FTM_POL_POL7(x) (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL7_SHIFT)) & FTM_POL_POL7_MASK) 5128 /*! @} */ 5129 5130 /*! @name FMS - Fault Mode Status */ 5131 /*! @{ */ 5132 #define FTM_FMS_FAULTF0_MASK (0x1U) 5133 #define FTM_FMS_FAULTF0_SHIFT (0U) 5134 /*! FAULTF0 - Fault Detection Flag 0 5135 * 0b0..No fault condition was detected at the fault input. 5136 * 0b1..A fault condition was detected at the fault input. 5137 */ 5138 #define FTM_FMS_FAULTF0(x) (((uint32_t)(((uint32_t)(x)) << FTM_FMS_FAULTF0_SHIFT)) & FTM_FMS_FAULTF0_MASK) 5139 #define FTM_FMS_FAULTF1_MASK (0x2U) 5140 #define FTM_FMS_FAULTF1_SHIFT (1U) 5141 /*! FAULTF1 - Fault Detection Flag 1 5142 * 0b0..No fault condition was detected at the fault input. 5143 * 0b1..A fault condition was detected at the fault input. 5144 */ 5145 #define FTM_FMS_FAULTF1(x) (((uint32_t)(((uint32_t)(x)) << FTM_FMS_FAULTF1_SHIFT)) & FTM_FMS_FAULTF1_MASK) 5146 #define FTM_FMS_FAULTF2_MASK (0x4U) 5147 #define FTM_FMS_FAULTF2_SHIFT (2U) 5148 /*! FAULTF2 - Fault Detection Flag 2 5149 * 0b0..No fault condition was detected at the fault input. 5150 * 0b1..A fault condition was detected at the fault input. 5151 */ 5152 #define FTM_FMS_FAULTF2(x) (((uint32_t)(((uint32_t)(x)) << FTM_FMS_FAULTF2_SHIFT)) & FTM_FMS_FAULTF2_MASK) 5153 #define FTM_FMS_FAULTF3_MASK (0x8U) 5154 #define FTM_FMS_FAULTF3_SHIFT (3U) 5155 /*! FAULTF3 - Fault Detection Flag 3 5156 * 0b0..No fault condition was detected at the fault input. 5157 * 0b1..A fault condition was detected at the fault input. 5158 */ 5159 #define FTM_FMS_FAULTF3(x) (((uint32_t)(((uint32_t)(x)) << FTM_FMS_FAULTF3_SHIFT)) & FTM_FMS_FAULTF3_MASK) 5160 #define FTM_FMS_FAULTIN_MASK (0x20U) 5161 #define FTM_FMS_FAULTIN_SHIFT (5U) 5162 /*! FAULTIN - Fault Inputs 5163 * 0b0..The logic OR of the enabled fault inputs is 0. 5164 * 0b1..The logic OR of the enabled fault inputs is 1. 5165 */ 5166 #define FTM_FMS_FAULTIN(x) (((uint32_t)(((uint32_t)(x)) << FTM_FMS_FAULTIN_SHIFT)) & FTM_FMS_FAULTIN_MASK) 5167 #define FTM_FMS_WPEN_MASK (0x40U) 5168 #define FTM_FMS_WPEN_SHIFT (6U) 5169 /*! WPEN - Write Protection Enable 5170 * 0b0..Write protection is disabled. Write protected bits can be written. 5171 * 0b1..Write protection is enabled. Write protected bits cannot be written. 5172 */ 5173 #define FTM_FMS_WPEN(x) (((uint32_t)(((uint32_t)(x)) << FTM_FMS_WPEN_SHIFT)) & FTM_FMS_WPEN_MASK) 5174 #define FTM_FMS_FAULTF_MASK (0x80U) 5175 #define FTM_FMS_FAULTF_SHIFT (7U) 5176 /*! FAULTF - Fault Detection Flag 5177 * 0b0..No fault condition was detected. 5178 * 0b1..A fault condition was detected. 5179 */ 5180 #define FTM_FMS_FAULTF(x) (((uint32_t)(((uint32_t)(x)) << FTM_FMS_FAULTF_SHIFT)) & FTM_FMS_FAULTF_MASK) 5181 /*! @} */ 5182 5183 /*! @name FILTER - Input Capture Filter Control */ 5184 /*! @{ */ 5185 #define FTM_FILTER_CH0FVAL_MASK (0xFU) 5186 #define FTM_FILTER_CH0FVAL_SHIFT (0U) 5187 #define FTM_FILTER_CH0FVAL(x) (((uint32_t)(((uint32_t)(x)) << FTM_FILTER_CH0FVAL_SHIFT)) & FTM_FILTER_CH0FVAL_MASK) 5188 #define FTM_FILTER_CH1FVAL_MASK (0xF0U) 5189 #define FTM_FILTER_CH1FVAL_SHIFT (4U) 5190 #define FTM_FILTER_CH1FVAL(x) (((uint32_t)(((uint32_t)(x)) << FTM_FILTER_CH1FVAL_SHIFT)) & FTM_FILTER_CH1FVAL_MASK) 5191 #define FTM_FILTER_CH2FVAL_MASK (0xF00U) 5192 #define FTM_FILTER_CH2FVAL_SHIFT (8U) 5193 #define FTM_FILTER_CH2FVAL(x) (((uint32_t)(((uint32_t)(x)) << FTM_FILTER_CH2FVAL_SHIFT)) & FTM_FILTER_CH2FVAL_MASK) 5194 #define FTM_FILTER_CH3FVAL_MASK (0xF000U) 5195 #define FTM_FILTER_CH3FVAL_SHIFT (12U) 5196 #define FTM_FILTER_CH3FVAL(x) (((uint32_t)(((uint32_t)(x)) << FTM_FILTER_CH3FVAL_SHIFT)) & FTM_FILTER_CH3FVAL_MASK) 5197 /*! @} */ 5198 5199 /*! @name FLTCTRL - Fault Control */ 5200 /*! @{ */ 5201 #define FTM_FLTCTRL_FAULT0EN_MASK (0x1U) 5202 #define FTM_FLTCTRL_FAULT0EN_SHIFT (0U) 5203 /*! FAULT0EN - Fault Input 0 Enable 5204 * 0b0..Fault input is disabled. 5205 * 0b1..Fault input is enabled. 5206 */ 5207 #define FTM_FLTCTRL_FAULT0EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FAULT0EN_SHIFT)) & FTM_FLTCTRL_FAULT0EN_MASK) 5208 #define FTM_FLTCTRL_FAULT1EN_MASK (0x2U) 5209 #define FTM_FLTCTRL_FAULT1EN_SHIFT (1U) 5210 /*! FAULT1EN - Fault Input 1 Enable 5211 * 0b0..Fault input is disabled. 5212 * 0b1..Fault input is enabled. 5213 */ 5214 #define FTM_FLTCTRL_FAULT1EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FAULT1EN_SHIFT)) & FTM_FLTCTRL_FAULT1EN_MASK) 5215 #define FTM_FLTCTRL_FAULT2EN_MASK (0x4U) 5216 #define FTM_FLTCTRL_FAULT2EN_SHIFT (2U) 5217 /*! FAULT2EN - Fault Input 2 Enable 5218 * 0b0..Fault input is disabled. 5219 * 0b1..Fault input is enabled. 5220 */ 5221 #define FTM_FLTCTRL_FAULT2EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FAULT2EN_SHIFT)) & FTM_FLTCTRL_FAULT2EN_MASK) 5222 #define FTM_FLTCTRL_FAULT3EN_MASK (0x8U) 5223 #define FTM_FLTCTRL_FAULT3EN_SHIFT (3U) 5224 /*! FAULT3EN - Fault Input 3 Enable 5225 * 0b0..Fault input is disabled. 5226 * 0b1..Fault input is enabled. 5227 */ 5228 #define FTM_FLTCTRL_FAULT3EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FAULT3EN_SHIFT)) & FTM_FLTCTRL_FAULT3EN_MASK) 5229 #define FTM_FLTCTRL_FFLTR0EN_MASK (0x10U) 5230 #define FTM_FLTCTRL_FFLTR0EN_SHIFT (4U) 5231 /*! FFLTR0EN - Fault Input 0 Filter Enable 5232 * 0b0..Fault input filter is disabled. 5233 * 0b1..Fault input filter is enabled. 5234 */ 5235 #define FTM_FLTCTRL_FFLTR0EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FFLTR0EN_SHIFT)) & FTM_FLTCTRL_FFLTR0EN_MASK) 5236 #define FTM_FLTCTRL_FFLTR1EN_MASK (0x20U) 5237 #define FTM_FLTCTRL_FFLTR1EN_SHIFT (5U) 5238 /*! FFLTR1EN - Fault Input 1 Filter Enable 5239 * 0b0..Fault input filter is disabled. 5240 * 0b1..Fault input filter is enabled. 5241 */ 5242 #define FTM_FLTCTRL_FFLTR1EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FFLTR1EN_SHIFT)) & FTM_FLTCTRL_FFLTR1EN_MASK) 5243 #define FTM_FLTCTRL_FFLTR2EN_MASK (0x40U) 5244 #define FTM_FLTCTRL_FFLTR2EN_SHIFT (6U) 5245 /*! FFLTR2EN - Fault Input 2 Filter Enable 5246 * 0b0..Fault input filter is disabled. 5247 * 0b1..Fault input filter is enabled. 5248 */ 5249 #define FTM_FLTCTRL_FFLTR2EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FFLTR2EN_SHIFT)) & FTM_FLTCTRL_FFLTR2EN_MASK) 5250 #define FTM_FLTCTRL_FFLTR3EN_MASK (0x80U) 5251 #define FTM_FLTCTRL_FFLTR3EN_SHIFT (7U) 5252 /*! FFLTR3EN - Fault Input 3 Filter Enable 5253 * 0b0..Fault input filter is disabled. 5254 * 0b1..Fault input filter is enabled. 5255 */ 5256 #define FTM_FLTCTRL_FFLTR3EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FFLTR3EN_SHIFT)) & FTM_FLTCTRL_FFLTR3EN_MASK) 5257 #define FTM_FLTCTRL_FFVAL_MASK (0xF00U) 5258 #define FTM_FLTCTRL_FFVAL_SHIFT (8U) 5259 #define FTM_FLTCTRL_FFVAL(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FFVAL_SHIFT)) & FTM_FLTCTRL_FFVAL_MASK) 5260 /*! @} */ 5261 5262 /*! @name QDCTRL - Quadrature Decoder Control And Status */ 5263 /*! @{ */ 5264 #define FTM_QDCTRL_QUADEN_MASK (0x1U) 5265 #define FTM_QDCTRL_QUADEN_SHIFT (0U) 5266 /*! QUADEN - Quadrature Decoder Mode Enable 5267 * 0b0..Quadrature Decoder mode is disabled. 5268 * 0b1..Quadrature Decoder mode is enabled. 5269 */ 5270 #define FTM_QDCTRL_QUADEN(x) (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_QUADEN_SHIFT)) & FTM_QDCTRL_QUADEN_MASK) 5271 #define FTM_QDCTRL_TOFDIR_MASK (0x2U) 5272 #define FTM_QDCTRL_TOFDIR_SHIFT (1U) 5273 /*! TOFDIR - Timer Overflow Direction In Quadrature Decoder Mode 5274 * 0b0..TOF bit was set on the bottom of counting. There was an FTM counter decrement and FTM counter changes from its minimum value (CNTIN register) to its maximum value (MOD register). 5275 * 0b1..TOF bit was set on the top of counting. There was an FTM counter increment and FTM counter changes from its maximum value (MOD register) to its minimum value (CNTIN register). 5276 */ 5277 #define FTM_QDCTRL_TOFDIR(x) (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_TOFDIR_SHIFT)) & FTM_QDCTRL_TOFDIR_MASK) 5278 #define FTM_QDCTRL_QUADIR_MASK (0x4U) 5279 #define FTM_QDCTRL_QUADIR_SHIFT (2U) 5280 /*! QUADIR - FTM Counter Direction In Quadrature Decoder Mode 5281 * 0b0..Counting direction is decreasing (FTM counter decrement). 5282 * 0b1..Counting direction is increasing (FTM counter increment). 5283 */ 5284 #define FTM_QDCTRL_QUADIR(x) (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_QUADIR_SHIFT)) & FTM_QDCTRL_QUADIR_MASK) 5285 #define FTM_QDCTRL_QUADMODE_MASK (0x8U) 5286 #define FTM_QDCTRL_QUADMODE_SHIFT (3U) 5287 /*! QUADMODE - Quadrature Decoder Mode 5288 * 0b0..Phase A and phase B encoding mode. 5289 * 0b1..Count and direction encoding mode. 5290 */ 5291 #define FTM_QDCTRL_QUADMODE(x) (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_QUADMODE_SHIFT)) & FTM_QDCTRL_QUADMODE_MASK) 5292 #define FTM_QDCTRL_PHBPOL_MASK (0x10U) 5293 #define FTM_QDCTRL_PHBPOL_SHIFT (4U) 5294 /*! PHBPOL - Phase B Input Polarity 5295 * 0b0..Normal polarity. Phase B input signal is not inverted before identifying the rising and falling edges of this signal. 5296 * 0b1..Inverted polarity. Phase B input signal is inverted before identifying the rising and falling edges of this signal. 5297 */ 5298 #define FTM_QDCTRL_PHBPOL(x) (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_PHBPOL_SHIFT)) & FTM_QDCTRL_PHBPOL_MASK) 5299 #define FTM_QDCTRL_PHAPOL_MASK (0x20U) 5300 #define FTM_QDCTRL_PHAPOL_SHIFT (5U) 5301 /*! PHAPOL - Phase A Input Polarity 5302 * 0b0..Normal polarity. Phase A input signal is not inverted before identifying the rising and falling edges of this signal. 5303 * 0b1..Inverted polarity. Phase A input signal is inverted before identifying the rising and falling edges of this signal. 5304 */ 5305 #define FTM_QDCTRL_PHAPOL(x) (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_PHAPOL_SHIFT)) & FTM_QDCTRL_PHAPOL_MASK) 5306 #define FTM_QDCTRL_PHBFLTREN_MASK (0x40U) 5307 #define FTM_QDCTRL_PHBFLTREN_SHIFT (6U) 5308 /*! PHBFLTREN - Phase B Input Filter Enable 5309 * 0b0..Phase B input filter is disabled. 5310 * 0b1..Phase B input filter is enabled. 5311 */ 5312 #define FTM_QDCTRL_PHBFLTREN(x) (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_PHBFLTREN_SHIFT)) & FTM_QDCTRL_PHBFLTREN_MASK) 5313 #define FTM_QDCTRL_PHAFLTREN_MASK (0x80U) 5314 #define FTM_QDCTRL_PHAFLTREN_SHIFT (7U) 5315 /*! PHAFLTREN - Phase A Input Filter Enable 5316 * 0b0..Phase A input filter is disabled. 5317 * 0b1..Phase A input filter is enabled. 5318 */ 5319 #define FTM_QDCTRL_PHAFLTREN(x) (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_PHAFLTREN_SHIFT)) & FTM_QDCTRL_PHAFLTREN_MASK) 5320 /*! @} */ 5321 5322 /*! @name CONF - Configuration */ 5323 /*! @{ */ 5324 #define FTM_CONF_NUMTOF_MASK (0x1FU) 5325 #define FTM_CONF_NUMTOF_SHIFT (0U) 5326 #define FTM_CONF_NUMTOF(x) (((uint32_t)(((uint32_t)(x)) << FTM_CONF_NUMTOF_SHIFT)) & FTM_CONF_NUMTOF_MASK) 5327 #define FTM_CONF_BDMMODE_MASK (0xC0U) 5328 #define FTM_CONF_BDMMODE_SHIFT (6U) 5329 #define FTM_CONF_BDMMODE(x) (((uint32_t)(((uint32_t)(x)) << FTM_CONF_BDMMODE_SHIFT)) & FTM_CONF_BDMMODE_MASK) 5330 #define FTM_CONF_GTBEEN_MASK (0x200U) 5331 #define FTM_CONF_GTBEEN_SHIFT (9U) 5332 /*! GTBEEN - Global Time Base Enable 5333 * 0b0..Use of an external global time base is disabled. 5334 * 0b1..Use of an external global time base is enabled. 5335 */ 5336 #define FTM_CONF_GTBEEN(x) (((uint32_t)(((uint32_t)(x)) << FTM_CONF_GTBEEN_SHIFT)) & FTM_CONF_GTBEEN_MASK) 5337 #define FTM_CONF_GTBEOUT_MASK (0x400U) 5338 #define FTM_CONF_GTBEOUT_SHIFT (10U) 5339 /*! GTBEOUT - Global Time Base Output 5340 * 0b0..A global time base signal generation is disabled. 5341 * 0b1..A global time base signal generation is enabled. 5342 */ 5343 #define FTM_CONF_GTBEOUT(x) (((uint32_t)(((uint32_t)(x)) << FTM_CONF_GTBEOUT_SHIFT)) & FTM_CONF_GTBEOUT_MASK) 5344 /*! @} */ 5345 5346 /*! @name FLTPOL - FTM Fault Input Polarity */ 5347 /*! @{ */ 5348 #define FTM_FLTPOL_FLT0POL_MASK (0x1U) 5349 #define FTM_FLTPOL_FLT0POL_SHIFT (0U) 5350 /*! FLT0POL - Fault Input 0 Polarity 5351 * 0b0..The fault input polarity is active high. A 1 at the fault input indicates a fault. 5352 * 0b1..The fault input polarity is active low. A 0 at the fault input indicates a fault. 5353 */ 5354 #define FTM_FLTPOL_FLT0POL(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTPOL_FLT0POL_SHIFT)) & FTM_FLTPOL_FLT0POL_MASK) 5355 #define FTM_FLTPOL_FLT1POL_MASK (0x2U) 5356 #define FTM_FLTPOL_FLT1POL_SHIFT (1U) 5357 /*! FLT1POL - Fault Input 1 Polarity 5358 * 0b0..The fault input polarity is active high. A 1 at the fault input indicates a fault. 5359 * 0b1..The fault input polarity is active low. A 0 at the fault input indicates a fault. 5360 */ 5361 #define FTM_FLTPOL_FLT1POL(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTPOL_FLT1POL_SHIFT)) & FTM_FLTPOL_FLT1POL_MASK) 5362 #define FTM_FLTPOL_FLT2POL_MASK (0x4U) 5363 #define FTM_FLTPOL_FLT2POL_SHIFT (2U) 5364 /*! FLT2POL - Fault Input 2 Polarity 5365 * 0b0..The fault input polarity is active high. A 1 at the fault input indicates a fault. 5366 * 0b1..The fault input polarity is active low. A 0 at the fault input indicates a fault. 5367 */ 5368 #define FTM_FLTPOL_FLT2POL(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTPOL_FLT2POL_SHIFT)) & FTM_FLTPOL_FLT2POL_MASK) 5369 #define FTM_FLTPOL_FLT3POL_MASK (0x8U) 5370 #define FTM_FLTPOL_FLT3POL_SHIFT (3U) 5371 /*! FLT3POL - Fault Input 3 Polarity 5372 * 0b0..The fault input polarity is active high. A 1 at the fault input indicates a fault. 5373 * 0b1..The fault input polarity is active low. A 0 at the fault input indicates a fault. 5374 */ 5375 #define FTM_FLTPOL_FLT3POL(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTPOL_FLT3POL_SHIFT)) & FTM_FLTPOL_FLT3POL_MASK) 5376 /*! @} */ 5377 5378 /*! @name SYNCONF - Synchronization Configuration */ 5379 /*! @{ */ 5380 #define FTM_SYNCONF_HWTRIGMODE_MASK (0x1U) 5381 #define FTM_SYNCONF_HWTRIGMODE_SHIFT (0U) 5382 /*! HWTRIGMODE - Hardware Trigger Mode 5383 * 0b0..FTM clears the TRIGj bit when the hardware trigger j is detected, where j = 0, 1,2. 5384 * 0b1..FTM does not clear the TRIGj bit when the hardware trigger j is detected, where j = 0, 1,2. 5385 */ 5386 #define FTM_SYNCONF_HWTRIGMODE(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_HWTRIGMODE_SHIFT)) & FTM_SYNCONF_HWTRIGMODE_MASK) 5387 #define FTM_SYNCONF_CNTINC_MASK (0x4U) 5388 #define FTM_SYNCONF_CNTINC_SHIFT (2U) 5389 /*! CNTINC - CNTIN Register Synchronization 5390 * 0b0..CNTIN register is updated with its buffer value at all rising edges of system clock. 5391 * 0b1..CNTIN register is updated with its buffer value by the PWM synchronization. 5392 */ 5393 #define FTM_SYNCONF_CNTINC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_CNTINC_SHIFT)) & FTM_SYNCONF_CNTINC_MASK) 5394 #define FTM_SYNCONF_INVC_MASK (0x10U) 5395 #define FTM_SYNCONF_INVC_SHIFT (4U) 5396 /*! INVC - INVCTRL Register Synchronization 5397 * 0b0..INVCTRL register is updated with its buffer value at all rising edges of system clock. 5398 * 0b1..INVCTRL register is updated with its buffer value by the PWM synchronization. 5399 */ 5400 #define FTM_SYNCONF_INVC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_INVC_SHIFT)) & FTM_SYNCONF_INVC_MASK) 5401 #define FTM_SYNCONF_SWOC_MASK (0x20U) 5402 #define FTM_SYNCONF_SWOC_SHIFT (5U) 5403 /*! SWOC - SWOCTRL Register Synchronization 5404 * 0b0..SWOCTRL register is updated with its buffer value at all rising edges of system clock. 5405 * 0b1..SWOCTRL register is updated with its buffer value by the PWM synchronization. 5406 */ 5407 #define FTM_SYNCONF_SWOC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_SWOC_SHIFT)) & FTM_SYNCONF_SWOC_MASK) 5408 #define FTM_SYNCONF_SYNCMODE_MASK (0x80U) 5409 #define FTM_SYNCONF_SYNCMODE_SHIFT (7U) 5410 /*! SYNCMODE - Synchronization Mode 5411 * 0b0..Legacy PWM synchronization is selected. 5412 * 0b1..Enhanced PWM synchronization is selected. 5413 */ 5414 #define FTM_SYNCONF_SYNCMODE(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_SYNCMODE_SHIFT)) & FTM_SYNCONF_SYNCMODE_MASK) 5415 #define FTM_SYNCONF_SWRSTCNT_MASK (0x100U) 5416 #define FTM_SYNCONF_SWRSTCNT_SHIFT (8U) 5417 /*! SWRSTCNT 5418 * 0b0..The software trigger does not activate the FTM counter synchronization. 5419 * 0b1..The software trigger activates the FTM counter synchronization. 5420 */ 5421 #define FTM_SYNCONF_SWRSTCNT(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_SWRSTCNT_SHIFT)) & FTM_SYNCONF_SWRSTCNT_MASK) 5422 #define FTM_SYNCONF_SWWRBUF_MASK (0x200U) 5423 #define FTM_SYNCONF_SWWRBUF_SHIFT (9U) 5424 /*! SWWRBUF 5425 * 0b0..The software trigger does not activate MOD, CNTIN, and CV registers synchronization. 5426 * 0b1..The software trigger activates MOD, CNTIN, and CV registers synchronization. 5427 */ 5428 #define FTM_SYNCONF_SWWRBUF(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_SWWRBUF_SHIFT)) & FTM_SYNCONF_SWWRBUF_MASK) 5429 #define FTM_SYNCONF_SWOM_MASK (0x400U) 5430 #define FTM_SYNCONF_SWOM_SHIFT (10U) 5431 /*! SWOM 5432 * 0b0..The software trigger does not activate the OUTMASK register synchronization. 5433 * 0b1..The software trigger activates the OUTMASK register synchronization. 5434 */ 5435 #define FTM_SYNCONF_SWOM(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_SWOM_SHIFT)) & FTM_SYNCONF_SWOM_MASK) 5436 #define FTM_SYNCONF_SWINVC_MASK (0x800U) 5437 #define FTM_SYNCONF_SWINVC_SHIFT (11U) 5438 /*! SWINVC 5439 * 0b0..The software trigger does not activate the INVCTRL register synchronization. 5440 * 0b1..The software trigger activates the INVCTRL register synchronization. 5441 */ 5442 #define FTM_SYNCONF_SWINVC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_SWINVC_SHIFT)) & FTM_SYNCONF_SWINVC_MASK) 5443 #define FTM_SYNCONF_SWSOC_MASK (0x1000U) 5444 #define FTM_SYNCONF_SWSOC_SHIFT (12U) 5445 /*! SWSOC 5446 * 0b0..The software trigger does not activate the SWOCTRL register synchronization. 5447 * 0b1..The software trigger activates the SWOCTRL register synchronization. 5448 */ 5449 #define FTM_SYNCONF_SWSOC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_SWSOC_SHIFT)) & FTM_SYNCONF_SWSOC_MASK) 5450 #define FTM_SYNCONF_HWRSTCNT_MASK (0x10000U) 5451 #define FTM_SYNCONF_HWRSTCNT_SHIFT (16U) 5452 /*! HWRSTCNT 5453 * 0b0..A hardware trigger does not activate the FTM counter synchronization. 5454 * 0b1..A hardware trigger activates the FTM counter synchronization. 5455 */ 5456 #define FTM_SYNCONF_HWRSTCNT(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_HWRSTCNT_SHIFT)) & FTM_SYNCONF_HWRSTCNT_MASK) 5457 #define FTM_SYNCONF_HWWRBUF_MASK (0x20000U) 5458 #define FTM_SYNCONF_HWWRBUF_SHIFT (17U) 5459 /*! HWWRBUF 5460 * 0b0..A hardware trigger does not activate MOD, CNTIN, and CV registers synchronization. 5461 * 0b1..A hardware trigger activates MOD, CNTIN, and CV registers synchronization. 5462 */ 5463 #define FTM_SYNCONF_HWWRBUF(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_HWWRBUF_SHIFT)) & FTM_SYNCONF_HWWRBUF_MASK) 5464 #define FTM_SYNCONF_HWOM_MASK (0x40000U) 5465 #define FTM_SYNCONF_HWOM_SHIFT (18U) 5466 /*! HWOM 5467 * 0b0..A hardware trigger does not activate the OUTMASK register synchronization. 5468 * 0b1..A hardware trigger activates the OUTMASK register synchronization. 5469 */ 5470 #define FTM_SYNCONF_HWOM(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_HWOM_SHIFT)) & FTM_SYNCONF_HWOM_MASK) 5471 #define FTM_SYNCONF_HWINVC_MASK (0x80000U) 5472 #define FTM_SYNCONF_HWINVC_SHIFT (19U) 5473 /*! HWINVC 5474 * 0b0..A hardware trigger does not activate the INVCTRL register synchronization. 5475 * 0b1..A hardware trigger activates the INVCTRL register synchronization. 5476 */ 5477 #define FTM_SYNCONF_HWINVC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_HWINVC_SHIFT)) & FTM_SYNCONF_HWINVC_MASK) 5478 #define FTM_SYNCONF_HWSOC_MASK (0x100000U) 5479 #define FTM_SYNCONF_HWSOC_SHIFT (20U) 5480 /*! HWSOC 5481 * 0b0..A hardware trigger does not activate the SWOCTRL register synchronization. 5482 * 0b1..A hardware trigger activates the SWOCTRL register synchronization. 5483 */ 5484 #define FTM_SYNCONF_HWSOC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_HWSOC_SHIFT)) & FTM_SYNCONF_HWSOC_MASK) 5485 /*! @} */ 5486 5487 /*! @name INVCTRL - FTM Inverting Control */ 5488 /*! @{ */ 5489 #define FTM_INVCTRL_INV0EN_MASK (0x1U) 5490 #define FTM_INVCTRL_INV0EN_SHIFT (0U) 5491 /*! INV0EN - Pair Channels 0 Inverting Enable 5492 * 0b0..Inverting is disabled. 5493 * 0b1..Inverting is enabled. 5494 */ 5495 #define FTM_INVCTRL_INV0EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_INVCTRL_INV0EN_SHIFT)) & FTM_INVCTRL_INV0EN_MASK) 5496 #define FTM_INVCTRL_INV1EN_MASK (0x2U) 5497 #define FTM_INVCTRL_INV1EN_SHIFT (1U) 5498 /*! INV1EN - Pair Channels 1 Inverting Enable 5499 * 0b0..Inverting is disabled. 5500 * 0b1..Inverting is enabled. 5501 */ 5502 #define FTM_INVCTRL_INV1EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_INVCTRL_INV1EN_SHIFT)) & FTM_INVCTRL_INV1EN_MASK) 5503 #define FTM_INVCTRL_INV2EN_MASK (0x4U) 5504 #define FTM_INVCTRL_INV2EN_SHIFT (2U) 5505 /*! INV2EN - Pair Channels 2 Inverting Enable 5506 * 0b0..Inverting is disabled. 5507 * 0b1..Inverting is enabled. 5508 */ 5509 #define FTM_INVCTRL_INV2EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_INVCTRL_INV2EN_SHIFT)) & FTM_INVCTRL_INV2EN_MASK) 5510 #define FTM_INVCTRL_INV3EN_MASK (0x8U) 5511 #define FTM_INVCTRL_INV3EN_SHIFT (3U) 5512 /*! INV3EN - Pair Channels 3 Inverting Enable 5513 * 0b0..Inverting is disabled. 5514 * 0b1..Inverting is enabled. 5515 */ 5516 #define FTM_INVCTRL_INV3EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_INVCTRL_INV3EN_SHIFT)) & FTM_INVCTRL_INV3EN_MASK) 5517 /*! @} */ 5518 5519 /*! @name SWOCTRL - FTM Software Output Control */ 5520 /*! @{ */ 5521 #define FTM_SWOCTRL_CH0OC_MASK (0x1U) 5522 #define FTM_SWOCTRL_CH0OC_SHIFT (0U) 5523 /*! CH0OC - Channel 0 Software Output Control Enable 5524 * 0b0..The channel output is not affected by software output control. 5525 * 0b1..The channel output is affected by software output control. 5526 */ 5527 #define FTM_SWOCTRL_CH0OC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH0OC_SHIFT)) & FTM_SWOCTRL_CH0OC_MASK) 5528 #define FTM_SWOCTRL_CH1OC_MASK (0x2U) 5529 #define FTM_SWOCTRL_CH1OC_SHIFT (1U) 5530 /*! CH1OC - Channel 1 Software Output Control Enable 5531 * 0b0..The channel output is not affected by software output control. 5532 * 0b1..The channel output is affected by software output control. 5533 */ 5534 #define FTM_SWOCTRL_CH1OC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH1OC_SHIFT)) & FTM_SWOCTRL_CH1OC_MASK) 5535 #define FTM_SWOCTRL_CH2OC_MASK (0x4U) 5536 #define FTM_SWOCTRL_CH2OC_SHIFT (2U) 5537 /*! CH2OC - Channel 2 Software Output Control Enable 5538 * 0b0..The channel output is not affected by software output control. 5539 * 0b1..The channel output is affected by software output control. 5540 */ 5541 #define FTM_SWOCTRL_CH2OC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH2OC_SHIFT)) & FTM_SWOCTRL_CH2OC_MASK) 5542 #define FTM_SWOCTRL_CH3OC_MASK (0x8U) 5543 #define FTM_SWOCTRL_CH3OC_SHIFT (3U) 5544 /*! CH3OC - Channel 3 Software Output Control Enable 5545 * 0b0..The channel output is not affected by software output control. 5546 * 0b1..The channel output is affected by software output control. 5547 */ 5548 #define FTM_SWOCTRL_CH3OC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH3OC_SHIFT)) & FTM_SWOCTRL_CH3OC_MASK) 5549 #define FTM_SWOCTRL_CH4OC_MASK (0x10U) 5550 #define FTM_SWOCTRL_CH4OC_SHIFT (4U) 5551 /*! CH4OC - Channel 4 Software Output Control Enable 5552 * 0b0..The channel output is not affected by software output control. 5553 * 0b1..The channel output is affected by software output control. 5554 */ 5555 #define FTM_SWOCTRL_CH4OC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH4OC_SHIFT)) & FTM_SWOCTRL_CH4OC_MASK) 5556 #define FTM_SWOCTRL_CH5OC_MASK (0x20U) 5557 #define FTM_SWOCTRL_CH5OC_SHIFT (5U) 5558 /*! CH5OC - Channel 5 Software Output Control Enable 5559 * 0b0..The channel output is not affected by software output control. 5560 * 0b1..The channel output is affected by software output control. 5561 */ 5562 #define FTM_SWOCTRL_CH5OC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH5OC_SHIFT)) & FTM_SWOCTRL_CH5OC_MASK) 5563 #define FTM_SWOCTRL_CH6OC_MASK (0x40U) 5564 #define FTM_SWOCTRL_CH6OC_SHIFT (6U) 5565 /*! CH6OC - Channel 6 Software Output Control Enable 5566 * 0b0..The channel output is not affected by software output control. 5567 * 0b1..The channel output is affected by software output control. 5568 */ 5569 #define FTM_SWOCTRL_CH6OC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH6OC_SHIFT)) & FTM_SWOCTRL_CH6OC_MASK) 5570 #define FTM_SWOCTRL_CH7OC_MASK (0x80U) 5571 #define FTM_SWOCTRL_CH7OC_SHIFT (7U) 5572 /*! CH7OC - Channel 7 Software Output Control Enable 5573 * 0b0..The channel output is not affected by software output control. 5574 * 0b1..The channel output is affected by software output control. 5575 */ 5576 #define FTM_SWOCTRL_CH7OC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH7OC_SHIFT)) & FTM_SWOCTRL_CH7OC_MASK) 5577 #define FTM_SWOCTRL_CH0OCV_MASK (0x100U) 5578 #define FTM_SWOCTRL_CH0OCV_SHIFT (8U) 5579 /*! CH0OCV - Channel 0 Software Output Control Value 5580 * 0b0..The software output control forces 0 to the channel output. 5581 * 0b1..The software output control forces 1 to the channel output. 5582 */ 5583 #define FTM_SWOCTRL_CH0OCV(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH0OCV_SHIFT)) & FTM_SWOCTRL_CH0OCV_MASK) 5584 #define FTM_SWOCTRL_CH1OCV_MASK (0x200U) 5585 #define FTM_SWOCTRL_CH1OCV_SHIFT (9U) 5586 /*! CH1OCV - Channel 1 Software Output Control Value 5587 * 0b0..The software output control forces 0 to the channel output. 5588 * 0b1..The software output control forces 1 to the channel output. 5589 */ 5590 #define FTM_SWOCTRL_CH1OCV(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH1OCV_SHIFT)) & FTM_SWOCTRL_CH1OCV_MASK) 5591 #define FTM_SWOCTRL_CH2OCV_MASK (0x400U) 5592 #define FTM_SWOCTRL_CH2OCV_SHIFT (10U) 5593 /*! CH2OCV - Channel 2 Software Output Control Value 5594 * 0b0..The software output control forces 0 to the channel output. 5595 * 0b1..The software output control forces 1 to the channel output. 5596 */ 5597 #define FTM_SWOCTRL_CH2OCV(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH2OCV_SHIFT)) & FTM_SWOCTRL_CH2OCV_MASK) 5598 #define FTM_SWOCTRL_CH3OCV_MASK (0x800U) 5599 #define FTM_SWOCTRL_CH3OCV_SHIFT (11U) 5600 /*! CH3OCV - Channel 3 Software Output Control Value 5601 * 0b0..The software output control forces 0 to the channel output. 5602 * 0b1..The software output control forces 1 to the channel output. 5603 */ 5604 #define FTM_SWOCTRL_CH3OCV(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH3OCV_SHIFT)) & FTM_SWOCTRL_CH3OCV_MASK) 5605 #define FTM_SWOCTRL_CH4OCV_MASK (0x1000U) 5606 #define FTM_SWOCTRL_CH4OCV_SHIFT (12U) 5607 /*! CH4OCV - Channel 4 Software Output Control Value 5608 * 0b0..The software output control forces 0 to the channel output. 5609 * 0b1..The software output control forces 1 to the channel output. 5610 */ 5611 #define FTM_SWOCTRL_CH4OCV(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH4OCV_SHIFT)) & FTM_SWOCTRL_CH4OCV_MASK) 5612 #define FTM_SWOCTRL_CH5OCV_MASK (0x2000U) 5613 #define FTM_SWOCTRL_CH5OCV_SHIFT (13U) 5614 /*! CH5OCV - Channel 5 Software Output Control Value 5615 * 0b0..The software output control forces 0 to the channel output. 5616 * 0b1..The software output control forces 1 to the channel output. 5617 */ 5618 #define FTM_SWOCTRL_CH5OCV(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH5OCV_SHIFT)) & FTM_SWOCTRL_CH5OCV_MASK) 5619 #define FTM_SWOCTRL_CH6OCV_MASK (0x4000U) 5620 #define FTM_SWOCTRL_CH6OCV_SHIFT (14U) 5621 /*! CH6OCV - Channel 6 Software Output Control Value 5622 * 0b0..The software output control forces 0 to the channel output. 5623 * 0b1..The software output control forces 1 to the channel output. 5624 */ 5625 #define FTM_SWOCTRL_CH6OCV(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH6OCV_SHIFT)) & FTM_SWOCTRL_CH6OCV_MASK) 5626 #define FTM_SWOCTRL_CH7OCV_MASK (0x8000U) 5627 #define FTM_SWOCTRL_CH7OCV_SHIFT (15U) 5628 /*! CH7OCV - Channel 7 Software Output Control Value 5629 * 0b0..The software output control forces 0 to the channel output. 5630 * 0b1..The software output control forces 1 to the channel output. 5631 */ 5632 #define FTM_SWOCTRL_CH7OCV(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH7OCV_SHIFT)) & FTM_SWOCTRL_CH7OCV_MASK) 5633 /*! @} */ 5634 5635 /*! @name PWMLOAD - FTM PWM Load */ 5636 /*! @{ */ 5637 #define FTM_PWMLOAD_CH0SEL_MASK (0x1U) 5638 #define FTM_PWMLOAD_CH0SEL_SHIFT (0U) 5639 /*! CH0SEL - Channel 0 Select 5640 * 0b0..Do not include the channel in the matching process. 5641 * 0b1..Include the channel in the matching process. 5642 */ 5643 #define FTM_PWMLOAD_CH0SEL(x) (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH0SEL_SHIFT)) & FTM_PWMLOAD_CH0SEL_MASK) 5644 #define FTM_PWMLOAD_CH1SEL_MASK (0x2U) 5645 #define FTM_PWMLOAD_CH1SEL_SHIFT (1U) 5646 /*! CH1SEL - Channel 1 Select 5647 * 0b0..Do not include the channel in the matching process. 5648 * 0b1..Include the channel in the matching process. 5649 */ 5650 #define FTM_PWMLOAD_CH1SEL(x) (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH1SEL_SHIFT)) & FTM_PWMLOAD_CH1SEL_MASK) 5651 #define FTM_PWMLOAD_CH2SEL_MASK (0x4U) 5652 #define FTM_PWMLOAD_CH2SEL_SHIFT (2U) 5653 /*! CH2SEL - Channel 2 Select 5654 * 0b0..Do not include the channel in the matching process. 5655 * 0b1..Include the channel in the matching process. 5656 */ 5657 #define FTM_PWMLOAD_CH2SEL(x) (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH2SEL_SHIFT)) & FTM_PWMLOAD_CH2SEL_MASK) 5658 #define FTM_PWMLOAD_CH3SEL_MASK (0x8U) 5659 #define FTM_PWMLOAD_CH3SEL_SHIFT (3U) 5660 /*! CH3SEL - Channel 3 Select 5661 * 0b0..Do not include the channel in the matching process. 5662 * 0b1..Include the channel in the matching process. 5663 */ 5664 #define FTM_PWMLOAD_CH3SEL(x) (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH3SEL_SHIFT)) & FTM_PWMLOAD_CH3SEL_MASK) 5665 #define FTM_PWMLOAD_CH4SEL_MASK (0x10U) 5666 #define FTM_PWMLOAD_CH4SEL_SHIFT (4U) 5667 /*! CH4SEL - Channel 4 Select 5668 * 0b0..Do not include the channel in the matching process. 5669 * 0b1..Include the channel in the matching process. 5670 */ 5671 #define FTM_PWMLOAD_CH4SEL(x) (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH4SEL_SHIFT)) & FTM_PWMLOAD_CH4SEL_MASK) 5672 #define FTM_PWMLOAD_CH5SEL_MASK (0x20U) 5673 #define FTM_PWMLOAD_CH5SEL_SHIFT (5U) 5674 /*! CH5SEL - Channel 5 Select 5675 * 0b0..Do not include the channel in the matching process. 5676 * 0b1..Include the channel in the matching process. 5677 */ 5678 #define FTM_PWMLOAD_CH5SEL(x) (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH5SEL_SHIFT)) & FTM_PWMLOAD_CH5SEL_MASK) 5679 #define FTM_PWMLOAD_CH6SEL_MASK (0x40U) 5680 #define FTM_PWMLOAD_CH6SEL_SHIFT (6U) 5681 /*! CH6SEL - Channel 6 Select 5682 * 0b0..Do not include the channel in the matching process. 5683 * 0b1..Include the channel in the matching process. 5684 */ 5685 #define FTM_PWMLOAD_CH6SEL(x) (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH6SEL_SHIFT)) & FTM_PWMLOAD_CH6SEL_MASK) 5686 #define FTM_PWMLOAD_CH7SEL_MASK (0x80U) 5687 #define FTM_PWMLOAD_CH7SEL_SHIFT (7U) 5688 /*! CH7SEL - Channel 7 Select 5689 * 0b0..Do not include the channel in the matching process. 5690 * 0b1..Include the channel in the matching process. 5691 */ 5692 #define FTM_PWMLOAD_CH7SEL(x) (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH7SEL_SHIFT)) & FTM_PWMLOAD_CH7SEL_MASK) 5693 #define FTM_PWMLOAD_LDOK_MASK (0x200U) 5694 #define FTM_PWMLOAD_LDOK_SHIFT (9U) 5695 /*! LDOK - Load Enable 5696 * 0b0..Loading updated values is disabled. 5697 * 0b1..Loading updated values is enabled. 5698 */ 5699 #define FTM_PWMLOAD_LDOK(x) (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_LDOK_SHIFT)) & FTM_PWMLOAD_LDOK_MASK) 5700 /*! @} */ 5701 5702 5703 /*! 5704 * @} 5705 */ /* end of group FTM_Register_Masks */ 5706 5707 5708 /* FTM - Peripheral instance base addresses */ 5709 /** Peripheral FTM0 base address */ 5710 #define FTM0_BASE (0x40038000u) 5711 /** Peripheral FTM0 base pointer */ 5712 #define FTM0 ((FTM_Type *)FTM0_BASE) 5713 /** Peripheral FTM1 base address */ 5714 #define FTM1_BASE (0x40039000u) 5715 /** Peripheral FTM1 base pointer */ 5716 #define FTM1 ((FTM_Type *)FTM1_BASE) 5717 /** Peripheral FTM2 base address */ 5718 #define FTM2_BASE (0x4003A000u) 5719 /** Peripheral FTM2 base pointer */ 5720 #define FTM2 ((FTM_Type *)FTM2_BASE) 5721 /** Peripheral FTM3 base address */ 5722 #define FTM3_BASE (0x40026000u) 5723 /** Peripheral FTM3 base pointer */ 5724 #define FTM3 ((FTM_Type *)FTM3_BASE) 5725 /** Peripheral FTM4 base address */ 5726 #define FTM4_BASE (0x40027000u) 5727 /** Peripheral FTM4 base pointer */ 5728 #define FTM4 ((FTM_Type *)FTM4_BASE) 5729 /** Peripheral FTM5 base address */ 5730 #define FTM5_BASE (0x40028000u) 5731 /** Peripheral FTM5 base pointer */ 5732 #define FTM5 ((FTM_Type *)FTM5_BASE) 5733 /** Array initializer of FTM peripheral base addresses */ 5734 #define FTM_BASE_ADDRS { FTM0_BASE, FTM1_BASE, FTM2_BASE, FTM3_BASE, FTM4_BASE, FTM5_BASE } 5735 /** Array initializer of FTM peripheral base pointers */ 5736 #define FTM_BASE_PTRS { FTM0, FTM1, FTM2, FTM3, FTM4, FTM5 } 5737 /** Interrupt vectors for the FTM peripheral type */ 5738 #define FTM_IRQS { FTM0_IRQn, FTM1_IRQn, FTM2_IRQn, FTM3_IRQn, FTM4_IRQn, FTM5_IRQn } 5739 5740 /*! 5741 * @} 5742 */ /* end of group FTM_Peripheral_Access_Layer */ 5743 5744 5745 /* ---------------------------------------------------------------------------- 5746 -- GPIO Peripheral Access Layer 5747 ---------------------------------------------------------------------------- */ 5748 5749 /*! 5750 * @addtogroup GPIO_Peripheral_Access_Layer GPIO Peripheral Access Layer 5751 * @{ 5752 */ 5753 5754 /** GPIO - Register Layout Typedef */ 5755 typedef struct { 5756 __IO uint32_t PDOR; /**< Port Data Output Register, offset: 0x0 */ 5757 __O uint32_t PSOR; /**< Port Set Output Register, offset: 0x4 */ 5758 __O uint32_t PCOR; /**< Port Clear Output Register, offset: 0x8 */ 5759 __O uint32_t PTOR; /**< Port Toggle Output Register, offset: 0xC */ 5760 __I uint32_t PDIR; /**< Port Data Input Register, offset: 0x10 */ 5761 __IO uint32_t PDDR; /**< Port Data Direction Register, offset: 0x14 */ 5762 } GPIO_Type; 5763 5764 /* ---------------------------------------------------------------------------- 5765 -- GPIO Register Masks 5766 ---------------------------------------------------------------------------- */ 5767 5768 /*! 5769 * @addtogroup GPIO_Register_Masks GPIO Register Masks 5770 * @{ 5771 */ 5772 5773 /*! @name PDOR - Port Data Output Register */ 5774 /*! @{ */ 5775 #define GPIO_PDOR_PDO_MASK (0xFFFFFFFFU) 5776 #define GPIO_PDOR_PDO_SHIFT (0U) 5777 /*! PDO - Port Data Output 5778 * 0b00000000000000000000000000000000..Logic level 0 is driven on pin, provided pin is configured for general-purpose output. 5779 * 0b00000000000000000000000000000001..Logic level 1 is driven on pin, provided pin is configured for general-purpose output. 5780 */ 5781 #define GPIO_PDOR_PDO(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO_SHIFT)) & GPIO_PDOR_PDO_MASK) 5782 /*! @} */ 5783 5784 /*! @name PSOR - Port Set Output Register */ 5785 /*! @{ */ 5786 #define GPIO_PSOR_PTSO_MASK (0xFFFFFFFFU) 5787 #define GPIO_PSOR_PTSO_SHIFT (0U) 5788 /*! PTSO - Port Set Output 5789 * 0b00000000000000000000000000000000..Corresponding bit in PDORn does not change. 5790 * 0b00000000000000000000000000000001..Corresponding bit in PDORn is set to logic 1. 5791 */ 5792 #define GPIO_PSOR_PTSO(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO_SHIFT)) & GPIO_PSOR_PTSO_MASK) 5793 /*! @} */ 5794 5795 /*! @name PCOR - Port Clear Output Register */ 5796 /*! @{ */ 5797 #define GPIO_PCOR_PTCO_MASK (0xFFFFFFFFU) 5798 #define GPIO_PCOR_PTCO_SHIFT (0U) 5799 /*! PTCO - Port Clear Output 5800 * 0b00000000000000000000000000000000..Corresponding bit in PDORn does not change. 5801 * 0b00000000000000000000000000000001..Corresponding bit in PDORn is cleared to logic 0. 5802 */ 5803 #define GPIO_PCOR_PTCO(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO_SHIFT)) & GPIO_PCOR_PTCO_MASK) 5804 /*! @} */ 5805 5806 /*! @name PTOR - Port Toggle Output Register */ 5807 /*! @{ */ 5808 #define GPIO_PTOR_PTTO_MASK (0xFFFFFFFFU) 5809 #define GPIO_PTOR_PTTO_SHIFT (0U) 5810 /*! PTTO - Port Toggle Output 5811 * 0b00000000000000000000000000000000..Corresponding bit in PDORn does not change. 5812 * 0b00000000000000000000000000000001..Corresponding bit in PDORn is set to the inverse of its existing logic state. 5813 */ 5814 #define GPIO_PTOR_PTTO(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO_SHIFT)) & GPIO_PTOR_PTTO_MASK) 5815 /*! @} */ 5816 5817 /*! @name PDIR - Port Data Input Register */ 5818 /*! @{ */ 5819 #define GPIO_PDIR_PDI_MASK (0xFFFFFFFFU) 5820 #define GPIO_PDIR_PDI_SHIFT (0U) 5821 /*! PDI - Port Data Input 5822 * 0b00000000000000000000000000000000..Pin logic level is logic 0, or is not configured for use by digital function. 5823 * 0b00000000000000000000000000000001..Pin logic level is logic 1. 5824 */ 5825 #define GPIO_PDIR_PDI(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI_SHIFT)) & GPIO_PDIR_PDI_MASK) 5826 /*! @} */ 5827 5828 /*! @name PDDR - Port Data Direction Register */ 5829 /*! @{ */ 5830 #define GPIO_PDDR_PDD_MASK (0xFFFFFFFFU) 5831 #define GPIO_PDDR_PDD_SHIFT (0U) 5832 /*! PDD - Port Data Direction 5833 * 0b00000000000000000000000000000000..Pin is configured as general-purpose input, for the GPIO function. 5834 * 0b00000000000000000000000000000001..Pin is configured as general-purpose output, for the GPIO function. 5835 */ 5836 #define GPIO_PDDR_PDD(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD_SHIFT)) & GPIO_PDDR_PDD_MASK) 5837 /*! @} */ 5838 5839 5840 /*! 5841 * @} 5842 */ /* end of group GPIO_Register_Masks */ 5843 5844 5845 /* GPIO - Peripheral instance base addresses */ 5846 /** Peripheral GPIOA base address */ 5847 #define GPIOA_BASE (0x400FF000u) 5848 /** Peripheral GPIOA base pointer */ 5849 #define GPIOA ((GPIO_Type *)GPIOA_BASE) 5850 /** Peripheral GPIOB base address */ 5851 #define GPIOB_BASE (0x400FF040u) 5852 /** Peripheral GPIOB base pointer */ 5853 #define GPIOB ((GPIO_Type *)GPIOB_BASE) 5854 /** Peripheral GPIOC base address */ 5855 #define GPIOC_BASE (0x400FF080u) 5856 /** Peripheral GPIOC base pointer */ 5857 #define GPIOC ((GPIO_Type *)GPIOC_BASE) 5858 /** Peripheral GPIOD base address */ 5859 #define GPIOD_BASE (0x400FF0C0u) 5860 /** Peripheral GPIOD base pointer */ 5861 #define GPIOD ((GPIO_Type *)GPIOD_BASE) 5862 /** Peripheral GPIOE base address */ 5863 #define GPIOE_BASE (0x400FF100u) 5864 /** Peripheral GPIOE base pointer */ 5865 #define GPIOE ((GPIO_Type *)GPIOE_BASE) 5866 /** Array initializer of GPIO peripheral base addresses */ 5867 #define GPIO_BASE_ADDRS { GPIOA_BASE, GPIOB_BASE, GPIOC_BASE, GPIOD_BASE, GPIOE_BASE } 5868 /** Array initializer of GPIO peripheral base pointers */ 5869 #define GPIO_BASE_PTRS { GPIOA, GPIOB, GPIOC, GPIOD, GPIOE } 5870 5871 /*! 5872 * @} 5873 */ /* end of group GPIO_Peripheral_Access_Layer */ 5874 5875 5876 /* ---------------------------------------------------------------------------- 5877 -- I2C Peripheral Access Layer 5878 ---------------------------------------------------------------------------- */ 5879 5880 /*! 5881 * @addtogroup I2C_Peripheral_Access_Layer I2C Peripheral Access Layer 5882 * @{ 5883 */ 5884 5885 /** I2C - Register Layout Typedef */ 5886 typedef struct { 5887 __IO uint8_t A1; /**< I2C Address Register 1, offset: 0x0 */ 5888 __IO uint8_t F; /**< I2C Frequency Divider register, offset: 0x1 */ 5889 __IO uint8_t C1; /**< I2C Control Register 1, offset: 0x2 */ 5890 __IO uint8_t S; /**< I2C Status register, offset: 0x3 */ 5891 __IO uint8_t D; /**< I2C Data I/O register, offset: 0x4 */ 5892 __IO uint8_t C2; /**< I2C Control Register 2, offset: 0x5 */ 5893 __IO uint8_t FLT; /**< I2C Programmable Input Glitch Filter Register, offset: 0x6 */ 5894 __IO uint8_t RA; /**< I2C Range Address register, offset: 0x7 */ 5895 __IO uint8_t SMB; /**< I2C SMBus Control and Status register, offset: 0x8 */ 5896 __IO uint8_t A2; /**< I2C Address Register 2, offset: 0x9 */ 5897 __IO uint8_t SLTH; /**< I2C SCL Low Timeout Register High, offset: 0xA */ 5898 __IO uint8_t SLTL; /**< I2C SCL Low Timeout Register Low, offset: 0xB */ 5899 } I2C_Type; 5900 5901 /* ---------------------------------------------------------------------------- 5902 -- I2C Register Masks 5903 ---------------------------------------------------------------------------- */ 5904 5905 /*! 5906 * @addtogroup I2C_Register_Masks I2C Register Masks 5907 * @{ 5908 */ 5909 5910 /*! @name A1 - I2C Address Register 1 */ 5911 /*! @{ */ 5912 #define I2C_A1_AD_MASK (0xFEU) 5913 #define I2C_A1_AD_SHIFT (1U) 5914 #define I2C_A1_AD(x) (((uint8_t)(((uint8_t)(x)) << I2C_A1_AD_SHIFT)) & I2C_A1_AD_MASK) 5915 /*! @} */ 5916 5917 /*! @name F - I2C Frequency Divider register */ 5918 /*! @{ */ 5919 #define I2C_F_ICR_MASK (0x3FU) 5920 #define I2C_F_ICR_SHIFT (0U) 5921 #define I2C_F_ICR(x) (((uint8_t)(((uint8_t)(x)) << I2C_F_ICR_SHIFT)) & I2C_F_ICR_MASK) 5922 #define I2C_F_MULT_MASK (0xC0U) 5923 #define I2C_F_MULT_SHIFT (6U) 5924 /*! MULT - Multiplier Factor 5925 * 0b00..mul = 1 5926 * 0b01..mul = 2 5927 * 0b10..mul = 4 5928 * 0b11..Reserved 5929 */ 5930 #define I2C_F_MULT(x) (((uint8_t)(((uint8_t)(x)) << I2C_F_MULT_SHIFT)) & I2C_F_MULT_MASK) 5931 /*! @} */ 5932 5933 /*! @name C1 - I2C Control Register 1 */ 5934 /*! @{ */ 5935 #define I2C_C1_DMAEN_MASK (0x1U) 5936 #define I2C_C1_DMAEN_SHIFT (0U) 5937 /*! DMAEN - DMA Enable 5938 * 0b0..All DMA signalling disabled. 5939 * 0b1..DMA transfer is enabled. While SMB[FACK] = 0, the following conditions trigger the DMA request: a data byte is received, and either address or data is transmitted. (ACK/NACK is automatic) the first byte received matches the A1 register or is a general call address. If any address matching occurs, S[IAAS] and S[TCF] are set. If the direction of transfer is known from master to slave, then it is not required to check S[SRW]. With this assumption, DMA can also be used in this case. In other cases, if the master reads data from the slave, then it is required to rewrite the C1 register operation. With this assumption, DMA cannot be used. When FACK = 1, an address or a data byte is transmitted. 5940 */ 5941 #define I2C_C1_DMAEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_DMAEN_SHIFT)) & I2C_C1_DMAEN_MASK) 5942 #define I2C_C1_WUEN_MASK (0x2U) 5943 #define I2C_C1_WUEN_SHIFT (1U) 5944 /*! WUEN - Wakeup Enable 5945 * 0b0..Normal operation. No interrupt generated when address matching in low power mode. 5946 * 0b1..Enables the wakeup function in low power mode. 5947 */ 5948 #define I2C_C1_WUEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_WUEN_SHIFT)) & I2C_C1_WUEN_MASK) 5949 #define I2C_C1_RSTA_MASK (0x4U) 5950 #define I2C_C1_RSTA_SHIFT (2U) 5951 #define I2C_C1_RSTA(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_RSTA_SHIFT)) & I2C_C1_RSTA_MASK) 5952 #define I2C_C1_TXAK_MASK (0x8U) 5953 #define I2C_C1_TXAK_SHIFT (3U) 5954 /*! TXAK - Transmit Acknowledge Enable 5955 * 0b0..An acknowledge signal is sent to the bus on the following receiving byte (if FACK is cleared) or the current receiving byte (if FACK is set). 5956 * 0b1..No acknowledge signal is sent to the bus on the following receiving data byte (if FACK is cleared) or the current receiving data byte (if FACK is set). 5957 */ 5958 #define I2C_C1_TXAK(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_TXAK_SHIFT)) & I2C_C1_TXAK_MASK) 5959 #define I2C_C1_TX_MASK (0x10U) 5960 #define I2C_C1_TX_SHIFT (4U) 5961 /*! TX - Transmit Mode Select 5962 * 0b0..Receive 5963 * 0b1..Transmit 5964 */ 5965 #define I2C_C1_TX(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_TX_SHIFT)) & I2C_C1_TX_MASK) 5966 #define I2C_C1_MST_MASK (0x20U) 5967 #define I2C_C1_MST_SHIFT (5U) 5968 /*! MST - Master Mode Select 5969 * 0b0..Slave mode 5970 * 0b1..Master mode 5971 */ 5972 #define I2C_C1_MST(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_MST_SHIFT)) & I2C_C1_MST_MASK) 5973 #define I2C_C1_IICIE_MASK (0x40U) 5974 #define I2C_C1_IICIE_SHIFT (6U) 5975 /*! IICIE - I2C Interrupt Enable 5976 * 0b0..Disabled 5977 * 0b1..Enabled 5978 */ 5979 #define I2C_C1_IICIE(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_IICIE_SHIFT)) & I2C_C1_IICIE_MASK) 5980 #define I2C_C1_IICEN_MASK (0x80U) 5981 #define I2C_C1_IICEN_SHIFT (7U) 5982 /*! IICEN - I2C Enable 5983 * 0b0..Disabled 5984 * 0b1..Enabled 5985 */ 5986 #define I2C_C1_IICEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_IICEN_SHIFT)) & I2C_C1_IICEN_MASK) 5987 /*! @} */ 5988 5989 /*! @name S - I2C Status register */ 5990 /*! @{ */ 5991 #define I2C_S_RXAK_MASK (0x1U) 5992 #define I2C_S_RXAK_SHIFT (0U) 5993 /*! RXAK - Receive Acknowledge 5994 * 0b0..Acknowledge signal was received after the completion of one byte of data transmission on the bus 5995 * 0b1..No acknowledge signal detected 5996 */ 5997 #define I2C_S_RXAK(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_RXAK_SHIFT)) & I2C_S_RXAK_MASK) 5998 #define I2C_S_IICIF_MASK (0x2U) 5999 #define I2C_S_IICIF_SHIFT (1U) 6000 /*! IICIF - Interrupt Flag 6001 * 0b0..No interrupt pending 6002 * 0b1..Interrupt pending 6003 */ 6004 #define I2C_S_IICIF(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_IICIF_SHIFT)) & I2C_S_IICIF_MASK) 6005 #define I2C_S_SRW_MASK (0x4U) 6006 #define I2C_S_SRW_SHIFT (2U) 6007 /*! SRW - Slave Read/Write 6008 * 0b0..Slave receive, master writing to slave 6009 * 0b1..Slave transmit, master reading from slave 6010 */ 6011 #define I2C_S_SRW(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_SRW_SHIFT)) & I2C_S_SRW_MASK) 6012 #define I2C_S_RAM_MASK (0x8U) 6013 #define I2C_S_RAM_SHIFT (3U) 6014 /*! RAM - Range Address Match 6015 * 0b0..Not addressed 6016 * 0b1..Addressed as a slave 6017 */ 6018 #define I2C_S_RAM(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_RAM_SHIFT)) & I2C_S_RAM_MASK) 6019 #define I2C_S_ARBL_MASK (0x10U) 6020 #define I2C_S_ARBL_SHIFT (4U) 6021 /*! ARBL - Arbitration Lost 6022 * 0b0..Standard bus operation. 6023 * 0b1..Loss of arbitration. 6024 */ 6025 #define I2C_S_ARBL(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_ARBL_SHIFT)) & I2C_S_ARBL_MASK) 6026 #define I2C_S_BUSY_MASK (0x20U) 6027 #define I2C_S_BUSY_SHIFT (5U) 6028 /*! BUSY - Bus Busy 6029 * 0b0..Bus is idle 6030 * 0b1..Bus is busy 6031 */ 6032 #define I2C_S_BUSY(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_BUSY_SHIFT)) & I2C_S_BUSY_MASK) 6033 #define I2C_S_IAAS_MASK (0x40U) 6034 #define I2C_S_IAAS_SHIFT (6U) 6035 /*! IAAS - Addressed As A Slave 6036 * 0b0..Not addressed 6037 * 0b1..Addressed as a slave 6038 */ 6039 #define I2C_S_IAAS(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_IAAS_SHIFT)) & I2C_S_IAAS_MASK) 6040 #define I2C_S_TCF_MASK (0x80U) 6041 #define I2C_S_TCF_SHIFT (7U) 6042 /*! TCF - Transfer Complete Flag 6043 * 0b0..Transfer in progress 6044 * 0b1..Transfer complete 6045 */ 6046 #define I2C_S_TCF(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_TCF_SHIFT)) & I2C_S_TCF_MASK) 6047 /*! @} */ 6048 6049 /*! @name D - I2C Data I/O register */ 6050 /*! @{ */ 6051 #define I2C_D_DATA_MASK (0xFFU) 6052 #define I2C_D_DATA_SHIFT (0U) 6053 #define I2C_D_DATA(x) (((uint8_t)(((uint8_t)(x)) << I2C_D_DATA_SHIFT)) & I2C_D_DATA_MASK) 6054 /*! @} */ 6055 6056 /*! @name C2 - I2C Control Register 2 */ 6057 /*! @{ */ 6058 #define I2C_C2_AD_MASK (0x7U) 6059 #define I2C_C2_AD_SHIFT (0U) 6060 #define I2C_C2_AD(x) (((uint8_t)(((uint8_t)(x)) << I2C_C2_AD_SHIFT)) & I2C_C2_AD_MASK) 6061 #define I2C_C2_RMEN_MASK (0x8U) 6062 #define I2C_C2_RMEN_SHIFT (3U) 6063 /*! RMEN - Range Address Matching Enable 6064 * 0b0..Range mode disabled. No address matching occurs for an address within the range of values of the A1 and RA registers. 6065 * 0b1..Range mode enabled. Address matching occurs when a slave receives an address within the range of values of the A1 and RA registers. 6066 */ 6067 #define I2C_C2_RMEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_C2_RMEN_SHIFT)) & I2C_C2_RMEN_MASK) 6068 #define I2C_C2_SBRC_MASK (0x10U) 6069 #define I2C_C2_SBRC_SHIFT (4U) 6070 /*! SBRC - Slave Baud Rate Control 6071 * 0b0..The slave baud rate follows the master baud rate and clock stretching may occur 6072 * 0b1..Slave baud rate is independent of the master baud rate 6073 */ 6074 #define I2C_C2_SBRC(x) (((uint8_t)(((uint8_t)(x)) << I2C_C2_SBRC_SHIFT)) & I2C_C2_SBRC_MASK) 6075 #define I2C_C2_HDRS_MASK (0x20U) 6076 #define I2C_C2_HDRS_SHIFT (5U) 6077 /*! HDRS - High Drive Select 6078 * 0b0..Normal drive mode 6079 * 0b1..High drive mode 6080 */ 6081 #define I2C_C2_HDRS(x) (((uint8_t)(((uint8_t)(x)) << I2C_C2_HDRS_SHIFT)) & I2C_C2_HDRS_MASK) 6082 #define I2C_C2_ADEXT_MASK (0x40U) 6083 #define I2C_C2_ADEXT_SHIFT (6U) 6084 /*! ADEXT - Address Extension 6085 * 0b0..7-bit address scheme 6086 * 0b1..10-bit address scheme 6087 */ 6088 #define I2C_C2_ADEXT(x) (((uint8_t)(((uint8_t)(x)) << I2C_C2_ADEXT_SHIFT)) & I2C_C2_ADEXT_MASK) 6089 #define I2C_C2_GCAEN_MASK (0x80U) 6090 #define I2C_C2_GCAEN_SHIFT (7U) 6091 /*! GCAEN - General Call Address Enable 6092 * 0b0..Disabled 6093 * 0b1..Enabled 6094 */ 6095 #define I2C_C2_GCAEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_C2_GCAEN_SHIFT)) & I2C_C2_GCAEN_MASK) 6096 /*! @} */ 6097 6098 /*! @name FLT - I2C Programmable Input Glitch Filter Register */ 6099 /*! @{ */ 6100 #define I2C_FLT_FLT_MASK (0xFU) 6101 #define I2C_FLT_FLT_SHIFT (0U) 6102 /*! FLT - I2C Programmable Filter Factor 6103 * 0b0000..No filter/bypass 6104 */ 6105 #define I2C_FLT_FLT(x) (((uint8_t)(((uint8_t)(x)) << I2C_FLT_FLT_SHIFT)) & I2C_FLT_FLT_MASK) 6106 #define I2C_FLT_STARTF_MASK (0x10U) 6107 #define I2C_FLT_STARTF_SHIFT (4U) 6108 /*! STARTF - I2C Bus Start Detect Flag 6109 * 0b0..No start happens on I2C bus 6110 * 0b1..Start detected on I2C bus 6111 */ 6112 #define I2C_FLT_STARTF(x) (((uint8_t)(((uint8_t)(x)) << I2C_FLT_STARTF_SHIFT)) & I2C_FLT_STARTF_MASK) 6113 #define I2C_FLT_SSIE_MASK (0x20U) 6114 #define I2C_FLT_SSIE_SHIFT (5U) 6115 /*! SSIE - I2C Bus Stop or Start Interrupt Enable 6116 * 0b0..Stop or start detection interrupt is disabled 6117 * 0b1..Stop or start detection interrupt is enabled 6118 */ 6119 #define I2C_FLT_SSIE(x) (((uint8_t)(((uint8_t)(x)) << I2C_FLT_SSIE_SHIFT)) & I2C_FLT_SSIE_MASK) 6120 #define I2C_FLT_STOPF_MASK (0x40U) 6121 #define I2C_FLT_STOPF_SHIFT (6U) 6122 /*! STOPF - I2C Bus Stop Detect Flag 6123 * 0b0..No stop happens on I2C bus 6124 * 0b1..Stop detected on I2C bus 6125 */ 6126 #define I2C_FLT_STOPF(x) (((uint8_t)(((uint8_t)(x)) << I2C_FLT_STOPF_SHIFT)) & I2C_FLT_STOPF_MASK) 6127 #define I2C_FLT_SHEN_MASK (0x80U) 6128 #define I2C_FLT_SHEN_SHIFT (7U) 6129 /*! SHEN - Stop Hold Enable 6130 * 0b0..Stop holdoff is disabled. The MCU's entry to stop mode is not gated. 6131 * 0b1..Stop holdoff is enabled. 6132 */ 6133 #define I2C_FLT_SHEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_FLT_SHEN_SHIFT)) & I2C_FLT_SHEN_MASK) 6134 /*! @} */ 6135 6136 /*! @name RA - I2C Range Address register */ 6137 /*! @{ */ 6138 #define I2C_RA_RAD_MASK (0xFEU) 6139 #define I2C_RA_RAD_SHIFT (1U) 6140 #define I2C_RA_RAD(x) (((uint8_t)(((uint8_t)(x)) << I2C_RA_RAD_SHIFT)) & I2C_RA_RAD_MASK) 6141 /*! @} */ 6142 6143 /*! @name SMB - I2C SMBus Control and Status register */ 6144 /*! @{ */ 6145 #define I2C_SMB_SHTF2IE_MASK (0x1U) 6146 #define I2C_SMB_SHTF2IE_SHIFT (0U) 6147 /*! SHTF2IE - SHTF2 Interrupt Enable 6148 * 0b0..SHTF2 interrupt is disabled 6149 * 0b1..SHTF2 interrupt is enabled 6150 */ 6151 #define I2C_SMB_SHTF2IE(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_SHTF2IE_SHIFT)) & I2C_SMB_SHTF2IE_MASK) 6152 #define I2C_SMB_SHTF2_MASK (0x2U) 6153 #define I2C_SMB_SHTF2_SHIFT (1U) 6154 /*! SHTF2 - SCL High Timeout Flag 2 6155 * 0b0..No SCL high and SDA low timeout occurs 6156 * 0b1..SCL high and SDA low timeout occurs 6157 */ 6158 #define I2C_SMB_SHTF2(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_SHTF2_SHIFT)) & I2C_SMB_SHTF2_MASK) 6159 #define I2C_SMB_SHTF1_MASK (0x4U) 6160 #define I2C_SMB_SHTF1_SHIFT (2U) 6161 /*! SHTF1 - SCL High Timeout Flag 1 6162 * 0b0..No SCL high and SDA high timeout occurs 6163 * 0b1..SCL high and SDA high timeout occurs 6164 */ 6165 #define I2C_SMB_SHTF1(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_SHTF1_SHIFT)) & I2C_SMB_SHTF1_MASK) 6166 #define I2C_SMB_SLTF_MASK (0x8U) 6167 #define I2C_SMB_SLTF_SHIFT (3U) 6168 /*! SLTF - SCL Low Timeout Flag 6169 * 0b0..No low timeout occurs 6170 * 0b1..Low timeout occurs 6171 */ 6172 #define I2C_SMB_SLTF(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_SLTF_SHIFT)) & I2C_SMB_SLTF_MASK) 6173 #define I2C_SMB_TCKSEL_MASK (0x10U) 6174 #define I2C_SMB_TCKSEL_SHIFT (4U) 6175 /*! TCKSEL - Timeout Counter Clock Select 6176 * 0b0..Timeout counter counts at the frequency of the I2C module clock / 64 6177 * 0b1..Timeout counter counts at the frequency of the I2C module clock 6178 */ 6179 #define I2C_SMB_TCKSEL(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_TCKSEL_SHIFT)) & I2C_SMB_TCKSEL_MASK) 6180 #define I2C_SMB_SIICAEN_MASK (0x20U) 6181 #define I2C_SMB_SIICAEN_SHIFT (5U) 6182 /*! SIICAEN - Second I2C Address Enable 6183 * 0b0..I2C address register 2 matching is disabled 6184 * 0b1..I2C address register 2 matching is enabled 6185 */ 6186 #define I2C_SMB_SIICAEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_SIICAEN_SHIFT)) & I2C_SMB_SIICAEN_MASK) 6187 #define I2C_SMB_ALERTEN_MASK (0x40U) 6188 #define I2C_SMB_ALERTEN_SHIFT (6U) 6189 /*! ALERTEN - SMBus Alert Response Address Enable 6190 * 0b0..SMBus alert response address matching is disabled 6191 * 0b1..SMBus alert response address matching is enabled 6192 */ 6193 #define I2C_SMB_ALERTEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_ALERTEN_SHIFT)) & I2C_SMB_ALERTEN_MASK) 6194 #define I2C_SMB_FACK_MASK (0x80U) 6195 #define I2C_SMB_FACK_SHIFT (7U) 6196 /*! FACK - Fast NACK/ACK Enable 6197 * 0b0..An ACK or NACK is sent on the following receiving data byte 6198 * 0b1..Writing 0 to TXAK after receiving a data byte generates an ACK. Writing 1 to TXAK after receiving a data byte generates a NACK. 6199 */ 6200 #define I2C_SMB_FACK(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_FACK_SHIFT)) & I2C_SMB_FACK_MASK) 6201 /*! @} */ 6202 6203 /*! @name A2 - I2C Address Register 2 */ 6204 /*! @{ */ 6205 #define I2C_A2_SAD_MASK (0xFEU) 6206 #define I2C_A2_SAD_SHIFT (1U) 6207 #define I2C_A2_SAD(x) (((uint8_t)(((uint8_t)(x)) << I2C_A2_SAD_SHIFT)) & I2C_A2_SAD_MASK) 6208 /*! @} */ 6209 6210 /*! @name SLTH - I2C SCL Low Timeout Register High */ 6211 /*! @{ */ 6212 #define I2C_SLTH_SSLT_MASK (0xFFU) 6213 #define I2C_SLTH_SSLT_SHIFT (0U) 6214 #define I2C_SLTH_SSLT(x) (((uint8_t)(((uint8_t)(x)) << I2C_SLTH_SSLT_SHIFT)) & I2C_SLTH_SSLT_MASK) 6215 /*! @} */ 6216 6217 /*! @name SLTL - I2C SCL Low Timeout Register Low */ 6218 /*! @{ */ 6219 #define I2C_SLTL_SSLT_MASK (0xFFU) 6220 #define I2C_SLTL_SSLT_SHIFT (0U) 6221 #define I2C_SLTL_SSLT(x) (((uint8_t)(((uint8_t)(x)) << I2C_SLTL_SSLT_SHIFT)) & I2C_SLTL_SSLT_MASK) 6222 /*! @} */ 6223 6224 6225 /*! 6226 * @} 6227 */ /* end of group I2C_Register_Masks */ 6228 6229 6230 /* I2C - Peripheral instance base addresses */ 6231 /** Peripheral I2C0 base address */ 6232 #define I2C0_BASE (0x40066000u) 6233 /** Peripheral I2C0 base pointer */ 6234 #define I2C0 ((I2C_Type *)I2C0_BASE) 6235 /** Array initializer of I2C peripheral base addresses */ 6236 #define I2C_BASE_ADDRS { I2C0_BASE } 6237 /** Array initializer of I2C peripheral base pointers */ 6238 #define I2C_BASE_PTRS { I2C0 } 6239 /** Interrupt vectors for the I2C peripheral type */ 6240 #define I2C_IRQS { I2C0_IRQn } 6241 6242 /*! 6243 * @} 6244 */ /* end of group I2C_Peripheral_Access_Layer */ 6245 6246 6247 /* ---------------------------------------------------------------------------- 6248 -- LLWU Peripheral Access Layer 6249 ---------------------------------------------------------------------------- */ 6250 6251 /*! 6252 * @addtogroup LLWU_Peripheral_Access_Layer LLWU Peripheral Access Layer 6253 * @{ 6254 */ 6255 6256 /** LLWU - Register Layout Typedef */ 6257 typedef struct { 6258 __IO uint8_t PE1; /**< LLWU Pin Enable 1 register, offset: 0x0 */ 6259 __IO uint8_t PE2; /**< LLWU Pin Enable 2 register, offset: 0x1 */ 6260 __IO uint8_t PE3; /**< LLWU Pin Enable 3 register, offset: 0x2 */ 6261 __IO uint8_t PE4; /**< LLWU Pin Enable 4 register, offset: 0x3 */ 6262 __IO uint8_t PE5; /**< LLWU Pin Enable 5 register, offset: 0x4 */ 6263 __IO uint8_t PE6; /**< LLWU Pin Enable 6 register, offset: 0x5 */ 6264 __IO uint8_t PE7; /**< LLWU Pin Enable 7 register, offset: 0x6 */ 6265 __IO uint8_t PE8; /**< LLWU Pin Enable 8 register, offset: 0x7 */ 6266 __IO uint8_t ME; /**< LLWU Module Enable register, offset: 0x8 */ 6267 __IO uint8_t PF1; /**< LLWU Pin Flag 1 register, offset: 0x9 */ 6268 __IO uint8_t PF2; /**< LLWU Pin Flag 2 register, offset: 0xA */ 6269 __IO uint8_t PF3; /**< LLWU Pin Flag 3 register, offset: 0xB */ 6270 __IO uint8_t PF4; /**< LLWU Pin Flag 4 register, offset: 0xC */ 6271 __I uint8_t MF5; /**< LLWU Module Flag 5 register, offset: 0xD */ 6272 __IO uint8_t FILT1; /**< LLWU Pin Filter 1 register, offset: 0xE */ 6273 __IO uint8_t FILT2; /**< LLWU Pin Filter 2 register, offset: 0xF */ 6274 } LLWU_Type; 6275 6276 /* ---------------------------------------------------------------------------- 6277 -- LLWU Register Masks 6278 ---------------------------------------------------------------------------- */ 6279 6280 /*! 6281 * @addtogroup LLWU_Register_Masks LLWU Register Masks 6282 * @{ 6283 */ 6284 6285 /*! @name PE1 - LLWU Pin Enable 1 register */ 6286 /*! @{ */ 6287 #define LLWU_PE1_WUPE0_MASK (0x3U) 6288 #define LLWU_PE1_WUPE0_SHIFT (0U) 6289 /*! WUPE0 - Wakeup Pin Enable For LLWU_P0 6290 * 0b00..External input pin disabled as wakeup input 6291 * 0b01..External input pin enabled with rising edge detection 6292 * 0b10..External input pin enabled with falling edge detection 6293 * 0b11..External input pin enabled with any change detection 6294 */ 6295 #define LLWU_PE1_WUPE0(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE1_WUPE0_SHIFT)) & LLWU_PE1_WUPE0_MASK) 6296 #define LLWU_PE1_WUPE1_MASK (0xCU) 6297 #define LLWU_PE1_WUPE1_SHIFT (2U) 6298 /*! WUPE1 - Wakeup Pin Enable For LLWU_P1 6299 * 0b00..External input pin disabled as wakeup input 6300 * 0b01..External input pin enabled with rising edge detection 6301 * 0b10..External input pin enabled with falling edge detection 6302 * 0b11..External input pin enabled with any change detection 6303 */ 6304 #define LLWU_PE1_WUPE1(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE1_WUPE1_SHIFT)) & LLWU_PE1_WUPE1_MASK) 6305 #define LLWU_PE1_WUPE2_MASK (0x30U) 6306 #define LLWU_PE1_WUPE2_SHIFT (4U) 6307 /*! WUPE2 - Wakeup Pin Enable For LLWU_P2 6308 * 0b00..External input pin disabled as wakeup input 6309 * 0b01..External input pin enabled with rising edge detection 6310 * 0b10..External input pin enabled with falling edge detection 6311 * 0b11..External input pin enabled with any change detection 6312 */ 6313 #define LLWU_PE1_WUPE2(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE1_WUPE2_SHIFT)) & LLWU_PE1_WUPE2_MASK) 6314 #define LLWU_PE1_WUPE3_MASK (0xC0U) 6315 #define LLWU_PE1_WUPE3_SHIFT (6U) 6316 /*! WUPE3 - Wakeup Pin Enable For LLWU_P3 6317 * 0b00..External input pin disabled as wakeup input 6318 * 0b01..External input pin enabled with rising edge detection 6319 * 0b10..External input pin enabled with falling edge detection 6320 * 0b11..External input pin enabled with any change detection 6321 */ 6322 #define LLWU_PE1_WUPE3(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE1_WUPE3_SHIFT)) & LLWU_PE1_WUPE3_MASK) 6323 /*! @} */ 6324 6325 /*! @name PE2 - LLWU Pin Enable 2 register */ 6326 /*! @{ */ 6327 #define LLWU_PE2_WUPE4_MASK (0x3U) 6328 #define LLWU_PE2_WUPE4_SHIFT (0U) 6329 /*! WUPE4 - Wakeup Pin Enable For LLWU_P4 6330 * 0b00..External input pin disabled as wakeup input 6331 * 0b01..External input pin enabled with rising edge detection 6332 * 0b10..External input pin enabled with falling edge detection 6333 * 0b11..External input pin enabled with any change detection 6334 */ 6335 #define LLWU_PE2_WUPE4(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE2_WUPE4_SHIFT)) & LLWU_PE2_WUPE4_MASK) 6336 #define LLWU_PE2_WUPE5_MASK (0xCU) 6337 #define LLWU_PE2_WUPE5_SHIFT (2U) 6338 /*! WUPE5 - Wakeup Pin Enable For LLWU_P5 6339 * 0b00..External input pin disabled as wakeup input 6340 * 0b01..External input pin enabled with rising edge detection 6341 * 0b10..External input pin enabled with falling edge detection 6342 * 0b11..External input pin enabled with any change detection 6343 */ 6344 #define LLWU_PE2_WUPE5(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE2_WUPE5_SHIFT)) & LLWU_PE2_WUPE5_MASK) 6345 #define LLWU_PE2_WUPE6_MASK (0x30U) 6346 #define LLWU_PE2_WUPE6_SHIFT (4U) 6347 /*! WUPE6 - Wakeup Pin Enable For LLWU_P6 6348 * 0b00..External input pin disabled as wakeup input 6349 * 0b01..External input pin enabled with rising edge detection 6350 * 0b10..External input pin enabled with falling edge detection 6351 * 0b11..External input pin enabled with any change detection 6352 */ 6353 #define LLWU_PE2_WUPE6(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE2_WUPE6_SHIFT)) & LLWU_PE2_WUPE6_MASK) 6354 #define LLWU_PE2_WUPE7_MASK (0xC0U) 6355 #define LLWU_PE2_WUPE7_SHIFT (6U) 6356 /*! WUPE7 - Wakeup Pin Enable For LLWU_P7 6357 * 0b00..External input pin disabled as wakeup input 6358 * 0b01..External input pin enabled with rising edge detection 6359 * 0b10..External input pin enabled with falling edge detection 6360 * 0b11..External input pin enabled with any change detection 6361 */ 6362 #define LLWU_PE2_WUPE7(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE2_WUPE7_SHIFT)) & LLWU_PE2_WUPE7_MASK) 6363 /*! @} */ 6364 6365 /*! @name PE3 - LLWU Pin Enable 3 register */ 6366 /*! @{ */ 6367 #define LLWU_PE3_WUPE8_MASK (0x3U) 6368 #define LLWU_PE3_WUPE8_SHIFT (0U) 6369 /*! WUPE8 - Wakeup Pin Enable For LLWU_P8 6370 * 0b00..External input pin disabled as wakeup input 6371 * 0b01..External input pin enabled with rising edge detection 6372 * 0b10..External input pin enabled with falling edge detection 6373 * 0b11..External input pin enabled with any change detection 6374 */ 6375 #define LLWU_PE3_WUPE8(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE3_WUPE8_SHIFT)) & LLWU_PE3_WUPE8_MASK) 6376 #define LLWU_PE3_WUPE9_MASK (0xCU) 6377 #define LLWU_PE3_WUPE9_SHIFT (2U) 6378 /*! WUPE9 - Wakeup Pin Enable For LLWU_P9 6379 * 0b00..External input pin disabled as wakeup input 6380 * 0b01..External input pin enabled with rising edge detection 6381 * 0b10..External input pin enabled with falling edge detection 6382 * 0b11..External input pin enabled with any change detection 6383 */ 6384 #define LLWU_PE3_WUPE9(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE3_WUPE9_SHIFT)) & LLWU_PE3_WUPE9_MASK) 6385 #define LLWU_PE3_WUPE10_MASK (0x30U) 6386 #define LLWU_PE3_WUPE10_SHIFT (4U) 6387 /*! WUPE10 - Wakeup Pin Enable For LLWU_P10 6388 * 0b00..External input pin disabled as wakeup input 6389 * 0b01..External input pin enabled with rising edge detection 6390 * 0b10..External input pin enabled with falling edge detection 6391 * 0b11..External input pin enabled with any change detection 6392 */ 6393 #define LLWU_PE3_WUPE10(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE3_WUPE10_SHIFT)) & LLWU_PE3_WUPE10_MASK) 6394 #define LLWU_PE3_WUPE11_MASK (0xC0U) 6395 #define LLWU_PE3_WUPE11_SHIFT (6U) 6396 /*! WUPE11 - Wakeup Pin Enable For LLWU_P11 6397 * 0b00..External input pin disabled as wakeup input 6398 * 0b01..External input pin enabled with rising edge detection 6399 * 0b10..External input pin enabled with falling edge detection 6400 * 0b11..External input pin enabled with any change detection 6401 */ 6402 #define LLWU_PE3_WUPE11(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE3_WUPE11_SHIFT)) & LLWU_PE3_WUPE11_MASK) 6403 /*! @} */ 6404 6405 /*! @name PE4 - LLWU Pin Enable 4 register */ 6406 /*! @{ */ 6407 #define LLWU_PE4_WUPE12_MASK (0x3U) 6408 #define LLWU_PE4_WUPE12_SHIFT (0U) 6409 /*! WUPE12 - Wakeup Pin Enable For LLWU_P12 6410 * 0b00..External input pin disabled as wakeup input 6411 * 0b01..External input pin enabled with rising edge detection 6412 * 0b10..External input pin enabled with falling edge detection 6413 * 0b11..External input pin enabled with any change detection 6414 */ 6415 #define LLWU_PE4_WUPE12(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE4_WUPE12_SHIFT)) & LLWU_PE4_WUPE12_MASK) 6416 #define LLWU_PE4_WUPE13_MASK (0xCU) 6417 #define LLWU_PE4_WUPE13_SHIFT (2U) 6418 /*! WUPE13 - Wakeup Pin Enable For LLWU_P13 6419 * 0b00..External input pin disabled as wakeup input 6420 * 0b01..External input pin enabled with rising edge detection 6421 * 0b10..External input pin enabled with falling edge detection 6422 * 0b11..External input pin enabled with any change detection 6423 */ 6424 #define LLWU_PE4_WUPE13(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE4_WUPE13_SHIFT)) & LLWU_PE4_WUPE13_MASK) 6425 #define LLWU_PE4_WUPE14_MASK (0x30U) 6426 #define LLWU_PE4_WUPE14_SHIFT (4U) 6427 /*! WUPE14 - Wakeup Pin Enable For LLWU_P14 6428 * 0b00..External input pin disabled as wakeup input 6429 * 0b01..External input pin enabled with rising edge detection 6430 * 0b10..External input pin enabled with falling edge detection 6431 * 0b11..External input pin enabled with any change detection 6432 */ 6433 #define LLWU_PE4_WUPE14(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE4_WUPE14_SHIFT)) & LLWU_PE4_WUPE14_MASK) 6434 #define LLWU_PE4_WUPE15_MASK (0xC0U) 6435 #define LLWU_PE4_WUPE15_SHIFT (6U) 6436 /*! WUPE15 - Wakeup Pin Enable For LLWU_P15 6437 * 0b00..External input pin disabled as wakeup input 6438 * 0b01..External input pin enabled with rising edge detection 6439 * 0b10..External input pin enabled with falling edge detection 6440 * 0b11..External input pin enabled with any change detection 6441 */ 6442 #define LLWU_PE4_WUPE15(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE4_WUPE15_SHIFT)) & LLWU_PE4_WUPE15_MASK) 6443 /*! @} */ 6444 6445 /*! @name PE5 - LLWU Pin Enable 5 register */ 6446 /*! @{ */ 6447 #define LLWU_PE5_WUPE16_MASK (0x3U) 6448 #define LLWU_PE5_WUPE16_SHIFT (0U) 6449 /*! WUPE16 - Wakeup Pin Enable For LLWU_P16 6450 * 0b00..External input pin disabled as wakeup input 6451 * 0b01..External input pin enabled with rising edge detection 6452 * 0b10..External input pin enabled with falling edge detection 6453 * 0b11..External input pin enabled with any change detection 6454 */ 6455 #define LLWU_PE5_WUPE16(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE5_WUPE16_SHIFT)) & LLWU_PE5_WUPE16_MASK) 6456 #define LLWU_PE5_WUPE17_MASK (0xCU) 6457 #define LLWU_PE5_WUPE17_SHIFT (2U) 6458 /*! WUPE17 - Wakeup Pin Enable For LLWU_P17 6459 * 0b00..External input pin disabled as wakeup input 6460 * 0b01..External input pin enabled with rising edge detection 6461 * 0b10..External input pin enabled with falling edge detection 6462 * 0b11..External input pin enabled with any change detection 6463 */ 6464 #define LLWU_PE5_WUPE17(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE5_WUPE17_SHIFT)) & LLWU_PE5_WUPE17_MASK) 6465 #define LLWU_PE5_WUPE18_MASK (0x30U) 6466 #define LLWU_PE5_WUPE18_SHIFT (4U) 6467 /*! WUPE18 - Wakeup Pin Enable For LLWU_P18 6468 * 0b00..External input pin disabled as wakeup input 6469 * 0b01..External input pin enabled with rising edge detection 6470 * 0b10..External input pin enabled with falling edge detection 6471 * 0b11..External input pin enabled with any change detection 6472 */ 6473 #define LLWU_PE5_WUPE18(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE5_WUPE18_SHIFT)) & LLWU_PE5_WUPE18_MASK) 6474 #define LLWU_PE5_WUPE19_MASK (0xC0U) 6475 #define LLWU_PE5_WUPE19_SHIFT (6U) 6476 /*! WUPE19 - Wakeup Pin Enable For LLWU_P19 6477 * 0b00..External input pin disabled as wakeup input 6478 * 0b01..External input pin enabled with rising edge detection 6479 * 0b10..External input pin enabled with falling edge detection 6480 * 0b11..External input pin enabled with any change detection 6481 */ 6482 #define LLWU_PE5_WUPE19(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE5_WUPE19_SHIFT)) & LLWU_PE5_WUPE19_MASK) 6483 /*! @} */ 6484 6485 /*! @name PE6 - LLWU Pin Enable 6 register */ 6486 /*! @{ */ 6487 #define LLWU_PE6_WUPE20_MASK (0x3U) 6488 #define LLWU_PE6_WUPE20_SHIFT (0U) 6489 /*! WUPE20 - Wakeup Pin Enable For LLWU_P20 6490 * 0b00..External input pin disabled as wakeup input 6491 * 0b01..External input pin enabled with rising edge detection 6492 * 0b10..External input pin enabled with falling edge detection 6493 * 0b11..External input pin enabled with any change detection 6494 */ 6495 #define LLWU_PE6_WUPE20(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE6_WUPE20_SHIFT)) & LLWU_PE6_WUPE20_MASK) 6496 #define LLWU_PE6_WUPE21_MASK (0xCU) 6497 #define LLWU_PE6_WUPE21_SHIFT (2U) 6498 /*! WUPE21 - Wakeup Pin Enable For LLWU_P21 6499 * 0b00..External input pin disabled as wakeup input 6500 * 0b01..External input pin enabled with rising edge detection 6501 * 0b10..External input pin enabled with falling edge detection 6502 * 0b11..External input pin enabled with any change detection 6503 */ 6504 #define LLWU_PE6_WUPE21(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE6_WUPE21_SHIFT)) & LLWU_PE6_WUPE21_MASK) 6505 #define LLWU_PE6_WUPE22_MASK (0x30U) 6506 #define LLWU_PE6_WUPE22_SHIFT (4U) 6507 /*! WUPE22 - Wakeup Pin Enable For LLWU_P22 6508 * 0b00..External input pin disabled as wakeup input 6509 * 0b01..External input pin enabled with rising edge detection 6510 * 0b10..External input pin enabled with falling edge detection 6511 * 0b11..External input pin enabled with any change detection 6512 */ 6513 #define LLWU_PE6_WUPE22(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE6_WUPE22_SHIFT)) & LLWU_PE6_WUPE22_MASK) 6514 #define LLWU_PE6_WUPE23_MASK (0xC0U) 6515 #define LLWU_PE6_WUPE23_SHIFT (6U) 6516 /*! WUPE23 - Wakeup Pin Enable For LLWU_P23 6517 * 0b00..External input pin disabled as wakeup input 6518 * 0b01..External input pin enabled with rising edge detection 6519 * 0b10..External input pin enabled with falling edge detection 6520 * 0b11..External input pin enabled with any change detection 6521 */ 6522 #define LLWU_PE6_WUPE23(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE6_WUPE23_SHIFT)) & LLWU_PE6_WUPE23_MASK) 6523 /*! @} */ 6524 6525 /*! @name PE7 - LLWU Pin Enable 7 register */ 6526 /*! @{ */ 6527 #define LLWU_PE7_WUPE24_MASK (0x3U) 6528 #define LLWU_PE7_WUPE24_SHIFT (0U) 6529 /*! WUPE24 - Wakeup Pin Enable For LLWU_P24 6530 * 0b00..External input pin disabled as wakeup input 6531 * 0b01..External input pin enabled with rising edge detection 6532 * 0b10..External input pin enabled with falling edge detection 6533 * 0b11..External input pin enabled with any change detection 6534 */ 6535 #define LLWU_PE7_WUPE24(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE7_WUPE24_SHIFT)) & LLWU_PE7_WUPE24_MASK) 6536 #define LLWU_PE7_WUPE25_MASK (0xCU) 6537 #define LLWU_PE7_WUPE25_SHIFT (2U) 6538 /*! WUPE25 - Wakeup Pin Enable For LLWU_P25 6539 * 0b00..External input pin disabled as wakeup input 6540 * 0b01..External input pin enabled with rising edge detection 6541 * 0b10..External input pin enabled with falling edge detection 6542 * 0b11..External input pin enabled with any change detection 6543 */ 6544 #define LLWU_PE7_WUPE25(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE7_WUPE25_SHIFT)) & LLWU_PE7_WUPE25_MASK) 6545 #define LLWU_PE7_WUPE26_MASK (0x30U) 6546 #define LLWU_PE7_WUPE26_SHIFT (4U) 6547 /*! WUPE26 - Wakeup Pin Enable For LLWU_P26 6548 * 0b00..External input pin disabled as wakeup input 6549 * 0b01..External input pin enabled with rising edge detection 6550 * 0b10..External input pin enabled with falling edge detection 6551 * 0b11..External input pin enabled with any change detection 6552 */ 6553 #define LLWU_PE7_WUPE26(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE7_WUPE26_SHIFT)) & LLWU_PE7_WUPE26_MASK) 6554 #define LLWU_PE7_WUPE27_MASK (0xC0U) 6555 #define LLWU_PE7_WUPE27_SHIFT (6U) 6556 /*! WUPE27 - Wakeup Pin Enable For LLWU_P27 6557 * 0b00..External input pin disabled as wakeup input 6558 * 0b01..External input pin enabled with rising edge detection 6559 * 0b10..External input pin enabled with falling edge detection 6560 * 0b11..External input pin enabled with any change detection 6561 */ 6562 #define LLWU_PE7_WUPE27(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE7_WUPE27_SHIFT)) & LLWU_PE7_WUPE27_MASK) 6563 /*! @} */ 6564 6565 /*! @name PE8 - LLWU Pin Enable 8 register */ 6566 /*! @{ */ 6567 #define LLWU_PE8_WUPE28_MASK (0x3U) 6568 #define LLWU_PE8_WUPE28_SHIFT (0U) 6569 /*! WUPE28 - Wakeup Pin Enable For LLWU_P28 6570 * 0b00..External input pin disabled as wakeup input 6571 * 0b01..External input pin enabled with rising edge detection 6572 * 0b10..External input pin enabled with falling edge detection 6573 * 0b11..External input pin enabled with any change detection 6574 */ 6575 #define LLWU_PE8_WUPE28(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE8_WUPE28_SHIFT)) & LLWU_PE8_WUPE28_MASK) 6576 #define LLWU_PE8_WUPE29_MASK (0xCU) 6577 #define LLWU_PE8_WUPE29_SHIFT (2U) 6578 /*! WUPE29 - Wakeup Pin Enable For LLWU_P29 6579 * 0b00..External input pin disabled as wakeup input 6580 * 0b01..External input pin enabled with rising edge detection 6581 * 0b10..External input pin enabled with falling edge detection 6582 * 0b11..External input pin enabled with any change detection 6583 */ 6584 #define LLWU_PE8_WUPE29(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE8_WUPE29_SHIFT)) & LLWU_PE8_WUPE29_MASK) 6585 #define LLWU_PE8_WUPE30_MASK (0x30U) 6586 #define LLWU_PE8_WUPE30_SHIFT (4U) 6587 /*! WUPE30 - Wakeup Pin Enable For LLWU_P30 6588 * 0b00..External input pin disabled as wakeup input 6589 * 0b01..External input pin enabled with rising edge detection 6590 * 0b10..External input pin enabled with falling edge detection 6591 * 0b11..External input pin enabled with any change detection 6592 */ 6593 #define LLWU_PE8_WUPE30(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE8_WUPE30_SHIFT)) & LLWU_PE8_WUPE30_MASK) 6594 #define LLWU_PE8_WUPE31_MASK (0xC0U) 6595 #define LLWU_PE8_WUPE31_SHIFT (6U) 6596 /*! WUPE31 - Wakeup Pin Enable For LLWU_P31 6597 * 0b00..External input pin disabled as wakeup input 6598 * 0b01..External input pin enabled with rising edge detection 6599 * 0b10..External input pin enabled with falling edge detection 6600 * 0b11..External input pin enabled with any change detection 6601 */ 6602 #define LLWU_PE8_WUPE31(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE8_WUPE31_SHIFT)) & LLWU_PE8_WUPE31_MASK) 6603 /*! @} */ 6604 6605 /*! @name ME - LLWU Module Enable register */ 6606 /*! @{ */ 6607 #define LLWU_ME_WUME0_MASK (0x1U) 6608 #define LLWU_ME_WUME0_SHIFT (0U) 6609 /*! WUME0 - Wakeup Module Enable For Module 0 6610 * 0b0..Internal module flag not used as wakeup source 6611 * 0b1..Internal module flag used as wakeup source 6612 */ 6613 #define LLWU_ME_WUME0(x) (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME0_SHIFT)) & LLWU_ME_WUME0_MASK) 6614 #define LLWU_ME_WUME1_MASK (0x2U) 6615 #define LLWU_ME_WUME1_SHIFT (1U) 6616 /*! WUME1 - Wakeup Module Enable for Module 1 6617 * 0b0..Internal module flag not used as wakeup source 6618 * 0b1..Internal module flag used as wakeup source 6619 */ 6620 #define LLWU_ME_WUME1(x) (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME1_SHIFT)) & LLWU_ME_WUME1_MASK) 6621 #define LLWU_ME_WUME2_MASK (0x4U) 6622 #define LLWU_ME_WUME2_SHIFT (2U) 6623 /*! WUME2 - Wakeup Module Enable For Module 2 6624 * 0b0..Internal module flag not used as wakeup source 6625 * 0b1..Internal module flag used as wakeup source 6626 */ 6627 #define LLWU_ME_WUME2(x) (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME2_SHIFT)) & LLWU_ME_WUME2_MASK) 6628 #define LLWU_ME_WUME3_MASK (0x8U) 6629 #define LLWU_ME_WUME3_SHIFT (3U) 6630 /*! WUME3 - Wakeup Module Enable For Module 3 6631 * 0b0..Internal module flag not used as wakeup source 6632 * 0b1..Internal module flag used as wakeup source 6633 */ 6634 #define LLWU_ME_WUME3(x) (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME3_SHIFT)) & LLWU_ME_WUME3_MASK) 6635 #define LLWU_ME_WUME4_MASK (0x10U) 6636 #define LLWU_ME_WUME4_SHIFT (4U) 6637 /*! WUME4 - Wakeup Module Enable For Module 4 6638 * 0b0..Internal module flag not used as wakeup source 6639 * 0b1..Internal module flag used as wakeup source 6640 */ 6641 #define LLWU_ME_WUME4(x) (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME4_SHIFT)) & LLWU_ME_WUME4_MASK) 6642 #define LLWU_ME_WUME5_MASK (0x20U) 6643 #define LLWU_ME_WUME5_SHIFT (5U) 6644 /*! WUME5 - Wakeup Module Enable For Module 5 6645 * 0b0..Internal module flag not used as wakeup source 6646 * 0b1..Internal module flag used as wakeup source 6647 */ 6648 #define LLWU_ME_WUME5(x) (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME5_SHIFT)) & LLWU_ME_WUME5_MASK) 6649 #define LLWU_ME_WUME6_MASK (0x40U) 6650 #define LLWU_ME_WUME6_SHIFT (6U) 6651 /*! WUME6 - Wakeup Module Enable For Module 6 6652 * 0b0..Internal module flag not used as wakeup source 6653 * 0b1..Internal module flag used as wakeup source 6654 */ 6655 #define LLWU_ME_WUME6(x) (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME6_SHIFT)) & LLWU_ME_WUME6_MASK) 6656 #define LLWU_ME_WUME7_MASK (0x80U) 6657 #define LLWU_ME_WUME7_SHIFT (7U) 6658 /*! WUME7 - Wakeup Module Enable For Module 7 6659 * 0b0..Internal module flag not used as wakeup source 6660 * 0b1..Internal module flag used as wakeup source 6661 */ 6662 #define LLWU_ME_WUME7(x) (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME7_SHIFT)) & LLWU_ME_WUME7_MASK) 6663 /*! @} */ 6664 6665 /*! @name PF1 - LLWU Pin Flag 1 register */ 6666 /*! @{ */ 6667 #define LLWU_PF1_WUF0_MASK (0x1U) 6668 #define LLWU_PF1_WUF0_SHIFT (0U) 6669 /*! WUF0 - Wakeup Flag For LLWU_P0 6670 * 0b0..LLWU_P0 input was not a wakeup source 6671 * 0b1..LLWU_P0 input was a wakeup source 6672 */ 6673 #define LLWU_PF1_WUF0(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PF1_WUF0_SHIFT)) & LLWU_PF1_WUF0_MASK) 6674 #define LLWU_PF1_WUF1_MASK (0x2U) 6675 #define LLWU_PF1_WUF1_SHIFT (1U) 6676 /*! WUF1 - Wakeup Flag For LLWU_P1 6677 * 0b0..LLWU_P1 input was not a wakeup source 6678 * 0b1..LLWU_P1 input was a wakeup source 6679 */ 6680 #define LLWU_PF1_WUF1(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PF1_WUF1_SHIFT)) & LLWU_PF1_WUF1_MASK) 6681 #define LLWU_PF1_WUF2_MASK (0x4U) 6682 #define LLWU_PF1_WUF2_SHIFT (2U) 6683 /*! WUF2 - Wakeup Flag For LLWU_P2 6684 * 0b0..LLWU_P2 input was not a wakeup source 6685 * 0b1..LLWU_P2 input was a wakeup source 6686 */ 6687 #define LLWU_PF1_WUF2(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PF1_WUF2_SHIFT)) & LLWU_PF1_WUF2_MASK) 6688 #define LLWU_PF1_WUF3_MASK (0x8U) 6689 #define LLWU_PF1_WUF3_SHIFT (3U) 6690 /*! WUF3 - Wakeup Flag For LLWU_P3 6691 * 0b0..LLWU_P3 input was not a wakeup source 6692 * 0b1..LLWU_P3 input was a wakeup source 6693 */ 6694 #define LLWU_PF1_WUF3(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PF1_WUF3_SHIFT)) & LLWU_PF1_WUF3_MASK) 6695 #define LLWU_PF1_WUF4_MASK (0x10U) 6696 #define LLWU_PF1_WUF4_SHIFT (4U) 6697 /*! WUF4 - Wakeup Flag For LLWU_P4 6698 * 0b0..LLWU_P4 input was not a wakeup source 6699 * 0b1..LLWU_P4 input was a wakeup source 6700 */ 6701 #define LLWU_PF1_WUF4(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PF1_WUF4_SHIFT)) & LLWU_PF1_WUF4_MASK) 6702 #define LLWU_PF1_WUF5_MASK (0x20U) 6703 #define LLWU_PF1_WUF5_SHIFT (5U) 6704 /*! WUF5 - Wakeup Flag For LLWU_P5 6705 * 0b0..LLWU_P5 input was not a wakeup source 6706 * 0b1..LLWU_P5 input was a wakeup source 6707 */ 6708 #define LLWU_PF1_WUF5(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PF1_WUF5_SHIFT)) & LLWU_PF1_WUF5_MASK) 6709 #define LLWU_PF1_WUF6_MASK (0x40U) 6710 #define LLWU_PF1_WUF6_SHIFT (6U) 6711 /*! WUF6 - Wakeup Flag For LLWU_P6 6712 * 0b0..LLWU_P6 input was not a wakeup source 6713 * 0b1..LLWU_P6 input was a wakeup source 6714 */ 6715 #define LLWU_PF1_WUF6(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PF1_WUF6_SHIFT)) & LLWU_PF1_WUF6_MASK) 6716 #define LLWU_PF1_WUF7_MASK (0x80U) 6717 #define LLWU_PF1_WUF7_SHIFT (7U) 6718 /*! WUF7 - Wakeup Flag For LLWU_P7 6719 * 0b0..LLWU_P7 input was not a wakeup source 6720 * 0b1..LLWU_P7 input was a wakeup source 6721 */ 6722 #define LLWU_PF1_WUF7(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PF1_WUF7_SHIFT)) & LLWU_PF1_WUF7_MASK) 6723 /*! @} */ 6724 6725 /*! @name PF2 - LLWU Pin Flag 2 register */ 6726 /*! @{ */ 6727 #define LLWU_PF2_WUF8_MASK (0x1U) 6728 #define LLWU_PF2_WUF8_SHIFT (0U) 6729 /*! WUF8 - Wakeup Flag For LLWU_P8 6730 * 0b0..LLWU_P8 input was not a wakeup source 6731 * 0b1..LLWU_P8 input was a wakeup source 6732 */ 6733 #define LLWU_PF2_WUF8(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PF2_WUF8_SHIFT)) & LLWU_PF2_WUF8_MASK) 6734 #define LLWU_PF2_WUF9_MASK (0x2U) 6735 #define LLWU_PF2_WUF9_SHIFT (1U) 6736 /*! WUF9 - Wakeup Flag For LLWU_P9 6737 * 0b0..LLWU_P9 input was not a wakeup source 6738 * 0b1..LLWU_P9 input was a wakeup source 6739 */ 6740 #define LLWU_PF2_WUF9(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PF2_WUF9_SHIFT)) & LLWU_PF2_WUF9_MASK) 6741 #define LLWU_PF2_WUF10_MASK (0x4U) 6742 #define LLWU_PF2_WUF10_SHIFT (2U) 6743 /*! WUF10 - Wakeup Flag For LLWU_P10 6744 * 0b0..LLWU_P10 input was not a wakeup source 6745 * 0b1..LLWU_P10 input was a wakeup source 6746 */ 6747 #define LLWU_PF2_WUF10(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PF2_WUF10_SHIFT)) & LLWU_PF2_WUF10_MASK) 6748 #define LLWU_PF2_WUF11_MASK (0x8U) 6749 #define LLWU_PF2_WUF11_SHIFT (3U) 6750 /*! WUF11 - Wakeup Flag For LLWU_P11 6751 * 0b0..LLWU_P11 input was not a wakeup source 6752 * 0b1..LLWU_P11 input was a wakeup source 6753 */ 6754 #define LLWU_PF2_WUF11(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PF2_WUF11_SHIFT)) & LLWU_PF2_WUF11_MASK) 6755 #define LLWU_PF2_WUF12_MASK (0x10U) 6756 #define LLWU_PF2_WUF12_SHIFT (4U) 6757 /*! WUF12 - Wakeup Flag For LLWU_P12 6758 * 0b0..LLWU_P12 input was not a wakeup source 6759 * 0b1..LLWU_P12 input was a wakeup source 6760 */ 6761 #define LLWU_PF2_WUF12(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PF2_WUF12_SHIFT)) & LLWU_PF2_WUF12_MASK) 6762 #define LLWU_PF2_WUF13_MASK (0x20U) 6763 #define LLWU_PF2_WUF13_SHIFT (5U) 6764 /*! WUF13 - Wakeup Flag For LLWU_P13 6765 * 0b0..LLWU_P13 input was not a wakeup source 6766 * 0b1..LLWU_P13 input was a wakeup source 6767 */ 6768 #define LLWU_PF2_WUF13(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PF2_WUF13_SHIFT)) & LLWU_PF2_WUF13_MASK) 6769 #define LLWU_PF2_WUF14_MASK (0x40U) 6770 #define LLWU_PF2_WUF14_SHIFT (6U) 6771 /*! WUF14 - Wakeup Flag For LLWU_P14 6772 * 0b0..LLWU_P14 input was not a wakeup source 6773 * 0b1..LLWU_P14 input was a wakeup source 6774 */ 6775 #define LLWU_PF2_WUF14(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PF2_WUF14_SHIFT)) & LLWU_PF2_WUF14_MASK) 6776 #define LLWU_PF2_WUF15_MASK (0x80U) 6777 #define LLWU_PF2_WUF15_SHIFT (7U) 6778 /*! WUF15 - Wakeup Flag For LLWU_P15 6779 * 0b0..LLWU_P15 input was not a wakeup source 6780 * 0b1..LLWU_P15 input was a wakeup source 6781 */ 6782 #define LLWU_PF2_WUF15(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PF2_WUF15_SHIFT)) & LLWU_PF2_WUF15_MASK) 6783 /*! @} */ 6784 6785 /*! @name PF3 - LLWU Pin Flag 3 register */ 6786 /*! @{ */ 6787 #define LLWU_PF3_WUF16_MASK (0x1U) 6788 #define LLWU_PF3_WUF16_SHIFT (0U) 6789 /*! WUF16 - Wakeup Flag For LLWU_P16 6790 * 0b0..LLWU_P16 input was not a wakeup source 6791 * 0b1..LLWU_P16 input was a wakeup source 6792 */ 6793 #define LLWU_PF3_WUF16(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PF3_WUF16_SHIFT)) & LLWU_PF3_WUF16_MASK) 6794 #define LLWU_PF3_WUF17_MASK (0x2U) 6795 #define LLWU_PF3_WUF17_SHIFT (1U) 6796 /*! WUF17 - Wakeup Flag For LLWU_P17 6797 * 0b0..LLWU_P17 input was not a wakeup source 6798 * 0b1..LLWU_P17 input was a wakeup source 6799 */ 6800 #define LLWU_PF3_WUF17(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PF3_WUF17_SHIFT)) & LLWU_PF3_WUF17_MASK) 6801 #define LLWU_PF3_WUF18_MASK (0x4U) 6802 #define LLWU_PF3_WUF18_SHIFT (2U) 6803 /*! WUF18 - Wakeup Flag For LLWU_P18 6804 * 0b0..LLWU_P18 input was not a wakeup source 6805 * 0b1..LLWU_P18 input was a wakeup source 6806 */ 6807 #define LLWU_PF3_WUF18(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PF3_WUF18_SHIFT)) & LLWU_PF3_WUF18_MASK) 6808 #define LLWU_PF3_WUF19_MASK (0x8U) 6809 #define LLWU_PF3_WUF19_SHIFT (3U) 6810 /*! WUF19 - Wakeup Flag For LLWU_P19 6811 * 0b0..LLWU_P19 input was not a wakeup source 6812 * 0b1..LLWU_P19 input was a wakeup source 6813 */ 6814 #define LLWU_PF3_WUF19(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PF3_WUF19_SHIFT)) & LLWU_PF3_WUF19_MASK) 6815 #define LLWU_PF3_WUF20_MASK (0x10U) 6816 #define LLWU_PF3_WUF20_SHIFT (4U) 6817 /*! WUF20 - Wakeup Flag For LLWU_P20 6818 * 0b0..LLWU_P20 input was not a wakeup source 6819 * 0b1..LLWU_P20 input was a wakeup source 6820 */ 6821 #define LLWU_PF3_WUF20(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PF3_WUF20_SHIFT)) & LLWU_PF3_WUF20_MASK) 6822 #define LLWU_PF3_WUF21_MASK (0x20U) 6823 #define LLWU_PF3_WUF21_SHIFT (5U) 6824 /*! WUF21 - Wakeup Flag For LLWU_P21 6825 * 0b0..LLWU_P21 input was not a wakeup source 6826 * 0b1..LLWU_P21 input was a wakeup source 6827 */ 6828 #define LLWU_PF3_WUF21(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PF3_WUF21_SHIFT)) & LLWU_PF3_WUF21_MASK) 6829 #define LLWU_PF3_WUF22_MASK (0x40U) 6830 #define LLWU_PF3_WUF22_SHIFT (6U) 6831 /*! WUF22 - Wakeup Flag For LLWU_P22 6832 * 0b0..LLWU_P22 input was not a wakeup source 6833 * 0b1..LLWU_P22 input was a wakeup source 6834 */ 6835 #define LLWU_PF3_WUF22(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PF3_WUF22_SHIFT)) & LLWU_PF3_WUF22_MASK) 6836 #define LLWU_PF3_WUF23_MASK (0x80U) 6837 #define LLWU_PF3_WUF23_SHIFT (7U) 6838 /*! WUF23 - Wakeup Flag For LLWU_P23 6839 * 0b0..LLWU_P23 input was not a wakeup source 6840 * 0b1..LLWU_P23 input was a wakeup source 6841 */ 6842 #define LLWU_PF3_WUF23(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PF3_WUF23_SHIFT)) & LLWU_PF3_WUF23_MASK) 6843 /*! @} */ 6844 6845 /*! @name PF4 - LLWU Pin Flag 4 register */ 6846 /*! @{ */ 6847 #define LLWU_PF4_WUF24_MASK (0x1U) 6848 #define LLWU_PF4_WUF24_SHIFT (0U) 6849 /*! WUF24 - Wakeup Flag For LLWU_P24 6850 * 0b0..LLWU_P24 input was not a wakeup source 6851 * 0b1..LLWU_P24 input was a wakeup source 6852 */ 6853 #define LLWU_PF4_WUF24(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PF4_WUF24_SHIFT)) & LLWU_PF4_WUF24_MASK) 6854 #define LLWU_PF4_WUF25_MASK (0x2U) 6855 #define LLWU_PF4_WUF25_SHIFT (1U) 6856 /*! WUF25 - Wakeup Flag For LLWU_P25 6857 * 0b0..LLWU_P25 input was not a wakeup source 6858 * 0b1..LLWU_P25 input was a wakeup source 6859 */ 6860 #define LLWU_PF4_WUF25(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PF4_WUF25_SHIFT)) & LLWU_PF4_WUF25_MASK) 6861 #define LLWU_PF4_WUF26_MASK (0x4U) 6862 #define LLWU_PF4_WUF26_SHIFT (2U) 6863 /*! WUF26 - Wakeup Flag For LLWU_P26 6864 * 0b0..LLWU_P26 input was not a wakeup source 6865 * 0b1..LLWU_P26 input was a wakeup source 6866 */ 6867 #define LLWU_PF4_WUF26(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PF4_WUF26_SHIFT)) & LLWU_PF4_WUF26_MASK) 6868 #define LLWU_PF4_WUF27_MASK (0x8U) 6869 #define LLWU_PF4_WUF27_SHIFT (3U) 6870 /*! WUF27 - Wakeup Flag For LLWU_P27 6871 * 0b0..LLWU_P27 input was not a wakeup source 6872 * 0b1..LLWU_P27 input was a wakeup source 6873 */ 6874 #define LLWU_PF4_WUF27(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PF4_WUF27_SHIFT)) & LLWU_PF4_WUF27_MASK) 6875 #define LLWU_PF4_WUF28_MASK (0x10U) 6876 #define LLWU_PF4_WUF28_SHIFT (4U) 6877 /*! WUF28 - Wakeup Flag For LLWU_P28 6878 * 0b0..LLWU_P28 input was not a wakeup source 6879 * 0b1..LLWU_P28 input was a wakeup source 6880 */ 6881 #define LLWU_PF4_WUF28(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PF4_WUF28_SHIFT)) & LLWU_PF4_WUF28_MASK) 6882 #define LLWU_PF4_WUF29_MASK (0x20U) 6883 #define LLWU_PF4_WUF29_SHIFT (5U) 6884 /*! WUF29 - Wakeup Flag For LLWU_P29 6885 * 0b0..LLWU_P29 input was not a wakeup source 6886 * 0b1..LLWU_P29 input was a wakeup source 6887 */ 6888 #define LLWU_PF4_WUF29(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PF4_WUF29_SHIFT)) & LLWU_PF4_WUF29_MASK) 6889 #define LLWU_PF4_WUF30_MASK (0x40U) 6890 #define LLWU_PF4_WUF30_SHIFT (6U) 6891 /*! WUF30 - Wakeup Flag For LLWU_P30 6892 * 0b0..LLWU_P30 input was not a wakeup source 6893 * 0b1..LLWU_P30 input was a wakeup source 6894 */ 6895 #define LLWU_PF4_WUF30(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PF4_WUF30_SHIFT)) & LLWU_PF4_WUF30_MASK) 6896 #define LLWU_PF4_WUF31_MASK (0x80U) 6897 #define LLWU_PF4_WUF31_SHIFT (7U) 6898 /*! WUF31 - Wakeup Flag For LLWU_P31 6899 * 0b0..LLWU_P31 input was not a wakeup source 6900 * 0b1..LLWU_P31 input was a wakeup source 6901 */ 6902 #define LLWU_PF4_WUF31(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PF4_WUF31_SHIFT)) & LLWU_PF4_WUF31_MASK) 6903 /*! @} */ 6904 6905 /*! @name MF5 - LLWU Module Flag 5 register */ 6906 /*! @{ */ 6907 #define LLWU_MF5_MWUF0_MASK (0x1U) 6908 #define LLWU_MF5_MWUF0_SHIFT (0U) 6909 /*! MWUF0 - Wakeup flag For module 0 6910 * 0b0..Module 0 input was not a wakeup source 6911 * 0b1..Module 0 input was a wakeup source 6912 */ 6913 #define LLWU_MF5_MWUF0(x) (((uint8_t)(((uint8_t)(x)) << LLWU_MF5_MWUF0_SHIFT)) & LLWU_MF5_MWUF0_MASK) 6914 #define LLWU_MF5_MWUF1_MASK (0x2U) 6915 #define LLWU_MF5_MWUF1_SHIFT (1U) 6916 /*! MWUF1 - Wakeup flag For module 1 6917 * 0b0..Module 1 input was not a wakeup source 6918 * 0b1..Module 1 input was a wakeup source 6919 */ 6920 #define LLWU_MF5_MWUF1(x) (((uint8_t)(((uint8_t)(x)) << LLWU_MF5_MWUF1_SHIFT)) & LLWU_MF5_MWUF1_MASK) 6921 #define LLWU_MF5_MWUF2_MASK (0x4U) 6922 #define LLWU_MF5_MWUF2_SHIFT (2U) 6923 /*! MWUF2 - Wakeup flag For module 2 6924 * 0b0..Module 2 input was not a wakeup source 6925 * 0b1..Module 2 input was a wakeup source 6926 */ 6927 #define LLWU_MF5_MWUF2(x) (((uint8_t)(((uint8_t)(x)) << LLWU_MF5_MWUF2_SHIFT)) & LLWU_MF5_MWUF2_MASK) 6928 #define LLWU_MF5_MWUF3_MASK (0x8U) 6929 #define LLWU_MF5_MWUF3_SHIFT (3U) 6930 /*! MWUF3 - Wakeup flag For module 3 6931 * 0b0..Module 3 input was not a wakeup source 6932 * 0b1..Module 3 input was a wakeup source 6933 */ 6934 #define LLWU_MF5_MWUF3(x) (((uint8_t)(((uint8_t)(x)) << LLWU_MF5_MWUF3_SHIFT)) & LLWU_MF5_MWUF3_MASK) 6935 #define LLWU_MF5_MWUF4_MASK (0x10U) 6936 #define LLWU_MF5_MWUF4_SHIFT (4U) 6937 /*! MWUF4 - Wakeup flag For module 4 6938 * 0b0..Module 4 input was not a wakeup source 6939 * 0b1..Module 4 input was a wakeup source 6940 */ 6941 #define LLWU_MF5_MWUF4(x) (((uint8_t)(((uint8_t)(x)) << LLWU_MF5_MWUF4_SHIFT)) & LLWU_MF5_MWUF4_MASK) 6942 #define LLWU_MF5_MWUF5_MASK (0x20U) 6943 #define LLWU_MF5_MWUF5_SHIFT (5U) 6944 /*! MWUF5 - Wakeup flag For module 5 6945 * 0b0..Module 5 input was not a wakeup source 6946 * 0b1..Module 5 input was a wakeup source 6947 */ 6948 #define LLWU_MF5_MWUF5(x) (((uint8_t)(((uint8_t)(x)) << LLWU_MF5_MWUF5_SHIFT)) & LLWU_MF5_MWUF5_MASK) 6949 #define LLWU_MF5_MWUF6_MASK (0x40U) 6950 #define LLWU_MF5_MWUF6_SHIFT (6U) 6951 /*! MWUF6 - Wakeup flag For module 6 6952 * 0b0..Module 6 input was not a wakeup source 6953 * 0b1..Module 6 input was a wakeup source 6954 */ 6955 #define LLWU_MF5_MWUF6(x) (((uint8_t)(((uint8_t)(x)) << LLWU_MF5_MWUF6_SHIFT)) & LLWU_MF5_MWUF6_MASK) 6956 #define LLWU_MF5_MWUF7_MASK (0x80U) 6957 #define LLWU_MF5_MWUF7_SHIFT (7U) 6958 /*! MWUF7 - Wakeup flag For module 7 6959 * 0b0..Module 7 input was not a wakeup source 6960 * 0b1..Module 7 input was a wakeup source 6961 */ 6962 #define LLWU_MF5_MWUF7(x) (((uint8_t)(((uint8_t)(x)) << LLWU_MF5_MWUF7_SHIFT)) & LLWU_MF5_MWUF7_MASK) 6963 /*! @} */ 6964 6965 /*! @name FILT1 - LLWU Pin Filter 1 register */ 6966 /*! @{ */ 6967 #define LLWU_FILT1_FILTSEL_MASK (0x1FU) 6968 #define LLWU_FILT1_FILTSEL_SHIFT (0U) 6969 /*! FILTSEL - Filter Pin Select 6970 * 0b00000..Select LLWU_P0 for filter 6971 * 0b11111..Select LLWU_P31 for filter 6972 */ 6973 #define LLWU_FILT1_FILTSEL(x) (((uint8_t)(((uint8_t)(x)) << LLWU_FILT1_FILTSEL_SHIFT)) & LLWU_FILT1_FILTSEL_MASK) 6974 #define LLWU_FILT1_FILTE_MASK (0x60U) 6975 #define LLWU_FILT1_FILTE_SHIFT (5U) 6976 /*! FILTE - Digital Filter On External Pin 6977 * 0b00..Filter disabled 6978 * 0b01..Filter posedge detect enabled 6979 * 0b10..Filter negedge detect enabled 6980 * 0b11..Filter any edge detect enabled 6981 */ 6982 #define LLWU_FILT1_FILTE(x) (((uint8_t)(((uint8_t)(x)) << LLWU_FILT1_FILTE_SHIFT)) & LLWU_FILT1_FILTE_MASK) 6983 #define LLWU_FILT1_FILTF_MASK (0x80U) 6984 #define LLWU_FILT1_FILTF_SHIFT (7U) 6985 /*! FILTF - Filter Detect Flag 6986 * 0b0..Pin Filter 1 was not a wakeup source 6987 * 0b1..Pin Filter 1 was a wakeup source 6988 */ 6989 #define LLWU_FILT1_FILTF(x) (((uint8_t)(((uint8_t)(x)) << LLWU_FILT1_FILTF_SHIFT)) & LLWU_FILT1_FILTF_MASK) 6990 /*! @} */ 6991 6992 /*! @name FILT2 - LLWU Pin Filter 2 register */ 6993 /*! @{ */ 6994 #define LLWU_FILT2_FILTSEL_MASK (0x1FU) 6995 #define LLWU_FILT2_FILTSEL_SHIFT (0U) 6996 /*! FILTSEL - Filter Pin Select 6997 * 0b00000..Select LLWU_P0 for filter 6998 * 0b11111..Select LLWU_P31 for filter 6999 */ 7000 #define LLWU_FILT2_FILTSEL(x) (((uint8_t)(((uint8_t)(x)) << LLWU_FILT2_FILTSEL_SHIFT)) & LLWU_FILT2_FILTSEL_MASK) 7001 #define LLWU_FILT2_FILTE_MASK (0x60U) 7002 #define LLWU_FILT2_FILTE_SHIFT (5U) 7003 /*! FILTE - Digital Filter On External Pin 7004 * 0b00..Filter disabled 7005 * 0b01..Filter posedge detect enabled 7006 * 0b10..Filter negedge detect enabled 7007 * 0b11..Filter any edge detect enabled 7008 */ 7009 #define LLWU_FILT2_FILTE(x) (((uint8_t)(((uint8_t)(x)) << LLWU_FILT2_FILTE_SHIFT)) & LLWU_FILT2_FILTE_MASK) 7010 #define LLWU_FILT2_FILTF_MASK (0x80U) 7011 #define LLWU_FILT2_FILTF_SHIFT (7U) 7012 /*! FILTF - Filter Detect Flag 7013 * 0b0..Pin Filter 2 was not a wakeup source 7014 * 0b1..Pin Filter 2 was a wakeup source 7015 */ 7016 #define LLWU_FILT2_FILTF(x) (((uint8_t)(((uint8_t)(x)) << LLWU_FILT2_FILTF_SHIFT)) & LLWU_FILT2_FILTF_MASK) 7017 /*! @} */ 7018 7019 7020 /*! 7021 * @} 7022 */ /* end of group LLWU_Register_Masks */ 7023 7024 7025 /* LLWU - Peripheral instance base addresses */ 7026 /** Peripheral LLWU base address */ 7027 #define LLWU_BASE (0x4007C000u) 7028 /** Peripheral LLWU base pointer */ 7029 #define LLWU ((LLWU_Type *)LLWU_BASE) 7030 /** Array initializer of LLWU peripheral base addresses */ 7031 #define LLWU_BASE_ADDRS { LLWU_BASE } 7032 /** Array initializer of LLWU peripheral base pointers */ 7033 #define LLWU_BASE_PTRS { LLWU } 7034 /** Interrupt vectors for the LLWU peripheral type */ 7035 #define LLWU_IRQS { LLWU_IRQn } 7036 7037 /*! 7038 * @} 7039 */ /* end of group LLWU_Peripheral_Access_Layer */ 7040 7041 7042 /* ---------------------------------------------------------------------------- 7043 -- LPTMR Peripheral Access Layer 7044 ---------------------------------------------------------------------------- */ 7045 7046 /*! 7047 * @addtogroup LPTMR_Peripheral_Access_Layer LPTMR Peripheral Access Layer 7048 * @{ 7049 */ 7050 7051 /** LPTMR - Register Layout Typedef */ 7052 typedef struct { 7053 __IO uint32_t CSR; /**< Low Power Timer Control Status Register, offset: 0x0 */ 7054 __IO uint32_t PSR; /**< Low Power Timer Prescale Register, offset: 0x4 */ 7055 __IO uint32_t CMR; /**< Low Power Timer Compare Register, offset: 0x8 */ 7056 __IO uint32_t CNR; /**< Low Power Timer Counter Register, offset: 0xC */ 7057 } LPTMR_Type; 7058 7059 /* ---------------------------------------------------------------------------- 7060 -- LPTMR Register Masks 7061 ---------------------------------------------------------------------------- */ 7062 7063 /*! 7064 * @addtogroup LPTMR_Register_Masks LPTMR Register Masks 7065 * @{ 7066 */ 7067 7068 /*! @name CSR - Low Power Timer Control Status Register */ 7069 /*! @{ */ 7070 #define LPTMR_CSR_TEN_MASK (0x1U) 7071 #define LPTMR_CSR_TEN_SHIFT (0U) 7072 /*! TEN - Timer Enable 7073 * 0b0..LPTMR is disabled and internal logic is reset. 7074 * 0b1..LPTMR is enabled. 7075 */ 7076 #define LPTMR_CSR_TEN(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TEN_SHIFT)) & LPTMR_CSR_TEN_MASK) 7077 #define LPTMR_CSR_TMS_MASK (0x2U) 7078 #define LPTMR_CSR_TMS_SHIFT (1U) 7079 /*! TMS - Timer Mode Select 7080 * 0b0..Time Counter mode. 7081 * 0b1..Pulse Counter mode. 7082 */ 7083 #define LPTMR_CSR_TMS(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TMS_SHIFT)) & LPTMR_CSR_TMS_MASK) 7084 #define LPTMR_CSR_TFC_MASK (0x4U) 7085 #define LPTMR_CSR_TFC_SHIFT (2U) 7086 /*! TFC - Timer Free-Running Counter 7087 * 0b0..CNR is reset whenever TCF is set. 7088 * 0b1..CNR is reset on overflow. 7089 */ 7090 #define LPTMR_CSR_TFC(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TFC_SHIFT)) & LPTMR_CSR_TFC_MASK) 7091 #define LPTMR_CSR_TPP_MASK (0x8U) 7092 #define LPTMR_CSR_TPP_SHIFT (3U) 7093 /*! TPP - Timer Pin Polarity 7094 * 0b0..Pulse Counter input source is active-high, and the CNR will increment on the rising-edge. 7095 * 0b1..Pulse Counter input source is active-low, and the CNR will increment on the falling-edge. 7096 */ 7097 #define LPTMR_CSR_TPP(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TPP_SHIFT)) & LPTMR_CSR_TPP_MASK) 7098 #define LPTMR_CSR_TPS_MASK (0x30U) 7099 #define LPTMR_CSR_TPS_SHIFT (4U) 7100 /*! TPS - Timer Pin Select 7101 * 0b00..Pulse counter input 0 is selected. 7102 * 0b01..Pulse counter input 1 is selected. 7103 * 0b10..Pulse counter input 2 is selected. 7104 * 0b11..Pulse counter input 3 is selected. 7105 */ 7106 #define LPTMR_CSR_TPS(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TPS_SHIFT)) & LPTMR_CSR_TPS_MASK) 7107 #define LPTMR_CSR_TIE_MASK (0x40U) 7108 #define LPTMR_CSR_TIE_SHIFT (6U) 7109 /*! TIE - Timer Interrupt Enable 7110 * 0b0..Timer interrupt disabled. 7111 * 0b1..Timer interrupt enabled. 7112 */ 7113 #define LPTMR_CSR_TIE(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TIE_SHIFT)) & LPTMR_CSR_TIE_MASK) 7114 #define LPTMR_CSR_TCF_MASK (0x80U) 7115 #define LPTMR_CSR_TCF_SHIFT (7U) 7116 /*! TCF - Timer Compare Flag 7117 * 0b0..The value of CNR is not equal to CMR and increments. 7118 * 0b1..The value of CNR is equal to CMR and increments. 7119 */ 7120 #define LPTMR_CSR_TCF(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TCF_SHIFT)) & LPTMR_CSR_TCF_MASK) 7121 /*! @} */ 7122 7123 /*! @name PSR - Low Power Timer Prescale Register */ 7124 /*! @{ */ 7125 #define LPTMR_PSR_PCS_MASK (0x3U) 7126 #define LPTMR_PSR_PCS_SHIFT (0U) 7127 /*! PCS - Prescaler Clock Select 7128 * 0b00..Prescaler/glitch filter clock 0 selected. 7129 * 0b01..Prescaler/glitch filter clock 1 selected. 7130 * 0b10..Prescaler/glitch filter clock 2 selected. 7131 * 0b11..Prescaler/glitch filter clock 3 selected. 7132 */ 7133 #define LPTMR_PSR_PCS(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_PSR_PCS_SHIFT)) & LPTMR_PSR_PCS_MASK) 7134 #define LPTMR_PSR_PBYP_MASK (0x4U) 7135 #define LPTMR_PSR_PBYP_SHIFT (2U) 7136 /*! PBYP - Prescaler Bypass 7137 * 0b0..Prescaler/glitch filter is enabled. 7138 * 0b1..Prescaler/glitch filter is bypassed. 7139 */ 7140 #define LPTMR_PSR_PBYP(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_PSR_PBYP_SHIFT)) & LPTMR_PSR_PBYP_MASK) 7141 #define LPTMR_PSR_PRESCALE_MASK (0x78U) 7142 #define LPTMR_PSR_PRESCALE_SHIFT (3U) 7143 /*! PRESCALE - Prescale Value 7144 * 0b0000..Prescaler divides the prescaler clock by 2; glitch filter does not support this configuration. 7145 * 0b0001..Prescaler divides the prescaler clock by 4; glitch filter recognizes change on input pin after 2 rising clock edges. 7146 * 0b0010..Prescaler divides the prescaler clock by 8; glitch filter recognizes change on input pin after 4 rising clock edges. 7147 * 0b0011..Prescaler divides the prescaler clock by 16; glitch filter recognizes change on input pin after 8 rising clock edges. 7148 * 0b0100..Prescaler divides the prescaler clock by 32; glitch filter recognizes change on input pin after 16 rising clock edges. 7149 * 0b0101..Prescaler divides the prescaler clock by 64; glitch filter recognizes change on input pin after 32 rising clock edges. 7150 * 0b0110..Prescaler divides the prescaler clock by 128; glitch filter recognizes change on input pin after 64 rising clock edges. 7151 * 0b0111..Prescaler divides the prescaler clock by 256; glitch filter recognizes change on input pin after 128 rising clock edges. 7152 * 0b1000..Prescaler divides the prescaler clock by 512; glitch filter recognizes change on input pin after 256 rising clock edges. 7153 * 0b1001..Prescaler divides the prescaler clock by 1024; glitch filter recognizes change on input pin after 512 rising clock edges. 7154 * 0b1010..Prescaler divides the prescaler clock by 2048; glitch filter recognizes change on input pin after 1024 rising clock edges. 7155 * 0b1011..Prescaler divides the prescaler clock by 4096; glitch filter recognizes change on input pin after 2048 rising clock edges. 7156 * 0b1100..Prescaler divides the prescaler clock by 8192; glitch filter recognizes change on input pin after 4096 rising clock edges. 7157 * 0b1101..Prescaler divides the prescaler clock by 16,384; glitch filter recognizes change on input pin after 8192 rising clock edges. 7158 * 0b1110..Prescaler divides the prescaler clock by 32,768; glitch filter recognizes change on input pin after 16,384 rising clock edges. 7159 * 0b1111..Prescaler divides the prescaler clock by 65,536; glitch filter recognizes change on input pin after 32,768 rising clock edges. 7160 */ 7161 #define LPTMR_PSR_PRESCALE(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_PSR_PRESCALE_SHIFT)) & LPTMR_PSR_PRESCALE_MASK) 7162 /*! @} */ 7163 7164 /*! @name CMR - Low Power Timer Compare Register */ 7165 /*! @{ */ 7166 #define LPTMR_CMR_COMPARE_MASK (0xFFFFU) 7167 #define LPTMR_CMR_COMPARE_SHIFT (0U) 7168 #define LPTMR_CMR_COMPARE(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CMR_COMPARE_SHIFT)) & LPTMR_CMR_COMPARE_MASK) 7169 /*! @} */ 7170 7171 /*! @name CNR - Low Power Timer Counter Register */ 7172 /*! @{ */ 7173 #define LPTMR_CNR_COUNTER_MASK (0xFFFFU) 7174 #define LPTMR_CNR_COUNTER_SHIFT (0U) 7175 #define LPTMR_CNR_COUNTER(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CNR_COUNTER_SHIFT)) & LPTMR_CNR_COUNTER_MASK) 7176 /*! @} */ 7177 7178 7179 /*! 7180 * @} 7181 */ /* end of group LPTMR_Register_Masks */ 7182 7183 7184 /* LPTMR - Peripheral instance base addresses */ 7185 /** Peripheral LPTMR0 base address */ 7186 #define LPTMR0_BASE (0x40040000u) 7187 /** Peripheral LPTMR0 base pointer */ 7188 #define LPTMR0 ((LPTMR_Type *)LPTMR0_BASE) 7189 /** Array initializer of LPTMR peripheral base addresses */ 7190 #define LPTMR_BASE_ADDRS { LPTMR0_BASE } 7191 /** Array initializer of LPTMR peripheral base pointers */ 7192 #define LPTMR_BASE_PTRS { LPTMR0 } 7193 /** Interrupt vectors for the LPTMR peripheral type */ 7194 #define LPTMR_IRQS { LPTMR0_IRQn } 7195 7196 /*! 7197 * @} 7198 */ /* end of group LPTMR_Peripheral_Access_Layer */ 7199 7200 7201 /* ---------------------------------------------------------------------------- 7202 -- MCG Peripheral Access Layer 7203 ---------------------------------------------------------------------------- */ 7204 7205 /*! 7206 * @addtogroup MCG_Peripheral_Access_Layer MCG Peripheral Access Layer 7207 * @{ 7208 */ 7209 7210 /** MCG - Register Layout Typedef */ 7211 typedef struct { 7212 __IO uint8_t C1; /**< MCG Control 1 Register, offset: 0x0 */ 7213 __IO uint8_t C2; /**< MCG Control 2 Register, offset: 0x1 */ 7214 __IO uint8_t C3; /**< MCG Control 3 Register, offset: 0x2 */ 7215 __IO uint8_t C4; /**< MCG Control 4 Register, offset: 0x3 */ 7216 uint8_t RESERVED_0[1]; 7217 __IO uint8_t C6; /**< MCG Control 6 Register, offset: 0x5 */ 7218 __I uint8_t S; /**< MCG Status Register, offset: 0x6 */ 7219 uint8_t RESERVED_1[1]; 7220 __IO uint8_t SC; /**< MCG Status and Control Register, offset: 0x8 */ 7221 uint8_t RESERVED_2[1]; 7222 __IO uint8_t ATCVH; /**< MCG Auto Trim Compare Value High Register, offset: 0xA */ 7223 __IO uint8_t ATCVL; /**< MCG Auto Trim Compare Value Low Register, offset: 0xB */ 7224 } MCG_Type; 7225 7226 /* ---------------------------------------------------------------------------- 7227 -- MCG Register Masks 7228 ---------------------------------------------------------------------------- */ 7229 7230 /*! 7231 * @addtogroup MCG_Register_Masks MCG Register Masks 7232 * @{ 7233 */ 7234 7235 /*! @name C1 - MCG Control 1 Register */ 7236 /*! @{ */ 7237 #define MCG_C1_IREFSTEN_MASK (0x1U) 7238 #define MCG_C1_IREFSTEN_SHIFT (0U) 7239 /*! IREFSTEN - Internal Reference Stop Enable 7240 * 0b0..Internal reference clock is disabled in Stop mode. 7241 * 0b1..Internal reference clock is enabled in Stop mode if IRCLKEN is set or if MCG is in FEI, FBI, or BLPI modes before entering Stop mode. 7242 */ 7243 #define MCG_C1_IREFSTEN(x) (((uint8_t)(((uint8_t)(x)) << MCG_C1_IREFSTEN_SHIFT)) & MCG_C1_IREFSTEN_MASK) 7244 #define MCG_C1_IRCLKEN_MASK (0x2U) 7245 #define MCG_C1_IRCLKEN_SHIFT (1U) 7246 /*! IRCLKEN - Internal Reference Clock Enable 7247 * 0b0..MCGIRCLK inactive. 7248 * 0b1..MCGIRCLK active. 7249 */ 7250 #define MCG_C1_IRCLKEN(x) (((uint8_t)(((uint8_t)(x)) << MCG_C1_IRCLKEN_SHIFT)) & MCG_C1_IRCLKEN_MASK) 7251 #define MCG_C1_IREFS_MASK (0x4U) 7252 #define MCG_C1_IREFS_SHIFT (2U) 7253 /*! IREFS - Internal Reference Select 7254 * 0b0..External reference clock is selected. 7255 * 0b1..The slow internal reference clock is selected. 7256 */ 7257 #define MCG_C1_IREFS(x) (((uint8_t)(((uint8_t)(x)) << MCG_C1_IREFS_SHIFT)) & MCG_C1_IREFS_MASK) 7258 #define MCG_C1_FRDIV_MASK (0x38U) 7259 #define MCG_C1_FRDIV_SHIFT (3U) 7260 /*! FRDIV - FLL External Reference Divider 7261 * 0b000..If RANGE = 0 , Divide Factor is 1; for all other RANGE values, Divide Factor is 32. 7262 * 0b001..If RANGE = 0 , Divide Factor is 2; for all other RANGE values, Divide Factor is 64. 7263 * 0b010..If RANGE = 0 , Divide Factor is 4; for all other RANGE values, Divide Factor is 128. 7264 * 0b011..If RANGE = 0 , Divide Factor is 8; for all other RANGE values, Divide Factor is 256. 7265 * 0b100..If RANGE = 0 , Divide Factor is 16; for all other RANGE values, Divide Factor is 512. 7266 * 0b101..If RANGE = 0 , Divide Factor is 32; for all other RANGE values, Divide Factor is 1024. 7267 * 0b110..If RANGE = 0 , Divide Factor is 64; for all other RANGE values, Divide Factor is 1280 . 7268 * 0b111..If RANGE = 0 , Divide Factor is 128; for all other RANGE values, Divide Factor is 1536 . 7269 */ 7270 #define MCG_C1_FRDIV(x) (((uint8_t)(((uint8_t)(x)) << MCG_C1_FRDIV_SHIFT)) & MCG_C1_FRDIV_MASK) 7271 #define MCG_C1_CLKS_MASK (0xC0U) 7272 #define MCG_C1_CLKS_SHIFT (6U) 7273 /*! CLKS - Clock Source Select 7274 * 0b00..Encoding 0 - Output of FLL is selected. 7275 * 0b01..Encoding 1 - Internal reference clock is selected. 7276 * 0b10..Encoding 2 - External reference clock is selected. 7277 * 0b11..Encoding 3 - Reserved. 7278 */ 7279 #define MCG_C1_CLKS(x) (((uint8_t)(((uint8_t)(x)) << MCG_C1_CLKS_SHIFT)) & MCG_C1_CLKS_MASK) 7280 /*! @} */ 7281 7282 /*! @name C2 - MCG Control 2 Register */ 7283 /*! @{ */ 7284 #define MCG_C2_IRCS_MASK (0x1U) 7285 #define MCG_C2_IRCS_SHIFT (0U) 7286 /*! IRCS - Internal Reference Clock Select 7287 * 0b0..Slow internal reference clock selected. 7288 * 0b1..Fast internal reference clock selected. 7289 */ 7290 #define MCG_C2_IRCS(x) (((uint8_t)(((uint8_t)(x)) << MCG_C2_IRCS_SHIFT)) & MCG_C2_IRCS_MASK) 7291 #define MCG_C2_LP_MASK (0x2U) 7292 #define MCG_C2_LP_SHIFT (1U) 7293 /*! LP - Low Power Select 7294 * 0b0..FLL is not disabled in bypass modes. 7295 * 0b1..FLL is disabled in bypass modes (lower power) 7296 */ 7297 #define MCG_C2_LP(x) (((uint8_t)(((uint8_t)(x)) << MCG_C2_LP_SHIFT)) & MCG_C2_LP_MASK) 7298 #define MCG_C2_EREFS_MASK (0x4U) 7299 #define MCG_C2_EREFS_SHIFT (2U) 7300 /*! EREFS - External Reference Select 7301 * 0b0..External reference clock requested. 7302 * 0b1..Oscillator requested. 7303 */ 7304 #define MCG_C2_EREFS(x) (((uint8_t)(((uint8_t)(x)) << MCG_C2_EREFS_SHIFT)) & MCG_C2_EREFS_MASK) 7305 #define MCG_C2_HGO_MASK (0x8U) 7306 #define MCG_C2_HGO_SHIFT (3U) 7307 /*! HGO - High Gain Oscillator Select 7308 * 0b0..Configure crystal oscillator for low-power operation. 7309 * 0b1..Configure crystal oscillator for high-gain operation. 7310 */ 7311 #define MCG_C2_HGO(x) (((uint8_t)(((uint8_t)(x)) << MCG_C2_HGO_SHIFT)) & MCG_C2_HGO_MASK) 7312 #define MCG_C2_RANGE_MASK (0x30U) 7313 #define MCG_C2_RANGE_SHIFT (4U) 7314 /*! RANGE - Frequency Range Select 7315 * 0b00..Encoding 0 - Low frequency range selected for the crystal oscillator . 7316 * 0b01..Encoding 1 - High frequency range selected for the crystal oscillator . 7317 * 0b1x..Encoding 2 - Very high frequency range selected for the crystal oscillator . 7318 */ 7319 #define MCG_C2_RANGE(x) (((uint8_t)(((uint8_t)(x)) << MCG_C2_RANGE_SHIFT)) & MCG_C2_RANGE_MASK) 7320 #define MCG_C2_FCFTRIM_MASK (0x40U) 7321 #define MCG_C2_FCFTRIM_SHIFT (6U) 7322 #define MCG_C2_FCFTRIM(x) (((uint8_t)(((uint8_t)(x)) << MCG_C2_FCFTRIM_SHIFT)) & MCG_C2_FCFTRIM_MASK) 7323 #define MCG_C2_LOCRE0_MASK (0x80U) 7324 #define MCG_C2_LOCRE0_SHIFT (7U) 7325 /*! LOCRE0 - Loss of Clock Reset Enable 7326 * 0b0..Interrupt request is generated on a loss of OSC0 external reference clock. 7327 * 0b1..Generate a reset request on a loss of OSC0 external reference clock. 7328 */ 7329 #define MCG_C2_LOCRE0(x) (((uint8_t)(((uint8_t)(x)) << MCG_C2_LOCRE0_SHIFT)) & MCG_C2_LOCRE0_MASK) 7330 /*! @} */ 7331 7332 /*! @name C3 - MCG Control 3 Register */ 7333 /*! @{ */ 7334 #define MCG_C3_SCTRIM_MASK (0xFFU) 7335 #define MCG_C3_SCTRIM_SHIFT (0U) 7336 #define MCG_C3_SCTRIM(x) (((uint8_t)(((uint8_t)(x)) << MCG_C3_SCTRIM_SHIFT)) & MCG_C3_SCTRIM_MASK) 7337 /*! @} */ 7338 7339 /*! @name C4 - MCG Control 4 Register */ 7340 /*! @{ */ 7341 #define MCG_C4_SCFTRIM_MASK (0x1U) 7342 #define MCG_C4_SCFTRIM_SHIFT (0U) 7343 #define MCG_C4_SCFTRIM(x) (((uint8_t)(((uint8_t)(x)) << MCG_C4_SCFTRIM_SHIFT)) & MCG_C4_SCFTRIM_MASK) 7344 #define MCG_C4_FCTRIM_MASK (0x1EU) 7345 #define MCG_C4_FCTRIM_SHIFT (1U) 7346 #define MCG_C4_FCTRIM(x) (((uint8_t)(((uint8_t)(x)) << MCG_C4_FCTRIM_SHIFT)) & MCG_C4_FCTRIM_MASK) 7347 #define MCG_C4_DRST_DRS_MASK (0x60U) 7348 #define MCG_C4_DRST_DRS_SHIFT (5U) 7349 /*! DRST_DRS - DCO Range Select 7350 * 0b00..Encoding 0 - Low range (reset default). 7351 * 0b01..Encoding 1 - Mid range. 7352 * 0b10..Encoding 2 - Mid-high range. 7353 * 0b11..Encoding 3 - High range. 7354 */ 7355 #define MCG_C4_DRST_DRS(x) (((uint8_t)(((uint8_t)(x)) << MCG_C4_DRST_DRS_SHIFT)) & MCG_C4_DRST_DRS_MASK) 7356 #define MCG_C4_DMX32_MASK (0x80U) 7357 #define MCG_C4_DMX32_SHIFT (7U) 7358 /*! DMX32 - DCO Maximum Frequency with 32.768 kHz Reference 7359 * 0b0..DCO has a default range of 25%. 7360 * 0b1..DCO is fine-tuned for maximum frequency with 32.768 kHz reference. 7361 */ 7362 #define MCG_C4_DMX32(x) (((uint8_t)(((uint8_t)(x)) << MCG_C4_DMX32_SHIFT)) & MCG_C4_DMX32_MASK) 7363 /*! @} */ 7364 7365 /*! @name C6 - MCG Control 6 Register */ 7366 /*! @{ */ 7367 #define MCG_C6_CME_MASK (0x20U) 7368 #define MCG_C6_CME_SHIFT (5U) 7369 /*! CME - Clock Monitor Enable 7370 * 0b0..External clock monitor is disabled. 7371 * 0b1..Generate a reset request on loss of external clock. 7372 */ 7373 #define MCG_C6_CME(x) (((uint8_t)(((uint8_t)(x)) << MCG_C6_CME_SHIFT)) & MCG_C6_CME_MASK) 7374 /*! @} */ 7375 7376 /*! @name S - MCG Status Register */ 7377 /*! @{ */ 7378 #define MCG_S_IRCST_MASK (0x1U) 7379 #define MCG_S_IRCST_SHIFT (0U) 7380 /*! IRCST - Internal Reference Clock Status 7381 * 0b0..Source of internal reference clock is the slow clock (32 kHz IRC). 7382 * 0b1..Source of internal reference clock is the fast clock (4 MHz IRC). 7383 */ 7384 #define MCG_S_IRCST(x) (((uint8_t)(((uint8_t)(x)) << MCG_S_IRCST_SHIFT)) & MCG_S_IRCST_MASK) 7385 #define MCG_S_OSCINIT0_MASK (0x2U) 7386 #define MCG_S_OSCINIT0_SHIFT (1U) 7387 #define MCG_S_OSCINIT0(x) (((uint8_t)(((uint8_t)(x)) << MCG_S_OSCINIT0_SHIFT)) & MCG_S_OSCINIT0_MASK) 7388 #define MCG_S_CLKST_MASK (0xCU) 7389 #define MCG_S_CLKST_SHIFT (2U) 7390 /*! CLKST - Clock Mode Status 7391 * 0b00..Encoding 0 - Output of the FLL is selected (reset default). 7392 * 0b01..Encoding 1 - Internal reference clock is selected. 7393 * 0b10..Encoding 2 - External reference clock is selected. 7394 * 0b11..Reserved. 7395 */ 7396 #define MCG_S_CLKST(x) (((uint8_t)(((uint8_t)(x)) << MCG_S_CLKST_SHIFT)) & MCG_S_CLKST_MASK) 7397 #define MCG_S_IREFST_MASK (0x10U) 7398 #define MCG_S_IREFST_SHIFT (4U) 7399 /*! IREFST - Internal Reference Status 7400 * 0b0..Source of FLL reference clock is the external reference clock. 7401 * 0b1..Source of FLL reference clock is the internal reference clock. 7402 */ 7403 #define MCG_S_IREFST(x) (((uint8_t)(((uint8_t)(x)) << MCG_S_IREFST_SHIFT)) & MCG_S_IREFST_MASK) 7404 /*! @} */ 7405 7406 /*! @name SC - MCG Status and Control Register */ 7407 /*! @{ */ 7408 #define MCG_SC_LOCS0_MASK (0x1U) 7409 #define MCG_SC_LOCS0_SHIFT (0U) 7410 /*! LOCS0 - OSC0 Loss of Clock Status 7411 * 0b0..Loss of OSC0 has not occurred. 7412 * 0b1..Loss of OSC0 has occurred. 7413 */ 7414 #define MCG_SC_LOCS0(x) (((uint8_t)(((uint8_t)(x)) << MCG_SC_LOCS0_SHIFT)) & MCG_SC_LOCS0_MASK) 7415 #define MCG_SC_FCRDIV_MASK (0xEU) 7416 #define MCG_SC_FCRDIV_SHIFT (1U) 7417 /*! FCRDIV - Fast Clock Internal Reference Divider 7418 * 0b000..Divide Factor is 1 7419 * 0b001..Divide Factor is 2. 7420 * 0b010..Divide Factor is 4. 7421 * 0b011..Divide Factor is 8. 7422 * 0b100..Divide Factor is 16 7423 * 0b101..Divide Factor is 32 7424 * 0b110..Divide Factor is 64 7425 * 0b111..Divide Factor is 128. 7426 */ 7427 #define MCG_SC_FCRDIV(x) (((uint8_t)(((uint8_t)(x)) << MCG_SC_FCRDIV_SHIFT)) & MCG_SC_FCRDIV_MASK) 7428 #define MCG_SC_FLTPRSRV_MASK (0x10U) 7429 #define MCG_SC_FLTPRSRV_SHIFT (4U) 7430 /*! FLTPRSRV - FLL Filter Preserve Enable 7431 * 0b0..FLL filter and FLL frequency will reset on changes to currect clock mode. 7432 * 0b1..Fll filter and FLL frequency retain their previous values during new clock mode change. 7433 */ 7434 #define MCG_SC_FLTPRSRV(x) (((uint8_t)(((uint8_t)(x)) << MCG_SC_FLTPRSRV_SHIFT)) & MCG_SC_FLTPRSRV_MASK) 7435 #define MCG_SC_ATMF_MASK (0x20U) 7436 #define MCG_SC_ATMF_SHIFT (5U) 7437 /*! ATMF - Automatic Trim Machine Fail Flag 7438 * 0b0..Automatic Trim Machine completed normally. 7439 * 0b1..Automatic Trim Machine failed. 7440 */ 7441 #define MCG_SC_ATMF(x) (((uint8_t)(((uint8_t)(x)) << MCG_SC_ATMF_SHIFT)) & MCG_SC_ATMF_MASK) 7442 #define MCG_SC_ATMS_MASK (0x40U) 7443 #define MCG_SC_ATMS_SHIFT (6U) 7444 /*! ATMS - Automatic Trim Machine Select 7445 * 0b0..32 kHz Internal Reference Clock selected. 7446 * 0b1..4 MHz Internal Reference Clock selected. 7447 */ 7448 #define MCG_SC_ATMS(x) (((uint8_t)(((uint8_t)(x)) << MCG_SC_ATMS_SHIFT)) & MCG_SC_ATMS_MASK) 7449 #define MCG_SC_ATME_MASK (0x80U) 7450 #define MCG_SC_ATME_SHIFT (7U) 7451 /*! ATME - Automatic Trim Machine Enable 7452 * 0b0..Auto Trim Machine disabled. 7453 * 0b1..Auto Trim Machine enabled. 7454 */ 7455 #define MCG_SC_ATME(x) (((uint8_t)(((uint8_t)(x)) << MCG_SC_ATME_SHIFT)) & MCG_SC_ATME_MASK) 7456 /*! @} */ 7457 7458 /*! @name ATCVH - MCG Auto Trim Compare Value High Register */ 7459 /*! @{ */ 7460 #define MCG_ATCVH_ATCVH_MASK (0xFFU) 7461 #define MCG_ATCVH_ATCVH_SHIFT (0U) 7462 #define MCG_ATCVH_ATCVH(x) (((uint8_t)(((uint8_t)(x)) << MCG_ATCVH_ATCVH_SHIFT)) & MCG_ATCVH_ATCVH_MASK) 7463 /*! @} */ 7464 7465 /*! @name ATCVL - MCG Auto Trim Compare Value Low Register */ 7466 /*! @{ */ 7467 #define MCG_ATCVL_ATCVL_MASK (0xFFU) 7468 #define MCG_ATCVL_ATCVL_SHIFT (0U) 7469 #define MCG_ATCVL_ATCVL(x) (((uint8_t)(((uint8_t)(x)) << MCG_ATCVL_ATCVL_SHIFT)) & MCG_ATCVL_ATCVL_MASK) 7470 /*! @} */ 7471 7472 7473 /*! 7474 * @} 7475 */ /* end of group MCG_Register_Masks */ 7476 7477 7478 /* MCG - Peripheral instance base addresses */ 7479 /** Peripheral MCG base address */ 7480 #define MCG_BASE (0x40064000u) 7481 /** Peripheral MCG base pointer */ 7482 #define MCG ((MCG_Type *)MCG_BASE) 7483 /** Array initializer of MCG peripheral base addresses */ 7484 #define MCG_BASE_ADDRS { MCG_BASE } 7485 /** Array initializer of MCG peripheral base pointers */ 7486 #define MCG_BASE_PTRS { MCG } 7487 /** Interrupt vectors for the MCG peripheral type */ 7488 #define MCG_IRQS { MCG_IRQn } 7489 7490 /*! 7491 * @} 7492 */ /* end of group MCG_Peripheral_Access_Layer */ 7493 7494 7495 /* ---------------------------------------------------------------------------- 7496 -- MCM Peripheral Access Layer 7497 ---------------------------------------------------------------------------- */ 7498 7499 /*! 7500 * @addtogroup MCM_Peripheral_Access_Layer MCM Peripheral Access Layer 7501 * @{ 7502 */ 7503 7504 /** MCM - Register Layout Typedef */ 7505 typedef struct { 7506 uint8_t RESERVED_0[8]; 7507 __I uint16_t PLASC; /**< Crossbar Switch (AXBS) Slave Configuration, offset: 0x8 */ 7508 __I uint16_t PLAMC; /**< Crossbar Switch (AXBS) Master Configuration, offset: 0xA */ 7509 __IO uint32_t PLACR; /**< Platform Control Register, offset: 0xC */ 7510 uint8_t RESERVED_1[48]; 7511 __IO uint32_t CPO; /**< Compute Operation Control Register, offset: 0x40 */ 7512 } MCM_Type; 7513 7514 /* ---------------------------------------------------------------------------- 7515 -- MCM Register Masks 7516 ---------------------------------------------------------------------------- */ 7517 7518 /*! 7519 * @addtogroup MCM_Register_Masks MCM Register Masks 7520 * @{ 7521 */ 7522 7523 /*! @name PLASC - Crossbar Switch (AXBS) Slave Configuration */ 7524 /*! @{ */ 7525 #define MCM_PLASC_ASC_MASK (0xFFU) 7526 #define MCM_PLASC_ASC_SHIFT (0U) 7527 /*! ASC - Each bit in the ASC field indicates whether there is a corresponding connection to the crossbar switch's slave input port. 7528 * 0b00000000..A bus slave connection to AXBS input port n is absent. 7529 * 0b00000001..A bus slave connection to AXBS input port n is present. 7530 */ 7531 #define MCM_PLASC_ASC(x) (((uint16_t)(((uint16_t)(x)) << MCM_PLASC_ASC_SHIFT)) & MCM_PLASC_ASC_MASK) 7532 /*! @} */ 7533 7534 /*! @name PLAMC - Crossbar Switch (AXBS) Master Configuration */ 7535 /*! @{ */ 7536 #define MCM_PLAMC_AMC_MASK (0xFFU) 7537 #define MCM_PLAMC_AMC_SHIFT (0U) 7538 /*! AMC - Each bit in the AMC field indicates whether there is a corresponding connection to the AXBS master input port. 7539 * 0b00000000..A bus master connection to AXBS input port n is absent 7540 * 0b00000001..A bus master connection to AXBS input port n is present 7541 */ 7542 #define MCM_PLAMC_AMC(x) (((uint16_t)(((uint16_t)(x)) << MCM_PLAMC_AMC_SHIFT)) & MCM_PLAMC_AMC_MASK) 7543 /*! @} */ 7544 7545 /*! @name PLACR - Platform Control Register */ 7546 /*! @{ */ 7547 #define MCM_PLACR_ARB_MASK (0x200U) 7548 #define MCM_PLACR_ARB_SHIFT (9U) 7549 /*! ARB - Arbitration select 7550 * 0b0..Fixed-priority arbitration for the crossbar masters 7551 * 0b1..Round-robin arbitration for the crossbar masters 7552 */ 7553 #define MCM_PLACR_ARB(x) (((uint32_t)(((uint32_t)(x)) << MCM_PLACR_ARB_SHIFT)) & MCM_PLACR_ARB_MASK) 7554 #define MCM_PLACR_CFCC_MASK (0x400U) 7555 #define MCM_PLACR_CFCC_SHIFT (10U) 7556 #define MCM_PLACR_CFCC(x) (((uint32_t)(((uint32_t)(x)) << MCM_PLACR_CFCC_SHIFT)) & MCM_PLACR_CFCC_MASK) 7557 #define MCM_PLACR_DFCDA_MASK (0x800U) 7558 #define MCM_PLACR_DFCDA_SHIFT (11U) 7559 /*! DFCDA - Disable Flash Controller Data Caching 7560 * 0b0..Enable flash controller data caching 7561 * 0b1..Disable flash controller data caching. 7562 */ 7563 #define MCM_PLACR_DFCDA(x) (((uint32_t)(((uint32_t)(x)) << MCM_PLACR_DFCDA_SHIFT)) & MCM_PLACR_DFCDA_MASK) 7564 #define MCM_PLACR_DFCIC_MASK (0x1000U) 7565 #define MCM_PLACR_DFCIC_SHIFT (12U) 7566 /*! DFCIC - Disable Flash Controller Instruction Caching 7567 * 0b0..Enable flash controller instruction caching. 7568 * 0b1..Disable flash controller instruction caching. 7569 */ 7570 #define MCM_PLACR_DFCIC(x) (((uint32_t)(((uint32_t)(x)) << MCM_PLACR_DFCIC_SHIFT)) & MCM_PLACR_DFCIC_MASK) 7571 #define MCM_PLACR_DFCC_MASK (0x2000U) 7572 #define MCM_PLACR_DFCC_SHIFT (13U) 7573 /*! DFCC - Disable Flash Controller Cache 7574 * 0b0..Enable flash controller cache. 7575 * 0b1..Disable flash controller cache. 7576 */ 7577 #define MCM_PLACR_DFCC(x) (((uint32_t)(((uint32_t)(x)) << MCM_PLACR_DFCC_SHIFT)) & MCM_PLACR_DFCC_MASK) 7578 #define MCM_PLACR_EFDS_MASK (0x4000U) 7579 #define MCM_PLACR_EFDS_SHIFT (14U) 7580 /*! EFDS - Enable Flash Data Speculation 7581 * 0b0..Disable flash data speculation. 7582 * 0b1..Enable flash data speculation. 7583 */ 7584 #define MCM_PLACR_EFDS(x) (((uint32_t)(((uint32_t)(x)) << MCM_PLACR_EFDS_SHIFT)) & MCM_PLACR_EFDS_MASK) 7585 #define MCM_PLACR_DFCS_MASK (0x8000U) 7586 #define MCM_PLACR_DFCS_SHIFT (15U) 7587 /*! DFCS - Disable Flash Controller Speculation 7588 * 0b0..Enable flash controller speculation. 7589 * 0b1..Disable flash controller speculation. 7590 */ 7591 #define MCM_PLACR_DFCS(x) (((uint32_t)(((uint32_t)(x)) << MCM_PLACR_DFCS_SHIFT)) & MCM_PLACR_DFCS_MASK) 7592 #define MCM_PLACR_ESFC_MASK (0x10000U) 7593 #define MCM_PLACR_ESFC_SHIFT (16U) 7594 /*! ESFC - Enable Stalling Flash Controller 7595 * 0b0..Disable stalling flash controller when flash is busy. 7596 * 0b1..Enable stalling flash controller when flash is busy. 7597 */ 7598 #define MCM_PLACR_ESFC(x) (((uint32_t)(((uint32_t)(x)) << MCM_PLACR_ESFC_SHIFT)) & MCM_PLACR_ESFC_MASK) 7599 /*! @} */ 7600 7601 /*! @name CPO - Compute Operation Control Register */ 7602 /*! @{ */ 7603 #define MCM_CPO_CPOREQ_MASK (0x1U) 7604 #define MCM_CPO_CPOREQ_SHIFT (0U) 7605 /*! CPOREQ - Compute Operation Request 7606 * 0b0..Request is cleared. 7607 * 0b1..Request Compute Operation. 7608 */ 7609 #define MCM_CPO_CPOREQ(x) (((uint32_t)(((uint32_t)(x)) << MCM_CPO_CPOREQ_SHIFT)) & MCM_CPO_CPOREQ_MASK) 7610 #define MCM_CPO_CPOACK_MASK (0x2U) 7611 #define MCM_CPO_CPOACK_SHIFT (1U) 7612 /*! CPOACK - Compute Operation Acknowledge 7613 * 0b0..Compute operation entry has not completed or compute operation exit has completed. 7614 * 0b1..Compute operation entry has completed or compute operation exit has not completed. 7615 */ 7616 #define MCM_CPO_CPOACK(x) (((uint32_t)(((uint32_t)(x)) << MCM_CPO_CPOACK_SHIFT)) & MCM_CPO_CPOACK_MASK) 7617 #define MCM_CPO_CPOWOI_MASK (0x4U) 7618 #define MCM_CPO_CPOWOI_SHIFT (2U) 7619 /*! CPOWOI - Compute Operation Wake-up on Interrupt 7620 * 0b0..No effect. 7621 * 0b1..When set, the CPOREQ is cleared on any interrupt or exception vector fetch. 7622 */ 7623 #define MCM_CPO_CPOWOI(x) (((uint32_t)(((uint32_t)(x)) << MCM_CPO_CPOWOI_SHIFT)) & MCM_CPO_CPOWOI_MASK) 7624 /*! @} */ 7625 7626 7627 /*! 7628 * @} 7629 */ /* end of group MCM_Register_Masks */ 7630 7631 7632 /* MCM - Peripheral instance base addresses */ 7633 /** Peripheral MCM base address */ 7634 #define MCM_BASE (0xF0003000u) 7635 /** Peripheral MCM base pointer */ 7636 #define MCM ((MCM_Type *)MCM_BASE) 7637 /** Array initializer of MCM peripheral base addresses */ 7638 #define MCM_BASE_ADDRS { MCM_BASE } 7639 /** Array initializer of MCM peripheral base pointers */ 7640 #define MCM_BASE_PTRS { MCM } 7641 7642 /*! 7643 * @} 7644 */ /* end of group MCM_Peripheral_Access_Layer */ 7645 7646 7647 /* ---------------------------------------------------------------------------- 7648 -- MMDVSQ Peripheral Access Layer 7649 ---------------------------------------------------------------------------- */ 7650 7651 /*! 7652 * @addtogroup MMDVSQ_Peripheral_Access_Layer MMDVSQ Peripheral Access Layer 7653 * @{ 7654 */ 7655 7656 /** MMDVSQ - Register Layout Typedef */ 7657 typedef struct { 7658 __IO uint32_t DEND; /**< Dividend Register, offset: 0x0 */ 7659 __IO uint32_t DSOR; /**< Divisor Register, offset: 0x4 */ 7660 __IO uint32_t CSR; /**< Control/Status Register, offset: 0x8 */ 7661 __IO uint32_t RES; /**< Result Register, offset: 0xC */ 7662 __IO uint32_t RCND; /**< Radicand Register, offset: 0x10 */ 7663 } MMDVSQ_Type; 7664 7665 /* ---------------------------------------------------------------------------- 7666 -- MMDVSQ Register Masks 7667 ---------------------------------------------------------------------------- */ 7668 7669 /*! 7670 * @addtogroup MMDVSQ_Register_Masks MMDVSQ Register Masks 7671 * @{ 7672 */ 7673 7674 /*! @name DEND - Dividend Register */ 7675 /*! @{ */ 7676 #define MMDVSQ_DEND_DIVIDEND_MASK (0xFFFFFFFFU) 7677 #define MMDVSQ_DEND_DIVIDEND_SHIFT (0U) 7678 #define MMDVSQ_DEND_DIVIDEND(x) (((uint32_t)(((uint32_t)(x)) << MMDVSQ_DEND_DIVIDEND_SHIFT)) & MMDVSQ_DEND_DIVIDEND_MASK) 7679 /*! @} */ 7680 7681 /*! @name DSOR - Divisor Register */ 7682 /*! @{ */ 7683 #define MMDVSQ_DSOR_DIVISOR_MASK (0xFFFFFFFFU) 7684 #define MMDVSQ_DSOR_DIVISOR_SHIFT (0U) 7685 #define MMDVSQ_DSOR_DIVISOR(x) (((uint32_t)(((uint32_t)(x)) << MMDVSQ_DSOR_DIVISOR_SHIFT)) & MMDVSQ_DSOR_DIVISOR_MASK) 7686 /*! @} */ 7687 7688 /*! @name CSR - Control/Status Register */ 7689 /*! @{ */ 7690 #define MMDVSQ_CSR_SRT_MASK (0x1U) 7691 #define MMDVSQ_CSR_SRT_SHIFT (0U) 7692 /*! SRT - Start 7693 * 0b0..No operation initiated 7694 * 0b1..If CSR[DFS] = 1, then initiate a divide calculation, else ignore 7695 */ 7696 #define MMDVSQ_CSR_SRT(x) (((uint32_t)(((uint32_t)(x)) << MMDVSQ_CSR_SRT_SHIFT)) & MMDVSQ_CSR_SRT_MASK) 7697 #define MMDVSQ_CSR_USGN_MASK (0x2U) 7698 #define MMDVSQ_CSR_USGN_SHIFT (1U) 7699 /*! USGN - Unsigned calculation 7700 * 0b0..Perform a signed divide 7701 * 0b1..Perform an unsigned divide 7702 */ 7703 #define MMDVSQ_CSR_USGN(x) (((uint32_t)(((uint32_t)(x)) << MMDVSQ_CSR_USGN_SHIFT)) & MMDVSQ_CSR_USGN_MASK) 7704 #define MMDVSQ_CSR_REM_MASK (0x4U) 7705 #define MMDVSQ_CSR_REM_SHIFT (2U) 7706 /*! REM - REMainder calculation 7707 * 0b0..Return the quotient in the RES for the divide calculation 7708 * 0b1..Return the remainder in the RES for the divide calculation 7709 */ 7710 #define MMDVSQ_CSR_REM(x) (((uint32_t)(((uint32_t)(x)) << MMDVSQ_CSR_REM_SHIFT)) & MMDVSQ_CSR_REM_MASK) 7711 #define MMDVSQ_CSR_DZE_MASK (0x8U) 7712 #define MMDVSQ_CSR_DZE_SHIFT (3U) 7713 /*! DZE - Divide-by-Zero-Enable 7714 * 0b0..Reads of the RES register return the register contents 7715 * 0b1..If CSR[DZ] = 1, an attempted read of RES register is error terminated to signal a divide-by-zero, else the register contents are returned 7716 */ 7717 #define MMDVSQ_CSR_DZE(x) (((uint32_t)(((uint32_t)(x)) << MMDVSQ_CSR_DZE_SHIFT)) & MMDVSQ_CSR_DZE_MASK) 7718 #define MMDVSQ_CSR_DZ_MASK (0x10U) 7719 #define MMDVSQ_CSR_DZ_SHIFT (4U) 7720 /*! DZ - Divide-by-Zero 7721 * 0b0..The last divide operation had a non-zero divisor, that is, DSOR != 0 7722 * 0b1..The last divide operation had a zero divisor, that is, DSOR = 0 7723 */ 7724 #define MMDVSQ_CSR_DZ(x) (((uint32_t)(((uint32_t)(x)) << MMDVSQ_CSR_DZ_SHIFT)) & MMDVSQ_CSR_DZ_MASK) 7725 #define MMDVSQ_CSR_DFS_MASK (0x20U) 7726 #define MMDVSQ_CSR_DFS_SHIFT (5U) 7727 /*! DFS - Disable Fast Start 7728 * 0b0..A divide operation is initiated by a write to the DSOR register 7729 * 0b1..A divide operation is initiated by a write to the CSR register with CSR[SRT] = 1 7730 */ 7731 #define MMDVSQ_CSR_DFS(x) (((uint32_t)(((uint32_t)(x)) << MMDVSQ_CSR_DFS_SHIFT)) & MMDVSQ_CSR_DFS_MASK) 7732 #define MMDVSQ_CSR_SQRT_MASK (0x20000000U) 7733 #define MMDVSQ_CSR_SQRT_SHIFT (29U) 7734 /*! SQRT - SQUARE ROOT 7735 * 0b0..Current or last MMDVSQ operation was not a square root 7736 * 0b1..Current or last MMDVSQ operation was a square root 7737 */ 7738 #define MMDVSQ_CSR_SQRT(x) (((uint32_t)(((uint32_t)(x)) << MMDVSQ_CSR_SQRT_SHIFT)) & MMDVSQ_CSR_SQRT_MASK) 7739 #define MMDVSQ_CSR_DIV_MASK (0x40000000U) 7740 #define MMDVSQ_CSR_DIV_SHIFT (30U) 7741 /*! DIV - DIVIDE 7742 * 0b0..Current or last MMDVSQ operation was not a divide 7743 * 0b1..Current or last MMDVSQ operation was a divide 7744 */ 7745 #define MMDVSQ_CSR_DIV(x) (((uint32_t)(((uint32_t)(x)) << MMDVSQ_CSR_DIV_SHIFT)) & MMDVSQ_CSR_DIV_MASK) 7746 #define MMDVSQ_CSR_BUSY_MASK (0x80000000U) 7747 #define MMDVSQ_CSR_BUSY_SHIFT (31U) 7748 /*! BUSY - BUSY 7749 * 0b0..MMDVSQ is idle 7750 * 0b1..MMDVSQ is busy performing a divide or square root calculation 7751 */ 7752 #define MMDVSQ_CSR_BUSY(x) (((uint32_t)(((uint32_t)(x)) << MMDVSQ_CSR_BUSY_SHIFT)) & MMDVSQ_CSR_BUSY_MASK) 7753 /*! @} */ 7754 7755 /*! @name RES - Result Register */ 7756 /*! @{ */ 7757 #define MMDVSQ_RES_RESULT_MASK (0xFFFFFFFFU) 7758 #define MMDVSQ_RES_RESULT_SHIFT (0U) 7759 #define MMDVSQ_RES_RESULT(x) (((uint32_t)(((uint32_t)(x)) << MMDVSQ_RES_RESULT_SHIFT)) & MMDVSQ_RES_RESULT_MASK) 7760 /*! @} */ 7761 7762 /*! @name RCND - Radicand Register */ 7763 /*! @{ */ 7764 #define MMDVSQ_RCND_RADICAND_MASK (0xFFFFFFFFU) 7765 #define MMDVSQ_RCND_RADICAND_SHIFT (0U) 7766 #define MMDVSQ_RCND_RADICAND(x) (((uint32_t)(((uint32_t)(x)) << MMDVSQ_RCND_RADICAND_SHIFT)) & MMDVSQ_RCND_RADICAND_MASK) 7767 /*! @} */ 7768 7769 7770 /*! 7771 * @} 7772 */ /* end of group MMDVSQ_Register_Masks */ 7773 7774 7775 /* MMDVSQ - Peripheral instance base addresses */ 7776 /** Peripheral MMDVSQ base address */ 7777 #define MMDVSQ_BASE (0xF0004000u) 7778 /** Peripheral MMDVSQ base pointer */ 7779 #define MMDVSQ ((MMDVSQ_Type *)MMDVSQ_BASE) 7780 /** Array initializer of MMDVSQ peripheral base addresses */ 7781 #define MMDVSQ_BASE_ADDRS { MMDVSQ_BASE } 7782 /** Array initializer of MMDVSQ peripheral base pointers */ 7783 #define MMDVSQ_BASE_PTRS { MMDVSQ } 7784 7785 /*! 7786 * @} 7787 */ /* end of group MMDVSQ_Peripheral_Access_Layer */ 7788 7789 7790 /* ---------------------------------------------------------------------------- 7791 -- MTB Peripheral Access Layer 7792 ---------------------------------------------------------------------------- */ 7793 7794 /*! 7795 * @addtogroup MTB_Peripheral_Access_Layer MTB Peripheral Access Layer 7796 * @{ 7797 */ 7798 7799 /** MTB - Register Layout Typedef */ 7800 typedef struct { 7801 __IO uint32_t POSITION; /**< MTB Position Register, offset: 0x0 */ 7802 __IO uint32_t MASTER; /**< MTB Master Register, offset: 0x4 */ 7803 __IO uint32_t FLOW; /**< MTB Flow Register, offset: 0x8 */ 7804 __I uint32_t BASE; /**< MTB Base Register, offset: 0xC */ 7805 uint8_t RESERVED_0[3824]; 7806 __I uint32_t MODECTRL; /**< Integration Mode Control Register, offset: 0xF00 */ 7807 uint8_t RESERVED_1[156]; 7808 __I uint32_t TAGSET; /**< Claim TAG Set Register, offset: 0xFA0 */ 7809 __I uint32_t TAGCLEAR; /**< Claim TAG Clear Register, offset: 0xFA4 */ 7810 uint8_t RESERVED_2[8]; 7811 __I uint32_t LOCKACCESS; /**< Lock Access Register, offset: 0xFB0 */ 7812 __I uint32_t LOCKSTAT; /**< Lock Status Register, offset: 0xFB4 */ 7813 __I uint32_t AUTHSTAT; /**< Authentication Status Register, offset: 0xFB8 */ 7814 __I uint32_t DEVICEARCH; /**< Device Architecture Register, offset: 0xFBC */ 7815 uint8_t RESERVED_3[8]; 7816 __I uint32_t DEVICECFG; /**< Device Configuration Register, offset: 0xFC8 */ 7817 __I uint32_t DEVICETYPID; /**< Device Type Identifier Register, offset: 0xFCC */ 7818 __I uint32_t PERIPHID4; /**< Peripheral ID Register, offset: 0xFD0 */ 7819 __I uint32_t PERIPHID5; /**< Peripheral ID Register, offset: 0xFD4 */ 7820 __I uint32_t PERIPHID6; /**< Peripheral ID Register, offset: 0xFD8 */ 7821 __I uint32_t PERIPHID7; /**< Peripheral ID Register, offset: 0xFDC */ 7822 __I uint32_t PERIPHID0; /**< Peripheral ID Register, offset: 0xFE0 */ 7823 __I uint32_t PERIPHID1; /**< Peripheral ID Register, offset: 0xFE4 */ 7824 __I uint32_t PERIPHID2; /**< Peripheral ID Register, offset: 0xFE8 */ 7825 __I uint32_t PERIPHID3; /**< Peripheral ID Register, offset: 0xFEC */ 7826 __I uint32_t COMPID[4]; /**< Component ID Register, array offset: 0xFF0, array step: 0x4 */ 7827 } MTB_Type; 7828 7829 /* ---------------------------------------------------------------------------- 7830 -- MTB Register Masks 7831 ---------------------------------------------------------------------------- */ 7832 7833 /*! 7834 * @addtogroup MTB_Register_Masks MTB Register Masks 7835 * @{ 7836 */ 7837 7838 /*! @name POSITION - MTB Position Register */ 7839 /*! @{ */ 7840 #define MTB_POSITION_WRAP_MASK (0x4U) 7841 #define MTB_POSITION_WRAP_SHIFT (2U) 7842 #define MTB_POSITION_WRAP(x) (((uint32_t)(((uint32_t)(x)) << MTB_POSITION_WRAP_SHIFT)) & MTB_POSITION_WRAP_MASK) 7843 #define MTB_POSITION_POINTER_MASK (0xFFFFFFF8U) 7844 #define MTB_POSITION_POINTER_SHIFT (3U) 7845 #define MTB_POSITION_POINTER(x) (((uint32_t)(((uint32_t)(x)) << MTB_POSITION_POINTER_SHIFT)) & MTB_POSITION_POINTER_MASK) 7846 /*! @} */ 7847 7848 /*! @name MASTER - MTB Master Register */ 7849 /*! @{ */ 7850 #define MTB_MASTER_MASK_MASK (0x1FU) 7851 #define MTB_MASTER_MASK_SHIFT (0U) 7852 #define MTB_MASTER_MASK(x) (((uint32_t)(((uint32_t)(x)) << MTB_MASTER_MASK_SHIFT)) & MTB_MASTER_MASK_MASK) 7853 #define MTB_MASTER_TSTARTEN_MASK (0x20U) 7854 #define MTB_MASTER_TSTARTEN_SHIFT (5U) 7855 #define MTB_MASTER_TSTARTEN(x) (((uint32_t)(((uint32_t)(x)) << MTB_MASTER_TSTARTEN_SHIFT)) & MTB_MASTER_TSTARTEN_MASK) 7856 #define MTB_MASTER_TSTOPEN_MASK (0x40U) 7857 #define MTB_MASTER_TSTOPEN_SHIFT (6U) 7858 #define MTB_MASTER_TSTOPEN(x) (((uint32_t)(((uint32_t)(x)) << MTB_MASTER_TSTOPEN_SHIFT)) & MTB_MASTER_TSTOPEN_MASK) 7859 #define MTB_MASTER_SFRWPRIV_MASK (0x80U) 7860 #define MTB_MASTER_SFRWPRIV_SHIFT (7U) 7861 #define MTB_MASTER_SFRWPRIV(x) (((uint32_t)(((uint32_t)(x)) << MTB_MASTER_SFRWPRIV_SHIFT)) & MTB_MASTER_SFRWPRIV_MASK) 7862 #define MTB_MASTER_RAMPRIV_MASK (0x100U) 7863 #define MTB_MASTER_RAMPRIV_SHIFT (8U) 7864 #define MTB_MASTER_RAMPRIV(x) (((uint32_t)(((uint32_t)(x)) << MTB_MASTER_RAMPRIV_SHIFT)) & MTB_MASTER_RAMPRIV_MASK) 7865 #define MTB_MASTER_HALTREQ_MASK (0x200U) 7866 #define MTB_MASTER_HALTREQ_SHIFT (9U) 7867 #define MTB_MASTER_HALTREQ(x) (((uint32_t)(((uint32_t)(x)) << MTB_MASTER_HALTREQ_SHIFT)) & MTB_MASTER_HALTREQ_MASK) 7868 #define MTB_MASTER_EN_MASK (0x80000000U) 7869 #define MTB_MASTER_EN_SHIFT (31U) 7870 #define MTB_MASTER_EN(x) (((uint32_t)(((uint32_t)(x)) << MTB_MASTER_EN_SHIFT)) & MTB_MASTER_EN_MASK) 7871 /*! @} */ 7872 7873 /*! @name FLOW - MTB Flow Register */ 7874 /*! @{ */ 7875 #define MTB_FLOW_AUTOSTOP_MASK (0x1U) 7876 #define MTB_FLOW_AUTOSTOP_SHIFT (0U) 7877 #define MTB_FLOW_AUTOSTOP(x) (((uint32_t)(((uint32_t)(x)) << MTB_FLOW_AUTOSTOP_SHIFT)) & MTB_FLOW_AUTOSTOP_MASK) 7878 #define MTB_FLOW_AUTOHALT_MASK (0x2U) 7879 #define MTB_FLOW_AUTOHALT_SHIFT (1U) 7880 #define MTB_FLOW_AUTOHALT(x) (((uint32_t)(((uint32_t)(x)) << MTB_FLOW_AUTOHALT_SHIFT)) & MTB_FLOW_AUTOHALT_MASK) 7881 #define MTB_FLOW_WATERMARK_MASK (0xFFFFFFF8U) 7882 #define MTB_FLOW_WATERMARK_SHIFT (3U) 7883 #define MTB_FLOW_WATERMARK(x) (((uint32_t)(((uint32_t)(x)) << MTB_FLOW_WATERMARK_SHIFT)) & MTB_FLOW_WATERMARK_MASK) 7884 /*! @} */ 7885 7886 /*! @name BASE - MTB Base Register */ 7887 /*! @{ */ 7888 #define MTB_BASE_BASEADDR_MASK (0xFFFFFFFFU) 7889 #define MTB_BASE_BASEADDR_SHIFT (0U) 7890 #define MTB_BASE_BASEADDR(x) (((uint32_t)(((uint32_t)(x)) << MTB_BASE_BASEADDR_SHIFT)) & MTB_BASE_BASEADDR_MASK) 7891 /*! @} */ 7892 7893 /*! @name MODECTRL - Integration Mode Control Register */ 7894 /*! @{ */ 7895 #define MTB_MODECTRL_MODECTRL_MASK (0xFFFFFFFFU) 7896 #define MTB_MODECTRL_MODECTRL_SHIFT (0U) 7897 #define MTB_MODECTRL_MODECTRL(x) (((uint32_t)(((uint32_t)(x)) << MTB_MODECTRL_MODECTRL_SHIFT)) & MTB_MODECTRL_MODECTRL_MASK) 7898 /*! @} */ 7899 7900 /*! @name TAGSET - Claim TAG Set Register */ 7901 /*! @{ */ 7902 #define MTB_TAGSET_TAGSET_MASK (0xFFFFFFFFU) 7903 #define MTB_TAGSET_TAGSET_SHIFT (0U) 7904 #define MTB_TAGSET_TAGSET(x) (((uint32_t)(((uint32_t)(x)) << MTB_TAGSET_TAGSET_SHIFT)) & MTB_TAGSET_TAGSET_MASK) 7905 /*! @} */ 7906 7907 /*! @name TAGCLEAR - Claim TAG Clear Register */ 7908 /*! @{ */ 7909 #define MTB_TAGCLEAR_TAGCLEAR_MASK (0xFFFFFFFFU) 7910 #define MTB_TAGCLEAR_TAGCLEAR_SHIFT (0U) 7911 #define MTB_TAGCLEAR_TAGCLEAR(x) (((uint32_t)(((uint32_t)(x)) << MTB_TAGCLEAR_TAGCLEAR_SHIFT)) & MTB_TAGCLEAR_TAGCLEAR_MASK) 7912 /*! @} */ 7913 7914 /*! @name LOCKACCESS - Lock Access Register */ 7915 /*! @{ */ 7916 #define MTB_LOCKACCESS_LOCKACCESS_MASK (0xFFFFFFFFU) 7917 #define MTB_LOCKACCESS_LOCKACCESS_SHIFT (0U) 7918 #define MTB_LOCKACCESS_LOCKACCESS(x) (((uint32_t)(((uint32_t)(x)) << MTB_LOCKACCESS_LOCKACCESS_SHIFT)) & MTB_LOCKACCESS_LOCKACCESS_MASK) 7919 /*! @} */ 7920 7921 /*! @name LOCKSTAT - Lock Status Register */ 7922 /*! @{ */ 7923 #define MTB_LOCKSTAT_LOCKSTAT_MASK (0xFFFFFFFFU) 7924 #define MTB_LOCKSTAT_LOCKSTAT_SHIFT (0U) 7925 #define MTB_LOCKSTAT_LOCKSTAT(x) (((uint32_t)(((uint32_t)(x)) << MTB_LOCKSTAT_LOCKSTAT_SHIFT)) & MTB_LOCKSTAT_LOCKSTAT_MASK) 7926 /*! @} */ 7927 7928 /*! @name AUTHSTAT - Authentication Status Register */ 7929 /*! @{ */ 7930 #define MTB_AUTHSTAT_BIT0_MASK (0x1U) 7931 #define MTB_AUTHSTAT_BIT0_SHIFT (0U) 7932 #define MTB_AUTHSTAT_BIT0(x) (((uint32_t)(((uint32_t)(x)) << MTB_AUTHSTAT_BIT0_SHIFT)) & MTB_AUTHSTAT_BIT0_MASK) 7933 #define MTB_AUTHSTAT_BIT1_MASK (0x2U) 7934 #define MTB_AUTHSTAT_BIT1_SHIFT (1U) 7935 #define MTB_AUTHSTAT_BIT1(x) (((uint32_t)(((uint32_t)(x)) << MTB_AUTHSTAT_BIT1_SHIFT)) & MTB_AUTHSTAT_BIT1_MASK) 7936 #define MTB_AUTHSTAT_BIT2_MASK (0x4U) 7937 #define MTB_AUTHSTAT_BIT2_SHIFT (2U) 7938 #define MTB_AUTHSTAT_BIT2(x) (((uint32_t)(((uint32_t)(x)) << MTB_AUTHSTAT_BIT2_SHIFT)) & MTB_AUTHSTAT_BIT2_MASK) 7939 #define MTB_AUTHSTAT_BIT3_MASK (0x8U) 7940 #define MTB_AUTHSTAT_BIT3_SHIFT (3U) 7941 #define MTB_AUTHSTAT_BIT3(x) (((uint32_t)(((uint32_t)(x)) << MTB_AUTHSTAT_BIT3_SHIFT)) & MTB_AUTHSTAT_BIT3_MASK) 7942 /*! @} */ 7943 7944 /*! @name DEVICEARCH - Device Architecture Register */ 7945 /*! @{ */ 7946 #define MTB_DEVICEARCH_DEVICEARCH_MASK (0xFFFFFFFFU) 7947 #define MTB_DEVICEARCH_DEVICEARCH_SHIFT (0U) 7948 #define MTB_DEVICEARCH_DEVICEARCH(x) (((uint32_t)(((uint32_t)(x)) << MTB_DEVICEARCH_DEVICEARCH_SHIFT)) & MTB_DEVICEARCH_DEVICEARCH_MASK) 7949 /*! @} */ 7950 7951 /*! @name DEVICECFG - Device Configuration Register */ 7952 /*! @{ */ 7953 #define MTB_DEVICECFG_DEVICECFG_MASK (0xFFFFFFFFU) 7954 #define MTB_DEVICECFG_DEVICECFG_SHIFT (0U) 7955 #define MTB_DEVICECFG_DEVICECFG(x) (((uint32_t)(((uint32_t)(x)) << MTB_DEVICECFG_DEVICECFG_SHIFT)) & MTB_DEVICECFG_DEVICECFG_MASK) 7956 /*! @} */ 7957 7958 /*! @name DEVICETYPID - Device Type Identifier Register */ 7959 /*! @{ */ 7960 #define MTB_DEVICETYPID_DEVICETYPID_MASK (0xFFFFFFFFU) 7961 #define MTB_DEVICETYPID_DEVICETYPID_SHIFT (0U) 7962 #define MTB_DEVICETYPID_DEVICETYPID(x) (((uint32_t)(((uint32_t)(x)) << MTB_DEVICETYPID_DEVICETYPID_SHIFT)) & MTB_DEVICETYPID_DEVICETYPID_MASK) 7963 /*! @} */ 7964 7965 /*! @name PERIPHID4 - Peripheral ID Register */ 7966 /*! @{ */ 7967 #define MTB_PERIPHID4_PERIPHID_MASK (0xFFFFFFFFU) 7968 #define MTB_PERIPHID4_PERIPHID_SHIFT (0U) 7969 #define MTB_PERIPHID4_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << MTB_PERIPHID4_PERIPHID_SHIFT)) & MTB_PERIPHID4_PERIPHID_MASK) 7970 /*! @} */ 7971 7972 /*! @name PERIPHID5 - Peripheral ID Register */ 7973 /*! @{ */ 7974 #define MTB_PERIPHID5_PERIPHID_MASK (0xFFFFFFFFU) 7975 #define MTB_PERIPHID5_PERIPHID_SHIFT (0U) 7976 #define MTB_PERIPHID5_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << MTB_PERIPHID5_PERIPHID_SHIFT)) & MTB_PERIPHID5_PERIPHID_MASK) 7977 /*! @} */ 7978 7979 /*! @name PERIPHID6 - Peripheral ID Register */ 7980 /*! @{ */ 7981 #define MTB_PERIPHID6_PERIPHID_MASK (0xFFFFFFFFU) 7982 #define MTB_PERIPHID6_PERIPHID_SHIFT (0U) 7983 #define MTB_PERIPHID6_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << MTB_PERIPHID6_PERIPHID_SHIFT)) & MTB_PERIPHID6_PERIPHID_MASK) 7984 /*! @} */ 7985 7986 /*! @name PERIPHID7 - Peripheral ID Register */ 7987 /*! @{ */ 7988 #define MTB_PERIPHID7_PERIPHID_MASK (0xFFFFFFFFU) 7989 #define MTB_PERIPHID7_PERIPHID_SHIFT (0U) 7990 #define MTB_PERIPHID7_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << MTB_PERIPHID7_PERIPHID_SHIFT)) & MTB_PERIPHID7_PERIPHID_MASK) 7991 /*! @} */ 7992 7993 /*! @name PERIPHID0 - Peripheral ID Register */ 7994 /*! @{ */ 7995 #define MTB_PERIPHID0_PERIPHID_MASK (0xFFFFFFFFU) 7996 #define MTB_PERIPHID0_PERIPHID_SHIFT (0U) 7997 #define MTB_PERIPHID0_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << MTB_PERIPHID0_PERIPHID_SHIFT)) & MTB_PERIPHID0_PERIPHID_MASK) 7998 /*! @} */ 7999 8000 /*! @name PERIPHID1 - Peripheral ID Register */ 8001 /*! @{ */ 8002 #define MTB_PERIPHID1_PERIPHID_MASK (0xFFFFFFFFU) 8003 #define MTB_PERIPHID1_PERIPHID_SHIFT (0U) 8004 #define MTB_PERIPHID1_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << MTB_PERIPHID1_PERIPHID_SHIFT)) & MTB_PERIPHID1_PERIPHID_MASK) 8005 /*! @} */ 8006 8007 /*! @name PERIPHID2 - Peripheral ID Register */ 8008 /*! @{ */ 8009 #define MTB_PERIPHID2_PERIPHID_MASK (0xFFFFFFFFU) 8010 #define MTB_PERIPHID2_PERIPHID_SHIFT (0U) 8011 #define MTB_PERIPHID2_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << MTB_PERIPHID2_PERIPHID_SHIFT)) & MTB_PERIPHID2_PERIPHID_MASK) 8012 /*! @} */ 8013 8014 /*! @name PERIPHID3 - Peripheral ID Register */ 8015 /*! @{ */ 8016 #define MTB_PERIPHID3_PERIPHID_MASK (0xFFFFFFFFU) 8017 #define MTB_PERIPHID3_PERIPHID_SHIFT (0U) 8018 #define MTB_PERIPHID3_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << MTB_PERIPHID3_PERIPHID_SHIFT)) & MTB_PERIPHID3_PERIPHID_MASK) 8019 /*! @} */ 8020 8021 /*! @name COMPID - Component ID Register */ 8022 /*! @{ */ 8023 #define MTB_COMPID_COMPID_MASK (0xFFFFFFFFU) 8024 #define MTB_COMPID_COMPID_SHIFT (0U) 8025 #define MTB_COMPID_COMPID(x) (((uint32_t)(((uint32_t)(x)) << MTB_COMPID_COMPID_SHIFT)) & MTB_COMPID_COMPID_MASK) 8026 /*! @} */ 8027 8028 /* The count of MTB_COMPID */ 8029 #define MTB_COMPID_COUNT (4U) 8030 8031 8032 /*! 8033 * @} 8034 */ /* end of group MTB_Register_Masks */ 8035 8036 8037 /* MTB - Peripheral instance base addresses */ 8038 /** Peripheral MTB base address */ 8039 #define MTB_BASE (0xF0000000u) 8040 /** Peripheral MTB base pointer */ 8041 #define MTB ((MTB_Type *)MTB_BASE) 8042 /** Array initializer of MTB peripheral base addresses */ 8043 #define MTB_BASE_ADDRS { MTB_BASE } 8044 /** Array initializer of MTB peripheral base pointers */ 8045 #define MTB_BASE_PTRS { MTB } 8046 8047 /*! 8048 * @} 8049 */ /* end of group MTB_Peripheral_Access_Layer */ 8050 8051 8052 /* ---------------------------------------------------------------------------- 8053 -- MTBDWT Peripheral Access Layer 8054 ---------------------------------------------------------------------------- */ 8055 8056 /*! 8057 * @addtogroup MTBDWT_Peripheral_Access_Layer MTBDWT Peripheral Access Layer 8058 * @{ 8059 */ 8060 8061 /** MTBDWT - Register Layout Typedef */ 8062 typedef struct { 8063 __I uint32_t CTRL; /**< MTB DWT Control Register, offset: 0x0 */ 8064 uint8_t RESERVED_0[28]; 8065 struct { /* offset: 0x20, array step: 0x10 */ 8066 __IO uint32_t COMP; /**< MTB_DWT Comparator Register, array offset: 0x20, array step: 0x10 */ 8067 __IO uint32_t MASK; /**< MTB_DWT Comparator Mask Register, array offset: 0x24, array step: 0x10 */ 8068 __IO uint32_t FCT; /**< MTB_DWT Comparator Function Register 0..MTB_DWT Comparator Function Register 1, array offset: 0x28, array step: 0x10 */ 8069 uint8_t RESERVED_0[4]; 8070 } COMPARATOR[2]; 8071 uint8_t RESERVED_1[448]; 8072 __IO uint32_t TBCTRL; /**< MTB_DWT Trace Buffer Control Register, offset: 0x200 */ 8073 uint8_t RESERVED_2[3524]; 8074 __I uint32_t DEVICECFG; /**< Device Configuration Register, offset: 0xFC8 */ 8075 __I uint32_t DEVICETYPID; /**< Device Type Identifier Register, offset: 0xFCC */ 8076 __I uint32_t PERIPHID4; /**< Peripheral ID Register, offset: 0xFD0 */ 8077 __I uint32_t PERIPHID5; /**< Peripheral ID Register, offset: 0xFD4 */ 8078 __I uint32_t PERIPHID6; /**< Peripheral ID Register, offset: 0xFD8 */ 8079 __I uint32_t PERIPHID7; /**< Peripheral ID Register, offset: 0xFDC */ 8080 __I uint32_t PERIPHID0; /**< Peripheral ID Register, offset: 0xFE0 */ 8081 __I uint32_t PERIPHID1; /**< Peripheral ID Register, offset: 0xFE4 */ 8082 __I uint32_t PERIPHID2; /**< Peripheral ID Register, offset: 0xFE8 */ 8083 __I uint32_t PERIPHID3; /**< Peripheral ID Register, offset: 0xFEC */ 8084 __I uint32_t COMPID[4]; /**< Component ID Register, array offset: 0xFF0, array step: 0x4 */ 8085 } MTBDWT_Type; 8086 8087 /* ---------------------------------------------------------------------------- 8088 -- MTBDWT Register Masks 8089 ---------------------------------------------------------------------------- */ 8090 8091 /*! 8092 * @addtogroup MTBDWT_Register_Masks MTBDWT Register Masks 8093 * @{ 8094 */ 8095 8096 /*! @name CTRL - MTB DWT Control Register */ 8097 /*! @{ */ 8098 #define MTBDWT_CTRL_DWTCFGCTRL_MASK (0xFFFFFFFU) 8099 #define MTBDWT_CTRL_DWTCFGCTRL_SHIFT (0U) 8100 #define MTBDWT_CTRL_DWTCFGCTRL(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_CTRL_DWTCFGCTRL_SHIFT)) & MTBDWT_CTRL_DWTCFGCTRL_MASK) 8101 #define MTBDWT_CTRL_NUMCMP_MASK (0xF0000000U) 8102 #define MTBDWT_CTRL_NUMCMP_SHIFT (28U) 8103 #define MTBDWT_CTRL_NUMCMP(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_CTRL_NUMCMP_SHIFT)) & MTBDWT_CTRL_NUMCMP_MASK) 8104 /*! @} */ 8105 8106 /*! @name COMP - MTB_DWT Comparator Register */ 8107 /*! @{ */ 8108 #define MTBDWT_COMP_COMP_MASK (0xFFFFFFFFU) 8109 #define MTBDWT_COMP_COMP_SHIFT (0U) 8110 #define MTBDWT_COMP_COMP(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_COMP_COMP_SHIFT)) & MTBDWT_COMP_COMP_MASK) 8111 /*! @} */ 8112 8113 /* The count of MTBDWT_COMP */ 8114 #define MTBDWT_COMP_COUNT (2U) 8115 8116 /*! @name MASK - MTB_DWT Comparator Mask Register */ 8117 /*! @{ */ 8118 #define MTBDWT_MASK_MASK_MASK (0x1FU) 8119 #define MTBDWT_MASK_MASK_SHIFT (0U) 8120 #define MTBDWT_MASK_MASK(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_MASK_MASK_SHIFT)) & MTBDWT_MASK_MASK_MASK) 8121 /*! @} */ 8122 8123 /* The count of MTBDWT_MASK */ 8124 #define MTBDWT_MASK_COUNT (2U) 8125 8126 /*! @name FCT - MTB_DWT Comparator Function Register 0..MTB_DWT Comparator Function Register 1 */ 8127 /*! @{ */ 8128 #define MTBDWT_FCT_FUNCTION_MASK (0xFU) 8129 #define MTBDWT_FCT_FUNCTION_SHIFT (0U) 8130 /*! FUNCTION - Function 8131 * 0b0000..Disabled. 8132 * 0b0100..Instruction fetch. 8133 * 0b0101..Data operand read. 8134 * 0b0110..Data operand write. 8135 * 0b0111..Data operand (read + write). 8136 */ 8137 #define MTBDWT_FCT_FUNCTION(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_FCT_FUNCTION_SHIFT)) & MTBDWT_FCT_FUNCTION_MASK) 8138 #define MTBDWT_FCT_DATAVMATCH_MASK (0x100U) 8139 #define MTBDWT_FCT_DATAVMATCH_SHIFT (8U) 8140 /*! DATAVMATCH - Data Value Match 8141 * 0b0..Perform address comparison. 8142 * 0b1..Perform data value comparison. 8143 */ 8144 #define MTBDWT_FCT_DATAVMATCH(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_FCT_DATAVMATCH_SHIFT)) & MTBDWT_FCT_DATAVMATCH_MASK) 8145 #define MTBDWT_FCT_DATAVSIZE_MASK (0xC00U) 8146 #define MTBDWT_FCT_DATAVSIZE_SHIFT (10U) 8147 /*! DATAVSIZE - Data Value Size 8148 * 0b00..Byte. 8149 * 0b01..Halfword. 8150 * 0b10..Word. 8151 * 0b11..Reserved. Any attempts to use this value results in UNPREDICTABLE behavior. 8152 */ 8153 #define MTBDWT_FCT_DATAVSIZE(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_FCT_DATAVSIZE_SHIFT)) & MTBDWT_FCT_DATAVSIZE_MASK) 8154 #define MTBDWT_FCT_DATAVADDR0_MASK (0xF000U) 8155 #define MTBDWT_FCT_DATAVADDR0_SHIFT (12U) 8156 #define MTBDWT_FCT_DATAVADDR0(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_FCT_DATAVADDR0_SHIFT)) & MTBDWT_FCT_DATAVADDR0_MASK) 8157 #define MTBDWT_FCT_MATCHED_MASK (0x1000000U) 8158 #define MTBDWT_FCT_MATCHED_SHIFT (24U) 8159 /*! MATCHED - Comparator match 8160 * 0b0..No match. 8161 * 0b1..Match occurred. 8162 */ 8163 #define MTBDWT_FCT_MATCHED(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_FCT_MATCHED_SHIFT)) & MTBDWT_FCT_MATCHED_MASK) 8164 /*! @} */ 8165 8166 /* The count of MTBDWT_FCT */ 8167 #define MTBDWT_FCT_COUNT (2U) 8168 8169 /*! @name TBCTRL - MTB_DWT Trace Buffer Control Register */ 8170 /*! @{ */ 8171 #define MTBDWT_TBCTRL_ACOMP0_MASK (0x1U) 8172 #define MTBDWT_TBCTRL_ACOMP0_SHIFT (0U) 8173 /*! ACOMP0 - Action based on Comparator 0 match 8174 * 0b0..Trigger TSTOP based on the assertion of MTBDWT_FCT0[MATCHED]. 8175 * 0b1..Trigger TSTART based on the assertion of MTBDWT_FCT0[MATCHED]. 8176 */ 8177 #define MTBDWT_TBCTRL_ACOMP0(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_TBCTRL_ACOMP0_SHIFT)) & MTBDWT_TBCTRL_ACOMP0_MASK) 8178 #define MTBDWT_TBCTRL_ACOMP1_MASK (0x2U) 8179 #define MTBDWT_TBCTRL_ACOMP1_SHIFT (1U) 8180 /*! ACOMP1 - Action based on Comparator 1 match 8181 * 0b0..Trigger TSTOP based on the assertion of MTBDWT_FCT1[MATCHED]. 8182 * 0b1..Trigger TSTART based on the assertion of MTBDWT_FCT1[MATCHED]. 8183 */ 8184 #define MTBDWT_TBCTRL_ACOMP1(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_TBCTRL_ACOMP1_SHIFT)) & MTBDWT_TBCTRL_ACOMP1_MASK) 8185 #define MTBDWT_TBCTRL_NUMCOMP_MASK (0xF0000000U) 8186 #define MTBDWT_TBCTRL_NUMCOMP_SHIFT (28U) 8187 #define MTBDWT_TBCTRL_NUMCOMP(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_TBCTRL_NUMCOMP_SHIFT)) & MTBDWT_TBCTRL_NUMCOMP_MASK) 8188 /*! @} */ 8189 8190 /*! @name DEVICECFG - Device Configuration Register */ 8191 /*! @{ */ 8192 #define MTBDWT_DEVICECFG_DEVICECFG_MASK (0xFFFFFFFFU) 8193 #define MTBDWT_DEVICECFG_DEVICECFG_SHIFT (0U) 8194 #define MTBDWT_DEVICECFG_DEVICECFG(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_DEVICECFG_DEVICECFG_SHIFT)) & MTBDWT_DEVICECFG_DEVICECFG_MASK) 8195 /*! @} */ 8196 8197 /*! @name DEVICETYPID - Device Type Identifier Register */ 8198 /*! @{ */ 8199 #define MTBDWT_DEVICETYPID_DEVICETYPID_MASK (0xFFFFFFFFU) 8200 #define MTBDWT_DEVICETYPID_DEVICETYPID_SHIFT (0U) 8201 #define MTBDWT_DEVICETYPID_DEVICETYPID(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_DEVICETYPID_DEVICETYPID_SHIFT)) & MTBDWT_DEVICETYPID_DEVICETYPID_MASK) 8202 /*! @} */ 8203 8204 /*! @name PERIPHID4 - Peripheral ID Register */ 8205 /*! @{ */ 8206 #define MTBDWT_PERIPHID4_PERIPHID_MASK (0xFFFFFFFFU) 8207 #define MTBDWT_PERIPHID4_PERIPHID_SHIFT (0U) 8208 #define MTBDWT_PERIPHID4_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_PERIPHID4_PERIPHID_SHIFT)) & MTBDWT_PERIPHID4_PERIPHID_MASK) 8209 /*! @} */ 8210 8211 /*! @name PERIPHID5 - Peripheral ID Register */ 8212 /*! @{ */ 8213 #define MTBDWT_PERIPHID5_PERIPHID_MASK (0xFFFFFFFFU) 8214 #define MTBDWT_PERIPHID5_PERIPHID_SHIFT (0U) 8215 #define MTBDWT_PERIPHID5_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_PERIPHID5_PERIPHID_SHIFT)) & MTBDWT_PERIPHID5_PERIPHID_MASK) 8216 /*! @} */ 8217 8218 /*! @name PERIPHID6 - Peripheral ID Register */ 8219 /*! @{ */ 8220 #define MTBDWT_PERIPHID6_PERIPHID_MASK (0xFFFFFFFFU) 8221 #define MTBDWT_PERIPHID6_PERIPHID_SHIFT (0U) 8222 #define MTBDWT_PERIPHID6_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_PERIPHID6_PERIPHID_SHIFT)) & MTBDWT_PERIPHID6_PERIPHID_MASK) 8223 /*! @} */ 8224 8225 /*! @name PERIPHID7 - Peripheral ID Register */ 8226 /*! @{ */ 8227 #define MTBDWT_PERIPHID7_PERIPHID_MASK (0xFFFFFFFFU) 8228 #define MTBDWT_PERIPHID7_PERIPHID_SHIFT (0U) 8229 #define MTBDWT_PERIPHID7_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_PERIPHID7_PERIPHID_SHIFT)) & MTBDWT_PERIPHID7_PERIPHID_MASK) 8230 /*! @} */ 8231 8232 /*! @name PERIPHID0 - Peripheral ID Register */ 8233 /*! @{ */ 8234 #define MTBDWT_PERIPHID0_PERIPHID_MASK (0xFFFFFFFFU) 8235 #define MTBDWT_PERIPHID0_PERIPHID_SHIFT (0U) 8236 #define MTBDWT_PERIPHID0_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_PERIPHID0_PERIPHID_SHIFT)) & MTBDWT_PERIPHID0_PERIPHID_MASK) 8237 /*! @} */ 8238 8239 /*! @name PERIPHID1 - Peripheral ID Register */ 8240 /*! @{ */ 8241 #define MTBDWT_PERIPHID1_PERIPHID_MASK (0xFFFFFFFFU) 8242 #define MTBDWT_PERIPHID1_PERIPHID_SHIFT (0U) 8243 #define MTBDWT_PERIPHID1_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_PERIPHID1_PERIPHID_SHIFT)) & MTBDWT_PERIPHID1_PERIPHID_MASK) 8244 /*! @} */ 8245 8246 /*! @name PERIPHID2 - Peripheral ID Register */ 8247 /*! @{ */ 8248 #define MTBDWT_PERIPHID2_PERIPHID_MASK (0xFFFFFFFFU) 8249 #define MTBDWT_PERIPHID2_PERIPHID_SHIFT (0U) 8250 #define MTBDWT_PERIPHID2_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_PERIPHID2_PERIPHID_SHIFT)) & MTBDWT_PERIPHID2_PERIPHID_MASK) 8251 /*! @} */ 8252 8253 /*! @name PERIPHID3 - Peripheral ID Register */ 8254 /*! @{ */ 8255 #define MTBDWT_PERIPHID3_PERIPHID_MASK (0xFFFFFFFFU) 8256 #define MTBDWT_PERIPHID3_PERIPHID_SHIFT (0U) 8257 #define MTBDWT_PERIPHID3_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_PERIPHID3_PERIPHID_SHIFT)) & MTBDWT_PERIPHID3_PERIPHID_MASK) 8258 /*! @} */ 8259 8260 /*! @name COMPID - Component ID Register */ 8261 /*! @{ */ 8262 #define MTBDWT_COMPID_COMPID_MASK (0xFFFFFFFFU) 8263 #define MTBDWT_COMPID_COMPID_SHIFT (0U) 8264 #define MTBDWT_COMPID_COMPID(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_COMPID_COMPID_SHIFT)) & MTBDWT_COMPID_COMPID_MASK) 8265 /*! @} */ 8266 8267 /* The count of MTBDWT_COMPID */ 8268 #define MTBDWT_COMPID_COUNT (4U) 8269 8270 8271 /*! 8272 * @} 8273 */ /* end of group MTBDWT_Register_Masks */ 8274 8275 8276 /* MTBDWT - Peripheral instance base addresses */ 8277 /** Peripheral MTBDWT base address */ 8278 #define MTBDWT_BASE (0xF0001000u) 8279 /** Peripheral MTBDWT base pointer */ 8280 #define MTBDWT ((MTBDWT_Type *)MTBDWT_BASE) 8281 /** Array initializer of MTBDWT peripheral base addresses */ 8282 #define MTBDWT_BASE_ADDRS { MTBDWT_BASE } 8283 /** Array initializer of MTBDWT peripheral base pointers */ 8284 #define MTBDWT_BASE_PTRS { MTBDWT } 8285 8286 /*! 8287 * @} 8288 */ /* end of group MTBDWT_Peripheral_Access_Layer */ 8289 8290 8291 /* ---------------------------------------------------------------------------- 8292 -- NV Peripheral Access Layer 8293 ---------------------------------------------------------------------------- */ 8294 8295 /*! 8296 * @addtogroup NV_Peripheral_Access_Layer NV Peripheral Access Layer 8297 * @{ 8298 */ 8299 8300 /** NV - Register Layout Typedef */ 8301 typedef struct { 8302 __I uint8_t BACKKEY3; /**< Backdoor Comparison Key 3., offset: 0x0 */ 8303 __I uint8_t BACKKEY2; /**< Backdoor Comparison Key 2., offset: 0x1 */ 8304 __I uint8_t BACKKEY1; /**< Backdoor Comparison Key 1., offset: 0x2 */ 8305 __I uint8_t BACKKEY0; /**< Backdoor Comparison Key 0., offset: 0x3 */ 8306 __I uint8_t BACKKEY7; /**< Backdoor Comparison Key 7., offset: 0x4 */ 8307 __I uint8_t BACKKEY6; /**< Backdoor Comparison Key 6., offset: 0x5 */ 8308 __I uint8_t BACKKEY5; /**< Backdoor Comparison Key 5., offset: 0x6 */ 8309 __I uint8_t BACKKEY4; /**< Backdoor Comparison Key 4., offset: 0x7 */ 8310 __I uint8_t FPROT3; /**< Non-volatile P-Flash Protection 1 - Low Register, offset: 0x8 */ 8311 __I uint8_t FPROT2; /**< Non-volatile P-Flash Protection 1 - High Register, offset: 0x9 */ 8312 __I uint8_t FPROT1; /**< Non-volatile P-Flash Protection 0 - Low Register, offset: 0xA */ 8313 __I uint8_t FPROT0; /**< Non-volatile P-Flash Protection 0 - High Register, offset: 0xB */ 8314 __I uint8_t FSEC; /**< Non-volatile Flash Security Register, offset: 0xC */ 8315 __I uint8_t FOPT; /**< Non-volatile Flash Option Register, offset: 0xD */ 8316 } NV_Type; 8317 8318 /* ---------------------------------------------------------------------------- 8319 -- NV Register Masks 8320 ---------------------------------------------------------------------------- */ 8321 8322 /*! 8323 * @addtogroup NV_Register_Masks NV Register Masks 8324 * @{ 8325 */ 8326 8327 /*! @name BACKKEY3 - Backdoor Comparison Key 3. */ 8328 /*! @{ */ 8329 #define NV_BACKKEY3_KEY_MASK (0xFFU) 8330 #define NV_BACKKEY3_KEY_SHIFT (0U) 8331 #define NV_BACKKEY3_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY3_KEY_SHIFT)) & NV_BACKKEY3_KEY_MASK) 8332 /*! @} */ 8333 8334 /*! @name BACKKEY2 - Backdoor Comparison Key 2. */ 8335 /*! @{ */ 8336 #define NV_BACKKEY2_KEY_MASK (0xFFU) 8337 #define NV_BACKKEY2_KEY_SHIFT (0U) 8338 #define NV_BACKKEY2_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY2_KEY_SHIFT)) & NV_BACKKEY2_KEY_MASK) 8339 /*! @} */ 8340 8341 /*! @name BACKKEY1 - Backdoor Comparison Key 1. */ 8342 /*! @{ */ 8343 #define NV_BACKKEY1_KEY_MASK (0xFFU) 8344 #define NV_BACKKEY1_KEY_SHIFT (0U) 8345 #define NV_BACKKEY1_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY1_KEY_SHIFT)) & NV_BACKKEY1_KEY_MASK) 8346 /*! @} */ 8347 8348 /*! @name BACKKEY0 - Backdoor Comparison Key 0. */ 8349 /*! @{ */ 8350 #define NV_BACKKEY0_KEY_MASK (0xFFU) 8351 #define NV_BACKKEY0_KEY_SHIFT (0U) 8352 #define NV_BACKKEY0_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY0_KEY_SHIFT)) & NV_BACKKEY0_KEY_MASK) 8353 /*! @} */ 8354 8355 /*! @name BACKKEY7 - Backdoor Comparison Key 7. */ 8356 /*! @{ */ 8357 #define NV_BACKKEY7_KEY_MASK (0xFFU) 8358 #define NV_BACKKEY7_KEY_SHIFT (0U) 8359 #define NV_BACKKEY7_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY7_KEY_SHIFT)) & NV_BACKKEY7_KEY_MASK) 8360 /*! @} */ 8361 8362 /*! @name BACKKEY6 - Backdoor Comparison Key 6. */ 8363 /*! @{ */ 8364 #define NV_BACKKEY6_KEY_MASK (0xFFU) 8365 #define NV_BACKKEY6_KEY_SHIFT (0U) 8366 #define NV_BACKKEY6_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY6_KEY_SHIFT)) & NV_BACKKEY6_KEY_MASK) 8367 /*! @} */ 8368 8369 /*! @name BACKKEY5 - Backdoor Comparison Key 5. */ 8370 /*! @{ */ 8371 #define NV_BACKKEY5_KEY_MASK (0xFFU) 8372 #define NV_BACKKEY5_KEY_SHIFT (0U) 8373 #define NV_BACKKEY5_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY5_KEY_SHIFT)) & NV_BACKKEY5_KEY_MASK) 8374 /*! @} */ 8375 8376 /*! @name BACKKEY4 - Backdoor Comparison Key 4. */ 8377 /*! @{ */ 8378 #define NV_BACKKEY4_KEY_MASK (0xFFU) 8379 #define NV_BACKKEY4_KEY_SHIFT (0U) 8380 #define NV_BACKKEY4_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY4_KEY_SHIFT)) & NV_BACKKEY4_KEY_MASK) 8381 /*! @} */ 8382 8383 /*! @name FPROT3 - Non-volatile P-Flash Protection 1 - Low Register */ 8384 /*! @{ */ 8385 #define NV_FPROT3_PROT_MASK (0xFFU) 8386 #define NV_FPROT3_PROT_SHIFT (0U) 8387 #define NV_FPROT3_PROT(x) (((uint8_t)(((uint8_t)(x)) << NV_FPROT3_PROT_SHIFT)) & NV_FPROT3_PROT_MASK) 8388 /*! @} */ 8389 8390 /*! @name FPROT2 - Non-volatile P-Flash Protection 1 - High Register */ 8391 /*! @{ */ 8392 #define NV_FPROT2_PROT_MASK (0xFFU) 8393 #define NV_FPROT2_PROT_SHIFT (0U) 8394 #define NV_FPROT2_PROT(x) (((uint8_t)(((uint8_t)(x)) << NV_FPROT2_PROT_SHIFT)) & NV_FPROT2_PROT_MASK) 8395 /*! @} */ 8396 8397 /*! @name FPROT1 - Non-volatile P-Flash Protection 0 - Low Register */ 8398 /*! @{ */ 8399 #define NV_FPROT1_PROT_MASK (0xFFU) 8400 #define NV_FPROT1_PROT_SHIFT (0U) 8401 #define NV_FPROT1_PROT(x) (((uint8_t)(((uint8_t)(x)) << NV_FPROT1_PROT_SHIFT)) & NV_FPROT1_PROT_MASK) 8402 /*! @} */ 8403 8404 /*! @name FPROT0 - Non-volatile P-Flash Protection 0 - High Register */ 8405 /*! @{ */ 8406 #define NV_FPROT0_PROT_MASK (0xFFU) 8407 #define NV_FPROT0_PROT_SHIFT (0U) 8408 #define NV_FPROT0_PROT(x) (((uint8_t)(((uint8_t)(x)) << NV_FPROT0_PROT_SHIFT)) & NV_FPROT0_PROT_MASK) 8409 /*! @} */ 8410 8411 /*! @name FSEC - Non-volatile Flash Security Register */ 8412 /*! @{ */ 8413 #define NV_FSEC_SEC_MASK (0x3U) 8414 #define NV_FSEC_SEC_SHIFT (0U) 8415 /*! SEC - Flash Security 8416 * 0b10..MCU security status is unsecure 8417 * 0b11..MCU security status is secure 8418 */ 8419 #define NV_FSEC_SEC(x) (((uint8_t)(((uint8_t)(x)) << NV_FSEC_SEC_SHIFT)) & NV_FSEC_SEC_MASK) 8420 #define NV_FSEC_FSLACC_MASK (0xCU) 8421 #define NV_FSEC_FSLACC_SHIFT (2U) 8422 /*! FSLACC - Freescale Failure Analysis Access Code 8423 * 0b10..Freescale factory access denied 8424 * 0b11..Freescale factory access granted 8425 */ 8426 #define NV_FSEC_FSLACC(x) (((uint8_t)(((uint8_t)(x)) << NV_FSEC_FSLACC_SHIFT)) & NV_FSEC_FSLACC_MASK) 8427 #define NV_FSEC_MEEN_MASK (0x30U) 8428 #define NV_FSEC_MEEN_SHIFT (4U) 8429 /*! MEEN 8430 * 0b10..Mass erase is disabled 8431 * 0b11..Mass erase is enabled 8432 */ 8433 #define NV_FSEC_MEEN(x) (((uint8_t)(((uint8_t)(x)) << NV_FSEC_MEEN_SHIFT)) & NV_FSEC_MEEN_MASK) 8434 #define NV_FSEC_KEYEN_MASK (0xC0U) 8435 #define NV_FSEC_KEYEN_SHIFT (6U) 8436 /*! KEYEN - Backdoor Key Security Enable 8437 * 0b10..Backdoor key access enabled 8438 * 0b11..Backdoor key access disabled 8439 */ 8440 #define NV_FSEC_KEYEN(x) (((uint8_t)(((uint8_t)(x)) << NV_FSEC_KEYEN_SHIFT)) & NV_FSEC_KEYEN_MASK) 8441 /*! @} */ 8442 8443 /*! @name FOPT - Non-volatile Flash Option Register */ 8444 /*! @{ */ 8445 #define NV_FOPT_LPBOOT0_MASK (0x1U) 8446 #define NV_FOPT_LPBOOT0_SHIFT (0U) 8447 /*! LPBOOT0 8448 * 0b0..Core and system clock divider (OUTDIV1) is 0x7 (divide by 8) when LPBOOT1=0 or 0x1 (divide by 2) when LPBOOT1=1. 8449 * 0b1..Core and system clock divider (OUTDIV1) is 0x3 (divide by 4) when LPBOOT1=0 or 0x0 (divide by 1) when LPBOOT1=1. 8450 */ 8451 #define NV_FOPT_LPBOOT0(x) (((uint8_t)(((uint8_t)(x)) << NV_FOPT_LPBOOT0_SHIFT)) & NV_FOPT_LPBOOT0_MASK) 8452 #define NV_FOPT_NMI_DIS_MASK (0x4U) 8453 #define NV_FOPT_NMI_DIS_SHIFT (2U) 8454 /*! NMI_DIS 8455 * 0b0..NMI interrupts are always blocked 8456 * 0b1..NMI_b pin/interrupts reset default to enabled 8457 */ 8458 #define NV_FOPT_NMI_DIS(x) (((uint8_t)(((uint8_t)(x)) << NV_FOPT_NMI_DIS_SHIFT)) & NV_FOPT_NMI_DIS_MASK) 8459 #define NV_FOPT_RESET_PIN_CFG_MASK (0x8U) 8460 #define NV_FOPT_RESET_PIN_CFG_SHIFT (3U) 8461 /*! RESET_PIN_CFG 8462 * 0b0..RESET pin is disabled following a POR and cannot be enabled as reset function 8463 * 0b1..RESET_b pin is dedicated 8464 */ 8465 #define NV_FOPT_RESET_PIN_CFG(x) (((uint8_t)(((uint8_t)(x)) << NV_FOPT_RESET_PIN_CFG_SHIFT)) & NV_FOPT_RESET_PIN_CFG_MASK) 8466 #define NV_FOPT_LPBOOT1_MASK (0x10U) 8467 #define NV_FOPT_LPBOOT1_SHIFT (4U) 8468 /*! LPBOOT1 8469 * 0b0..Core and system clock divider (OUTDIV1) is 0x7 (divide by 8) when LPBOOT0=0 or 0x3 (divide by 4) when LPBOOT0=1. 8470 * 0b1..Core and system clock divider (OUTDIV1) is 0x1 (divide by 2) when LPBOOT0=0 or 0x0 (divide by 1) when LPBOOT0=1. 8471 */ 8472 #define NV_FOPT_LPBOOT1(x) (((uint8_t)(((uint8_t)(x)) << NV_FOPT_LPBOOT1_SHIFT)) & NV_FOPT_LPBOOT1_MASK) 8473 #define NV_FOPT_FAST_INIT_MASK (0x20U) 8474 #define NV_FOPT_FAST_INIT_SHIFT (5U) 8475 /*! FAST_INIT 8476 * 0b0..Slower initialization 8477 * 0b1..Fast Initialization 8478 */ 8479 #define NV_FOPT_FAST_INIT(x) (((uint8_t)(((uint8_t)(x)) << NV_FOPT_FAST_INIT_SHIFT)) & NV_FOPT_FAST_INIT_MASK) 8480 /*! @} */ 8481 8482 8483 /*! 8484 * @} 8485 */ /* end of group NV_Register_Masks */ 8486 8487 8488 /* NV - Peripheral instance base addresses */ 8489 /** Peripheral FTFA_FlashConfig base address */ 8490 #define FTFA_FlashConfig_BASE (0x400u) 8491 /** Peripheral FTFA_FlashConfig base pointer */ 8492 #define FTFA_FlashConfig ((NV_Type *)FTFA_FlashConfig_BASE) 8493 /** Array initializer of NV peripheral base addresses */ 8494 #define NV_BASE_ADDRS { FTFA_FlashConfig_BASE } 8495 /** Array initializer of NV peripheral base pointers */ 8496 #define NV_BASE_PTRS { FTFA_FlashConfig } 8497 8498 /*! 8499 * @} 8500 */ /* end of group NV_Peripheral_Access_Layer */ 8501 8502 8503 /* ---------------------------------------------------------------------------- 8504 -- OSC Peripheral Access Layer 8505 ---------------------------------------------------------------------------- */ 8506 8507 /*! 8508 * @addtogroup OSC_Peripheral_Access_Layer OSC Peripheral Access Layer 8509 * @{ 8510 */ 8511 8512 /** OSC - Register Layout Typedef */ 8513 typedef struct { 8514 __IO uint8_t CR; /**< OSC Control Register, offset: 0x0 */ 8515 } OSC_Type; 8516 8517 /* ---------------------------------------------------------------------------- 8518 -- OSC Register Masks 8519 ---------------------------------------------------------------------------- */ 8520 8521 /*! 8522 * @addtogroup OSC_Register_Masks OSC Register Masks 8523 * @{ 8524 */ 8525 8526 /*! @name CR - OSC Control Register */ 8527 /*! @{ */ 8528 #define OSC_CR_SC16P_MASK (0x1U) 8529 #define OSC_CR_SC16P_SHIFT (0U) 8530 /*! SC16P - Oscillator 16 pF Capacitor Load Configure 8531 * 0b0..Disable the selection. 8532 * 0b1..Add 16 pF capacitor to the oscillator load. 8533 */ 8534 #define OSC_CR_SC16P(x) (((uint8_t)(((uint8_t)(x)) << OSC_CR_SC16P_SHIFT)) & OSC_CR_SC16P_MASK) 8535 #define OSC_CR_SC8P_MASK (0x2U) 8536 #define OSC_CR_SC8P_SHIFT (1U) 8537 /*! SC8P - Oscillator 8 pF Capacitor Load Configure 8538 * 0b0..Disable the selection. 8539 * 0b1..Add 8 pF capacitor to the oscillator load. 8540 */ 8541 #define OSC_CR_SC8P(x) (((uint8_t)(((uint8_t)(x)) << OSC_CR_SC8P_SHIFT)) & OSC_CR_SC8P_MASK) 8542 #define OSC_CR_SC4P_MASK (0x4U) 8543 #define OSC_CR_SC4P_SHIFT (2U) 8544 /*! SC4P - Oscillator 4 pF Capacitor Load Configure 8545 * 0b0..Disable the selection. 8546 * 0b1..Add 4 pF capacitor to the oscillator load. 8547 */ 8548 #define OSC_CR_SC4P(x) (((uint8_t)(((uint8_t)(x)) << OSC_CR_SC4P_SHIFT)) & OSC_CR_SC4P_MASK) 8549 #define OSC_CR_SC2P_MASK (0x8U) 8550 #define OSC_CR_SC2P_SHIFT (3U) 8551 /*! SC2P - Oscillator 2 pF Capacitor Load Configure 8552 * 0b0..Disable the selection. 8553 * 0b1..Add 2 pF capacitor to the oscillator load. 8554 */ 8555 #define OSC_CR_SC2P(x) (((uint8_t)(((uint8_t)(x)) << OSC_CR_SC2P_SHIFT)) & OSC_CR_SC2P_MASK) 8556 #define OSC_CR_EREFSTEN_MASK (0x20U) 8557 #define OSC_CR_EREFSTEN_SHIFT (5U) 8558 /*! EREFSTEN - External Reference Stop Enable 8559 * 0b0..External reference clock is disabled in Stop mode. 8560 * 0b1..External reference clock stays enabled in Stop mode if ERCLKEN is set before entering Stop mode. 8561 */ 8562 #define OSC_CR_EREFSTEN(x) (((uint8_t)(((uint8_t)(x)) << OSC_CR_EREFSTEN_SHIFT)) & OSC_CR_EREFSTEN_MASK) 8563 #define OSC_CR_ERCLKEN_MASK (0x80U) 8564 #define OSC_CR_ERCLKEN_SHIFT (7U) 8565 /*! ERCLKEN - External Reference Enable 8566 * 0b0..External reference clock is inactive. 8567 * 0b1..External reference clock is enabled. 8568 */ 8569 #define OSC_CR_ERCLKEN(x) (((uint8_t)(((uint8_t)(x)) << OSC_CR_ERCLKEN_SHIFT)) & OSC_CR_ERCLKEN_MASK) 8570 /*! @} */ 8571 8572 8573 /*! 8574 * @} 8575 */ /* end of group OSC_Register_Masks */ 8576 8577 8578 /* OSC - Peripheral instance base addresses */ 8579 /** Peripheral OSC0 base address */ 8580 #define OSC0_BASE (0x40065000u) 8581 /** Peripheral OSC0 base pointer */ 8582 #define OSC0 ((OSC_Type *)OSC0_BASE) 8583 /** Array initializer of OSC peripheral base addresses */ 8584 #define OSC_BASE_ADDRS { OSC0_BASE } 8585 /** Array initializer of OSC peripheral base pointers */ 8586 #define OSC_BASE_PTRS { OSC0 } 8587 8588 /*! 8589 * @} 8590 */ /* end of group OSC_Peripheral_Access_Layer */ 8591 8592 8593 /* ---------------------------------------------------------------------------- 8594 -- PDB Peripheral Access Layer 8595 ---------------------------------------------------------------------------- */ 8596 8597 /*! 8598 * @addtogroup PDB_Peripheral_Access_Layer PDB Peripheral Access Layer 8599 * @{ 8600 */ 8601 8602 /** PDB - Register Layout Typedef */ 8603 typedef struct { 8604 __IO uint32_t SC; /**< Status and Control register, offset: 0x0 */ 8605 __IO uint32_t MOD; /**< Modulus register, offset: 0x4 */ 8606 __I uint32_t CNT; /**< Counter register, offset: 0x8 */ 8607 __IO uint32_t IDLY; /**< Interrupt Delay register, offset: 0xC */ 8608 struct { /* offset: 0x10, array step: 0x28 */ 8609 __IO uint32_t C1; /**< Channel n Control register 1, array offset: 0x10, array step: 0x28 */ 8610 __IO uint32_t S; /**< Channel n Status register, array offset: 0x14, array step: 0x28 */ 8611 __IO uint32_t DLY[2]; /**< Channel n Delay 0 register..Channel n Delay 1 register, array offset: 0x18, array step: index*0x28, index2*0x4 */ 8612 uint8_t RESERVED_0[24]; 8613 } CH[2]; 8614 uint8_t RESERVED_0[240]; 8615 struct { /* offset: 0x150, array step: 0x8 */ 8616 __IO uint32_t INTC; /**< DAC Interval Trigger n Control register, array offset: 0x150, array step: 0x8 */ 8617 __IO uint32_t INT; /**< DAC Interval n register, array offset: 0x154, array step: 0x8 */ 8618 } DAC[1]; 8619 uint8_t RESERVED_1[56]; 8620 __IO uint32_t POEN; /**< Pulse-Out n Enable register, offset: 0x190 */ 8621 __IO uint32_t PODLY[2]; /**< Pulse-Out n Delay register, array offset: 0x194, array step: 0x4 */ 8622 } PDB_Type; 8623 8624 /* ---------------------------------------------------------------------------- 8625 -- PDB Register Masks 8626 ---------------------------------------------------------------------------- */ 8627 8628 /*! 8629 * @addtogroup PDB_Register_Masks PDB Register Masks 8630 * @{ 8631 */ 8632 8633 /*! @name SC - Status and Control register */ 8634 /*! @{ */ 8635 #define PDB_SC_LDOK_MASK (0x1U) 8636 #define PDB_SC_LDOK_SHIFT (0U) 8637 #define PDB_SC_LDOK(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_LDOK_SHIFT)) & PDB_SC_LDOK_MASK) 8638 #define PDB_SC_CONT_MASK (0x2U) 8639 #define PDB_SC_CONT_SHIFT (1U) 8640 /*! CONT - Continuous Mode Enable 8641 * 0b0..PDB operation in One-Shot mode 8642 * 0b1..PDB operation in Continuous mode 8643 */ 8644 #define PDB_SC_CONT(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_CONT_SHIFT)) & PDB_SC_CONT_MASK) 8645 #define PDB_SC_MULT_MASK (0xCU) 8646 #define PDB_SC_MULT_SHIFT (2U) 8647 /*! MULT - Multiplication Factor Select for Prescaler 8648 * 0b00..Multiplication factor is 1. 8649 * 0b01..Multiplication factor is 10. 8650 * 0b10..Multiplication factor is 20. 8651 * 0b11..Multiplication factor is 40. 8652 */ 8653 #define PDB_SC_MULT(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_MULT_SHIFT)) & PDB_SC_MULT_MASK) 8654 #define PDB_SC_PDBIE_MASK (0x20U) 8655 #define PDB_SC_PDBIE_SHIFT (5U) 8656 /*! PDBIE - PDB Interrupt Enable 8657 * 0b0..PDB interrupt disabled. 8658 * 0b1..PDB interrupt enabled. 8659 */ 8660 #define PDB_SC_PDBIE(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_PDBIE_SHIFT)) & PDB_SC_PDBIE_MASK) 8661 #define PDB_SC_PDBIF_MASK (0x40U) 8662 #define PDB_SC_PDBIF_SHIFT (6U) 8663 #define PDB_SC_PDBIF(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_PDBIF_SHIFT)) & PDB_SC_PDBIF_MASK) 8664 #define PDB_SC_PDBEN_MASK (0x80U) 8665 #define PDB_SC_PDBEN_SHIFT (7U) 8666 /*! PDBEN - PDB Enable 8667 * 0b0..PDB disabled. Counter is off. 8668 * 0b1..PDB enabled. 8669 */ 8670 #define PDB_SC_PDBEN(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_PDBEN_SHIFT)) & PDB_SC_PDBEN_MASK) 8671 #define PDB_SC_TRGSEL_MASK (0xF00U) 8672 #define PDB_SC_TRGSEL_SHIFT (8U) 8673 /*! TRGSEL - Trigger Input Source Select 8674 * 0b0000..Trigger-In 0 is selected. 8675 * 0b0001..Trigger-In 1 is selected. 8676 * 0b0010..Trigger-In 2 is selected. 8677 * 0b0011..Trigger-In 3 is selected. 8678 * 0b0100..Trigger-In 4 is selected. 8679 * 0b0101..Trigger-In 5 is selected. 8680 * 0b0110..Trigger-In 6 is selected. 8681 * 0b0111..Trigger-In 7 is selected. 8682 * 0b1000..Trigger-In 8 is selected. 8683 * 0b1001..Trigger-In 9 is selected. 8684 * 0b1010..Trigger-In 10 is selected. 8685 * 0b1011..Trigger-In 11 is selected. 8686 * 0b1100..Trigger-In 12 is selected. 8687 * 0b1101..Trigger-In 13 is selected. 8688 * 0b1110..Trigger-In 14 is selected. 8689 * 0b1111..Software trigger is selected. 8690 */ 8691 #define PDB_SC_TRGSEL(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_TRGSEL_SHIFT)) & PDB_SC_TRGSEL_MASK) 8692 #define PDB_SC_PRESCALER_MASK (0x7000U) 8693 #define PDB_SC_PRESCALER_SHIFT (12U) 8694 /*! PRESCALER - Prescaler Divider Select 8695 * 0b000..Counting uses the peripheral clock divided by multiplication factor selected by MULT. 8696 * 0b001..Counting uses the peripheral clock divided by twice of the multiplication factor selected by MULT. 8697 * 0b010..Counting uses the peripheral clock divided by four times of the multiplication factor selected by MULT. 8698 * 0b011..Counting uses the peripheral clock divided by eight times of the multiplication factor selected by MULT. 8699 * 0b100..Counting uses the peripheral clock divided by 16 times of the multiplication factor selected by MULT. 8700 * 0b101..Counting uses the peripheral clock divided by 32 times of the multiplication factor selected by MULT. 8701 * 0b110..Counting uses the peripheral clock divided by 64 times of the multiplication factor selected by MULT. 8702 * 0b111..Counting uses the peripheral clock divided by 128 times of the multiplication factor selected by MULT. 8703 */ 8704 #define PDB_SC_PRESCALER(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_PRESCALER_SHIFT)) & PDB_SC_PRESCALER_MASK) 8705 #define PDB_SC_DMAEN_MASK (0x8000U) 8706 #define PDB_SC_DMAEN_SHIFT (15U) 8707 /*! DMAEN - DMA Enable 8708 * 0b0..DMA disabled. 8709 * 0b1..DMA enabled. 8710 */ 8711 #define PDB_SC_DMAEN(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_DMAEN_SHIFT)) & PDB_SC_DMAEN_MASK) 8712 #define PDB_SC_SWTRIG_MASK (0x10000U) 8713 #define PDB_SC_SWTRIG_SHIFT (16U) 8714 #define PDB_SC_SWTRIG(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_SWTRIG_SHIFT)) & PDB_SC_SWTRIG_MASK) 8715 #define PDB_SC_PDBEIE_MASK (0x20000U) 8716 #define PDB_SC_PDBEIE_SHIFT (17U) 8717 /*! PDBEIE - PDB Sequence Error Interrupt Enable 8718 * 0b0..PDB sequence error interrupt disabled. 8719 * 0b1..PDB sequence error interrupt enabled. 8720 */ 8721 #define PDB_SC_PDBEIE(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_PDBEIE_SHIFT)) & PDB_SC_PDBEIE_MASK) 8722 #define PDB_SC_LDMOD_MASK (0xC0000U) 8723 #define PDB_SC_LDMOD_SHIFT (18U) 8724 /*! LDMOD - Load Mode Select 8725 * 0b00..The internal registers are loaded with the values from their buffers immediately after 1 is written to LDOK. 8726 * 0b01..The internal registers are loaded with the values from their buffers when the PDB counter reaches the MOD register value after 1 is written to LDOK. 8727 * 0b10..The internal registers are loaded with the values from their buffers when a trigger input event is detected after 1 is written to LDOK. 8728 * 0b11..The internal registers are loaded with the values from their buffers when either the PDB counter reaches the MOD register value or a trigger input event is detected, after 1 is written to LDOK. 8729 */ 8730 #define PDB_SC_LDMOD(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_LDMOD_SHIFT)) & PDB_SC_LDMOD_MASK) 8731 /*! @} */ 8732 8733 /*! @name MOD - Modulus register */ 8734 /*! @{ */ 8735 #define PDB_MOD_MOD_MASK (0xFFFFU) 8736 #define PDB_MOD_MOD_SHIFT (0U) 8737 #define PDB_MOD_MOD(x) (((uint32_t)(((uint32_t)(x)) << PDB_MOD_MOD_SHIFT)) & PDB_MOD_MOD_MASK) 8738 /*! @} */ 8739 8740 /*! @name CNT - Counter register */ 8741 /*! @{ */ 8742 #define PDB_CNT_CNT_MASK (0xFFFFU) 8743 #define PDB_CNT_CNT_SHIFT (0U) 8744 #define PDB_CNT_CNT(x) (((uint32_t)(((uint32_t)(x)) << PDB_CNT_CNT_SHIFT)) & PDB_CNT_CNT_MASK) 8745 /*! @} */ 8746 8747 /*! @name IDLY - Interrupt Delay register */ 8748 /*! @{ */ 8749 #define PDB_IDLY_IDLY_MASK (0xFFFFU) 8750 #define PDB_IDLY_IDLY_SHIFT (0U) 8751 #define PDB_IDLY_IDLY(x) (((uint32_t)(((uint32_t)(x)) << PDB_IDLY_IDLY_SHIFT)) & PDB_IDLY_IDLY_MASK) 8752 /*! @} */ 8753 8754 /*! @name C1 - Channel n Control register 1 */ 8755 /*! @{ */ 8756 #define PDB_C1_EN_MASK (0xFFU) 8757 #define PDB_C1_EN_SHIFT (0U) 8758 /*! EN - PDB Channel Pre-Trigger Enable 8759 * 0b00000000..PDB channel's corresponding pre-trigger disabled. 8760 * 0b00000001..PDB channel's corresponding pre-trigger enabled. 8761 */ 8762 #define PDB_C1_EN(x) (((uint32_t)(((uint32_t)(x)) << PDB_C1_EN_SHIFT)) & PDB_C1_EN_MASK) 8763 #define PDB_C1_TOS_MASK (0xFF00U) 8764 #define PDB_C1_TOS_SHIFT (8U) 8765 /*! TOS - PDB Channel Pre-Trigger Output Select 8766 * 0b00000000..PDB channel's corresponding pre-trigger is in bypassed mode. The pre-trigger asserts one peripheral clock cycle after a rising edge is detected on selected trigger input source or software trigger is selected and SWTRIG is written with 1. 8767 * 0b00000001..PDB channel's corresponding pre-trigger asserts when the counter reaches the channel delay register and one peripheral clock cycle after a rising edge is detected on selected trigger input source or software trigger is selected and SETRIG is written with 1. 8768 */ 8769 #define PDB_C1_TOS(x) (((uint32_t)(((uint32_t)(x)) << PDB_C1_TOS_SHIFT)) & PDB_C1_TOS_MASK) 8770 #define PDB_C1_BB_MASK (0xFF0000U) 8771 #define PDB_C1_BB_SHIFT (16U) 8772 /*! BB - PDB Channel Pre-Trigger Back-to-Back Operation Enable 8773 * 0b00000000..PDB channel's corresponding pre-trigger back-to-back operation disabled. 8774 * 0b00000001..PDB channel's corresponding pre-trigger back-to-back operation enabled. 8775 */ 8776 #define PDB_C1_BB(x) (((uint32_t)(((uint32_t)(x)) << PDB_C1_BB_SHIFT)) & PDB_C1_BB_MASK) 8777 /*! @} */ 8778 8779 /* The count of PDB_C1 */ 8780 #define PDB_C1_COUNT (2U) 8781 8782 /*! @name S - Channel n Status register */ 8783 /*! @{ */ 8784 #define PDB_S_ERR_MASK (0xFFU) 8785 #define PDB_S_ERR_SHIFT (0U) 8786 /*! ERR - PDB Channel Sequence Error Flags 8787 * 0b00000000..Sequence error not detected on PDB channel's corresponding pre-trigger. 8788 * 0b00000001..Sequence error detected on PDB channel's corresponding pre-trigger. ADCn block can be triggered for a conversion by one pre-trigger from PDB channel n. When one conversion, which is triggered by one of the pre-triggers from PDB channel n, is in progress, new trigger from PDB channel's corresponding pre-trigger m cannot be accepted by ADCn, and ERR[m] is set. Writing 0's to clear the sequence error flags. 8789 */ 8790 #define PDB_S_ERR(x) (((uint32_t)(((uint32_t)(x)) << PDB_S_ERR_SHIFT)) & PDB_S_ERR_MASK) 8791 #define PDB_S_CF_MASK (0xFF0000U) 8792 #define PDB_S_CF_SHIFT (16U) 8793 #define PDB_S_CF(x) (((uint32_t)(((uint32_t)(x)) << PDB_S_CF_SHIFT)) & PDB_S_CF_MASK) 8794 /*! @} */ 8795 8796 /* The count of PDB_S */ 8797 #define PDB_S_COUNT (2U) 8798 8799 /*! @name DLY - Channel n Delay 0 register..Channel n Delay 1 register */ 8800 /*! @{ */ 8801 #define PDB_DLY_DLY_MASK (0xFFFFU) 8802 #define PDB_DLY_DLY_SHIFT (0U) 8803 #define PDB_DLY_DLY(x) (((uint32_t)(((uint32_t)(x)) << PDB_DLY_DLY_SHIFT)) & PDB_DLY_DLY_MASK) 8804 /*! @} */ 8805 8806 /* The count of PDB_DLY */ 8807 #define PDB_DLY_COUNT (2U) 8808 8809 /* The count of PDB_DLY */ 8810 #define PDB_DLY_COUNT2 (2U) 8811 8812 /*! @name INTC - DAC Interval Trigger n Control register */ 8813 /*! @{ */ 8814 #define PDB_INTC_TOE_MASK (0x1U) 8815 #define PDB_INTC_TOE_SHIFT (0U) 8816 /*! TOE - DAC Interval Trigger Enable 8817 * 0b0..DAC interval trigger disabled. 8818 * 0b1..DAC interval trigger enabled. 8819 */ 8820 #define PDB_INTC_TOE(x) (((uint32_t)(((uint32_t)(x)) << PDB_INTC_TOE_SHIFT)) & PDB_INTC_TOE_MASK) 8821 #define PDB_INTC_EXT_MASK (0x2U) 8822 #define PDB_INTC_EXT_SHIFT (1U) 8823 /*! EXT - DAC External Trigger Input Enable 8824 * 0b0..DAC external trigger input disabled. DAC interval counter is reset and started counting when a rising edge is detected on selected trigger input source or software trigger is selected and SWTRIG is written with 1. 8825 * 0b1..DAC external trigger input enabled. DAC interval counter is bypassed and DAC external trigger input triggers the DAC interval trigger. 8826 */ 8827 #define PDB_INTC_EXT(x) (((uint32_t)(((uint32_t)(x)) << PDB_INTC_EXT_SHIFT)) & PDB_INTC_EXT_MASK) 8828 /*! @} */ 8829 8830 /* The count of PDB_INTC */ 8831 #define PDB_INTC_COUNT (1U) 8832 8833 /*! @name INT - DAC Interval n register */ 8834 /*! @{ */ 8835 #define PDB_INT_INT_MASK (0xFFFFU) 8836 #define PDB_INT_INT_SHIFT (0U) 8837 #define PDB_INT_INT(x) (((uint32_t)(((uint32_t)(x)) << PDB_INT_INT_SHIFT)) & PDB_INT_INT_MASK) 8838 /*! @} */ 8839 8840 /* The count of PDB_INT */ 8841 #define PDB_INT_COUNT (1U) 8842 8843 /*! @name POEN - Pulse-Out n Enable register */ 8844 /*! @{ */ 8845 #define PDB_POEN_POEN_MASK (0xFFU) 8846 #define PDB_POEN_POEN_SHIFT (0U) 8847 /*! POEN - PDB Pulse-Out Enable 8848 * 0b00000000..PDB Pulse-Out disabled 8849 * 0b00000001..PDB Pulse-Out enabled 8850 */ 8851 #define PDB_POEN_POEN(x) (((uint32_t)(((uint32_t)(x)) << PDB_POEN_POEN_SHIFT)) & PDB_POEN_POEN_MASK) 8852 /*! @} */ 8853 8854 /*! @name PODLY - Pulse-Out n Delay register */ 8855 /*! @{ */ 8856 #define PDB_PODLY_DLY2_MASK (0xFFFFU) 8857 #define PDB_PODLY_DLY2_SHIFT (0U) 8858 #define PDB_PODLY_DLY2(x) (((uint32_t)(((uint32_t)(x)) << PDB_PODLY_DLY2_SHIFT)) & PDB_PODLY_DLY2_MASK) 8859 #define PDB_PODLY_DLY1_MASK (0xFFFF0000U) 8860 #define PDB_PODLY_DLY1_SHIFT (16U) 8861 #define PDB_PODLY_DLY1(x) (((uint32_t)(((uint32_t)(x)) << PDB_PODLY_DLY1_SHIFT)) & PDB_PODLY_DLY1_MASK) 8862 /*! @} */ 8863 8864 /* The count of PDB_PODLY */ 8865 #define PDB_PODLY_COUNT (2U) 8866 8867 8868 /*! 8869 * @} 8870 */ /* end of group PDB_Register_Masks */ 8871 8872 8873 /* PDB - Peripheral instance base addresses */ 8874 /** Peripheral PDB0 base address */ 8875 #define PDB0_BASE (0x40036000u) 8876 /** Peripheral PDB0 base pointer */ 8877 #define PDB0 ((PDB_Type *)PDB0_BASE) 8878 /** Peripheral PDB1 base address */ 8879 #define PDB1_BASE (0x40031000u) 8880 /** Peripheral PDB1 base pointer */ 8881 #define PDB1 ((PDB_Type *)PDB1_BASE) 8882 /** Array initializer of PDB peripheral base addresses */ 8883 #define PDB_BASE_ADDRS { PDB0_BASE, PDB1_BASE } 8884 /** Array initializer of PDB peripheral base pointers */ 8885 #define PDB_BASE_PTRS { PDB0, PDB1 } 8886 /** Interrupt vectors for the PDB peripheral type */ 8887 #define PDB_IRQS { PDB0_PDB1_IRQn, PDB0_PDB1_IRQn } 8888 8889 /*! 8890 * @} 8891 */ /* end of group PDB_Peripheral_Access_Layer */ 8892 8893 8894 /* ---------------------------------------------------------------------------- 8895 -- PMC Peripheral Access Layer 8896 ---------------------------------------------------------------------------- */ 8897 8898 /*! 8899 * @addtogroup PMC_Peripheral_Access_Layer PMC Peripheral Access Layer 8900 * @{ 8901 */ 8902 8903 /** PMC - Register Layout Typedef */ 8904 typedef struct { 8905 __IO uint8_t LVDSC1; /**< Low Voltage Detect Status And Control 1 register, offset: 0x0 */ 8906 __IO uint8_t LVDSC2; /**< Low Voltage Detect Status And Control 2 register, offset: 0x1 */ 8907 __IO uint8_t REGSC; /**< Regulator Status And Control register, offset: 0x2 */ 8908 } PMC_Type; 8909 8910 /* ---------------------------------------------------------------------------- 8911 -- PMC Register Masks 8912 ---------------------------------------------------------------------------- */ 8913 8914 /*! 8915 * @addtogroup PMC_Register_Masks PMC Register Masks 8916 * @{ 8917 */ 8918 8919 /*! @name LVDSC1 - Low Voltage Detect Status And Control 1 register */ 8920 /*! @{ */ 8921 #define PMC_LVDSC1_LVDV_MASK (0x3U) 8922 #define PMC_LVDSC1_LVDV_SHIFT (0U) 8923 /*! LVDV - Low-Voltage Detect Voltage Select 8924 * 0b00..Low trip point selected (V LVD = V LVDL ) 8925 * 0b01..High trip point selected (V LVD = V LVDH ) 8926 * 0b10..Reserved 8927 * 0b11..Reserved 8928 */ 8929 #define PMC_LVDSC1_LVDV(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC1_LVDV_SHIFT)) & PMC_LVDSC1_LVDV_MASK) 8930 #define PMC_LVDSC1_LVDRE_MASK (0x10U) 8931 #define PMC_LVDSC1_LVDRE_SHIFT (4U) 8932 /*! LVDRE - Low-Voltage Detect Reset Enable 8933 * 0b0..LVDF does not generate hardware resets 8934 * 0b1..Force an MCU reset when LVDF = 1 8935 */ 8936 #define PMC_LVDSC1_LVDRE(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC1_LVDRE_SHIFT)) & PMC_LVDSC1_LVDRE_MASK) 8937 #define PMC_LVDSC1_LVDIE_MASK (0x20U) 8938 #define PMC_LVDSC1_LVDIE_SHIFT (5U) 8939 /*! LVDIE - Low-Voltage Detect Interrupt Enable 8940 * 0b0..Hardware interrupt disabled (use polling) 8941 * 0b1..Request a hardware interrupt when LVDF = 1 8942 */ 8943 #define PMC_LVDSC1_LVDIE(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC1_LVDIE_SHIFT)) & PMC_LVDSC1_LVDIE_MASK) 8944 #define PMC_LVDSC1_LVDACK_MASK (0x40U) 8945 #define PMC_LVDSC1_LVDACK_SHIFT (6U) 8946 #define PMC_LVDSC1_LVDACK(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC1_LVDACK_SHIFT)) & PMC_LVDSC1_LVDACK_MASK) 8947 #define PMC_LVDSC1_LVDF_MASK (0x80U) 8948 #define PMC_LVDSC1_LVDF_SHIFT (7U) 8949 /*! LVDF - Low-Voltage Detect Flag 8950 * 0b0..Low-voltage event not detected 8951 * 0b1..Low-voltage event detected 8952 */ 8953 #define PMC_LVDSC1_LVDF(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC1_LVDF_SHIFT)) & PMC_LVDSC1_LVDF_MASK) 8954 /*! @} */ 8955 8956 /*! @name LVDSC2 - Low Voltage Detect Status And Control 2 register */ 8957 /*! @{ */ 8958 #define PMC_LVDSC2_LVWV_MASK (0x3U) 8959 #define PMC_LVDSC2_LVWV_SHIFT (0U) 8960 /*! LVWV - Low-Voltage Warning Voltage Select 8961 * 0b00..Low trip point selected (VLVW = VLVW1) 8962 * 0b01..Mid 1 trip point selected (VLVW = VLVW2) 8963 * 0b10..Mid 2 trip point selected (VLVW = VLVW3) 8964 * 0b11..High trip point selected (VLVW = VLVW4) 8965 */ 8966 #define PMC_LVDSC2_LVWV(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC2_LVWV_SHIFT)) & PMC_LVDSC2_LVWV_MASK) 8967 #define PMC_LVDSC2_LVWIE_MASK (0x20U) 8968 #define PMC_LVDSC2_LVWIE_SHIFT (5U) 8969 /*! LVWIE - Low-Voltage Warning Interrupt Enable 8970 * 0b0..Hardware interrupt disabled (use polling) 8971 * 0b1..Request a hardware interrupt when LVWF = 1 8972 */ 8973 #define PMC_LVDSC2_LVWIE(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC2_LVWIE_SHIFT)) & PMC_LVDSC2_LVWIE_MASK) 8974 #define PMC_LVDSC2_LVWACK_MASK (0x40U) 8975 #define PMC_LVDSC2_LVWACK_SHIFT (6U) 8976 #define PMC_LVDSC2_LVWACK(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC2_LVWACK_SHIFT)) & PMC_LVDSC2_LVWACK_MASK) 8977 #define PMC_LVDSC2_LVWF_MASK (0x80U) 8978 #define PMC_LVDSC2_LVWF_SHIFT (7U) 8979 /*! LVWF - Low-Voltage Warning Flag 8980 * 0b0..Low-voltage warning event not detected 8981 * 0b1..Low-voltage warning event detected 8982 */ 8983 #define PMC_LVDSC2_LVWF(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC2_LVWF_SHIFT)) & PMC_LVDSC2_LVWF_MASK) 8984 /*! @} */ 8985 8986 /*! @name REGSC - Regulator Status And Control register */ 8987 /*! @{ */ 8988 #define PMC_REGSC_BGBE_MASK (0x1U) 8989 #define PMC_REGSC_BGBE_SHIFT (0U) 8990 /*! BGBE - Bandgap Buffer Enable 8991 * 0b0..Bandgap buffer not enabled 8992 * 0b1..Bandgap buffer enabled 8993 */ 8994 #define PMC_REGSC_BGBE(x) (((uint8_t)(((uint8_t)(x)) << PMC_REGSC_BGBE_SHIFT)) & PMC_REGSC_BGBE_MASK) 8995 #define PMC_REGSC_REGONS_MASK (0x4U) 8996 #define PMC_REGSC_REGONS_SHIFT (2U) 8997 /*! REGONS - Regulator In Run Regulation Status 8998 * 0b0..Regulator is in stop regulation or in transition to/from it 8999 * 0b1..Regulator is in run regulation 9000 */ 9001 #define PMC_REGSC_REGONS(x) (((uint8_t)(((uint8_t)(x)) << PMC_REGSC_REGONS_SHIFT)) & PMC_REGSC_REGONS_MASK) 9002 #define PMC_REGSC_ACKISO_MASK (0x8U) 9003 #define PMC_REGSC_ACKISO_SHIFT (3U) 9004 /*! ACKISO - Acknowledge Isolation 9005 * 0b0..Peripherals and I/O pads are in normal run state. 9006 * 0b1..Certain peripherals and I/O pads are in an isolated and latched state. 9007 */ 9008 #define PMC_REGSC_ACKISO(x) (((uint8_t)(((uint8_t)(x)) << PMC_REGSC_ACKISO_SHIFT)) & PMC_REGSC_ACKISO_MASK) 9009 #define PMC_REGSC_BGEN_MASK (0x10U) 9010 #define PMC_REGSC_BGEN_SHIFT (4U) 9011 /*! BGEN - Bandgap Enable In VLPx Operation 9012 * 0b0..Bandgap voltage reference is disabled in VLPx , and VLLSx modes. 9013 * 0b1..Bandgap voltage reference is enabled in VLPx , and VLLSx modes. 9014 */ 9015 #define PMC_REGSC_BGEN(x) (((uint8_t)(((uint8_t)(x)) << PMC_REGSC_BGEN_SHIFT)) & PMC_REGSC_BGEN_MASK) 9016 /*! @} */ 9017 9018 9019 /*! 9020 * @} 9021 */ /* end of group PMC_Register_Masks */ 9022 9023 9024 /* PMC - Peripheral instance base addresses */ 9025 /** Peripheral PMC base address */ 9026 #define PMC_BASE (0x4007D000u) 9027 /** Peripheral PMC base pointer */ 9028 #define PMC ((PMC_Type *)PMC_BASE) 9029 /** Array initializer of PMC peripheral base addresses */ 9030 #define PMC_BASE_ADDRS { PMC_BASE } 9031 /** Array initializer of PMC peripheral base pointers */ 9032 #define PMC_BASE_PTRS { PMC } 9033 /** Interrupt vectors for the PMC peripheral type */ 9034 #define PMC_IRQS { LVD_LVW_IRQn } 9035 9036 /*! 9037 * @} 9038 */ /* end of group PMC_Peripheral_Access_Layer */ 9039 9040 9041 /* ---------------------------------------------------------------------------- 9042 -- PORT Peripheral Access Layer 9043 ---------------------------------------------------------------------------- */ 9044 9045 /*! 9046 * @addtogroup PORT_Peripheral_Access_Layer PORT Peripheral Access Layer 9047 * @{ 9048 */ 9049 9050 /** PORT - Register Layout Typedef */ 9051 typedef struct { 9052 __IO uint32_t PCR[32]; /**< Pin Control Register n, array offset: 0x0, array step: 0x4 */ 9053 __O uint32_t GPCLR; /**< Global Pin Control Low Register, offset: 0x80 */ 9054 __O uint32_t GPCHR; /**< Global Pin Control High Register, offset: 0x84 */ 9055 uint8_t RESERVED_0[24]; 9056 __IO uint32_t ISFR; /**< Interrupt Status Flag Register, offset: 0xA0 */ 9057 } PORT_Type; 9058 9059 /* ---------------------------------------------------------------------------- 9060 -- PORT Register Masks 9061 ---------------------------------------------------------------------------- */ 9062 9063 /*! 9064 * @addtogroup PORT_Register_Masks PORT Register Masks 9065 * @{ 9066 */ 9067 9068 /*! @name PCR - Pin Control Register n */ 9069 /*! @{ */ 9070 #define PORT_PCR_PS_MASK (0x1U) 9071 #define PORT_PCR_PS_SHIFT (0U) 9072 /*! PS - Pull Select 9073 * 0b0..Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. 9074 * 0b1..Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. 9075 */ 9076 #define PORT_PCR_PS(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_PS_SHIFT)) & PORT_PCR_PS_MASK) 9077 #define PORT_PCR_PE_MASK (0x2U) 9078 #define PORT_PCR_PE_SHIFT (1U) 9079 /*! PE - Pull Enable 9080 * 0b0..Internal pullup or pulldown resistor is not enabled on the corresponding pin. 9081 * 0b1..Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. 9082 */ 9083 #define PORT_PCR_PE(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_PE_SHIFT)) & PORT_PCR_PE_MASK) 9084 #define PORT_PCR_SRE_MASK (0x4U) 9085 #define PORT_PCR_SRE_SHIFT (2U) 9086 /*! SRE - Slew Rate Enable 9087 * 0b0..Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. 9088 * 0b1..Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. 9089 */ 9090 #define PORT_PCR_SRE(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_SRE_SHIFT)) & PORT_PCR_SRE_MASK) 9091 #define PORT_PCR_PFE_MASK (0x10U) 9092 #define PORT_PCR_PFE_SHIFT (4U) 9093 /*! PFE - Passive Filter Enable 9094 * 0b0..Passive input filter is disabled on the corresponding pin. 9095 * 0b1..Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. 9096 */ 9097 #define PORT_PCR_PFE(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_PFE_SHIFT)) & PORT_PCR_PFE_MASK) 9098 #define PORT_PCR_DSE_MASK (0x40U) 9099 #define PORT_PCR_DSE_SHIFT (6U) 9100 /*! DSE - Drive Strength Enable 9101 * 0b0..Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. 9102 * 0b1..High drive strength is configured on the corresponding pin, if pin is configured as a digital output. 9103 */ 9104 #define PORT_PCR_DSE(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_DSE_SHIFT)) & PORT_PCR_DSE_MASK) 9105 #define PORT_PCR_MUX_MASK (0x700U) 9106 #define PORT_PCR_MUX_SHIFT (8U) 9107 /*! MUX - Pin Mux Control 9108 * 0b000..Pin disabled (analog). 9109 * 0b001..Alternative 1 (GPIO). 9110 * 0b010..Alternative 2 (chip-specific). 9111 * 0b011..Alternative 3 (chip-specific). 9112 * 0b100..Alternative 4 (chip-specific). 9113 * 0b101..Alternative 5 (chip-specific). 9114 * 0b110..Alternative 6 (chip-specific). 9115 * 0b111..Alternative 7 (chip-specific). 9116 */ 9117 #define PORT_PCR_MUX(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_MUX_SHIFT)) & PORT_PCR_MUX_MASK) 9118 #define PORT_PCR_IRQC_MASK (0xF0000U) 9119 #define PORT_PCR_IRQC_SHIFT (16U) 9120 /*! IRQC - Interrupt Configuration 9121 * 0b0000..Interrupt Status Flag (ISF) is disabled. 9122 * 0b0001..ISF flag and DMA request on rising edge. 9123 * 0b0010..ISF flag and DMA request on falling edge. 9124 * 0b0011..ISF flag and DMA request on either edge. 9125 * 0b0100..Reserved. 9126 * 0b0101..Reserved. 9127 * 0b0110..Reserved. 9128 * 0b0111..Reserved. 9129 * 0b1000..ISF flag and Interrupt when logic 0. 9130 * 0b1001..ISF flag and Interrupt on rising-edge. 9131 * 0b1010..ISF flag and Interrupt on falling-edge. 9132 * 0b1011..ISF flag and Interrupt on either edge. 9133 * 0b1100..ISF flag and Interrupt when logic 1. 9134 * 0b1101..Reserved. 9135 * 0b1110..Reserved. 9136 * 0b1111..Reserved. 9137 */ 9138 #define PORT_PCR_IRQC(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_IRQC_SHIFT)) & PORT_PCR_IRQC_MASK) 9139 #define PORT_PCR_ISF_MASK (0x1000000U) 9140 #define PORT_PCR_ISF_SHIFT (24U) 9141 /*! ISF - Interrupt Status Flag 9142 * 0b0..Configured interrupt is not detected. 9143 * 0b1..Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. 9144 */ 9145 #define PORT_PCR_ISF(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_ISF_SHIFT)) & PORT_PCR_ISF_MASK) 9146 /*! @} */ 9147 9148 /* The count of PORT_PCR */ 9149 #define PORT_PCR_COUNT (32U) 9150 9151 /*! @name GPCLR - Global Pin Control Low Register */ 9152 /*! @{ */ 9153 #define PORT_GPCLR_GPWD_MASK (0xFFFFU) 9154 #define PORT_GPCLR_GPWD_SHIFT (0U) 9155 #define PORT_GPCLR_GPWD(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCLR_GPWD_SHIFT)) & PORT_GPCLR_GPWD_MASK) 9156 #define PORT_GPCLR_GPWE_MASK (0xFFFF0000U) 9157 #define PORT_GPCLR_GPWE_SHIFT (16U) 9158 /*! GPWE - Global Pin Write Enable 9159 * 0b0000000000000000..Corresponding Pin Control Register is not updated with the value in GPWD. 9160 * 0b0000000000000001..Corresponding Pin Control Register is updated with the value in GPWD. 9161 */ 9162 #define PORT_GPCLR_GPWE(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCLR_GPWE_SHIFT)) & PORT_GPCLR_GPWE_MASK) 9163 /*! @} */ 9164 9165 /*! @name GPCHR - Global Pin Control High Register */ 9166 /*! @{ */ 9167 #define PORT_GPCHR_GPWD_MASK (0xFFFFU) 9168 #define PORT_GPCHR_GPWD_SHIFT (0U) 9169 #define PORT_GPCHR_GPWD(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCHR_GPWD_SHIFT)) & PORT_GPCHR_GPWD_MASK) 9170 #define PORT_GPCHR_GPWE_MASK (0xFFFF0000U) 9171 #define PORT_GPCHR_GPWE_SHIFT (16U) 9172 /*! GPWE - Global Pin Write Enable 9173 * 0b0000000000000000..Corresponding Pin Control Register is not updated with the value in GPWD. 9174 * 0b0000000000000001..Corresponding Pin Control Register is updated with the value in GPWD. 9175 */ 9176 #define PORT_GPCHR_GPWE(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCHR_GPWE_SHIFT)) & PORT_GPCHR_GPWE_MASK) 9177 /*! @} */ 9178 9179 /*! @name ISFR - Interrupt Status Flag Register */ 9180 /*! @{ */ 9181 #define PORT_ISFR_ISF_MASK (0xFFFFFFFFU) 9182 #define PORT_ISFR_ISF_SHIFT (0U) 9183 /*! ISF - Interrupt Status Flag 9184 * 0b00000000000000000000000000000000..Configured interrupt is not detected. 9185 * 0b00000000000000000000000000000001..Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. 9186 */ 9187 #define PORT_ISFR_ISF(x) (((uint32_t)(((uint32_t)(x)) << PORT_ISFR_ISF_SHIFT)) & PORT_ISFR_ISF_MASK) 9188 /*! @} */ 9189 9190 9191 /*! 9192 * @} 9193 */ /* end of group PORT_Register_Masks */ 9194 9195 9196 /* PORT - Peripheral instance base addresses */ 9197 /** Peripheral PORTA base address */ 9198 #define PORTA_BASE (0x40049000u) 9199 /** Peripheral PORTA base pointer */ 9200 #define PORTA ((PORT_Type *)PORTA_BASE) 9201 /** Peripheral PORTB base address */ 9202 #define PORTB_BASE (0x4004A000u) 9203 /** Peripheral PORTB base pointer */ 9204 #define PORTB ((PORT_Type *)PORTB_BASE) 9205 /** Peripheral PORTC base address */ 9206 #define PORTC_BASE (0x4004B000u) 9207 /** Peripheral PORTC base pointer */ 9208 #define PORTC ((PORT_Type *)PORTC_BASE) 9209 /** Peripheral PORTD base address */ 9210 #define PORTD_BASE (0x4004C000u) 9211 /** Peripheral PORTD base pointer */ 9212 #define PORTD ((PORT_Type *)PORTD_BASE) 9213 /** Peripheral PORTE base address */ 9214 #define PORTE_BASE (0x4004D000u) 9215 /** Peripheral PORTE base pointer */ 9216 #define PORTE ((PORT_Type *)PORTE_BASE) 9217 /** Array initializer of PORT peripheral base addresses */ 9218 #define PORT_BASE_ADDRS { PORTA_BASE, PORTB_BASE, PORTC_BASE, PORTD_BASE, PORTE_BASE } 9219 /** Array initializer of PORT peripheral base pointers */ 9220 #define PORT_BASE_PTRS { PORTA, PORTB, PORTC, PORTD, PORTE } 9221 /** Interrupt vectors for the PORT peripheral type */ 9222 #define PORT_IRQS { PORTA_IRQn, PORTB_PORTC_PORTD_PORTE_IRQn, PORTB_PORTC_PORTD_PORTE_IRQn, PORTB_PORTC_PORTD_PORTE_IRQn, PORTB_PORTC_PORTD_PORTE_IRQn } 9223 9224 /*! 9225 * @} 9226 */ /* end of group PORT_Peripheral_Access_Layer */ 9227 9228 9229 /* ---------------------------------------------------------------------------- 9230 -- RCM Peripheral Access Layer 9231 ---------------------------------------------------------------------------- */ 9232 9233 /*! 9234 * @addtogroup RCM_Peripheral_Access_Layer RCM Peripheral Access Layer 9235 * @{ 9236 */ 9237 9238 /** RCM - Register Layout Typedef */ 9239 typedef struct { 9240 __I uint8_t SRS0; /**< System Reset Status Register 0, offset: 0x0 */ 9241 __I uint8_t SRS1; /**< System Reset Status Register 1, offset: 0x1 */ 9242 uint8_t RESERVED_0[2]; 9243 __IO uint8_t RPFC; /**< Reset Pin Filter Control register, offset: 0x4 */ 9244 __IO uint8_t RPFW; /**< Reset Pin Filter Width register, offset: 0x5 */ 9245 } RCM_Type; 9246 9247 /* ---------------------------------------------------------------------------- 9248 -- RCM Register Masks 9249 ---------------------------------------------------------------------------- */ 9250 9251 /*! 9252 * @addtogroup RCM_Register_Masks RCM Register Masks 9253 * @{ 9254 */ 9255 9256 /*! @name SRS0 - System Reset Status Register 0 */ 9257 /*! @{ */ 9258 #define RCM_SRS0_WAKEUP_MASK (0x1U) 9259 #define RCM_SRS0_WAKEUP_SHIFT (0U) 9260 /*! WAKEUP - Low Leakage Wakeup Reset 9261 * 0b0..Reset not caused by LLWU module wakeup source 9262 * 0b1..Reset caused by LLWU module wakeup source 9263 */ 9264 #define RCM_SRS0_WAKEUP(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS0_WAKEUP_SHIFT)) & RCM_SRS0_WAKEUP_MASK) 9265 #define RCM_SRS0_LVD_MASK (0x2U) 9266 #define RCM_SRS0_LVD_SHIFT (1U) 9267 /*! LVD - Low-Voltage Detect Reset 9268 * 0b0..Reset not caused by LVD trip or POR 9269 * 0b1..Reset caused by LVD trip or POR 9270 */ 9271 #define RCM_SRS0_LVD(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS0_LVD_SHIFT)) & RCM_SRS0_LVD_MASK) 9272 #define RCM_SRS0_LOC_MASK (0x4U) 9273 #define RCM_SRS0_LOC_SHIFT (2U) 9274 /*! LOC - Loss-of-Clock Reset 9275 * 0b0..Reset not caused by a loss of external clock. 9276 * 0b1..Reset caused by a loss of external clock. 9277 */ 9278 #define RCM_SRS0_LOC(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS0_LOC_SHIFT)) & RCM_SRS0_LOC_MASK) 9279 #define RCM_SRS0_WDOG_MASK (0x20U) 9280 #define RCM_SRS0_WDOG_SHIFT (5U) 9281 /*! WDOG - Watchdog 9282 * 0b0..Reset not caused by watchdog timeout 9283 * 0b1..Reset caused by watchdog timeout 9284 */ 9285 #define RCM_SRS0_WDOG(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS0_WDOG_SHIFT)) & RCM_SRS0_WDOG_MASK) 9286 #define RCM_SRS0_PIN_MASK (0x40U) 9287 #define RCM_SRS0_PIN_SHIFT (6U) 9288 /*! PIN - External Reset Pin 9289 * 0b0..Reset not caused by external reset pin 9290 * 0b1..Reset caused by external reset pin 9291 */ 9292 #define RCM_SRS0_PIN(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS0_PIN_SHIFT)) & RCM_SRS0_PIN_MASK) 9293 #define RCM_SRS0_POR_MASK (0x80U) 9294 #define RCM_SRS0_POR_SHIFT (7U) 9295 /*! POR - Power-On Reset 9296 * 0b0..Reset not caused by POR 9297 * 0b1..Reset caused by POR 9298 */ 9299 #define RCM_SRS0_POR(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS0_POR_SHIFT)) & RCM_SRS0_POR_MASK) 9300 /*! @} */ 9301 9302 /*! @name SRS1 - System Reset Status Register 1 */ 9303 /*! @{ */ 9304 #define RCM_SRS1_LOCKUP_MASK (0x2U) 9305 #define RCM_SRS1_LOCKUP_SHIFT (1U) 9306 /*! LOCKUP - Core Lockup 9307 * 0b0..Reset not caused by core LOCKUP event 9308 * 0b1..Reset caused by core LOCKUP event 9309 */ 9310 #define RCM_SRS1_LOCKUP(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS1_LOCKUP_SHIFT)) & RCM_SRS1_LOCKUP_MASK) 9311 #define RCM_SRS1_SW_MASK (0x4U) 9312 #define RCM_SRS1_SW_SHIFT (2U) 9313 /*! SW - Software 9314 * 0b0..Reset not caused by software setting of SYSRESETREQ bit 9315 * 0b1..Reset caused by software setting of SYSRESETREQ bit 9316 */ 9317 #define RCM_SRS1_SW(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS1_SW_SHIFT)) & RCM_SRS1_SW_MASK) 9318 #define RCM_SRS1_MDM_AP_MASK (0x8U) 9319 #define RCM_SRS1_MDM_AP_SHIFT (3U) 9320 /*! MDM_AP - MDM-AP System Reset Request 9321 * 0b0..Reset not caused by host debugger system setting of the System Reset Request bit 9322 * 0b1..Reset caused by host debugger system setting of the System Reset Request bit 9323 */ 9324 #define RCM_SRS1_MDM_AP(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS1_MDM_AP_SHIFT)) & RCM_SRS1_MDM_AP_MASK) 9325 #define RCM_SRS1_SACKERR_MASK (0x20U) 9326 #define RCM_SRS1_SACKERR_SHIFT (5U) 9327 /*! SACKERR - Stop Mode Acknowledge Error Reset 9328 * 0b0..Reset not caused by peripheral failure to acknowledge attempt to enter stop mode 9329 * 0b1..Reset caused by peripheral failure to acknowledge attempt to enter stop mode 9330 */ 9331 #define RCM_SRS1_SACKERR(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS1_SACKERR_SHIFT)) & RCM_SRS1_SACKERR_MASK) 9332 /*! @} */ 9333 9334 /*! @name RPFC - Reset Pin Filter Control register */ 9335 /*! @{ */ 9336 #define RCM_RPFC_RSTFLTSRW_MASK (0x3U) 9337 #define RCM_RPFC_RSTFLTSRW_SHIFT (0U) 9338 /*! RSTFLTSRW - Reset Pin Filter Select in Run and Wait Modes 9339 * 0b00..All filtering disabled 9340 * 0b01..Bus clock filter enabled for normal operation 9341 * 0b10..LPO clock filter enabled for normal operation 9342 * 0b11..Reserved 9343 */ 9344 #define RCM_RPFC_RSTFLTSRW(x) (((uint8_t)(((uint8_t)(x)) << RCM_RPFC_RSTFLTSRW_SHIFT)) & RCM_RPFC_RSTFLTSRW_MASK) 9345 #define RCM_RPFC_RSTFLTSS_MASK (0x4U) 9346 #define RCM_RPFC_RSTFLTSS_SHIFT (2U) 9347 /*! RSTFLTSS - Reset Pin Filter Select in Stop Mode 9348 * 0b0..All filtering disabled 9349 * 0b1..LPO clock filter enabled 9350 */ 9351 #define RCM_RPFC_RSTFLTSS(x) (((uint8_t)(((uint8_t)(x)) << RCM_RPFC_RSTFLTSS_SHIFT)) & RCM_RPFC_RSTFLTSS_MASK) 9352 /*! @} */ 9353 9354 /*! @name RPFW - Reset Pin Filter Width register */ 9355 /*! @{ */ 9356 #define RCM_RPFW_RSTFLTSEL_MASK (0x1FU) 9357 #define RCM_RPFW_RSTFLTSEL_SHIFT (0U) 9358 /*! RSTFLTSEL - Reset Pin Filter Bus Clock Select 9359 * 0b00000..Bus clock filter count is 1 9360 * 0b00001..Bus clock filter count is 2 9361 * 0b00010..Bus clock filter count is 3 9362 * 0b00011..Bus clock filter count is 4 9363 * 0b00100..Bus clock filter count is 5 9364 * 0b00101..Bus clock filter count is 6 9365 * 0b00110..Bus clock filter count is 7 9366 * 0b00111..Bus clock filter count is 8 9367 * 0b01000..Bus clock filter count is 9 9368 * 0b01001..Bus clock filter count is 10 9369 * 0b01010..Bus clock filter count is 11 9370 * 0b01011..Bus clock filter count is 12 9371 * 0b01100..Bus clock filter count is 13 9372 * 0b01101..Bus clock filter count is 14 9373 * 0b01110..Bus clock filter count is 15 9374 * 0b01111..Bus clock filter count is 16 9375 * 0b10000..Bus clock filter count is 17 9376 * 0b10001..Bus clock filter count is 18 9377 * 0b10010..Bus clock filter count is 19 9378 * 0b10011..Bus clock filter count is 20 9379 * 0b10100..Bus clock filter count is 21 9380 * 0b10101..Bus clock filter count is 22 9381 * 0b10110..Bus clock filter count is 23 9382 * 0b10111..Bus clock filter count is 24 9383 * 0b11000..Bus clock filter count is 25 9384 * 0b11001..Bus clock filter count is 26 9385 * 0b11010..Bus clock filter count is 27 9386 * 0b11011..Bus clock filter count is 28 9387 * 0b11100..Bus clock filter count is 29 9388 * 0b11101..Bus clock filter count is 30 9389 * 0b11110..Bus clock filter count is 31 9390 * 0b11111..Bus clock filter count is 32 9391 */ 9392 #define RCM_RPFW_RSTFLTSEL(x) (((uint8_t)(((uint8_t)(x)) << RCM_RPFW_RSTFLTSEL_SHIFT)) & RCM_RPFW_RSTFLTSEL_MASK) 9393 /*! @} */ 9394 9395 9396 /*! 9397 * @} 9398 */ /* end of group RCM_Register_Masks */ 9399 9400 9401 /* RCM - Peripheral instance base addresses */ 9402 /** Peripheral RCM base address */ 9403 #define RCM_BASE (0x4007F000u) 9404 /** Peripheral RCM base pointer */ 9405 #define RCM ((RCM_Type *)RCM_BASE) 9406 /** Array initializer of RCM peripheral base addresses */ 9407 #define RCM_BASE_ADDRS { RCM_BASE } 9408 /** Array initializer of RCM peripheral base pointers */ 9409 #define RCM_BASE_PTRS { RCM } 9410 9411 /*! 9412 * @} 9413 */ /* end of group RCM_Peripheral_Access_Layer */ 9414 9415 9416 /* ---------------------------------------------------------------------------- 9417 -- ROM Peripheral Access Layer 9418 ---------------------------------------------------------------------------- */ 9419 9420 /*! 9421 * @addtogroup ROM_Peripheral_Access_Layer ROM Peripheral Access Layer 9422 * @{ 9423 */ 9424 9425 /** ROM - Register Layout Typedef */ 9426 typedef struct { 9427 __I uint32_t ENTRY[3]; /**< Entry, array offset: 0x0, array step: 0x4 */ 9428 __I uint32_t TABLEMARK; /**< End of Table Marker Register, offset: 0xC */ 9429 uint8_t RESERVED_0[4028]; 9430 __I uint32_t SYSACCESS; /**< System Access Register, offset: 0xFCC */ 9431 __I uint32_t PERIPHID4; /**< Peripheral ID Register, offset: 0xFD0 */ 9432 __I uint32_t PERIPHID5; /**< Peripheral ID Register, offset: 0xFD4 */ 9433 __I uint32_t PERIPHID6; /**< Peripheral ID Register, offset: 0xFD8 */ 9434 __I uint32_t PERIPHID7; /**< Peripheral ID Register, offset: 0xFDC */ 9435 __I uint32_t PERIPHID0; /**< Peripheral ID Register, offset: 0xFE0 */ 9436 __I uint32_t PERIPHID1; /**< Peripheral ID Register, offset: 0xFE4 */ 9437 __I uint32_t PERIPHID2; /**< Peripheral ID Register, offset: 0xFE8 */ 9438 __I uint32_t PERIPHID3; /**< Peripheral ID Register, offset: 0xFEC */ 9439 __I uint32_t COMPID[4]; /**< Component ID Register, array offset: 0xFF0, array step: 0x4 */ 9440 } ROM_Type; 9441 9442 /* ---------------------------------------------------------------------------- 9443 -- ROM Register Masks 9444 ---------------------------------------------------------------------------- */ 9445 9446 /*! 9447 * @addtogroup ROM_Register_Masks ROM Register Masks 9448 * @{ 9449 */ 9450 9451 /*! @name ENTRY - Entry */ 9452 /*! @{ */ 9453 #define ROM_ENTRY_ENTRY_MASK (0xFFFFFFFFU) 9454 #define ROM_ENTRY_ENTRY_SHIFT (0U) 9455 #define ROM_ENTRY_ENTRY(x) (((uint32_t)(((uint32_t)(x)) << ROM_ENTRY_ENTRY_SHIFT)) & ROM_ENTRY_ENTRY_MASK) 9456 /*! @} */ 9457 9458 /* The count of ROM_ENTRY */ 9459 #define ROM_ENTRY_COUNT (3U) 9460 9461 /*! @name TABLEMARK - End of Table Marker Register */ 9462 /*! @{ */ 9463 #define ROM_TABLEMARK_MARK_MASK (0xFFFFFFFFU) 9464 #define ROM_TABLEMARK_MARK_SHIFT (0U) 9465 #define ROM_TABLEMARK_MARK(x) (((uint32_t)(((uint32_t)(x)) << ROM_TABLEMARK_MARK_SHIFT)) & ROM_TABLEMARK_MARK_MASK) 9466 /*! @} */ 9467 9468 /*! @name SYSACCESS - System Access Register */ 9469 /*! @{ */ 9470 #define ROM_SYSACCESS_SYSACCESS_MASK (0xFFFFFFFFU) 9471 #define ROM_SYSACCESS_SYSACCESS_SHIFT (0U) 9472 #define ROM_SYSACCESS_SYSACCESS(x) (((uint32_t)(((uint32_t)(x)) << ROM_SYSACCESS_SYSACCESS_SHIFT)) & ROM_SYSACCESS_SYSACCESS_MASK) 9473 /*! @} */ 9474 9475 /*! @name PERIPHID4 - Peripheral ID Register */ 9476 /*! @{ */ 9477 #define ROM_PERIPHID4_PERIPHID_MASK (0xFFFFFFFFU) 9478 #define ROM_PERIPHID4_PERIPHID_SHIFT (0U) 9479 #define ROM_PERIPHID4_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << ROM_PERIPHID4_PERIPHID_SHIFT)) & ROM_PERIPHID4_PERIPHID_MASK) 9480 /*! @} */ 9481 9482 /*! @name PERIPHID5 - Peripheral ID Register */ 9483 /*! @{ */ 9484 #define ROM_PERIPHID5_PERIPHID_MASK (0xFFFFFFFFU) 9485 #define ROM_PERIPHID5_PERIPHID_SHIFT (0U) 9486 #define ROM_PERIPHID5_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << ROM_PERIPHID5_PERIPHID_SHIFT)) & ROM_PERIPHID5_PERIPHID_MASK) 9487 /*! @} */ 9488 9489 /*! @name PERIPHID6 - Peripheral ID Register */ 9490 /*! @{ */ 9491 #define ROM_PERIPHID6_PERIPHID_MASK (0xFFFFFFFFU) 9492 #define ROM_PERIPHID6_PERIPHID_SHIFT (0U) 9493 #define ROM_PERIPHID6_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << ROM_PERIPHID6_PERIPHID_SHIFT)) & ROM_PERIPHID6_PERIPHID_MASK) 9494 /*! @} */ 9495 9496 /*! @name PERIPHID7 - Peripheral ID Register */ 9497 /*! @{ */ 9498 #define ROM_PERIPHID7_PERIPHID_MASK (0xFFFFFFFFU) 9499 #define ROM_PERIPHID7_PERIPHID_SHIFT (0U) 9500 #define ROM_PERIPHID7_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << ROM_PERIPHID7_PERIPHID_SHIFT)) & ROM_PERIPHID7_PERIPHID_MASK) 9501 /*! @} */ 9502 9503 /*! @name PERIPHID0 - Peripheral ID Register */ 9504 /*! @{ */ 9505 #define ROM_PERIPHID0_PERIPHID_MASK (0xFFFFFFFFU) 9506 #define ROM_PERIPHID0_PERIPHID_SHIFT (0U) 9507 #define ROM_PERIPHID0_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << ROM_PERIPHID0_PERIPHID_SHIFT)) & ROM_PERIPHID0_PERIPHID_MASK) 9508 /*! @} */ 9509 9510 /*! @name PERIPHID1 - Peripheral ID Register */ 9511 /*! @{ */ 9512 #define ROM_PERIPHID1_PERIPHID_MASK (0xFFFFFFFFU) 9513 #define ROM_PERIPHID1_PERIPHID_SHIFT (0U) 9514 #define ROM_PERIPHID1_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << ROM_PERIPHID1_PERIPHID_SHIFT)) & ROM_PERIPHID1_PERIPHID_MASK) 9515 /*! @} */ 9516 9517 /*! @name PERIPHID2 - Peripheral ID Register */ 9518 /*! @{ */ 9519 #define ROM_PERIPHID2_PERIPHID_MASK (0xFFFFFFFFU) 9520 #define ROM_PERIPHID2_PERIPHID_SHIFT (0U) 9521 #define ROM_PERIPHID2_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << ROM_PERIPHID2_PERIPHID_SHIFT)) & ROM_PERIPHID2_PERIPHID_MASK) 9522 /*! @} */ 9523 9524 /*! @name PERIPHID3 - Peripheral ID Register */ 9525 /*! @{ */ 9526 #define ROM_PERIPHID3_PERIPHID_MASK (0xFFFFFFFFU) 9527 #define ROM_PERIPHID3_PERIPHID_SHIFT (0U) 9528 #define ROM_PERIPHID3_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << ROM_PERIPHID3_PERIPHID_SHIFT)) & ROM_PERIPHID3_PERIPHID_MASK) 9529 /*! @} */ 9530 9531 /*! @name COMPID - Component ID Register */ 9532 /*! @{ */ 9533 #define ROM_COMPID_COMPID_MASK (0xFFFFFFFFU) 9534 #define ROM_COMPID_COMPID_SHIFT (0U) 9535 #define ROM_COMPID_COMPID(x) (((uint32_t)(((uint32_t)(x)) << ROM_COMPID_COMPID_SHIFT)) & ROM_COMPID_COMPID_MASK) 9536 /*! @} */ 9537 9538 /* The count of ROM_COMPID */ 9539 #define ROM_COMPID_COUNT (4U) 9540 9541 9542 /*! 9543 * @} 9544 */ /* end of group ROM_Register_Masks */ 9545 9546 9547 /* ROM - Peripheral instance base addresses */ 9548 /** Peripheral ROM base address */ 9549 #define ROM_BASE (0xF0002000u) 9550 /** Peripheral ROM base pointer */ 9551 #define ROM ((ROM_Type *)ROM_BASE) 9552 /** Array initializer of ROM peripheral base addresses */ 9553 #define ROM_BASE_ADDRS { ROM_BASE } 9554 /** Array initializer of ROM peripheral base pointers */ 9555 #define ROM_BASE_PTRS { ROM } 9556 9557 /*! 9558 * @} 9559 */ /* end of group ROM_Peripheral_Access_Layer */ 9560 9561 9562 /* ---------------------------------------------------------------------------- 9563 -- SIM Peripheral Access Layer 9564 ---------------------------------------------------------------------------- */ 9565 9566 /*! 9567 * @addtogroup SIM_Peripheral_Access_Layer SIM Peripheral Access Layer 9568 * @{ 9569 */ 9570 9571 /** SIM - Register Layout Typedef */ 9572 typedef struct { 9573 __IO uint32_t SOPT1; /**< System Options Register 1, offset: 0x0 */ 9574 uint8_t RESERVED_0[4096]; 9575 __IO uint32_t SOPT2; /**< System Options Register 2, offset: 0x1004 */ 9576 uint8_t RESERVED_1[4]; 9577 __IO uint32_t SOPT4; /**< System Options Register 4, offset: 0x100C */ 9578 __IO uint32_t SOPT5; /**< System Options Register 5, offset: 0x1010 */ 9579 __IO uint32_t SOPT6; /**< Systems Option Register 6, offset: 0x1014 */ 9580 __IO uint32_t SOPT7; /**< System Options Register 7, offset: 0x1018 */ 9581 __IO uint32_t SOPT8; /**< System Options Register 8, offset: 0x101C */ 9582 __IO uint32_t SOPT9; /**< System Options Register 9, offset: 0x1020 */ 9583 __I uint32_t SDID; /**< System Device Identification Register, offset: 0x1024 */ 9584 uint8_t RESERVED_2[12]; 9585 __IO uint32_t SCGC4; /**< System Clock Gating Control Register 4, offset: 0x1034 */ 9586 __IO uint32_t SCGC5; /**< System Clock Gating Control Register 5, offset: 0x1038 */ 9587 __IO uint32_t SCGC6; /**< System Clock Gating Control Register 6, offset: 0x103C */ 9588 __IO uint32_t SCGC7; /**< System Clock Gating Control Register 7, offset: 0x1040 */ 9589 __IO uint32_t CLKDIV1; /**< System Clock Divider Register 1, offset: 0x1044 */ 9590 uint8_t RESERVED_3[4]; 9591 __IO uint32_t FCFG1; /**< Flash Configuration Register 1, offset: 0x104C */ 9592 __I uint32_t FCFG2; /**< Flash Configuration Register 2, offset: 0x1050 */ 9593 uint8_t RESERVED_4[4]; 9594 __I uint32_t UIDMH; /**< Unique Identification Register Mid-High, offset: 0x1058 */ 9595 __I uint32_t UIDML; /**< Unique Identification Register Mid Low, offset: 0x105C */ 9596 __I uint32_t UIDL; /**< Unique Identification Register Low, offset: 0x1060 */ 9597 uint8_t RESERVED_5[156]; 9598 __IO uint32_t WDOGC; /**< WDOG Control Register, offset: 0x1100 */ 9599 } SIM_Type; 9600 9601 /* ---------------------------------------------------------------------------- 9602 -- SIM Register Masks 9603 ---------------------------------------------------------------------------- */ 9604 9605 /*! 9606 * @addtogroup SIM_Register_Masks SIM Register Masks 9607 * @{ 9608 */ 9609 9610 /*! @name SOPT1 - System Options Register 1 */ 9611 /*! @{ */ 9612 #define SIM_SOPT1_OSC32KSEL_MASK (0xC0000U) 9613 #define SIM_SOPT1_OSC32KSEL_SHIFT (18U) 9614 /*! OSC32KSEL - 32K Oscillator Clock Select 9615 * 0b00..System oscillator (OSC32KCLK) 9616 * 0b01..Reserved 9617 * 0b10..Reserved 9618 * 0b11..LPO 1 kHz 9619 */ 9620 #define SIM_SOPT1_OSC32KSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1_OSC32KSEL_SHIFT)) & SIM_SOPT1_OSC32KSEL_MASK) 9621 /*! @} */ 9622 9623 /*! @name SOPT2 - System Options Register 2 */ 9624 /*! @{ */ 9625 #define SIM_SOPT2_CLKOUTSEL_MASK (0xE0U) 9626 #define SIM_SOPT2_CLKOUTSEL_SHIFT (5U) 9627 /*! CLKOUTSEL - CLKOUT Select 9628 * 0b000..Reserved 9629 * 0b001..Reserved 9630 * 0b010..Bus clock 9631 * 0b011..LPO clock (1 kHz) 9632 * 0b100..MCGIRCLK 9633 * 0b101..Reserved 9634 * 0b110..OSCERCLK 9635 * 0b111..Reserved 9636 */ 9637 #define SIM_SOPT2_CLKOUTSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_CLKOUTSEL_SHIFT)) & SIM_SOPT2_CLKOUTSEL_MASK) 9638 #define SIM_SOPT2_FTMFFCLKSEL_MASK (0x3000000U) 9639 #define SIM_SOPT2_FTMFFCLKSEL_SHIFT (24U) 9640 /*! FTMFFCLKSEL - FTM Fixed Frequency Clock Select 9641 * 0b00..MCGFFCLK 9642 * 0b01..MCGIRCLK 9643 * 0b10..OSCERCLK 9644 * 0b11..MCGFFCLK 9645 */ 9646 #define SIM_SOPT2_FTMFFCLKSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_FTMFFCLKSEL_SHIFT)) & SIM_SOPT2_FTMFFCLKSEL_MASK) 9647 /*! @} */ 9648 9649 /*! @name SOPT4 - System Options Register 4 */ 9650 /*! @{ */ 9651 #define SIM_SOPT4_FTM0FLT0_MASK (0x1U) 9652 #define SIM_SOPT4_FTM0FLT0_SHIFT (0U) 9653 /*! FTM0FLT0 - FTM0 Fault 0 Select 9654 * 0b0..FTM0_FLT0 pin 9655 * 0b1..CMP0 out 9656 */ 9657 #define SIM_SOPT4_FTM0FLT0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM0FLT0_SHIFT)) & SIM_SOPT4_FTM0FLT0_MASK) 9658 #define SIM_SOPT4_FTM0FLT1_MASK (0x2U) 9659 #define SIM_SOPT4_FTM0FLT1_SHIFT (1U) 9660 /*! FTM0FLT1 - FTM0 Fault 1 Select 9661 * 0b0..FTM0_FLT1 pin 9662 * 0b1..CMP1 out 9663 */ 9664 #define SIM_SOPT4_FTM0FLT1(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM0FLT1_SHIFT)) & SIM_SOPT4_FTM0FLT1_MASK) 9665 #define SIM_SOPT4_FTM1FLT0_MASK (0x4U) 9666 #define SIM_SOPT4_FTM1FLT0_SHIFT (2U) 9667 /*! FTM1FLT0 - FTM1 Fault 0 Select 9668 * 0b0..FTM1_FLT0 pin 9669 * 0b1..CMP0 out 9670 */ 9671 #define SIM_SOPT4_FTM1FLT0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM1FLT0_SHIFT)) & SIM_SOPT4_FTM1FLT0_MASK) 9672 #define SIM_SOPT4_FTM2FLT0_MASK (0x8U) 9673 #define SIM_SOPT4_FTM2FLT0_SHIFT (3U) 9674 /*! FTM2FLT0 - FTM2 Fault 0 Select 9675 * 0b0..FTM2_FLT0 pin 9676 * 0b1..CMP0 out 9677 */ 9678 #define SIM_SOPT4_FTM2FLT0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM2FLT0_SHIFT)) & SIM_SOPT4_FTM2FLT0_MASK) 9679 #define SIM_SOPT4_FTM0TRG0SRC_MASK (0x80U) 9680 #define SIM_SOPT4_FTM0TRG0SRC_SHIFT (7U) 9681 /*! FTM0TRG0SRC - FlexTimer 0 Hardware Trigger 0 Source Select 9682 * 0b0..CMP0 output drives FTM0 hardware trigger 0 9683 * 0b1..FTM1 channel match drives FTM0 hardware trigger 0 9684 */ 9685 #define SIM_SOPT4_FTM0TRG0SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM0TRG0SRC_SHIFT)) & SIM_SOPT4_FTM0TRG0SRC_MASK) 9686 #define SIM_SOPT4_FTM0TRG1SRC_MASK (0x100U) 9687 #define SIM_SOPT4_FTM0TRG1SRC_SHIFT (8U) 9688 /*! FTM0TRG1SRC - FlexTimer 0 Hardware Trigger 1 Source Select 9689 * 0b0..PDB0 channel 1 trigger drives FTM0 hardware trigger 1 9690 * 0b1..FTM2 channel match drives FTM0 hardware trigger 1 9691 */ 9692 #define SIM_SOPT4_FTM0TRG1SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM0TRG1SRC_SHIFT)) & SIM_SOPT4_FTM0TRG1SRC_MASK) 9693 #define SIM_SOPT4_FTM0TRG2SRC_MASK (0x200U) 9694 #define SIM_SOPT4_FTM0TRG2SRC_SHIFT (9U) 9695 /*! FTM0TRG2SRC - FlexTimer 0 Hardware Trigger 2 Source Select 9696 * 0b0..CMP0 output drives FTM0 hardware trigger 2 9697 * 0b1..CMP1 output drives FTM0 hardware trigger 2 9698 */ 9699 #define SIM_SOPT4_FTM0TRG2SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM0TRG2SRC_SHIFT)) & SIM_SOPT4_FTM0TRG2SRC_MASK) 9700 #define SIM_SOPT4_FTM1TRG0SRC_MASK (0x400U) 9701 #define SIM_SOPT4_FTM1TRG0SRC_SHIFT (10U) 9702 /*! FTM1TRG0SRC - FlexTimer 1 Hardware Trigger 0 Source Select 9703 * 0b0..CMP0 output drives FTM1 hardware trigger 0 9704 * 0b1..FTM0 channel match drives FTM1 hardware trigger 0 9705 */ 9706 #define SIM_SOPT4_FTM1TRG0SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM1TRG0SRC_SHIFT)) & SIM_SOPT4_FTM1TRG0SRC_MASK) 9707 #define SIM_SOPT4_FTM1TRG1SRC_MASK (0x800U) 9708 #define SIM_SOPT4_FTM1TRG1SRC_SHIFT (11U) 9709 /*! FTM1TRG1SRC - FlexTimer 1 Hardware Trigger 1 Source Select 9710 * 0b0..PDB0 channel 1 trigger drives FTM1 hardware trigger 1 9711 * 0b1..FTM2 channel match drives FTM1 hardware trigger 1 9712 */ 9713 #define SIM_SOPT4_FTM1TRG1SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM1TRG1SRC_SHIFT)) & SIM_SOPT4_FTM1TRG1SRC_MASK) 9714 #define SIM_SOPT4_FTM1TRG2SRC_MASK (0x1000U) 9715 #define SIM_SOPT4_FTM1TRG2SRC_SHIFT (12U) 9716 /*! FTM1TRG2SRC - FlexTimer 1 Hardware Trigger 2 Source Select 9717 * 0b0..CMP0 output drives FTM1 hardware trigger 2 9718 * 0b1..CMP1 output drives FTM1 hardware trigger 2 9719 */ 9720 #define SIM_SOPT4_FTM1TRG2SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM1TRG2SRC_SHIFT)) & SIM_SOPT4_FTM1TRG2SRC_MASK) 9721 #define SIM_SOPT4_FTM2TRG0SRC_MASK (0x2000U) 9722 #define SIM_SOPT4_FTM2TRG0SRC_SHIFT (13U) 9723 /*! FTM2TRG0SRC - FlexTimer 2 Hardware Trigger 0 Source Select 9724 * 0b0..CMP0 output drives FTM2 hardware trigger 0 9725 * 0b1..FTM0 channel match drives FTM2 hardware trigger 0 9726 */ 9727 #define SIM_SOPT4_FTM2TRG0SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM2TRG0SRC_SHIFT)) & SIM_SOPT4_FTM2TRG0SRC_MASK) 9728 #define SIM_SOPT4_FTM2TRG1SRC_MASK (0x4000U) 9729 #define SIM_SOPT4_FTM2TRG1SRC_SHIFT (14U) 9730 /*! FTM2TRG1SRC - FlexTimer 2 Hardware Trigger 1 Source Select 9731 * 0b0..PDB0 output trigger 1 drives FTM2 hardware trigger 1 9732 * 0b1..FTM1 channel match drives FTM2 hardware trigger 1 9733 */ 9734 #define SIM_SOPT4_FTM2TRG1SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM2TRG1SRC_SHIFT)) & SIM_SOPT4_FTM2TRG1SRC_MASK) 9735 #define SIM_SOPT4_FTM2TRG2SRC_MASK (0x8000U) 9736 #define SIM_SOPT4_FTM2TRG2SRC_SHIFT (15U) 9737 /*! FTM2TRG2SRC - FlexTimer 2 Hardware Trigger 2 Source Select 9738 * 0b0..CMP0 output drives FTM2 hardware trigger 2 9739 * 0b1..CMP1 output drives FTM2 hardware trigger 2 9740 */ 9741 #define SIM_SOPT4_FTM2TRG2SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM2TRG2SRC_SHIFT)) & SIM_SOPT4_FTM2TRG2SRC_MASK) 9742 #define SIM_SOPT4_FTM1CH0SRC_MASK (0xC0000U) 9743 #define SIM_SOPT4_FTM1CH0SRC_SHIFT (18U) 9744 /*! FTM1CH0SRC - FTM1 Channel 0 Input Capture Source Select 9745 * 0b00..FTM1_CH0 signal 9746 * 0b01..CMP0 output 9747 * 0b10..CMP1 output 9748 * 0b11..Reserved 9749 */ 9750 #define SIM_SOPT4_FTM1CH0SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM1CH0SRC_SHIFT)) & SIM_SOPT4_FTM1CH0SRC_MASK) 9751 #define SIM_SOPT4_FTM2CH0SRC_MASK (0x300000U) 9752 #define SIM_SOPT4_FTM2CH0SRC_SHIFT (20U) 9753 /*! FTM2CH0SRC - FTM2 Channel 0 Input Capture Source Select 9754 * 0b00..FTM2_CH0 signal 9755 * 0b01..CMP0 output 9756 * 0b10..CMP1 output 9757 * 0b11..Reserved 9758 */ 9759 #define SIM_SOPT4_FTM2CH0SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM2CH0SRC_SHIFT)) & SIM_SOPT4_FTM2CH0SRC_MASK) 9760 #define SIM_SOPT4_FTM2CH1SRC_MASK (0x400000U) 9761 #define SIM_SOPT4_FTM2CH1SRC_SHIFT (22U) 9762 /*! FTM2CH1SRC - FTM2 Channel 1 Input Capture Source Select 9763 * 0b0..FTM2_CH1 pin is fed to FTM2 CH1 9764 * 0b1..FTM2_CH1 pin XOR FTM2_CH0 pin XOR FTM1_CH1 pin is fed to FTM2 CH1 If this field is set, then the three input pins feed FTM2 channel 1 input capture. In this case, FTM1 channel 1 cannot be used for input capture of FTM1, as it has no pin. FTM1 channel1 can be used for Output Compare mode of FTM1, though without an output. 9765 */ 9766 #define SIM_SOPT4_FTM2CH1SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM2CH1SRC_SHIFT)) & SIM_SOPT4_FTM2CH1SRC_MASK) 9767 #define SIM_SOPT4_FTM0CLKSEL_MASK (0x3000000U) 9768 #define SIM_SOPT4_FTM0CLKSEL_SHIFT (24U) 9769 /*! FTM0CLKSEL - FTM0 External Clock Pin Select 9770 * 0b00..FTM0 external clock driven by FTM_CLKIN0 pin 9771 * 0b01..FTM0 external clock driven by FTM_CLKIN1 pin 9772 * 0b10..FTM0 external clock driven by FTM_CLKIN2 pin 9773 * 0b11..Reserved 9774 */ 9775 #define SIM_SOPT4_FTM0CLKSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM0CLKSEL_SHIFT)) & SIM_SOPT4_FTM0CLKSEL_MASK) 9776 #define SIM_SOPT4_FTM1CLKSEL_MASK (0xC000000U) 9777 #define SIM_SOPT4_FTM1CLKSEL_SHIFT (26U) 9778 /*! FTM1CLKSEL - FTM1 External Clock Pin Select 9779 * 0b00..FTM1 external clock driven by FTM_CLKIN0 pin 9780 * 0b01..FTM1 external clock driven by FTM_CLKIN1 pin 9781 * 0b10..FTM1 external clock driven by FTM_CLKIN2 pin 9782 * 0b11..Reserved 9783 */ 9784 #define SIM_SOPT4_FTM1CLKSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM1CLKSEL_SHIFT)) & SIM_SOPT4_FTM1CLKSEL_MASK) 9785 #define SIM_SOPT4_FTM2CLKSEL_MASK (0x30000000U) 9786 #define SIM_SOPT4_FTM2CLKSEL_SHIFT (28U) 9787 /*! FTM2CLKSEL - FTM2 External Clock Pin Select 9788 * 0b00..FTM2 external clock driven by FTM_CLKIN0 pin 9789 * 0b01..FTM2 external clock driven by FTM_CLKIN1 pin 9790 * 0b10..FTM2 external clock driven by FTM_CLKIN2 pin 9791 * 0b11..Reserved 9792 */ 9793 #define SIM_SOPT4_FTM2CLKSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM2CLKSEL_SHIFT)) & SIM_SOPT4_FTM2CLKSEL_MASK) 9794 /*! @} */ 9795 9796 /*! @name SOPT5 - System Options Register 5 */ 9797 /*! @{ */ 9798 #define SIM_SOPT5_UART0TXSRC_MASK (0x3U) 9799 #define SIM_SOPT5_UART0TXSRC_SHIFT (0U) 9800 /*! UART0TXSRC - UART 0 Transmit Data Source Select 9801 * 0b00..UART0_TX pin 9802 * 0b01..UART0_TX pin modulated with FTM1 channel 0 output 9803 * 0b10..UART0_TX pin modulated with FTM2 channel 0 output 9804 * 0b11..Reserved 9805 */ 9806 #define SIM_SOPT5_UART0TXSRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT5_UART0TXSRC_SHIFT)) & SIM_SOPT5_UART0TXSRC_MASK) 9807 #define SIM_SOPT5_UART0RXSRC_MASK (0xCU) 9808 #define SIM_SOPT5_UART0RXSRC_SHIFT (2U) 9809 /*! UART0RXSRC - UART 0 Receive Data Source Select 9810 * 0b00..UART0_RX pin 9811 * 0b01..CMP0 9812 * 0b10..CMP1 9813 * 0b11..Reserved 9814 */ 9815 #define SIM_SOPT5_UART0RXSRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT5_UART0RXSRC_SHIFT)) & SIM_SOPT5_UART0RXSRC_MASK) 9816 #define SIM_SOPT5_UART1TXSRC_MASK (0x30U) 9817 #define SIM_SOPT5_UART1TXSRC_SHIFT (4U) 9818 /*! UART1TXSRC - UART 1 Transmit Data Source Select 9819 * 0b00..UART1_TX pin 9820 * 0b01..UART1_TX pin modulated with FTM1 channel 0 output 9821 * 0b10..UART1_TX pin modulated with FTM2 channel 0 output 9822 * 0b11..Reserved 9823 */ 9824 #define SIM_SOPT5_UART1TXSRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT5_UART1TXSRC_SHIFT)) & SIM_SOPT5_UART1TXSRC_MASK) 9825 #define SIM_SOPT5_UART1RXSRC_MASK (0xC0U) 9826 #define SIM_SOPT5_UART1RXSRC_SHIFT (6U) 9827 /*! UART1RXSRC - UART 1 Receive Data Source Select 9828 * 0b00..UART1_RX pin 9829 * 0b01..CMP0 9830 * 0b10..CMP1 9831 * 0b11..Reserved 9832 */ 9833 #define SIM_SOPT5_UART1RXSRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT5_UART1RXSRC_SHIFT)) & SIM_SOPT5_UART1RXSRC_MASK) 9834 #define SIM_SOPT5_UART0ODE_MASK (0x10000U) 9835 #define SIM_SOPT5_UART0ODE_SHIFT (16U) 9836 /*! UART0ODE - UART0 Open Drain Enable 9837 * 0b0..Open drain is disabled on UART0 9838 * 0b1..Open drain is enabled on UART0 9839 */ 9840 #define SIM_SOPT5_UART0ODE(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT5_UART0ODE_SHIFT)) & SIM_SOPT5_UART0ODE_MASK) 9841 #define SIM_SOPT5_UART1ODE_MASK (0x20000U) 9842 #define SIM_SOPT5_UART1ODE_SHIFT (17U) 9843 /*! UART1ODE - UART1 Open Drain Enable 9844 * 0b0..Open drain is disabled on UART1 9845 * 0b1..Open drain is enabled on UART1 9846 */ 9847 #define SIM_SOPT5_UART1ODE(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT5_UART1ODE_SHIFT)) & SIM_SOPT5_UART1ODE_MASK) 9848 /*! @} */ 9849 9850 /*! @name SOPT6 - Systems Option Register 6 */ 9851 /*! @{ */ 9852 #define SIM_SOPT6_FTM3FLT0_MASK (0x1U) 9853 #define SIM_SOPT6_FTM3FLT0_SHIFT (0U) 9854 /*! FTM3FLT0 - FTM3 Fault 0 Select 9855 * 0b0..FTM3_FLT0 pin 9856 * 0b1..CMP0 out 9857 */ 9858 #define SIM_SOPT6_FTM3FLT0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT6_FTM3FLT0_SHIFT)) & SIM_SOPT6_FTM3FLT0_MASK) 9859 #define SIM_SOPT6_FTM4FLT0_MASK (0x4U) 9860 #define SIM_SOPT6_FTM4FLT0_SHIFT (2U) 9861 /*! FTM4FLT0 - FTM4 Fault 0 Select 9862 * 0b0..FTM4_FLT0 pin 9863 * 0b1..CMP0 out 9864 */ 9865 #define SIM_SOPT6_FTM4FLT0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT6_FTM4FLT0_SHIFT)) & SIM_SOPT6_FTM4FLT0_MASK) 9866 #define SIM_SOPT6_FTM5FLT0_MASK (0x8U) 9867 #define SIM_SOPT6_FTM5FLT0_SHIFT (3U) 9868 /*! FTM5FLT0 - FTM5 Fault 0 Select 9869 * 0b0..FTM5_FLT0 pin 9870 * 0b1..CMP0 out 9871 */ 9872 #define SIM_SOPT6_FTM5FLT0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT6_FTM5FLT0_SHIFT)) & SIM_SOPT6_FTM5FLT0_MASK) 9873 #define SIM_SOPT6_FTM3TRG0SRC_MASK (0x80U) 9874 #define SIM_SOPT6_FTM3TRG0SRC_SHIFT (7U) 9875 /*! FTM3TRG0SRC - FlexTimer 3 Hardware Trigger 0 Source Select 9876 * 0b0..CMP0 output drives FTM3 hardware trigger 0 9877 * 0b1..FTM5 channel match drives FTM3 hardware trigger 0 9878 */ 9879 #define SIM_SOPT6_FTM3TRG0SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT6_FTM3TRG0SRC_SHIFT)) & SIM_SOPT6_FTM3TRG0SRC_MASK) 9880 #define SIM_SOPT6_FTM3TRG1SRC_MASK (0x100U) 9881 #define SIM_SOPT6_FTM3TRG1SRC_SHIFT (8U) 9882 /*! FTM3TRG1SRC - FlexTimer 3 Hardware Trigger 1 Source Select 9883 * 0b0..PDB1 output drives FTM3 hardware trigger 1 9884 * 0b1..FTM4 channel match drives FTM3 hardware trigger 1 9885 */ 9886 #define SIM_SOPT6_FTM3TRG1SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT6_FTM3TRG1SRC_SHIFT)) & SIM_SOPT6_FTM3TRG1SRC_MASK) 9887 #define SIM_SOPT6_FTM3TRG2SRC_MASK (0x200U) 9888 #define SIM_SOPT6_FTM3TRG2SRC_SHIFT (9U) 9889 /*! FTM3TRG2SRC - FlexTimer 3 Hardware Trigger 2 Source Select 9890 * 0b0..CMP0 output drives FTM3 hardware trigger 2 9891 * 0b1..CMP1 output drives FTM3 hardware trigger 2 9892 */ 9893 #define SIM_SOPT6_FTM3TRG2SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT6_FTM3TRG2SRC_SHIFT)) & SIM_SOPT6_FTM3TRG2SRC_MASK) 9894 #define SIM_SOPT6_FTM4TRG0SRC_MASK (0x400U) 9895 #define SIM_SOPT6_FTM4TRG0SRC_SHIFT (10U) 9896 /*! FTM4TRG0SRC - FlexTimer 4 Hardware Trigger 0 Source Select 9897 * 0b0..CMP0 output drives FTM4 hardware trigger 0 9898 * 0b1..FTM3 channel match drives FTM4 hardware trigger 0 9899 */ 9900 #define SIM_SOPT6_FTM4TRG0SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT6_FTM4TRG0SRC_SHIFT)) & SIM_SOPT6_FTM4TRG0SRC_MASK) 9901 #define SIM_SOPT6_FTM4TRG1SRC_MASK (0x800U) 9902 #define SIM_SOPT6_FTM4TRG1SRC_SHIFT (11U) 9903 /*! FTM4TRG1SRC - FlexTimer 4 Hardware Trigger 1 Source Select 9904 * 0b0..PDB1 output trigger 1 drives FTM4 hardware trigger 1 9905 * 0b1..FTM5 channel match drives FTM4 hardware trigger 1 9906 */ 9907 #define SIM_SOPT6_FTM4TRG1SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT6_FTM4TRG1SRC_SHIFT)) & SIM_SOPT6_FTM4TRG1SRC_MASK) 9908 #define SIM_SOPT6_FTM4TRG2SRC_MASK (0x1000U) 9909 #define SIM_SOPT6_FTM4TRG2SRC_SHIFT (12U) 9910 /*! FTM4TRG2SRC - FlexTimer 4 Hardware Trigger 2 Source Select 9911 * 0b0..CMP0 output drives FTM4 hardware trigger 2 9912 * 0b1..CMP1 output drives FTM4 hardware trigger 2 9913 */ 9914 #define SIM_SOPT6_FTM4TRG2SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT6_FTM4TRG2SRC_SHIFT)) & SIM_SOPT6_FTM4TRG2SRC_MASK) 9915 #define SIM_SOPT6_FTM5TRG0SRC_MASK (0x2000U) 9916 #define SIM_SOPT6_FTM5TRG0SRC_SHIFT (13U) 9917 /*! FTM5TRG0SRC - FlexTimer 5 Hardware Trigger 0 Source Select 9918 * 0b0..CMP0 output drives FTM5 hardware trigger 0 9919 * 0b1..FTM3 channel match drives FTM5 hardware trigger 0 9920 */ 9921 #define SIM_SOPT6_FTM5TRG0SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT6_FTM5TRG0SRC_SHIFT)) & SIM_SOPT6_FTM5TRG0SRC_MASK) 9922 #define SIM_SOPT6_FTM5TRG1SRC_MASK (0x4000U) 9923 #define SIM_SOPT6_FTM5TRG1SRC_SHIFT (14U) 9924 /*! FTM5TRG1SRC - FlexTimer 5 Hardware Trigger 1 Source Select 9925 * 0b0..PDB1 output trigger 1 drives FTM5 hardware trigger 1 9926 * 0b1..FTM4 channel match drives FTM5 hardware trigger 1 9927 */ 9928 #define SIM_SOPT6_FTM5TRG1SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT6_FTM5TRG1SRC_SHIFT)) & SIM_SOPT6_FTM5TRG1SRC_MASK) 9929 #define SIM_SOPT6_FTM5TRG2SRC_MASK (0x8000U) 9930 #define SIM_SOPT6_FTM5TRG2SRC_SHIFT (15U) 9931 /*! FTM5TRG2SRC - FlexTimer 5 Hardware Trigger 2 Source Select 9932 * 0b0..CMP0 output drives FTM5 hardware trigger 2 9933 * 0b1..CMP1 output drives FTM5 hardware trigger 2 9934 */ 9935 #define SIM_SOPT6_FTM5TRG2SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT6_FTM5TRG2SRC_SHIFT)) & SIM_SOPT6_FTM5TRG2SRC_MASK) 9936 #define SIM_SOPT6_FTM4CH0SRC_MASK (0xC0000U) 9937 #define SIM_SOPT6_FTM4CH0SRC_SHIFT (18U) 9938 /*! FTM4CH0SRC - FTM4 channel 0 input capture source select 9939 * 0b00..FTM4_CH0 signal 9940 * 0b01..CMP0 output 9941 * 0b10..CMP1 output 9942 * 0b11..Reserved 9943 */ 9944 #define SIM_SOPT6_FTM4CH0SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT6_FTM4CH0SRC_SHIFT)) & SIM_SOPT6_FTM4CH0SRC_MASK) 9945 #define SIM_SOPT6_FTM5CH0SRC_MASK (0x300000U) 9946 #define SIM_SOPT6_FTM5CH0SRC_SHIFT (20U) 9947 /*! FTM5CH0SRC - FTM5 channel 0 input capture source select 9948 * 0b00..FTM5_CH0 signal 9949 * 0b01..CMP0 output 9950 * 0b10..CMP1 output 9951 * 0b11..Reserved 9952 */ 9953 #define SIM_SOPT6_FTM5CH0SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT6_FTM5CH0SRC_SHIFT)) & SIM_SOPT6_FTM5CH0SRC_MASK) 9954 #define SIM_SOPT6_FTM3CLKSEL_MASK (0x3000000U) 9955 #define SIM_SOPT6_FTM3CLKSEL_SHIFT (24U) 9956 /*! FTM3CLKSEL - FTM3 External Clock Pin Select 9957 * 0b00..FTM3 external clock driven by FTM_CLKIN0 pin 9958 * 0b01..FTM3 external clock driven by FTM_CLKIN1 pin 9959 * 0b10..FTM3 external clock driven by FTM_CLKIN2 pin 9960 * 0b11..Reserved 9961 */ 9962 #define SIM_SOPT6_FTM3CLKSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT6_FTM3CLKSEL_SHIFT)) & SIM_SOPT6_FTM3CLKSEL_MASK) 9963 #define SIM_SOPT6_FTM4CLKSEL_MASK (0xC000000U) 9964 #define SIM_SOPT6_FTM4CLKSEL_SHIFT (26U) 9965 /*! FTM4CLKSEL - FTM4 External Clock Pin Select 9966 * 0b00..FTM4 external clock driven by FTM_CLKIN0 pin 9967 * 0b01..FTM4 external clock driven by FTM_CLKIN1 pin 9968 * 0b10..FTM4 external clock driven by FTM_CLKIN2 pin 9969 * 0b11..Reserved 9970 */ 9971 #define SIM_SOPT6_FTM4CLKSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT6_FTM4CLKSEL_SHIFT)) & SIM_SOPT6_FTM4CLKSEL_MASK) 9972 #define SIM_SOPT6_FTM5CLKSEL_MASK (0x30000000U) 9973 #define SIM_SOPT6_FTM5CLKSEL_SHIFT (28U) 9974 /*! FTM5CLKSEL - FTM5 External Clock Pin Select 9975 * 0b00..FTM5 external clock driven by FTM_CLKIN0 pin 9976 * 0b01..FTM5 external clock driven by FTM_CLKIN1 pin 9977 * 0b10..FTM5 external clock driven by FTM_CLKIN2 pin 9978 * 0b11..Reserved 9979 */ 9980 #define SIM_SOPT6_FTM5CLKSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT6_FTM5CLKSEL_SHIFT)) & SIM_SOPT6_FTM5CLKSEL_MASK) 9981 /*! @} */ 9982 9983 /*! @name SOPT7 - System Options Register 7 */ 9984 /*! @{ */ 9985 #define SIM_SOPT7_ADC0TRGSEL_MASK (0xFU) 9986 #define SIM_SOPT7_ADC0TRGSEL_SHIFT (0U) 9987 /*! ADC0TRGSEL - ADC0 Trigger Select 9988 * 0b0000..External trigger pin input (PDB_EXTRG0) 9989 * 0b0001..CMP0 output 9990 * 0b0010..CMP1 output 9991 * 0b0011..External trigger pin input (PDB_EXTRG1) 9992 * 0b0100..DMA channel 0 transfer last write complete 9993 * 0b0101..DMA channel 1 transfer last write complete 9994 * 0b0110..DMA channel 2 transfer last write complete 9995 * 0b0111..DMA channel 3 transfer last write complete 9996 * 0b1000..FTM0 intialtrig or external trig output 9997 * 0b1001..FTM1 intial trig or external trig output 9998 * 0b1010..FTM2 intial trig or external trig output 9999 * 0b1011..FTM3 intial trig or external trig output 10000 * 0b1100..FTM4 intial trig or external trig output 10001 * 0b1101..FTM5 intial trig or external trig output 10002 * 0b1110..LPTMR0 trigger 10003 * 0b1111..Reserved 10004 */ 10005 #define SIM_SOPT7_ADC0TRGSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT7_ADC0TRGSEL_SHIFT)) & SIM_SOPT7_ADC0TRGSEL_MASK) 10006 #define SIM_SOPT7_ADC0PRETRGSEL_MASK (0x10U) 10007 #define SIM_SOPT7_ADC0PRETRGSEL_SHIFT (4U) 10008 /*! ADC0PRETRGSEL - ADC0 Pre-trigger Select 10009 * 0b0..Pre-trigger A for ADC0. Clearing this field will result in ADHWTSA=1 and ADHWTSB=0. 10010 * 0b1..Pre-trigger B for ADC0. Setting this bit will result in ADHWTSA=0 and ADHWTSB=1. 10011 */ 10012 #define SIM_SOPT7_ADC0PRETRGSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT7_ADC0PRETRGSEL_SHIFT)) & SIM_SOPT7_ADC0PRETRGSEL_MASK) 10013 #define SIM_SOPT7_ADC0ALTTRGEN_MASK (0xC0U) 10014 #define SIM_SOPT7_ADC0ALTTRGEN_SHIFT (6U) 10015 /*! ADC0ALTTRGEN 10016 * 0b00..PDB0 CH0 triggers ADC0 10017 * 0b01..PDB1 CH0 triggers ADC0 10018 * 0b10..Alt trigger source as per ADC0TRGSEL 10019 * 0b11..PDB0 CH0 OR PDB1 CH0 trigger ADC0 10020 */ 10021 #define SIM_SOPT7_ADC0ALTTRGEN(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT7_ADC0ALTTRGEN_SHIFT)) & SIM_SOPT7_ADC0ALTTRGEN_MASK) 10022 #define SIM_SOPT7_ADC1TRGSEL_MASK (0xF00U) 10023 #define SIM_SOPT7_ADC1TRGSEL_SHIFT (8U) 10024 /*! ADC1TRGSEL - ADC1 Trigger Select 10025 * 0b0000..External trigger pin input (PDB_EXTRG0) 10026 * 0b0001..CMP0 output 10027 * 0b0010..CMP1 output 10028 * 0b0011..External trigger pin input (PDB_EXTRG1) 10029 * 0b0100..DMA channel 0 transfer last write complete 10030 * 0b0101..DMA channel 1 transfer last write complete 10031 * 0b0110..DMA channel 2 transfer last write complete 10032 * 0b0111..DMA channel 3 transfer last write complete 10033 * 0b1000..FTM0 intialtrig or external trig output 10034 * 0b1001..FTM1 intial trig or external trig output 10035 * 0b1010..FTM2 intial trig or external trig output 10036 * 0b1011..FTM3 intial trig or external trig output 10037 * 0b1100..FTM4 intial trig or external trig output 10038 * 0b1101..FTM5 intial trig or external trig output 10039 * 0b1110..LPTMR0 trigger 10040 * 0b1111..Reserved 10041 */ 10042 #define SIM_SOPT7_ADC1TRGSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT7_ADC1TRGSEL_SHIFT)) & SIM_SOPT7_ADC1TRGSEL_MASK) 10043 #define SIM_SOPT7_ADC1PRETRGSEL_MASK (0x1000U) 10044 #define SIM_SOPT7_ADC1PRETRGSEL_SHIFT (12U) 10045 /*! ADC1PRETRGSEL - ADC1 Pre-trigger Select 10046 * 0b0..Pre-trigger A for ADC1. Clearing this field will result in ADHWTSA=1 and ADHWTSB=0. 10047 * 0b1..Pre-trigger B for ADC1. Setting this bit will result in ADHWTSA=0 and ADHWTSB=1. 10048 */ 10049 #define SIM_SOPT7_ADC1PRETRGSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT7_ADC1PRETRGSEL_SHIFT)) & SIM_SOPT7_ADC1PRETRGSEL_MASK) 10050 #define SIM_SOPT7_ADC1ALTTRGEN_MASK (0xC000U) 10051 #define SIM_SOPT7_ADC1ALTTRGEN_SHIFT (14U) 10052 /*! ADC1ALTTRGEN 10053 * 0b00..PDB0 CH1 triggers ADC1 10054 * 0b01..PDB1 CH1 triggers ADC1 10055 * 0b10..Alt trigger source ADC1TRGSEL 10056 * 0b11..PDB0 CH1 OR PDB1 CH1 trigger ADC1 10057 */ 10058 #define SIM_SOPT7_ADC1ALTTRGEN(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT7_ADC1ALTTRGEN_SHIFT)) & SIM_SOPT7_ADC1ALTTRGEN_MASK) 10059 #define SIM_SOPT7_ADC0ALTCLKSRC_MASK (0x3000000U) 10060 #define SIM_SOPT7_ADC0ALTCLKSRC_SHIFT (24U) 10061 /*! ADC0ALTCLKSRC - ADC0 ALT Clock Source Select 10062 * 0b00..OUTDIV5 output 10063 * 0b01..MCGIRCLK 10064 * 0b10..OSCERCLK 10065 * 0b11..Reserved 10066 */ 10067 #define SIM_SOPT7_ADC0ALTCLKSRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT7_ADC0ALTCLKSRC_SHIFT)) & SIM_SOPT7_ADC0ALTCLKSRC_MASK) 10068 #define SIM_SOPT7_ADC1ALTCLKSRC_MASK (0xC000000U) 10069 #define SIM_SOPT7_ADC1ALTCLKSRC_SHIFT (26U) 10070 /*! ADC1ALTCLKSRC - ADC1 ALT Clock Source Select 10071 * 0b00..OUTDIV5 output 10072 * 0b01..MCGIRCLK 10073 * 0b10..OSCERCLK 10074 * 0b11..Reserved 10075 */ 10076 #define SIM_SOPT7_ADC1ALTCLKSRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT7_ADC1ALTCLKSRC_SHIFT)) & SIM_SOPT7_ADC1ALTCLKSRC_MASK) 10077 /*! @} */ 10078 10079 /*! @name SOPT8 - System Options Register 8 */ 10080 /*! @{ */ 10081 #define SIM_SOPT8_FTM0SYNCBIT_MASK (0x1U) 10082 #define SIM_SOPT8_FTM0SYNCBIT_SHIFT (0U) 10083 /*! FTM0SYNCBIT - FlexTimer 0 Hardware Trigger 0 configure by software 10084 * 0b0..No effect to FTM0; this allow the hardware trigger options to function as expected. See SOPT4[FTM0TRG0SRC]. 10085 * 0b1..If TRIG0 enabled, this refreshes the FTM0CNTIN and all buffered registers of the FTM0 (must write 0 first then write 1); this masks the hardware trigger. 10086 */ 10087 #define SIM_SOPT8_FTM0SYNCBIT(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM0SYNCBIT_SHIFT)) & SIM_SOPT8_FTM0SYNCBIT_MASK) 10088 #define SIM_SOPT8_FTM1SYNCBIT_MASK (0x2U) 10089 #define SIM_SOPT8_FTM1SYNCBIT_SHIFT (1U) 10090 /*! FTM1SYNCBIT - FlexTimer 1 Hardware Trigger 0 configure by software 10091 * 0b0..No effect to FTM1; this allows the hardware trigger options to function as expected. See SOPT4[FTM1TRG0SRC]. 10092 * 0b1..If TRIG0 enabled, this refreshes the FTM1CNTIN and all buffered registers of the FTM1 (must write 0 first then write 1); this masks the hardware trigger. 10093 */ 10094 #define SIM_SOPT8_FTM1SYNCBIT(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM1SYNCBIT_SHIFT)) & SIM_SOPT8_FTM1SYNCBIT_MASK) 10095 #define SIM_SOPT8_FTM2SYNCBIT_MASK (0x4U) 10096 #define SIM_SOPT8_FTM2SYNCBIT_SHIFT (2U) 10097 /*! FTM2SYNCBIT - FlexTimer 2 Hardware Trigger 0 configure by software 10098 * 0b0..No effect to FTM2; this allows the hardware trigger options to function as expected. See SOPT4[FTM2TRG0SRC]. 10099 * 0b1..If TRIG0 is enabled, this refreshes the FTM2CNTIN and all buffered registers of the FTM2 (must write 0 first then write 1); this masks the hardware trigger. 10100 */ 10101 #define SIM_SOPT8_FTM2SYNCBIT(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM2SYNCBIT_SHIFT)) & SIM_SOPT8_FTM2SYNCBIT_MASK) 10102 #define SIM_SOPT8_FTM3SYNCBIT_MASK (0x8U) 10103 #define SIM_SOPT8_FTM3SYNCBIT_SHIFT (3U) 10104 /*! FTM3SYNCBIT - FlexTimer 3 Hardware Trigger 0 configure by software 10105 * 0b0..No effect to FTM3; this allows the hardware trigger options to function as expected. See SOPT6[FTM3TRG0SRC]. 10106 * 0b1..If TRIG0 is enabled, this refreshes the FTM3CNTIN and allbuffered registers of the FTM3 (must write 0 first then write 1); this masks the hardware trigger. 10107 */ 10108 #define SIM_SOPT8_FTM3SYNCBIT(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM3SYNCBIT_SHIFT)) & SIM_SOPT8_FTM3SYNCBIT_MASK) 10109 #define SIM_SOPT8_FTM4SYNCBIT_MASK (0x10U) 10110 #define SIM_SOPT8_FTM4SYNCBIT_SHIFT (4U) 10111 /*! FTM4SYNCBIT - FlexTimer 4 Hardware Trigger 0 configure by software 10112 * 0b0..No effect to FTM4; this allows the hardware trigger options to function as expected. See SOPT6[FTM4TRG0SRC]. 10113 * 0b1..If TRIG0 is enabled, this refreshes the FTM4CNTIN and allbuffered registers of the FTM4 (must write 0 first then write 1); this masks the hardware trigger. 10114 */ 10115 #define SIM_SOPT8_FTM4SYNCBIT(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM4SYNCBIT_SHIFT)) & SIM_SOPT8_FTM4SYNCBIT_MASK) 10116 #define SIM_SOPT8_FTM5SYNCBIT_MASK (0x20U) 10117 #define SIM_SOPT8_FTM5SYNCBIT_SHIFT (5U) 10118 /*! FTM5SYNCBIT - FlexTimer 5 Hardware Trigger 0 configure by software 10119 * 0b0..No effect on FTM5; this allows the hardware trigger options to function as expected. See SOPT6[FTM5TRG0SRC]. 10120 * 0b1..If TRIG0 is enabled, this refreshes the FTM5CNTIN and allbuffered registers of the FTM5 (must write 0 first then write 1); this masks the hardware trigger. 10121 */ 10122 #define SIM_SOPT8_FTM5SYNCBIT(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM5SYNCBIT_SHIFT)) & SIM_SOPT8_FTM5SYNCBIT_MASK) 10123 #define SIM_SOPT8_CARRIER_SELECT0_MASK (0x300U) 10124 #define SIM_SOPT8_CARRIER_SELECT0_SHIFT (8U) 10125 /*! CARRIER_SELECT0 - Carrier frequency selection for FTM0/2 output channel 10126 * 0b00..FTM1_CH1 output provides the carrier signal for Timer Modulation mode 10127 * 0b01..LPTMR0 prescaler output provides the carrier signal for Timer Modulation mode 10128 * 0b10..FTM5_CH1 output provides the carrier signal for Timer Modulation mode 10129 * 0b11..Reserved 10130 */ 10131 #define SIM_SOPT8_CARRIER_SELECT0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_CARRIER_SELECT0_SHIFT)) & SIM_SOPT8_CARRIER_SELECT0_MASK) 10132 #define SIM_SOPT8_FTM0OCH0SRC_MASK (0x10000U) 10133 #define SIM_SOPT8_FTM0OCH0SRC_SHIFT (16U) 10134 /*! FTM0OCH0SRC - FTM0 channel 0 output PWM/OCMP mode source select 10135 * 0b0..FTM0CH0 pin is the output of FTM0 channel 0 PWM/OCMP 10136 * 0b1..FTM0CH0 pin is the output of FTM0 channel 0 PWM/OCMP modulating the carrier frequency, as per CARRIER_SELECT0 10137 */ 10138 #define SIM_SOPT8_FTM0OCH0SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM0OCH0SRC_SHIFT)) & SIM_SOPT8_FTM0OCH0SRC_MASK) 10139 #define SIM_SOPT8_FTM0OCH1SRC_MASK (0x20000U) 10140 #define SIM_SOPT8_FTM0OCH1SRC_SHIFT (17U) 10141 /*! FTM0OCH1SRC - FTM0 channel 1 output PWM/OCMP mode source select 10142 * 0b0..FTM0CH1 pin is the output of FTM0 channel 1 PWM/OCMP 10143 * 0b1..FTM0CH1 pin is the output of FTM0 channel 1 PWM/OCMP modulating the carrier frequency, as per CARRIER_SELECT0 10144 */ 10145 #define SIM_SOPT8_FTM0OCH1SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM0OCH1SRC_SHIFT)) & SIM_SOPT8_FTM0OCH1SRC_MASK) 10146 #define SIM_SOPT8_FTM0OCH2SRC_MASK (0x40000U) 10147 #define SIM_SOPT8_FTM0OCH2SRC_SHIFT (18U) 10148 /*! FTM0OCH2SRC - FTM0 channel 2 output PWM/OCMP mode source select 10149 * 0b0..FTM0CH2 pin is the output of FTM0 channel 2 PWM/OCMP 10150 * 0b1..FTM0CH2 pin is the output of FTM0 channel 2 PWM/OCMP modulating the carrier frequency, as per CARRIER_SELECT0 10151 */ 10152 #define SIM_SOPT8_FTM0OCH2SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM0OCH2SRC_SHIFT)) & SIM_SOPT8_FTM0OCH2SRC_MASK) 10153 #define SIM_SOPT8_FTM0OCH3SRC_MASK (0x80000U) 10154 #define SIM_SOPT8_FTM0OCH3SRC_SHIFT (19U) 10155 /*! FTM0OCH3SRC - FTM0 channel 3 output PWM/OCMP mode source select 10156 * 0b0..FTM0CH3 pin is the output of FTM0 channel 3 PWM/OCMP 10157 * 0b1..FTM0CH3 pin is the output of FTM0 channel 3 PWM/OCMP modulating the carrier frequency, as per CARRIER_SELECT0 10158 */ 10159 #define SIM_SOPT8_FTM0OCH3SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM0OCH3SRC_SHIFT)) & SIM_SOPT8_FTM0OCH3SRC_MASK) 10160 #define SIM_SOPT8_FTM0OCH4SRC_MASK (0x100000U) 10161 #define SIM_SOPT8_FTM0OCH4SRC_SHIFT (20U) 10162 /*! FTM0OCH4SRC - FTM0 channel 4 output PWM/OCMP mode source select 10163 * 0b0..FTM0CH4 pin is the output of FTM0 channel 4 PWM/OCMP 10164 * 0b1..FTM0CH4 pin is the output of FTM0 channel 4 PWM/OCMP modulating the carrier frequency, as per CARRIER_SELECT0 10165 */ 10166 #define SIM_SOPT8_FTM0OCH4SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM0OCH4SRC_SHIFT)) & SIM_SOPT8_FTM0OCH4SRC_MASK) 10167 #define SIM_SOPT8_FTM0OCH5SRC_MASK (0x200000U) 10168 #define SIM_SOPT8_FTM0OCH5SRC_SHIFT (21U) 10169 /*! FTM0OCH5SRC - FTM0 channel 5 output PWM/OCMP mode source select 10170 * 0b0..FTM0CH5 pin is the output of FTM0 channel 5 PWM/OCMP 10171 * 0b1..FTM0CH5 pin is the output of FTM0 channel 5 PWM/OCMP modulating the carrier frequency, as per CARRIER_SELECT0 10172 */ 10173 #define SIM_SOPT8_FTM0OCH5SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM0OCH5SRC_SHIFT)) & SIM_SOPT8_FTM0OCH5SRC_MASK) 10174 #define SIM_SOPT8_FTM2OCH0SRC_MASK (0x400000U) 10175 #define SIM_SOPT8_FTM2OCH0SRC_SHIFT (22U) 10176 /*! FTM2OCH0SRC - FTM2 channel 0 output PWM/OCMP mode source select 10177 * 0b0..FTM2CH0 pin is the output of FTM2 channel 0 PWM/OCMP 10178 * 0b1..FTM2CH0 pin is the output of FTM2 channel 0 PWM/OCMP modulating the carrier frequency, as per CARRIER_SELECT0 10179 */ 10180 #define SIM_SOPT8_FTM2OCH0SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM2OCH0SRC_SHIFT)) & SIM_SOPT8_FTM2OCH0SRC_MASK) 10181 #define SIM_SOPT8_FTM2OCH1SRC_MASK (0x800000U) 10182 #define SIM_SOPT8_FTM2OCH1SRC_SHIFT (23U) 10183 /*! FTM2OCH1SRC - FTM2 channel 1 output PWM/OCMP mode source select 10184 * 0b0..FTM2CH1 pin is the output of FTM2 channel 1 PWM/OCMP 10185 * 0b1..FTM2CH1 pin is the output of FTM2 channel 1 PWM/OCMP modulating the carrier frequency, as per CARRIER_SELECT0 10186 */ 10187 #define SIM_SOPT8_FTM2OCH1SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM2OCH1SRC_SHIFT)) & SIM_SOPT8_FTM2OCH1SRC_MASK) 10188 /*! @} */ 10189 10190 /*! @name SOPT9 - System Options Register 9 */ 10191 /*! @{ */ 10192 #define SIM_SOPT9_CARRIER_SELECT1_MASK (0x300U) 10193 #define SIM_SOPT9_CARRIER_SELECT1_SHIFT (8U) 10194 /*! CARRIER_SELECT1 - Carrier frequency selection for FTM3/4 output channel 10195 * 0b00..FTM1_CH1 output provides the carrier signal for Timer Modulation mode 10196 * 0b01..LPTMR0 prescaler output provides the carrier signal for Timer Modulation mode 10197 * 0b10..FTM5_CH1 output provides the carrier signal for Timer Modulation mode 10198 * 0b11..Reserved 10199 */ 10200 #define SIM_SOPT9_CARRIER_SELECT1(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT9_CARRIER_SELECT1_SHIFT)) & SIM_SOPT9_CARRIER_SELECT1_MASK) 10201 #define SIM_SOPT9_FTM3OCH0SRC_MASK (0x10000U) 10202 #define SIM_SOPT9_FTM3OCH0SRC_SHIFT (16U) 10203 /*! FTM3OCH0SRC - FTM3 channel 0 output PWM/OCMP mode source select 10204 * 0b0..FTM3CH0 pin is the output of FTM3 channel 0 PWM/OCMP 10205 * 0b1..FTM3CH0 pin is the output of FTM3 channel 0 PWM/OCMP modulating the carrier frequency, as per CARRIER_SELECT1 10206 */ 10207 #define SIM_SOPT9_FTM3OCH0SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT9_FTM3OCH0SRC_SHIFT)) & SIM_SOPT9_FTM3OCH0SRC_MASK) 10208 #define SIM_SOPT9_FTM3OCH1SRC_MASK (0x20000U) 10209 #define SIM_SOPT9_FTM3OCH1SRC_SHIFT (17U) 10210 /*! FTM3OCH1SRC - FTM3 channel 1 output PWM/OCMP mode source select 10211 * 0b0..FTM3CH1 pin is the output of FTM3 channel 1 PWM/OCMP 10212 * 0b1..FTM3CH1 pin is the output of FTM3 channel 1 PWM/OCMP modulating the carrier frequency, as per CARRIER_SELECT1 10213 */ 10214 #define SIM_SOPT9_FTM3OCH1SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT9_FTM3OCH1SRC_SHIFT)) & SIM_SOPT9_FTM3OCH1SRC_MASK) 10215 #define SIM_SOPT9_FTM3OCH2SRC_MASK (0x40000U) 10216 #define SIM_SOPT9_FTM3OCH2SRC_SHIFT (18U) 10217 /*! FTM3OCH2SRC - FTM3 channel 2 output PWM/OCMP mode source select 10218 * 0b0..FTM3CH2 pin is the output of FTM3 channel 2 PWM/OCMP 10219 * 0b1..FTM3CH2 pin is the output of FTM3 channel 2 PWM/OCMP modulating the carrier frequency, as per CARRIER_SELECT1 10220 */ 10221 #define SIM_SOPT9_FTM3OCH2SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT9_FTM3OCH2SRC_SHIFT)) & SIM_SOPT9_FTM3OCH2SRC_MASK) 10222 #define SIM_SOPT9_FTM3OCH3SRC_MASK (0x80000U) 10223 #define SIM_SOPT9_FTM3OCH3SRC_SHIFT (19U) 10224 /*! FTM3OCH3SRC - FTM3 channel 3 output PWM/OCMP mode source select 10225 * 0b0..FTM3CH3 pin is the output of FTM3 channel 3 PWM/OCMP 10226 * 0b1..FTM3CH3 pin is the output of FTM3 channel 3 PWM/OCMP modulating the carrier frequency, as per CARRIER_SELECT1 10227 */ 10228 #define SIM_SOPT9_FTM3OCH3SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT9_FTM3OCH3SRC_SHIFT)) & SIM_SOPT9_FTM3OCH3SRC_MASK) 10229 #define SIM_SOPT9_FTM3OCH4SRC_MASK (0x100000U) 10230 #define SIM_SOPT9_FTM3OCH4SRC_SHIFT (20U) 10231 /*! FTM3OCH4SRC - FTM3 channel 4 output PWM/OCMP mode source select 10232 * 0b0..FTM3CH4 pin is the output of FTM3 channel 4 PWM/OCMP 10233 * 0b1..FTM3CH4 pin is the output of FTM3 channel 4 PWM/OCMP modulating the carrier frequency, as per CARRIER_SELECT1 10234 */ 10235 #define SIM_SOPT9_FTM3OCH4SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT9_FTM3OCH4SRC_SHIFT)) & SIM_SOPT9_FTM3OCH4SRC_MASK) 10236 #define SIM_SOPT9_FTM3OCH5SRC_MASK (0x200000U) 10237 #define SIM_SOPT9_FTM3OCH5SRC_SHIFT (21U) 10238 /*! FTM3OCH5SRC - FTM3 channel 5 output PWM/OCMP mode source select 10239 * 0b0..FTM3CH5 pin is the output of FTM3 channel 5 PWM/OCMP 10240 * 0b1..FTM3CH5 pin is the output of FTM3 channel 5 PWM/OCMP modulating the carrier frequency, as per CARRIER_SELECT1 10241 */ 10242 #define SIM_SOPT9_FTM3OCH5SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT9_FTM3OCH5SRC_SHIFT)) & SIM_SOPT9_FTM3OCH5SRC_MASK) 10243 #define SIM_SOPT9_FTM4OCH0SRC_MASK (0x400000U) 10244 #define SIM_SOPT9_FTM4OCH0SRC_SHIFT (22U) 10245 /*! FTM4OCH0SRC - FTM4 channel 0 output PWM/OCMP mode source select 10246 * 0b0..FTM4CH0 pin is the output of FTM4 channel 0 PWM/OCMP 10247 * 0b1..FTM4CH0 pin is the output of FTM4 channel 0 PWM/OCMP modulating the carrier frequency, as per CARRIER_SELECT1 10248 */ 10249 #define SIM_SOPT9_FTM4OCH0SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT9_FTM4OCH0SRC_SHIFT)) & SIM_SOPT9_FTM4OCH0SRC_MASK) 10250 #define SIM_SOPT9_FTM4OCH1SRC_MASK (0x800000U) 10251 #define SIM_SOPT9_FTM4OCH1SRC_SHIFT (23U) 10252 /*! FTM4OCH1SRC - FTM4 channel 1 output PWM/OCMP mode source select 10253 * 0b0..FTM4CH1 pin is the output of FTM4 channel 1 PWM/OCMP 10254 * 0b1..FTM4CH1 pin is the output of FTM4 channel 1 PWM/OCMP modulating the carrier frequency, as per CARRIER_SELECT1 10255 */ 10256 #define SIM_SOPT9_FTM4OCH1SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT9_FTM4OCH1SRC_SHIFT)) & SIM_SOPT9_FTM4OCH1SRC_MASK) 10257 /*! @} */ 10258 10259 /*! @name SDID - System Device Identification Register */ 10260 /*! @{ */ 10261 #define SIM_SDID_PINID_MASK (0xFU) 10262 #define SIM_SDID_PINID_SHIFT (0U) 10263 /*! PINID - Pincount identification 10264 * 0b0000..Reserved 10265 * 0b0001..Reserved 10266 * 0b0010..32-pin 10267 * 0b0011..Reserved 10268 * 0b0100..48-pin 10269 * 0b0101..64-pin 10270 * 0b0110..Reserved 10271 * 0b0111..Reserved 10272 * 0b1000..Reserved 10273 * 0b1001..Reserved 10274 * 0b1010..Reserved 10275 * 0b1011..Reserved 10276 * 0b1100..Reserved 10277 * 0b1101..Reserved 10278 * 0b1110..Reserved 10279 * 0b1111..Reserved 10280 */ 10281 #define SIM_SDID_PINID(x) (((uint32_t)(((uint32_t)(x)) << SIM_SDID_PINID_SHIFT)) & SIM_SDID_PINID_MASK) 10282 #define SIM_SDID_DIEID_MASK (0xF80U) 10283 #define SIM_SDID_DIEID_SHIFT (7U) 10284 #define SIM_SDID_DIEID(x) (((uint32_t)(((uint32_t)(x)) << SIM_SDID_DIEID_SHIFT)) & SIM_SDID_DIEID_MASK) 10285 #define SIM_SDID_REVID_MASK (0xF000U) 10286 #define SIM_SDID_REVID_SHIFT (12U) 10287 #define SIM_SDID_REVID(x) (((uint32_t)(((uint32_t)(x)) << SIM_SDID_REVID_SHIFT)) & SIM_SDID_REVID_MASK) 10288 #define SIM_SDID_SRAMSIZE_MASK (0xF0000U) 10289 #define SIM_SDID_SRAMSIZE_SHIFT (16U) 10290 /*! SRAMSIZE 10291 * 0b0000..Reserved 10292 * 0b0001..Reserved 10293 * 0b0010..Reserved 10294 * 0b0011..Reserved 10295 * 0b0100..Reserved 10296 * 0b0101..16 KB 10297 * 0b0110..Reserved 10298 * 0b0111..Reserved 10299 */ 10300 #define SIM_SDID_SRAMSIZE(x) (((uint32_t)(((uint32_t)(x)) << SIM_SDID_SRAMSIZE_SHIFT)) & SIM_SDID_SRAMSIZE_MASK) 10301 #define SIM_SDID_SERIERID_MASK (0xF00000U) 10302 #define SIM_SDID_SERIERID_SHIFT (20U) 10303 /*! SERIERID - Series ID 10304 * 0b0110..V-family - Motor control 10305 */ 10306 #define SIM_SDID_SERIERID(x) (((uint32_t)(((uint32_t)(x)) << SIM_SDID_SERIERID_SHIFT)) & SIM_SDID_SERIERID_MASK) 10307 #define SIM_SDID_SUBFAMID_MASK (0xF000000U) 10308 #define SIM_SDID_SUBFAMID_SHIFT (24U) 10309 /*! SUBFAMID - V Sub-family ID 10310 * 0b0000..MKV10xxxx 10311 * 0b0001..MKV11xxxx 10312 */ 10313 #define SIM_SDID_SUBFAMID(x) (((uint32_t)(((uint32_t)(x)) << SIM_SDID_SUBFAMID_SHIFT)) & SIM_SDID_SUBFAMID_MASK) 10314 #define SIM_SDID_FAMID_MASK (0xF0000000U) 10315 #define SIM_SDID_FAMID_SHIFT (28U) 10316 /*! FAMID - V-Family ID 10317 * 0b0001..MKV1xZx 10318 */ 10319 #define SIM_SDID_FAMID(x) (((uint32_t)(((uint32_t)(x)) << SIM_SDID_FAMID_SHIFT)) & SIM_SDID_FAMID_MASK) 10320 /*! @} */ 10321 10322 /*! @name SCGC4 - System Clock Gating Control Register 4 */ 10323 /*! @{ */ 10324 #define SIM_SCGC4_EWM_MASK (0x2U) 10325 #define SIM_SCGC4_EWM_SHIFT (1U) 10326 /*! EWM - EWM Clock Gate Control 10327 * 0b0..Clock disabled 10328 * 0b1..Clock enabled 10329 */ 10330 #define SIM_SCGC4_EWM(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_EWM_SHIFT)) & SIM_SCGC4_EWM_MASK) 10331 #define SIM_SCGC4_I2C0_MASK (0x40U) 10332 #define SIM_SCGC4_I2C0_SHIFT (6U) 10333 /*! I2C0 - I2C0 Clock Gate Control 10334 * 0b0..Clock disabled 10335 * 0b1..Clock enabled 10336 */ 10337 #define SIM_SCGC4_I2C0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_I2C0_SHIFT)) & SIM_SCGC4_I2C0_MASK) 10338 #define SIM_SCGC4_UART0_MASK (0x400U) 10339 #define SIM_SCGC4_UART0_SHIFT (10U) 10340 /*! UART0 - UART0 Clock Gate Control 10341 * 0b0..Clock disabled 10342 * 0b1..Clock enabled 10343 */ 10344 #define SIM_SCGC4_UART0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_UART0_SHIFT)) & SIM_SCGC4_UART0_MASK) 10345 #define SIM_SCGC4_UART1_MASK (0x800U) 10346 #define SIM_SCGC4_UART1_SHIFT (11U) 10347 /*! UART1 - UART1 Clock Gate Control 10348 * 0b0..Clock disabled 10349 * 0b1..Clock enabled 10350 */ 10351 #define SIM_SCGC4_UART1(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_UART1_SHIFT)) & SIM_SCGC4_UART1_MASK) 10352 #define SIM_SCGC4_CMP_MASK (0x80000U) 10353 #define SIM_SCGC4_CMP_SHIFT (19U) 10354 /*! CMP - Comparator Clock Gate Control 10355 * 0b0..Clock disabled 10356 * 0b1..Clock enabled 10357 */ 10358 #define SIM_SCGC4_CMP(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_CMP_SHIFT)) & SIM_SCGC4_CMP_MASK) 10359 /*! @} */ 10360 10361 /*! @name SCGC5 - System Clock Gating Control Register 5 */ 10362 /*! @{ */ 10363 #define SIM_SCGC5_LPTMR_MASK (0x1U) 10364 #define SIM_SCGC5_LPTMR_SHIFT (0U) 10365 /*! LPTMR - Low Power Timer Clock Gate Control 10366 * 0b0..Access disabled 10367 * 0b1..Access enabled 10368 */ 10369 #define SIM_SCGC5_LPTMR(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_LPTMR_SHIFT)) & SIM_SCGC5_LPTMR_MASK) 10370 #define SIM_SCGC5_PORTA_MASK (0x200U) 10371 #define SIM_SCGC5_PORTA_SHIFT (9U) 10372 /*! PORTA - Port A Clock Gate Control 10373 * 0b0..Clock disabled 10374 * 0b1..Clock enabled 10375 */ 10376 #define SIM_SCGC5_PORTA(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_PORTA_SHIFT)) & SIM_SCGC5_PORTA_MASK) 10377 #define SIM_SCGC5_PORTB_MASK (0x400U) 10378 #define SIM_SCGC5_PORTB_SHIFT (10U) 10379 /*! PORTB - Port B Clock Gate Control 10380 * 0b0..Clock disabled 10381 * 0b1..Clock enabled 10382 */ 10383 #define SIM_SCGC5_PORTB(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_PORTB_SHIFT)) & SIM_SCGC5_PORTB_MASK) 10384 #define SIM_SCGC5_PORTC_MASK (0x800U) 10385 #define SIM_SCGC5_PORTC_SHIFT (11U) 10386 /*! PORTC - Port C Clock Gate Control 10387 * 0b0..Clock disabled 10388 * 0b1..Clock enabled 10389 */ 10390 #define SIM_SCGC5_PORTC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_PORTC_SHIFT)) & SIM_SCGC5_PORTC_MASK) 10391 #define SIM_SCGC5_PORTD_MASK (0x1000U) 10392 #define SIM_SCGC5_PORTD_SHIFT (12U) 10393 /*! PORTD - Port D Clock Gate Control 10394 * 0b0..Clock disabled 10395 * 0b1..Clock enabled 10396 */ 10397 #define SIM_SCGC5_PORTD(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_PORTD_SHIFT)) & SIM_SCGC5_PORTD_MASK) 10398 #define SIM_SCGC5_PORTE_MASK (0x2000U) 10399 #define SIM_SCGC5_PORTE_SHIFT (13U) 10400 /*! PORTE - Port E Clock Gate Control 10401 * 0b0..Clock disabled 10402 * 0b1..Clock enabled 10403 */ 10404 #define SIM_SCGC5_PORTE(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_PORTE_SHIFT)) & SIM_SCGC5_PORTE_MASK) 10405 /*! @} */ 10406 10407 /*! @name SCGC6 - System Clock Gating Control Register 6 */ 10408 /*! @{ */ 10409 #define SIM_SCGC6_FTF_MASK (0x1U) 10410 #define SIM_SCGC6_FTF_SHIFT (0U) 10411 /*! FTF - Flash Memory Clock Gate Control 10412 * 0b0..Clock disabled 10413 * 0b1..Clock enabled 10414 */ 10415 #define SIM_SCGC6_FTF(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_FTF_SHIFT)) & SIM_SCGC6_FTF_MASK) 10416 #define SIM_SCGC6_DMAMUX_MASK (0x2U) 10417 #define SIM_SCGC6_DMAMUX_SHIFT (1U) 10418 /*! DMAMUX - DMA Mux Clock Gate Control 10419 * 0b0..Clock disabled 10420 * 0b1..Clock enabled 10421 */ 10422 #define SIM_SCGC6_DMAMUX(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_DMAMUX_SHIFT)) & SIM_SCGC6_DMAMUX_MASK) 10423 #define SIM_SCGC6_FLEXCAN0_MASK (0x10U) 10424 #define SIM_SCGC6_FLEXCAN0_SHIFT (4U) 10425 /*! FLEXCAN0 - FLEXCAN0 Clock Gate Control 10426 * 0b0..Clock disabled 10427 * 0b1..Clock enabled 10428 */ 10429 #define SIM_SCGC6_FLEXCAN0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_FLEXCAN0_SHIFT)) & SIM_SCGC6_FLEXCAN0_MASK) 10430 #define SIM_SCGC6_FTM3_MASK (0x40U) 10431 #define SIM_SCGC6_FTM3_SHIFT (6U) 10432 /*! FTM3 - FTM3 Clock Gate Control 10433 * 0b0..Clock disabled 10434 * 0b1..Clock enabled 10435 */ 10436 #define SIM_SCGC6_FTM3(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_FTM3_SHIFT)) & SIM_SCGC6_FTM3_MASK) 10437 #define SIM_SCGC6_FTM4_MASK (0x80U) 10438 #define SIM_SCGC6_FTM4_SHIFT (7U) 10439 /*! FTM4 - FTM4 Clock Gate Control 10440 * 0b0..Clock disabled 10441 * 0b1..Clock enabled 10442 */ 10443 #define SIM_SCGC6_FTM4(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_FTM4_SHIFT)) & SIM_SCGC6_FTM4_MASK) 10444 #define SIM_SCGC6_FTM5_MASK (0x100U) 10445 #define SIM_SCGC6_FTM5_SHIFT (8U) 10446 /*! FTM5 - FTM5 Clock Gate Control 10447 * 0b0..Clock disabled 10448 * 0b1..Clock enabled 10449 */ 10450 #define SIM_SCGC6_FTM5(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_FTM5_SHIFT)) & SIM_SCGC6_FTM5_MASK) 10451 #define SIM_SCGC6_SPI0_MASK (0x1000U) 10452 #define SIM_SCGC6_SPI0_SHIFT (12U) 10453 /*! SPI0 - SPI0 Clock Gate Control 10454 * 0b0..Clock disabled 10455 * 0b1..Clock enabled 10456 */ 10457 #define SIM_SCGC6_SPI0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_SPI0_SHIFT)) & SIM_SCGC6_SPI0_MASK) 10458 #define SIM_SCGC6_PDB1_MASK (0x20000U) 10459 #define SIM_SCGC6_PDB1_SHIFT (17U) 10460 /*! PDB1 - PDB1 Clock Gate Control 10461 * 0b0..Clock disabled 10462 * 0b1..Clock enabled 10463 */ 10464 #define SIM_SCGC6_PDB1(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_PDB1_SHIFT)) & SIM_SCGC6_PDB1_MASK) 10465 #define SIM_SCGC6_CRC_MASK (0x40000U) 10466 #define SIM_SCGC6_CRC_SHIFT (18U) 10467 /*! CRC - CRC Clock Gate Control 10468 * 0b0..Clock disabled 10469 * 0b1..Clock enabled 10470 */ 10471 #define SIM_SCGC6_CRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_CRC_SHIFT)) & SIM_SCGC6_CRC_MASK) 10472 #define SIM_SCGC6_PDB0_MASK (0x400000U) 10473 #define SIM_SCGC6_PDB0_SHIFT (22U) 10474 /*! PDB0 - PDB0 Clock Gate Control 10475 * 0b0..Clock disabled 10476 * 0b1..Clock enabled 10477 */ 10478 #define SIM_SCGC6_PDB0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_PDB0_SHIFT)) & SIM_SCGC6_PDB0_MASK) 10479 #define SIM_SCGC6_FTM0_MASK (0x1000000U) 10480 #define SIM_SCGC6_FTM0_SHIFT (24U) 10481 /*! FTM0 - FTM0 Clock Gate Control 10482 * 0b0..Clock disabled 10483 * 0b1..Clock enabled 10484 */ 10485 #define SIM_SCGC6_FTM0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_FTM0_SHIFT)) & SIM_SCGC6_FTM0_MASK) 10486 #define SIM_SCGC6_FTM1_MASK (0x2000000U) 10487 #define SIM_SCGC6_FTM1_SHIFT (25U) 10488 /*! FTM1 - FTM1 Clock Gate Control 10489 * 0b0..Clock disabled 10490 * 0b1..Clock enabled 10491 */ 10492 #define SIM_SCGC6_FTM1(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_FTM1_SHIFT)) & SIM_SCGC6_FTM1_MASK) 10493 #define SIM_SCGC6_FTM2_MASK (0x4000000U) 10494 #define SIM_SCGC6_FTM2_SHIFT (26U) 10495 /*! FTM2 - FTM2 Clock Gate Control 10496 * 0b0..Clock disabled 10497 * 0b1..Clock enabled 10498 */ 10499 #define SIM_SCGC6_FTM2(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_FTM2_SHIFT)) & SIM_SCGC6_FTM2_MASK) 10500 #define SIM_SCGC6_ADC0_MASK (0x8000000U) 10501 #define SIM_SCGC6_ADC0_SHIFT (27U) 10502 /*! ADC0 - ADC0 Clock Gate Control 10503 * 0b0..Clock disabled 10504 * 0b1..Clock enabled 10505 */ 10506 #define SIM_SCGC6_ADC0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_ADC0_SHIFT)) & SIM_SCGC6_ADC0_MASK) 10507 #define SIM_SCGC6_ADC1_MASK (0x10000000U) 10508 #define SIM_SCGC6_ADC1_SHIFT (28U) 10509 /*! ADC1 - ADC1 Clock Gate Control 10510 * 0b0..Clock disabled 10511 * 0b1..Clock enabled 10512 */ 10513 #define SIM_SCGC6_ADC1(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_ADC1_SHIFT)) & SIM_SCGC6_ADC1_MASK) 10514 #define SIM_SCGC6_DAC0_MASK (0x80000000U) 10515 #define SIM_SCGC6_DAC0_SHIFT (31U) 10516 /*! DAC0 - DAC0 Clock Gate Control 10517 * 0b0..Clock disabled 10518 * 0b1..Clock enabled 10519 */ 10520 #define SIM_SCGC6_DAC0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_DAC0_SHIFT)) & SIM_SCGC6_DAC0_MASK) 10521 /*! @} */ 10522 10523 /*! @name SCGC7 - System Clock Gating Control Register 7 */ 10524 /*! @{ */ 10525 #define SIM_SCGC7_DMA_MASK (0x100U) 10526 #define SIM_SCGC7_DMA_SHIFT (8U) 10527 /*! DMA - DMA Clock Gate Control 10528 * 0b0..Clock disabled 10529 * 0b1..Clock enabled 10530 */ 10531 #define SIM_SCGC7_DMA(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC7_DMA_SHIFT)) & SIM_SCGC7_DMA_MASK) 10532 /*! @} */ 10533 10534 /*! @name CLKDIV1 - System Clock Divider Register 1 */ 10535 /*! @{ */ 10536 #define SIM_CLKDIV1_OUTDIV5_MASK (0x7000U) 10537 #define SIM_CLKDIV1_OUTDIV5_SHIFT (12U) 10538 /*! OUTDIV5 - Clock 5 Output Divider Value 10539 * 0b000..Divide-by-1 10540 * 0b001..Divide-by-2 10541 * 0b010..Divide-by-3 10542 * 0b011..Divide-by-4 10543 * 0b100..Divide-by-5 10544 * 0b101..Divide-by-6 10545 * 0b110..Divide-by-7 10546 * 0b111..Divide-by-8 10547 */ 10548 #define SIM_CLKDIV1_OUTDIV5(x) (((uint32_t)(((uint32_t)(x)) << SIM_CLKDIV1_OUTDIV5_SHIFT)) & SIM_CLKDIV1_OUTDIV5_MASK) 10549 #define SIM_CLKDIV1_OUTDIV5EN_MASK (0x8000U) 10550 #define SIM_CLKDIV1_OUTDIV5EN_SHIFT (15U) 10551 /*! OUTDIV5EN - OUTDIV5 Divider Control 10552 * 0b0..OUTDIV5 disabled 10553 * 0b1..OUTDIV5 enabled 10554 */ 10555 #define SIM_CLKDIV1_OUTDIV5EN(x) (((uint32_t)(((uint32_t)(x)) << SIM_CLKDIV1_OUTDIV5EN_SHIFT)) & SIM_CLKDIV1_OUTDIV5EN_MASK) 10556 #define SIM_CLKDIV1_OUTDIV4_MASK (0x70000U) 10557 #define SIM_CLKDIV1_OUTDIV4_SHIFT (16U) 10558 /*! OUTDIV4 - Clock 4 Output Divider Value 10559 * 0b000..Divide-by-1. 10560 * 0b001..Divide-by-2. 10561 * 0b010..Divide-by-3. 10562 * 0b011..Divide-by-4. 10563 * 0b100..Divide-by-5. 10564 * 0b101..Divide-by-6. 10565 * 0b110..Divide-by-7. 10566 * 0b111..Divide-by-8. 10567 */ 10568 #define SIM_CLKDIV1_OUTDIV4(x) (((uint32_t)(((uint32_t)(x)) << SIM_CLKDIV1_OUTDIV4_SHIFT)) & SIM_CLKDIV1_OUTDIV4_MASK) 10569 #define SIM_CLKDIV1_OUTDIV1_MASK (0xF0000000U) 10570 #define SIM_CLKDIV1_OUTDIV1_SHIFT (28U) 10571 /*! OUTDIV1 - Clock 1 Output Divider Value 10572 * 0b0000..Divide-by-1. 10573 * 0b0001..Divide-by-2. 10574 * 0b0010..Divide-by-3. 10575 * 0b0011..Divide-by-4. 10576 * 0b0100..Divide-by-5. 10577 * 0b0101..Divide-by-6. 10578 * 0b0110..Divide-by-7. 10579 * 0b0111..Divide-by-8. 10580 * 0b1000..Divide-by-9. 10581 * 0b1001..Divide-by-10. 10582 * 0b1010..Divide-by-11. 10583 * 0b1011..Divide-by-12. 10584 * 0b1100..Divide-by-13. 10585 * 0b1101..Divide-by-14. 10586 * 0b1110..Divide-by-15. 10587 * 0b1111..Divide-by-16. 10588 */ 10589 #define SIM_CLKDIV1_OUTDIV1(x) (((uint32_t)(((uint32_t)(x)) << SIM_CLKDIV1_OUTDIV1_SHIFT)) & SIM_CLKDIV1_OUTDIV1_MASK) 10590 /*! @} */ 10591 10592 /*! @name FCFG1 - Flash Configuration Register 1 */ 10593 /*! @{ */ 10594 #define SIM_FCFG1_FLASHDIS_MASK (0x1U) 10595 #define SIM_FCFG1_FLASHDIS_SHIFT (0U) 10596 /*! FLASHDIS - Flash Disable 10597 * 0b0..Flash is enabled 10598 * 0b1..Flash is disabled 10599 */ 10600 #define SIM_FCFG1_FLASHDIS(x) (((uint32_t)(((uint32_t)(x)) << SIM_FCFG1_FLASHDIS_SHIFT)) & SIM_FCFG1_FLASHDIS_MASK) 10601 #define SIM_FCFG1_FLASHDOZE_MASK (0x2U) 10602 #define SIM_FCFG1_FLASHDOZE_SHIFT (1U) 10603 /*! FLASHDOZE - Flash Doze 10604 * 0b0..Flash remains enabled during Doze mode 10605 * 0b1..Flash is disabled for the duration of Doze mode 10606 */ 10607 #define SIM_FCFG1_FLASHDOZE(x) (((uint32_t)(((uint32_t)(x)) << SIM_FCFG1_FLASHDOZE_SHIFT)) & SIM_FCFG1_FLASHDOZE_MASK) 10608 #define SIM_FCFG1_PFSIZE_MASK (0xF000000U) 10609 #define SIM_FCFG1_PFSIZE_SHIFT (24U) 10610 /*! PFSIZE - Program Flash Size 10611 * 0b0000..8 KB of program flash memory, 0.25 KB protection region 10612 * 0b0001..16 KB of program flash memory, 0.5 KB protection region 10613 * 0b0011..32 KB of program flash memory, 1 KB protection region 10614 * 0b0101..64 KB of program flash memory, 2 KB protection region 10615 * 0b0111..128 KB of program flash memory, 4 KB protection region 10616 * 0b1001..256 KB of program flash memory, 4 KB protection region 10617 * 0b1111..32 KB of program flash memory, 1 KB protection region 10618 */ 10619 #define SIM_FCFG1_PFSIZE(x) (((uint32_t)(((uint32_t)(x)) << SIM_FCFG1_PFSIZE_SHIFT)) & SIM_FCFG1_PFSIZE_MASK) 10620 /*! @} */ 10621 10622 /*! @name FCFG2 - Flash Configuration Register 2 */ 10623 /*! @{ */ 10624 #define SIM_FCFG2_MAXADDR_MASK (0x7F000000U) 10625 #define SIM_FCFG2_MAXADDR_SHIFT (24U) 10626 #define SIM_FCFG2_MAXADDR(x) (((uint32_t)(((uint32_t)(x)) << SIM_FCFG2_MAXADDR_SHIFT)) & SIM_FCFG2_MAXADDR_MASK) 10627 /*! @} */ 10628 10629 /*! @name UIDMH - Unique Identification Register Mid-High */ 10630 /*! @{ */ 10631 #define SIM_UIDMH_UID_MASK (0xFFFFU) 10632 #define SIM_UIDMH_UID_SHIFT (0U) 10633 #define SIM_UIDMH_UID(x) (((uint32_t)(((uint32_t)(x)) << SIM_UIDMH_UID_SHIFT)) & SIM_UIDMH_UID_MASK) 10634 /*! @} */ 10635 10636 /*! @name UIDML - Unique Identification Register Mid Low */ 10637 /*! @{ */ 10638 #define SIM_UIDML_UID_MASK (0xFFFFFFFFU) 10639 #define SIM_UIDML_UID_SHIFT (0U) 10640 #define SIM_UIDML_UID(x) (((uint32_t)(((uint32_t)(x)) << SIM_UIDML_UID_SHIFT)) & SIM_UIDML_UID_MASK) 10641 /*! @} */ 10642 10643 /*! @name UIDL - Unique Identification Register Low */ 10644 /*! @{ */ 10645 #define SIM_UIDL_UID_MASK (0xFFFFFFFFU) 10646 #define SIM_UIDL_UID_SHIFT (0U) 10647 #define SIM_UIDL_UID(x) (((uint32_t)(((uint32_t)(x)) << SIM_UIDL_UID_SHIFT)) & SIM_UIDL_UID_MASK) 10648 /*! @} */ 10649 10650 /*! @name WDOGC - WDOG Control Register */ 10651 /*! @{ */ 10652 #define SIM_WDOGC_WDOGCLKS_MASK (0x2U) 10653 #define SIM_WDOGC_WDOGCLKS_SHIFT (1U) 10654 /*! WDOGCLKS - WDOG Clock Select 10655 * 0b0..Internal 1 kHz clock is source to WDOG 10656 * 0b1..MCGIRCLK is source to WDOG 10657 */ 10658 #define SIM_WDOGC_WDOGCLKS(x) (((uint32_t)(((uint32_t)(x)) << SIM_WDOGC_WDOGCLKS_SHIFT)) & SIM_WDOGC_WDOGCLKS_MASK) 10659 /*! @} */ 10660 10661 10662 /*! 10663 * @} 10664 */ /* end of group SIM_Register_Masks */ 10665 10666 10667 /* SIM - Peripheral instance base addresses */ 10668 /** Peripheral SIM base address */ 10669 #define SIM_BASE (0x40047000u) 10670 /** Peripheral SIM base pointer */ 10671 #define SIM ((SIM_Type *)SIM_BASE) 10672 /** Array initializer of SIM peripheral base addresses */ 10673 #define SIM_BASE_ADDRS { SIM_BASE } 10674 /** Array initializer of SIM peripheral base pointers */ 10675 #define SIM_BASE_PTRS { SIM } 10676 10677 /*! 10678 * @} 10679 */ /* end of group SIM_Peripheral_Access_Layer */ 10680 10681 10682 /* ---------------------------------------------------------------------------- 10683 -- SMC Peripheral Access Layer 10684 ---------------------------------------------------------------------------- */ 10685 10686 /*! 10687 * @addtogroup SMC_Peripheral_Access_Layer SMC Peripheral Access Layer 10688 * @{ 10689 */ 10690 10691 /** SMC - Register Layout Typedef */ 10692 typedef struct { 10693 __IO uint8_t PMPROT; /**< Power Mode Protection register, offset: 0x0 */ 10694 __IO uint8_t PMCTRL; /**< Power Mode Control register, offset: 0x1 */ 10695 __IO uint8_t STOPCTRL; /**< Stop Control Register, offset: 0x2 */ 10696 __I uint8_t PMSTAT; /**< Power Mode Status register, offset: 0x3 */ 10697 } SMC_Type; 10698 10699 /* ---------------------------------------------------------------------------- 10700 -- SMC Register Masks 10701 ---------------------------------------------------------------------------- */ 10702 10703 /*! 10704 * @addtogroup SMC_Register_Masks SMC Register Masks 10705 * @{ 10706 */ 10707 10708 /*! @name PMPROT - Power Mode Protection register */ 10709 /*! @{ */ 10710 #define SMC_PMPROT_AVLLS_MASK (0x2U) 10711 #define SMC_PMPROT_AVLLS_SHIFT (1U) 10712 /*! AVLLS - Allow Very-Low-Leakage Stop Mode 10713 * 0b0..Any VLLSx mode is not allowed 10714 * 0b1..Any VLLSx mode is allowed 10715 */ 10716 #define SMC_PMPROT_AVLLS(x) (((uint8_t)(((uint8_t)(x)) << SMC_PMPROT_AVLLS_SHIFT)) & SMC_PMPROT_AVLLS_MASK) 10717 #define SMC_PMPROT_AVLP_MASK (0x20U) 10718 #define SMC_PMPROT_AVLP_SHIFT (5U) 10719 /*! AVLP - Allow Very-Low-Power Modes 10720 * 0b0..VLPR, VLPW, and VLPS are not allowed. 10721 * 0b1..VLPR, VLPW, and VLPS are allowed. 10722 */ 10723 #define SMC_PMPROT_AVLP(x) (((uint8_t)(((uint8_t)(x)) << SMC_PMPROT_AVLP_SHIFT)) & SMC_PMPROT_AVLP_MASK) 10724 /*! @} */ 10725 10726 /*! @name PMCTRL - Power Mode Control register */ 10727 /*! @{ */ 10728 #define SMC_PMCTRL_STOPM_MASK (0x7U) 10729 #define SMC_PMCTRL_STOPM_SHIFT (0U) 10730 /*! STOPM - Stop Mode Control 10731 * 0b000..Normal Stop (STOP) 10732 * 0b001..Reserved 10733 * 0b010..Very-Low-Power Stop (VLPS) 10734 * 0b011..Reserved 10735 * 0b100..Very-Low-Leakage Stop (VLLSx) 10736 * 0b101..Reserved 10737 * 0b110..Reseved 10738 * 0b111..Reserved 10739 */ 10740 #define SMC_PMCTRL_STOPM(x) (((uint8_t)(((uint8_t)(x)) << SMC_PMCTRL_STOPM_SHIFT)) & SMC_PMCTRL_STOPM_MASK) 10741 #define SMC_PMCTRL_STOPA_MASK (0x8U) 10742 #define SMC_PMCTRL_STOPA_SHIFT (3U) 10743 /*! STOPA - Stop Aborted 10744 * 0b0..The previous stop mode entry was successsful. 10745 * 0b1..The previous stop mode entry was aborted. 10746 */ 10747 #define SMC_PMCTRL_STOPA(x) (((uint8_t)(((uint8_t)(x)) << SMC_PMCTRL_STOPA_SHIFT)) & SMC_PMCTRL_STOPA_MASK) 10748 #define SMC_PMCTRL_RUNM_MASK (0x60U) 10749 #define SMC_PMCTRL_RUNM_SHIFT (5U) 10750 /*! RUNM - Run Mode Control 10751 * 0b00..Normal Run mode (RUN) 10752 * 0b01..Reserved 10753 * 0b10..Very-Low-Power Run mode (VLPR) 10754 * 0b11..Reserved 10755 */ 10756 #define SMC_PMCTRL_RUNM(x) (((uint8_t)(((uint8_t)(x)) << SMC_PMCTRL_RUNM_SHIFT)) & SMC_PMCTRL_RUNM_MASK) 10757 /*! @} */ 10758 10759 /*! @name STOPCTRL - Stop Control Register */ 10760 /*! @{ */ 10761 #define SMC_STOPCTRL_VLLSM_MASK (0x7U) 10762 #define SMC_STOPCTRL_VLLSM_SHIFT (0U) 10763 /*! VLLSM - VLLS Mode Control 10764 * 0b000..VLLS0 10765 * 0b001..VLLS1 10766 * 0b010..Reserved 10767 * 0b011..VLLS3 10768 * 0b100..Reserved 10769 * 0b101..Reserved 10770 * 0b110..Reserved 10771 * 0b111..Reserved 10772 */ 10773 #define SMC_STOPCTRL_VLLSM(x) (((uint8_t)(((uint8_t)(x)) << SMC_STOPCTRL_VLLSM_SHIFT)) & SMC_STOPCTRL_VLLSM_MASK) 10774 #define SMC_STOPCTRL_PORPO_MASK (0x20U) 10775 #define SMC_STOPCTRL_PORPO_SHIFT (5U) 10776 /*! PORPO - POR Power Option 10777 * 0b0..POR detect circuit is enabled in VLLS0 10778 * 0b1..POR detect circuit is disabled in VLLS0 10779 */ 10780 #define SMC_STOPCTRL_PORPO(x) (((uint8_t)(((uint8_t)(x)) << SMC_STOPCTRL_PORPO_SHIFT)) & SMC_STOPCTRL_PORPO_MASK) 10781 #define SMC_STOPCTRL_PSTOPO_MASK (0xC0U) 10782 #define SMC_STOPCTRL_PSTOPO_SHIFT (6U) 10783 /*! PSTOPO - Partial Stop Option 10784 * 0b00..STOP - Normal Stop mode 10785 * 0b01..PSTOP1 - Partial Stop with both system and bus clocks disabled 10786 * 0b10..PSTOP2 - Partial Stop with system clock disabled and bus clock enabled 10787 * 0b11..Reserved 10788 */ 10789 #define SMC_STOPCTRL_PSTOPO(x) (((uint8_t)(((uint8_t)(x)) << SMC_STOPCTRL_PSTOPO_SHIFT)) & SMC_STOPCTRL_PSTOPO_MASK) 10790 /*! @} */ 10791 10792 /*! @name PMSTAT - Power Mode Status register */ 10793 /*! @{ */ 10794 #define SMC_PMSTAT_PMSTAT_MASK (0xFFU) 10795 #define SMC_PMSTAT_PMSTAT_SHIFT (0U) 10796 #define SMC_PMSTAT_PMSTAT(x) (((uint8_t)(((uint8_t)(x)) << SMC_PMSTAT_PMSTAT_SHIFT)) & SMC_PMSTAT_PMSTAT_MASK) 10797 /*! @} */ 10798 10799 10800 /*! 10801 * @} 10802 */ /* end of group SMC_Register_Masks */ 10803 10804 10805 /* SMC - Peripheral instance base addresses */ 10806 /** Peripheral SMC base address */ 10807 #define SMC_BASE (0x4007E000u) 10808 /** Peripheral SMC base pointer */ 10809 #define SMC ((SMC_Type *)SMC_BASE) 10810 /** Array initializer of SMC peripheral base addresses */ 10811 #define SMC_BASE_ADDRS { SMC_BASE } 10812 /** Array initializer of SMC peripheral base pointers */ 10813 #define SMC_BASE_PTRS { SMC } 10814 10815 /*! 10816 * @} 10817 */ /* end of group SMC_Peripheral_Access_Layer */ 10818 10819 10820 /* ---------------------------------------------------------------------------- 10821 -- SPI Peripheral Access Layer 10822 ---------------------------------------------------------------------------- */ 10823 10824 /*! 10825 * @addtogroup SPI_Peripheral_Access_Layer SPI Peripheral Access Layer 10826 * @{ 10827 */ 10828 10829 /** SPI - Register Layout Typedef */ 10830 typedef struct { 10831 __IO uint32_t MCR; /**< Module Configuration Register, offset: 0x0 */ 10832 uint8_t RESERVED_0[4]; 10833 __IO uint32_t TCR; /**< Transfer Count Register, offset: 0x8 */ 10834 union { /* offset: 0xC */ 10835 __IO uint32_t CTAR[2]; /**< Clock and Transfer Attributes Register (In Master Mode), array offset: 0xC, array step: 0x4 */ 10836 __IO uint32_t CTAR_SLAVE[1]; /**< Clock and Transfer Attributes Register (In Slave Mode), array offset: 0xC, array step: 0x4 */ 10837 }; 10838 uint8_t RESERVED_1[24]; 10839 __IO uint32_t SR; /**< Status Register, offset: 0x2C */ 10840 __IO uint32_t RSER; /**< DMA/Interrupt Request Select and Enable Register, offset: 0x30 */ 10841 union { /* offset: 0x34 */ 10842 __IO uint32_t PUSHR; /**< PUSH TX FIFO Register In Master Mode, offset: 0x34 */ 10843 __IO uint32_t PUSHR_SLAVE; /**< PUSH TX FIFO Register In Slave Mode, offset: 0x34 */ 10844 }; 10845 __I uint32_t POPR; /**< POP RX FIFO Register, offset: 0x38 */ 10846 __I uint32_t TXFR0; /**< Transmit FIFO Registers, offset: 0x3C */ 10847 __I uint32_t TXFR1; /**< Transmit FIFO Registers, offset: 0x40 */ 10848 __I uint32_t TXFR2; /**< Transmit FIFO Registers, offset: 0x44 */ 10849 __I uint32_t TXFR3; /**< Transmit FIFO Registers, offset: 0x48 */ 10850 uint8_t RESERVED_2[48]; 10851 __I uint32_t RXFR0; /**< Receive FIFO Registers, offset: 0x7C */ 10852 __I uint32_t RXFR1; /**< Receive FIFO Registers, offset: 0x80 */ 10853 __I uint32_t RXFR2; /**< Receive FIFO Registers, offset: 0x84 */ 10854 __I uint32_t RXFR3; /**< Receive FIFO Registers, offset: 0x88 */ 10855 uint8_t RESERVED_3[176]; 10856 __I uint32_t SREX; /**< Status Register Extended, offset: 0x13C */ 10857 } SPI_Type; 10858 10859 /* ---------------------------------------------------------------------------- 10860 -- SPI Register Masks 10861 ---------------------------------------------------------------------------- */ 10862 10863 /*! 10864 * @addtogroup SPI_Register_Masks SPI Register Masks 10865 * @{ 10866 */ 10867 10868 /*! @name MCR - Module Configuration Register */ 10869 /*! @{ */ 10870 #define SPI_MCR_HALT_MASK (0x1U) 10871 #define SPI_MCR_HALT_SHIFT (0U) 10872 /*! HALT - Halt 10873 * 0b0..Start transfers. 10874 * 0b1..Stop transfers. 10875 */ 10876 #define SPI_MCR_HALT(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_HALT_SHIFT)) & SPI_MCR_HALT_MASK) 10877 #define SPI_MCR_SMPL_PT_MASK (0x300U) 10878 #define SPI_MCR_SMPL_PT_SHIFT (8U) 10879 /*! SMPL_PT - Sample Point 10880 * 0b00..0 protocol clock cycles between SCK edge and SIN sample 10881 * 0b01..1 protocol clock cycle between SCK edge and SIN sample 10882 * 0b10..2 protocol clock cycles between SCK edge and SIN sample 10883 * 0b11..Reserved 10884 */ 10885 #define SPI_MCR_SMPL_PT(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_SMPL_PT_SHIFT)) & SPI_MCR_SMPL_PT_MASK) 10886 #define SPI_MCR_CLR_RXF_MASK (0x400U) 10887 #define SPI_MCR_CLR_RXF_SHIFT (10U) 10888 /*! CLR_RXF - CLR_RXF 10889 * 0b0..Do not clear the RX FIFO counter. 10890 * 0b1..Clear the RX FIFO counter. 10891 */ 10892 #define SPI_MCR_CLR_RXF(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_CLR_RXF_SHIFT)) & SPI_MCR_CLR_RXF_MASK) 10893 #define SPI_MCR_CLR_TXF_MASK (0x800U) 10894 #define SPI_MCR_CLR_TXF_SHIFT (11U) 10895 /*! CLR_TXF - Clear TX FIFO 10896 * 0b0..Do not clear the TX FIFO counter. 10897 * 0b1..Clear the TX FIFO counter. 10898 */ 10899 #define SPI_MCR_CLR_TXF(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_CLR_TXF_SHIFT)) & SPI_MCR_CLR_TXF_MASK) 10900 #define SPI_MCR_DIS_RXF_MASK (0x1000U) 10901 #define SPI_MCR_DIS_RXF_SHIFT (12U) 10902 /*! DIS_RXF - Disable Receive FIFO 10903 * 0b0..RX FIFO is enabled. 10904 * 0b1..RX FIFO is disabled. 10905 */ 10906 #define SPI_MCR_DIS_RXF(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_DIS_RXF_SHIFT)) & SPI_MCR_DIS_RXF_MASK) 10907 #define SPI_MCR_DIS_TXF_MASK (0x2000U) 10908 #define SPI_MCR_DIS_TXF_SHIFT (13U) 10909 /*! DIS_TXF - Disable Transmit FIFO 10910 * 0b0..TX FIFO is enabled. 10911 * 0b1..TX FIFO is disabled. 10912 */ 10913 #define SPI_MCR_DIS_TXF(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_DIS_TXF_SHIFT)) & SPI_MCR_DIS_TXF_MASK) 10914 #define SPI_MCR_MDIS_MASK (0x4000U) 10915 #define SPI_MCR_MDIS_SHIFT (14U) 10916 /*! MDIS - Module Disable 10917 * 0b0..Enables the module clocks. 10918 * 0b1..Allows external logic to disable the module clocks. 10919 */ 10920 #define SPI_MCR_MDIS(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_MDIS_SHIFT)) & SPI_MCR_MDIS_MASK) 10921 #define SPI_MCR_DOZE_MASK (0x8000U) 10922 #define SPI_MCR_DOZE_SHIFT (15U) 10923 /*! DOZE - Doze Enable 10924 * 0b0..Doze mode has no effect on the module. 10925 * 0b1..Doze mode disables the module. 10926 */ 10927 #define SPI_MCR_DOZE(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_DOZE_SHIFT)) & SPI_MCR_DOZE_MASK) 10928 #define SPI_MCR_PCSIS_MASK (0x1F0000U) 10929 #define SPI_MCR_PCSIS_SHIFT (16U) 10930 /*! PCSIS - Peripheral Chip Select x Inactive State 10931 * 0b00000..The inactive state of PCSx is low. 10932 * 0b00001..The inactive state of PCSx is high. 10933 */ 10934 #define SPI_MCR_PCSIS(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_PCSIS_SHIFT)) & SPI_MCR_PCSIS_MASK) 10935 #define SPI_MCR_ROOE_MASK (0x1000000U) 10936 #define SPI_MCR_ROOE_SHIFT (24U) 10937 /*! ROOE - Receive FIFO Overflow Overwrite Enable 10938 * 0b0..Incoming data is ignored. 10939 * 0b1..Incoming data is shifted into the shift register. 10940 */ 10941 #define SPI_MCR_ROOE(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_ROOE_SHIFT)) & SPI_MCR_ROOE_MASK) 10942 #define SPI_MCR_MTFE_MASK (0x4000000U) 10943 #define SPI_MCR_MTFE_SHIFT (26U) 10944 /*! MTFE - Modified Transfer Format Enable 10945 * 0b0..Modified SPI transfer format disabled. 10946 * 0b1..Modified SPI transfer format enabled. 10947 */ 10948 #define SPI_MCR_MTFE(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_MTFE_SHIFT)) & SPI_MCR_MTFE_MASK) 10949 #define SPI_MCR_FRZ_MASK (0x8000000U) 10950 #define SPI_MCR_FRZ_SHIFT (27U) 10951 /*! FRZ - Freeze 10952 * 0b0..Do not halt serial transfers in Debug mode. 10953 * 0b1..Halt serial transfers in Debug mode. 10954 */ 10955 #define SPI_MCR_FRZ(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_FRZ_SHIFT)) & SPI_MCR_FRZ_MASK) 10956 #define SPI_MCR_DCONF_MASK (0x30000000U) 10957 #define SPI_MCR_DCONF_SHIFT (28U) 10958 /*! DCONF - SPI Configuration. 10959 * 0b00..SPI 10960 * 0b01..Reserved 10961 * 0b10..Reserved 10962 * 0b11..Reserved 10963 */ 10964 #define SPI_MCR_DCONF(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_DCONF_SHIFT)) & SPI_MCR_DCONF_MASK) 10965 #define SPI_MCR_CONT_SCKE_MASK (0x40000000U) 10966 #define SPI_MCR_CONT_SCKE_SHIFT (30U) 10967 /*! CONT_SCKE - Continuous SCK Enable 10968 * 0b0..Continuous SCK disabled. 10969 * 0b1..Continuous SCK enabled. 10970 */ 10971 #define SPI_MCR_CONT_SCKE(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_CONT_SCKE_SHIFT)) & SPI_MCR_CONT_SCKE_MASK) 10972 #define SPI_MCR_MSTR_MASK (0x80000000U) 10973 #define SPI_MCR_MSTR_SHIFT (31U) 10974 /*! MSTR - Master/Slave Mode Select 10975 * 0b0..Enables Slave mode 10976 * 0b1..Enables Master mode 10977 */ 10978 #define SPI_MCR_MSTR(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_MSTR_SHIFT)) & SPI_MCR_MSTR_MASK) 10979 /*! @} */ 10980 10981 /*! @name TCR - Transfer Count Register */ 10982 /*! @{ */ 10983 #define SPI_TCR_SPI_TCNT_MASK (0xFFFF0000U) 10984 #define SPI_TCR_SPI_TCNT_SHIFT (16U) 10985 #define SPI_TCR_SPI_TCNT(x) (((uint32_t)(((uint32_t)(x)) << SPI_TCR_SPI_TCNT_SHIFT)) & SPI_TCR_SPI_TCNT_MASK) 10986 /*! @} */ 10987 10988 /*! @name CTAR - Clock and Transfer Attributes Register (In Master Mode) */ 10989 /*! @{ */ 10990 #define SPI_CTAR_BR_MASK (0xFU) 10991 #define SPI_CTAR_BR_SHIFT (0U) 10992 #define SPI_CTAR_BR(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_BR_SHIFT)) & SPI_CTAR_BR_MASK) 10993 #define SPI_CTAR_DT_MASK (0xF0U) 10994 #define SPI_CTAR_DT_SHIFT (4U) 10995 #define SPI_CTAR_DT(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_DT_SHIFT)) & SPI_CTAR_DT_MASK) 10996 #define SPI_CTAR_ASC_MASK (0xF00U) 10997 #define SPI_CTAR_ASC_SHIFT (8U) 10998 #define SPI_CTAR_ASC(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_ASC_SHIFT)) & SPI_CTAR_ASC_MASK) 10999 #define SPI_CTAR_CSSCK_MASK (0xF000U) 11000 #define SPI_CTAR_CSSCK_SHIFT (12U) 11001 #define SPI_CTAR_CSSCK(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_CSSCK_SHIFT)) & SPI_CTAR_CSSCK_MASK) 11002 #define SPI_CTAR_PBR_MASK (0x30000U) 11003 #define SPI_CTAR_PBR_SHIFT (16U) 11004 /*! PBR - Baud Rate Prescaler 11005 * 0b00..Baud Rate Prescaler value is 2. 11006 * 0b01..Baud Rate Prescaler value is 3. 11007 * 0b10..Baud Rate Prescaler value is 5. 11008 * 0b11..Baud Rate Prescaler value is 7. 11009 */ 11010 #define SPI_CTAR_PBR(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_PBR_SHIFT)) & SPI_CTAR_PBR_MASK) 11011 #define SPI_CTAR_PDT_MASK (0xC0000U) 11012 #define SPI_CTAR_PDT_SHIFT (18U) 11013 /*! PDT - Delay after Transfer Prescaler 11014 * 0b00..Delay after Transfer Prescaler value is 1. 11015 * 0b01..Delay after Transfer Prescaler value is 3. 11016 * 0b10..Delay after Transfer Prescaler value is 5. 11017 * 0b11..Delay after Transfer Prescaler value is 7. 11018 */ 11019 #define SPI_CTAR_PDT(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_PDT_SHIFT)) & SPI_CTAR_PDT_MASK) 11020 #define SPI_CTAR_PASC_MASK (0x300000U) 11021 #define SPI_CTAR_PASC_SHIFT (20U) 11022 /*! PASC - After SCK Delay Prescaler 11023 * 0b00..Delay after Transfer Prescaler value is 1. 11024 * 0b01..Delay after Transfer Prescaler value is 3. 11025 * 0b10..Delay after Transfer Prescaler value is 5. 11026 * 0b11..Delay after Transfer Prescaler value is 7. 11027 */ 11028 #define SPI_CTAR_PASC(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_PASC_SHIFT)) & SPI_CTAR_PASC_MASK) 11029 #define SPI_CTAR_PCSSCK_MASK (0xC00000U) 11030 #define SPI_CTAR_PCSSCK_SHIFT (22U) 11031 /*! PCSSCK - PCS to SCK Delay Prescaler 11032 * 0b00..PCS to SCK Prescaler value is 1. 11033 * 0b01..PCS to SCK Prescaler value is 3. 11034 * 0b10..PCS to SCK Prescaler value is 5. 11035 * 0b11..PCS to SCK Prescaler value is 7. 11036 */ 11037 #define SPI_CTAR_PCSSCK(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_PCSSCK_SHIFT)) & SPI_CTAR_PCSSCK_MASK) 11038 #define SPI_CTAR_LSBFE_MASK (0x1000000U) 11039 #define SPI_CTAR_LSBFE_SHIFT (24U) 11040 /*! LSBFE - LSB First 11041 * 0b0..Data is transferred MSB first. 11042 * 0b1..Data is transferred LSB first. 11043 */ 11044 #define SPI_CTAR_LSBFE(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_LSBFE_SHIFT)) & SPI_CTAR_LSBFE_MASK) 11045 #define SPI_CTAR_CPHA_MASK (0x2000000U) 11046 #define SPI_CTAR_CPHA_SHIFT (25U) 11047 /*! CPHA - Clock Phase 11048 * 0b0..Data is captured on the leading edge of SCK and changed on the following edge. 11049 * 0b1..Data is changed on the leading edge of SCK and captured on the following edge. 11050 */ 11051 #define SPI_CTAR_CPHA(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_CPHA_SHIFT)) & SPI_CTAR_CPHA_MASK) 11052 #define SPI_CTAR_CPOL_MASK (0x4000000U) 11053 #define SPI_CTAR_CPOL_SHIFT (26U) 11054 /*! CPOL - Clock Polarity 11055 * 0b0..The inactive state value of SCK is low. 11056 * 0b1..The inactive state value of SCK is high. 11057 */ 11058 #define SPI_CTAR_CPOL(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_CPOL_SHIFT)) & SPI_CTAR_CPOL_MASK) 11059 #define SPI_CTAR_FMSZ_MASK (0x78000000U) 11060 #define SPI_CTAR_FMSZ_SHIFT (27U) 11061 #define SPI_CTAR_FMSZ(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_FMSZ_SHIFT)) & SPI_CTAR_FMSZ_MASK) 11062 #define SPI_CTAR_DBR_MASK (0x80000000U) 11063 #define SPI_CTAR_DBR_SHIFT (31U) 11064 /*! DBR - Double Baud Rate 11065 * 0b0..The baud rate is computed normally with a 50/50 duty cycle. 11066 * 0b1..The baud rate is doubled with the duty cycle depending on the Baud Rate Prescaler. 11067 */ 11068 #define SPI_CTAR_DBR(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_DBR_SHIFT)) & SPI_CTAR_DBR_MASK) 11069 /*! @} */ 11070 11071 /* The count of SPI_CTAR */ 11072 #define SPI_CTAR_COUNT (2U) 11073 11074 /*! @name CTAR_SLAVE - Clock and Transfer Attributes Register (In Slave Mode) */ 11075 /*! @{ */ 11076 #define SPI_CTAR_SLAVE_CPHA_MASK (0x2000000U) 11077 #define SPI_CTAR_SLAVE_CPHA_SHIFT (25U) 11078 /*! CPHA - Clock Phase 11079 * 0b0..Data is captured on the leading edge of SCK and changed on the following edge. 11080 * 0b1..Data is changed on the leading edge of SCK and captured on the following edge. 11081 */ 11082 #define SPI_CTAR_SLAVE_CPHA(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_SLAVE_CPHA_SHIFT)) & SPI_CTAR_SLAVE_CPHA_MASK) 11083 #define SPI_CTAR_SLAVE_CPOL_MASK (0x4000000U) 11084 #define SPI_CTAR_SLAVE_CPOL_SHIFT (26U) 11085 /*! CPOL - Clock Polarity 11086 * 0b0..The inactive state value of SCK is low. 11087 * 0b1..The inactive state value of SCK is high. 11088 */ 11089 #define SPI_CTAR_SLAVE_CPOL(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_SLAVE_CPOL_SHIFT)) & SPI_CTAR_SLAVE_CPOL_MASK) 11090 #define SPI_CTAR_SLAVE_FMSZ_MASK (0x78000000U) 11091 #define SPI_CTAR_SLAVE_FMSZ_SHIFT (27U) 11092 #define SPI_CTAR_SLAVE_FMSZ(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_SLAVE_FMSZ_SHIFT)) & SPI_CTAR_SLAVE_FMSZ_MASK) 11093 /*! @} */ 11094 11095 /* The count of SPI_CTAR_SLAVE */ 11096 #define SPI_CTAR_SLAVE_COUNT (1U) 11097 11098 /*! @name SR - Status Register */ 11099 /*! @{ */ 11100 #define SPI_SR_POPNXTPTR_MASK (0xFU) 11101 #define SPI_SR_POPNXTPTR_SHIFT (0U) 11102 #define SPI_SR_POPNXTPTR(x) (((uint32_t)(((uint32_t)(x)) << SPI_SR_POPNXTPTR_SHIFT)) & SPI_SR_POPNXTPTR_MASK) 11103 #define SPI_SR_RXCTR_MASK (0xF0U) 11104 #define SPI_SR_RXCTR_SHIFT (4U) 11105 #define SPI_SR_RXCTR(x) (((uint32_t)(((uint32_t)(x)) << SPI_SR_RXCTR_SHIFT)) & SPI_SR_RXCTR_MASK) 11106 #define SPI_SR_TXNXTPTR_MASK (0xF00U) 11107 #define SPI_SR_TXNXTPTR_SHIFT (8U) 11108 #define SPI_SR_TXNXTPTR(x) (((uint32_t)(((uint32_t)(x)) << SPI_SR_TXNXTPTR_SHIFT)) & SPI_SR_TXNXTPTR_MASK) 11109 #define SPI_SR_TXCTR_MASK (0xF000U) 11110 #define SPI_SR_TXCTR_SHIFT (12U) 11111 #define SPI_SR_TXCTR(x) (((uint32_t)(((uint32_t)(x)) << SPI_SR_TXCTR_SHIFT)) & SPI_SR_TXCTR_MASK) 11112 #define SPI_SR_RFDF_MASK (0x20000U) 11113 #define SPI_SR_RFDF_SHIFT (17U) 11114 /*! RFDF - Receive FIFO Drain Flag 11115 * 0b0..RX FIFO is empty. 11116 * 0b1..RX FIFO is not empty. 11117 */ 11118 #define SPI_SR_RFDF(x) (((uint32_t)(((uint32_t)(x)) << SPI_SR_RFDF_SHIFT)) & SPI_SR_RFDF_MASK) 11119 #define SPI_SR_RFOF_MASK (0x80000U) 11120 #define SPI_SR_RFOF_SHIFT (19U) 11121 /*! RFOF - Receive FIFO Overflow Flag 11122 * 0b0..No Rx FIFO overflow. 11123 * 0b1..Rx FIFO overflow has occurred. 11124 */ 11125 #define SPI_SR_RFOF(x) (((uint32_t)(((uint32_t)(x)) << SPI_SR_RFOF_SHIFT)) & SPI_SR_RFOF_MASK) 11126 #define SPI_SR_TFFF_MASK (0x2000000U) 11127 #define SPI_SR_TFFF_SHIFT (25U) 11128 /*! TFFF - Transmit FIFO Fill Flag 11129 * 0b0..TX FIFO is full. 11130 * 0b1..TX FIFO is not full. 11131 */ 11132 #define SPI_SR_TFFF(x) (((uint32_t)(((uint32_t)(x)) << SPI_SR_TFFF_SHIFT)) & SPI_SR_TFFF_MASK) 11133 #define SPI_SR_TFUF_MASK (0x8000000U) 11134 #define SPI_SR_TFUF_SHIFT (27U) 11135 /*! TFUF - Transmit FIFO Underflow Flag 11136 * 0b0..No TX FIFO underflow. 11137 * 0b1..TX FIFO underflow has occurred. 11138 */ 11139 #define SPI_SR_TFUF(x) (((uint32_t)(((uint32_t)(x)) << SPI_SR_TFUF_SHIFT)) & SPI_SR_TFUF_MASK) 11140 #define SPI_SR_EOQF_MASK (0x10000000U) 11141 #define SPI_SR_EOQF_SHIFT (28U) 11142 /*! EOQF - End of Queue Flag 11143 * 0b0..EOQ is not set in the executing command. 11144 * 0b1..EOQ is set in the executing SPI command. 11145 */ 11146 #define SPI_SR_EOQF(x) (((uint32_t)(((uint32_t)(x)) << SPI_SR_EOQF_SHIFT)) & SPI_SR_EOQF_MASK) 11147 #define SPI_SR_TXRXS_MASK (0x40000000U) 11148 #define SPI_SR_TXRXS_SHIFT (30U) 11149 /*! TXRXS - TX and RX Status 11150 * 0b0..Transmit and receive operations are disabled (The module is in Stopped state). 11151 * 0b1..Transmit and receive operations are enabled (The module is in Running state). 11152 */ 11153 #define SPI_SR_TXRXS(x) (((uint32_t)(((uint32_t)(x)) << SPI_SR_TXRXS_SHIFT)) & SPI_SR_TXRXS_MASK) 11154 #define SPI_SR_TCF_MASK (0x80000000U) 11155 #define SPI_SR_TCF_SHIFT (31U) 11156 /*! TCF - Transfer Complete Flag 11157 * 0b0..Transfer not complete. 11158 * 0b1..Transfer complete. 11159 */ 11160 #define SPI_SR_TCF(x) (((uint32_t)(((uint32_t)(x)) << SPI_SR_TCF_SHIFT)) & SPI_SR_TCF_MASK) 11161 /*! @} */ 11162 11163 /*! @name RSER - DMA/Interrupt Request Select and Enable Register */ 11164 /*! @{ */ 11165 #define SPI_RSER_RFDF_DIRS_MASK (0x10000U) 11166 #define SPI_RSER_RFDF_DIRS_SHIFT (16U) 11167 /*! RFDF_DIRS - Receive FIFO Drain DMA or Interrupt Request Select 11168 * 0b0..Interrupt request. 11169 * 0b1..DMA request. 11170 */ 11171 #define SPI_RSER_RFDF_DIRS(x) (((uint32_t)(((uint32_t)(x)) << SPI_RSER_RFDF_DIRS_SHIFT)) & SPI_RSER_RFDF_DIRS_MASK) 11172 #define SPI_RSER_RFDF_RE_MASK (0x20000U) 11173 #define SPI_RSER_RFDF_RE_SHIFT (17U) 11174 /*! RFDF_RE - Receive FIFO Drain Request Enable 11175 * 0b0..RFDF interrupt or DMA requests are disabled. 11176 * 0b1..RFDF interrupt or DMA requests are enabled. 11177 */ 11178 #define SPI_RSER_RFDF_RE(x) (((uint32_t)(((uint32_t)(x)) << SPI_RSER_RFDF_RE_SHIFT)) & SPI_RSER_RFDF_RE_MASK) 11179 #define SPI_RSER_RFOF_RE_MASK (0x80000U) 11180 #define SPI_RSER_RFOF_RE_SHIFT (19U) 11181 /*! RFOF_RE - Receive FIFO Overflow Request Enable 11182 * 0b0..RFOF interrupt requests are disabled. 11183 * 0b1..RFOF interrupt requests are enabled. 11184 */ 11185 #define SPI_RSER_RFOF_RE(x) (((uint32_t)(((uint32_t)(x)) << SPI_RSER_RFOF_RE_SHIFT)) & SPI_RSER_RFOF_RE_MASK) 11186 #define SPI_RSER_TFFF_DIRS_MASK (0x1000000U) 11187 #define SPI_RSER_TFFF_DIRS_SHIFT (24U) 11188 /*! TFFF_DIRS - Transmit FIFO Fill DMA or Interrupt Request Select 11189 * 0b0..TFFF flag generates interrupt requests. 11190 * 0b1..TFFF flag generates DMA requests. 11191 */ 11192 #define SPI_RSER_TFFF_DIRS(x) (((uint32_t)(((uint32_t)(x)) << SPI_RSER_TFFF_DIRS_SHIFT)) & SPI_RSER_TFFF_DIRS_MASK) 11193 #define SPI_RSER_TFFF_RE_MASK (0x2000000U) 11194 #define SPI_RSER_TFFF_RE_SHIFT (25U) 11195 /*! TFFF_RE - Transmit FIFO Fill Request Enable 11196 * 0b0..TFFF interrupts or DMA requests are disabled. 11197 * 0b1..TFFF interrupts or DMA requests are enabled. 11198 */ 11199 #define SPI_RSER_TFFF_RE(x) (((uint32_t)(((uint32_t)(x)) << SPI_RSER_TFFF_RE_SHIFT)) & SPI_RSER_TFFF_RE_MASK) 11200 #define SPI_RSER_TFUF_RE_MASK (0x8000000U) 11201 #define SPI_RSER_TFUF_RE_SHIFT (27U) 11202 /*! TFUF_RE - Transmit FIFO Underflow Request Enable 11203 * 0b0..TFUF interrupt requests are disabled. 11204 * 0b1..TFUF interrupt requests are enabled. 11205 */ 11206 #define SPI_RSER_TFUF_RE(x) (((uint32_t)(((uint32_t)(x)) << SPI_RSER_TFUF_RE_SHIFT)) & SPI_RSER_TFUF_RE_MASK) 11207 #define SPI_RSER_EOQF_RE_MASK (0x10000000U) 11208 #define SPI_RSER_EOQF_RE_SHIFT (28U) 11209 /*! EOQF_RE - Finished Request Enable 11210 * 0b0..EOQF interrupt requests are disabled. 11211 * 0b1..EOQF interrupt requests are enabled. 11212 */ 11213 #define SPI_RSER_EOQF_RE(x) (((uint32_t)(((uint32_t)(x)) << SPI_RSER_EOQF_RE_SHIFT)) & SPI_RSER_EOQF_RE_MASK) 11214 #define SPI_RSER_TCF_RE_MASK (0x80000000U) 11215 #define SPI_RSER_TCF_RE_SHIFT (31U) 11216 /*! TCF_RE - Transmission Complete Request Enable 11217 * 0b0..TCF interrupt requests are disabled. 11218 * 0b1..TCF interrupt requests are enabled. 11219 */ 11220 #define SPI_RSER_TCF_RE(x) (((uint32_t)(((uint32_t)(x)) << SPI_RSER_TCF_RE_SHIFT)) & SPI_RSER_TCF_RE_MASK) 11221 /*! @} */ 11222 11223 /*! @name PUSHR - PUSH TX FIFO Register In Master Mode */ 11224 /*! @{ */ 11225 #define SPI_PUSHR_TXDATA_MASK (0xFFFFU) 11226 #define SPI_PUSHR_TXDATA_SHIFT (0U) 11227 #define SPI_PUSHR_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_PUSHR_TXDATA_SHIFT)) & SPI_PUSHR_TXDATA_MASK) 11228 #define SPI_PUSHR_PCS_MASK (0x1F0000U) 11229 #define SPI_PUSHR_PCS_SHIFT (16U) 11230 /*! PCS 11231 * 0b00000..Negate the PCS[x] signal. 11232 * 0b00001..Assert the PCS[x] signal. 11233 */ 11234 #define SPI_PUSHR_PCS(x) (((uint32_t)(((uint32_t)(x)) << SPI_PUSHR_PCS_SHIFT)) & SPI_PUSHR_PCS_MASK) 11235 #define SPI_PUSHR_CTCNT_MASK (0x4000000U) 11236 #define SPI_PUSHR_CTCNT_SHIFT (26U) 11237 /*! CTCNT - Clear Transfer Counter 11238 * 0b0..Do not clear the TCR[TCNT] field. 11239 * 0b1..Clear the TCR[TCNT] field. 11240 */ 11241 #define SPI_PUSHR_CTCNT(x) (((uint32_t)(((uint32_t)(x)) << SPI_PUSHR_CTCNT_SHIFT)) & SPI_PUSHR_CTCNT_MASK) 11242 #define SPI_PUSHR_EOQ_MASK (0x8000000U) 11243 #define SPI_PUSHR_EOQ_SHIFT (27U) 11244 /*! EOQ - End Of Queue 11245 * 0b0..The SPI data is not the last data to transfer. 11246 * 0b1..The SPI data is the last data to transfer. 11247 */ 11248 #define SPI_PUSHR_EOQ(x) (((uint32_t)(((uint32_t)(x)) << SPI_PUSHR_EOQ_SHIFT)) & SPI_PUSHR_EOQ_MASK) 11249 #define SPI_PUSHR_CTAS_MASK (0x70000000U) 11250 #define SPI_PUSHR_CTAS_SHIFT (28U) 11251 /*! CTAS - Clock and Transfer Attributes Select 11252 * 0b000..CTAR0 11253 * 0b001..CTAR1 11254 * 0b010..Reserved 11255 * 0b011..Reserved 11256 * 0b100..Reserved 11257 * 0b101..Reserved 11258 * 0b110..Reserved 11259 * 0b111..Reserved 11260 */ 11261 #define SPI_PUSHR_CTAS(x) (((uint32_t)(((uint32_t)(x)) << SPI_PUSHR_CTAS_SHIFT)) & SPI_PUSHR_CTAS_MASK) 11262 #define SPI_PUSHR_CONT_MASK (0x80000000U) 11263 #define SPI_PUSHR_CONT_SHIFT (31U) 11264 /*! CONT - Continuous Peripheral Chip Select Enable 11265 * 0b0..Return PCSn signals to their inactive state between transfers. 11266 * 0b1..Keep PCSn signals asserted between transfers. 11267 */ 11268 #define SPI_PUSHR_CONT(x) (((uint32_t)(((uint32_t)(x)) << SPI_PUSHR_CONT_SHIFT)) & SPI_PUSHR_CONT_MASK) 11269 /*! @} */ 11270 11271 /*! @name PUSHR_SLAVE - PUSH TX FIFO Register In Slave Mode */ 11272 /*! @{ */ 11273 #define SPI_PUSHR_SLAVE_TXDATA_MASK (0xFFFFU) 11274 #define SPI_PUSHR_SLAVE_TXDATA_SHIFT (0U) 11275 #define SPI_PUSHR_SLAVE_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_PUSHR_SLAVE_TXDATA_SHIFT)) & SPI_PUSHR_SLAVE_TXDATA_MASK) 11276 /*! @} */ 11277 11278 /*! @name POPR - POP RX FIFO Register */ 11279 /*! @{ */ 11280 #define SPI_POPR_RXDATA_MASK (0xFFFFFFFFU) 11281 #define SPI_POPR_RXDATA_SHIFT (0U) 11282 #define SPI_POPR_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_POPR_RXDATA_SHIFT)) & SPI_POPR_RXDATA_MASK) 11283 /*! @} */ 11284 11285 /*! @name TXFR0 - Transmit FIFO Registers */ 11286 /*! @{ */ 11287 #define SPI_TXFR0_TXDATA_MASK (0xFFFFU) 11288 #define SPI_TXFR0_TXDATA_SHIFT (0U) 11289 #define SPI_TXFR0_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_TXFR0_TXDATA_SHIFT)) & SPI_TXFR0_TXDATA_MASK) 11290 #define SPI_TXFR0_TXCMD_TXDATA_MASK (0xFFFF0000U) 11291 #define SPI_TXFR0_TXCMD_TXDATA_SHIFT (16U) 11292 #define SPI_TXFR0_TXCMD_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_TXFR0_TXCMD_TXDATA_SHIFT)) & SPI_TXFR0_TXCMD_TXDATA_MASK) 11293 /*! @} */ 11294 11295 /*! @name TXFR1 - Transmit FIFO Registers */ 11296 /*! @{ */ 11297 #define SPI_TXFR1_TXDATA_MASK (0xFFFFU) 11298 #define SPI_TXFR1_TXDATA_SHIFT (0U) 11299 #define SPI_TXFR1_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_TXFR1_TXDATA_SHIFT)) & SPI_TXFR1_TXDATA_MASK) 11300 #define SPI_TXFR1_TXCMD_TXDATA_MASK (0xFFFF0000U) 11301 #define SPI_TXFR1_TXCMD_TXDATA_SHIFT (16U) 11302 #define SPI_TXFR1_TXCMD_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_TXFR1_TXCMD_TXDATA_SHIFT)) & SPI_TXFR1_TXCMD_TXDATA_MASK) 11303 /*! @} */ 11304 11305 /*! @name TXFR2 - Transmit FIFO Registers */ 11306 /*! @{ */ 11307 #define SPI_TXFR2_TXDATA_MASK (0xFFFFU) 11308 #define SPI_TXFR2_TXDATA_SHIFT (0U) 11309 #define SPI_TXFR2_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_TXFR2_TXDATA_SHIFT)) & SPI_TXFR2_TXDATA_MASK) 11310 #define SPI_TXFR2_TXCMD_TXDATA_MASK (0xFFFF0000U) 11311 #define SPI_TXFR2_TXCMD_TXDATA_SHIFT (16U) 11312 #define SPI_TXFR2_TXCMD_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_TXFR2_TXCMD_TXDATA_SHIFT)) & SPI_TXFR2_TXCMD_TXDATA_MASK) 11313 /*! @} */ 11314 11315 /*! @name TXFR3 - Transmit FIFO Registers */ 11316 /*! @{ */ 11317 #define SPI_TXFR3_TXDATA_MASK (0xFFFFU) 11318 #define SPI_TXFR3_TXDATA_SHIFT (0U) 11319 #define SPI_TXFR3_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_TXFR3_TXDATA_SHIFT)) & SPI_TXFR3_TXDATA_MASK) 11320 #define SPI_TXFR3_TXCMD_TXDATA_MASK (0xFFFF0000U) 11321 #define SPI_TXFR3_TXCMD_TXDATA_SHIFT (16U) 11322 #define SPI_TXFR3_TXCMD_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_TXFR3_TXCMD_TXDATA_SHIFT)) & SPI_TXFR3_TXCMD_TXDATA_MASK) 11323 /*! @} */ 11324 11325 /*! @name RXFR0 - Receive FIFO Registers */ 11326 /*! @{ */ 11327 #define SPI_RXFR0_RXDATA_MASK (0xFFFFFFFFU) 11328 #define SPI_RXFR0_RXDATA_SHIFT (0U) 11329 #define SPI_RXFR0_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_RXFR0_RXDATA_SHIFT)) & SPI_RXFR0_RXDATA_MASK) 11330 /*! @} */ 11331 11332 /*! @name RXFR1 - Receive FIFO Registers */ 11333 /*! @{ */ 11334 #define SPI_RXFR1_RXDATA_MASK (0xFFFFFFFFU) 11335 #define SPI_RXFR1_RXDATA_SHIFT (0U) 11336 #define SPI_RXFR1_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_RXFR1_RXDATA_SHIFT)) & SPI_RXFR1_RXDATA_MASK) 11337 /*! @} */ 11338 11339 /*! @name RXFR2 - Receive FIFO Registers */ 11340 /*! @{ */ 11341 #define SPI_RXFR2_RXDATA_MASK (0xFFFFFFFFU) 11342 #define SPI_RXFR2_RXDATA_SHIFT (0U) 11343 #define SPI_RXFR2_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_RXFR2_RXDATA_SHIFT)) & SPI_RXFR2_RXDATA_MASK) 11344 /*! @} */ 11345 11346 /*! @name RXFR3 - Receive FIFO Registers */ 11347 /*! @{ */ 11348 #define SPI_RXFR3_RXDATA_MASK (0xFFFFFFFFU) 11349 #define SPI_RXFR3_RXDATA_SHIFT (0U) 11350 #define SPI_RXFR3_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_RXFR3_RXDATA_SHIFT)) & SPI_RXFR3_RXDATA_MASK) 11351 /*! @} */ 11352 11353 /*! @name SREX - Status Register Extended */ 11354 /*! @{ */ 11355 #define SPI_SREX_CMDNXTPTR_MASK (0xFU) 11356 #define SPI_SREX_CMDNXTPTR_SHIFT (0U) 11357 #define SPI_SREX_CMDNXTPTR(x) (((uint32_t)(((uint32_t)(x)) << SPI_SREX_CMDNXTPTR_SHIFT)) & SPI_SREX_CMDNXTPTR_MASK) 11358 #define SPI_SREX_CMDCTR_MASK (0x1F0U) 11359 #define SPI_SREX_CMDCTR_SHIFT (4U) 11360 #define SPI_SREX_CMDCTR(x) (((uint32_t)(((uint32_t)(x)) << SPI_SREX_CMDCTR_SHIFT)) & SPI_SREX_CMDCTR_MASK) 11361 #define SPI_SREX_TXCTR4_MASK (0x800U) 11362 #define SPI_SREX_TXCTR4_SHIFT (11U) 11363 #define SPI_SREX_TXCTR4(x) (((uint32_t)(((uint32_t)(x)) << SPI_SREX_TXCTR4_SHIFT)) & SPI_SREX_TXCTR4_MASK) 11364 #define SPI_SREX_RXCTR4_MASK (0x4000U) 11365 #define SPI_SREX_RXCTR4_SHIFT (14U) 11366 #define SPI_SREX_RXCTR4(x) (((uint32_t)(((uint32_t)(x)) << SPI_SREX_RXCTR4_SHIFT)) & SPI_SREX_RXCTR4_MASK) 11367 /*! @} */ 11368 11369 11370 /*! 11371 * @} 11372 */ /* end of group SPI_Register_Masks */ 11373 11374 11375 /* SPI - Peripheral instance base addresses */ 11376 /** Peripheral SPI0 base address */ 11377 #define SPI0_BASE (0x4002C000u) 11378 /** Peripheral SPI0 base pointer */ 11379 #define SPI0 ((SPI_Type *)SPI0_BASE) 11380 /** Array initializer of SPI peripheral base addresses */ 11381 #define SPI_BASE_ADDRS { SPI0_BASE } 11382 /** Array initializer of SPI peripheral base pointers */ 11383 #define SPI_BASE_PTRS { SPI0 } 11384 /** Interrupt vectors for the SPI peripheral type */ 11385 #define SPI_IRQS { SPI0_IRQn } 11386 11387 /*! 11388 * @} 11389 */ /* end of group SPI_Peripheral_Access_Layer */ 11390 11391 11392 /* ---------------------------------------------------------------------------- 11393 -- UART Peripheral Access Layer 11394 ---------------------------------------------------------------------------- */ 11395 11396 /*! 11397 * @addtogroup UART_Peripheral_Access_Layer UART Peripheral Access Layer 11398 * @{ 11399 */ 11400 11401 /** UART - Register Layout Typedef */ 11402 typedef struct { 11403 __IO uint8_t BDH; /**< UART Baud Rate Registers: High, offset: 0x0 */ 11404 __IO uint8_t BDL; /**< UART Baud Rate Registers: Low, offset: 0x1 */ 11405 __IO uint8_t C1; /**< UART Control Register 1, offset: 0x2 */ 11406 __IO uint8_t C2; /**< UART Control Register 2, offset: 0x3 */ 11407 __I uint8_t S1; /**< UART Status Register 1, offset: 0x4 */ 11408 __IO uint8_t S2; /**< UART Status Register 2, offset: 0x5 */ 11409 __IO uint8_t C3; /**< UART Control Register 3, offset: 0x6 */ 11410 __IO uint8_t D; /**< UART Data Register, offset: 0x7 */ 11411 __IO uint8_t MA1; /**< UART Match Address Registers 1, offset: 0x8 */ 11412 __IO uint8_t MA2; /**< UART Match Address Registers 2, offset: 0x9 */ 11413 __IO uint8_t C4; /**< UART Control Register 4, offset: 0xA */ 11414 __IO uint8_t C5; /**< UART Control Register 5, offset: 0xB */ 11415 __I uint8_t ED; /**< UART Extended Data Register, offset: 0xC */ 11416 __IO uint8_t MODEM; /**< UART Modem Register, offset: 0xD */ 11417 uint8_t RESERVED_0[2]; 11418 __IO uint8_t PFIFO; /**< UART FIFO Parameters, offset: 0x10 */ 11419 __IO uint8_t CFIFO; /**< UART FIFO Control Register, offset: 0x11 */ 11420 __IO uint8_t SFIFO; /**< UART FIFO Status Register, offset: 0x12 */ 11421 __IO uint8_t TWFIFO; /**< UART FIFO Transmit Watermark, offset: 0x13 */ 11422 __I uint8_t TCFIFO; /**< UART FIFO Transmit Count, offset: 0x14 */ 11423 __IO uint8_t RWFIFO; /**< UART FIFO Receive Watermark, offset: 0x15 */ 11424 __I uint8_t RCFIFO; /**< UART FIFO Receive Count, offset: 0x16 */ 11425 } UART_Type; 11426 11427 /* ---------------------------------------------------------------------------- 11428 -- UART Register Masks 11429 ---------------------------------------------------------------------------- */ 11430 11431 /*! 11432 * @addtogroup UART_Register_Masks UART Register Masks 11433 * @{ 11434 */ 11435 11436 /*! @name BDH - UART Baud Rate Registers: High */ 11437 /*! @{ */ 11438 #define UART_BDH_SBR_MASK (0x1FU) 11439 #define UART_BDH_SBR_SHIFT (0U) 11440 #define UART_BDH_SBR(x) (((uint8_t)(((uint8_t)(x)) << UART_BDH_SBR_SHIFT)) & UART_BDH_SBR_MASK) 11441 #define UART_BDH_SBNS_MASK (0x20U) 11442 #define UART_BDH_SBNS_SHIFT (5U) 11443 /*! SBNS - Stop Bit Number Select 11444 * 0b0..Data frame consists of a single stop bit. 11445 * 0b1..Data frame consists of two stop bits. 11446 */ 11447 #define UART_BDH_SBNS(x) (((uint8_t)(((uint8_t)(x)) << UART_BDH_SBNS_SHIFT)) & UART_BDH_SBNS_MASK) 11448 #define UART_BDH_RXEDGIE_MASK (0x40U) 11449 #define UART_BDH_RXEDGIE_SHIFT (6U) 11450 /*! RXEDGIE - RxD Input Active Edge Interrupt Enable 11451 * 0b0..Hardware interrupts from RXEDGIF disabled using polling. 11452 * 0b1..RXEDGIF interrupt request enabled. 11453 */ 11454 #define UART_BDH_RXEDGIE(x) (((uint8_t)(((uint8_t)(x)) << UART_BDH_RXEDGIE_SHIFT)) & UART_BDH_RXEDGIE_MASK) 11455 #define UART_BDH_LBKDIE_MASK (0x80U) 11456 #define UART_BDH_LBKDIE_SHIFT (7U) 11457 /*! LBKDIE - LIN Break Detect Interrupt Enable 11458 * 0b0..LBKDIF interrupt requests disabled. 11459 * 0b1..LBKDIF interrupt requests enabled. 11460 */ 11461 #define UART_BDH_LBKDIE(x) (((uint8_t)(((uint8_t)(x)) << UART_BDH_LBKDIE_SHIFT)) & UART_BDH_LBKDIE_MASK) 11462 /*! @} */ 11463 11464 /*! @name BDL - UART Baud Rate Registers: Low */ 11465 /*! @{ */ 11466 #define UART_BDL_SBR_MASK (0xFFU) 11467 #define UART_BDL_SBR_SHIFT (0U) 11468 #define UART_BDL_SBR(x) (((uint8_t)(((uint8_t)(x)) << UART_BDL_SBR_SHIFT)) & UART_BDL_SBR_MASK) 11469 /*! @} */ 11470 11471 /*! @name C1 - UART Control Register 1 */ 11472 /*! @{ */ 11473 #define UART_C1_PT_MASK (0x1U) 11474 #define UART_C1_PT_SHIFT (0U) 11475 /*! PT - Parity Type 11476 * 0b0..Even parity. 11477 * 0b1..Odd parity. 11478 */ 11479 #define UART_C1_PT(x) (((uint8_t)(((uint8_t)(x)) << UART_C1_PT_SHIFT)) & UART_C1_PT_MASK) 11480 #define UART_C1_PE_MASK (0x2U) 11481 #define UART_C1_PE_SHIFT (1U) 11482 /*! PE - Parity Enable 11483 * 0b0..Parity function disabled. 11484 * 0b1..Parity function enabled. 11485 */ 11486 #define UART_C1_PE(x) (((uint8_t)(((uint8_t)(x)) << UART_C1_PE_SHIFT)) & UART_C1_PE_MASK) 11487 #define UART_C1_ILT_MASK (0x4U) 11488 #define UART_C1_ILT_SHIFT (2U) 11489 /*! ILT - Idle Line Type Select 11490 * 0b0..Idle character bit count starts after start bit. 11491 * 0b1..Idle character bit count starts after stop bit. 11492 */ 11493 #define UART_C1_ILT(x) (((uint8_t)(((uint8_t)(x)) << UART_C1_ILT_SHIFT)) & UART_C1_ILT_MASK) 11494 #define UART_C1_WAKE_MASK (0x8U) 11495 #define UART_C1_WAKE_SHIFT (3U) 11496 /*! WAKE - Receiver Wakeup Method Select 11497 * 0b0..Idle line wakeup. 11498 * 0b1..Address mark wakeup. 11499 */ 11500 #define UART_C1_WAKE(x) (((uint8_t)(((uint8_t)(x)) << UART_C1_WAKE_SHIFT)) & UART_C1_WAKE_MASK) 11501 #define UART_C1_M_MASK (0x10U) 11502 #define UART_C1_M_SHIFT (4U) 11503 /*! M - 9-bit or 8-bit Mode Select 11504 * 0b0..Normal-start + 8 data bits (MSB/LSB first as determined by MSBF) + stop. 11505 * 0b1..Use-start + 9 data bits (MSB/LSB first as determined by MSBF) + stop. 11506 */ 11507 #define UART_C1_M(x) (((uint8_t)(((uint8_t)(x)) << UART_C1_M_SHIFT)) & UART_C1_M_MASK) 11508 #define UART_C1_RSRC_MASK (0x20U) 11509 #define UART_C1_RSRC_SHIFT (5U) 11510 /*! RSRC - Receiver Source Select 11511 * 0b0..Selects internal loop back mode. The receiver input is internally connected to transmitter output. 11512 * 0b1..Single wire UART mode where the receiver input is connected to the transmit pin input signal. 11513 */ 11514 #define UART_C1_RSRC(x) (((uint8_t)(((uint8_t)(x)) << UART_C1_RSRC_SHIFT)) & UART_C1_RSRC_MASK) 11515 #define UART_C1_UARTSWAI_MASK (0x40U) 11516 #define UART_C1_UARTSWAI_SHIFT (6U) 11517 /*! UARTSWAI - UART Stops in Wait Mode 11518 * 0b0..UART clock continues to run in Wait mode. 11519 * 0b1..UART clock freezes while CPU is in Wait mode. 11520 */ 11521 #define UART_C1_UARTSWAI(x) (((uint8_t)(((uint8_t)(x)) << UART_C1_UARTSWAI_SHIFT)) & UART_C1_UARTSWAI_MASK) 11522 #define UART_C1_LOOPS_MASK (0x80U) 11523 #define UART_C1_LOOPS_SHIFT (7U) 11524 /*! LOOPS - Loop Mode Select 11525 * 0b0..Normal operation. 11526 * 0b1..Loop mode where transmitter output is internally connected to receiver input. The receiver input is determined by RSRC. 11527 */ 11528 #define UART_C1_LOOPS(x) (((uint8_t)(((uint8_t)(x)) << UART_C1_LOOPS_SHIFT)) & UART_C1_LOOPS_MASK) 11529 /*! @} */ 11530 11531 /*! @name C2 - UART Control Register 2 */ 11532 /*! @{ */ 11533 #define UART_C2_SBK_MASK (0x1U) 11534 #define UART_C2_SBK_SHIFT (0U) 11535 /*! SBK - Send Break 11536 * 0b0..Normal transmitter operation. 11537 * 0b1..Queue break characters to be sent. 11538 */ 11539 #define UART_C2_SBK(x) (((uint8_t)(((uint8_t)(x)) << UART_C2_SBK_SHIFT)) & UART_C2_SBK_MASK) 11540 #define UART_C2_RWU_MASK (0x2U) 11541 #define UART_C2_RWU_SHIFT (1U) 11542 /*! RWU - Receiver Wakeup Control 11543 * 0b0..Normal operation. 11544 * 0b1..RWU enables the wakeup function and inhibits further receiver interrupt requests. Normally, hardware wakes the receiver by automatically clearing RWU. 11545 */ 11546 #define UART_C2_RWU(x) (((uint8_t)(((uint8_t)(x)) << UART_C2_RWU_SHIFT)) & UART_C2_RWU_MASK) 11547 #define UART_C2_RE_MASK (0x4U) 11548 #define UART_C2_RE_SHIFT (2U) 11549 /*! RE - Receiver Enable 11550 * 0b0..Receiver off. 11551 * 0b1..Receiver on. 11552 */ 11553 #define UART_C2_RE(x) (((uint8_t)(((uint8_t)(x)) << UART_C2_RE_SHIFT)) & UART_C2_RE_MASK) 11554 #define UART_C2_TE_MASK (0x8U) 11555 #define UART_C2_TE_SHIFT (3U) 11556 /*! TE - Transmitter Enable 11557 * 0b0..Transmitter off. 11558 * 0b1..Transmitter on. 11559 */ 11560 #define UART_C2_TE(x) (((uint8_t)(((uint8_t)(x)) << UART_C2_TE_SHIFT)) & UART_C2_TE_MASK) 11561 #define UART_C2_ILIE_MASK (0x10U) 11562 #define UART_C2_ILIE_SHIFT (4U) 11563 /*! ILIE - Idle Line Interrupt Enable 11564 * 0b0..IDLE interrupt requests disabled. 11565 * 0b1..IDLE interrupt requests enabled. 11566 */ 11567 #define UART_C2_ILIE(x) (((uint8_t)(((uint8_t)(x)) << UART_C2_ILIE_SHIFT)) & UART_C2_ILIE_MASK) 11568 #define UART_C2_RIE_MASK (0x20U) 11569 #define UART_C2_RIE_SHIFT (5U) 11570 /*! RIE - Receiver Full Interrupt or DMA Transfer Enable 11571 * 0b0..RDRF interrupt and DMA transfer requests disabled. 11572 * 0b1..RDRF interrupt or DMA transfer requests enabled. 11573 */ 11574 #define UART_C2_RIE(x) (((uint8_t)(((uint8_t)(x)) << UART_C2_RIE_SHIFT)) & UART_C2_RIE_MASK) 11575 #define UART_C2_TCIE_MASK (0x40U) 11576 #define UART_C2_TCIE_SHIFT (6U) 11577 /*! TCIE - Transmission Complete Interrupt Enable 11578 * 0b0..TC interrupt requests disabled. 11579 * 0b1..TC interrupt requests enabled. 11580 */ 11581 #define UART_C2_TCIE(x) (((uint8_t)(((uint8_t)(x)) << UART_C2_TCIE_SHIFT)) & UART_C2_TCIE_MASK) 11582 #define UART_C2_TIE_MASK (0x80U) 11583 #define UART_C2_TIE_SHIFT (7U) 11584 /*! TIE - Transmitter Interrupt or DMA Transfer Enable. 11585 * 0b0..TDRE interrupt and DMA transfer requests disabled. 11586 * 0b1..TDRE interrupt or DMA transfer requests enabled. 11587 */ 11588 #define UART_C2_TIE(x) (((uint8_t)(((uint8_t)(x)) << UART_C2_TIE_SHIFT)) & UART_C2_TIE_MASK) 11589 /*! @} */ 11590 11591 /*! @name S1 - UART Status Register 1 */ 11592 /*! @{ */ 11593 #define UART_S1_PF_MASK (0x1U) 11594 #define UART_S1_PF_SHIFT (0U) 11595 /*! PF - Parity Error Flag 11596 * 0b0..No parity error detected since the last time this flag was cleared. If the receive buffer has a depth greater than 1, then there may be data in the receive buffer what was received with a parity error. 11597 * 0b1..At least one dataword was received with a parity error since the last time this flag was cleared. 11598 */ 11599 #define UART_S1_PF(x) (((uint8_t)(((uint8_t)(x)) << UART_S1_PF_SHIFT)) & UART_S1_PF_MASK) 11600 #define UART_S1_FE_MASK (0x2U) 11601 #define UART_S1_FE_SHIFT (1U) 11602 /*! FE - Framing Error Flag 11603 * 0b0..No framing error detected. 11604 * 0b1..Framing error. 11605 */ 11606 #define UART_S1_FE(x) (((uint8_t)(((uint8_t)(x)) << UART_S1_FE_SHIFT)) & UART_S1_FE_MASK) 11607 #define UART_S1_NF_MASK (0x4U) 11608 #define UART_S1_NF_SHIFT (2U) 11609 /*! NF - Noise Flag 11610 * 0b0..No noise detected since the last time this flag was cleared. If the receive buffer has a depth greater than 1 then there may be data in the receiver buffer that was received with noise. 11611 * 0b1..At least one dataword was received with noise detected since the last time the flag was cleared. 11612 */ 11613 #define UART_S1_NF(x) (((uint8_t)(((uint8_t)(x)) << UART_S1_NF_SHIFT)) & UART_S1_NF_MASK) 11614 #define UART_S1_OR_MASK (0x8U) 11615 #define UART_S1_OR_SHIFT (3U) 11616 /*! OR - Receiver Overrun Flag 11617 * 0b0..No overrun has occurred since the last time the flag was cleared. 11618 * 0b1..Overrun has occurred or the overrun flag has not been cleared since the last overrun occured. 11619 */ 11620 #define UART_S1_OR(x) (((uint8_t)(((uint8_t)(x)) << UART_S1_OR_SHIFT)) & UART_S1_OR_MASK) 11621 #define UART_S1_IDLE_MASK (0x10U) 11622 #define UART_S1_IDLE_SHIFT (4U) 11623 /*! IDLE - Idle Line Flag 11624 * 0b0..Receiver input is either active now or has never become active since the IDLE flag was last cleared. 11625 * 0b1..Receiver input has become idle or the flag has not been cleared since it last asserted. 11626 */ 11627 #define UART_S1_IDLE(x) (((uint8_t)(((uint8_t)(x)) << UART_S1_IDLE_SHIFT)) & UART_S1_IDLE_MASK) 11628 #define UART_S1_RDRF_MASK (0x20U) 11629 #define UART_S1_RDRF_SHIFT (5U) 11630 /*! RDRF - Receive Data Register Full Flag 11631 * 0b0..The number of datawords in the receive buffer is less than the number indicated by RXWATER. 11632 * 0b1..The number of datawords in the receive buffer is equal to or greater than the number indicated by RXWATER at some point in time since this flag was last cleared. 11633 */ 11634 #define UART_S1_RDRF(x) (((uint8_t)(((uint8_t)(x)) << UART_S1_RDRF_SHIFT)) & UART_S1_RDRF_MASK) 11635 #define UART_S1_TC_MASK (0x40U) 11636 #define UART_S1_TC_SHIFT (6U) 11637 /*! TC - Transmit Complete Flag 11638 * 0b0..Transmitter active (sending data, a preamble, or a break). 11639 * 0b1..Transmitter idle (transmission activity complete). 11640 */ 11641 #define UART_S1_TC(x) (((uint8_t)(((uint8_t)(x)) << UART_S1_TC_SHIFT)) & UART_S1_TC_MASK) 11642 #define UART_S1_TDRE_MASK (0x80U) 11643 #define UART_S1_TDRE_SHIFT (7U) 11644 /*! TDRE - Transmit Data Register Empty Flag 11645 * 0b0..The amount of data in the transmit buffer is greater than the value indicated by TWFIFO[TXWATER]. 11646 * 0b1..The amount of data in the transmit buffer is less than or equal to the value indicated by TWFIFO[TXWATER] at some point in time since the flag has been cleared. 11647 */ 11648 #define UART_S1_TDRE(x) (((uint8_t)(((uint8_t)(x)) << UART_S1_TDRE_SHIFT)) & UART_S1_TDRE_MASK) 11649 /*! @} */ 11650 11651 /*! @name S2 - UART Status Register 2 */ 11652 /*! @{ */ 11653 #define UART_S2_RAF_MASK (0x1U) 11654 #define UART_S2_RAF_SHIFT (0U) 11655 /*! RAF - Receiver Active Flag 11656 * 0b0..UART receiver idle/inactive waiting for a start bit. 11657 * 0b1..UART receiver active, RxD input not idle. 11658 */ 11659 #define UART_S2_RAF(x) (((uint8_t)(((uint8_t)(x)) << UART_S2_RAF_SHIFT)) & UART_S2_RAF_MASK) 11660 #define UART_S2_LBKDE_MASK (0x2U) 11661 #define UART_S2_LBKDE_SHIFT (1U) 11662 /*! LBKDE - LIN Break Detection Enable 11663 * 0b0..Break character detection is disabled. 11664 * 0b1..Break character is detected at length of 11 bit times if C1[M] = 0 or 12 bits time if C1[M] = 1. 11665 */ 11666 #define UART_S2_LBKDE(x) (((uint8_t)(((uint8_t)(x)) << UART_S2_LBKDE_SHIFT)) & UART_S2_LBKDE_MASK) 11667 #define UART_S2_BRK13_MASK (0x4U) 11668 #define UART_S2_BRK13_SHIFT (2U) 11669 /*! BRK13 - Break Transmit Character Length 11670 * 0b0..Break character is 10, 11, or 12 bits long. 11671 * 0b1..Break character is 13 or 14 bits long. 11672 */ 11673 #define UART_S2_BRK13(x) (((uint8_t)(((uint8_t)(x)) << UART_S2_BRK13_SHIFT)) & UART_S2_BRK13_MASK) 11674 #define UART_S2_RWUID_MASK (0x8U) 11675 #define UART_S2_RWUID_SHIFT (3U) 11676 /*! RWUID - Receive Wakeup Idle Detect 11677 * 0b0..S1[IDLE] is not set upon detection of an idle character. 11678 * 0b1..S1[IDLE] is set upon detection of an idle character. 11679 */ 11680 #define UART_S2_RWUID(x) (((uint8_t)(((uint8_t)(x)) << UART_S2_RWUID_SHIFT)) & UART_S2_RWUID_MASK) 11681 #define UART_S2_RXINV_MASK (0x10U) 11682 #define UART_S2_RXINV_SHIFT (4U) 11683 /*! RXINV - Receive Data Inversion 11684 * 0b0..Receive data is not inverted. 11685 * 0b1..Receive data is inverted. 11686 */ 11687 #define UART_S2_RXINV(x) (((uint8_t)(((uint8_t)(x)) << UART_S2_RXINV_SHIFT)) & UART_S2_RXINV_MASK) 11688 #define UART_S2_MSBF_MASK (0x20U) 11689 #define UART_S2_MSBF_SHIFT (5U) 11690 /*! MSBF - Most Significant Bit First 11691 * 0b0..LSB (bit0) is the first bit that is transmitted following the start bit. Further, the first bit received after the start bit is identified as bit0. 11692 * 0b1..MSB (bit8, bit7 or bit6) is the first bit that is transmitted following the start bit, depending on the setting of C1[M] and C1[PE]. Further, the first bit received after the start bit is identified as bit8, bit7, or bit6, depending on the setting of C1[M] and C1[PE]. 11693 */ 11694 #define UART_S2_MSBF(x) (((uint8_t)(((uint8_t)(x)) << UART_S2_MSBF_SHIFT)) & UART_S2_MSBF_MASK) 11695 #define UART_S2_RXEDGIF_MASK (0x40U) 11696 #define UART_S2_RXEDGIF_SHIFT (6U) 11697 /*! RXEDGIF - RxD Pin Active Edge Interrupt Flag 11698 * 0b0..No active edge on the receive pin has occurred. 11699 * 0b1..An active edge on the receive pin has occurred. 11700 */ 11701 #define UART_S2_RXEDGIF(x) (((uint8_t)(((uint8_t)(x)) << UART_S2_RXEDGIF_SHIFT)) & UART_S2_RXEDGIF_MASK) 11702 #define UART_S2_LBKDIF_MASK (0x80U) 11703 #define UART_S2_LBKDIF_SHIFT (7U) 11704 /*! LBKDIF - LIN Break Detect Interrupt Flag 11705 * 0b0..No LIN break character detected. 11706 * 0b1..LIN break character detected. 11707 */ 11708 #define UART_S2_LBKDIF(x) (((uint8_t)(((uint8_t)(x)) << UART_S2_LBKDIF_SHIFT)) & UART_S2_LBKDIF_MASK) 11709 /*! @} */ 11710 11711 /*! @name C3 - UART Control Register 3 */ 11712 /*! @{ */ 11713 #define UART_C3_PEIE_MASK (0x1U) 11714 #define UART_C3_PEIE_SHIFT (0U) 11715 /*! PEIE - Parity Error Interrupt Enable 11716 * 0b0..PF interrupt requests are disabled. 11717 * 0b1..PF interrupt requests are enabled. 11718 */ 11719 #define UART_C3_PEIE(x) (((uint8_t)(((uint8_t)(x)) << UART_C3_PEIE_SHIFT)) & UART_C3_PEIE_MASK) 11720 #define UART_C3_FEIE_MASK (0x2U) 11721 #define UART_C3_FEIE_SHIFT (1U) 11722 /*! FEIE - Framing Error Interrupt Enable 11723 * 0b0..FE interrupt requests are disabled. 11724 * 0b1..FE interrupt requests are enabled. 11725 */ 11726 #define UART_C3_FEIE(x) (((uint8_t)(((uint8_t)(x)) << UART_C3_FEIE_SHIFT)) & UART_C3_FEIE_MASK) 11727 #define UART_C3_NEIE_MASK (0x4U) 11728 #define UART_C3_NEIE_SHIFT (2U) 11729 /*! NEIE - Noise Error Interrupt Enable 11730 * 0b0..NF interrupt requests are disabled. 11731 * 0b1..NF interrupt requests are enabled. 11732 */ 11733 #define UART_C3_NEIE(x) (((uint8_t)(((uint8_t)(x)) << UART_C3_NEIE_SHIFT)) & UART_C3_NEIE_MASK) 11734 #define UART_C3_ORIE_MASK (0x8U) 11735 #define UART_C3_ORIE_SHIFT (3U) 11736 /*! ORIE - Overrun Error Interrupt Enable 11737 * 0b0..OR interrupts are disabled. 11738 * 0b1..OR interrupt requests are enabled. 11739 */ 11740 #define UART_C3_ORIE(x) (((uint8_t)(((uint8_t)(x)) << UART_C3_ORIE_SHIFT)) & UART_C3_ORIE_MASK) 11741 #define UART_C3_TXINV_MASK (0x10U) 11742 #define UART_C3_TXINV_SHIFT (4U) 11743 /*! TXINV - Transmit Data Inversion. 11744 * 0b0..Transmit data is not inverted. 11745 * 0b1..Transmit data is inverted. 11746 */ 11747 #define UART_C3_TXINV(x) (((uint8_t)(((uint8_t)(x)) << UART_C3_TXINV_SHIFT)) & UART_C3_TXINV_MASK) 11748 #define UART_C3_TXDIR_MASK (0x20U) 11749 #define UART_C3_TXDIR_SHIFT (5U) 11750 /*! TXDIR - Transmitter Pin Data Direction in Single-Wire mode 11751 * 0b0..TXD pin is an input in single wire mode. 11752 * 0b1..TXD pin is an output in single wire mode. 11753 */ 11754 #define UART_C3_TXDIR(x) (((uint8_t)(((uint8_t)(x)) << UART_C3_TXDIR_SHIFT)) & UART_C3_TXDIR_MASK) 11755 #define UART_C3_T8_MASK (0x40U) 11756 #define UART_C3_T8_SHIFT (6U) 11757 #define UART_C3_T8(x) (((uint8_t)(((uint8_t)(x)) << UART_C3_T8_SHIFT)) & UART_C3_T8_MASK) 11758 #define UART_C3_R8_MASK (0x80U) 11759 #define UART_C3_R8_SHIFT (7U) 11760 #define UART_C3_R8(x) (((uint8_t)(((uint8_t)(x)) << UART_C3_R8_SHIFT)) & UART_C3_R8_MASK) 11761 /*! @} */ 11762 11763 /*! @name D - UART Data Register */ 11764 /*! @{ */ 11765 #define UART_D_RT_MASK (0xFFU) 11766 #define UART_D_RT_SHIFT (0U) 11767 #define UART_D_RT(x) (((uint8_t)(((uint8_t)(x)) << UART_D_RT_SHIFT)) & UART_D_RT_MASK) 11768 /*! @} */ 11769 11770 /*! @name MA1 - UART Match Address Registers 1 */ 11771 /*! @{ */ 11772 #define UART_MA1_MA_MASK (0xFFU) 11773 #define UART_MA1_MA_SHIFT (0U) 11774 #define UART_MA1_MA(x) (((uint8_t)(((uint8_t)(x)) << UART_MA1_MA_SHIFT)) & UART_MA1_MA_MASK) 11775 /*! @} */ 11776 11777 /*! @name MA2 - UART Match Address Registers 2 */ 11778 /*! @{ */ 11779 #define UART_MA2_MA_MASK (0xFFU) 11780 #define UART_MA2_MA_SHIFT (0U) 11781 #define UART_MA2_MA(x) (((uint8_t)(((uint8_t)(x)) << UART_MA2_MA_SHIFT)) & UART_MA2_MA_MASK) 11782 /*! @} */ 11783 11784 /*! @name C4 - UART Control Register 4 */ 11785 /*! @{ */ 11786 #define UART_C4_BRFA_MASK (0x1FU) 11787 #define UART_C4_BRFA_SHIFT (0U) 11788 #define UART_C4_BRFA(x) (((uint8_t)(((uint8_t)(x)) << UART_C4_BRFA_SHIFT)) & UART_C4_BRFA_MASK) 11789 #define UART_C4_M10_MASK (0x20U) 11790 #define UART_C4_M10_SHIFT (5U) 11791 /*! M10 - 10-bit Mode select 11792 * 0b0..The parity bit is the ninth bit in the serial transmission. 11793 * 0b1..The parity bit is the tenth bit in the serial transmission. 11794 */ 11795 #define UART_C4_M10(x) (((uint8_t)(((uint8_t)(x)) << UART_C4_M10_SHIFT)) & UART_C4_M10_MASK) 11796 #define UART_C4_MAEN2_MASK (0x40U) 11797 #define UART_C4_MAEN2_SHIFT (6U) 11798 /*! MAEN2 - Match Address Mode Enable 2 11799 * 0b0..All data received is transferred to the data buffer if MAEN1 is cleared. 11800 * 0b1..All data received with the most significant bit cleared, is discarded. All data received with the most significant bit set, is compared with contents of MA2 register. If no match occurs, the data is discarded. If a match occurs, data is transferred to the data buffer. 11801 */ 11802 #define UART_C4_MAEN2(x) (((uint8_t)(((uint8_t)(x)) << UART_C4_MAEN2_SHIFT)) & UART_C4_MAEN2_MASK) 11803 #define UART_C4_MAEN1_MASK (0x80U) 11804 #define UART_C4_MAEN1_SHIFT (7U) 11805 /*! MAEN1 - Match Address Mode Enable 1 11806 * 0b0..All data received is transferred to the data buffer if MAEN2 is cleared. 11807 * 0b1..All data received with the most significant bit cleared, is discarded. All data received with the most significant bit set, is compared with contents of MA1 register. If no match occurs, the data is discarded. If match occurs, data is transferred to the data buffer. 11808 */ 11809 #define UART_C4_MAEN1(x) (((uint8_t)(((uint8_t)(x)) << UART_C4_MAEN1_SHIFT)) & UART_C4_MAEN1_MASK) 11810 /*! @} */ 11811 11812 /*! @name C5 - UART Control Register 5 */ 11813 /*! @{ */ 11814 #define UART_C5_RDMAS_MASK (0x20U) 11815 #define UART_C5_RDMAS_SHIFT (5U) 11816 /*! RDMAS - Receiver Full DMA Select 11817 * 0b0..If C2[RIE] and S1[RDRF] are set, the RDFR interrupt request signal is asserted to request an interrupt service. 11818 * 0b1..If C2[RIE] and S1[RDRF] are set, the RDRF DMA request signal is asserted to request a DMA transfer. 11819 */ 11820 #define UART_C5_RDMAS(x) (((uint8_t)(((uint8_t)(x)) << UART_C5_RDMAS_SHIFT)) & UART_C5_RDMAS_MASK) 11821 #define UART_C5_TDMAS_MASK (0x80U) 11822 #define UART_C5_TDMAS_SHIFT (7U) 11823 /*! TDMAS - Transmitter DMA Select 11824 * 0b0..If C2[TIE] is set and the S1[TDRE] flag is set, the TDRE interrupt request signal is asserted to request interrupt service. 11825 * 0b1..If C2[TIE] is set and the S1[TDRE] flag is set, the TDRE DMA request signal is asserted to request a DMA transfer. 11826 */ 11827 #define UART_C5_TDMAS(x) (((uint8_t)(((uint8_t)(x)) << UART_C5_TDMAS_SHIFT)) & UART_C5_TDMAS_MASK) 11828 /*! @} */ 11829 11830 /*! @name ED - UART Extended Data Register */ 11831 /*! @{ */ 11832 #define UART_ED_PARITYE_MASK (0x40U) 11833 #define UART_ED_PARITYE_SHIFT (6U) 11834 /*! PARITYE 11835 * 0b0..The dataword was received without a parity error. 11836 * 0b1..The dataword was received with a parity error. 11837 */ 11838 #define UART_ED_PARITYE(x) (((uint8_t)(((uint8_t)(x)) << UART_ED_PARITYE_SHIFT)) & UART_ED_PARITYE_MASK) 11839 #define UART_ED_NOISY_MASK (0x80U) 11840 #define UART_ED_NOISY_SHIFT (7U) 11841 /*! NOISY 11842 * 0b0..The dataword was received without noise. 11843 * 0b1..The data was received with noise. 11844 */ 11845 #define UART_ED_NOISY(x) (((uint8_t)(((uint8_t)(x)) << UART_ED_NOISY_SHIFT)) & UART_ED_NOISY_MASK) 11846 /*! @} */ 11847 11848 /*! @name MODEM - UART Modem Register */ 11849 /*! @{ */ 11850 #define UART_MODEM_TXCTSE_MASK (0x1U) 11851 #define UART_MODEM_TXCTSE_SHIFT (0U) 11852 /*! TXCTSE - Transmitter clear-to-send enable 11853 * 0b0..CTS has no effect on the transmitter. 11854 * 0b1..Enables clear-to-send operation. The transmitter checks the state of CTS each time it is ready to send a character. If CTS is asserted, the character is sent. If CTS is deasserted, the signal TXD remains in the mark state and transmission is delayed until CTS is asserted. Changes in CTS as a character is being sent do not affect its transmission. 11855 */ 11856 #define UART_MODEM_TXCTSE(x) (((uint8_t)(((uint8_t)(x)) << UART_MODEM_TXCTSE_SHIFT)) & UART_MODEM_TXCTSE_MASK) 11857 #define UART_MODEM_TXRTSE_MASK (0x2U) 11858 #define UART_MODEM_TXRTSE_SHIFT (1U) 11859 /*! TXRTSE - Transmitter request-to-send enable 11860 * 0b0..The transmitter has no effect on RTS. 11861 * 0b1..When a character is placed into an empty transmitter data buffer , RTS asserts one bit time before the start bit is transmitted. RTS deasserts one bit time after all characters in the transmitter data buffer and shift register are completely sent, including the last stop bit. (FIFO) Ensure that C2[TE] is asserted before assertion of this bit. 11862 */ 11863 #define UART_MODEM_TXRTSE(x) (((uint8_t)(((uint8_t)(x)) << UART_MODEM_TXRTSE_SHIFT)) & UART_MODEM_TXRTSE_MASK) 11864 #define UART_MODEM_TXRTSPOL_MASK (0x4U) 11865 #define UART_MODEM_TXRTSPOL_SHIFT (2U) 11866 /*! TXRTSPOL - Transmitter request-to-send polarity 11867 * 0b0..Transmitter RTS is active low. 11868 * 0b1..Transmitter RTS is active high. 11869 */ 11870 #define UART_MODEM_TXRTSPOL(x) (((uint8_t)(((uint8_t)(x)) << UART_MODEM_TXRTSPOL_SHIFT)) & UART_MODEM_TXRTSPOL_MASK) 11871 #define UART_MODEM_RXRTSE_MASK (0x8U) 11872 #define UART_MODEM_RXRTSE_SHIFT (3U) 11873 /*! RXRTSE - Receiver request-to-send enable 11874 * 0b0..The receiver has no effect on RTS. 11875 * 0b1..RTS is deasserted if the number of characters in the receiver data register (FIFO) is equal to or greater than RWFIFO[RXWATER]. RTS is asserted when the number of characters in the receiver data register (FIFO) is less than RWFIFO[RXWATER]. See Hardware flow control 11876 */ 11877 #define UART_MODEM_RXRTSE(x) (((uint8_t)(((uint8_t)(x)) << UART_MODEM_RXRTSE_SHIFT)) & UART_MODEM_RXRTSE_MASK) 11878 /*! @} */ 11879 11880 /*! @name PFIFO - UART FIFO Parameters */ 11881 /*! @{ */ 11882 #define UART_PFIFO_RXFIFOSIZE_MASK (0x7U) 11883 #define UART_PFIFO_RXFIFOSIZE_SHIFT (0U) 11884 /*! RXFIFOSIZE - Receive FIFO. Buffer Depth 11885 * 0b000..Receive FIFO/Buffer depth = 1 dataword. 11886 * 0b001..Receive FIFO/Buffer depth = 4 datawords. 11887 * 0b010..Receive FIFO/Buffer depth = 8 datawords. 11888 * 0b011..Receive FIFO/Buffer depth = 16 datawords. 11889 * 0b100..Receive FIFO/Buffer depth = 32 datawords. 11890 * 0b101..Receive FIFO/Buffer depth = 64 datawords. 11891 * 0b110..Receive FIFO/Buffer depth = 128 datawords. 11892 * 0b111..Reserved. 11893 */ 11894 #define UART_PFIFO_RXFIFOSIZE(x) (((uint8_t)(((uint8_t)(x)) << UART_PFIFO_RXFIFOSIZE_SHIFT)) & UART_PFIFO_RXFIFOSIZE_MASK) 11895 #define UART_PFIFO_RXFE_MASK (0x8U) 11896 #define UART_PFIFO_RXFE_SHIFT (3U) 11897 /*! RXFE - Receive FIFO Enable 11898 * 0b0..Receive FIFO is not enabled. Buffer is depth 1. (Legacy support) 11899 * 0b1..Receive FIFO is enabled. Buffer is depth indicted by RXFIFOSIZE. 11900 */ 11901 #define UART_PFIFO_RXFE(x) (((uint8_t)(((uint8_t)(x)) << UART_PFIFO_RXFE_SHIFT)) & UART_PFIFO_RXFE_MASK) 11902 #define UART_PFIFO_TXFIFOSIZE_MASK (0x70U) 11903 #define UART_PFIFO_TXFIFOSIZE_SHIFT (4U) 11904 /*! TXFIFOSIZE - Transmit FIFO. Buffer Depth 11905 * 0b000..Transmit FIFO/Buffer depth = 1 dataword. 11906 * 0b001..Transmit FIFO/Buffer depth = 4 datawords. 11907 * 0b010..Transmit FIFO/Buffer depth = 8 datawords. 11908 * 0b011..Transmit FIFO/Buffer depth = 16 datawords. 11909 * 0b100..Transmit FIFO/Buffer depth = 32 datawords. 11910 * 0b101..Transmit FIFO/Buffer depth = 64 datawords. 11911 * 0b110..Transmit FIFO/Buffer depth = 128 datawords. 11912 * 0b111..Reserved. 11913 */ 11914 #define UART_PFIFO_TXFIFOSIZE(x) (((uint8_t)(((uint8_t)(x)) << UART_PFIFO_TXFIFOSIZE_SHIFT)) & UART_PFIFO_TXFIFOSIZE_MASK) 11915 #define UART_PFIFO_TXFE_MASK (0x80U) 11916 #define UART_PFIFO_TXFE_SHIFT (7U) 11917 /*! TXFE - Transmit FIFO Enable 11918 * 0b0..Transmit FIFO is not enabled. Buffer is depth 1. (Legacy support). 11919 * 0b1..Transmit FIFO is enabled. Buffer is depth indicated by TXFIFOSIZE. 11920 */ 11921 #define UART_PFIFO_TXFE(x) (((uint8_t)(((uint8_t)(x)) << UART_PFIFO_TXFE_SHIFT)) & UART_PFIFO_TXFE_MASK) 11922 /*! @} */ 11923 11924 /*! @name CFIFO - UART FIFO Control Register */ 11925 /*! @{ */ 11926 #define UART_CFIFO_RXUFE_MASK (0x1U) 11927 #define UART_CFIFO_RXUFE_SHIFT (0U) 11928 /*! RXUFE - Receive FIFO Underflow Interrupt Enable 11929 * 0b0..RXUF flag does not generate an interrupt to the host. 11930 * 0b1..RXUF flag generates an interrupt to the host. 11931 */ 11932 #define UART_CFIFO_RXUFE(x) (((uint8_t)(((uint8_t)(x)) << UART_CFIFO_RXUFE_SHIFT)) & UART_CFIFO_RXUFE_MASK) 11933 #define UART_CFIFO_TXOFE_MASK (0x2U) 11934 #define UART_CFIFO_TXOFE_SHIFT (1U) 11935 /*! TXOFE - Transmit FIFO Overflow Interrupt Enable 11936 * 0b0..TXOF flag does not generate an interrupt to the host. 11937 * 0b1..TXOF flag generates an interrupt to the host. 11938 */ 11939 #define UART_CFIFO_TXOFE(x) (((uint8_t)(((uint8_t)(x)) << UART_CFIFO_TXOFE_SHIFT)) & UART_CFIFO_TXOFE_MASK) 11940 #define UART_CFIFO_RXOFE_MASK (0x4U) 11941 #define UART_CFIFO_RXOFE_SHIFT (2U) 11942 /*! RXOFE - Receive FIFO Overflow Interrupt Enable 11943 * 0b0..RXOF flag does not generate an interrupt to the host. 11944 * 0b1..RXOF flag generates an interrupt to the host. 11945 */ 11946 #define UART_CFIFO_RXOFE(x) (((uint8_t)(((uint8_t)(x)) << UART_CFIFO_RXOFE_SHIFT)) & UART_CFIFO_RXOFE_MASK) 11947 #define UART_CFIFO_RXFLUSH_MASK (0x40U) 11948 #define UART_CFIFO_RXFLUSH_SHIFT (6U) 11949 /*! RXFLUSH - Receive FIFO/Buffer Flush 11950 * 0b0..No flush operation occurs. 11951 * 0b1..All data in the receive FIFO/buffer is cleared out. 11952 */ 11953 #define UART_CFIFO_RXFLUSH(x) (((uint8_t)(((uint8_t)(x)) << UART_CFIFO_RXFLUSH_SHIFT)) & UART_CFIFO_RXFLUSH_MASK) 11954 #define UART_CFIFO_TXFLUSH_MASK (0x80U) 11955 #define UART_CFIFO_TXFLUSH_SHIFT (7U) 11956 /*! TXFLUSH - Transmit FIFO/Buffer Flush 11957 * 0b0..No flush operation occurs. 11958 * 0b1..All data in the transmit FIFO/Buffer is cleared out. 11959 */ 11960 #define UART_CFIFO_TXFLUSH(x) (((uint8_t)(((uint8_t)(x)) << UART_CFIFO_TXFLUSH_SHIFT)) & UART_CFIFO_TXFLUSH_MASK) 11961 /*! @} */ 11962 11963 /*! @name SFIFO - UART FIFO Status Register */ 11964 /*! @{ */ 11965 #define UART_SFIFO_RXUF_MASK (0x1U) 11966 #define UART_SFIFO_RXUF_SHIFT (0U) 11967 /*! RXUF - Receiver Buffer Underflow Flag 11968 * 0b0..No receive buffer underflow has occurred since the last time the flag was cleared. 11969 * 0b1..At least one receive buffer underflow has occurred since the last time the flag was cleared. 11970 */ 11971 #define UART_SFIFO_RXUF(x) (((uint8_t)(((uint8_t)(x)) << UART_SFIFO_RXUF_SHIFT)) & UART_SFIFO_RXUF_MASK) 11972 #define UART_SFIFO_TXOF_MASK (0x2U) 11973 #define UART_SFIFO_TXOF_SHIFT (1U) 11974 /*! TXOF - Transmitter Buffer Overflow Flag 11975 * 0b0..No transmit buffer overflow has occurred since the last time the flag was cleared. 11976 * 0b1..At least one transmit buffer overflow has occurred since the last time the flag was cleared. 11977 */ 11978 #define UART_SFIFO_TXOF(x) (((uint8_t)(((uint8_t)(x)) << UART_SFIFO_TXOF_SHIFT)) & UART_SFIFO_TXOF_MASK) 11979 #define UART_SFIFO_RXOF_MASK (0x4U) 11980 #define UART_SFIFO_RXOF_SHIFT (2U) 11981 /*! RXOF - Receiver Buffer Overflow Flag 11982 * 0b0..No receive buffer overflow has occurred since the last time the flag was cleared. 11983 * 0b1..At least one receive buffer overflow has occurred since the last time the flag was cleared. 11984 */ 11985 #define UART_SFIFO_RXOF(x) (((uint8_t)(((uint8_t)(x)) << UART_SFIFO_RXOF_SHIFT)) & UART_SFIFO_RXOF_MASK) 11986 #define UART_SFIFO_RXEMPT_MASK (0x40U) 11987 #define UART_SFIFO_RXEMPT_SHIFT (6U) 11988 /*! RXEMPT - Receive Buffer/FIFO Empty 11989 * 0b0..Receive buffer is not empty. 11990 * 0b1..Receive buffer is empty. 11991 */ 11992 #define UART_SFIFO_RXEMPT(x) (((uint8_t)(((uint8_t)(x)) << UART_SFIFO_RXEMPT_SHIFT)) & UART_SFIFO_RXEMPT_MASK) 11993 #define UART_SFIFO_TXEMPT_MASK (0x80U) 11994 #define UART_SFIFO_TXEMPT_SHIFT (7U) 11995 /*! TXEMPT - Transmit Buffer/FIFO Empty 11996 * 0b0..Transmit buffer is not empty. 11997 * 0b1..Transmit buffer is empty. 11998 */ 11999 #define UART_SFIFO_TXEMPT(x) (((uint8_t)(((uint8_t)(x)) << UART_SFIFO_TXEMPT_SHIFT)) & UART_SFIFO_TXEMPT_MASK) 12000 /*! @} */ 12001 12002 /*! @name TWFIFO - UART FIFO Transmit Watermark */ 12003 /*! @{ */ 12004 #define UART_TWFIFO_TXWATER_MASK (0xFFU) 12005 #define UART_TWFIFO_TXWATER_SHIFT (0U) 12006 #define UART_TWFIFO_TXWATER(x) (((uint8_t)(((uint8_t)(x)) << UART_TWFIFO_TXWATER_SHIFT)) & UART_TWFIFO_TXWATER_MASK) 12007 /*! @} */ 12008 12009 /*! @name TCFIFO - UART FIFO Transmit Count */ 12010 /*! @{ */ 12011 #define UART_TCFIFO_TXCOUNT_MASK (0xFFU) 12012 #define UART_TCFIFO_TXCOUNT_SHIFT (0U) 12013 #define UART_TCFIFO_TXCOUNT(x) (((uint8_t)(((uint8_t)(x)) << UART_TCFIFO_TXCOUNT_SHIFT)) & UART_TCFIFO_TXCOUNT_MASK) 12014 /*! @} */ 12015 12016 /*! @name RWFIFO - UART FIFO Receive Watermark */ 12017 /*! @{ */ 12018 #define UART_RWFIFO_RXWATER_MASK (0xFFU) 12019 #define UART_RWFIFO_RXWATER_SHIFT (0U) 12020 #define UART_RWFIFO_RXWATER(x) (((uint8_t)(((uint8_t)(x)) << UART_RWFIFO_RXWATER_SHIFT)) & UART_RWFIFO_RXWATER_MASK) 12021 /*! @} */ 12022 12023 /*! @name RCFIFO - UART FIFO Receive Count */ 12024 /*! @{ */ 12025 #define UART_RCFIFO_RXCOUNT_MASK (0xFFU) 12026 #define UART_RCFIFO_RXCOUNT_SHIFT (0U) 12027 #define UART_RCFIFO_RXCOUNT(x) (((uint8_t)(((uint8_t)(x)) << UART_RCFIFO_RXCOUNT_SHIFT)) & UART_RCFIFO_RXCOUNT_MASK) 12028 /*! @} */ 12029 12030 12031 /*! 12032 * @} 12033 */ /* end of group UART_Register_Masks */ 12034 12035 12036 /* UART - Peripheral instance base addresses */ 12037 /** Peripheral UART0 base address */ 12038 #define UART0_BASE (0x4006A000u) 12039 /** Peripheral UART0 base pointer */ 12040 #define UART0 ((UART_Type *)UART0_BASE) 12041 /** Peripheral UART1 base address */ 12042 #define UART1_BASE (0x4006B000u) 12043 /** Peripheral UART1 base pointer */ 12044 #define UART1 ((UART_Type *)UART1_BASE) 12045 /** Array initializer of UART peripheral base addresses */ 12046 #define UART_BASE_ADDRS { UART0_BASE, UART1_BASE } 12047 /** Array initializer of UART peripheral base pointers */ 12048 #define UART_BASE_PTRS { UART0, UART1 } 12049 /** Interrupt vectors for the UART peripheral type */ 12050 #define UART_RX_TX_IRQS { UART0_IRQn, UART1_IRQn } 12051 #define UART_ERR_IRQS { UART0_IRQn, UART1_IRQn } 12052 #define UART_LON_IRQS { UART0_IRQn, NotAvail_IRQn } 12053 12054 /*! 12055 * @} 12056 */ /* end of group UART_Peripheral_Access_Layer */ 12057 12058 12059 /* ---------------------------------------------------------------------------- 12060 -- WDOG Peripheral Access Layer 12061 ---------------------------------------------------------------------------- */ 12062 12063 /*! 12064 * @addtogroup WDOG_Peripheral_Access_Layer WDOG Peripheral Access Layer 12065 * @{ 12066 */ 12067 12068 /** WDOG - Register Layout Typedef */ 12069 typedef struct { 12070 __IO uint16_t STCTRLH; /**< Watchdog Status and Control Register High, offset: 0x0 */ 12071 __IO uint16_t STCTRLL; /**< Watchdog Status and Control Register Low, offset: 0x2 */ 12072 __IO uint16_t TOVALH; /**< Watchdog Time-out Value Register High, offset: 0x4 */ 12073 __IO uint16_t TOVALL; /**< Watchdog Time-out Value Register Low, offset: 0x6 */ 12074 __IO uint16_t WINH; /**< Watchdog Window Register High, offset: 0x8 */ 12075 __IO uint16_t WINL; /**< Watchdog Window Register Low, offset: 0xA */ 12076 __IO uint16_t REFRESH; /**< Watchdog Refresh register, offset: 0xC */ 12077 __IO uint16_t UNLOCK; /**< Watchdog Unlock register, offset: 0xE */ 12078 __IO uint16_t TMROUTH; /**< Watchdog Timer Output Register High, offset: 0x10 */ 12079 __IO uint16_t TMROUTL; /**< Watchdog Timer Output Register Low, offset: 0x12 */ 12080 __IO uint16_t RSTCNT; /**< Watchdog Reset Count register, offset: 0x14 */ 12081 __IO uint16_t PRESC; /**< Watchdog Prescaler register, offset: 0x16 */ 12082 } WDOG_Type; 12083 12084 /* ---------------------------------------------------------------------------- 12085 -- WDOG Register Masks 12086 ---------------------------------------------------------------------------- */ 12087 12088 /*! 12089 * @addtogroup WDOG_Register_Masks WDOG Register Masks 12090 * @{ 12091 */ 12092 12093 /*! @name STCTRLH - Watchdog Status and Control Register High */ 12094 /*! @{ */ 12095 #define WDOG_STCTRLH_WDOGEN_MASK (0x1U) 12096 #define WDOG_STCTRLH_WDOGEN_SHIFT (0U) 12097 /*! WDOGEN 12098 * 0b0..WDOG is disabled. 12099 * 0b1..WDOG is enabled. 12100 */ 12101 #define WDOG_STCTRLH_WDOGEN(x) (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_WDOGEN_SHIFT)) & WDOG_STCTRLH_WDOGEN_MASK) 12102 #define WDOG_STCTRLH_CLKSRC_MASK (0x2U) 12103 #define WDOG_STCTRLH_CLKSRC_SHIFT (1U) 12104 /*! CLKSRC 12105 * 0b0..WDOG clock sourced from LPO . 12106 * 0b1..WDOG clock sourced from alternate clock source. 12107 */ 12108 #define WDOG_STCTRLH_CLKSRC(x) (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_CLKSRC_SHIFT)) & WDOG_STCTRLH_CLKSRC_MASK) 12109 #define WDOG_STCTRLH_IRQRSTEN_MASK (0x4U) 12110 #define WDOG_STCTRLH_IRQRSTEN_SHIFT (2U) 12111 /*! IRQRSTEN 12112 * 0b0..WDOG time-out generates reset only. 12113 * 0b1..WDOG time-out initially generates an interrupt. After WCT, it generates a reset. 12114 */ 12115 #define WDOG_STCTRLH_IRQRSTEN(x) (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_IRQRSTEN_SHIFT)) & WDOG_STCTRLH_IRQRSTEN_MASK) 12116 #define WDOG_STCTRLH_WINEN_MASK (0x8U) 12117 #define WDOG_STCTRLH_WINEN_SHIFT (3U) 12118 /*! WINEN 12119 * 0b0..Windowing mode is disabled. 12120 * 0b1..Windowing mode is enabled. 12121 */ 12122 #define WDOG_STCTRLH_WINEN(x) (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_WINEN_SHIFT)) & WDOG_STCTRLH_WINEN_MASK) 12123 #define WDOG_STCTRLH_ALLOWUPDATE_MASK (0x10U) 12124 #define WDOG_STCTRLH_ALLOWUPDATE_SHIFT (4U) 12125 /*! ALLOWUPDATE 12126 * 0b0..No further updates allowed to WDOG write-once registers. 12127 * 0b1..WDOG write-once registers can be unlocked for updating. 12128 */ 12129 #define WDOG_STCTRLH_ALLOWUPDATE(x) (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_ALLOWUPDATE_SHIFT)) & WDOG_STCTRLH_ALLOWUPDATE_MASK) 12130 #define WDOG_STCTRLH_DBGEN_MASK (0x20U) 12131 #define WDOG_STCTRLH_DBGEN_SHIFT (5U) 12132 /*! DBGEN 12133 * 0b0..WDOG is disabled in CPU Debug mode. 12134 * 0b1..WDOG is enabled in CPU Debug mode. 12135 */ 12136 #define WDOG_STCTRLH_DBGEN(x) (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_DBGEN_SHIFT)) & WDOG_STCTRLH_DBGEN_MASK) 12137 #define WDOG_STCTRLH_STOPEN_MASK (0x40U) 12138 #define WDOG_STCTRLH_STOPEN_SHIFT (6U) 12139 /*! STOPEN 12140 * 0b0..WDOG is disabled in CPU Stop mode. 12141 * 0b1..WDOG is enabled in CPU Stop mode. 12142 */ 12143 #define WDOG_STCTRLH_STOPEN(x) (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_STOPEN_SHIFT)) & WDOG_STCTRLH_STOPEN_MASK) 12144 #define WDOG_STCTRLH_WAITEN_MASK (0x80U) 12145 #define WDOG_STCTRLH_WAITEN_SHIFT (7U) 12146 /*! WAITEN 12147 * 0b0..WDOG is disabled in CPU Wait mode. 12148 * 0b1..WDOG is enabled in CPU Wait mode. 12149 */ 12150 #define WDOG_STCTRLH_WAITEN(x) (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_WAITEN_SHIFT)) & WDOG_STCTRLH_WAITEN_MASK) 12151 #define WDOG_STCTRLH_TESTWDOG_MASK (0x400U) 12152 #define WDOG_STCTRLH_TESTWDOG_SHIFT (10U) 12153 #define WDOG_STCTRLH_TESTWDOG(x) (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_TESTWDOG_SHIFT)) & WDOG_STCTRLH_TESTWDOG_MASK) 12154 #define WDOG_STCTRLH_TESTSEL_MASK (0x800U) 12155 #define WDOG_STCTRLH_TESTSEL_SHIFT (11U) 12156 /*! TESTSEL 12157 * 0b0..Quick test. The timer runs in normal operation. You can load a small time-out value to do a quick test. 12158 * 0b1..Byte test. Puts the timer in the byte test mode where individual bytes of the timer are enabled for operation and are compared for time-out against the corresponding byte of the programmed time-out value. Select the byte through BYTESEL[1:0] for testing. 12159 */ 12160 #define WDOG_STCTRLH_TESTSEL(x) (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_TESTSEL_SHIFT)) & WDOG_STCTRLH_TESTSEL_MASK) 12161 #define WDOG_STCTRLH_BYTESEL_MASK (0x3000U) 12162 #define WDOG_STCTRLH_BYTESEL_SHIFT (12U) 12163 /*! BYTESEL 12164 * 0b00..Byte 0 selected 12165 * 0b01..Byte 1 selected 12166 * 0b10..Byte 2 selected 12167 * 0b11..Byte 3 selected 12168 */ 12169 #define WDOG_STCTRLH_BYTESEL(x) (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_BYTESEL_SHIFT)) & WDOG_STCTRLH_BYTESEL_MASK) 12170 #define WDOG_STCTRLH_DISTESTWDOG_MASK (0x4000U) 12171 #define WDOG_STCTRLH_DISTESTWDOG_SHIFT (14U) 12172 /*! DISTESTWDOG 12173 * 0b0..WDOG functional test mode is not disabled. 12174 * 0b1..WDOG functional test mode is disabled permanently until reset. 12175 */ 12176 #define WDOG_STCTRLH_DISTESTWDOG(x) (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_DISTESTWDOG_SHIFT)) & WDOG_STCTRLH_DISTESTWDOG_MASK) 12177 /*! @} */ 12178 12179 /*! @name STCTRLL - Watchdog Status and Control Register Low */ 12180 /*! @{ */ 12181 #define WDOG_STCTRLL_INTFLG_MASK (0x8000U) 12182 #define WDOG_STCTRLL_INTFLG_SHIFT (15U) 12183 #define WDOG_STCTRLL_INTFLG(x) (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLL_INTFLG_SHIFT)) & WDOG_STCTRLL_INTFLG_MASK) 12184 /*! @} */ 12185 12186 /*! @name TOVALH - Watchdog Time-out Value Register High */ 12187 /*! @{ */ 12188 #define WDOG_TOVALH_TOVALHIGH_MASK (0xFFFFU) 12189 #define WDOG_TOVALH_TOVALHIGH_SHIFT (0U) 12190 #define WDOG_TOVALH_TOVALHIGH(x) (((uint16_t)(((uint16_t)(x)) << WDOG_TOVALH_TOVALHIGH_SHIFT)) & WDOG_TOVALH_TOVALHIGH_MASK) 12191 /*! @} */ 12192 12193 /*! @name TOVALL - Watchdog Time-out Value Register Low */ 12194 /*! @{ */ 12195 #define WDOG_TOVALL_TOVALLOW_MASK (0xFFFFU) 12196 #define WDOG_TOVALL_TOVALLOW_SHIFT (0U) 12197 #define WDOG_TOVALL_TOVALLOW(x) (((uint16_t)(((uint16_t)(x)) << WDOG_TOVALL_TOVALLOW_SHIFT)) & WDOG_TOVALL_TOVALLOW_MASK) 12198 /*! @} */ 12199 12200 /*! @name WINH - Watchdog Window Register High */ 12201 /*! @{ */ 12202 #define WDOG_WINH_WINHIGH_MASK (0xFFFFU) 12203 #define WDOG_WINH_WINHIGH_SHIFT (0U) 12204 #define WDOG_WINH_WINHIGH(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WINH_WINHIGH_SHIFT)) & WDOG_WINH_WINHIGH_MASK) 12205 /*! @} */ 12206 12207 /*! @name WINL - Watchdog Window Register Low */ 12208 /*! @{ */ 12209 #define WDOG_WINL_WINLOW_MASK (0xFFFFU) 12210 #define WDOG_WINL_WINLOW_SHIFT (0U) 12211 #define WDOG_WINL_WINLOW(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WINL_WINLOW_SHIFT)) & WDOG_WINL_WINLOW_MASK) 12212 /*! @} */ 12213 12214 /*! @name REFRESH - Watchdog Refresh register */ 12215 /*! @{ */ 12216 #define WDOG_REFRESH_WDOGREFRESH_MASK (0xFFFFU) 12217 #define WDOG_REFRESH_WDOGREFRESH_SHIFT (0U) 12218 #define WDOG_REFRESH_WDOGREFRESH(x) (((uint16_t)(((uint16_t)(x)) << WDOG_REFRESH_WDOGREFRESH_SHIFT)) & WDOG_REFRESH_WDOGREFRESH_MASK) 12219 /*! @} */ 12220 12221 /*! @name UNLOCK - Watchdog Unlock register */ 12222 /*! @{ */ 12223 #define WDOG_UNLOCK_WDOGUNLOCK_MASK (0xFFFFU) 12224 #define WDOG_UNLOCK_WDOGUNLOCK_SHIFT (0U) 12225 #define WDOG_UNLOCK_WDOGUNLOCK(x) (((uint16_t)(((uint16_t)(x)) << WDOG_UNLOCK_WDOGUNLOCK_SHIFT)) & WDOG_UNLOCK_WDOGUNLOCK_MASK) 12226 /*! @} */ 12227 12228 /*! @name TMROUTH - Watchdog Timer Output Register High */ 12229 /*! @{ */ 12230 #define WDOG_TMROUTH_TIMEROUTHIGH_MASK (0xFFFFU) 12231 #define WDOG_TMROUTH_TIMEROUTHIGH_SHIFT (0U) 12232 #define WDOG_TMROUTH_TIMEROUTHIGH(x) (((uint16_t)(((uint16_t)(x)) << WDOG_TMROUTH_TIMEROUTHIGH_SHIFT)) & WDOG_TMROUTH_TIMEROUTHIGH_MASK) 12233 /*! @} */ 12234 12235 /*! @name TMROUTL - Watchdog Timer Output Register Low */ 12236 /*! @{ */ 12237 #define WDOG_TMROUTL_TIMEROUTLOW_MASK (0xFFFFU) 12238 #define WDOG_TMROUTL_TIMEROUTLOW_SHIFT (0U) 12239 #define WDOG_TMROUTL_TIMEROUTLOW(x) (((uint16_t)(((uint16_t)(x)) << WDOG_TMROUTL_TIMEROUTLOW_SHIFT)) & WDOG_TMROUTL_TIMEROUTLOW_MASK) 12240 /*! @} */ 12241 12242 /*! @name RSTCNT - Watchdog Reset Count register */ 12243 /*! @{ */ 12244 #define WDOG_RSTCNT_RSTCNT_MASK (0xFFFFU) 12245 #define WDOG_RSTCNT_RSTCNT_SHIFT (0U) 12246 #define WDOG_RSTCNT_RSTCNT(x) (((uint16_t)(((uint16_t)(x)) << WDOG_RSTCNT_RSTCNT_SHIFT)) & WDOG_RSTCNT_RSTCNT_MASK) 12247 /*! @} */ 12248 12249 /*! @name PRESC - Watchdog Prescaler register */ 12250 /*! @{ */ 12251 #define WDOG_PRESC_PRESCVAL_MASK (0x700U) 12252 #define WDOG_PRESC_PRESCVAL_SHIFT (8U) 12253 #define WDOG_PRESC_PRESCVAL(x) (((uint16_t)(((uint16_t)(x)) << WDOG_PRESC_PRESCVAL_SHIFT)) & WDOG_PRESC_PRESCVAL_MASK) 12254 /*! @} */ 12255 12256 12257 /*! 12258 * @} 12259 */ /* end of group WDOG_Register_Masks */ 12260 12261 12262 /* WDOG - Peripheral instance base addresses */ 12263 /** Peripheral WDOG base address */ 12264 #define WDOG_BASE (0x40052000u) 12265 /** Peripheral WDOG base pointer */ 12266 #define WDOG ((WDOG_Type *)WDOG_BASE) 12267 /** Array initializer of WDOG peripheral base addresses */ 12268 #define WDOG_BASE_ADDRS { WDOG_BASE } 12269 /** Array initializer of WDOG peripheral base pointers */ 12270 #define WDOG_BASE_PTRS { WDOG } 12271 /** Interrupt vectors for the WDOG peripheral type */ 12272 #define WDOG_IRQS { WDOG_EWM_IRQn } 12273 12274 /*! 12275 * @} 12276 */ /* end of group WDOG_Peripheral_Access_Layer */ 12277 12278 12279 /* 12280 ** End of section using anonymous unions 12281 */ 12282 12283 #if defined(__ARMCC_VERSION) 12284 #if (__ARMCC_VERSION >= 6010050) 12285 #pragma clang diagnostic pop 12286 #else 12287 #pragma pop 12288 #endif 12289 #elif defined(__CWCC__) 12290 #pragma pop 12291 #elif defined(__GNUC__) 12292 /* leave anonymous unions enabled */ 12293 #elif defined(__IAR_SYSTEMS_ICC__) 12294 #pragma language=default 12295 #else 12296 #error Not supported compiler type 12297 #endif 12298 12299 /*! 12300 * @} 12301 */ /* end of group Peripheral_access_layer */ 12302 12303 12304 /* ---------------------------------------------------------------------------- 12305 -- Macros for use with bit field definitions (xxx_SHIFT, xxx_MASK). 12306 ---------------------------------------------------------------------------- */ 12307 12308 /*! 12309 * @addtogroup Bit_Field_Generic_Macros Macros for use with bit field definitions (xxx_SHIFT, xxx_MASK). 12310 * @{ 12311 */ 12312 12313 #if defined(__ARMCC_VERSION) 12314 #if (__ARMCC_VERSION >= 6010050) 12315 #pragma clang system_header 12316 #endif 12317 #elif defined(__IAR_SYSTEMS_ICC__) 12318 #pragma system_include 12319 #endif 12320 12321 /** 12322 * @brief Mask and left-shift a bit field value for use in a register bit range. 12323 * @param field Name of the register bit field. 12324 * @param value Value of the bit field. 12325 * @return Masked and shifted value. 12326 */ 12327 #define NXP_VAL2FLD(field, value) (((value) << (field ## _SHIFT)) & (field ## _MASK)) 12328 /** 12329 * @brief Mask and right-shift a register value to extract a bit field value. 12330 * @param field Name of the register bit field. 12331 * @param value Value of the register. 12332 * @return Masked and shifted bit field value. 12333 */ 12334 #define NXP_FLD2VAL(field, value) (((value) & (field ## _MASK)) >> (field ## _SHIFT)) 12335 12336 /*! 12337 * @} 12338 */ /* end of group Bit_Field_Generic_Macros */ 12339 12340 12341 /* ---------------------------------------------------------------------------- 12342 -- SDK Compatibility 12343 ---------------------------------------------------------------------------- */ 12344 12345 /*! 12346 * @addtogroup SDK_Compatibility_Symbols SDK Compatibility 12347 * @{ 12348 */ 12349 12350 #define ADC_PGA_PGAOFSM_MASK This_symbol_has_been_deprecated 12351 #define ADC_PGA_PGAOFSM_SHIFT This_symbol_has_been_deprecated 12352 #define ADC_PGA_PGAG_MASK This_symbol_has_been_deprecated 12353 #define ADC_PGA_PGAG_SHIFT This_symbol_has_been_deprecated 12354 #define ADC_PGA_PGAG(x) This_symbol_has_been_deprecated 12355 #define ADC_PGA_PGALPb_MASK This_symbol_has_been_deprecated 12356 #define ADC_PGA_PGALPb_SHIFT This_symbol_has_been_deprecated 12357 #define ADC_PGA_PGACHPb_MASK This_symbol_has_been_deprecated 12358 #define ADC_PGA_PGACHPb_SHIFT This_symbol_has_been_deprecated 12359 #define ADC_PGA_PGAEN_MASK This_symbol_has_been_deprecated 12360 #define ADC_PGA_PGAEN_SHIFT This_symbol_has_been_deprecated 12361 #define UART_C6_CP_MASK This_symbol_has_been_deprecated 12362 #define UART_C6_CP_SHIFT This_symbol_has_been_deprecated 12363 #define UART_C6_CE_MASK This_symbol_has_been_deprecated 12364 #define UART_C6_CE_SHIFT This_symbol_has_been_deprecated 12365 #define UART_C6_TX709_MASK This_symbol_has_been_deprecated 12366 #define UART_C6_TX709_SHIFT This_symbol_has_been_deprecated 12367 #define UART_C6_EN709_MASK This_symbol_has_been_deprecated 12368 #define UART_C6_EN709_SHIFT This_symbol_has_been_deprecated 12369 #define UART_PCTH_PCTH_MASK This_symbol_has_been_deprecated 12370 #define UART_PCTH_PCTH_SHIFT This_symbol_has_been_deprecated 12371 #define UART_PCTH_PCTH(x) This_symbol_has_been_deprecated 12372 #define UART_PCTL_PCTL_MASK This_symbol_has_been_deprecated 12373 #define UART_PCTL_PCTL_SHIFT This_symbol_has_been_deprecated 12374 #define UART_PCTL_PCTL(x) This_symbol_has_been_deprecated 12375 #define UART_IE0_CPTXIE_MASK This_symbol_has_been_deprecated 12376 #define UART_IE0_CPTXIE_SHIFT This_symbol_has_been_deprecated 12377 #define UART_IE0_CTXDIE_MASK This_symbol_has_been_deprecated 12378 #define UART_IE0_CTXDIE_SHIFT This_symbol_has_been_deprecated 12379 #define UART_IE0_RPLOFIE_MASK This_symbol_has_been_deprecated 12380 #define UART_IE0_RPLOFIE_SHIFT This_symbol_has_been_deprecated 12381 #define UART_SDTH_SDTH_MASK This_symbol_has_been_deprecated 12382 #define UART_SDTH_SDTH_SHIFT This_symbol_has_been_deprecated 12383 #define UART_SDTH_SDTH(x) This_symbol_has_been_deprecated 12384 #define UART_SDTL_SDTL_MASK This_symbol_has_been_deprecated 12385 #define UART_SDTL_SDTL_SHIFT This_symbol_has_been_deprecated 12386 #define UART_SDTL_SDTL(x) This_symbol_has_been_deprecated 12387 #define UART_PRE_PREAMBLE_MASK This_symbol_has_been_deprecated 12388 #define UART_PRE_PREAMBLE_SHIFT This_symbol_has_been_deprecated 12389 #define UART_PRE_PREAMBLE(x) This_symbol_has_been_deprecated 12390 #define UART_TPL_TPL_MASK This_symbol_has_been_deprecated 12391 #define UART_TPL_TPL_SHIFT This_symbol_has_been_deprecated 12392 #define UART_TPL_TPL(x) This_symbol_has_been_deprecated 12393 #define UART_IE_TXDIE_MASK This_symbol_has_been_deprecated 12394 #define UART_IE_TXDIE_SHIFT This_symbol_has_been_deprecated 12395 #define UART_IE_PSIE_MASK This_symbol_has_been_deprecated 12396 #define UART_IE_PSIE_SHIFT This_symbol_has_been_deprecated 12397 #define UART_IE_PCTEIE_MASK This_symbol_has_been_deprecated 12398 #define UART_IE_PCTEIE_SHIFT This_symbol_has_been_deprecated 12399 #define UART_IE_PTXIE_MASK This_symbol_has_been_deprecated 12400 #define UART_IE_PTXIE_SHIFT This_symbol_has_been_deprecated 12401 #define UART_IE_PRXIE_MASK This_symbol_has_been_deprecated 12402 #define UART_IE_PRXIE_SHIFT This_symbol_has_been_deprecated 12403 #define UART_IE_ISDIE_MASK This_symbol_has_been_deprecated 12404 #define UART_IE_ISDIE_SHIFT This_symbol_has_been_deprecated 12405 #define UART_IE_WBEIE_MASK This_symbol_has_been_deprecated 12406 #define UART_IE_WBEIE_SHIFT This_symbol_has_been_deprecated 12407 #define UART_IE_PEIE_MASK This_symbol_has_been_deprecated 12408 #define UART_IE_PEIE_SHIFT This_symbol_has_been_deprecated 12409 #define UART_WB_WBASE_MASK This_symbol_has_been_deprecated 12410 #define UART_WB_WBASE_SHIFT This_symbol_has_been_deprecated 12411 #define UART_WB_WBASE(x) This_symbol_has_been_deprecated 12412 #define UART_S3_TXFF_MASK This_symbol_has_been_deprecated 12413 #define UART_S3_TXFF_SHIFT This_symbol_has_been_deprecated 12414 #define UART_S3_PSF_MASK This_symbol_has_been_deprecated 12415 #define UART_S3_PSF_SHIFT This_symbol_has_been_deprecated 12416 #define UART_S3_PCTEF_MASK This_symbol_has_been_deprecated 12417 #define UART_S3_PCTEF_SHIFT This_symbol_has_been_deprecated 12418 #define UART_S3_PTXF_MASK This_symbol_has_been_deprecated 12419 #define UART_S3_PTXF_SHIFT This_symbol_has_been_deprecated 12420 #define UART_S3_PRXF_MASK This_symbol_has_been_deprecated 12421 #define UART_S3_PRXF_SHIFT This_symbol_has_been_deprecated 12422 #define UART_S3_ISD_MASK This_symbol_has_been_deprecated 12423 #define UART_S3_ISD_SHIFT This_symbol_has_been_deprecated 12424 #define UART_S3_WBEF_MASK This_symbol_has_been_deprecated 12425 #define UART_S3_WBEF_SHIFT This_symbol_has_been_deprecated 12426 #define UART_S3_PEF_MASK This_symbol_has_been_deprecated 12427 #define UART_S3_PEF_SHIFT This_symbol_has_been_deprecated 12428 #define UART_S4_FE_MASK This_symbol_has_been_deprecated 12429 #define UART_S4_FE_SHIFT This_symbol_has_been_deprecated 12430 #define UART_S4_TXDF_MASK This_symbol_has_been_deprecated 12431 #define UART_S4_TXDF_SHIFT This_symbol_has_been_deprecated 12432 #define UART_S4_CDET_MASK This_symbol_has_been_deprecated 12433 #define UART_S4_CDET_SHIFT This_symbol_has_been_deprecated 12434 #define UART_S4_CDET(x) This_symbol_has_been_deprecated 12435 #define UART_S4_RPLOF_MASK This_symbol_has_been_deprecated 12436 #define UART_S4_RPLOF_SHIFT This_symbol_has_been_deprecated 12437 #define UART_S4_LNF_MASK This_symbol_has_been_deprecated 12438 #define UART_S4_LNF_SHIFT This_symbol_has_been_deprecated 12439 #define UART_RPL_RPL_MASK This_symbol_has_been_deprecated 12440 #define UART_RPL_RPL_SHIFT This_symbol_has_been_deprecated 12441 #define UART_RPL_RPL(x) This_symbol_has_been_deprecated 12442 #define UART_RPREL_RPREL_MASK This_symbol_has_been_deprecated 12443 #define UART_RPREL_RPREL_SHIFT This_symbol_has_been_deprecated 12444 #define UART_RPREL_RPREL(x) This_symbol_has_been_deprecated 12445 #define UART_CPW_CPW_MASK This_symbol_has_been_deprecated 12446 #define UART_CPW_CPW_SHIFT This_symbol_has_been_deprecated 12447 #define UART_CPW_CPW(x) This_symbol_has_been_deprecated 12448 #define UART_RIDTH_RIDTH_MASK This_symbol_has_been_deprecated 12449 #define UART_RIDTH_RIDTH_SHIFT This_symbol_has_been_deprecated 12450 #define UART_RIDTH_RIDTH(x) This_symbol_has_been_deprecated 12451 #define UART_RIDTL_RIDTL_MASK This_symbol_has_been_deprecated 12452 #define UART_RIDTL_RIDTL_SHIFT This_symbol_has_been_deprecated 12453 #define UART_RIDTL_RIDTL(x) This_symbol_has_been_deprecated 12454 #define UART_TIDTH_TIDTH_MASK This_symbol_has_been_deprecated 12455 #define UART_TIDTH_TIDTH_SHIFT This_symbol_has_been_deprecated 12456 #define UART_TIDTH_TIDTH(x) This_symbol_has_been_deprecated 12457 #define UART_TIDTL_TIDTL_MASK This_symbol_has_been_deprecated 12458 #define UART_TIDTL_TIDTL_SHIFT This_symbol_has_been_deprecated 12459 #define UART_TIDTL_TIDTL(x) This_symbol_has_been_deprecated 12460 #define UART_RB1TH_RB1TH_MASK This_symbol_has_been_deprecated 12461 #define UART_RB1TH_RB1TH_SHIFT This_symbol_has_been_deprecated 12462 #define UART_RB1TH_RB1TH(x) This_symbol_has_been_deprecated 12463 #define UART_RB1TL_RB1TL_MASK This_symbol_has_been_deprecated 12464 #define UART_RB1TL_RB1TL_SHIFT This_symbol_has_been_deprecated 12465 #define UART_RB1TL_RB1TL(x) This_symbol_has_been_deprecated 12466 #define UART_TB1TH_TB1TH_MASK This_symbol_has_been_deprecated 12467 #define UART_TB1TH_TB1TH_SHIFT This_symbol_has_been_deprecated 12468 #define UART_TB1TH_TB1TH(x) This_symbol_has_been_deprecated 12469 #define UART_TB1TL_TB1TL_MASK This_symbol_has_been_deprecated 12470 #define UART_TB1TL_TB1TL_SHIFT This_symbol_has_been_deprecated 12471 #define UART_TB1TL_TB1TL(x) This_symbol_has_been_deprecated 12472 #define UART_PROG_REG_MIN_DMC1_MASK This_symbol_has_been_deprecated 12473 #define UART_PROG_REG_MIN_DMC1_SHIFT This_symbol_has_been_deprecated 12474 #define UART_PROG_REG_MIN_DMC1(x) This_symbol_has_been_deprecated 12475 #define UART_PROG_REG_LCV_LEN_MASK This_symbol_has_been_deprecated 12476 #define UART_PROG_REG_LCV_LEN_SHIFT This_symbol_has_been_deprecated 12477 #define UART_PROG_REG_LCV_LEN(x) This_symbol_has_been_deprecated 12478 #define UART_STATE_REG_SM_STATE_MASK This_symbol_has_been_deprecated 12479 #define UART_STATE_REG_SM_STATE_SHIFT This_symbol_has_been_deprecated 12480 #define UART_STATE_REG_SM_STATE(x) This_symbol_has_been_deprecated 12481 #define UART_STATE_REG_TX_STATE_MASK This_symbol_has_been_deprecated 12482 #define UART_STATE_REG_TX_STATE_SHIFT This_symbol_has_been_deprecated 12483 #define UART_STATE_REG_TX_STATE(x) This_symbol_has_been_deprecated 12484 #define MCG_C2_EREFS0_MASK MCG_C2_EREFS_MASK 12485 #define MCG_C2_EREFS0_SHIFT MCG_C2_EREFS_SHIFT 12486 #define MCG_C2_HGO0_MASK MCG_C2_HGO_MASK 12487 #define MCG_C2_HGO0_SHIFT MCG_C2_HGO_SHIFT 12488 #define MCG_C2_RANGE0_MASK MCG_C2_RANGE_MASK 12489 #define MCG_C2_RANGE0_SHIFT MCG_C2_RANGE_SHIFT 12490 #define MCG_C2_RANGE0(x) MCG_C2_RANGE(x) 12491 #define DSPI0 SPI0 12492 #define FLEXCAN0 CAN0 12493 #define DMAMUX0 DMAMUX 12494 #define DMA0_04_IRQn DMA0_DMA4_IRQn 12495 #define DMA0_15_IRQn DMA1_DMA5_IRQn 12496 #define DMA0_26_IRQn DMA2_DMA6_IRQn 12497 #define DMA0_37_IRQn DMA3_DMA7_IRQn 12498 #define DMA0_04_DriverIRQHandler DMA0_DMA4_DriverIRQHandler 12499 #define DMA0_15_DriverIRQHandler DMA1_DMA5_DriverIRQHandler 12500 #define DMA0_26_DriverIRQHandler DMA2_DMA6_DriverIRQHandler 12501 #define DMA0_37_DriverIRQHandler DMA3_DMA7_DriverIRQHandler 12502 #define kDmaRequestMux0Reserved14 kDmaRequestMux0CAN0Rx 12503 12504 /*! 12505 * @} 12506 */ /* end of group SDK_Compatibility_Symbols */ 12507 12508 12509 #endif /* _MKV11Z7_H_ */ 12510 12511
