1 /* 2 ** ################################################################### 3 ** Processors: MKE16Z32VLD4 4 ** MKE16Z32VLF4 5 ** MKE16Z64VLD4 6 ** MKE16Z64VLF4 7 ** 8 ** Compilers: Freescale C/C++ for Embedded ARM 9 ** GNU C Compiler 10 ** IAR ANSI C/C++ Compiler for ARM 11 ** Keil ARM C/C++ Compiler 12 ** MCUXpresso Compiler 13 ** 14 ** Reference manual: KE1xZP48M48SF0RM, Rev. 1, Sep. 2018 15 ** Version: rev. 3.0, 2020-01-22 16 ** Build: b200925 17 ** 18 ** Abstract: 19 ** CMSIS Peripheral Access Layer for MKE16Z4 20 ** 21 ** Copyright 1997-2016 Freescale Semiconductor, Inc. 22 ** Copyright 2016-2020 NXP 23 ** All rights reserved. 24 ** 25 ** SPDX-License-Identifier: BSD-3-Clause 26 ** 27 ** http: www.nxp.com 28 ** mail: support@nxp.com 29 ** 30 ** Revisions: 31 ** - rev. 1.0 (2018-05-09) 32 ** Initial version. 33 ** - rev. 2.0 (2018-09-17) 34 ** Based on rev1 RM. 35 ** - rev. 3.0 (2020-01-22) 36 ** Add 40 pins part numbers. 37 ** 38 ** ################################################################### 39 */ 40 41 /*! 42 * @file MKE16Z4.h 43 * @version 3.0 44 * @date 2020-01-22 45 * @brief CMSIS Peripheral Access Layer for MKE16Z4 46 * 47 * CMSIS Peripheral Access Layer for MKE16Z4 48 */ 49 50 #ifndef _MKE16Z4_H_ 51 #define _MKE16Z4_H_ /**< Symbol preventing repeated inclusion */ 52 53 /** Memory map major version (memory maps with equal major version number are 54 * compatible) */ 55 #define MCU_MEM_MAP_VERSION 0x0300U 56 /** Memory map minor version */ 57 #define MCU_MEM_MAP_VERSION_MINOR 0x0000U 58 59 60 /* ---------------------------------------------------------------------------- 61 -- Interrupt vector numbers 62 ---------------------------------------------------------------------------- */ 63 64 /*! 65 * @addtogroup Interrupt_vector_numbers Interrupt vector numbers 66 * @{ 67 */ 68 69 /** Interrupt Number Definitions */ 70 #define NUMBER_OF_INT_VECTORS 48 /**< Number of interrupts in the Vector table */ 71 72 typedef enum IRQn { 73 /* Auxiliary constants */ 74 NotAvail_IRQn = -128, /**< Not available device specific interrupt */ 75 76 /* Core interrupts */ 77 NonMaskableInt_IRQn = -14, /**< Non Maskable Interrupt */ 78 HardFault_IRQn = -13, /**< Cortex-M0 SV Hard Fault Interrupt */ 79 SVCall_IRQn = -5, /**< Cortex-M0 SV Call Interrupt */ 80 PendSV_IRQn = -2, /**< Cortex-M0 Pend SV Interrupt */ 81 SysTick_IRQn = -1, /**< Cortex-M0 System Tick Interrupt */ 82 83 /* Device specific interrupts */ 84 Reserved16_IRQn = 0, /**< Reserved interrupt */ 85 Reserved17_IRQn = 1, /**< Reserved interrupt */ 86 Reserved18_IRQn = 2, /**< Reserved interrupt */ 87 Reserved19_IRQn = 3, /**< Reserved interrupt */ 88 Reserved20_IRQn = 4, /**< Reserved interrupt */ 89 FTFA_IRQn = 5, /**< Flash memory single interrupt vector for all sources */ 90 LVD_LVW_IRQn = 6, /**< Low-voltage detect, low-voltage warning */ 91 PORTAE_IRQn = 7, /**< Pin detect (Port A, E) */ 92 LPI2C0_IRQn = 8, /**< Inter-integrated circuit 0 interrupt */ 93 Reserved25_IRQn = 9, /**< Reserved interrupt */ 94 LPSPI0_IRQn = 10, /**< Serial peripheral Interface 0 interrupt */ 95 Reserved27_IRQn = 11, /**< Reserved interrupt */ 96 LPUART0_IRQn = 12, /**< Single interrupt vector for all sources */ 97 LPUART1_IRQn = 13, /**< Single interrupt vector for all sources */ 98 LPUART2_IRQn = 14, /**< Single interrupt vector for all sources */ 99 ADC0_IRQn = 15, /**< ADC0 conversion complete interrupt */ 100 CMP0_IRQn = 16, /**< CMP0 interrupt */ 101 FTM0_IRQn = 17, /**< FTM0 single interrupt vector for all sources */ 102 FTM1_IRQn = 18, /**< FTM1 single interrupt vector for all sources */ 103 Reserved35_IRQn = 19, /**< Reserved interrupt */ 104 RTC_IRQn = 20, /**< Single interrupt vector for all sources */ 105 Reserved37_IRQn = 21, /**< Reserved interrupt */ 106 LPIT0_IRQn = 22, /**< LPIT channel 0-1 */ 107 Reserved39_IRQn = 23, /**< Reserved interrupt */ 108 TSI_IRQn = 24, /**< TSI interrupt */ 109 PDB0_IRQn = 25, /**< Programmable delay block interrupt */ 110 PORTBCD_IRQn = 26, /**< Pin detect (Port B, C, D) */ 111 SCG_RCM_IRQn = 27, /**< Single interrupt vector for SCG and RCM */ 112 WDOG_EWM_IRQn = 28, /**< Single interrupt vector for WDOG and EWM */ 113 PWT_LPTMR0_IRQn = 29, /**< Single interrupt vector for PWT and LPTMR0 */ 114 MSCAN_Rx_IRQn = 30, /**< MSCAN Rx Interrupt */ 115 MSCAN_ORed_IRQn = 31 /**< MSCAN Tx, Err and Wake-up interrupt */ 116 } IRQn_Type; 117 118 /*! 119 * @} 120 */ /* end of group Interrupt_vector_numbers */ 121 122 123 /* ---------------------------------------------------------------------------- 124 -- Cortex M0 Core Configuration 125 ---------------------------------------------------------------------------- */ 126 127 /*! 128 * @addtogroup Cortex_Core_Configuration Cortex M0 Core Configuration 129 * @{ 130 */ 131 132 #define __CM0PLUS_REV 0x0000 /**< Core revision r0p0 */ 133 #define __MPU_PRESENT 0 /**< Defines if an MPU is present or not */ 134 #define __VTOR_PRESENT 1 /**< Defines if VTOR is present or not */ 135 #define __NVIC_PRIO_BITS 2 /**< Number of priority bits implemented in the NVIC */ 136 #define __Vendor_SysTickConfig 0 /**< Vendor specific implementation of SysTickConfig is defined */ 137 138 #include "core_cm0plus.h" /* Core Peripheral Access Layer */ 139 #include "system_MKE16Z4.h" /* Device specific configuration file */ 140 141 /*! 142 * @} 143 */ /* end of group Cortex_Core_Configuration */ 144 145 146 /* ---------------------------------------------------------------------------- 147 -- Mapping Information 148 ---------------------------------------------------------------------------- */ 149 150 /*! 151 * @addtogroup Mapping_Information Mapping Information 152 * @{ 153 */ 154 155 /** Mapping Information */ 156 /*! 157 * @addtogroup trgmux_source 158 * @{ */ 159 160 /******************************************************************************* 161 * Definitions 162 *******************************************************************************/ 163 164 /*! 165 * @brief Structure for the TRGMUX source 166 * 167 * Defines the structure for the TRGMUX source collections. 168 */ 169 typedef enum _trgmux_source 170 { 171 kTRGMUX_SourceTriggerMuxInput0 = 0U, /**< Trigger Mux input 0 is selected */ 172 kTRGMUX_SourceVss = 0U, /**< VSS is disabled */ 173 kTRGMUX_SourceTriggerMuxInput1 = 1U, /**< Trigger Mux input 1 is selected */ 174 kTRGMUX_SourceVdd = 1U, /**< VDD is disabled */ 175 kTRGMUX_SourceTriggerMuxInput2 = 2U, /**< Trigger Mux input 2 is selected */ 176 kTRGMUX_SimSoftwareTrigger = 2U, /**< SIM Software Trigger is selected */ 177 kTRGMUX_SourceTriggerMuxInput3 = 3U, /**< Trigger Mux input 3 is selected */ 178 kTRGMUX_SourceRtcSeconds = 4U, /**< RTC Seconds input is selected */ 179 kTRGMUX_SourceRtcAlarm = 5U, /**< RTC Alarm input is selected */ 180 kTRGMUX_SourceLptmr0 = 6U, /**< LPTMR0 input is selected */ 181 kTRGMUX_SourceLpit0Ch0 = 7U, /**< LPIT0 Channel0 is selected */ 182 kTRGMUX_SourceLpuart0RxData = 7U, /**< LPUART0 RX Data is selected */ 183 kTRGMUX_SourceLpit0Ch1 = 8U, /**< LPIT0 Channel1 is selected */ 184 kTRGMUX_SourceLpuart0TxData = 8U, /**< LPUART0 TX Data is selected */ 185 kTRGMUX_SourceFtm0 = 11U, /**< FTM0 is selected */ 186 kTRGMUX_SourceLpi2c0SlaveStop = 11U, /**< LPI2C0 Slave STOP is selected */ 187 kTRGMUX_SourceFtm1 = 12U, /**< FTM1 is selected */ 188 kTRGMUX_SourceLpspi0Frame = 12U, /**< LPSPI0 Frame is selected */ 189 kTRGMUX_SourceAdc0CocoA = 15U, /**< ADC0 COCOA is selected */ 190 kTRGMUX_SourceLpuart1TxData = 15U, /**< LPUART1 TX Data is selected */ 191 kTRGMUX_SourceAdc0CocoB = 16U, /**< ADC0 COCOB is selected */ 192 kTRGMUX_SourceLpuart1RxIdle = 16U, /**< LPUART1 RX Idle is selected */ 193 kTRGMUX_SourceCmp0Output = 17U, /**< CMP0 Output is selected */ 194 kTRGMUX_SourceTrgmux1Output0 = 24U, /**< TRGMUX1 Output 0 is selected */ 195 kTRGMUX_SourceTrgmux1Output1 = 25U, /**< TRGMUX1 Output 1 is selected */ 196 kTRGMUX_SourceTrgmux1Output2 = 26U, /**< TRGMUX1 Output 2 is selected */ 197 kTRGMUX_SourceTrgmux1Output3 = 27U, /**< TRGMUX1 Output 3 is selected */ 198 kTRGMUX_SourceLpuart0Idle = 9U, /**< LPUART0 Idle is selected */ 199 kTRGMUX_SourceLpi2c0MasterStop = 10U, /**< LPI2C0 Master STOP is selected */ 200 kTRGMUX_SourceLpspi0RxData = 13U, /**< LPSPI0 RX Data is selected */ 201 kTRGMUX_SourceLpuart1RxData = 14U, /**< LPUART1 RX Data is selected */ 202 kTRGMUX_SourcePdb0Pulse0 = 23U, /**< PDB0 Pulse0 is selected */ 203 } trgmux_source_t; 204 205 /*! 206 * @brief Structure for the TRGMUX device 207 * 208 * Defines the structure for the TRGMUX device collections. 209 */ 210 typedef enum _trgmux_device 211 { 212 kTRGMUX_ExtOut0_3 = 1U, /**< EXTOUT0 device trigger input */ 213 kTRGMUX_Adc0 = 3U, /**< ADC0 device trigger input */ 214 kTRGMUX_Cmp0 = 7U, /**< CMP0 device trigger input */ 215 kTRGMUX_Ftm0 = 10U, /**< FTM0 device trigger input */ 216 kTRGMUX_Ftm1 = 11U, /**< FTM1 device trigger input */ 217 kTRGMUX_Pdb0 = 14U, /**< PDB0 device trigger input */ 218 kTRGMUX_Lpit = 18U, /**< LPIT device trigger input */ 219 kTRGMUX_Lpuart0 = 19U, /**< LPUART0 device trigger input */ 220 kTRGMUX_Lpuart1 = 20U, /**< LPUART1 device trigger input */ 221 kTRGMUX_Lpi2c0 = 21U, /**< LPI2C0 device trigger input */ 222 kTRGMUX_Lpspi0 = 23U, /**< LPSPI0 device trigger input */ 223 kTRGMUX_Lptmr0 = 25U, /**< LPTMR0 device trigger input */ 224 kTRGMUX_Tsi = 26U, /**< TSI device trigger input */ 225 kTRGMUX_Pwt = 27U, /**< PWT device trigger input */ 226 kTRGMUX_Ctrl0 = 0U, /**< CTRL0 device trigger input */ 227 } trgmux_device_t; 228 229 /* @} */ 230 231 232 /*! 233 * @} 234 */ /* end of group Mapping_Information */ 235 236 237 /* ---------------------------------------------------------------------------- 238 -- Device Peripheral Access Layer 239 ---------------------------------------------------------------------------- */ 240 241 /*! 242 * @addtogroup Peripheral_access_layer Device Peripheral Access Layer 243 * @{ 244 */ 245 246 247 /* 248 ** Start of section using anonymous unions 249 */ 250 251 #if defined(__ARMCC_VERSION) 252 #if (__ARMCC_VERSION >= 6010050) 253 #pragma clang diagnostic push 254 #else 255 #pragma push 256 #pragma anon_unions 257 #endif 258 #elif defined(__CWCC__) 259 #pragma push 260 #pragma cpp_extensions on 261 #elif defined(__GNUC__) 262 /* anonymous unions are enabled by default */ 263 #elif defined(__IAR_SYSTEMS_ICC__) 264 #pragma language=extended 265 #else 266 #error Not supported compiler type 267 #endif 268 269 /* ---------------------------------------------------------------------------- 270 -- ADC Peripheral Access Layer 271 ---------------------------------------------------------------------------- */ 272 273 /*! 274 * @addtogroup ADC_Peripheral_Access_Layer ADC Peripheral Access Layer 275 * @{ 276 */ 277 278 /** ADC - Register Layout Typedef */ 279 typedef struct { 280 __IO uint32_t SC1[4]; /**< ADC Status and Control Register 1, array offset: 0x0, array step: 0x4 */ 281 uint8_t RESERVED_0[48]; 282 __IO uint32_t CFG1; /**< ADC Configuration Register 1, offset: 0x40 */ 283 __IO uint32_t CFG2; /**< ADC Configuration Register 2, offset: 0x44 */ 284 __IO uint32_t R[4]; /**< ADC Data Result Registers, array offset: 0x48, array step: 0x4 */ 285 uint8_t RESERVED_1[48]; 286 __IO uint32_t CV1; /**< Compare Value Registers, offset: 0x88 */ 287 __IO uint32_t CV2; /**< Compare Value Registers, offset: 0x8C */ 288 __IO uint32_t SC2; /**< Status and Control Register 2, offset: 0x90 */ 289 __IO uint32_t SC3; /**< Status and Control Register 3, offset: 0x94 */ 290 __IO uint32_t BASE_OFS; /**< BASE Offset Register, offset: 0x98 */ 291 __IO uint32_t OFS; /**< ADC Offset Correction Register, offset: 0x9C */ 292 __IO uint32_t USR_OFS; /**< USER Offset Correction Register, offset: 0xA0 */ 293 __IO uint32_t XOFS; /**< ADC X Offset Correction Register, offset: 0xA4 */ 294 __IO uint32_t YOFS; /**< ADC Y Offset Correction Register, offset: 0xA8 */ 295 __IO uint32_t G; /**< ADC Gain Register, offset: 0xAC */ 296 __IO uint32_t UG; /**< ADC User Gain Register, offset: 0xB0 */ 297 __IO uint32_t CLPS; /**< ADC General Calibration Value Register S, offset: 0xB4 */ 298 __IO uint32_t CLP3; /**< ADC Plus-Side General Calibration Value Register 3, offset: 0xB8 */ 299 __IO uint32_t CLP2; /**< ADC Plus-Side General Calibration Value Register 2, offset: 0xBC */ 300 __IO uint32_t CLP1; /**< ADC Plus-Side General Calibration Value Register 1, offset: 0xC0 */ 301 __IO uint32_t CLP0; /**< ADC Plus-Side General Calibration Value Register 0, offset: 0xC4 */ 302 __IO uint32_t CLPX; /**< ADC Plus-Side General Calibration Value Register X, offset: 0xC8 */ 303 __IO uint32_t CLP9; /**< ADC Plus-Side General Calibration Value Register 9, offset: 0xCC */ 304 __IO uint32_t CLPS_OFS; /**< ADC General Calibration Offset Value Register S, offset: 0xD0 */ 305 __IO uint32_t CLP3_OFS; /**< ADC Plus-Side General Calibration Offset Value Register 3, offset: 0xD4 */ 306 __IO uint32_t CLP2_OFS; /**< ADC Plus-Side General Calibration Offset Value Register 2, offset: 0xD8 */ 307 __IO uint32_t CLP1_OFS; /**< ADC Plus-Side General Calibration Offset Value Register 1, offset: 0xDC */ 308 __IO uint32_t CLP0_OFS; /**< ADC Plus-Side General Calibration Offset Value Register 0, offset: 0xE0 */ 309 __IO uint32_t CLPX_OFS; /**< ADC Plus-Side General Calibration Offset Value Register X, offset: 0xE4 */ 310 __IO uint32_t CLP9_OFS; /**< ADC Plus-Side General Calibration Offset Value Register 9, offset: 0xE8 */ 311 } ADC_Type; 312 313 /* ---------------------------------------------------------------------------- 314 -- ADC Register Masks 315 ---------------------------------------------------------------------------- */ 316 317 /*! 318 * @addtogroup ADC_Register_Masks ADC Register Masks 319 * @{ 320 */ 321 322 /*! @name SC1 - ADC Status and Control Register 1 */ 323 /*! @{ */ 324 #define ADC_SC1_ADCH_MASK (0x1FU) 325 #define ADC_SC1_ADCH_SHIFT (0U) 326 /*! ADCH - Input channel select 327 * 0b00000..External channel 0 is selected as input. 328 * 0b00001..External channel 1 is selected as input. 329 * 0b00010..External channel 2 is selected as input. 330 * 0b00011..External channel 3 is selected as input. 331 * 0b00100..External channel 4 is selected as input. 332 * 0b00101..External channel 5 is selected as input. 333 * 0b00110..External channel 6 is selected as input. 334 * 0b00111..External channel 7 is selected as input. 335 * 0b01000..External channel 8 is selected as input. 336 * 0b01001..External channel 9 is selected as input. 337 * 0b01010..External channel 10 is selected as input. 338 * 0b01011..External channel 11 is selected as input. 339 * 0b01100..External channel 12 is selected as input. 340 * 0b01101..External channel 13 is selected as input. 341 * 0b01110..External channel 14 is selected as input. 342 * 0b01111..External channel 15 is selected as input. 343 * 0b10000..Reserved 344 * 0b10001..Reserved 345 * 0b10010..External channel 18 is selected as input. 346 * 0b10011..External channel 19 is selected as input. 347 * 0b10100..Reserved. 348 * 0b10101..Internal channel 0 is selected as input. 349 * 0b10110..Internal channel 1 is selected as input. 350 * 0b10111..Internal channel 2 is selected as input. 351 * 0b11000..Reserved 352 * 0b11001..Reserved 353 * 0b11010..Temp Sensor 354 * 0b11011..Band Gap 355 * 0b11100..Internal channel 3 is selected as input. 356 * 0b11101..VREFSH is selected as input. Voltage reference selected is determined by SC2[REFSEL]. 357 * 0b11110..VREFSL is selected as input. Voltage reference selected is determined by SC2[REFSEL]. 358 * 0b11111..Module is disabled 359 */ 360 #define ADC_SC1_ADCH(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC1_ADCH_SHIFT)) & ADC_SC1_ADCH_MASK) 361 #define ADC_SC1_AIEN_MASK (0x40U) 362 #define ADC_SC1_AIEN_SHIFT (6U) 363 /*! AIEN - Interrupt Enable 364 * 0b0..Conversion complete interrupt is disabled. 365 * 0b1..Conversion complete interrupt is enabled. 366 */ 367 #define ADC_SC1_AIEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC1_AIEN_SHIFT)) & ADC_SC1_AIEN_MASK) 368 #define ADC_SC1_COCO_MASK (0x80U) 369 #define ADC_SC1_COCO_SHIFT (7U) 370 /*! COCO - Conversion Complete Flag 371 * 0b0..Conversion is not complete. 372 * 0b1..Conversion is complete. 373 */ 374 #define ADC_SC1_COCO(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC1_COCO_SHIFT)) & ADC_SC1_COCO_MASK) 375 /*! @} */ 376 377 /* The count of ADC_SC1 */ 378 #define ADC_SC1_COUNT (4U) 379 380 /*! @name CFG1 - ADC Configuration Register 1 */ 381 /*! @{ */ 382 #define ADC_CFG1_ADICLK_MASK (0x3U) 383 #define ADC_CFG1_ADICLK_SHIFT (0U) 384 /*! ADICLK - Input Clock Select 385 * 0b00..Alternate clock 1 (ALTCLK1) 386 * 0b01..Alternate clock 2 (ALTCLK2) 387 * 0b10..Alternate clock 3 (ALTCLK3) 388 * 0b11..Alternate clock 4 (ALTCLK4) 389 */ 390 #define ADC_CFG1_ADICLK(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG1_ADICLK_SHIFT)) & ADC_CFG1_ADICLK_MASK) 391 #define ADC_CFG1_MODE_MASK (0xCU) 392 #define ADC_CFG1_MODE_SHIFT (2U) 393 /*! MODE - Conversion mode selection 394 * 0b00..8-bit conversion. 395 * 0b01..12-bit conversion. 396 * 0b10..10-bit conversion. 397 * 0b11..Reserved 398 */ 399 #define ADC_CFG1_MODE(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG1_MODE_SHIFT)) & ADC_CFG1_MODE_MASK) 400 #define ADC_CFG1_ADIV_MASK (0x60U) 401 #define ADC_CFG1_ADIV_SHIFT (5U) 402 /*! ADIV - Clock Divide Select 403 * 0b00..The divide ratio is 1 and the clock rate is input clock. 404 * 0b01..The divide ratio is 2 and the clock rate is (input clock)/2. 405 * 0b10..The divide ratio is 4 and the clock rate is (input clock)/4. 406 * 0b11..The divide ratio is 8 and the clock rate is (input clock)/8. 407 */ 408 #define ADC_CFG1_ADIV(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG1_ADIV_SHIFT)) & ADC_CFG1_ADIV_MASK) 409 /*! @} */ 410 411 /*! @name CFG2 - ADC Configuration Register 2 */ 412 /*! @{ */ 413 #define ADC_CFG2_SMPLTS_MASK (0xFFU) 414 #define ADC_CFG2_SMPLTS_SHIFT (0U) 415 /*! SMPLTS - Sample Time Select 416 */ 417 #define ADC_CFG2_SMPLTS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG2_SMPLTS_SHIFT)) & ADC_CFG2_SMPLTS_MASK) 418 /*! @} */ 419 420 /*! @name R - ADC Data Result Registers */ 421 /*! @{ */ 422 #define ADC_R_D_MASK (0xFFFU) 423 #define ADC_R_D_SHIFT (0U) 424 /*! D - Data result 425 */ 426 #define ADC_R_D(x) (((uint32_t)(((uint32_t)(x)) << ADC_R_D_SHIFT)) & ADC_R_D_MASK) 427 /*! @} */ 428 429 /* The count of ADC_R */ 430 #define ADC_R_COUNT (4U) 431 432 /*! @name CV1 - Compare Value Registers */ 433 /*! @{ */ 434 #define ADC_CV1_CV_MASK (0xFFFFU) 435 #define ADC_CV1_CV_SHIFT (0U) 436 /*! CV - Compare Value. 437 */ 438 #define ADC_CV1_CV(x) (((uint32_t)(((uint32_t)(x)) << ADC_CV1_CV_SHIFT)) & ADC_CV1_CV_MASK) 439 /*! @} */ 440 441 /*! @name CV2 - Compare Value Registers */ 442 /*! @{ */ 443 #define ADC_CV2_CV_MASK (0xFFFFU) 444 #define ADC_CV2_CV_SHIFT (0U) 445 /*! CV - Compare Value. 446 */ 447 #define ADC_CV2_CV(x) (((uint32_t)(((uint32_t)(x)) << ADC_CV2_CV_SHIFT)) & ADC_CV2_CV_MASK) 448 /*! @} */ 449 450 /*! @name SC2 - Status and Control Register 2 */ 451 /*! @{ */ 452 #define ADC_SC2_REFSEL_MASK (0x3U) 453 #define ADC_SC2_REFSEL_SHIFT (0U) 454 /*! REFSEL - Voltage Reference Selection 455 * 0b00..Default voltage reference pin pair, that is, external pins VREFH and VREFL 456 * 0b01..Alternate reference voltage, that is, VALTH. This voltage may be additional external pin or internal 457 * source depending on the MCU configuration. See the chip configuration information for details specific to 458 * this MCU. 459 * 0b10..Reserved 460 * 0b11..Reserved 461 */ 462 #define ADC_SC2_REFSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_REFSEL_SHIFT)) & ADC_SC2_REFSEL_MASK) 463 #define ADC_SC2_ACREN_MASK (0x8U) 464 #define ADC_SC2_ACREN_SHIFT (3U) 465 /*! ACREN - Compare Function Range Enable 466 */ 467 #define ADC_SC2_ACREN(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_ACREN_SHIFT)) & ADC_SC2_ACREN_MASK) 468 #define ADC_SC2_ACFGT_MASK (0x10U) 469 #define ADC_SC2_ACFGT_SHIFT (4U) 470 /*! ACFGT - Compare Function Greater Than Enable 471 */ 472 #define ADC_SC2_ACFGT(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_ACFGT_SHIFT)) & ADC_SC2_ACFGT_MASK) 473 #define ADC_SC2_ACFE_MASK (0x20U) 474 #define ADC_SC2_ACFE_SHIFT (5U) 475 /*! ACFE - Compare Function Enable 476 * 0b0..Compare function disabled. 477 * 0b1..Compare function enabled. 478 */ 479 #define ADC_SC2_ACFE(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_ACFE_SHIFT)) & ADC_SC2_ACFE_MASK) 480 #define ADC_SC2_ADTRG_MASK (0x40U) 481 #define ADC_SC2_ADTRG_SHIFT (6U) 482 /*! ADTRG - Conversion Trigger Select 483 * 0b0..Software trigger selected. 484 * 0b1..Hardware trigger selected. 485 */ 486 #define ADC_SC2_ADTRG(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_ADTRG_SHIFT)) & ADC_SC2_ADTRG_MASK) 487 #define ADC_SC2_ADACT_MASK (0x80U) 488 #define ADC_SC2_ADACT_SHIFT (7U) 489 /*! ADACT - Conversion Active 490 * 0b0..Conversion not in progress. 491 * 0b1..Conversion in progress. 492 */ 493 #define ADC_SC2_ADACT(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_ADACT_SHIFT)) & ADC_SC2_ADACT_MASK) 494 /*! @} */ 495 496 /*! @name SC3 - Status and Control Register 3 */ 497 /*! @{ */ 498 #define ADC_SC3_AVGS_MASK (0x3U) 499 #define ADC_SC3_AVGS_SHIFT (0U) 500 /*! AVGS - Hardware Average Select 501 * 0b00..4 samples averaged. 502 * 0b01..8 samples averaged. 503 * 0b10..16 samples averaged. 504 * 0b11..32 samples averaged. 505 */ 506 #define ADC_SC3_AVGS(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC3_AVGS_SHIFT)) & ADC_SC3_AVGS_MASK) 507 #define ADC_SC3_AVGE_MASK (0x4U) 508 #define ADC_SC3_AVGE_SHIFT (2U) 509 /*! AVGE - Hardware Average Enable 510 * 0b0..Hardware average function disabled. 511 * 0b1..Hardware average function enabled. 512 */ 513 #define ADC_SC3_AVGE(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC3_AVGE_SHIFT)) & ADC_SC3_AVGE_MASK) 514 #define ADC_SC3_ADCO_MASK (0x8U) 515 #define ADC_SC3_ADCO_SHIFT (3U) 516 /*! ADCO - Continuous Conversion Enable 517 * 0b0..One conversion will be performed (or one set of conversions, if AVGE is set) after a conversion is initiated. 518 * 0b1..Continuous conversions will be performed (or continuous sets of conversions, if AVGE is set) after a conversion is initiated. 519 */ 520 #define ADC_SC3_ADCO(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC3_ADCO_SHIFT)) & ADC_SC3_ADCO_MASK) 521 #define ADC_SC3_CAL_MASK (0x80U) 522 #define ADC_SC3_CAL_SHIFT (7U) 523 /*! CAL - Calibration 524 */ 525 #define ADC_SC3_CAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC3_CAL_SHIFT)) & ADC_SC3_CAL_MASK) 526 /*! @} */ 527 528 /*! @name BASE_OFS - BASE Offset Register */ 529 /*! @{ */ 530 #define ADC_BASE_OFS_BA_OFS_MASK (0xFFU) 531 #define ADC_BASE_OFS_BA_OFS_SHIFT (0U) 532 /*! BA_OFS - Base Offset Error Correction Value 533 */ 534 #define ADC_BASE_OFS_BA_OFS(x) (((uint32_t)(((uint32_t)(x)) << ADC_BASE_OFS_BA_OFS_SHIFT)) & ADC_BASE_OFS_BA_OFS_MASK) 535 /*! @} */ 536 537 /*! @name OFS - ADC Offset Correction Register */ 538 /*! @{ */ 539 #define ADC_OFS_OFS_MASK (0xFFFFU) 540 #define ADC_OFS_OFS_SHIFT (0U) 541 /*! OFS - Offset Error Correction Value 542 */ 543 #define ADC_OFS_OFS(x) (((uint32_t)(((uint32_t)(x)) << ADC_OFS_OFS_SHIFT)) & ADC_OFS_OFS_MASK) 544 /*! @} */ 545 546 /*! @name USR_OFS - USER Offset Correction Register */ 547 /*! @{ */ 548 #define ADC_USR_OFS_USR_OFS_MASK (0xFFU) 549 #define ADC_USR_OFS_USR_OFS_SHIFT (0U) 550 /*! USR_OFS - USER Offset Error Correction Value 551 */ 552 #define ADC_USR_OFS_USR_OFS(x) (((uint32_t)(((uint32_t)(x)) << ADC_USR_OFS_USR_OFS_SHIFT)) & ADC_USR_OFS_USR_OFS_MASK) 553 /*! @} */ 554 555 /*! @name XOFS - ADC X Offset Correction Register */ 556 /*! @{ */ 557 #define ADC_XOFS_XOFS_MASK (0x3FU) 558 #define ADC_XOFS_XOFS_SHIFT (0U) 559 /*! XOFS - X offset error correction value 560 */ 561 #define ADC_XOFS_XOFS(x) (((uint32_t)(((uint32_t)(x)) << ADC_XOFS_XOFS_SHIFT)) & ADC_XOFS_XOFS_MASK) 562 /*! @} */ 563 564 /*! @name YOFS - ADC Y Offset Correction Register */ 565 /*! @{ */ 566 #define ADC_YOFS_YOFS_MASK (0xFFU) 567 #define ADC_YOFS_YOFS_SHIFT (0U) 568 /*! YOFS - Y offset error correction value 569 */ 570 #define ADC_YOFS_YOFS(x) (((uint32_t)(((uint32_t)(x)) << ADC_YOFS_YOFS_SHIFT)) & ADC_YOFS_YOFS_MASK) 571 /*! @} */ 572 573 /*! @name G - ADC Gain Register */ 574 /*! @{ */ 575 #define ADC_G_G_MASK (0x7FFU) 576 #define ADC_G_G_SHIFT (0U) 577 /*! G - G 578 */ 579 #define ADC_G_G(x) (((uint32_t)(((uint32_t)(x)) << ADC_G_G_SHIFT)) & ADC_G_G_MASK) 580 /*! @} */ 581 582 /*! @name UG - ADC User Gain Register */ 583 /*! @{ */ 584 #define ADC_UG_UG_MASK (0x3FFU) 585 #define ADC_UG_UG_SHIFT (0U) 586 /*! UG - UG 587 */ 588 #define ADC_UG_UG(x) (((uint32_t)(((uint32_t)(x)) << ADC_UG_UG_SHIFT)) & ADC_UG_UG_MASK) 589 /*! @} */ 590 591 /*! @name CLPS - ADC General Calibration Value Register S */ 592 /*! @{ */ 593 #define ADC_CLPS_CLPS_MASK (0x7FU) 594 #define ADC_CLPS_CLPS_SHIFT (0U) 595 /*! CLPS - CLPS 596 */ 597 #define ADC_CLPS_CLPS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLPS_CLPS_SHIFT)) & ADC_CLPS_CLPS_MASK) 598 /*! @} */ 599 600 /*! @name CLP3 - ADC Plus-Side General Calibration Value Register 3 */ 601 /*! @{ */ 602 #define ADC_CLP3_CLP3_MASK (0x3FFU) 603 #define ADC_CLP3_CLP3_SHIFT (0U) 604 /*! CLP3 - CLP3 605 */ 606 #define ADC_CLP3_CLP3(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLP3_CLP3_SHIFT)) & ADC_CLP3_CLP3_MASK) 607 /*! @} */ 608 609 /*! @name CLP2 - ADC Plus-Side General Calibration Value Register 2 */ 610 /*! @{ */ 611 #define ADC_CLP2_CLP2_MASK (0x3FFU) 612 #define ADC_CLP2_CLP2_SHIFT (0U) 613 /*! CLP2 - CLP2 614 */ 615 #define ADC_CLP2_CLP2(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLP2_CLP2_SHIFT)) & ADC_CLP2_CLP2_MASK) 616 /*! @} */ 617 618 /*! @name CLP1 - ADC Plus-Side General Calibration Value Register 1 */ 619 /*! @{ */ 620 #define ADC_CLP1_CLP1_MASK (0x1FFU) 621 #define ADC_CLP1_CLP1_SHIFT (0U) 622 /*! CLP1 - CLP1 623 */ 624 #define ADC_CLP1_CLP1(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLP1_CLP1_SHIFT)) & ADC_CLP1_CLP1_MASK) 625 /*! @} */ 626 627 /*! @name CLP0 - ADC Plus-Side General Calibration Value Register 0 */ 628 /*! @{ */ 629 #define ADC_CLP0_CLP0_MASK (0xFFU) 630 #define ADC_CLP0_CLP0_SHIFT (0U) 631 /*! CLP0 - CLP0 632 */ 633 #define ADC_CLP0_CLP0(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLP0_CLP0_SHIFT)) & ADC_CLP0_CLP0_MASK) 634 /*! @} */ 635 636 /*! @name CLPX - ADC Plus-Side General Calibration Value Register X */ 637 /*! @{ */ 638 #define ADC_CLPX_CLPX_MASK (0x7FU) 639 #define ADC_CLPX_CLPX_SHIFT (0U) 640 /*! CLPX - CLPX 641 */ 642 #define ADC_CLPX_CLPX(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLPX_CLPX_SHIFT)) & ADC_CLPX_CLPX_MASK) 643 /*! @} */ 644 645 /*! @name CLP9 - ADC Plus-Side General Calibration Value Register 9 */ 646 /*! @{ */ 647 #define ADC_CLP9_CLP9_MASK (0x7FU) 648 #define ADC_CLP9_CLP9_SHIFT (0U) 649 /*! CLP9 - CLP9 650 */ 651 #define ADC_CLP9_CLP9(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLP9_CLP9_SHIFT)) & ADC_CLP9_CLP9_MASK) 652 /*! @} */ 653 654 /*! @name CLPS_OFS - ADC General Calibration Offset Value Register S */ 655 /*! @{ */ 656 #define ADC_CLPS_OFS_CLPS_OFS_MASK (0xFU) 657 #define ADC_CLPS_OFS_CLPS_OFS_SHIFT (0U) 658 /*! CLPS_OFS - CLPS Offset 659 */ 660 #define ADC_CLPS_OFS_CLPS_OFS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLPS_OFS_CLPS_OFS_SHIFT)) & ADC_CLPS_OFS_CLPS_OFS_MASK) 661 /*! @} */ 662 663 /*! @name CLP3_OFS - ADC Plus-Side General Calibration Offset Value Register 3 */ 664 /*! @{ */ 665 #define ADC_CLP3_OFS_CLP3_OFS_MASK (0xFU) 666 #define ADC_CLP3_OFS_CLP3_OFS_SHIFT (0U) 667 /*! CLP3_OFS - CLP3 Offset 668 */ 669 #define ADC_CLP3_OFS_CLP3_OFS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLP3_OFS_CLP3_OFS_SHIFT)) & ADC_CLP3_OFS_CLP3_OFS_MASK) 670 /*! @} */ 671 672 /*! @name CLP2_OFS - ADC Plus-Side General Calibration Offset Value Register 2 */ 673 /*! @{ */ 674 #define ADC_CLP2_OFS_CLP2_OFS_MASK (0xFU) 675 #define ADC_CLP2_OFS_CLP2_OFS_SHIFT (0U) 676 /*! CLP2_OFS - CLP2 Offset 677 */ 678 #define ADC_CLP2_OFS_CLP2_OFS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLP2_OFS_CLP2_OFS_SHIFT)) & ADC_CLP2_OFS_CLP2_OFS_MASK) 679 /*! @} */ 680 681 /*! @name CLP1_OFS - ADC Plus-Side General Calibration Offset Value Register 1 */ 682 /*! @{ */ 683 #define ADC_CLP1_OFS_CLP1_OFS_MASK (0xFU) 684 #define ADC_CLP1_OFS_CLP1_OFS_SHIFT (0U) 685 /*! CLP1_OFS - CLP1 Offset 686 */ 687 #define ADC_CLP1_OFS_CLP1_OFS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLP1_OFS_CLP1_OFS_SHIFT)) & ADC_CLP1_OFS_CLP1_OFS_MASK) 688 /*! @} */ 689 690 /*! @name CLP0_OFS - ADC Plus-Side General Calibration Offset Value Register 0 */ 691 /*! @{ */ 692 #define ADC_CLP0_OFS_CLP0_OFS_MASK (0xFU) 693 #define ADC_CLP0_OFS_CLP0_OFS_SHIFT (0U) 694 /*! CLP0_OFS - CLP0 Offset 695 */ 696 #define ADC_CLP0_OFS_CLP0_OFS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLP0_OFS_CLP0_OFS_SHIFT)) & ADC_CLP0_OFS_CLP0_OFS_MASK) 697 /*! @} */ 698 699 /*! @name CLPX_OFS - ADC Plus-Side General Calibration Offset Value Register X */ 700 /*! @{ */ 701 #define ADC_CLPX_OFS_CLPX_OFS_MASK (0xFFFU) 702 #define ADC_CLPX_OFS_CLPX_OFS_SHIFT (0U) 703 /*! CLPX_OFS - CLPX Offset 704 */ 705 #define ADC_CLPX_OFS_CLPX_OFS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLPX_OFS_CLPX_OFS_SHIFT)) & ADC_CLPX_OFS_CLPX_OFS_MASK) 706 /*! @} */ 707 708 /*! @name CLP9_OFS - ADC Plus-Side General Calibration Offset Value Register 9 */ 709 /*! @{ */ 710 #define ADC_CLP9_OFS_CLP9_OFS_MASK (0xFFFU) 711 #define ADC_CLP9_OFS_CLP9_OFS_SHIFT (0U) 712 /*! CLP9_OFS - CLP9 Offset 713 */ 714 #define ADC_CLP9_OFS_CLP9_OFS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLP9_OFS_CLP9_OFS_SHIFT)) & ADC_CLP9_OFS_CLP9_OFS_MASK) 715 /*! @} */ 716 717 718 /*! 719 * @} 720 */ /* end of group ADC_Register_Masks */ 721 722 723 /* ADC - Peripheral instance base addresses */ 724 /** Peripheral ADC0 base address */ 725 #define ADC0_BASE (0x4003B000u) 726 /** Peripheral ADC0 base pointer */ 727 #define ADC0 ((ADC_Type *)ADC0_BASE) 728 /** Array initializer of ADC peripheral base addresses */ 729 #define ADC_BASE_ADDRS { ADC0_BASE } 730 /** Array initializer of ADC peripheral base pointers */ 731 #define ADC_BASE_PTRS { ADC0 } 732 /** Interrupt vectors for the ADC peripheral type */ 733 #define ADC_IRQS { ADC0_IRQn } 734 735 /*! 736 * @} 737 */ /* end of group ADC_Peripheral_Access_Layer */ 738 739 740 /* ---------------------------------------------------------------------------- 741 -- CMP Peripheral Access Layer 742 ---------------------------------------------------------------------------- */ 743 744 /*! 745 * @addtogroup CMP_Peripheral_Access_Layer CMP Peripheral Access Layer 746 * @{ 747 */ 748 749 /** CMP - Register Layout Typedef */ 750 typedef struct { 751 __IO uint32_t C0; /**< CMP Control Register 0, offset: 0x0 */ 752 __IO uint32_t C1; /**< CMP Control Register 1, offset: 0x4 */ 753 __IO uint32_t C2; /**< CMP Control Register 2, offset: 0x8 */ 754 } CMP_Type; 755 756 /* ---------------------------------------------------------------------------- 757 -- CMP Register Masks 758 ---------------------------------------------------------------------------- */ 759 760 /*! 761 * @addtogroup CMP_Register_Masks CMP Register Masks 762 * @{ 763 */ 764 765 /*! @name C0 - CMP Control Register 0 */ 766 /*! @{ */ 767 #define CMP_C0_HYSTCTR_MASK (0x3U) 768 #define CMP_C0_HYSTCTR_SHIFT (0U) 769 /*! HYSTCTR - Comparator hard block hysteresis control. See chip data sheet to get the actual hysteresis value with each level 770 * 0b00..The hard block output has level 0 hysteresis internally. 771 * 0b01..The hard block output has level 1 hysteresis internally. 772 * 0b10..The hard block output has level 2 hysteresis internally. 773 * 0b11..The hard block output has level 3 hysteresis internally. 774 */ 775 #define CMP_C0_HYSTCTR(x) (((uint32_t)(((uint32_t)(x)) << CMP_C0_HYSTCTR_SHIFT)) & CMP_C0_HYSTCTR_MASK) 776 #define CMP_C0_OFFSET_MASK (0x4U) 777 #define CMP_C0_OFFSET_SHIFT (2U) 778 /*! OFFSET - Comparator hard block offset control. See chip data sheet to get the actual offset value with each level 779 * 0b0..The comparator hard block output has level 0 offset internally. 780 * 0b1..The comparator hard block output has level 1 offset internally. 781 */ 782 #define CMP_C0_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << CMP_C0_OFFSET_SHIFT)) & CMP_C0_OFFSET_MASK) 783 #define CMP_C0_FILTER_CNT_MASK (0x70U) 784 #define CMP_C0_FILTER_CNT_SHIFT (4U) 785 /*! FILTER_CNT - Filter Sample Count 786 * 0b000..Filter is disabled. If SE = 1, then COUT is a logic zero (this is not a legal state, and is not recommended). If SE = 0, COUT = COUTA. 787 * 0b001..1 consecutive sample must agree (comparator output is simply sampled). 788 * 0b010..2 consecutive samples must agree. 789 * 0b011..3 consecutive samples must agree. 790 * 0b100..4 consecutive samples must agree. 791 * 0b101..5 consecutive samples must agree. 792 * 0b110..6 consecutive samples must agree. 793 * 0b111..7 consecutive samples must agree. 794 */ 795 #define CMP_C0_FILTER_CNT(x) (((uint32_t)(((uint32_t)(x)) << CMP_C0_FILTER_CNT_SHIFT)) & CMP_C0_FILTER_CNT_MASK) 796 #define CMP_C0_EN_MASK (0x100U) 797 #define CMP_C0_EN_SHIFT (8U) 798 /*! EN - Comparator Module Enable 799 * 0b0..Analog Comparator is disabled. 800 * 0b1..Analog Comparator is enabled. 801 */ 802 #define CMP_C0_EN(x) (((uint32_t)(((uint32_t)(x)) << CMP_C0_EN_SHIFT)) & CMP_C0_EN_MASK) 803 #define CMP_C0_OPE_MASK (0x200U) 804 #define CMP_C0_OPE_SHIFT (9U) 805 /*! OPE - Comparator Output Pin Enable 806 * 0b0..When OPE is 0, the comparator output (after window/filter settings dependent on software configuration) is not available to a packaged pin. 807 * 0b1..When OPE is 1, and if the software has configured the comparator to own a packaged pin, the comparator is available in a packaged pin. 808 */ 809 #define CMP_C0_OPE(x) (((uint32_t)(((uint32_t)(x)) << CMP_C0_OPE_SHIFT)) & CMP_C0_OPE_MASK) 810 #define CMP_C0_COS_MASK (0x400U) 811 #define CMP_C0_COS_SHIFT (10U) 812 /*! COS - Comparator Output Select 813 * 0b0..Set CMPO to equal COUT (filtered comparator output). 814 * 0b1..Set CMPO to equal COUTA (unfiltered comparator output). 815 */ 816 #define CMP_C0_COS(x) (((uint32_t)(((uint32_t)(x)) << CMP_C0_COS_SHIFT)) & CMP_C0_COS_MASK) 817 #define CMP_C0_INVT_MASK (0x800U) 818 #define CMP_C0_INVT_SHIFT (11U) 819 /*! INVT - Comparator invert 820 * 0b0..Does not invert the comparator output. 821 * 0b1..Inverts the comparator output. 822 */ 823 #define CMP_C0_INVT(x) (((uint32_t)(((uint32_t)(x)) << CMP_C0_INVT_SHIFT)) & CMP_C0_INVT_MASK) 824 #define CMP_C0_PMODE_MASK (0x1000U) 825 #define CMP_C0_PMODE_SHIFT (12U) 826 /*! PMODE - Power Mode Select 827 * 0b0..Low Speed (LS) comparison mode is selected. 828 * 0b1..High Speed (HS) comparison mode is selected, in VLPx mode, or Stop mode switched to Low Speed (LS) mode. 829 */ 830 #define CMP_C0_PMODE(x) (((uint32_t)(((uint32_t)(x)) << CMP_C0_PMODE_SHIFT)) & CMP_C0_PMODE_MASK) 831 #define CMP_C0_WE_MASK (0x4000U) 832 #define CMP_C0_WE_SHIFT (14U) 833 /*! WE - Windowing Enable 834 * 0b0..Windowing mode is not selected. 835 * 0b1..Windowing mode is selected. 836 */ 837 #define CMP_C0_WE(x) (((uint32_t)(((uint32_t)(x)) << CMP_C0_WE_SHIFT)) & CMP_C0_WE_MASK) 838 #define CMP_C0_SE_MASK (0x8000U) 839 #define CMP_C0_SE_SHIFT (15U) 840 /*! SE - Sample Enable 841 * 0b0..Sampling mode is not selected. 842 * 0b1..Sampling mode is selected. 843 */ 844 #define CMP_C0_SE(x) (((uint32_t)(((uint32_t)(x)) << CMP_C0_SE_SHIFT)) & CMP_C0_SE_MASK) 845 #define CMP_C0_FPR_MASK (0xFF0000U) 846 #define CMP_C0_FPR_SHIFT (16U) 847 /*! FPR - Filter Sample Period 848 */ 849 #define CMP_C0_FPR(x) (((uint32_t)(((uint32_t)(x)) << CMP_C0_FPR_SHIFT)) & CMP_C0_FPR_MASK) 850 #define CMP_C0_COUT_MASK (0x1000000U) 851 #define CMP_C0_COUT_SHIFT (24U) 852 /*! COUT - Analog Comparator Output 853 */ 854 #define CMP_C0_COUT(x) (((uint32_t)(((uint32_t)(x)) << CMP_C0_COUT_SHIFT)) & CMP_C0_COUT_MASK) 855 #define CMP_C0_CFF_MASK (0x2000000U) 856 #define CMP_C0_CFF_SHIFT (25U) 857 /*! CFF - Analog Comparator Flag Falling 858 * 0b0..A falling edge has not been detected on COUT. 859 * 0b1..A falling edge on COUT has occurred. 860 */ 861 #define CMP_C0_CFF(x) (((uint32_t)(((uint32_t)(x)) << CMP_C0_CFF_SHIFT)) & CMP_C0_CFF_MASK) 862 #define CMP_C0_CFR_MASK (0x4000000U) 863 #define CMP_C0_CFR_SHIFT (26U) 864 /*! CFR - Analog Comparator Flag Rising 865 * 0b0..A rising edge has not been detected on COUT. 866 * 0b1..A rising edge on COUT has occurred. 867 */ 868 #define CMP_C0_CFR(x) (((uint32_t)(((uint32_t)(x)) << CMP_C0_CFR_SHIFT)) & CMP_C0_CFR_MASK) 869 #define CMP_C0_IEF_MASK (0x8000000U) 870 #define CMP_C0_IEF_SHIFT (27U) 871 /*! IEF - Comparator Interrupt Enable Falling 872 * 0b0..Interrupt is disabled. 873 * 0b1..Interrupt is enabled. 874 */ 875 #define CMP_C0_IEF(x) (((uint32_t)(((uint32_t)(x)) << CMP_C0_IEF_SHIFT)) & CMP_C0_IEF_MASK) 876 #define CMP_C0_IER_MASK (0x10000000U) 877 #define CMP_C0_IER_SHIFT (28U) 878 /*! IER - Comparator Interrupt Enable Rising 879 * 0b0..Interrupt is disabled. 880 * 0b1..Interrupt is enabled. 881 */ 882 #define CMP_C0_IER(x) (((uint32_t)(((uint32_t)(x)) << CMP_C0_IER_SHIFT)) & CMP_C0_IER_MASK) 883 #define CMP_C0_DMAEN_MASK (0x40000000U) 884 #define CMP_C0_DMAEN_SHIFT (30U) 885 /*! DMAEN - DMA Enable 886 * 0b0..DMA is disabled. 887 * 0b1..DMA is enabled. 888 */ 889 #define CMP_C0_DMAEN(x) (((uint32_t)(((uint32_t)(x)) << CMP_C0_DMAEN_SHIFT)) & CMP_C0_DMAEN_MASK) 890 /*! @} */ 891 892 /*! @name C1 - CMP Control Register 1 */ 893 /*! @{ */ 894 #define CMP_C1_VOSEL_MASK (0xFFU) 895 #define CMP_C1_VOSEL_SHIFT (0U) 896 /*! VOSEL - DAC Output Voltage Select 897 */ 898 #define CMP_C1_VOSEL(x) (((uint32_t)(((uint32_t)(x)) << CMP_C1_VOSEL_SHIFT)) & CMP_C1_VOSEL_MASK) 899 #define CMP_C1_MSEL_MASK (0x700U) 900 #define CMP_C1_MSEL_SHIFT (8U) 901 /*! MSEL - Minus Input MUX Control 902 * 0b000..IN0 903 * 0b001..IN1 904 * 0b010..IN2 905 * 0b011..IN3 906 * 0b100..IN4 907 * 0b101..IN5 908 * 0b110..IN6 909 * 0b111..IN7 910 */ 911 #define CMP_C1_MSEL(x) (((uint32_t)(((uint32_t)(x)) << CMP_C1_MSEL_SHIFT)) & CMP_C1_MSEL_MASK) 912 #define CMP_C1_PSEL_MASK (0x3800U) 913 #define CMP_C1_PSEL_SHIFT (11U) 914 /*! PSEL - Plus Input MUX Control 915 * 0b000..IN0 916 * 0b001..IN1 917 * 0b010..IN2 918 * 0b011..IN3 919 * 0b100..IN4 920 * 0b101..IN5 921 * 0b110..IN6 922 * 0b111..IN7 923 */ 924 #define CMP_C1_PSEL(x) (((uint32_t)(((uint32_t)(x)) << CMP_C1_PSEL_SHIFT)) & CMP_C1_PSEL_MASK) 925 #define CMP_C1_VRSEL_MASK (0x4000U) 926 #define CMP_C1_VRSEL_SHIFT (14U) 927 /*! VRSEL - Supply Voltage Reference Source Select 928 * 0b0..Vin1 is selected as resistor ladder network supply reference Vin. 929 * 0b1..Vin2 is selected as resistor ladder network supply reference Vin. 930 */ 931 #define CMP_C1_VRSEL(x) (((uint32_t)(((uint32_t)(x)) << CMP_C1_VRSEL_SHIFT)) & CMP_C1_VRSEL_MASK) 932 #define CMP_C1_DACEN_MASK (0x8000U) 933 #define CMP_C1_DACEN_SHIFT (15U) 934 /*! DACEN - DAC Enable 935 * 0b0..DAC is disabled. 936 * 0b1..DAC is enabled. 937 */ 938 #define CMP_C1_DACEN(x) (((uint32_t)(((uint32_t)(x)) << CMP_C1_DACEN_SHIFT)) & CMP_C1_DACEN_MASK) 939 #define CMP_C1_CHN0_MASK (0x10000U) 940 #define CMP_C1_CHN0_SHIFT (16U) 941 /*! CHN0 - Channel 0 input enable 942 */ 943 #define CMP_C1_CHN0(x) (((uint32_t)(((uint32_t)(x)) << CMP_C1_CHN0_SHIFT)) & CMP_C1_CHN0_MASK) 944 #define CMP_C1_CHN1_MASK (0x20000U) 945 #define CMP_C1_CHN1_SHIFT (17U) 946 /*! CHN1 - Channel 1 input enable 947 */ 948 #define CMP_C1_CHN1(x) (((uint32_t)(((uint32_t)(x)) << CMP_C1_CHN1_SHIFT)) & CMP_C1_CHN1_MASK) 949 #define CMP_C1_CHN2_MASK (0x40000U) 950 #define CMP_C1_CHN2_SHIFT (18U) 951 /*! CHN2 - Channel 2 input enable 952 */ 953 #define CMP_C1_CHN2(x) (((uint32_t)(((uint32_t)(x)) << CMP_C1_CHN2_SHIFT)) & CMP_C1_CHN2_MASK) 954 #define CMP_C1_CHN3_MASK (0x80000U) 955 #define CMP_C1_CHN3_SHIFT (19U) 956 /*! CHN3 - Channel 3 input enable 957 */ 958 #define CMP_C1_CHN3(x) (((uint32_t)(((uint32_t)(x)) << CMP_C1_CHN3_SHIFT)) & CMP_C1_CHN3_MASK) 959 #define CMP_C1_CHN4_MASK (0x100000U) 960 #define CMP_C1_CHN4_SHIFT (20U) 961 /*! CHN4 - Channel 4 input enable 962 */ 963 #define CMP_C1_CHN4(x) (((uint32_t)(((uint32_t)(x)) << CMP_C1_CHN4_SHIFT)) & CMP_C1_CHN4_MASK) 964 #define CMP_C1_CHN5_MASK (0x200000U) 965 #define CMP_C1_CHN5_SHIFT (21U) 966 /*! CHN5 - Channel 5 input enable 967 */ 968 #define CMP_C1_CHN5(x) (((uint32_t)(((uint32_t)(x)) << CMP_C1_CHN5_SHIFT)) & CMP_C1_CHN5_MASK) 969 #define CMP_C1_CHN6_MASK (0x400000U) 970 #define CMP_C1_CHN6_SHIFT (22U) 971 /*! CHN6 - Channel 6 input enable 972 */ 973 #define CMP_C1_CHN6(x) (((uint32_t)(((uint32_t)(x)) << CMP_C1_CHN6_SHIFT)) & CMP_C1_CHN6_MASK) 974 #define CMP_C1_CHN7_MASK (0x800000U) 975 #define CMP_C1_CHN7_SHIFT (23U) 976 /*! CHN7 - Channel 7 input enable 977 */ 978 #define CMP_C1_CHN7(x) (((uint32_t)(((uint32_t)(x)) << CMP_C1_CHN7_SHIFT)) & CMP_C1_CHN7_MASK) 979 #define CMP_C1_INNSEL_MASK (0x3000000U) 980 #define CMP_C1_INNSEL_SHIFT (24U) 981 /*! INNSEL - Selection of the input to the negative port of the comparator 982 * 0b00..IN0, from the 8-bit DAC output 983 * 0b01..IN1, from the analog 8-1 mux 984 * 0b10..Reserved 985 * 0b11..Reserved 986 */ 987 #define CMP_C1_INNSEL(x) (((uint32_t)(((uint32_t)(x)) << CMP_C1_INNSEL_SHIFT)) & CMP_C1_INNSEL_MASK) 988 #define CMP_C1_INPSEL_MASK (0x18000000U) 989 #define CMP_C1_INPSEL_SHIFT (27U) 990 /*! INPSEL - Selection of the input to the positive port of the comparator 991 * 0b00..IN0, from the 8-bit DAC output 992 * 0b01..IN1, from the analog 8-1 mux 993 * 0b10..Reserved 994 * 0b11..Reserved 995 */ 996 #define CMP_C1_INPSEL(x) (((uint32_t)(((uint32_t)(x)) << CMP_C1_INPSEL_SHIFT)) & CMP_C1_INPSEL_MASK) 997 /*! @} */ 998 999 /*! @name C2 - CMP Control Register 2 */ 1000 /*! @{ */ 1001 #define CMP_C2_ACOn_MASK (0xFFU) 1002 #define CMP_C2_ACOn_SHIFT (0U) 1003 #define CMP_C2_ACOn(x) (((uint32_t)(((uint32_t)(x)) << CMP_C2_ACOn_SHIFT)) & CMP_C2_ACOn_MASK) 1004 #define CMP_C2_INITMOD_MASK (0x3F00U) 1005 #define CMP_C2_INITMOD_SHIFT (8U) 1006 /*! INITMOD - Comparator and DAC initialization delay modulus. 1007 * 0b000000..The modulus is set to 64 (same with 111111). 1008 */ 1009 #define CMP_C2_INITMOD(x) (((uint32_t)(((uint32_t)(x)) << CMP_C2_INITMOD_SHIFT)) & CMP_C2_INITMOD_MASK) 1010 #define CMP_C2_NSAM_MASK (0xC000U) 1011 #define CMP_C2_NSAM_SHIFT (14U) 1012 /*! NSAM - Number of sample clocks 1013 * 0b00..The comparison result is sampled as soon as the active channel is scanned in one round-robin clock. 1014 * 0b01..The sampling takes place 1 round-robin clock cycle after the next cycle of the round-robin clock. 1015 * 0b10..The sampling takes place 2 round-robin clock cycles after the next cycle of the round-robin clock. 1016 * 0b11..The sampling takes place 3 round-robin clock cycles after the next cycle of the round-robin clock. 1017 */ 1018 #define CMP_C2_NSAM(x) (((uint32_t)(((uint32_t)(x)) << CMP_C2_NSAM_SHIFT)) & CMP_C2_NSAM_MASK) 1019 #define CMP_C2_CH0F_MASK (0x10000U) 1020 #define CMP_C2_CH0F_SHIFT (16U) 1021 #define CMP_C2_CH0F(x) (((uint32_t)(((uint32_t)(x)) << CMP_C2_CH0F_SHIFT)) & CMP_C2_CH0F_MASK) 1022 #define CMP_C2_CH1F_MASK (0x20000U) 1023 #define CMP_C2_CH1F_SHIFT (17U) 1024 #define CMP_C2_CH1F(x) (((uint32_t)(((uint32_t)(x)) << CMP_C2_CH1F_SHIFT)) & CMP_C2_CH1F_MASK) 1025 #define CMP_C2_CH2F_MASK (0x40000U) 1026 #define CMP_C2_CH2F_SHIFT (18U) 1027 #define CMP_C2_CH2F(x) (((uint32_t)(((uint32_t)(x)) << CMP_C2_CH2F_SHIFT)) & CMP_C2_CH2F_MASK) 1028 #define CMP_C2_CH3F_MASK (0x80000U) 1029 #define CMP_C2_CH3F_SHIFT (19U) 1030 #define CMP_C2_CH3F(x) (((uint32_t)(((uint32_t)(x)) << CMP_C2_CH3F_SHIFT)) & CMP_C2_CH3F_MASK) 1031 #define CMP_C2_CH4F_MASK (0x100000U) 1032 #define CMP_C2_CH4F_SHIFT (20U) 1033 #define CMP_C2_CH4F(x) (((uint32_t)(((uint32_t)(x)) << CMP_C2_CH4F_SHIFT)) & CMP_C2_CH4F_MASK) 1034 #define CMP_C2_CH5F_MASK (0x200000U) 1035 #define CMP_C2_CH5F_SHIFT (21U) 1036 #define CMP_C2_CH5F(x) (((uint32_t)(((uint32_t)(x)) << CMP_C2_CH5F_SHIFT)) & CMP_C2_CH5F_MASK) 1037 #define CMP_C2_CH6F_MASK (0x400000U) 1038 #define CMP_C2_CH6F_SHIFT (22U) 1039 #define CMP_C2_CH6F(x) (((uint32_t)(((uint32_t)(x)) << CMP_C2_CH6F_SHIFT)) & CMP_C2_CH6F_MASK) 1040 #define CMP_C2_CH7F_MASK (0x800000U) 1041 #define CMP_C2_CH7F_SHIFT (23U) 1042 #define CMP_C2_CH7F(x) (((uint32_t)(((uint32_t)(x)) << CMP_C2_CH7F_SHIFT)) & CMP_C2_CH7F_MASK) 1043 #define CMP_C2_FXMXCH_MASK (0xE000000U) 1044 #define CMP_C2_FXMXCH_SHIFT (25U) 1045 /*! FXMXCH - Fixed channel selection 1046 * 0b000..Channel 0 is selected as the fixed reference input for the fixed mux port. 1047 * 0b001..Channel 1 is selected as the fixed reference input for the fixed mux port. 1048 * 0b010..Channel 2 is selected as the fixed reference input for the fixed mux port. 1049 * 0b011..Channel 3 is selected as the fixed reference input for the fixed mux port. 1050 * 0b100..Channel 4 is selected as the fixed reference input for the fixed mux port. 1051 * 0b101..Channel 5 is selected as the fixed reference input for the fixed mux port. 1052 * 0b110..Channel 6 is selected as the fixed reference input for the fixed mux port. 1053 * 0b111..Channel 7 is selected as the fixed reference input for the fixed mux port. 1054 */ 1055 #define CMP_C2_FXMXCH(x) (((uint32_t)(((uint32_t)(x)) << CMP_C2_FXMXCH_SHIFT)) & CMP_C2_FXMXCH_MASK) 1056 #define CMP_C2_FXMP_MASK (0x20000000U) 1057 #define CMP_C2_FXMP_SHIFT (29U) 1058 /*! FXMP - Fixed MUX Port 1059 * 0b0..The Plus port is fixed. Only the inputs to the Minus port are swept in each round. 1060 * 0b1..The Minus port is fixed. Only the inputs to the Plus port are swept in each round. 1061 */ 1062 #define CMP_C2_FXMP(x) (((uint32_t)(((uint32_t)(x)) << CMP_C2_FXMP_SHIFT)) & CMP_C2_FXMP_MASK) 1063 #define CMP_C2_RRIE_MASK (0x40000000U) 1064 #define CMP_C2_RRIE_SHIFT (30U) 1065 /*! RRIE - Round-Robin interrupt enable 1066 * 0b0..The round-robin interrupt is disabled. 1067 * 0b1..The round-robin interrupt is enabled when a comparison result changes from the last sample. 1068 */ 1069 #define CMP_C2_RRIE(x) (((uint32_t)(((uint32_t)(x)) << CMP_C2_RRIE_SHIFT)) & CMP_C2_RRIE_MASK) 1070 #define CMP_C2_RRE_MASK (0x80000000U) 1071 #define CMP_C2_RRE_SHIFT (31U) 1072 /*! RRE - Round-Robin Enable 1073 * 0b0..Round-robin operation is disabled. 1074 * 0b1..Round-robin operation is enabled. 1075 */ 1076 #define CMP_C2_RRE(x) (((uint32_t)(((uint32_t)(x)) << CMP_C2_RRE_SHIFT)) & CMP_C2_RRE_MASK) 1077 /*! @} */ 1078 1079 1080 /*! 1081 * @} 1082 */ /* end of group CMP_Register_Masks */ 1083 1084 1085 /* CMP - Peripheral instance base addresses */ 1086 /** Peripheral CMP0 base address */ 1087 #define CMP0_BASE (0x40073000u) 1088 /** Peripheral CMP0 base pointer */ 1089 #define CMP0 ((CMP_Type *)CMP0_BASE) 1090 /** Array initializer of CMP peripheral base addresses */ 1091 #define CMP_BASE_ADDRS { CMP0_BASE } 1092 /** Array initializer of CMP peripheral base pointers */ 1093 #define CMP_BASE_PTRS { CMP0 } 1094 /** Interrupt vectors for the CMP peripheral type */ 1095 #define CMP_IRQS { CMP0_IRQn } 1096 1097 /*! 1098 * @} 1099 */ /* end of group CMP_Peripheral_Access_Layer */ 1100 1101 1102 /* ---------------------------------------------------------------------------- 1103 -- CRC Peripheral Access Layer 1104 ---------------------------------------------------------------------------- */ 1105 1106 /*! 1107 * @addtogroup CRC_Peripheral_Access_Layer CRC Peripheral Access Layer 1108 * @{ 1109 */ 1110 1111 /** CRC - Register Layout Typedef */ 1112 typedef struct { 1113 union { /* offset: 0x0 */ 1114 struct { /* offset: 0x0 */ 1115 __IO uint8_t DATALL; /**< CRC_DATALL register., offset: 0x0 */ 1116 __IO uint8_t DATALU; /**< CRC_DATALU register., offset: 0x1 */ 1117 __IO uint8_t DATAHL; /**< CRC_DATAHL register., offset: 0x2 */ 1118 __IO uint8_t DATAHU; /**< CRC_DATAHU register., offset: 0x3 */ 1119 } ACCESS8BIT; 1120 struct { /* offset: 0x0 */ 1121 __IO uint16_t DATAL; /**< CRC_DATAL register., offset: 0x0 */ 1122 __IO uint16_t DATAH; /**< CRC_DATAH register., offset: 0x2 */ 1123 } ACCESS16BIT; 1124 __IO uint32_t DATA; /**< CRC Data register, offset: 0x0 */ 1125 }; 1126 union { /* offset: 0x4 */ 1127 struct { /* offset: 0x4 */ 1128 __IO uint8_t GPOLYLL; /**< CRC_GPOLYLL register., offset: 0x4 */ 1129 __IO uint8_t GPOLYLU; /**< CRC_GPOLYLU register., offset: 0x5 */ 1130 __IO uint8_t GPOLYHL; /**< CRC_GPOLYHL register., offset: 0x6 */ 1131 __IO uint8_t GPOLYHU; /**< CRC_GPOLYHU register., offset: 0x7 */ 1132 } GPOLY_ACCESS8BIT; 1133 struct { /* offset: 0x4 */ 1134 __IO uint16_t GPOLYL; /**< CRC_GPOLYL register., offset: 0x4 */ 1135 __IO uint16_t GPOLYH; /**< CRC_GPOLYH register., offset: 0x6 */ 1136 } GPOLY_ACCESS16BIT; 1137 __IO uint32_t GPOLY; /**< CRC Polynomial register, offset: 0x4 */ 1138 }; 1139 union { /* offset: 0x8 */ 1140 struct { /* offset: 0x8 */ 1141 uint8_t RESERVED_0[3]; 1142 __IO uint8_t CTRLHU; /**< CRC_CTRLHU register., offset: 0xB */ 1143 } CTRL_ACCESS8BIT; 1144 __IO uint32_t CTRL; /**< CRC Control register, offset: 0x8 */ 1145 }; 1146 } CRC_Type; 1147 1148 /* ---------------------------------------------------------------------------- 1149 -- CRC Register Masks 1150 ---------------------------------------------------------------------------- */ 1151 1152 /*! 1153 * @addtogroup CRC_Register_Masks CRC Register Masks 1154 * @{ 1155 */ 1156 1157 /*! @name DATALL - CRC_DATALL register. */ 1158 /*! @{ */ 1159 #define CRC_DATALL_DATALL_MASK (0xFFU) 1160 #define CRC_DATALL_DATALL_SHIFT (0U) 1161 /*! DATALL - CRCLL stores the first 8 bits of the 32 bit DATA 1162 */ 1163 #define CRC_DATALL_DATALL(x) (((uint8_t)(((uint8_t)(x)) << CRC_DATALL_DATALL_SHIFT)) & CRC_DATALL_DATALL_MASK) 1164 /*! @} */ 1165 1166 /*! @name DATALU - CRC_DATALU register. */ 1167 /*! @{ */ 1168 #define CRC_DATALU_DATALU_MASK (0xFFU) 1169 #define CRC_DATALU_DATALU_SHIFT (0U) 1170 /*! DATALU - DATALL stores the second 8 bits of the 32 bit CRC 1171 */ 1172 #define CRC_DATALU_DATALU(x) (((uint8_t)(((uint8_t)(x)) << CRC_DATALU_DATALU_SHIFT)) & CRC_DATALU_DATALU_MASK) 1173 /*! @} */ 1174 1175 /*! @name DATAHL - CRC_DATAHL register. */ 1176 /*! @{ */ 1177 #define CRC_DATAHL_DATAHL_MASK (0xFFU) 1178 #define CRC_DATAHL_DATAHL_SHIFT (0U) 1179 /*! DATAHL - DATAHL stores the third 8 bits of the 32 bit CRC 1180 */ 1181 #define CRC_DATAHL_DATAHL(x) (((uint8_t)(((uint8_t)(x)) << CRC_DATAHL_DATAHL_SHIFT)) & CRC_DATAHL_DATAHL_MASK) 1182 /*! @} */ 1183 1184 /*! @name DATAHU - CRC_DATAHU register. */ 1185 /*! @{ */ 1186 #define CRC_DATAHU_DATAHU_MASK (0xFFU) 1187 #define CRC_DATAHU_DATAHU_SHIFT (0U) 1188 /*! DATAHU - DATAHU stores the fourth 8 bits of the 32 bit CRC 1189 */ 1190 #define CRC_DATAHU_DATAHU(x) (((uint8_t)(((uint8_t)(x)) << CRC_DATAHU_DATAHU_SHIFT)) & CRC_DATAHU_DATAHU_MASK) 1191 /*! @} */ 1192 1193 /*! @name DATAL - CRC_DATAL register. */ 1194 /*! @{ */ 1195 #define CRC_DATAL_DATAL_MASK (0xFFFFU) 1196 #define CRC_DATAL_DATAL_SHIFT (0U) 1197 /*! DATAL - DATAL stores the lower 16 bits of the 16/32 bit CRC 1198 */ 1199 #define CRC_DATAL_DATAL(x) (((uint16_t)(((uint16_t)(x)) << CRC_DATAL_DATAL_SHIFT)) & CRC_DATAL_DATAL_MASK) 1200 /*! @} */ 1201 1202 /*! @name DATAH - CRC_DATAH register. */ 1203 /*! @{ */ 1204 #define CRC_DATAH_DATAH_MASK (0xFFFFU) 1205 #define CRC_DATAH_DATAH_SHIFT (0U) 1206 /*! DATAH - DATAH stores the high 16 bits of the 16/32 bit CRC 1207 */ 1208 #define CRC_DATAH_DATAH(x) (((uint16_t)(((uint16_t)(x)) << CRC_DATAH_DATAH_SHIFT)) & CRC_DATAH_DATAH_MASK) 1209 /*! @} */ 1210 1211 /*! @name DATA - CRC Data register */ 1212 /*! @{ */ 1213 #define CRC_DATA_LL_MASK (0xFFU) 1214 #define CRC_DATA_LL_SHIFT (0U) 1215 /*! LL - CRC Low Lower Byte 1216 */ 1217 #define CRC_DATA_LL(x) (((uint32_t)(((uint32_t)(x)) << CRC_DATA_LL_SHIFT)) & CRC_DATA_LL_MASK) 1218 #define CRC_DATA_LU_MASK (0xFF00U) 1219 #define CRC_DATA_LU_SHIFT (8U) 1220 /*! LU - CRC Low Upper Byte 1221 */ 1222 #define CRC_DATA_LU(x) (((uint32_t)(((uint32_t)(x)) << CRC_DATA_LU_SHIFT)) & CRC_DATA_LU_MASK) 1223 #define CRC_DATA_HL_MASK (0xFF0000U) 1224 #define CRC_DATA_HL_SHIFT (16U) 1225 /*! HL - CRC High Lower Byte 1226 */ 1227 #define CRC_DATA_HL(x) (((uint32_t)(((uint32_t)(x)) << CRC_DATA_HL_SHIFT)) & CRC_DATA_HL_MASK) 1228 #define CRC_DATA_HU_MASK (0xFF000000U) 1229 #define CRC_DATA_HU_SHIFT (24U) 1230 /*! HU - CRC High Upper Byte 1231 */ 1232 #define CRC_DATA_HU(x) (((uint32_t)(((uint32_t)(x)) << CRC_DATA_HU_SHIFT)) & CRC_DATA_HU_MASK) 1233 /*! @} */ 1234 1235 /*! @name GPOLYLL - CRC_GPOLYLL register. */ 1236 /*! @{ */ 1237 #define CRC_GPOLYLL_GPOLYLL_MASK (0xFFU) 1238 #define CRC_GPOLYLL_GPOLYLL_SHIFT (0U) 1239 /*! GPOLYLL - POLYLL stores the first 8 bits of the 32 bit CRC 1240 */ 1241 #define CRC_GPOLYLL_GPOLYLL(x) (((uint8_t)(((uint8_t)(x)) << CRC_GPOLYLL_GPOLYLL_SHIFT)) & CRC_GPOLYLL_GPOLYLL_MASK) 1242 /*! @} */ 1243 1244 /*! @name GPOLYLU - CRC_GPOLYLU register. */ 1245 /*! @{ */ 1246 #define CRC_GPOLYLU_GPOLYLU_MASK (0xFFU) 1247 #define CRC_GPOLYLU_GPOLYLU_SHIFT (0U) 1248 /*! GPOLYLU - POLYLL stores the second 8 bits of the 32 bit CRC 1249 */ 1250 #define CRC_GPOLYLU_GPOLYLU(x) (((uint8_t)(((uint8_t)(x)) << CRC_GPOLYLU_GPOLYLU_SHIFT)) & CRC_GPOLYLU_GPOLYLU_MASK) 1251 /*! @} */ 1252 1253 /*! @name GPOLYHL - CRC_GPOLYHL register. */ 1254 /*! @{ */ 1255 #define CRC_GPOLYHL_GPOLYHL_MASK (0xFFU) 1256 #define CRC_GPOLYHL_GPOLYHL_SHIFT (0U) 1257 /*! GPOLYHL - POLYHL stores the third 8 bits of the 32 bit CRC 1258 */ 1259 #define CRC_GPOLYHL_GPOLYHL(x) (((uint8_t)(((uint8_t)(x)) << CRC_GPOLYHL_GPOLYHL_SHIFT)) & CRC_GPOLYHL_GPOLYHL_MASK) 1260 /*! @} */ 1261 1262 /*! @name GPOLYHU - CRC_GPOLYHU register. */ 1263 /*! @{ */ 1264 #define CRC_GPOLYHU_GPOLYHU_MASK (0xFFU) 1265 #define CRC_GPOLYHU_GPOLYHU_SHIFT (0U) 1266 /*! GPOLYHU - POLYHU stores the fourth 8 bits of the 32 bit CRC 1267 */ 1268 #define CRC_GPOLYHU_GPOLYHU(x) (((uint8_t)(((uint8_t)(x)) << CRC_GPOLYHU_GPOLYHU_SHIFT)) & CRC_GPOLYHU_GPOLYHU_MASK) 1269 /*! @} */ 1270 1271 /*! @name GPOLYL - CRC_GPOLYL register. */ 1272 /*! @{ */ 1273 #define CRC_GPOLYL_GPOLYL_MASK (0xFFFFU) 1274 #define CRC_GPOLYL_GPOLYL_SHIFT (0U) 1275 /*! GPOLYL - POLYL stores the lower 16 bits of the 16/32 bit CRC polynomial value 1276 */ 1277 #define CRC_GPOLYL_GPOLYL(x) (((uint16_t)(((uint16_t)(x)) << CRC_GPOLYL_GPOLYL_SHIFT)) & CRC_GPOLYL_GPOLYL_MASK) 1278 /*! @} */ 1279 1280 /*! @name GPOLYH - CRC_GPOLYH register. */ 1281 /*! @{ */ 1282 #define CRC_GPOLYH_GPOLYH_MASK (0xFFFFU) 1283 #define CRC_GPOLYH_GPOLYH_SHIFT (0U) 1284 /*! GPOLYH - POLYH stores the high 16 bits of the 16/32 bit CRC polynomial value 1285 */ 1286 #define CRC_GPOLYH_GPOLYH(x) (((uint16_t)(((uint16_t)(x)) << CRC_GPOLYH_GPOLYH_SHIFT)) & CRC_GPOLYH_GPOLYH_MASK) 1287 /*! @} */ 1288 1289 /*! @name GPOLY - CRC Polynomial register */ 1290 /*! @{ */ 1291 #define CRC_GPOLY_LOW_MASK (0xFFFFU) 1292 #define CRC_GPOLY_LOW_SHIFT (0U) 1293 /*! LOW - Low Polynominal Half-word 1294 */ 1295 #define CRC_GPOLY_LOW(x) (((uint32_t)(((uint32_t)(x)) << CRC_GPOLY_LOW_SHIFT)) & CRC_GPOLY_LOW_MASK) 1296 #define CRC_GPOLY_HIGH_MASK (0xFFFF0000U) 1297 #define CRC_GPOLY_HIGH_SHIFT (16U) 1298 /*! HIGH - High Polynominal Half-word 1299 */ 1300 #define CRC_GPOLY_HIGH(x) (((uint32_t)(((uint32_t)(x)) << CRC_GPOLY_HIGH_SHIFT)) & CRC_GPOLY_HIGH_MASK) 1301 /*! @} */ 1302 1303 /*! @name CTRLHU - CRC_CTRLHU register. */ 1304 /*! @{ */ 1305 #define CRC_CTRLHU_TCRC_MASK (0x1U) 1306 #define CRC_CTRLHU_TCRC_SHIFT (0U) 1307 /*! TCRC 1308 * 0b0..16-bit CRC protocol. 1309 * 0b1..32-bit CRC protocol. 1310 */ 1311 #define CRC_CTRLHU_TCRC(x) (((uint8_t)(((uint8_t)(x)) << CRC_CTRLHU_TCRC_SHIFT)) & CRC_CTRLHU_TCRC_MASK) 1312 #define CRC_CTRLHU_WAS_MASK (0x2U) 1313 #define CRC_CTRLHU_WAS_SHIFT (1U) 1314 /*! WAS 1315 * 0b0..Writes to CRC data register are data values. 1316 * 0b1..Writes to CRC data reguster are seed values. 1317 */ 1318 #define CRC_CTRLHU_WAS(x) (((uint8_t)(((uint8_t)(x)) << CRC_CTRLHU_WAS_SHIFT)) & CRC_CTRLHU_WAS_MASK) 1319 #define CRC_CTRLHU_FXOR_MASK (0x4U) 1320 #define CRC_CTRLHU_FXOR_SHIFT (2U) 1321 /*! FXOR 1322 * 0b0..No XOR on reading. 1323 * 0b1..Invert or complement the read value of CRC data register. 1324 */ 1325 #define CRC_CTRLHU_FXOR(x) (((uint8_t)(((uint8_t)(x)) << CRC_CTRLHU_FXOR_SHIFT)) & CRC_CTRLHU_FXOR_MASK) 1326 #define CRC_CTRLHU_TOTR_MASK (0x30U) 1327 #define CRC_CTRLHU_TOTR_SHIFT (4U) 1328 /*! TOTR 1329 * 0b00..No Transposition. 1330 * 0b01..Bits in bytes are transposed, bytes are not transposed. 1331 * 0b10..Both bits in bytes and bytes are transposed. 1332 * 0b11..Only bytes are transposed; no bits in a byte are transposed. 1333 */ 1334 #define CRC_CTRLHU_TOTR(x) (((uint8_t)(((uint8_t)(x)) << CRC_CTRLHU_TOTR_SHIFT)) & CRC_CTRLHU_TOTR_MASK) 1335 #define CRC_CTRLHU_TOT_MASK (0xC0U) 1336 #define CRC_CTRLHU_TOT_SHIFT (6U) 1337 /*! TOT 1338 * 0b00..No Transposition. 1339 * 0b01..Bits in bytes are transposed, bytes are not transposed. 1340 * 0b10..Both bits in bytes and bytes are transposed. 1341 * 0b11..Only bytes are transposed; no bits in a byte are transposed. 1342 */ 1343 #define CRC_CTRLHU_TOT(x) (((uint8_t)(((uint8_t)(x)) << CRC_CTRLHU_TOT_SHIFT)) & CRC_CTRLHU_TOT_MASK) 1344 /*! @} */ 1345 1346 /*! @name CTRL - CRC Control register */ 1347 /*! @{ */ 1348 #define CRC_CTRL_TCRC_MASK (0x1000000U) 1349 #define CRC_CTRL_TCRC_SHIFT (24U) 1350 /*! TCRC 1351 * 0b0..16-bit CRC protocol. 1352 * 0b1..32-bit CRC protocol. 1353 */ 1354 #define CRC_CTRL_TCRC(x) (((uint32_t)(((uint32_t)(x)) << CRC_CTRL_TCRC_SHIFT)) & CRC_CTRL_TCRC_MASK) 1355 #define CRC_CTRL_WAS_MASK (0x2000000U) 1356 #define CRC_CTRL_WAS_SHIFT (25U) 1357 /*! WAS - Write CRC Data Register As Seed 1358 * 0b0..Writes to the CRC data register are data values. 1359 * 0b1..Writes to the CRC data register are seed values. 1360 */ 1361 #define CRC_CTRL_WAS(x) (((uint32_t)(((uint32_t)(x)) << CRC_CTRL_WAS_SHIFT)) & CRC_CTRL_WAS_MASK) 1362 #define CRC_CTRL_FXOR_MASK (0x4000000U) 1363 #define CRC_CTRL_FXOR_SHIFT (26U) 1364 /*! FXOR - Complement Read Of CRC Data Register 1365 * 0b0..No XOR on reading. 1366 * 0b1..Invert or complement the read value of the CRC Data register. 1367 */ 1368 #define CRC_CTRL_FXOR(x) (((uint32_t)(((uint32_t)(x)) << CRC_CTRL_FXOR_SHIFT)) & CRC_CTRL_FXOR_MASK) 1369 #define CRC_CTRL_TOTR_MASK (0x30000000U) 1370 #define CRC_CTRL_TOTR_SHIFT (28U) 1371 /*! TOTR - Type Of Transpose For Read 1372 * 0b00..No transposition. 1373 * 0b01..Bits in bytes are transposed; bytes are not transposed. 1374 * 0b10..Both bits in bytes and bytes are transposed. 1375 * 0b11..Only bytes are transposed; no bits in a byte are transposed. 1376 */ 1377 #define CRC_CTRL_TOTR(x) (((uint32_t)(((uint32_t)(x)) << CRC_CTRL_TOTR_SHIFT)) & CRC_CTRL_TOTR_MASK) 1378 #define CRC_CTRL_TOT_MASK (0xC0000000U) 1379 #define CRC_CTRL_TOT_SHIFT (30U) 1380 /*! TOT - Type Of Transpose For Writes 1381 * 0b00..No transposition. 1382 * 0b01..Bits in bytes are transposed; bytes are not transposed. 1383 * 0b10..Both bits in bytes and bytes are transposed. 1384 * 0b11..Only bytes are transposed; no bits in a byte are transposed. 1385 */ 1386 #define CRC_CTRL_TOT(x) (((uint32_t)(((uint32_t)(x)) << CRC_CTRL_TOT_SHIFT)) & CRC_CTRL_TOT_MASK) 1387 /*! @} */ 1388 1389 1390 /*! 1391 * @} 1392 */ /* end of group CRC_Register_Masks */ 1393 1394 1395 /* CRC - Peripheral instance base addresses */ 1396 /** Peripheral CRC base address */ 1397 #define CRC_BASE (0x40032000u) 1398 /** Peripheral CRC base pointer */ 1399 #define CRC0 ((CRC_Type *)CRC_BASE) 1400 /** Array initializer of CRC peripheral base addresses */ 1401 #define CRC_BASE_ADDRS { CRC_BASE } 1402 /** Array initializer of CRC peripheral base pointers */ 1403 #define CRC_BASE_PTRS { CRC0 } 1404 1405 /*! 1406 * @} 1407 */ /* end of group CRC_Peripheral_Access_Layer */ 1408 1409 1410 /* ---------------------------------------------------------------------------- 1411 -- EWM Peripheral Access Layer 1412 ---------------------------------------------------------------------------- */ 1413 1414 /*! 1415 * @addtogroup EWM_Peripheral_Access_Layer EWM Peripheral Access Layer 1416 * @{ 1417 */ 1418 1419 /** EWM - Register Layout Typedef */ 1420 typedef struct { 1421 __IO uint8_t CTRL; /**< Control Register, offset: 0x0 */ 1422 __O uint8_t SERV; /**< Service Register, offset: 0x1 */ 1423 __IO uint8_t CMPL; /**< Compare Low Register, offset: 0x2 */ 1424 __IO uint8_t CMPH; /**< Compare High Register, offset: 0x3 */ 1425 uint8_t RESERVED_0[1]; 1426 __IO uint8_t CLKPRESCALER; /**< Clock Prescaler Register, offset: 0x5 */ 1427 } EWM_Type; 1428 1429 /* ---------------------------------------------------------------------------- 1430 -- EWM Register Masks 1431 ---------------------------------------------------------------------------- */ 1432 1433 /*! 1434 * @addtogroup EWM_Register_Masks EWM Register Masks 1435 * @{ 1436 */ 1437 1438 /*! @name CTRL - Control Register */ 1439 /*! @{ */ 1440 #define EWM_CTRL_EWMEN_MASK (0x1U) 1441 #define EWM_CTRL_EWMEN_SHIFT (0U) 1442 /*! EWMEN - EWM enable. 1443 */ 1444 #define EWM_CTRL_EWMEN(x) (((uint8_t)(((uint8_t)(x)) << EWM_CTRL_EWMEN_SHIFT)) & EWM_CTRL_EWMEN_MASK) 1445 #define EWM_CTRL_ASSIN_MASK (0x2U) 1446 #define EWM_CTRL_ASSIN_SHIFT (1U) 1447 /*! ASSIN - EWM_in's Assertion State Select. 1448 */ 1449 #define EWM_CTRL_ASSIN(x) (((uint8_t)(((uint8_t)(x)) << EWM_CTRL_ASSIN_SHIFT)) & EWM_CTRL_ASSIN_MASK) 1450 #define EWM_CTRL_INEN_MASK (0x4U) 1451 #define EWM_CTRL_INEN_SHIFT (2U) 1452 /*! INEN - Input Enable. 1453 */ 1454 #define EWM_CTRL_INEN(x) (((uint8_t)(((uint8_t)(x)) << EWM_CTRL_INEN_SHIFT)) & EWM_CTRL_INEN_MASK) 1455 #define EWM_CTRL_INTEN_MASK (0x8U) 1456 #define EWM_CTRL_INTEN_SHIFT (3U) 1457 /*! INTEN - Interrupt Enable. 1458 */ 1459 #define EWM_CTRL_INTEN(x) (((uint8_t)(((uint8_t)(x)) << EWM_CTRL_INTEN_SHIFT)) & EWM_CTRL_INTEN_MASK) 1460 /*! @} */ 1461 1462 /*! @name SERV - Service Register */ 1463 /*! @{ */ 1464 #define EWM_SERV_SERVICE_MASK (0xFFU) 1465 #define EWM_SERV_SERVICE_SHIFT (0U) 1466 #define EWM_SERV_SERVICE(x) (((uint8_t)(((uint8_t)(x)) << EWM_SERV_SERVICE_SHIFT)) & EWM_SERV_SERVICE_MASK) 1467 /*! @} */ 1468 1469 /*! @name CMPL - Compare Low Register */ 1470 /*! @{ */ 1471 #define EWM_CMPL_COMPAREL_MASK (0xFFU) 1472 #define EWM_CMPL_COMPAREL_SHIFT (0U) 1473 #define EWM_CMPL_COMPAREL(x) (((uint8_t)(((uint8_t)(x)) << EWM_CMPL_COMPAREL_SHIFT)) & EWM_CMPL_COMPAREL_MASK) 1474 /*! @} */ 1475 1476 /*! @name CMPH - Compare High Register */ 1477 /*! @{ */ 1478 #define EWM_CMPH_COMPAREH_MASK (0xFFU) 1479 #define EWM_CMPH_COMPAREH_SHIFT (0U) 1480 #define EWM_CMPH_COMPAREH(x) (((uint8_t)(((uint8_t)(x)) << EWM_CMPH_COMPAREH_SHIFT)) & EWM_CMPH_COMPAREH_MASK) 1481 /*! @} */ 1482 1483 /*! @name CLKPRESCALER - Clock Prescaler Register */ 1484 /*! @{ */ 1485 #define EWM_CLKPRESCALER_CLK_DIV_MASK (0xFFU) 1486 #define EWM_CLKPRESCALER_CLK_DIV_SHIFT (0U) 1487 #define EWM_CLKPRESCALER_CLK_DIV(x) (((uint8_t)(((uint8_t)(x)) << EWM_CLKPRESCALER_CLK_DIV_SHIFT)) & EWM_CLKPRESCALER_CLK_DIV_MASK) 1488 /*! @} */ 1489 1490 1491 /*! 1492 * @} 1493 */ /* end of group EWM_Register_Masks */ 1494 1495 1496 /* EWM - Peripheral instance base addresses */ 1497 /** Peripheral EWM base address */ 1498 #define EWM_BASE (0x40061000u) 1499 /** Peripheral EWM base pointer */ 1500 #define EWM ((EWM_Type *)EWM_BASE) 1501 /** Array initializer of EWM peripheral base addresses */ 1502 #define EWM_BASE_ADDRS { EWM_BASE } 1503 /** Array initializer of EWM peripheral base pointers */ 1504 #define EWM_BASE_PTRS { EWM } 1505 /** Interrupt vectors for the EWM peripheral type */ 1506 #define EWM_IRQS { WDOG_EWM_IRQn } 1507 1508 /*! 1509 * @} 1510 */ /* end of group EWM_Peripheral_Access_Layer */ 1511 1512 1513 /* ---------------------------------------------------------------------------- 1514 -- FGPIO Peripheral Access Layer 1515 ---------------------------------------------------------------------------- */ 1516 1517 /*! 1518 * @addtogroup FGPIO_Peripheral_Access_Layer FGPIO Peripheral Access Layer 1519 * @{ 1520 */ 1521 1522 /** FGPIO - Register Layout Typedef */ 1523 typedef struct { 1524 __IO uint32_t PDOR; /**< Port Data Output Register, offset: 0x0 */ 1525 __O uint32_t PSOR; /**< Port Set Output Register, offset: 0x4 */ 1526 __O uint32_t PCOR; /**< Port Clear Output Register, offset: 0x8 */ 1527 __O uint32_t PTOR; /**< Port Toggle Output Register, offset: 0xC */ 1528 __I uint32_t PDIR; /**< Port Data Input Register, offset: 0x10 */ 1529 __IO uint32_t PDDR; /**< Port Data Direction Register, offset: 0x14 */ 1530 } FGPIO_Type; 1531 1532 /* ---------------------------------------------------------------------------- 1533 -- FGPIO Register Masks 1534 ---------------------------------------------------------------------------- */ 1535 1536 /*! 1537 * @addtogroup FGPIO_Register_Masks FGPIO Register Masks 1538 * @{ 1539 */ 1540 1541 /*! @name PDOR - Port Data Output Register */ 1542 /*! @{ */ 1543 #define FGPIO_PDOR_PDO_MASK (0xFFFFFFFFU) 1544 #define FGPIO_PDOR_PDO_SHIFT (0U) 1545 /*! PDO - Port Data Output 1546 * 0b00000000000000000000000000000000..Logic level 0 is driven on pin, provided pin is configured for general-purpose output. 1547 * 0b00000000000000000000000000000001..Logic level 1 is driven on pin, provided pin is configured for general-purpose output. 1548 */ 1549 #define FGPIO_PDOR_PDO(x) (((uint32_t)(((uint32_t)(x)) << FGPIO_PDOR_PDO_SHIFT)) & FGPIO_PDOR_PDO_MASK) 1550 /*! @} */ 1551 1552 /*! @name PSOR - Port Set Output Register */ 1553 /*! @{ */ 1554 #define FGPIO_PSOR_PTSO_MASK (0xFFFFFFFFU) 1555 #define FGPIO_PSOR_PTSO_SHIFT (0U) 1556 /*! PTSO - Port Set Output 1557 * 0b00000000000000000000000000000000..Corresponding bit in PDORn does not change. 1558 * 0b00000000000000000000000000000001..Corresponding bit in PDORn is set to logic 1. 1559 */ 1560 #define FGPIO_PSOR_PTSO(x) (((uint32_t)(((uint32_t)(x)) << FGPIO_PSOR_PTSO_SHIFT)) & FGPIO_PSOR_PTSO_MASK) 1561 /*! @} */ 1562 1563 /*! @name PCOR - Port Clear Output Register */ 1564 /*! @{ */ 1565 #define FGPIO_PCOR_PTCO_MASK (0xFFFFFFFFU) 1566 #define FGPIO_PCOR_PTCO_SHIFT (0U) 1567 /*! PTCO - Port Clear Output 1568 * 0b00000000000000000000000000000000..Corresponding bit in PDORn does not change. 1569 * 0b00000000000000000000000000000001..Corresponding bit in PDORn is cleared to logic 0. 1570 */ 1571 #define FGPIO_PCOR_PTCO(x) (((uint32_t)(((uint32_t)(x)) << FGPIO_PCOR_PTCO_SHIFT)) & FGPIO_PCOR_PTCO_MASK) 1572 /*! @} */ 1573 1574 /*! @name PTOR - Port Toggle Output Register */ 1575 /*! @{ */ 1576 #define FGPIO_PTOR_PTTO_MASK (0xFFFFFFFFU) 1577 #define FGPIO_PTOR_PTTO_SHIFT (0U) 1578 /*! PTTO - Port Toggle Output 1579 * 0b00000000000000000000000000000000..Corresponding bit in PDORn does not change. 1580 * 0b00000000000000000000000000000001..Corresponding bit in PDORn is set to the inverse of its existing logic state. 1581 */ 1582 #define FGPIO_PTOR_PTTO(x) (((uint32_t)(((uint32_t)(x)) << FGPIO_PTOR_PTTO_SHIFT)) & FGPIO_PTOR_PTTO_MASK) 1583 /*! @} */ 1584 1585 /*! @name PDIR - Port Data Input Register */ 1586 /*! @{ */ 1587 #define FGPIO_PDIR_PDI_MASK (0xFFFFFFFFU) 1588 #define FGPIO_PDIR_PDI_SHIFT (0U) 1589 /*! PDI - Port Data Input 1590 * 0b00000000000000000000000000000000..Pin logic level is logic 0, or is not configured for use by digital function. 1591 * 0b00000000000000000000000000000001..Pin logic level is logic 1. 1592 */ 1593 #define FGPIO_PDIR_PDI(x) (((uint32_t)(((uint32_t)(x)) << FGPIO_PDIR_PDI_SHIFT)) & FGPIO_PDIR_PDI_MASK) 1594 /*! @} */ 1595 1596 /*! @name PDDR - Port Data Direction Register */ 1597 /*! @{ */ 1598 #define FGPIO_PDDR_PDD_MASK (0xFFFFFFFFU) 1599 #define FGPIO_PDDR_PDD_SHIFT (0U) 1600 /*! PDD - Port Data Direction 1601 * 0b00000000000000000000000000000000..Pin is configured as general-purpose input, for the GPIO function. 1602 * 0b00000000000000000000000000000001..Pin is configured as general-purpose output, for the GPIO function. 1603 */ 1604 #define FGPIO_PDDR_PDD(x) (((uint32_t)(((uint32_t)(x)) << FGPIO_PDDR_PDD_SHIFT)) & FGPIO_PDDR_PDD_MASK) 1605 /*! @} */ 1606 1607 1608 /*! 1609 * @} 1610 */ /* end of group FGPIO_Register_Masks */ 1611 1612 1613 /* FGPIO - Peripheral instance base addresses */ 1614 /** Peripheral FGPIOA base address */ 1615 #define FGPIOA_BASE (0xF8000000u) 1616 /** Peripheral FGPIOA base pointer */ 1617 #define FGPIOA ((FGPIO_Type *)FGPIOA_BASE) 1618 /** Peripheral FGPIOB base address */ 1619 #define FGPIOB_BASE (0xF8000040u) 1620 /** Peripheral FGPIOB base pointer */ 1621 #define FGPIOB ((FGPIO_Type *)FGPIOB_BASE) 1622 /** Peripheral FGPIOC base address */ 1623 #define FGPIOC_BASE (0xF8000080u) 1624 /** Peripheral FGPIOC base pointer */ 1625 #define FGPIOC ((FGPIO_Type *)FGPIOC_BASE) 1626 /** Peripheral FGPIOD base address */ 1627 #define FGPIOD_BASE (0xF80000C0u) 1628 /** Peripheral FGPIOD base pointer */ 1629 #define FGPIOD ((FGPIO_Type *)FGPIOD_BASE) 1630 /** Peripheral FGPIOE base address */ 1631 #define FGPIOE_BASE (0xF8000100u) 1632 /** Peripheral FGPIOE base pointer */ 1633 #define FGPIOE ((FGPIO_Type *)FGPIOE_BASE) 1634 /** Array initializer of FGPIO peripheral base addresses */ 1635 #define FGPIO_BASE_ADDRS { FGPIOA_BASE, FGPIOB_BASE, FGPIOC_BASE, FGPIOD_BASE, FGPIOE_BASE } 1636 /** Array initializer of FGPIO peripheral base pointers */ 1637 #define FGPIO_BASE_PTRS { FGPIOA, FGPIOB, FGPIOC, FGPIOD, FGPIOE } 1638 1639 /*! 1640 * @} 1641 */ /* end of group FGPIO_Peripheral_Access_Layer */ 1642 1643 1644 /* ---------------------------------------------------------------------------- 1645 -- FTFA Peripheral Access Layer 1646 ---------------------------------------------------------------------------- */ 1647 1648 /*! 1649 * @addtogroup FTFA_Peripheral_Access_Layer FTFA Peripheral Access Layer 1650 * @{ 1651 */ 1652 1653 /** FTFA - Register Layout Typedef */ 1654 typedef struct { 1655 __IO uint8_t FSTAT; /**< Flash Status Register, offset: 0x0 */ 1656 __IO uint8_t FCNFG; /**< Flash Configuration Register, offset: 0x1 */ 1657 __I uint8_t FSEC; /**< Flash Security Register, offset: 0x2 */ 1658 __I uint8_t FOPT; /**< Flash Option Register, offset: 0x3 */ 1659 __IO uint8_t FCCOB3; /**< Flash Common Command Object Registers, offset: 0x4 */ 1660 __IO uint8_t FCCOB2; /**< Flash Common Command Object Registers, offset: 0x5 */ 1661 __IO uint8_t FCCOB1; /**< Flash Common Command Object Registers, offset: 0x6 */ 1662 __IO uint8_t FCCOB0; /**< Flash Common Command Object Registers, offset: 0x7 */ 1663 __IO uint8_t FCCOB7; /**< Flash Common Command Object Registers, offset: 0x8 */ 1664 __IO uint8_t FCCOB6; /**< Flash Common Command Object Registers, offset: 0x9 */ 1665 __IO uint8_t FCCOB5; /**< Flash Common Command Object Registers, offset: 0xA */ 1666 __IO uint8_t FCCOB4; /**< Flash Common Command Object Registers, offset: 0xB */ 1667 __IO uint8_t FCCOBB; /**< Flash Common Command Object Registers, offset: 0xC */ 1668 __IO uint8_t FCCOBA; /**< Flash Common Command Object Registers, offset: 0xD */ 1669 __IO uint8_t FCCOB9; /**< Flash Common Command Object Registers, offset: 0xE */ 1670 __IO uint8_t FCCOB8; /**< Flash Common Command Object Registers, offset: 0xF */ 1671 __IO uint8_t FPROT3; /**< Program Flash Protection Registers, offset: 0x10 */ 1672 __IO uint8_t FPROT2; /**< Program Flash Protection Registers, offset: 0x11 */ 1673 __IO uint8_t FPROT1; /**< Program Flash Protection Registers, offset: 0x12 */ 1674 __IO uint8_t FPROT0; /**< Program Flash Protection Registers, offset: 0x13 */ 1675 } FTFA_Type; 1676 1677 /* ---------------------------------------------------------------------------- 1678 -- FTFA Register Masks 1679 ---------------------------------------------------------------------------- */ 1680 1681 /*! 1682 * @addtogroup FTFA_Register_Masks FTFA Register Masks 1683 * @{ 1684 */ 1685 1686 /*! @name FSTAT - Flash Status Register */ 1687 /*! @{ */ 1688 #define FTFA_FSTAT_MGSTAT0_MASK (0x1U) 1689 #define FTFA_FSTAT_MGSTAT0_SHIFT (0U) 1690 /*! MGSTAT0 - Memory Controller Command Completion Status Flag 1691 */ 1692 #define FTFA_FSTAT_MGSTAT0(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FSTAT_MGSTAT0_SHIFT)) & FTFA_FSTAT_MGSTAT0_MASK) 1693 #define FTFA_FSTAT_FPVIOL_MASK (0x10U) 1694 #define FTFA_FSTAT_FPVIOL_SHIFT (4U) 1695 /*! FPVIOL - Flash Protection Violation Flag 1696 * 0b0..No protection violation detected 1697 * 0b1..Protection violation detected 1698 */ 1699 #define FTFA_FSTAT_FPVIOL(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FSTAT_FPVIOL_SHIFT)) & FTFA_FSTAT_FPVIOL_MASK) 1700 #define FTFA_FSTAT_ACCERR_MASK (0x20U) 1701 #define FTFA_FSTAT_ACCERR_SHIFT (5U) 1702 /*! ACCERR - Flash Access Error Flag 1703 * 0b0..No access error detected 1704 * 0b1..Access error detected 1705 */ 1706 #define FTFA_FSTAT_ACCERR(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FSTAT_ACCERR_SHIFT)) & FTFA_FSTAT_ACCERR_MASK) 1707 #define FTFA_FSTAT_RDCOLERR_MASK (0x40U) 1708 #define FTFA_FSTAT_RDCOLERR_SHIFT (6U) 1709 /*! RDCOLERR - Flash Read Collision Error Flag 1710 * 0b0..No collision error detected 1711 * 0b1..Collision error detected 1712 */ 1713 #define FTFA_FSTAT_RDCOLERR(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FSTAT_RDCOLERR_SHIFT)) & FTFA_FSTAT_RDCOLERR_MASK) 1714 #define FTFA_FSTAT_CCIF_MASK (0x80U) 1715 #define FTFA_FSTAT_CCIF_SHIFT (7U) 1716 /*! CCIF - Command Complete Interrupt Flag 1717 * 0b0..Flash command in progress 1718 * 0b1..Flash command has completed 1719 */ 1720 #define FTFA_FSTAT_CCIF(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FSTAT_CCIF_SHIFT)) & FTFA_FSTAT_CCIF_MASK) 1721 /*! @} */ 1722 1723 /*! @name FCNFG - Flash Configuration Register */ 1724 /*! @{ */ 1725 #define FTFA_FCNFG_ERSSUSP_MASK (0x10U) 1726 #define FTFA_FCNFG_ERSSUSP_SHIFT (4U) 1727 /*! ERSSUSP - Erase Suspend 1728 * 0b0..No suspend requested 1729 * 0b1..Suspend the current Erase Flash Sector command execution. 1730 */ 1731 #define FTFA_FCNFG_ERSSUSP(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCNFG_ERSSUSP_SHIFT)) & FTFA_FCNFG_ERSSUSP_MASK) 1732 #define FTFA_FCNFG_ERSAREQ_MASK (0x20U) 1733 #define FTFA_FCNFG_ERSAREQ_SHIFT (5U) 1734 /*! ERSAREQ - Erase All Request 1735 * 0b0..No request or request complete 1736 * 0b1..Request to: run the Erase All Blocks command, verify the erased state, program the security byte in the 1737 * Flash Configuration Field to the unsecure state, and release MCU security by setting the FSEC[SEC] field to 1738 * the unsecure state. 1739 */ 1740 #define FTFA_FCNFG_ERSAREQ(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCNFG_ERSAREQ_SHIFT)) & FTFA_FCNFG_ERSAREQ_MASK) 1741 #define FTFA_FCNFG_RDCOLLIE_MASK (0x40U) 1742 #define FTFA_FCNFG_RDCOLLIE_SHIFT (6U) 1743 /*! RDCOLLIE - Read Collision Error Interrupt Enable 1744 * 0b0..Read collision error interrupt disabled 1745 * 0b1..Read collision error interrupt enabled. An interrupt request is generated whenever a flash memory read 1746 * collision error is detected (see the description of FSTAT[RDCOLERR]). 1747 */ 1748 #define FTFA_FCNFG_RDCOLLIE(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCNFG_RDCOLLIE_SHIFT)) & FTFA_FCNFG_RDCOLLIE_MASK) 1749 #define FTFA_FCNFG_CCIE_MASK (0x80U) 1750 #define FTFA_FCNFG_CCIE_SHIFT (7U) 1751 /*! CCIE - Command Complete Interrupt Enable 1752 * 0b0..Command complete interrupt disabled 1753 * 0b1..Command complete interrupt enabled. An interrupt request is generated whenever the FSTAT[CCIF] flag is set. 1754 */ 1755 #define FTFA_FCNFG_CCIE(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCNFG_CCIE_SHIFT)) & FTFA_FCNFG_CCIE_MASK) 1756 /*! @} */ 1757 1758 /*! @name FSEC - Flash Security Register */ 1759 /*! @{ */ 1760 #define FTFA_FSEC_SEC_MASK (0x3U) 1761 #define FTFA_FSEC_SEC_SHIFT (0U) 1762 /*! SEC - Flash Security 1763 * 0b00..MCU security status is secure. 1764 * 0b01..MCU security status is secure. 1765 * 0b10..MCU security status is unsecure. (The standard shipping condition of the flash memory module is unsecure.) 1766 * 0b11..MCU security status is secure. 1767 */ 1768 #define FTFA_FSEC_SEC(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FSEC_SEC_SHIFT)) & FTFA_FSEC_SEC_MASK) 1769 #define FTFA_FSEC_FSLACC_MASK (0xCU) 1770 #define FTFA_FSEC_FSLACC_SHIFT (2U) 1771 /*! FSLACC - Factory Security Level Access Code 1772 * 0b00..NXP factory access granted 1773 * 0b01..NXP factory access denied 1774 * 0b10..NXP factory access denied 1775 * 0b11..NXP factory access granted 1776 */ 1777 #define FTFA_FSEC_FSLACC(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FSEC_FSLACC_SHIFT)) & FTFA_FSEC_FSLACC_MASK) 1778 #define FTFA_FSEC_MEEN_MASK (0x30U) 1779 #define FTFA_FSEC_MEEN_SHIFT (4U) 1780 /*! MEEN - Mass Erase Enable 1781 * 0b00..Mass erase is enabled 1782 * 0b01..Mass erase is enabled 1783 * 0b10..Mass erase is disabled 1784 * 0b11..Mass erase is enabled 1785 */ 1786 #define FTFA_FSEC_MEEN(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FSEC_MEEN_SHIFT)) & FTFA_FSEC_MEEN_MASK) 1787 #define FTFA_FSEC_KEYEN_MASK (0xC0U) 1788 #define FTFA_FSEC_KEYEN_SHIFT (6U) 1789 /*! KEYEN - Backdoor Key Security Enable 1790 * 0b00..Backdoor key access disabled 1791 * 0b01..Backdoor key access disabled (preferred KEYEN state to disable backdoor key access) 1792 * 0b10..Backdoor key access enabled 1793 * 0b11..Backdoor key access disabled 1794 */ 1795 #define FTFA_FSEC_KEYEN(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FSEC_KEYEN_SHIFT)) & FTFA_FSEC_KEYEN_MASK) 1796 /*! @} */ 1797 1798 /*! @name FOPT - Flash Option Register */ 1799 /*! @{ */ 1800 #define FTFA_FOPT_OPT_MASK (0xFFU) 1801 #define FTFA_FOPT_OPT_SHIFT (0U) 1802 /*! OPT - Nonvolatile Option 1803 */ 1804 #define FTFA_FOPT_OPT(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FOPT_OPT_SHIFT)) & FTFA_FOPT_OPT_MASK) 1805 /*! @} */ 1806 1807 /*! @name FCCOB3 - Flash Common Command Object Registers */ 1808 /*! @{ */ 1809 #define FTFA_FCCOB3_CCOBn_MASK (0xFFU) 1810 #define FTFA_FCCOB3_CCOBn_SHIFT (0U) 1811 #define FTFA_FCCOB3_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOB3_CCOBn_SHIFT)) & FTFA_FCCOB3_CCOBn_MASK) 1812 /*! @} */ 1813 1814 /*! @name FCCOB2 - Flash Common Command Object Registers */ 1815 /*! @{ */ 1816 #define FTFA_FCCOB2_CCOBn_MASK (0xFFU) 1817 #define FTFA_FCCOB2_CCOBn_SHIFT (0U) 1818 #define FTFA_FCCOB2_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOB2_CCOBn_SHIFT)) & FTFA_FCCOB2_CCOBn_MASK) 1819 /*! @} */ 1820 1821 /*! @name FCCOB1 - Flash Common Command Object Registers */ 1822 /*! @{ */ 1823 #define FTFA_FCCOB1_CCOBn_MASK (0xFFU) 1824 #define FTFA_FCCOB1_CCOBn_SHIFT (0U) 1825 #define FTFA_FCCOB1_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOB1_CCOBn_SHIFT)) & FTFA_FCCOB1_CCOBn_MASK) 1826 /*! @} */ 1827 1828 /*! @name FCCOB0 - Flash Common Command Object Registers */ 1829 /*! @{ */ 1830 #define FTFA_FCCOB0_CCOBn_MASK (0xFFU) 1831 #define FTFA_FCCOB0_CCOBn_SHIFT (0U) 1832 #define FTFA_FCCOB0_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOB0_CCOBn_SHIFT)) & FTFA_FCCOB0_CCOBn_MASK) 1833 /*! @} */ 1834 1835 /*! @name FCCOB7 - Flash Common Command Object Registers */ 1836 /*! @{ */ 1837 #define FTFA_FCCOB7_CCOBn_MASK (0xFFU) 1838 #define FTFA_FCCOB7_CCOBn_SHIFT (0U) 1839 #define FTFA_FCCOB7_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOB7_CCOBn_SHIFT)) & FTFA_FCCOB7_CCOBn_MASK) 1840 /*! @} */ 1841 1842 /*! @name FCCOB6 - Flash Common Command Object Registers */ 1843 /*! @{ */ 1844 #define FTFA_FCCOB6_CCOBn_MASK (0xFFU) 1845 #define FTFA_FCCOB6_CCOBn_SHIFT (0U) 1846 #define FTFA_FCCOB6_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOB6_CCOBn_SHIFT)) & FTFA_FCCOB6_CCOBn_MASK) 1847 /*! @} */ 1848 1849 /*! @name FCCOB5 - Flash Common Command Object Registers */ 1850 /*! @{ */ 1851 #define FTFA_FCCOB5_CCOBn_MASK (0xFFU) 1852 #define FTFA_FCCOB5_CCOBn_SHIFT (0U) 1853 #define FTFA_FCCOB5_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOB5_CCOBn_SHIFT)) & FTFA_FCCOB5_CCOBn_MASK) 1854 /*! @} */ 1855 1856 /*! @name FCCOB4 - Flash Common Command Object Registers */ 1857 /*! @{ */ 1858 #define FTFA_FCCOB4_CCOBn_MASK (0xFFU) 1859 #define FTFA_FCCOB4_CCOBn_SHIFT (0U) 1860 #define FTFA_FCCOB4_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOB4_CCOBn_SHIFT)) & FTFA_FCCOB4_CCOBn_MASK) 1861 /*! @} */ 1862 1863 /*! @name FCCOBB - Flash Common Command Object Registers */ 1864 /*! @{ */ 1865 #define FTFA_FCCOBB_CCOBn_MASK (0xFFU) 1866 #define FTFA_FCCOBB_CCOBn_SHIFT (0U) 1867 #define FTFA_FCCOBB_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOBB_CCOBn_SHIFT)) & FTFA_FCCOBB_CCOBn_MASK) 1868 /*! @} */ 1869 1870 /*! @name FCCOBA - Flash Common Command Object Registers */ 1871 /*! @{ */ 1872 #define FTFA_FCCOBA_CCOBn_MASK (0xFFU) 1873 #define FTFA_FCCOBA_CCOBn_SHIFT (0U) 1874 #define FTFA_FCCOBA_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOBA_CCOBn_SHIFT)) & FTFA_FCCOBA_CCOBn_MASK) 1875 /*! @} */ 1876 1877 /*! @name FCCOB9 - Flash Common Command Object Registers */ 1878 /*! @{ */ 1879 #define FTFA_FCCOB9_CCOBn_MASK (0xFFU) 1880 #define FTFA_FCCOB9_CCOBn_SHIFT (0U) 1881 #define FTFA_FCCOB9_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOB9_CCOBn_SHIFT)) & FTFA_FCCOB9_CCOBn_MASK) 1882 /*! @} */ 1883 1884 /*! @name FCCOB8 - Flash Common Command Object Registers */ 1885 /*! @{ */ 1886 #define FTFA_FCCOB8_CCOBn_MASK (0xFFU) 1887 #define FTFA_FCCOB8_CCOBn_SHIFT (0U) 1888 #define FTFA_FCCOB8_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOB8_CCOBn_SHIFT)) & FTFA_FCCOB8_CCOBn_MASK) 1889 /*! @} */ 1890 1891 /*! @name FPROT3 - Program Flash Protection Registers */ 1892 /*! @{ */ 1893 #define FTFA_FPROT3_PROT_MASK (0xFFU) 1894 #define FTFA_FPROT3_PROT_SHIFT (0U) 1895 /*! PROT - Program Flash Region Protect 1896 * 0b00000000..Program flash region is protected. 1897 * 0b00000001..Program flash region is not protected 1898 */ 1899 #define FTFA_FPROT3_PROT(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FPROT3_PROT_SHIFT)) & FTFA_FPROT3_PROT_MASK) 1900 /*! @} */ 1901 1902 /*! @name FPROT2 - Program Flash Protection Registers */ 1903 /*! @{ */ 1904 #define FTFA_FPROT2_PROT_MASK (0xFFU) 1905 #define FTFA_FPROT2_PROT_SHIFT (0U) 1906 /*! PROT - Program Flash Region Protect 1907 * 0b00000000..Program flash region is protected. 1908 * 0b00000001..Program flash region is not protected 1909 */ 1910 #define FTFA_FPROT2_PROT(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FPROT2_PROT_SHIFT)) & FTFA_FPROT2_PROT_MASK) 1911 /*! @} */ 1912 1913 /*! @name FPROT1 - Program Flash Protection Registers */ 1914 /*! @{ */ 1915 #define FTFA_FPROT1_PROT_MASK (0xFFU) 1916 #define FTFA_FPROT1_PROT_SHIFT (0U) 1917 /*! PROT - Program Flash Region Protect 1918 * 0b00000000..Program flash region is protected. 1919 * 0b00000001..Program flash region is not protected 1920 */ 1921 #define FTFA_FPROT1_PROT(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FPROT1_PROT_SHIFT)) & FTFA_FPROT1_PROT_MASK) 1922 /*! @} */ 1923 1924 /*! @name FPROT0 - Program Flash Protection Registers */ 1925 /*! @{ */ 1926 #define FTFA_FPROT0_PROT_MASK (0xFFU) 1927 #define FTFA_FPROT0_PROT_SHIFT (0U) 1928 /*! PROT - Program Flash Region Protect 1929 * 0b00000000..Program flash region is protected. 1930 * 0b00000001..Program flash region is not protected 1931 */ 1932 #define FTFA_FPROT0_PROT(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FPROT0_PROT_SHIFT)) & FTFA_FPROT0_PROT_MASK) 1933 /*! @} */ 1934 1935 1936 /*! 1937 * @} 1938 */ /* end of group FTFA_Register_Masks */ 1939 1940 1941 /* FTFA - Peripheral instance base addresses */ 1942 /** Peripheral FTFA base address */ 1943 #define FTFA_BASE (0x40020000u) 1944 /** Peripheral FTFA base pointer */ 1945 #define FTFA ((FTFA_Type *)FTFA_BASE) 1946 /** Array initializer of FTFA peripheral base addresses */ 1947 #define FTFA_BASE_ADDRS { FTFA_BASE } 1948 /** Array initializer of FTFA peripheral base pointers */ 1949 #define FTFA_BASE_PTRS { FTFA } 1950 1951 /*! 1952 * @} 1953 */ /* end of group FTFA_Peripheral_Access_Layer */ 1954 1955 1956 /* ---------------------------------------------------------------------------- 1957 -- FTM Peripheral Access Layer 1958 ---------------------------------------------------------------------------- */ 1959 1960 /*! 1961 * @addtogroup FTM_Peripheral_Access_Layer FTM Peripheral Access Layer 1962 * @{ 1963 */ 1964 1965 /** FTM - Register Layout Typedef */ 1966 typedef struct { 1967 __IO uint32_t SC; /**< Status And Control, offset: 0x0 */ 1968 __IO uint32_t CNT; /**< Counter, offset: 0x4 */ 1969 __IO uint32_t MOD; /**< Modulo, offset: 0x8 */ 1970 struct { /* offset: 0xC, array step: 0x8 */ 1971 __IO uint32_t CnSC; /**< Channel (n) Status And Control, array offset: 0xC, array step: 0x8 */ 1972 __IO uint32_t CnV; /**< Channel (n) Value, array offset: 0x10, array step: 0x8 */ 1973 } CONTROLS[6]; 1974 uint8_t RESERVED_0[16]; 1975 __IO uint32_t CNTIN; /**< Counter Initial Value, offset: 0x4C */ 1976 __IO uint32_t STATUS; /**< Capture And Compare Status, offset: 0x50 */ 1977 __IO uint32_t MODE; /**< Features Mode Selection, offset: 0x54 */ 1978 __IO uint32_t SYNC; /**< Synchronization, offset: 0x58 */ 1979 __IO uint32_t OUTINIT; /**< Initial State For Channels Output, offset: 0x5C */ 1980 __IO uint32_t OUTMASK; /**< Output Mask, offset: 0x60 */ 1981 __IO uint32_t COMBINE; /**< Function For Linked Channels, offset: 0x64 */ 1982 __IO uint32_t DEADTIME; /**< Deadtime Configuration, offset: 0x68 */ 1983 __IO uint32_t EXTTRIG; /**< FTM External Trigger, offset: 0x6C */ 1984 __IO uint32_t POL; /**< Channels Polarity, offset: 0x70 */ 1985 __IO uint32_t FMS; /**< Fault Mode Status, offset: 0x74 */ 1986 __IO uint32_t FILTER; /**< Input Capture Filter Control, offset: 0x78 */ 1987 __IO uint32_t FLTCTRL; /**< Fault Control, offset: 0x7C */ 1988 __IO uint32_t QDCTRL; /**< Quadrature Decoder Control And Status, offset: 0x80 */ 1989 __IO uint32_t CONF; /**< Configuration, offset: 0x84 */ 1990 __IO uint32_t FLTPOL; /**< FTM Fault Input Polarity, offset: 0x88 */ 1991 __IO uint32_t SYNCONF; /**< Synchronization Configuration, offset: 0x8C */ 1992 __IO uint32_t INVCTRL; /**< FTM Inverting Control, offset: 0x90 */ 1993 __IO uint32_t SWOCTRL; /**< FTM Software Output Control, offset: 0x94 */ 1994 __IO uint32_t PWMLOAD; /**< FTM PWM Load, offset: 0x98 */ 1995 __IO uint32_t HCR; /**< Half Cycle Register, offset: 0x9C */ 1996 uint8_t RESERVED_1[352]; 1997 __IO uint32_t MOD_MIRROR; /**< Mirror of Modulo Value, offset: 0x200 */ 1998 __IO uint32_t CV_MIRROR[6]; /**< Mirror of Channel (n) Match Value, array offset: 0x204, array step: 0x4 */ 1999 } FTM_Type; 2000 2001 /* ---------------------------------------------------------------------------- 2002 -- FTM Register Masks 2003 ---------------------------------------------------------------------------- */ 2004 2005 /*! 2006 * @addtogroup FTM_Register_Masks FTM Register Masks 2007 * @{ 2008 */ 2009 2010 /*! @name SC - Status And Control */ 2011 /*! @{ */ 2012 #define FTM_SC_PS_MASK (0x7U) 2013 #define FTM_SC_PS_SHIFT (0U) 2014 /*! PS - Prescale Factor Selection 2015 * 0b000..Divide by 1 2016 * 0b001..Divide by 2 2017 * 0b010..Divide by 4 2018 * 0b011..Divide by 8 2019 * 0b100..Divide by 16 2020 * 0b101..Divide by 32 2021 * 0b110..Divide by 64 2022 * 0b111..Divide by 128 2023 */ 2024 #define FTM_SC_PS(x) (((uint32_t)(((uint32_t)(x)) << FTM_SC_PS_SHIFT)) & FTM_SC_PS_MASK) 2025 #define FTM_SC_CLKS_MASK (0x18U) 2026 #define FTM_SC_CLKS_SHIFT (3U) 2027 /*! CLKS - Clock Source Selection 2028 * 0b00..No clock selected. This in effect disables the FTM counter. 2029 * 0b01..FTM input clock 2030 * 0b10..Fixed frequency clock 2031 * 0b11..External clock 2032 */ 2033 #define FTM_SC_CLKS(x) (((uint32_t)(((uint32_t)(x)) << FTM_SC_CLKS_SHIFT)) & FTM_SC_CLKS_MASK) 2034 #define FTM_SC_CPWMS_MASK (0x20U) 2035 #define FTM_SC_CPWMS_SHIFT (5U) 2036 /*! CPWMS - Center-Aligned PWM Select 2037 * 0b0..FTM counter operates in Up Counting mode. 2038 * 0b1..FTM counter operates in Up-Down Counting mode. 2039 */ 2040 #define FTM_SC_CPWMS(x) (((uint32_t)(((uint32_t)(x)) << FTM_SC_CPWMS_SHIFT)) & FTM_SC_CPWMS_MASK) 2041 #define FTM_SC_RIE_MASK (0x40U) 2042 #define FTM_SC_RIE_SHIFT (6U) 2043 /*! RIE - Reload Point Interrupt Enable 2044 * 0b0..Reload point interrupt is disabled. 2045 * 0b1..Reload point interrupt is enabled. 2046 */ 2047 #define FTM_SC_RIE(x) (((uint32_t)(((uint32_t)(x)) << FTM_SC_RIE_SHIFT)) & FTM_SC_RIE_MASK) 2048 #define FTM_SC_RF_MASK (0x80U) 2049 #define FTM_SC_RF_SHIFT (7U) 2050 /*! RF - Reload Flag 2051 * 0b0..A selected reload point did not happen. 2052 * 0b1..A selected reload point happened. 2053 */ 2054 #define FTM_SC_RF(x) (((uint32_t)(((uint32_t)(x)) << FTM_SC_RF_SHIFT)) & FTM_SC_RF_MASK) 2055 #define FTM_SC_TOIE_MASK (0x100U) 2056 #define FTM_SC_TOIE_SHIFT (8U) 2057 /*! TOIE - Timer Overflow Interrupt Enable 2058 * 0b0..Disable TOF interrupts. Use software polling. 2059 * 0b1..Enable TOF interrupts. An interrupt is generated when TOF equals one. 2060 */ 2061 #define FTM_SC_TOIE(x) (((uint32_t)(((uint32_t)(x)) << FTM_SC_TOIE_SHIFT)) & FTM_SC_TOIE_MASK) 2062 #define FTM_SC_TOF_MASK (0x200U) 2063 #define FTM_SC_TOF_SHIFT (9U) 2064 /*! TOF - Timer Overflow Flag 2065 * 0b0..FTM counter has not overflowed. 2066 * 0b1..FTM counter has overflowed. 2067 */ 2068 #define FTM_SC_TOF(x) (((uint32_t)(((uint32_t)(x)) << FTM_SC_TOF_SHIFT)) & FTM_SC_TOF_MASK) 2069 #define FTM_SC_PWMEN0_MASK (0x10000U) 2070 #define FTM_SC_PWMEN0_SHIFT (16U) 2071 /*! PWMEN0 - Channel 0 PWM enable bit 2072 * 0b0..Channel output port is disabled. 2073 * 0b1..Channel output port is enabled. 2074 */ 2075 #define FTM_SC_PWMEN0(x) (((uint32_t)(((uint32_t)(x)) << FTM_SC_PWMEN0_SHIFT)) & FTM_SC_PWMEN0_MASK) 2076 #define FTM_SC_PWMEN1_MASK (0x20000U) 2077 #define FTM_SC_PWMEN1_SHIFT (17U) 2078 /*! PWMEN1 - Channel 1 PWM enable bit 2079 * 0b0..Channel output port is disabled. 2080 * 0b1..Channel output port is enabled. 2081 */ 2082 #define FTM_SC_PWMEN1(x) (((uint32_t)(((uint32_t)(x)) << FTM_SC_PWMEN1_SHIFT)) & FTM_SC_PWMEN1_MASK) 2083 #define FTM_SC_PWMEN2_MASK (0x40000U) 2084 #define FTM_SC_PWMEN2_SHIFT (18U) 2085 /*! PWMEN2 - Channel 2 PWM enable bit 2086 * 0b0..Channel output port is disabled. 2087 * 0b1..Channel output port is enabled. 2088 */ 2089 #define FTM_SC_PWMEN2(x) (((uint32_t)(((uint32_t)(x)) << FTM_SC_PWMEN2_SHIFT)) & FTM_SC_PWMEN2_MASK) 2090 #define FTM_SC_PWMEN3_MASK (0x80000U) 2091 #define FTM_SC_PWMEN3_SHIFT (19U) 2092 /*! PWMEN3 - Channel 3 PWM enable bit 2093 * 0b0..Channel output port is disabled. 2094 * 0b1..Channel output port is enabled. 2095 */ 2096 #define FTM_SC_PWMEN3(x) (((uint32_t)(((uint32_t)(x)) << FTM_SC_PWMEN3_SHIFT)) & FTM_SC_PWMEN3_MASK) 2097 #define FTM_SC_PWMEN4_MASK (0x100000U) 2098 #define FTM_SC_PWMEN4_SHIFT (20U) 2099 /*! PWMEN4 - Channel 4 PWM enable bit 2100 * 0b0..Channel output port is disabled. 2101 * 0b1..Channel output port is enabled. 2102 */ 2103 #define FTM_SC_PWMEN4(x) (((uint32_t)(((uint32_t)(x)) << FTM_SC_PWMEN4_SHIFT)) & FTM_SC_PWMEN4_MASK) 2104 #define FTM_SC_PWMEN5_MASK (0x200000U) 2105 #define FTM_SC_PWMEN5_SHIFT (21U) 2106 /*! PWMEN5 - Channel 5 PWM enable bit 2107 * 0b0..Channel output port is disabled. 2108 * 0b1..Channel output port is enabled. 2109 */ 2110 #define FTM_SC_PWMEN5(x) (((uint32_t)(((uint32_t)(x)) << FTM_SC_PWMEN5_SHIFT)) & FTM_SC_PWMEN5_MASK) 2111 /*! @} */ 2112 2113 /*! @name CNT - Counter */ 2114 /*! @{ */ 2115 #define FTM_CNT_COUNT_MASK (0xFFFFU) 2116 #define FTM_CNT_COUNT_SHIFT (0U) 2117 /*! COUNT - Counter Value 2118 */ 2119 #define FTM_CNT_COUNT(x) (((uint32_t)(((uint32_t)(x)) << FTM_CNT_COUNT_SHIFT)) & FTM_CNT_COUNT_MASK) 2120 /*! @} */ 2121 2122 /*! @name MOD - Modulo */ 2123 /*! @{ */ 2124 #define FTM_MOD_MOD_MASK (0xFFFFU) 2125 #define FTM_MOD_MOD_SHIFT (0U) 2126 /*! MOD - MOD 2127 */ 2128 #define FTM_MOD_MOD(x) (((uint32_t)(((uint32_t)(x)) << FTM_MOD_MOD_SHIFT)) & FTM_MOD_MOD_MASK) 2129 /*! @} */ 2130 2131 /*! @name CnSC - Channel (n) Status And Control */ 2132 /*! @{ */ 2133 #define FTM_CnSC_ICRST_MASK (0x2U) 2134 #define FTM_CnSC_ICRST_SHIFT (1U) 2135 /*! ICRST - FTM counter reset by the selected input capture event. 2136 * 0b0..FTM counter is not reset when the selected channel (n) input event is detected. 2137 * 0b1..FTM counter is reset when the selected channel (n) input event is detected. 2138 */ 2139 #define FTM_CnSC_ICRST(x) (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_ICRST_SHIFT)) & FTM_CnSC_ICRST_MASK) 2140 #define FTM_CnSC_ELSA_MASK (0x4U) 2141 #define FTM_CnSC_ELSA_SHIFT (2U) 2142 /*! ELSA - Channel (n) Edge or Level Select 2143 */ 2144 #define FTM_CnSC_ELSA(x) (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_ELSA_SHIFT)) & FTM_CnSC_ELSA_MASK) 2145 #define FTM_CnSC_ELSB_MASK (0x8U) 2146 #define FTM_CnSC_ELSB_SHIFT (3U) 2147 /*! ELSB - Channel (n) Edge or Level Select 2148 */ 2149 #define FTM_CnSC_ELSB(x) (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_ELSB_SHIFT)) & FTM_CnSC_ELSB_MASK) 2150 #define FTM_CnSC_MSA_MASK (0x10U) 2151 #define FTM_CnSC_MSA_SHIFT (4U) 2152 /*! MSA - Channel (n) Mode Select 2153 */ 2154 #define FTM_CnSC_MSA(x) (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_MSA_SHIFT)) & FTM_CnSC_MSA_MASK) 2155 #define FTM_CnSC_MSB_MASK (0x20U) 2156 #define FTM_CnSC_MSB_SHIFT (5U) 2157 /*! MSB - Channel (n) Mode Select 2158 */ 2159 #define FTM_CnSC_MSB(x) (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_MSB_SHIFT)) & FTM_CnSC_MSB_MASK) 2160 #define FTM_CnSC_CHIE_MASK (0x40U) 2161 #define FTM_CnSC_CHIE_SHIFT (6U) 2162 /*! CHIE - Channel (n) Interrupt Enable 2163 * 0b0..Disable channel (n) interrupt. Use software polling. 2164 * 0b1..Enable channel (n) interrupt. 2165 */ 2166 #define FTM_CnSC_CHIE(x) (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_CHIE_SHIFT)) & FTM_CnSC_CHIE_MASK) 2167 #define FTM_CnSC_CHF_MASK (0x80U) 2168 #define FTM_CnSC_CHF_SHIFT (7U) 2169 /*! CHF - Channel (n) Flag 2170 * 0b0..No channel (n) event has occurred. 2171 * 0b1..A channel (n) event has occurred. 2172 */ 2173 #define FTM_CnSC_CHF(x) (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_CHF_SHIFT)) & FTM_CnSC_CHF_MASK) 2174 #define FTM_CnSC_TRIGMODE_MASK (0x100U) 2175 #define FTM_CnSC_TRIGMODE_SHIFT (8U) 2176 /*! TRIGMODE - Trigger mode control 2177 * 0b0..Channel outputs will generate the normal PWM outputs without generating a pulse. 2178 * 0b1..If a match in the channel occurs, a trigger generation on channel output will happen. The trigger pulse width has one FTM clock cycle. 2179 */ 2180 #define FTM_CnSC_TRIGMODE(x) (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_TRIGMODE_SHIFT)) & FTM_CnSC_TRIGMODE_MASK) 2181 #define FTM_CnSC_CHIS_MASK (0x200U) 2182 #define FTM_CnSC_CHIS_SHIFT (9U) 2183 /*! CHIS - Channel (n) Input State 2184 * 0b0..The channel (n) input is zero. 2185 * 0b1..The channel (n) input is one. 2186 */ 2187 #define FTM_CnSC_CHIS(x) (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_CHIS_SHIFT)) & FTM_CnSC_CHIS_MASK) 2188 /*! @} */ 2189 2190 /* The count of FTM_CnSC */ 2191 #define FTM_CnSC_COUNT (6U) 2192 2193 /*! @name CnV - Channel (n) Value */ 2194 /*! @{ */ 2195 #define FTM_CnV_VAL_MASK (0xFFFFU) 2196 #define FTM_CnV_VAL_SHIFT (0U) 2197 /*! VAL - Channel Value 2198 */ 2199 #define FTM_CnV_VAL(x) (((uint32_t)(((uint32_t)(x)) << FTM_CnV_VAL_SHIFT)) & FTM_CnV_VAL_MASK) 2200 /*! @} */ 2201 2202 /* The count of FTM_CnV */ 2203 #define FTM_CnV_COUNT (6U) 2204 2205 /*! @name CNTIN - Counter Initial Value */ 2206 /*! @{ */ 2207 #define FTM_CNTIN_INIT_MASK (0xFFFFU) 2208 #define FTM_CNTIN_INIT_SHIFT (0U) 2209 /*! INIT - INIT 2210 */ 2211 #define FTM_CNTIN_INIT(x) (((uint32_t)(((uint32_t)(x)) << FTM_CNTIN_INIT_SHIFT)) & FTM_CNTIN_INIT_MASK) 2212 /*! @} */ 2213 2214 /*! @name STATUS - Capture And Compare Status */ 2215 /*! @{ */ 2216 #define FTM_STATUS_CH0F_MASK (0x1U) 2217 #define FTM_STATUS_CH0F_SHIFT (0U) 2218 /*! CH0F - Channel 0 Flag 2219 * 0b0..No channel event has occurred. 2220 * 0b1..A channel event has occurred. 2221 */ 2222 #define FTM_STATUS_CH0F(x) (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH0F_SHIFT)) & FTM_STATUS_CH0F_MASK) 2223 #define FTM_STATUS_CH1F_MASK (0x2U) 2224 #define FTM_STATUS_CH1F_SHIFT (1U) 2225 /*! CH1F - Channel 1 Flag 2226 * 0b0..No channel event has occurred. 2227 * 0b1..A channel event has occurred. 2228 */ 2229 #define FTM_STATUS_CH1F(x) (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH1F_SHIFT)) & FTM_STATUS_CH1F_MASK) 2230 #define FTM_STATUS_CH2F_MASK (0x4U) 2231 #define FTM_STATUS_CH2F_SHIFT (2U) 2232 /*! CH2F - Channel 2 Flag 2233 * 0b0..No channel event has occurred. 2234 * 0b1..A channel event has occurred. 2235 */ 2236 #define FTM_STATUS_CH2F(x) (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH2F_SHIFT)) & FTM_STATUS_CH2F_MASK) 2237 #define FTM_STATUS_CH3F_MASK (0x8U) 2238 #define FTM_STATUS_CH3F_SHIFT (3U) 2239 /*! CH3F - Channel 3 Flag 2240 * 0b0..No channel event has occurred. 2241 * 0b1..A channel event has occurred. 2242 */ 2243 #define FTM_STATUS_CH3F(x) (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH3F_SHIFT)) & FTM_STATUS_CH3F_MASK) 2244 #define FTM_STATUS_CH4F_MASK (0x10U) 2245 #define FTM_STATUS_CH4F_SHIFT (4U) 2246 /*! CH4F - Channel 4 Flag 2247 * 0b0..No channel event has occurred. 2248 * 0b1..A channel event has occurred. 2249 */ 2250 #define FTM_STATUS_CH4F(x) (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH4F_SHIFT)) & FTM_STATUS_CH4F_MASK) 2251 #define FTM_STATUS_CH5F_MASK (0x20U) 2252 #define FTM_STATUS_CH5F_SHIFT (5U) 2253 /*! CH5F - Channel 5 Flag 2254 * 0b0..No channel event has occurred. 2255 * 0b1..A channel event has occurred. 2256 */ 2257 #define FTM_STATUS_CH5F(x) (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH5F_SHIFT)) & FTM_STATUS_CH5F_MASK) 2258 /*! @} */ 2259 2260 /*! @name MODE - Features Mode Selection */ 2261 /*! @{ */ 2262 #define FTM_MODE_FTMEN_MASK (0x1U) 2263 #define FTM_MODE_FTMEN_SHIFT (0U) 2264 /*! FTMEN - FTM Enable 2265 * 0b0..TPM compatibility. Free running counter and synchronization compatible with TPM. 2266 * 0b1..Free running counter and synchronization are different from TPM behavior. 2267 */ 2268 #define FTM_MODE_FTMEN(x) (((uint32_t)(((uint32_t)(x)) << FTM_MODE_FTMEN_SHIFT)) & FTM_MODE_FTMEN_MASK) 2269 #define FTM_MODE_INIT_MASK (0x2U) 2270 #define FTM_MODE_INIT_SHIFT (1U) 2271 /*! INIT - Initialize The Channels Output 2272 */ 2273 #define FTM_MODE_INIT(x) (((uint32_t)(((uint32_t)(x)) << FTM_MODE_INIT_SHIFT)) & FTM_MODE_INIT_MASK) 2274 #define FTM_MODE_WPDIS_MASK (0x4U) 2275 #define FTM_MODE_WPDIS_SHIFT (2U) 2276 /*! WPDIS - Write Protection Disable 2277 * 0b0..Write protection is enabled. 2278 * 0b1..Write protection is disabled. 2279 */ 2280 #define FTM_MODE_WPDIS(x) (((uint32_t)(((uint32_t)(x)) << FTM_MODE_WPDIS_SHIFT)) & FTM_MODE_WPDIS_MASK) 2281 #define FTM_MODE_PWMSYNC_MASK (0x8U) 2282 #define FTM_MODE_PWMSYNC_SHIFT (3U) 2283 /*! PWMSYNC - PWM Synchronization Mode 2284 * 0b0..No restrictions. Software and hardware triggers can be used by MOD, CnV, OUTMASK, and FTM counter synchronization. 2285 * 0b1..Software trigger can only be used by MOD and CnV synchronization, and hardware triggers can only be used 2286 * by OUTMASK and FTM counter synchronization. 2287 */ 2288 #define FTM_MODE_PWMSYNC(x) (((uint32_t)(((uint32_t)(x)) << FTM_MODE_PWMSYNC_SHIFT)) & FTM_MODE_PWMSYNC_MASK) 2289 #define FTM_MODE_CAPTEST_MASK (0x10U) 2290 #define FTM_MODE_CAPTEST_SHIFT (4U) 2291 /*! CAPTEST - Capture Test Mode Enable 2292 * 0b0..Capture test mode is disabled. 2293 * 0b1..Capture test mode is enabled. 2294 */ 2295 #define FTM_MODE_CAPTEST(x) (((uint32_t)(((uint32_t)(x)) << FTM_MODE_CAPTEST_SHIFT)) & FTM_MODE_CAPTEST_MASK) 2296 #define FTM_MODE_FAULTM_MASK (0x60U) 2297 #define FTM_MODE_FAULTM_SHIFT (5U) 2298 /*! FAULTM - Fault Control Mode 2299 * 0b00..Fault control is disabled for all channels. 2300 * 0b01..Fault control is enabled for even channels only (channels 0, 2, 4, and 6), and the selected mode is the manual fault clearing. 2301 * 0b10..Fault control is enabled for all channels, and the selected mode is the manual fault clearing. 2302 * 0b11..Fault control is enabled for all channels, and the selected mode is the automatic fault clearing. 2303 */ 2304 #define FTM_MODE_FAULTM(x) (((uint32_t)(((uint32_t)(x)) << FTM_MODE_FAULTM_SHIFT)) & FTM_MODE_FAULTM_MASK) 2305 #define FTM_MODE_FAULTIE_MASK (0x80U) 2306 #define FTM_MODE_FAULTIE_SHIFT (7U) 2307 /*! FAULTIE - Fault Interrupt Enable 2308 * 0b0..Fault control interrupt is disabled. 2309 * 0b1..Fault control interrupt is enabled. 2310 */ 2311 #define FTM_MODE_FAULTIE(x) (((uint32_t)(((uint32_t)(x)) << FTM_MODE_FAULTIE_SHIFT)) & FTM_MODE_FAULTIE_MASK) 2312 /*! @} */ 2313 2314 /*! @name SYNC - Synchronization */ 2315 /*! @{ */ 2316 #define FTM_SYNC_CNTMIN_MASK (0x1U) 2317 #define FTM_SYNC_CNTMIN_SHIFT (0U) 2318 /*! CNTMIN - Minimum Loading Point Enable 2319 * 0b0..The minimum loading point is disabled. 2320 * 0b1..The minimum loading point is enabled. 2321 */ 2322 #define FTM_SYNC_CNTMIN(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_CNTMIN_SHIFT)) & FTM_SYNC_CNTMIN_MASK) 2323 #define FTM_SYNC_CNTMAX_MASK (0x2U) 2324 #define FTM_SYNC_CNTMAX_SHIFT (1U) 2325 /*! CNTMAX - Maximum Loading Point Enable 2326 * 0b0..The maximum loading point is disabled. 2327 * 0b1..The maximum loading point is enabled. 2328 */ 2329 #define FTM_SYNC_CNTMAX(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_CNTMAX_SHIFT)) & FTM_SYNC_CNTMAX_MASK) 2330 #define FTM_SYNC_REINIT_MASK (0x4U) 2331 #define FTM_SYNC_REINIT_SHIFT (2U) 2332 /*! REINIT - FTM Counter Reinitialization by Synchronization 2333 * 0b0..FTM counter continues to count normally. 2334 * 0b1..FTM counter is updated with its initial value when the selected trigger is detected. 2335 */ 2336 #define FTM_SYNC_REINIT(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_REINIT_SHIFT)) & FTM_SYNC_REINIT_MASK) 2337 #define FTM_SYNC_SYNCHOM_MASK (0x8U) 2338 #define FTM_SYNC_SYNCHOM_SHIFT (3U) 2339 /*! SYNCHOM - Output Mask Synchronization 2340 * 0b0..OUTMASK register is updated with the value of its buffer in all rising edges of the FTM input clock. 2341 * 0b1..OUTMASK register is updated with the value of its buffer only by the PWM synchronization. 2342 */ 2343 #define FTM_SYNC_SYNCHOM(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_SYNCHOM_SHIFT)) & FTM_SYNC_SYNCHOM_MASK) 2344 #define FTM_SYNC_TRIG0_MASK (0x10U) 2345 #define FTM_SYNC_TRIG0_SHIFT (4U) 2346 /*! TRIG0 - PWM Synchronization Hardware Trigger 0 2347 * 0b0..Trigger is disabled. 2348 * 0b1..Trigger is enabled. 2349 */ 2350 #define FTM_SYNC_TRIG0(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_TRIG0_SHIFT)) & FTM_SYNC_TRIG0_MASK) 2351 #define FTM_SYNC_TRIG1_MASK (0x20U) 2352 #define FTM_SYNC_TRIG1_SHIFT (5U) 2353 /*! TRIG1 - PWM Synchronization Hardware Trigger 1 2354 * 0b0..Trigger is disabled. 2355 * 0b1..Trigger is enabled. 2356 */ 2357 #define FTM_SYNC_TRIG1(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_TRIG1_SHIFT)) & FTM_SYNC_TRIG1_MASK) 2358 #define FTM_SYNC_TRIG2_MASK (0x40U) 2359 #define FTM_SYNC_TRIG2_SHIFT (6U) 2360 /*! TRIG2 - PWM Synchronization Hardware Trigger 2 2361 * 0b0..Trigger is disabled. 2362 * 0b1..Trigger is enabled. 2363 */ 2364 #define FTM_SYNC_TRIG2(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_TRIG2_SHIFT)) & FTM_SYNC_TRIG2_MASK) 2365 #define FTM_SYNC_SWSYNC_MASK (0x80U) 2366 #define FTM_SYNC_SWSYNC_SHIFT (7U) 2367 /*! SWSYNC - PWM Synchronization Software Trigger 2368 * 0b0..Software trigger is not selected. 2369 * 0b1..Software trigger is selected. 2370 */ 2371 #define FTM_SYNC_SWSYNC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_SWSYNC_SHIFT)) & FTM_SYNC_SWSYNC_MASK) 2372 /*! @} */ 2373 2374 /*! @name OUTINIT - Initial State For Channels Output */ 2375 /*! @{ */ 2376 #define FTM_OUTINIT_CH0OI_MASK (0x1U) 2377 #define FTM_OUTINIT_CH0OI_SHIFT (0U) 2378 /*! CH0OI - Channel 0 Output Initialization Value 2379 * 0b0..The initialization value is 0. 2380 * 0b1..The initialization value is 1. 2381 */ 2382 #define FTM_OUTINIT_CH0OI(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH0OI_SHIFT)) & FTM_OUTINIT_CH0OI_MASK) 2383 #define FTM_OUTINIT_CH1OI_MASK (0x2U) 2384 #define FTM_OUTINIT_CH1OI_SHIFT (1U) 2385 /*! CH1OI - Channel 1 Output Initialization Value 2386 * 0b0..The initialization value is 0. 2387 * 0b1..The initialization value is 1. 2388 */ 2389 #define FTM_OUTINIT_CH1OI(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH1OI_SHIFT)) & FTM_OUTINIT_CH1OI_MASK) 2390 #define FTM_OUTINIT_CH2OI_MASK (0x4U) 2391 #define FTM_OUTINIT_CH2OI_SHIFT (2U) 2392 /*! CH2OI - Channel 2 Output Initialization Value 2393 * 0b0..The initialization value is 0. 2394 * 0b1..The initialization value is 1. 2395 */ 2396 #define FTM_OUTINIT_CH2OI(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH2OI_SHIFT)) & FTM_OUTINIT_CH2OI_MASK) 2397 #define FTM_OUTINIT_CH3OI_MASK (0x8U) 2398 #define FTM_OUTINIT_CH3OI_SHIFT (3U) 2399 /*! CH3OI - Channel 3 Output Initialization Value 2400 * 0b0..The initialization value is 0. 2401 * 0b1..The initialization value is 1. 2402 */ 2403 #define FTM_OUTINIT_CH3OI(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH3OI_SHIFT)) & FTM_OUTINIT_CH3OI_MASK) 2404 #define FTM_OUTINIT_CH4OI_MASK (0x10U) 2405 #define FTM_OUTINIT_CH4OI_SHIFT (4U) 2406 /*! CH4OI - Channel 4 Output Initialization Value 2407 * 0b0..The initialization value is 0. 2408 * 0b1..The initialization value is 1. 2409 */ 2410 #define FTM_OUTINIT_CH4OI(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH4OI_SHIFT)) & FTM_OUTINIT_CH4OI_MASK) 2411 #define FTM_OUTINIT_CH5OI_MASK (0x20U) 2412 #define FTM_OUTINIT_CH5OI_SHIFT (5U) 2413 /*! CH5OI - Channel 5 Output Initialization Value 2414 * 0b0..The initialization value is 0. 2415 * 0b1..The initialization value is 1. 2416 */ 2417 #define FTM_OUTINIT_CH5OI(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH5OI_SHIFT)) & FTM_OUTINIT_CH5OI_MASK) 2418 /*! @} */ 2419 2420 /*! @name OUTMASK - Output Mask */ 2421 /*! @{ */ 2422 #define FTM_OUTMASK_CH0OM_MASK (0x1U) 2423 #define FTM_OUTMASK_CH0OM_SHIFT (0U) 2424 /*! CH0OM - Channel 0 Output Mask 2425 * 0b0..Channel output is not masked. It continues to operate normally. 2426 * 0b1..Channel output is masked. It is forced to its inactive state. 2427 */ 2428 #define FTM_OUTMASK_CH0OM(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH0OM_SHIFT)) & FTM_OUTMASK_CH0OM_MASK) 2429 #define FTM_OUTMASK_CH1OM_MASK (0x2U) 2430 #define FTM_OUTMASK_CH1OM_SHIFT (1U) 2431 /*! CH1OM - Channel 1 Output Mask 2432 * 0b0..Channel output is not masked. It continues to operate normally. 2433 * 0b1..Channel output is masked. It is forced to its inactive state. 2434 */ 2435 #define FTM_OUTMASK_CH1OM(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH1OM_SHIFT)) & FTM_OUTMASK_CH1OM_MASK) 2436 #define FTM_OUTMASK_CH2OM_MASK (0x4U) 2437 #define FTM_OUTMASK_CH2OM_SHIFT (2U) 2438 /*! CH2OM - Channel 2 Output Mask 2439 * 0b0..Channel output is not masked. It continues to operate normally. 2440 * 0b1..Channel output is masked. It is forced to its inactive state. 2441 */ 2442 #define FTM_OUTMASK_CH2OM(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH2OM_SHIFT)) & FTM_OUTMASK_CH2OM_MASK) 2443 #define FTM_OUTMASK_CH3OM_MASK (0x8U) 2444 #define FTM_OUTMASK_CH3OM_SHIFT (3U) 2445 /*! CH3OM - Channel 3 Output Mask 2446 * 0b0..Channel output is not masked. It continues to operate normally. 2447 * 0b1..Channel output is masked. It is forced to its inactive state. 2448 */ 2449 #define FTM_OUTMASK_CH3OM(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH3OM_SHIFT)) & FTM_OUTMASK_CH3OM_MASK) 2450 #define FTM_OUTMASK_CH4OM_MASK (0x10U) 2451 #define FTM_OUTMASK_CH4OM_SHIFT (4U) 2452 /*! CH4OM - Channel 4 Output Mask 2453 * 0b0..Channel output is not masked. It continues to operate normally. 2454 * 0b1..Channel output is masked. It is forced to its inactive state. 2455 */ 2456 #define FTM_OUTMASK_CH4OM(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH4OM_SHIFT)) & FTM_OUTMASK_CH4OM_MASK) 2457 #define FTM_OUTMASK_CH5OM_MASK (0x20U) 2458 #define FTM_OUTMASK_CH5OM_SHIFT (5U) 2459 /*! CH5OM - Channel 5 Output Mask 2460 * 0b0..Channel output is not masked. It continues to operate normally. 2461 * 0b1..Channel output is masked. It is forced to its inactive state. 2462 */ 2463 #define FTM_OUTMASK_CH5OM(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH5OM_SHIFT)) & FTM_OUTMASK_CH5OM_MASK) 2464 /*! @} */ 2465 2466 /*! @name COMBINE - Function For Linked Channels */ 2467 /*! @{ */ 2468 #define FTM_COMBINE_COMBINE0_MASK (0x1U) 2469 #define FTM_COMBINE_COMBINE0_SHIFT (0U) 2470 /*! COMBINE0 - Combine Channels For n = 0 2471 */ 2472 #define FTM_COMBINE_COMBINE0(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMBINE0_SHIFT)) & FTM_COMBINE_COMBINE0_MASK) 2473 #define FTM_COMBINE_COMP0_MASK (0x2U) 2474 #define FTM_COMBINE_COMP0_SHIFT (1U) 2475 /*! COMP0 - Complement Of Channel (n) For n = 0 2476 * 0b0..The channel (n+1) output is the same as the channel (n) output. 2477 * 0b1..The channel (n+1) output is the complement of the channel (n) output. 2478 */ 2479 #define FTM_COMBINE_COMP0(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMP0_SHIFT)) & FTM_COMBINE_COMP0_MASK) 2480 #define FTM_COMBINE_DECAPEN0_MASK (0x4U) 2481 #define FTM_COMBINE_DECAPEN0_SHIFT (2U) 2482 /*! DECAPEN0 - Dual Edge Capture Mode Enable For n = 0 2483 */ 2484 #define FTM_COMBINE_DECAPEN0(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAPEN0_SHIFT)) & FTM_COMBINE_DECAPEN0_MASK) 2485 #define FTM_COMBINE_DECAP0_MASK (0x8U) 2486 #define FTM_COMBINE_DECAP0_SHIFT (3U) 2487 /*! DECAP0 - Dual Edge Capture Mode Captures For n = 0 2488 * 0b0..The dual edge captures are inactive. 2489 * 0b1..The dual edge captures are active. 2490 */ 2491 #define FTM_COMBINE_DECAP0(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAP0_SHIFT)) & FTM_COMBINE_DECAP0_MASK) 2492 #define FTM_COMBINE_DTEN0_MASK (0x10U) 2493 #define FTM_COMBINE_DTEN0_SHIFT (4U) 2494 /*! DTEN0 - Deadtime Enable For n = 0 2495 * 0b0..The deadtime insertion in this pair of channels is disabled. 2496 * 0b1..The deadtime insertion in this pair of channels is enabled. 2497 */ 2498 #define FTM_COMBINE_DTEN0(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DTEN0_SHIFT)) & FTM_COMBINE_DTEN0_MASK) 2499 #define FTM_COMBINE_SYNCEN0_MASK (0x20U) 2500 #define FTM_COMBINE_SYNCEN0_SHIFT (5U) 2501 /*! SYNCEN0 - Synchronization Enable For n = 0 2502 * 0b0..The PWM synchronization in this pair of channels is disabled. 2503 * 0b1..The PWM synchronization in this pair of channels is enabled. 2504 */ 2505 #define FTM_COMBINE_SYNCEN0(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_SYNCEN0_SHIFT)) & FTM_COMBINE_SYNCEN0_MASK) 2506 #define FTM_COMBINE_FAULTEN0_MASK (0x40U) 2507 #define FTM_COMBINE_FAULTEN0_SHIFT (6U) 2508 /*! FAULTEN0 - Fault Control Enable For n = 0 2509 * 0b0..The fault control in this pair of channels is disabled. 2510 * 0b1..The fault control in this pair of channels is enabled. 2511 */ 2512 #define FTM_COMBINE_FAULTEN0(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_FAULTEN0_SHIFT)) & FTM_COMBINE_FAULTEN0_MASK) 2513 #define FTM_COMBINE_COMBINE1_MASK (0x100U) 2514 #define FTM_COMBINE_COMBINE1_SHIFT (8U) 2515 /*! COMBINE1 - Combine Channels For n = 2 2516 */ 2517 #define FTM_COMBINE_COMBINE1(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMBINE1_SHIFT)) & FTM_COMBINE_COMBINE1_MASK) 2518 #define FTM_COMBINE_COMP1_MASK (0x200U) 2519 #define FTM_COMBINE_COMP1_SHIFT (9U) 2520 /*! COMP1 - Complement Of Channel (n) For n = 2 2521 * 0b0..The channel (n+1) output is the same as the channel (n) output. 2522 * 0b1..The channel (n+1) output is the complement of the channel (n) output. 2523 */ 2524 #define FTM_COMBINE_COMP1(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMP1_SHIFT)) & FTM_COMBINE_COMP1_MASK) 2525 #define FTM_COMBINE_DECAPEN1_MASK (0x400U) 2526 #define FTM_COMBINE_DECAPEN1_SHIFT (10U) 2527 /*! DECAPEN1 - Dual Edge Capture Mode Enable For n = 2 2528 */ 2529 #define FTM_COMBINE_DECAPEN1(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAPEN1_SHIFT)) & FTM_COMBINE_DECAPEN1_MASK) 2530 #define FTM_COMBINE_DECAP1_MASK (0x800U) 2531 #define FTM_COMBINE_DECAP1_SHIFT (11U) 2532 /*! DECAP1 - Dual Edge Capture Mode Captures For n = 2 2533 * 0b0..The dual edge captures are inactive. 2534 * 0b1..The dual edge captures are active. 2535 */ 2536 #define FTM_COMBINE_DECAP1(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAP1_SHIFT)) & FTM_COMBINE_DECAP1_MASK) 2537 #define FTM_COMBINE_DTEN1_MASK (0x1000U) 2538 #define FTM_COMBINE_DTEN1_SHIFT (12U) 2539 /*! DTEN1 - Deadtime Enable For n = 2 2540 * 0b0..The deadtime insertion in this pair of channels is disabled. 2541 * 0b1..The deadtime insertion in this pair of channels is enabled. 2542 */ 2543 #define FTM_COMBINE_DTEN1(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DTEN1_SHIFT)) & FTM_COMBINE_DTEN1_MASK) 2544 #define FTM_COMBINE_SYNCEN1_MASK (0x2000U) 2545 #define FTM_COMBINE_SYNCEN1_SHIFT (13U) 2546 /*! SYNCEN1 - Synchronization Enable For n = 2 2547 * 0b0..The PWM synchronization in this pair of channels is disabled. 2548 * 0b1..The PWM synchronization in this pair of channels is enabled. 2549 */ 2550 #define FTM_COMBINE_SYNCEN1(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_SYNCEN1_SHIFT)) & FTM_COMBINE_SYNCEN1_MASK) 2551 #define FTM_COMBINE_FAULTEN1_MASK (0x4000U) 2552 #define FTM_COMBINE_FAULTEN1_SHIFT (14U) 2553 /*! FAULTEN1 - Fault Control Enable For n = 2 2554 * 0b0..The fault control in this pair of channels is disabled. 2555 * 0b1..The fault control in this pair of channels is enabled. 2556 */ 2557 #define FTM_COMBINE_FAULTEN1(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_FAULTEN1_SHIFT)) & FTM_COMBINE_FAULTEN1_MASK) 2558 #define FTM_COMBINE_COMBINE2_MASK (0x10000U) 2559 #define FTM_COMBINE_COMBINE2_SHIFT (16U) 2560 /*! COMBINE2 - Combine Channels For n = 4 2561 */ 2562 #define FTM_COMBINE_COMBINE2(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMBINE2_SHIFT)) & FTM_COMBINE_COMBINE2_MASK) 2563 #define FTM_COMBINE_COMP2_MASK (0x20000U) 2564 #define FTM_COMBINE_COMP2_SHIFT (17U) 2565 /*! COMP2 - Complement Of Channel (n) For n = 4 2566 * 0b0..The channel (n+1) output is the same as the channel (n) output. 2567 * 0b1..The channel (n+1) output is the complement of the channel (n) output. 2568 */ 2569 #define FTM_COMBINE_COMP2(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMP2_SHIFT)) & FTM_COMBINE_COMP2_MASK) 2570 #define FTM_COMBINE_DECAPEN2_MASK (0x40000U) 2571 #define FTM_COMBINE_DECAPEN2_SHIFT (18U) 2572 /*! DECAPEN2 - Dual Edge Capture Mode Enable For n = 4 2573 */ 2574 #define FTM_COMBINE_DECAPEN2(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAPEN2_SHIFT)) & FTM_COMBINE_DECAPEN2_MASK) 2575 #define FTM_COMBINE_DECAP2_MASK (0x80000U) 2576 #define FTM_COMBINE_DECAP2_SHIFT (19U) 2577 /*! DECAP2 - Dual Edge Capture Mode Captures For n = 4 2578 * 0b0..The dual edge captures are inactive. 2579 * 0b1..The dual edge captures are active. 2580 */ 2581 #define FTM_COMBINE_DECAP2(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAP2_SHIFT)) & FTM_COMBINE_DECAP2_MASK) 2582 #define FTM_COMBINE_DTEN2_MASK (0x100000U) 2583 #define FTM_COMBINE_DTEN2_SHIFT (20U) 2584 /*! DTEN2 - Deadtime Enable For n = 4 2585 * 0b0..The deadtime insertion in this pair of channels is disabled. 2586 * 0b1..The deadtime insertion in this pair of channels is enabled. 2587 */ 2588 #define FTM_COMBINE_DTEN2(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DTEN2_SHIFT)) & FTM_COMBINE_DTEN2_MASK) 2589 #define FTM_COMBINE_SYNCEN2_MASK (0x200000U) 2590 #define FTM_COMBINE_SYNCEN2_SHIFT (21U) 2591 /*! SYNCEN2 - Synchronization Enable For n = 4 2592 * 0b0..The PWM synchronization in this pair of channels is disabled. 2593 * 0b1..The PWM synchronization in this pair of channels is enabled. 2594 */ 2595 #define FTM_COMBINE_SYNCEN2(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_SYNCEN2_SHIFT)) & FTM_COMBINE_SYNCEN2_MASK) 2596 #define FTM_COMBINE_FAULTEN2_MASK (0x400000U) 2597 #define FTM_COMBINE_FAULTEN2_SHIFT (22U) 2598 /*! FAULTEN2 - Fault Control Enable For n = 4 2599 * 0b0..The fault control in this pair of channels is disabled. 2600 * 0b1..The fault control in this pair of channels is enabled. 2601 */ 2602 #define FTM_COMBINE_FAULTEN2(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_FAULTEN2_SHIFT)) & FTM_COMBINE_FAULTEN2_MASK) 2603 /*! @} */ 2604 2605 /*! @name DEADTIME - Deadtime Configuration */ 2606 /*! @{ */ 2607 #define FTM_DEADTIME_DTVAL_MASK (0x3FU) 2608 #define FTM_DEADTIME_DTVAL_SHIFT (0U) 2609 /*! DTVAL - Deadtime Value 2610 */ 2611 #define FTM_DEADTIME_DTVAL(x) (((uint32_t)(((uint32_t)(x)) << FTM_DEADTIME_DTVAL_SHIFT)) & FTM_DEADTIME_DTVAL_MASK) 2612 #define FTM_DEADTIME_DTPS_MASK (0xC0U) 2613 #define FTM_DEADTIME_DTPS_SHIFT (6U) 2614 /*! DTPS - Deadtime Prescaler Value 2615 * 0b0x..Divide the FTM input clock by 1. 2616 * 0b10..Divide the FTM input clock by 4. 2617 * 0b11..Divide the FTM input clock by 16. 2618 */ 2619 #define FTM_DEADTIME_DTPS(x) (((uint32_t)(((uint32_t)(x)) << FTM_DEADTIME_DTPS_SHIFT)) & FTM_DEADTIME_DTPS_MASK) 2620 /*! @} */ 2621 2622 /*! @name EXTTRIG - FTM External Trigger */ 2623 /*! @{ */ 2624 #define FTM_EXTTRIG_CH2TRIG_MASK (0x1U) 2625 #define FTM_EXTTRIG_CH2TRIG_SHIFT (0U) 2626 /*! CH2TRIG - Channel 2 External Trigger Enable 2627 * 0b0..The generation of this external trigger is disabled. 2628 * 0b1..The generation of this external trigger is enabled. 2629 */ 2630 #define FTM_EXTTRIG_CH2TRIG(x) (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_CH2TRIG_SHIFT)) & FTM_EXTTRIG_CH2TRIG_MASK) 2631 #define FTM_EXTTRIG_CH3TRIG_MASK (0x2U) 2632 #define FTM_EXTTRIG_CH3TRIG_SHIFT (1U) 2633 /*! CH3TRIG - Channel 3 External Trigger Enable 2634 * 0b0..The generation of this external trigger is disabled. 2635 * 0b1..The generation of this external trigger is enabled. 2636 */ 2637 #define FTM_EXTTRIG_CH3TRIG(x) (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_CH3TRIG_SHIFT)) & FTM_EXTTRIG_CH3TRIG_MASK) 2638 #define FTM_EXTTRIG_CH4TRIG_MASK (0x4U) 2639 #define FTM_EXTTRIG_CH4TRIG_SHIFT (2U) 2640 /*! CH4TRIG - Channel 4 External Trigger Enable 2641 * 0b0..The generation of this external trigger is disabled. 2642 * 0b1..The generation of this external trigger is enabled. 2643 */ 2644 #define FTM_EXTTRIG_CH4TRIG(x) (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_CH4TRIG_SHIFT)) & FTM_EXTTRIG_CH4TRIG_MASK) 2645 #define FTM_EXTTRIG_CH5TRIG_MASK (0x8U) 2646 #define FTM_EXTTRIG_CH5TRIG_SHIFT (3U) 2647 /*! CH5TRIG - Channel 5 External Trigger Enable 2648 * 0b0..The generation of this external trigger is disabled. 2649 * 0b1..The generation of this external trigger is enabled. 2650 */ 2651 #define FTM_EXTTRIG_CH5TRIG(x) (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_CH5TRIG_SHIFT)) & FTM_EXTTRIG_CH5TRIG_MASK) 2652 #define FTM_EXTTRIG_CH0TRIG_MASK (0x10U) 2653 #define FTM_EXTTRIG_CH0TRIG_SHIFT (4U) 2654 /*! CH0TRIG - Channel 0 External Trigger Enable 2655 * 0b0..The generation of this external trigger is disabled. 2656 * 0b1..The generation of this external trigger is enabled. 2657 */ 2658 #define FTM_EXTTRIG_CH0TRIG(x) (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_CH0TRIG_SHIFT)) & FTM_EXTTRIG_CH0TRIG_MASK) 2659 #define FTM_EXTTRIG_CH1TRIG_MASK (0x20U) 2660 #define FTM_EXTTRIG_CH1TRIG_SHIFT (5U) 2661 /*! CH1TRIG - Channel 1 External Trigger Enable 2662 * 0b0..The generation of this external trigger is disabled. 2663 * 0b1..The generation of this external trigger is enabled. 2664 */ 2665 #define FTM_EXTTRIG_CH1TRIG(x) (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_CH1TRIG_SHIFT)) & FTM_EXTTRIG_CH1TRIG_MASK) 2666 #define FTM_EXTTRIG_INITTRIGEN_MASK (0x40U) 2667 #define FTM_EXTTRIG_INITTRIGEN_SHIFT (6U) 2668 /*! INITTRIGEN - Initialization Trigger Enable 2669 * 0b0..The generation of initialization trigger is disabled. 2670 * 0b1..The generation of initialization trigger is enabled. 2671 */ 2672 #define FTM_EXTTRIG_INITTRIGEN(x) (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_INITTRIGEN_SHIFT)) & FTM_EXTTRIG_INITTRIGEN_MASK) 2673 #define FTM_EXTTRIG_TRIGF_MASK (0x80U) 2674 #define FTM_EXTTRIG_TRIGF_SHIFT (7U) 2675 /*! TRIGF - Channel Trigger Flag 2676 * 0b0..No channel trigger was generated. 2677 * 0b1..A channel trigger was generated. 2678 */ 2679 #define FTM_EXTTRIG_TRIGF(x) (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_TRIGF_SHIFT)) & FTM_EXTTRIG_TRIGF_MASK) 2680 /*! @} */ 2681 2682 /*! @name POL - Channels Polarity */ 2683 /*! @{ */ 2684 #define FTM_POL_POL0_MASK (0x1U) 2685 #define FTM_POL_POL0_SHIFT (0U) 2686 /*! POL0 - Channel 0 Polarity 2687 * 0b0..The channel polarity is active high. 2688 * 0b1..The channel polarity is active low. 2689 */ 2690 #define FTM_POL_POL0(x) (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL0_SHIFT)) & FTM_POL_POL0_MASK) 2691 #define FTM_POL_POL1_MASK (0x2U) 2692 #define FTM_POL_POL1_SHIFT (1U) 2693 /*! POL1 - Channel 1 Polarity 2694 * 0b0..The channel polarity is active high. 2695 * 0b1..The channel polarity is active low. 2696 */ 2697 #define FTM_POL_POL1(x) (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL1_SHIFT)) & FTM_POL_POL1_MASK) 2698 #define FTM_POL_POL2_MASK (0x4U) 2699 #define FTM_POL_POL2_SHIFT (2U) 2700 /*! POL2 - Channel 2 Polarity 2701 * 0b0..The channel polarity is active high. 2702 * 0b1..The channel polarity is active low. 2703 */ 2704 #define FTM_POL_POL2(x) (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL2_SHIFT)) & FTM_POL_POL2_MASK) 2705 #define FTM_POL_POL3_MASK (0x8U) 2706 #define FTM_POL_POL3_SHIFT (3U) 2707 /*! POL3 - Channel 3 Polarity 2708 * 0b0..The channel polarity is active high. 2709 * 0b1..The channel polarity is active low. 2710 */ 2711 #define FTM_POL_POL3(x) (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL3_SHIFT)) & FTM_POL_POL3_MASK) 2712 #define FTM_POL_POL4_MASK (0x10U) 2713 #define FTM_POL_POL4_SHIFT (4U) 2714 /*! POL4 - Channel 4 Polarity 2715 * 0b0..The channel polarity is active high. 2716 * 0b1..The channel polarity is active low. 2717 */ 2718 #define FTM_POL_POL4(x) (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL4_SHIFT)) & FTM_POL_POL4_MASK) 2719 #define FTM_POL_POL5_MASK (0x20U) 2720 #define FTM_POL_POL5_SHIFT (5U) 2721 /*! POL5 - Channel 5 Polarity 2722 * 0b0..The channel polarity is active high. 2723 * 0b1..The channel polarity is active low. 2724 */ 2725 #define FTM_POL_POL5(x) (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL5_SHIFT)) & FTM_POL_POL5_MASK) 2726 /*! @} */ 2727 2728 /*! @name FMS - Fault Mode Status */ 2729 /*! @{ */ 2730 #define FTM_FMS_FAULTF0_MASK (0x1U) 2731 #define FTM_FMS_FAULTF0_SHIFT (0U) 2732 /*! FAULTF0 - Fault Detection Flag 0 2733 * 0b0..No fault condition was detected at the fault input. 2734 * 0b1..A fault condition was detected at the fault input. 2735 */ 2736 #define FTM_FMS_FAULTF0(x) (((uint32_t)(((uint32_t)(x)) << FTM_FMS_FAULTF0_SHIFT)) & FTM_FMS_FAULTF0_MASK) 2737 #define FTM_FMS_FAULTF1_MASK (0x2U) 2738 #define FTM_FMS_FAULTF1_SHIFT (1U) 2739 /*! FAULTF1 - Fault Detection Flag 1 2740 * 0b0..No fault condition was detected at the fault input. 2741 * 0b1..A fault condition was detected at the fault input. 2742 */ 2743 #define FTM_FMS_FAULTF1(x) (((uint32_t)(((uint32_t)(x)) << FTM_FMS_FAULTF1_SHIFT)) & FTM_FMS_FAULTF1_MASK) 2744 #define FTM_FMS_FAULTF2_MASK (0x4U) 2745 #define FTM_FMS_FAULTF2_SHIFT (2U) 2746 /*! FAULTF2 - Fault Detection Flag 2 2747 * 0b0..No fault condition was detected at the fault input. 2748 * 0b1..A fault condition was detected at the fault input. 2749 */ 2750 #define FTM_FMS_FAULTF2(x) (((uint32_t)(((uint32_t)(x)) << FTM_FMS_FAULTF2_SHIFT)) & FTM_FMS_FAULTF2_MASK) 2751 #define FTM_FMS_FAULTF3_MASK (0x8U) 2752 #define FTM_FMS_FAULTF3_SHIFT (3U) 2753 /*! FAULTF3 - Fault Detection Flag 3 2754 * 0b0..No fault condition was detected at the fault input. 2755 * 0b1..A fault condition was detected at the fault input. 2756 */ 2757 #define FTM_FMS_FAULTF3(x) (((uint32_t)(((uint32_t)(x)) << FTM_FMS_FAULTF3_SHIFT)) & FTM_FMS_FAULTF3_MASK) 2758 #define FTM_FMS_FAULTIN_MASK (0x20U) 2759 #define FTM_FMS_FAULTIN_SHIFT (5U) 2760 /*! FAULTIN - Fault Inputs 2761 * 0b0..The logic OR of the enabled fault inputs is 0. 2762 * 0b1..The logic OR of the enabled fault inputs is 1. 2763 */ 2764 #define FTM_FMS_FAULTIN(x) (((uint32_t)(((uint32_t)(x)) << FTM_FMS_FAULTIN_SHIFT)) & FTM_FMS_FAULTIN_MASK) 2765 #define FTM_FMS_WPEN_MASK (0x40U) 2766 #define FTM_FMS_WPEN_SHIFT (6U) 2767 /*! WPEN - Write Protection Enable 2768 * 0b0..Write protection is disabled. Write protected bits can be written. 2769 * 0b1..Write protection is enabled. Write protected bits cannot be written. 2770 */ 2771 #define FTM_FMS_WPEN(x) (((uint32_t)(((uint32_t)(x)) << FTM_FMS_WPEN_SHIFT)) & FTM_FMS_WPEN_MASK) 2772 #define FTM_FMS_FAULTF_MASK (0x80U) 2773 #define FTM_FMS_FAULTF_SHIFT (7U) 2774 /*! FAULTF - Fault Detection Flag 2775 * 0b0..No fault condition was detected. 2776 * 0b1..A fault condition was detected. 2777 */ 2778 #define FTM_FMS_FAULTF(x) (((uint32_t)(((uint32_t)(x)) << FTM_FMS_FAULTF_SHIFT)) & FTM_FMS_FAULTF_MASK) 2779 /*! @} */ 2780 2781 /*! @name FILTER - Input Capture Filter Control */ 2782 /*! @{ */ 2783 #define FTM_FILTER_CH0FVAL_MASK (0xFU) 2784 #define FTM_FILTER_CH0FVAL_SHIFT (0U) 2785 /*! CH0FVAL - Channel 0 Input Filter 2786 */ 2787 #define FTM_FILTER_CH0FVAL(x) (((uint32_t)(((uint32_t)(x)) << FTM_FILTER_CH0FVAL_SHIFT)) & FTM_FILTER_CH0FVAL_MASK) 2788 #define FTM_FILTER_CH1FVAL_MASK (0xF0U) 2789 #define FTM_FILTER_CH1FVAL_SHIFT (4U) 2790 /*! CH1FVAL - Channel 1 Input Filter 2791 */ 2792 #define FTM_FILTER_CH1FVAL(x) (((uint32_t)(((uint32_t)(x)) << FTM_FILTER_CH1FVAL_SHIFT)) & FTM_FILTER_CH1FVAL_MASK) 2793 #define FTM_FILTER_CH2FVAL_MASK (0xF00U) 2794 #define FTM_FILTER_CH2FVAL_SHIFT (8U) 2795 /*! CH2FVAL - Channel 2 Input Filter 2796 */ 2797 #define FTM_FILTER_CH2FVAL(x) (((uint32_t)(((uint32_t)(x)) << FTM_FILTER_CH2FVAL_SHIFT)) & FTM_FILTER_CH2FVAL_MASK) 2798 #define FTM_FILTER_CH3FVAL_MASK (0xF000U) 2799 #define FTM_FILTER_CH3FVAL_SHIFT (12U) 2800 /*! CH3FVAL - Channel 3 Input Filter 2801 */ 2802 #define FTM_FILTER_CH3FVAL(x) (((uint32_t)(((uint32_t)(x)) << FTM_FILTER_CH3FVAL_SHIFT)) & FTM_FILTER_CH3FVAL_MASK) 2803 /*! @} */ 2804 2805 /*! @name FLTCTRL - Fault Control */ 2806 /*! @{ */ 2807 #define FTM_FLTCTRL_FAULT0EN_MASK (0x1U) 2808 #define FTM_FLTCTRL_FAULT0EN_SHIFT (0U) 2809 /*! FAULT0EN - Fault Input 0 Enable 2810 * 0b0..Fault input is disabled. 2811 * 0b1..Fault input is enabled. 2812 */ 2813 #define FTM_FLTCTRL_FAULT0EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FAULT0EN_SHIFT)) & FTM_FLTCTRL_FAULT0EN_MASK) 2814 #define FTM_FLTCTRL_FAULT1EN_MASK (0x2U) 2815 #define FTM_FLTCTRL_FAULT1EN_SHIFT (1U) 2816 /*! FAULT1EN - Fault Input 1 Enable 2817 * 0b0..Fault input is disabled. 2818 * 0b1..Fault input is enabled. 2819 */ 2820 #define FTM_FLTCTRL_FAULT1EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FAULT1EN_SHIFT)) & FTM_FLTCTRL_FAULT1EN_MASK) 2821 #define FTM_FLTCTRL_FAULT2EN_MASK (0x4U) 2822 #define FTM_FLTCTRL_FAULT2EN_SHIFT (2U) 2823 /*! FAULT2EN - Fault Input 2 Enable 2824 * 0b0..Fault input is disabled. 2825 * 0b1..Fault input is enabled. 2826 */ 2827 #define FTM_FLTCTRL_FAULT2EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FAULT2EN_SHIFT)) & FTM_FLTCTRL_FAULT2EN_MASK) 2828 #define FTM_FLTCTRL_FAULT3EN_MASK (0x8U) 2829 #define FTM_FLTCTRL_FAULT3EN_SHIFT (3U) 2830 /*! FAULT3EN - Fault Input 3 Enable 2831 * 0b0..Fault input is disabled. 2832 * 0b1..Fault input is enabled. 2833 */ 2834 #define FTM_FLTCTRL_FAULT3EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FAULT3EN_SHIFT)) & FTM_FLTCTRL_FAULT3EN_MASK) 2835 #define FTM_FLTCTRL_FFLTR0EN_MASK (0x10U) 2836 #define FTM_FLTCTRL_FFLTR0EN_SHIFT (4U) 2837 /*! FFLTR0EN - Fault Input 0 Filter Enable 2838 * 0b0..Fault input filter is disabled. 2839 * 0b1..Fault input filter is enabled. 2840 */ 2841 #define FTM_FLTCTRL_FFLTR0EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FFLTR0EN_SHIFT)) & FTM_FLTCTRL_FFLTR0EN_MASK) 2842 #define FTM_FLTCTRL_FFLTR1EN_MASK (0x20U) 2843 #define FTM_FLTCTRL_FFLTR1EN_SHIFT (5U) 2844 /*! FFLTR1EN - Fault Input 1 Filter Enable 2845 * 0b0..Fault input filter is disabled. 2846 * 0b1..Fault input filter is enabled. 2847 */ 2848 #define FTM_FLTCTRL_FFLTR1EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FFLTR1EN_SHIFT)) & FTM_FLTCTRL_FFLTR1EN_MASK) 2849 #define FTM_FLTCTRL_FFLTR2EN_MASK (0x40U) 2850 #define FTM_FLTCTRL_FFLTR2EN_SHIFT (6U) 2851 /*! FFLTR2EN - Fault Input 2 Filter Enable 2852 * 0b0..Fault input filter is disabled. 2853 * 0b1..Fault input filter is enabled. 2854 */ 2855 #define FTM_FLTCTRL_FFLTR2EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FFLTR2EN_SHIFT)) & FTM_FLTCTRL_FFLTR2EN_MASK) 2856 #define FTM_FLTCTRL_FFLTR3EN_MASK (0x80U) 2857 #define FTM_FLTCTRL_FFLTR3EN_SHIFT (7U) 2858 /*! FFLTR3EN - Fault Input 3 Filter Enable 2859 * 0b0..Fault input filter is disabled. 2860 * 0b1..Fault input filter is enabled. 2861 */ 2862 #define FTM_FLTCTRL_FFLTR3EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FFLTR3EN_SHIFT)) & FTM_FLTCTRL_FFLTR3EN_MASK) 2863 #define FTM_FLTCTRL_FFVAL_MASK (0xF00U) 2864 #define FTM_FLTCTRL_FFVAL_SHIFT (8U) 2865 /*! FFVAL - Fault Input Filter 2866 */ 2867 #define FTM_FLTCTRL_FFVAL(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FFVAL_SHIFT)) & FTM_FLTCTRL_FFVAL_MASK) 2868 #define FTM_FLTCTRL_FSTATE_MASK (0x8000U) 2869 #define FTM_FLTCTRL_FSTATE_SHIFT (15U) 2870 /*! FSTATE - Fault output state 2871 * 0b0..FTM outputs will be placed into safe values when fault events in ongoing (defined by POL bits). 2872 * 0b1..FTM outputs will be tri-stated when fault event is ongoing 2873 */ 2874 #define FTM_FLTCTRL_FSTATE(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FSTATE_SHIFT)) & FTM_FLTCTRL_FSTATE_MASK) 2875 /*! @} */ 2876 2877 /*! @name QDCTRL - Quadrature Decoder Control And Status */ 2878 /*! @{ */ 2879 #define FTM_QDCTRL_QUADEN_MASK (0x1U) 2880 #define FTM_QDCTRL_QUADEN_SHIFT (0U) 2881 /*! QUADEN - Quadrature Decoder Mode Enable 2882 * 0b0..Quadrature Decoder mode is disabled. 2883 * 0b1..Quadrature Decoder mode is enabled. 2884 */ 2885 #define FTM_QDCTRL_QUADEN(x) (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_QUADEN_SHIFT)) & FTM_QDCTRL_QUADEN_MASK) 2886 #define FTM_QDCTRL_TOFDIR_MASK (0x2U) 2887 #define FTM_QDCTRL_TOFDIR_SHIFT (1U) 2888 /*! TOFDIR - Timer Overflow Direction In Quadrature Decoder Mode 2889 * 0b0..TOF bit was set on the bottom of counting. There was an FTM counter decrement and FTM counter changes 2890 * from its minimum value (CNTIN register) to its maximum value (MOD register). 2891 * 0b1..TOF bit was set on the top of counting. There was an FTM counter increment and FTM counter changes from 2892 * its maximum value (MOD register) to its minimum value (CNTIN register). 2893 */ 2894 #define FTM_QDCTRL_TOFDIR(x) (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_TOFDIR_SHIFT)) & FTM_QDCTRL_TOFDIR_MASK) 2895 #define FTM_QDCTRL_QUADIR_MASK (0x4U) 2896 #define FTM_QDCTRL_QUADIR_SHIFT (2U) 2897 /*! QUADIR - FTM Counter Direction In Quadrature Decoder Mode 2898 * 0b0..Counting direction is decreasing (FTM counter decrement). 2899 * 0b1..Counting direction is increasing (FTM counter increment). 2900 */ 2901 #define FTM_QDCTRL_QUADIR(x) (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_QUADIR_SHIFT)) & FTM_QDCTRL_QUADIR_MASK) 2902 #define FTM_QDCTRL_QUADMODE_MASK (0x8U) 2903 #define FTM_QDCTRL_QUADMODE_SHIFT (3U) 2904 /*! QUADMODE - Quadrature Decoder Mode 2905 * 0b0..Phase A and phase B encoding mode. 2906 * 0b1..Count and direction encoding mode. 2907 */ 2908 #define FTM_QDCTRL_QUADMODE(x) (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_QUADMODE_SHIFT)) & FTM_QDCTRL_QUADMODE_MASK) 2909 #define FTM_QDCTRL_PHBPOL_MASK (0x10U) 2910 #define FTM_QDCTRL_PHBPOL_SHIFT (4U) 2911 /*! PHBPOL - Phase B Input Polarity 2912 * 0b0..Normal polarity. Phase B input signal is not inverted before identifying the rising and falling edges of this signal. 2913 * 0b1..Inverted polarity. Phase B input signal is inverted before identifying the rising and falling edges of this signal. 2914 */ 2915 #define FTM_QDCTRL_PHBPOL(x) (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_PHBPOL_SHIFT)) & FTM_QDCTRL_PHBPOL_MASK) 2916 #define FTM_QDCTRL_PHAPOL_MASK (0x20U) 2917 #define FTM_QDCTRL_PHAPOL_SHIFT (5U) 2918 /*! PHAPOL - Phase A Input Polarity 2919 * 0b0..Normal polarity. Phase A input signal is not inverted before identifying the rising and falling edges of this signal. 2920 * 0b1..Inverted polarity. Phase A input signal is inverted before identifying the rising and falling edges of this signal. 2921 */ 2922 #define FTM_QDCTRL_PHAPOL(x) (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_PHAPOL_SHIFT)) & FTM_QDCTRL_PHAPOL_MASK) 2923 #define FTM_QDCTRL_PHBFLTREN_MASK (0x40U) 2924 #define FTM_QDCTRL_PHBFLTREN_SHIFT (6U) 2925 /*! PHBFLTREN - Phase B Input Filter Enable 2926 * 0b0..Phase B input filter is disabled. 2927 * 0b1..Phase B input filter is enabled. 2928 */ 2929 #define FTM_QDCTRL_PHBFLTREN(x) (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_PHBFLTREN_SHIFT)) & FTM_QDCTRL_PHBFLTREN_MASK) 2930 #define FTM_QDCTRL_PHAFLTREN_MASK (0x80U) 2931 #define FTM_QDCTRL_PHAFLTREN_SHIFT (7U) 2932 /*! PHAFLTREN - Phase A Input Filter Enable 2933 * 0b0..Phase A input filter is disabled. 2934 * 0b1..Phase A input filter is enabled. 2935 */ 2936 #define FTM_QDCTRL_PHAFLTREN(x) (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_PHAFLTREN_SHIFT)) & FTM_QDCTRL_PHAFLTREN_MASK) 2937 /*! @} */ 2938 2939 /*! @name CONF - Configuration */ 2940 /*! @{ */ 2941 #define FTM_CONF_LDFQ_MASK (0x1FU) 2942 #define FTM_CONF_LDFQ_SHIFT (0U) 2943 /*! LDFQ - Frequency of the Reload Opportunities 2944 */ 2945 #define FTM_CONF_LDFQ(x) (((uint32_t)(((uint32_t)(x)) << FTM_CONF_LDFQ_SHIFT)) & FTM_CONF_LDFQ_MASK) 2946 #define FTM_CONF_BDMMODE_MASK (0xC0U) 2947 #define FTM_CONF_BDMMODE_SHIFT (6U) 2948 /*! BDMMODE - Debug Mode 2949 */ 2950 #define FTM_CONF_BDMMODE(x) (((uint32_t)(((uint32_t)(x)) << FTM_CONF_BDMMODE_SHIFT)) & FTM_CONF_BDMMODE_MASK) 2951 #define FTM_CONF_GTBEEN_MASK (0x200U) 2952 #define FTM_CONF_GTBEEN_SHIFT (9U) 2953 /*! GTBEEN - Global Time Base Enable 2954 * 0b0..Use of an external global time base is disabled. 2955 * 0b1..Use of an external global time base is enabled. 2956 */ 2957 #define FTM_CONF_GTBEEN(x) (((uint32_t)(((uint32_t)(x)) << FTM_CONF_GTBEEN_SHIFT)) & FTM_CONF_GTBEEN_MASK) 2958 #define FTM_CONF_GTBEOUT_MASK (0x400U) 2959 #define FTM_CONF_GTBEOUT_SHIFT (10U) 2960 /*! GTBEOUT - Global Time Base Output 2961 * 0b0..A global time base signal generation is disabled. 2962 * 0b1..A global time base signal generation is enabled. 2963 */ 2964 #define FTM_CONF_GTBEOUT(x) (((uint32_t)(((uint32_t)(x)) << FTM_CONF_GTBEOUT_SHIFT)) & FTM_CONF_GTBEOUT_MASK) 2965 #define FTM_CONF_ITRIGR_MASK (0x800U) 2966 #define FTM_CONF_ITRIGR_SHIFT (11U) 2967 /*! ITRIGR - Initialization trigger on Reload Point 2968 * 0b0..Initialization trigger is generated on counter wrap events. 2969 * 0b1..Initialization trigger is generated when a reload point is reached. 2970 */ 2971 #define FTM_CONF_ITRIGR(x) (((uint32_t)(((uint32_t)(x)) << FTM_CONF_ITRIGR_SHIFT)) & FTM_CONF_ITRIGR_MASK) 2972 /*! @} */ 2973 2974 /*! @name FLTPOL - FTM Fault Input Polarity */ 2975 /*! @{ */ 2976 #define FTM_FLTPOL_FLT0POL_MASK (0x1U) 2977 #define FTM_FLTPOL_FLT0POL_SHIFT (0U) 2978 /*! FLT0POL - Fault Input 0 Polarity 2979 * 0b0..The fault input polarity is active high. A 1 at the fault input indicates a fault. 2980 * 0b1..The fault input polarity is active low. A 0 at the fault input indicates a fault. 2981 */ 2982 #define FTM_FLTPOL_FLT0POL(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTPOL_FLT0POL_SHIFT)) & FTM_FLTPOL_FLT0POL_MASK) 2983 #define FTM_FLTPOL_FLT1POL_MASK (0x2U) 2984 #define FTM_FLTPOL_FLT1POL_SHIFT (1U) 2985 /*! FLT1POL - Fault Input 1 Polarity 2986 * 0b0..The fault input polarity is active high. A 1 at the fault input indicates a fault. 2987 * 0b1..The fault input polarity is active low. A 0 at the fault input indicates a fault. 2988 */ 2989 #define FTM_FLTPOL_FLT1POL(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTPOL_FLT1POL_SHIFT)) & FTM_FLTPOL_FLT1POL_MASK) 2990 #define FTM_FLTPOL_FLT2POL_MASK (0x4U) 2991 #define FTM_FLTPOL_FLT2POL_SHIFT (2U) 2992 /*! FLT2POL - Fault Input 2 Polarity 2993 * 0b0..The fault input polarity is active high. A 1 at the fault input indicates a fault. 2994 * 0b1..The fault input polarity is active low. A 0 at the fault input indicates a fault. 2995 */ 2996 #define FTM_FLTPOL_FLT2POL(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTPOL_FLT2POL_SHIFT)) & FTM_FLTPOL_FLT2POL_MASK) 2997 #define FTM_FLTPOL_FLT3POL_MASK (0x8U) 2998 #define FTM_FLTPOL_FLT3POL_SHIFT (3U) 2999 /*! FLT3POL - Fault Input 3 Polarity 3000 * 0b0..The fault input polarity is active high. A 1 at the fault input indicates a fault. 3001 * 0b1..The fault input polarity is active low. A 0 at the fault input indicates a fault. 3002 */ 3003 #define FTM_FLTPOL_FLT3POL(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTPOL_FLT3POL_SHIFT)) & FTM_FLTPOL_FLT3POL_MASK) 3004 /*! @} */ 3005 3006 /*! @name SYNCONF - Synchronization Configuration */ 3007 /*! @{ */ 3008 #define FTM_SYNCONF_HWTRIGMODE_MASK (0x1U) 3009 #define FTM_SYNCONF_HWTRIGMODE_SHIFT (0U) 3010 /*! HWTRIGMODE - Hardware Trigger Mode 3011 * 0b0..FTM clears the TRIGj bit when the hardware trigger j is detected, where j = 0, 1,2. 3012 * 0b1..FTM does not clear the TRIGj bit when the hardware trigger j is detected, where j = 0, 1,2. 3013 */ 3014 #define FTM_SYNCONF_HWTRIGMODE(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_HWTRIGMODE_SHIFT)) & FTM_SYNCONF_HWTRIGMODE_MASK) 3015 #define FTM_SYNCONF_CNTINC_MASK (0x4U) 3016 #define FTM_SYNCONF_CNTINC_SHIFT (2U) 3017 /*! CNTINC - CNTIN Register Synchronization 3018 * 0b0..CNTIN register is updated with its buffer value at all rising edges of FTM input clock. 3019 * 0b1..CNTIN register is updated with its buffer value by the PWM synchronization. 3020 */ 3021 #define FTM_SYNCONF_CNTINC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_CNTINC_SHIFT)) & FTM_SYNCONF_CNTINC_MASK) 3022 #define FTM_SYNCONF_INVC_MASK (0x10U) 3023 #define FTM_SYNCONF_INVC_SHIFT (4U) 3024 /*! INVC - INVCTRL Register Synchronization 3025 * 0b0..INVCTRL register is updated with its buffer value at all rising edges of FTM input clock. 3026 * 0b1..INVCTRL register is updated with its buffer value by the PWM synchronization. 3027 */ 3028 #define FTM_SYNCONF_INVC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_INVC_SHIFT)) & FTM_SYNCONF_INVC_MASK) 3029 #define FTM_SYNCONF_SWOC_MASK (0x20U) 3030 #define FTM_SYNCONF_SWOC_SHIFT (5U) 3031 /*! SWOC - SWOCTRL Register Synchronization 3032 * 0b0..SWOCTRL register is updated with its buffer value at all rising edges of FTM input clock. 3033 * 0b1..SWOCTRL register is updated with its buffer value by the PWM synchronization. 3034 */ 3035 #define FTM_SYNCONF_SWOC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_SWOC_SHIFT)) & FTM_SYNCONF_SWOC_MASK) 3036 #define FTM_SYNCONF_SYNCMODE_MASK (0x80U) 3037 #define FTM_SYNCONF_SYNCMODE_SHIFT (7U) 3038 /*! SYNCMODE - Synchronization Mode 3039 * 0b0..Legacy PWM synchronization is selected. 3040 * 0b1..Enhanced PWM synchronization is selected. 3041 */ 3042 #define FTM_SYNCONF_SYNCMODE(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_SYNCMODE_SHIFT)) & FTM_SYNCONF_SYNCMODE_MASK) 3043 #define FTM_SYNCONF_SWRSTCNT_MASK (0x100U) 3044 #define FTM_SYNCONF_SWRSTCNT_SHIFT (8U) 3045 /*! SWRSTCNT - FTM counter synchronization is activated by the software trigger 3046 * 0b0..The software trigger does not activate the FTM counter synchronization. 3047 * 0b1..The software trigger activates the FTM counter synchronization. 3048 */ 3049 #define FTM_SYNCONF_SWRSTCNT(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_SWRSTCNT_SHIFT)) & FTM_SYNCONF_SWRSTCNT_MASK) 3050 #define FTM_SYNCONF_SWWRBUF_MASK (0x200U) 3051 #define FTM_SYNCONF_SWWRBUF_SHIFT (9U) 3052 /*! SWWRBUF - MOD, HCR, CNTIN, and CV registers synchronization is activated by the software trigger 3053 * 0b0..The software trigger does not activate MOD, HCR, CNTIN, and CV registers synchronization. 3054 * 0b1..The software trigger activates MOD, HCR, CNTIN, and CV registers synchronization. 3055 */ 3056 #define FTM_SYNCONF_SWWRBUF(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_SWWRBUF_SHIFT)) & FTM_SYNCONF_SWWRBUF_MASK) 3057 #define FTM_SYNCONF_SWOM_MASK (0x400U) 3058 #define FTM_SYNCONF_SWOM_SHIFT (10U) 3059 /*! SWOM - Output mask synchronization is activated by the software trigger 3060 * 0b0..The software trigger does not activate the OUTMASK register synchronization. 3061 * 0b1..The software trigger activates the OUTMASK register synchronization. 3062 */ 3063 #define FTM_SYNCONF_SWOM(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_SWOM_SHIFT)) & FTM_SYNCONF_SWOM_MASK) 3064 #define FTM_SYNCONF_SWINVC_MASK (0x800U) 3065 #define FTM_SYNCONF_SWINVC_SHIFT (11U) 3066 /*! SWINVC - Inverting control synchronization is activated by the software trigger 3067 * 0b0..The software trigger does not activate the INVCTRL register synchronization. 3068 * 0b1..The software trigger activates the INVCTRL register synchronization. 3069 */ 3070 #define FTM_SYNCONF_SWINVC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_SWINVC_SHIFT)) & FTM_SYNCONF_SWINVC_MASK) 3071 #define FTM_SYNCONF_SWSOC_MASK (0x1000U) 3072 #define FTM_SYNCONF_SWSOC_SHIFT (12U) 3073 /*! SWSOC - Software output control synchronization is activated by the software trigger 3074 * 0b0..The software trigger does not activate the SWOCTRL register synchronization. 3075 * 0b1..The software trigger activates the SWOCTRL register synchronization. 3076 */ 3077 #define FTM_SYNCONF_SWSOC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_SWSOC_SHIFT)) & FTM_SYNCONF_SWSOC_MASK) 3078 #define FTM_SYNCONF_HWRSTCNT_MASK (0x10000U) 3079 #define FTM_SYNCONF_HWRSTCNT_SHIFT (16U) 3080 /*! HWRSTCNT - FTM counter synchronization is activated by a hardware trigger 3081 * 0b0..A hardware trigger does not activate the FTM counter synchronization. 3082 * 0b1..A hardware trigger activates the FTM counter synchronization. 3083 */ 3084 #define FTM_SYNCONF_HWRSTCNT(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_HWRSTCNT_SHIFT)) & FTM_SYNCONF_HWRSTCNT_MASK) 3085 #define FTM_SYNCONF_HWWRBUF_MASK (0x20000U) 3086 #define FTM_SYNCONF_HWWRBUF_SHIFT (17U) 3087 /*! HWWRBUF - MOD, HCR, CNTIN, and CV registers synchronization is activated by a hardware trigger 3088 * 0b0..A hardware trigger does not activate MOD, HCR, CNTIN, and CV registers synchronization. 3089 * 0b1..A hardware trigger activates MOD, HCR, CNTIN, and CV registers synchronization. 3090 */ 3091 #define FTM_SYNCONF_HWWRBUF(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_HWWRBUF_SHIFT)) & FTM_SYNCONF_HWWRBUF_MASK) 3092 #define FTM_SYNCONF_HWOM_MASK (0x40000U) 3093 #define FTM_SYNCONF_HWOM_SHIFT (18U) 3094 /*! HWOM - Output mask synchronization is activated by a hardware trigger 3095 * 0b0..A hardware trigger does not activate the OUTMASK register synchronization. 3096 * 0b1..A hardware trigger activates the OUTMASK register synchronization. 3097 */ 3098 #define FTM_SYNCONF_HWOM(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_HWOM_SHIFT)) & FTM_SYNCONF_HWOM_MASK) 3099 #define FTM_SYNCONF_HWINVC_MASK (0x80000U) 3100 #define FTM_SYNCONF_HWINVC_SHIFT (19U) 3101 /*! HWINVC - Inverting control synchronization is activated by a hardware trigger 3102 * 0b0..A hardware trigger does not activate the INVCTRL register synchronization. 3103 * 0b1..A hardware trigger activates the INVCTRL register synchronization. 3104 */ 3105 #define FTM_SYNCONF_HWINVC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_HWINVC_SHIFT)) & FTM_SYNCONF_HWINVC_MASK) 3106 #define FTM_SYNCONF_HWSOC_MASK (0x100000U) 3107 #define FTM_SYNCONF_HWSOC_SHIFT (20U) 3108 /*! HWSOC - Software output control synchronization is activated by a hardware trigger 3109 * 0b0..A hardware trigger does not activate the SWOCTRL register synchronization. 3110 * 0b1..A hardware trigger activates the SWOCTRL register synchronization. 3111 */ 3112 #define FTM_SYNCONF_HWSOC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_HWSOC_SHIFT)) & FTM_SYNCONF_HWSOC_MASK) 3113 /*! @} */ 3114 3115 /*! @name INVCTRL - FTM Inverting Control */ 3116 /*! @{ */ 3117 #define FTM_INVCTRL_INV0EN_MASK (0x1U) 3118 #define FTM_INVCTRL_INV0EN_SHIFT (0U) 3119 /*! INV0EN - Pair Channels 0 Inverting Enable 3120 * 0b0..Inverting is disabled. 3121 * 0b1..Inverting is enabled. 3122 */ 3123 #define FTM_INVCTRL_INV0EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_INVCTRL_INV0EN_SHIFT)) & FTM_INVCTRL_INV0EN_MASK) 3124 #define FTM_INVCTRL_INV1EN_MASK (0x2U) 3125 #define FTM_INVCTRL_INV1EN_SHIFT (1U) 3126 /*! INV1EN - Pair Channels 1 Inverting Enable 3127 * 0b0..Inverting is disabled. 3128 * 0b1..Inverting is enabled. 3129 */ 3130 #define FTM_INVCTRL_INV1EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_INVCTRL_INV1EN_SHIFT)) & FTM_INVCTRL_INV1EN_MASK) 3131 #define FTM_INVCTRL_INV2EN_MASK (0x4U) 3132 #define FTM_INVCTRL_INV2EN_SHIFT (2U) 3133 /*! INV2EN - Pair Channels 2 Inverting Enable 3134 * 0b0..Inverting is disabled. 3135 * 0b1..Inverting is enabled. 3136 */ 3137 #define FTM_INVCTRL_INV2EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_INVCTRL_INV2EN_SHIFT)) & FTM_INVCTRL_INV2EN_MASK) 3138 /*! @} */ 3139 3140 /*! @name SWOCTRL - FTM Software Output Control */ 3141 /*! @{ */ 3142 #define FTM_SWOCTRL_CH0OC_MASK (0x1U) 3143 #define FTM_SWOCTRL_CH0OC_SHIFT (0U) 3144 /*! CH0OC - Channel 0 Software Output Control Enable 3145 * 0b0..The channel output is not affected by software output control. 3146 * 0b1..The channel output is affected by software output control. 3147 */ 3148 #define FTM_SWOCTRL_CH0OC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH0OC_SHIFT)) & FTM_SWOCTRL_CH0OC_MASK) 3149 #define FTM_SWOCTRL_CH1OC_MASK (0x2U) 3150 #define FTM_SWOCTRL_CH1OC_SHIFT (1U) 3151 /*! CH1OC - Channel 1 Software Output Control Enable 3152 * 0b0..The channel output is not affected by software output control. 3153 * 0b1..The channel output is affected by software output control. 3154 */ 3155 #define FTM_SWOCTRL_CH1OC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH1OC_SHIFT)) & FTM_SWOCTRL_CH1OC_MASK) 3156 #define FTM_SWOCTRL_CH2OC_MASK (0x4U) 3157 #define FTM_SWOCTRL_CH2OC_SHIFT (2U) 3158 /*! CH2OC - Channel 2 Software Output Control Enable 3159 * 0b0..The channel output is not affected by software output control. 3160 * 0b1..The channel output is affected by software output control. 3161 */ 3162 #define FTM_SWOCTRL_CH2OC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH2OC_SHIFT)) & FTM_SWOCTRL_CH2OC_MASK) 3163 #define FTM_SWOCTRL_CH3OC_MASK (0x8U) 3164 #define FTM_SWOCTRL_CH3OC_SHIFT (3U) 3165 /*! CH3OC - Channel 3 Software Output Control Enable 3166 * 0b0..The channel output is not affected by software output control. 3167 * 0b1..The channel output is affected by software output control. 3168 */ 3169 #define FTM_SWOCTRL_CH3OC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH3OC_SHIFT)) & FTM_SWOCTRL_CH3OC_MASK) 3170 #define FTM_SWOCTRL_CH4OC_MASK (0x10U) 3171 #define FTM_SWOCTRL_CH4OC_SHIFT (4U) 3172 /*! CH4OC - Channel 4 Software Output Control Enable 3173 * 0b0..The channel output is not affected by software output control. 3174 * 0b1..The channel output is affected by software output control. 3175 */ 3176 #define FTM_SWOCTRL_CH4OC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH4OC_SHIFT)) & FTM_SWOCTRL_CH4OC_MASK) 3177 #define FTM_SWOCTRL_CH5OC_MASK (0x20U) 3178 #define FTM_SWOCTRL_CH5OC_SHIFT (5U) 3179 /*! CH5OC - Channel 5 Software Output Control Enable 3180 * 0b0..The channel output is not affected by software output control. 3181 * 0b1..The channel output is affected by software output control. 3182 */ 3183 #define FTM_SWOCTRL_CH5OC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH5OC_SHIFT)) & FTM_SWOCTRL_CH5OC_MASK) 3184 #define FTM_SWOCTRL_CH0OCV_MASK (0x100U) 3185 #define FTM_SWOCTRL_CH0OCV_SHIFT (8U) 3186 /*! CH0OCV - Channel 0 Software Output Control Value 3187 * 0b0..The software output control forces 0 to the channel output. 3188 * 0b1..The software output control forces 1 to the channel output. 3189 */ 3190 #define FTM_SWOCTRL_CH0OCV(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH0OCV_SHIFT)) & FTM_SWOCTRL_CH0OCV_MASK) 3191 #define FTM_SWOCTRL_CH1OCV_MASK (0x200U) 3192 #define FTM_SWOCTRL_CH1OCV_SHIFT (9U) 3193 /*! CH1OCV - Channel 1 Software Output Control Value 3194 * 0b0..The software output control forces 0 to the channel output. 3195 * 0b1..The software output control forces 1 to the channel output. 3196 */ 3197 #define FTM_SWOCTRL_CH1OCV(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH1OCV_SHIFT)) & FTM_SWOCTRL_CH1OCV_MASK) 3198 #define FTM_SWOCTRL_CH2OCV_MASK (0x400U) 3199 #define FTM_SWOCTRL_CH2OCV_SHIFT (10U) 3200 /*! CH2OCV - Channel 2 Software Output Control Value 3201 * 0b0..The software output control forces 0 to the channel output. 3202 * 0b1..The software output control forces 1 to the channel output. 3203 */ 3204 #define FTM_SWOCTRL_CH2OCV(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH2OCV_SHIFT)) & FTM_SWOCTRL_CH2OCV_MASK) 3205 #define FTM_SWOCTRL_CH3OCV_MASK (0x800U) 3206 #define FTM_SWOCTRL_CH3OCV_SHIFT (11U) 3207 /*! CH3OCV - Channel 3 Software Output Control Value 3208 * 0b0..The software output control forces 0 to the channel output. 3209 * 0b1..The software output control forces 1 to the channel output. 3210 */ 3211 #define FTM_SWOCTRL_CH3OCV(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH3OCV_SHIFT)) & FTM_SWOCTRL_CH3OCV_MASK) 3212 #define FTM_SWOCTRL_CH4OCV_MASK (0x1000U) 3213 #define FTM_SWOCTRL_CH4OCV_SHIFT (12U) 3214 /*! CH4OCV - Channel 4 Software Output Control Value 3215 * 0b0..The software output control forces 0 to the channel output. 3216 * 0b1..The software output control forces 1 to the channel output. 3217 */ 3218 #define FTM_SWOCTRL_CH4OCV(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH4OCV_SHIFT)) & FTM_SWOCTRL_CH4OCV_MASK) 3219 #define FTM_SWOCTRL_CH5OCV_MASK (0x2000U) 3220 #define FTM_SWOCTRL_CH5OCV_SHIFT (13U) 3221 /*! CH5OCV - Channel 5 Software Output Control Value 3222 * 0b0..The software output control forces 0 to the channel output. 3223 * 0b1..The software output control forces 1 to the channel output. 3224 */ 3225 #define FTM_SWOCTRL_CH5OCV(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH5OCV_SHIFT)) & FTM_SWOCTRL_CH5OCV_MASK) 3226 /*! @} */ 3227 3228 /*! @name PWMLOAD - FTM PWM Load */ 3229 /*! @{ */ 3230 #define FTM_PWMLOAD_CH0SEL_MASK (0x1U) 3231 #define FTM_PWMLOAD_CH0SEL_SHIFT (0U) 3232 /*! CH0SEL - Channel 0 Select 3233 * 0b0..Channel match is not included as a reload opportunity. 3234 * 0b1..Channel match is included as a reload opportunity. 3235 */ 3236 #define FTM_PWMLOAD_CH0SEL(x) (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH0SEL_SHIFT)) & FTM_PWMLOAD_CH0SEL_MASK) 3237 #define FTM_PWMLOAD_CH1SEL_MASK (0x2U) 3238 #define FTM_PWMLOAD_CH1SEL_SHIFT (1U) 3239 /*! CH1SEL - Channel 1 Select 3240 * 0b0..Channel match is not included as a reload opportunity. 3241 * 0b1..Channel match is included as a reload opportunity. 3242 */ 3243 #define FTM_PWMLOAD_CH1SEL(x) (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH1SEL_SHIFT)) & FTM_PWMLOAD_CH1SEL_MASK) 3244 #define FTM_PWMLOAD_CH2SEL_MASK (0x4U) 3245 #define FTM_PWMLOAD_CH2SEL_SHIFT (2U) 3246 /*! CH2SEL - Channel 2 Select 3247 * 0b0..Channel match is not included as a reload opportunity. 3248 * 0b1..Channel match is included as a reload opportunity. 3249 */ 3250 #define FTM_PWMLOAD_CH2SEL(x) (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH2SEL_SHIFT)) & FTM_PWMLOAD_CH2SEL_MASK) 3251 #define FTM_PWMLOAD_CH3SEL_MASK (0x8U) 3252 #define FTM_PWMLOAD_CH3SEL_SHIFT (3U) 3253 /*! CH3SEL - Channel 3 Select 3254 * 0b0..Channel match is not included as a reload opportunity. 3255 * 0b1..Channel match is included as a reload opportunity. 3256 */ 3257 #define FTM_PWMLOAD_CH3SEL(x) (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH3SEL_SHIFT)) & FTM_PWMLOAD_CH3SEL_MASK) 3258 #define FTM_PWMLOAD_CH4SEL_MASK (0x10U) 3259 #define FTM_PWMLOAD_CH4SEL_SHIFT (4U) 3260 /*! CH4SEL - Channel 4 Select 3261 * 0b0..Channel match is not included as a reload opportunity. 3262 * 0b1..Channel match is included as a reload opportunity. 3263 */ 3264 #define FTM_PWMLOAD_CH4SEL(x) (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH4SEL_SHIFT)) & FTM_PWMLOAD_CH4SEL_MASK) 3265 #define FTM_PWMLOAD_CH5SEL_MASK (0x20U) 3266 #define FTM_PWMLOAD_CH5SEL_SHIFT (5U) 3267 /*! CH5SEL - Channel 5 Select 3268 * 0b0..Channel match is not included as a reload opportunity. 3269 * 0b1..Channel match is included as a reload opportunity. 3270 */ 3271 #define FTM_PWMLOAD_CH5SEL(x) (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH5SEL_SHIFT)) & FTM_PWMLOAD_CH5SEL_MASK) 3272 #define FTM_PWMLOAD_HCSEL_MASK (0x100U) 3273 #define FTM_PWMLOAD_HCSEL_SHIFT (8U) 3274 /*! HCSEL - Half Cycle Select 3275 * 0b0..Half cycle reload is disabled and it is not considered as a reload opportunity. 3276 * 0b1..Half cycle reload is enabled and it is considered as a reload opportunity. 3277 */ 3278 #define FTM_PWMLOAD_HCSEL(x) (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_HCSEL_SHIFT)) & FTM_PWMLOAD_HCSEL_MASK) 3279 #define FTM_PWMLOAD_LDOK_MASK (0x200U) 3280 #define FTM_PWMLOAD_LDOK_SHIFT (9U) 3281 /*! LDOK - Load Enable 3282 * 0b0..Loading updated values is disabled. 3283 * 0b1..Loading updated values is enabled. 3284 */ 3285 #define FTM_PWMLOAD_LDOK(x) (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_LDOK_SHIFT)) & FTM_PWMLOAD_LDOK_MASK) 3286 #define FTM_PWMLOAD_GLEN_MASK (0x400U) 3287 #define FTM_PWMLOAD_GLEN_SHIFT (10U) 3288 /*! GLEN - Global Load Enable 3289 * 0b0..Global Load Ok disabled. 3290 * 0b1..Global Load OK enabled. A pulse event on the module global load input sets the LDOK bit. 3291 */ 3292 #define FTM_PWMLOAD_GLEN(x) (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_GLEN_SHIFT)) & FTM_PWMLOAD_GLEN_MASK) 3293 #define FTM_PWMLOAD_GLDOK_MASK (0x800U) 3294 #define FTM_PWMLOAD_GLDOK_SHIFT (11U) 3295 /*! GLDOK - Global Load OK 3296 * 0b0..No action. 3297 * 0b1..LDOK bit is set. 3298 */ 3299 #define FTM_PWMLOAD_GLDOK(x) (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_GLDOK_SHIFT)) & FTM_PWMLOAD_GLDOK_MASK) 3300 /*! @} */ 3301 3302 /*! @name HCR - Half Cycle Register */ 3303 /*! @{ */ 3304 #define FTM_HCR_HCVAL_MASK (0xFFFFU) 3305 #define FTM_HCR_HCVAL_SHIFT (0U) 3306 /*! HCVAL - Half Cycle Value 3307 */ 3308 #define FTM_HCR_HCVAL(x) (((uint32_t)(((uint32_t)(x)) << FTM_HCR_HCVAL_SHIFT)) & FTM_HCR_HCVAL_MASK) 3309 /*! @} */ 3310 3311 /*! @name MOD_MIRROR - Mirror of Modulo Value */ 3312 /*! @{ */ 3313 #define FTM_MOD_MIRROR_FRACMOD_MASK (0xF800U) 3314 #define FTM_MOD_MIRROR_FRACMOD_SHIFT (11U) 3315 /*! FRACMOD - Modulo Fractional Value 3316 */ 3317 #define FTM_MOD_MIRROR_FRACMOD(x) (((uint32_t)(((uint32_t)(x)) << FTM_MOD_MIRROR_FRACMOD_SHIFT)) & FTM_MOD_MIRROR_FRACMOD_MASK) 3318 #define FTM_MOD_MIRROR_MOD_MASK (0xFFFF0000U) 3319 #define FTM_MOD_MIRROR_MOD_SHIFT (16U) 3320 /*! MOD - Mirror of the Modulo Integer Value 3321 */ 3322 #define FTM_MOD_MIRROR_MOD(x) (((uint32_t)(((uint32_t)(x)) << FTM_MOD_MIRROR_MOD_SHIFT)) & FTM_MOD_MIRROR_MOD_MASK) 3323 /*! @} */ 3324 3325 /*! @name CV_MIRROR - Mirror of Channel (n) Match Value */ 3326 /*! @{ */ 3327 #define FTM_CV_MIRROR_FRACVAL_MASK (0xF800U) 3328 #define FTM_CV_MIRROR_FRACVAL_SHIFT (11U) 3329 /*! FRACVAL - Channel (n) Match Fractional Value 3330 */ 3331 #define FTM_CV_MIRROR_FRACVAL(x) (((uint32_t)(((uint32_t)(x)) << FTM_CV_MIRROR_FRACVAL_SHIFT)) & FTM_CV_MIRROR_FRACVAL_MASK) 3332 #define FTM_CV_MIRROR_VAL_MASK (0xFFFF0000U) 3333 #define FTM_CV_MIRROR_VAL_SHIFT (16U) 3334 /*! VAL - Mirror of the Channel (n) Match Integer Value 3335 */ 3336 #define FTM_CV_MIRROR_VAL(x) (((uint32_t)(((uint32_t)(x)) << FTM_CV_MIRROR_VAL_SHIFT)) & FTM_CV_MIRROR_VAL_MASK) 3337 /*! @} */ 3338 3339 /* The count of FTM_CV_MIRROR */ 3340 #define FTM_CV_MIRROR_COUNT (6U) 3341 3342 3343 /*! 3344 * @} 3345 */ /* end of group FTM_Register_Masks */ 3346 3347 3348 /* FTM - Peripheral instance base addresses */ 3349 /** Peripheral FTM0 base address */ 3350 #define FTM0_BASE (0x40038000u) 3351 /** Peripheral FTM0 base pointer */ 3352 #define FTM0 ((FTM_Type *)FTM0_BASE) 3353 /** Peripheral FTM1 base address */ 3354 #define FTM1_BASE (0x40039000u) 3355 /** Peripheral FTM1 base pointer */ 3356 #define FTM1 ((FTM_Type *)FTM1_BASE) 3357 /** Array initializer of FTM peripheral base addresses */ 3358 #define FTM_BASE_ADDRS { FTM0_BASE, FTM1_BASE } 3359 /** Array initializer of FTM peripheral base pointers */ 3360 #define FTM_BASE_PTRS { FTM0, FTM1 } 3361 /** Interrupt vectors for the FTM peripheral type */ 3362 #define FTM_IRQS { FTM0_IRQn, FTM1_IRQn } 3363 3364 /*! 3365 * @} 3366 */ /* end of group FTM_Peripheral_Access_Layer */ 3367 3368 3369 /* ---------------------------------------------------------------------------- 3370 -- GPIO Peripheral Access Layer 3371 ---------------------------------------------------------------------------- */ 3372 3373 /*! 3374 * @addtogroup GPIO_Peripheral_Access_Layer GPIO Peripheral Access Layer 3375 * @{ 3376 */ 3377 3378 /** GPIO - Register Layout Typedef */ 3379 typedef struct { 3380 __IO uint32_t PDOR; /**< Port Data Output Register, offset: 0x0 */ 3381 __O uint32_t PSOR; /**< Port Set Output Register, offset: 0x4 */ 3382 __O uint32_t PCOR; /**< Port Clear Output Register, offset: 0x8 */ 3383 __O uint32_t PTOR; /**< Port Toggle Output Register, offset: 0xC */ 3384 __I uint32_t PDIR; /**< Port Data Input Register, offset: 0x10 */ 3385 __IO uint32_t PDDR; /**< Port Data Direction Register, offset: 0x14 */ 3386 } GPIO_Type; 3387 3388 /* ---------------------------------------------------------------------------- 3389 -- GPIO Register Masks 3390 ---------------------------------------------------------------------------- */ 3391 3392 /*! 3393 * @addtogroup GPIO_Register_Masks GPIO Register Masks 3394 * @{ 3395 */ 3396 3397 /*! @name PDOR - Port Data Output Register */ 3398 /*! @{ */ 3399 #define GPIO_PDOR_PDO_MASK (0xFFFFFFFFU) 3400 #define GPIO_PDOR_PDO_SHIFT (0U) 3401 /*! PDO - Port Data Output 3402 * 0b00000000000000000000000000000000..Logic level 0 is driven on pin, provided pin is configured for general-purpose output. 3403 * 0b00000000000000000000000000000001..Logic level 1 is driven on pin, provided pin is configured for general-purpose output. 3404 */ 3405 #define GPIO_PDOR_PDO(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO_SHIFT)) & GPIO_PDOR_PDO_MASK) 3406 /*! @} */ 3407 3408 /*! @name PSOR - Port Set Output Register */ 3409 /*! @{ */ 3410 #define GPIO_PSOR_PTSO_MASK (0xFFFFFFFFU) 3411 #define GPIO_PSOR_PTSO_SHIFT (0U) 3412 /*! PTSO - Port Set Output 3413 * 0b00000000000000000000000000000000..Corresponding bit in PDORn does not change. 3414 * 0b00000000000000000000000000000001..Corresponding bit in PDORn is set to logic 1. 3415 */ 3416 #define GPIO_PSOR_PTSO(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO_SHIFT)) & GPIO_PSOR_PTSO_MASK) 3417 /*! @} */ 3418 3419 /*! @name PCOR - Port Clear Output Register */ 3420 /*! @{ */ 3421 #define GPIO_PCOR_PTCO_MASK (0xFFFFFFFFU) 3422 #define GPIO_PCOR_PTCO_SHIFT (0U) 3423 /*! PTCO - Port Clear Output 3424 * 0b00000000000000000000000000000000..Corresponding bit in PDORn does not change. 3425 * 0b00000000000000000000000000000001..Corresponding bit in PDORn is cleared to logic 0. 3426 */ 3427 #define GPIO_PCOR_PTCO(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO_SHIFT)) & GPIO_PCOR_PTCO_MASK) 3428 /*! @} */ 3429 3430 /*! @name PTOR - Port Toggle Output Register */ 3431 /*! @{ */ 3432 #define GPIO_PTOR_PTTO_MASK (0xFFFFFFFFU) 3433 #define GPIO_PTOR_PTTO_SHIFT (0U) 3434 /*! PTTO - Port Toggle Output 3435 * 0b00000000000000000000000000000000..Corresponding bit in PDORn does not change. 3436 * 0b00000000000000000000000000000001..Corresponding bit in PDORn is set to the inverse of its existing logic state. 3437 */ 3438 #define GPIO_PTOR_PTTO(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO_SHIFT)) & GPIO_PTOR_PTTO_MASK) 3439 /*! @} */ 3440 3441 /*! @name PDIR - Port Data Input Register */ 3442 /*! @{ */ 3443 #define GPIO_PDIR_PDI_MASK (0xFFFFFFFFU) 3444 #define GPIO_PDIR_PDI_SHIFT (0U) 3445 /*! PDI - Port Data Input 3446 * 0b00000000000000000000000000000000..Pin logic level is logic 0, or is not configured for use by digital function. 3447 * 0b00000000000000000000000000000001..Pin logic level is logic 1. 3448 */ 3449 #define GPIO_PDIR_PDI(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI_SHIFT)) & GPIO_PDIR_PDI_MASK) 3450 /*! @} */ 3451 3452 /*! @name PDDR - Port Data Direction Register */ 3453 /*! @{ */ 3454 #define GPIO_PDDR_PDD_MASK (0xFFFFFFFFU) 3455 #define GPIO_PDDR_PDD_SHIFT (0U) 3456 /*! PDD - Port Data Direction 3457 * 0b00000000000000000000000000000000..Pin is configured as general-purpose input, for the GPIO function. 3458 * 0b00000000000000000000000000000001..Pin is configured as general-purpose output, for the GPIO function. 3459 */ 3460 #define GPIO_PDDR_PDD(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD_SHIFT)) & GPIO_PDDR_PDD_MASK) 3461 /*! @} */ 3462 3463 3464 /*! 3465 * @} 3466 */ /* end of group GPIO_Register_Masks */ 3467 3468 3469 /* GPIO - Peripheral instance base addresses */ 3470 /** Peripheral GPIOA base address */ 3471 #define GPIOA_BASE (0x400FF000u) 3472 /** Peripheral GPIOA base pointer */ 3473 #define GPIOA ((GPIO_Type *)GPIOA_BASE) 3474 /** Peripheral GPIOB base address */ 3475 #define GPIOB_BASE (0x400FF040u) 3476 /** Peripheral GPIOB base pointer */ 3477 #define GPIOB ((GPIO_Type *)GPIOB_BASE) 3478 /** Peripheral GPIOC base address */ 3479 #define GPIOC_BASE (0x400FF080u) 3480 /** Peripheral GPIOC base pointer */ 3481 #define GPIOC ((GPIO_Type *)GPIOC_BASE) 3482 /** Peripheral GPIOD base address */ 3483 #define GPIOD_BASE (0x400FF0C0u) 3484 /** Peripheral GPIOD base pointer */ 3485 #define GPIOD ((GPIO_Type *)GPIOD_BASE) 3486 /** Peripheral GPIOE base address */ 3487 #define GPIOE_BASE (0x400FF100u) 3488 /** Peripheral GPIOE base pointer */ 3489 #define GPIOE ((GPIO_Type *)GPIOE_BASE) 3490 /** Array initializer of GPIO peripheral base addresses */ 3491 #define GPIO_BASE_ADDRS { GPIOA_BASE, GPIOB_BASE, GPIOC_BASE, GPIOD_BASE, GPIOE_BASE } 3492 /** Array initializer of GPIO peripheral base pointers */ 3493 #define GPIO_BASE_PTRS { GPIOA, GPIOB, GPIOC, GPIOD, GPIOE } 3494 3495 /*! 3496 * @} 3497 */ /* end of group GPIO_Peripheral_Access_Layer */ 3498 3499 3500 /* ---------------------------------------------------------------------------- 3501 -- LPI2C Peripheral Access Layer 3502 ---------------------------------------------------------------------------- */ 3503 3504 /*! 3505 * @addtogroup LPI2C_Peripheral_Access_Layer LPI2C Peripheral Access Layer 3506 * @{ 3507 */ 3508 3509 /** LPI2C - Register Layout Typedef */ 3510 typedef struct { 3511 __I uint32_t VERID; /**< Version ID Register, offset: 0x0 */ 3512 __I uint32_t PARAM; /**< Parameter Register, offset: 0x4 */ 3513 uint8_t RESERVED_0[8]; 3514 __IO uint32_t MCR; /**< Master Control Register, offset: 0x10 */ 3515 __IO uint32_t MSR; /**< Master Status Register, offset: 0x14 */ 3516 __IO uint32_t MIER; /**< Master Interrupt Enable Register, offset: 0x18 */ 3517 __IO uint32_t MDER; /**< Master DMA Enable Register, offset: 0x1C */ 3518 __IO uint32_t MCFGR0; /**< Master Configuration Register 0, offset: 0x20 */ 3519 __IO uint32_t MCFGR1; /**< Master Configuration Register 1, offset: 0x24 */ 3520 __IO uint32_t MCFGR2; /**< Master Configuration Register 2, offset: 0x28 */ 3521 __IO uint32_t MCFGR3; /**< Master Configuration Register 3, offset: 0x2C */ 3522 uint8_t RESERVED_1[16]; 3523 __IO uint32_t MDMR; /**< Master Data Match Register, offset: 0x40 */ 3524 uint8_t RESERVED_2[4]; 3525 __IO uint32_t MCCR0; /**< Master Clock Configuration Register 0, offset: 0x48 */ 3526 uint8_t RESERVED_3[4]; 3527 __IO uint32_t MCCR1; /**< Master Clock Configuration Register 1, offset: 0x50 */ 3528 uint8_t RESERVED_4[4]; 3529 __IO uint32_t MFCR; /**< Master FIFO Control Register, offset: 0x58 */ 3530 __I uint32_t MFSR; /**< Master FIFO Status Register, offset: 0x5C */ 3531 __O uint32_t MTDR; /**< Master Transmit Data Register, offset: 0x60 */ 3532 uint8_t RESERVED_5[12]; 3533 __I uint32_t MRDR; /**< Master Receive Data Register, offset: 0x70 */ 3534 uint8_t RESERVED_6[156]; 3535 __IO uint32_t SCR; /**< Slave Control Register, offset: 0x110 */ 3536 __IO uint32_t SSR; /**< Slave Status Register, offset: 0x114 */ 3537 __IO uint32_t SIER; /**< Slave Interrupt Enable Register, offset: 0x118 */ 3538 __IO uint32_t SDER; /**< Slave DMA Enable Register, offset: 0x11C */ 3539 uint8_t RESERVED_7[4]; 3540 __IO uint32_t SCFGR1; /**< Slave Configuration Register 1, offset: 0x124 */ 3541 __IO uint32_t SCFGR2; /**< Slave Configuration Register 2, offset: 0x128 */ 3542 uint8_t RESERVED_8[20]; 3543 __IO uint32_t SAMR; /**< Slave Address Match Register, offset: 0x140 */ 3544 uint8_t RESERVED_9[12]; 3545 __I uint32_t SASR; /**< Slave Address Status Register, offset: 0x150 */ 3546 __IO uint32_t STAR; /**< Slave Transmit ACK Register, offset: 0x154 */ 3547 uint8_t RESERVED_10[8]; 3548 __O uint32_t STDR; /**< Slave Transmit Data Register, offset: 0x160 */ 3549 uint8_t RESERVED_11[12]; 3550 __I uint32_t SRDR; /**< Slave Receive Data Register, offset: 0x170 */ 3551 } LPI2C_Type; 3552 3553 /* ---------------------------------------------------------------------------- 3554 -- LPI2C Register Masks 3555 ---------------------------------------------------------------------------- */ 3556 3557 /*! 3558 * @addtogroup LPI2C_Register_Masks LPI2C Register Masks 3559 * @{ 3560 */ 3561 3562 /*! @name VERID - Version ID Register */ 3563 /*! @{ */ 3564 #define LPI2C_VERID_FEATURE_MASK (0xFFFFU) 3565 #define LPI2C_VERID_FEATURE_SHIFT (0U) 3566 /*! FEATURE - Feature Specification Number 3567 * 0b0000000000000010..Master only with standard feature set. 3568 * 0b0000000000000011..Master and slave with standard feature set. 3569 */ 3570 #define LPI2C_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_VERID_FEATURE_SHIFT)) & LPI2C_VERID_FEATURE_MASK) 3571 #define LPI2C_VERID_MINOR_MASK (0xFF0000U) 3572 #define LPI2C_VERID_MINOR_SHIFT (16U) 3573 /*! MINOR - Minor Version Number 3574 */ 3575 #define LPI2C_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_VERID_MINOR_SHIFT)) & LPI2C_VERID_MINOR_MASK) 3576 #define LPI2C_VERID_MAJOR_MASK (0xFF000000U) 3577 #define LPI2C_VERID_MAJOR_SHIFT (24U) 3578 /*! MAJOR - Major Version Number 3579 */ 3580 #define LPI2C_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_VERID_MAJOR_SHIFT)) & LPI2C_VERID_MAJOR_MASK) 3581 /*! @} */ 3582 3583 /*! @name PARAM - Parameter Register */ 3584 /*! @{ */ 3585 #define LPI2C_PARAM_MTXFIFO_MASK (0xFU) 3586 #define LPI2C_PARAM_MTXFIFO_SHIFT (0U) 3587 /*! MTXFIFO - Master Transmit FIFO Size 3588 */ 3589 #define LPI2C_PARAM_MTXFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_PARAM_MTXFIFO_SHIFT)) & LPI2C_PARAM_MTXFIFO_MASK) 3590 #define LPI2C_PARAM_MRXFIFO_MASK (0xF00U) 3591 #define LPI2C_PARAM_MRXFIFO_SHIFT (8U) 3592 /*! MRXFIFO - Master Receive FIFO Size 3593 */ 3594 #define LPI2C_PARAM_MRXFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_PARAM_MRXFIFO_SHIFT)) & LPI2C_PARAM_MRXFIFO_MASK) 3595 /*! @} */ 3596 3597 /*! @name MCR - Master Control Register */ 3598 /*! @{ */ 3599 #define LPI2C_MCR_MEN_MASK (0x1U) 3600 #define LPI2C_MCR_MEN_SHIFT (0U) 3601 /*! MEN - Master Enable 3602 * 0b0..Master logic is disabled. 3603 * 0b1..Master logic is enabled. 3604 */ 3605 #define LPI2C_MCR_MEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_MEN_SHIFT)) & LPI2C_MCR_MEN_MASK) 3606 #define LPI2C_MCR_RST_MASK (0x2U) 3607 #define LPI2C_MCR_RST_SHIFT (1U) 3608 /*! RST - Software Reset 3609 * 0b0..Master logic is not reset. 3610 * 0b1..Master logic is reset. 3611 */ 3612 #define LPI2C_MCR_RST(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_RST_SHIFT)) & LPI2C_MCR_RST_MASK) 3613 #define LPI2C_MCR_DOZEN_MASK (0x4U) 3614 #define LPI2C_MCR_DOZEN_SHIFT (2U) 3615 /*! DOZEN - Doze mode enable 3616 * 0b0..Master is enabled in Doze mode. 3617 * 0b1..Master is disabled in Doze mode. 3618 */ 3619 #define LPI2C_MCR_DOZEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_DOZEN_SHIFT)) & LPI2C_MCR_DOZEN_MASK) 3620 #define LPI2C_MCR_DBGEN_MASK (0x8U) 3621 #define LPI2C_MCR_DBGEN_SHIFT (3U) 3622 /*! DBGEN - Debug Enable 3623 * 0b0..Master is disabled in debug mode. 3624 * 0b1..Master is enabled in debug mode. 3625 */ 3626 #define LPI2C_MCR_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_DBGEN_SHIFT)) & LPI2C_MCR_DBGEN_MASK) 3627 #define LPI2C_MCR_RTF_MASK (0x100U) 3628 #define LPI2C_MCR_RTF_SHIFT (8U) 3629 /*! RTF - Reset Transmit FIFO 3630 * 0b0..No effect. 3631 * 0b1..Transmit FIFO is reset. 3632 */ 3633 #define LPI2C_MCR_RTF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_RTF_SHIFT)) & LPI2C_MCR_RTF_MASK) 3634 #define LPI2C_MCR_RRF_MASK (0x200U) 3635 #define LPI2C_MCR_RRF_SHIFT (9U) 3636 /*! RRF - Reset Receive FIFO 3637 * 0b0..No effect. 3638 * 0b1..Receive FIFO is reset. 3639 */ 3640 #define LPI2C_MCR_RRF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_RRF_SHIFT)) & LPI2C_MCR_RRF_MASK) 3641 /*! @} */ 3642 3643 /*! @name MSR - Master Status Register */ 3644 /*! @{ */ 3645 #define LPI2C_MSR_TDF_MASK (0x1U) 3646 #define LPI2C_MSR_TDF_SHIFT (0U) 3647 /*! TDF - Transmit Data Flag 3648 * 0b0..Transmit data not requested. 3649 * 0b1..Transmit data is requested. 3650 */ 3651 #define LPI2C_MSR_TDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_TDF_SHIFT)) & LPI2C_MSR_TDF_MASK) 3652 #define LPI2C_MSR_RDF_MASK (0x2U) 3653 #define LPI2C_MSR_RDF_SHIFT (1U) 3654 /*! RDF - Receive Data Flag 3655 * 0b0..Receive Data is not ready. 3656 * 0b1..Receive data is ready. 3657 */ 3658 #define LPI2C_MSR_RDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_RDF_SHIFT)) & LPI2C_MSR_RDF_MASK) 3659 #define LPI2C_MSR_EPF_MASK (0x100U) 3660 #define LPI2C_MSR_EPF_SHIFT (8U) 3661 /*! EPF - End Packet Flag 3662 * 0b0..Master has not generated a STOP or Repeated START condition. 3663 * 0b1..Master has generated a STOP or Repeated START condition. 3664 */ 3665 #define LPI2C_MSR_EPF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_EPF_SHIFT)) & LPI2C_MSR_EPF_MASK) 3666 #define LPI2C_MSR_SDF_MASK (0x200U) 3667 #define LPI2C_MSR_SDF_SHIFT (9U) 3668 /*! SDF - STOP Detect Flag 3669 * 0b0..Master has not generated a STOP condition. 3670 * 0b1..Master has generated a STOP condition. 3671 */ 3672 #define LPI2C_MSR_SDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_SDF_SHIFT)) & LPI2C_MSR_SDF_MASK) 3673 #define LPI2C_MSR_NDF_MASK (0x400U) 3674 #define LPI2C_MSR_NDF_SHIFT (10U) 3675 /*! NDF - NACK Detect Flag 3676 * 0b0..Unexpected NACK not detected. 3677 * 0b1..Unexpected NACK was detected. 3678 */ 3679 #define LPI2C_MSR_NDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_NDF_SHIFT)) & LPI2C_MSR_NDF_MASK) 3680 #define LPI2C_MSR_ALF_MASK (0x800U) 3681 #define LPI2C_MSR_ALF_SHIFT (11U) 3682 /*! ALF - Arbitration Lost Flag 3683 * 0b0..Master has not lost arbitration. 3684 * 0b1..Master has lost arbitration. 3685 */ 3686 #define LPI2C_MSR_ALF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_ALF_SHIFT)) & LPI2C_MSR_ALF_MASK) 3687 #define LPI2C_MSR_FEF_MASK (0x1000U) 3688 #define LPI2C_MSR_FEF_SHIFT (12U) 3689 /*! FEF - FIFO Error Flag 3690 * 0b0..No error. 3691 * 0b1..Master sending or receiving data without START condition. 3692 */ 3693 #define LPI2C_MSR_FEF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_FEF_SHIFT)) & LPI2C_MSR_FEF_MASK) 3694 #define LPI2C_MSR_PLTF_MASK (0x2000U) 3695 #define LPI2C_MSR_PLTF_SHIFT (13U) 3696 /*! PLTF - Pin Low Timeout Flag 3697 * 0b0..Pin low timeout has not occurred or is disabled. 3698 * 0b1..Pin low timeout has occurred. 3699 */ 3700 #define LPI2C_MSR_PLTF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_PLTF_SHIFT)) & LPI2C_MSR_PLTF_MASK) 3701 #define LPI2C_MSR_DMF_MASK (0x4000U) 3702 #define LPI2C_MSR_DMF_SHIFT (14U) 3703 /*! DMF - Data Match Flag 3704 * 0b0..Have not received matching data. 3705 * 0b1..Have received matching data. 3706 */ 3707 #define LPI2C_MSR_DMF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_DMF_SHIFT)) & LPI2C_MSR_DMF_MASK) 3708 #define LPI2C_MSR_MBF_MASK (0x1000000U) 3709 #define LPI2C_MSR_MBF_SHIFT (24U) 3710 /*! MBF - Master Busy Flag 3711 * 0b0..I2C Master is idle. 3712 * 0b1..I2C Master is busy. 3713 */ 3714 #define LPI2C_MSR_MBF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_MBF_SHIFT)) & LPI2C_MSR_MBF_MASK) 3715 #define LPI2C_MSR_BBF_MASK (0x2000000U) 3716 #define LPI2C_MSR_BBF_SHIFT (25U) 3717 /*! BBF - Bus Busy Flag 3718 * 0b0..I2C Bus is idle. 3719 * 0b1..I2C Bus is busy. 3720 */ 3721 #define LPI2C_MSR_BBF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_BBF_SHIFT)) & LPI2C_MSR_BBF_MASK) 3722 /*! @} */ 3723 3724 /*! @name MIER - Master Interrupt Enable Register */ 3725 /*! @{ */ 3726 #define LPI2C_MIER_TDIE_MASK (0x1U) 3727 #define LPI2C_MIER_TDIE_SHIFT (0U) 3728 /*! TDIE - Transmit Data Interrupt Enable 3729 * 0b0..Interrupt disabled. 3730 * 0b1..Interrupt enabled 3731 */ 3732 #define LPI2C_MIER_TDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_TDIE_SHIFT)) & LPI2C_MIER_TDIE_MASK) 3733 #define LPI2C_MIER_RDIE_MASK (0x2U) 3734 #define LPI2C_MIER_RDIE_SHIFT (1U) 3735 /*! RDIE - Receive Data Interrupt Enable 3736 * 0b0..Interrupt disabled. 3737 * 0b1..Interrupt enabled. 3738 */ 3739 #define LPI2C_MIER_RDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_RDIE_SHIFT)) & LPI2C_MIER_RDIE_MASK) 3740 #define LPI2C_MIER_EPIE_MASK (0x100U) 3741 #define LPI2C_MIER_EPIE_SHIFT (8U) 3742 /*! EPIE - End Packet Interrupt Enable 3743 * 0b0..Interrupt disabled. 3744 * 0b1..Interrupt enabled. 3745 */ 3746 #define LPI2C_MIER_EPIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_EPIE_SHIFT)) & LPI2C_MIER_EPIE_MASK) 3747 #define LPI2C_MIER_SDIE_MASK (0x200U) 3748 #define LPI2C_MIER_SDIE_SHIFT (9U) 3749 /*! SDIE - STOP Detect Interrupt Enable 3750 * 0b0..Interrupt disabled. 3751 * 0b1..Interrupt enabled. 3752 */ 3753 #define LPI2C_MIER_SDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_SDIE_SHIFT)) & LPI2C_MIER_SDIE_MASK) 3754 #define LPI2C_MIER_NDIE_MASK (0x400U) 3755 #define LPI2C_MIER_NDIE_SHIFT (10U) 3756 /*! NDIE - NACK Detect Interrupt Enable 3757 * 0b0..Interrupt disabled. 3758 * 0b1..Interrupt enabled. 3759 */ 3760 #define LPI2C_MIER_NDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_NDIE_SHIFT)) & LPI2C_MIER_NDIE_MASK) 3761 #define LPI2C_MIER_ALIE_MASK (0x800U) 3762 #define LPI2C_MIER_ALIE_SHIFT (11U) 3763 /*! ALIE - Arbitration Lost Interrupt Enable 3764 * 0b0..Interrupt disabled. 3765 * 0b1..Interrupt enabled. 3766 */ 3767 #define LPI2C_MIER_ALIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_ALIE_SHIFT)) & LPI2C_MIER_ALIE_MASK) 3768 #define LPI2C_MIER_FEIE_MASK (0x1000U) 3769 #define LPI2C_MIER_FEIE_SHIFT (12U) 3770 /*! FEIE - FIFO Error Interrupt Enable 3771 * 0b0..Interrupt disabled. 3772 * 0b1..Interrupt enabled. 3773 */ 3774 #define LPI2C_MIER_FEIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_FEIE_SHIFT)) & LPI2C_MIER_FEIE_MASK) 3775 #define LPI2C_MIER_PLTIE_MASK (0x2000U) 3776 #define LPI2C_MIER_PLTIE_SHIFT (13U) 3777 /*! PLTIE - Pin Low Timeout Interrupt Enable 3778 * 0b0..Interrupt disabled. 3779 * 0b1..Interrupt enabled. 3780 */ 3781 #define LPI2C_MIER_PLTIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_PLTIE_SHIFT)) & LPI2C_MIER_PLTIE_MASK) 3782 #define LPI2C_MIER_DMIE_MASK (0x4000U) 3783 #define LPI2C_MIER_DMIE_SHIFT (14U) 3784 /*! DMIE - Data Match Interrupt Enable 3785 * 0b0..Interrupt disabled. 3786 * 0b1..Interrupt enabled. 3787 */ 3788 #define LPI2C_MIER_DMIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_DMIE_SHIFT)) & LPI2C_MIER_DMIE_MASK) 3789 /*! @} */ 3790 3791 /*! @name MDER - Master DMA Enable Register */ 3792 /*! @{ */ 3793 #define LPI2C_MDER_TDDE_MASK (0x1U) 3794 #define LPI2C_MDER_TDDE_SHIFT (0U) 3795 /*! TDDE - Transmit Data DMA Enable 3796 * 0b0..DMA request disabled. 3797 * 0b1..DMA request enabled 3798 */ 3799 #define LPI2C_MDER_TDDE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MDER_TDDE_SHIFT)) & LPI2C_MDER_TDDE_MASK) 3800 #define LPI2C_MDER_RDDE_MASK (0x2U) 3801 #define LPI2C_MDER_RDDE_SHIFT (1U) 3802 /*! RDDE - Receive Data DMA Enable 3803 * 0b0..DMA request disabled. 3804 * 0b1..DMA request enabled. 3805 */ 3806 #define LPI2C_MDER_RDDE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MDER_RDDE_SHIFT)) & LPI2C_MDER_RDDE_MASK) 3807 /*! @} */ 3808 3809 /*! @name MCFGR0 - Master Configuration Register 0 */ 3810 /*! @{ */ 3811 #define LPI2C_MCFGR0_HREN_MASK (0x1U) 3812 #define LPI2C_MCFGR0_HREN_SHIFT (0U) 3813 /*! HREN - Host Request Enable 3814 * 0b0..Host request input is disabled. 3815 * 0b1..Host request input is enabled. 3816 */ 3817 #define LPI2C_MCFGR0_HREN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_HREN_SHIFT)) & LPI2C_MCFGR0_HREN_MASK) 3818 #define LPI2C_MCFGR0_HRPOL_MASK (0x2U) 3819 #define LPI2C_MCFGR0_HRPOL_SHIFT (1U) 3820 /*! HRPOL - Host Request Polarity 3821 * 0b0..Active low. 3822 * 0b1..Active high. 3823 */ 3824 #define LPI2C_MCFGR0_HRPOL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_HRPOL_SHIFT)) & LPI2C_MCFGR0_HRPOL_MASK) 3825 #define LPI2C_MCFGR0_HRSEL_MASK (0x4U) 3826 #define LPI2C_MCFGR0_HRSEL_SHIFT (2U) 3827 /*! HRSEL - Host Request Select 3828 * 0b0..Host request input is pin LPI2C_HREQ. 3829 * 0b1..Host request input is input trigger. 3830 */ 3831 #define LPI2C_MCFGR0_HRSEL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_HRSEL_SHIFT)) & LPI2C_MCFGR0_HRSEL_MASK) 3832 #define LPI2C_MCFGR0_CIRFIFO_MASK (0x100U) 3833 #define LPI2C_MCFGR0_CIRFIFO_SHIFT (8U) 3834 /*! CIRFIFO - Circular FIFO Enable 3835 * 0b0..Circular FIFO is disabled. 3836 * 0b1..Circular FIFO is enabled. 3837 */ 3838 #define LPI2C_MCFGR0_CIRFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_CIRFIFO_SHIFT)) & LPI2C_MCFGR0_CIRFIFO_MASK) 3839 #define LPI2C_MCFGR0_RDMO_MASK (0x200U) 3840 #define LPI2C_MCFGR0_RDMO_SHIFT (9U) 3841 /*! RDMO - Receive Data Match Only 3842 * 0b0..Received data is stored in the receive FIFO as normal. 3843 * 0b1..Received data is discarded unless the RMF is set. 3844 */ 3845 #define LPI2C_MCFGR0_RDMO(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_RDMO_SHIFT)) & LPI2C_MCFGR0_RDMO_MASK) 3846 /*! @} */ 3847 3848 /*! @name MCFGR1 - Master Configuration Register 1 */ 3849 /*! @{ */ 3850 #define LPI2C_MCFGR1_PRESCALE_MASK (0x7U) 3851 #define LPI2C_MCFGR1_PRESCALE_SHIFT (0U) 3852 /*! PRESCALE - Prescaler 3853 * 0b000..Divide by 1. 3854 * 0b001..Divide by 2. 3855 * 0b010..Divide by 4. 3856 * 0b011..Divide by 8. 3857 * 0b100..Divide by 16. 3858 * 0b101..Divide by 32. 3859 * 0b110..Divide by 64. 3860 * 0b111..Divide by 128. 3861 */ 3862 #define LPI2C_MCFGR1_PRESCALE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_PRESCALE_SHIFT)) & LPI2C_MCFGR1_PRESCALE_MASK) 3863 #define LPI2C_MCFGR1_AUTOSTOP_MASK (0x100U) 3864 #define LPI2C_MCFGR1_AUTOSTOP_SHIFT (8U) 3865 /*! AUTOSTOP - Automatic STOP Generation 3866 * 0b0..No effect. 3867 * 0b1..STOP condition is automatically generated whenever the transmit FIFO is empty and LPI2C master is busy. 3868 */ 3869 #define LPI2C_MCFGR1_AUTOSTOP(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_AUTOSTOP_SHIFT)) & LPI2C_MCFGR1_AUTOSTOP_MASK) 3870 #define LPI2C_MCFGR1_IGNACK_MASK (0x200U) 3871 #define LPI2C_MCFGR1_IGNACK_SHIFT (9U) 3872 /*! IGNACK 3873 * 0b0..LPI2C Master will receive ACK and NACK normally. 3874 * 0b1..LPI2C Master will treat a received NACK as if it was an ACK. 3875 */ 3876 #define LPI2C_MCFGR1_IGNACK(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_IGNACK_SHIFT)) & LPI2C_MCFGR1_IGNACK_MASK) 3877 #define LPI2C_MCFGR1_TIMECFG_MASK (0x400U) 3878 #define LPI2C_MCFGR1_TIMECFG_SHIFT (10U) 3879 /*! TIMECFG - Timeout Configuration 3880 * 0b0..Pin Low Timeout Flag will set if SCL is low for longer than the configured timeout. 3881 * 0b1..Pin Low Timeout Flag will set if either SCL or SDA is low for longer than the configured timeout. 3882 */ 3883 #define LPI2C_MCFGR1_TIMECFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_TIMECFG_SHIFT)) & LPI2C_MCFGR1_TIMECFG_MASK) 3884 #define LPI2C_MCFGR1_MATCFG_MASK (0x70000U) 3885 #define LPI2C_MCFGR1_MATCFG_SHIFT (16U) 3886 /*! MATCFG - Match Configuration 3887 * 0b000..Match disabled. 3888 * 0b001..Reserved. 3889 * 0b010..Match enabled (1st data word equals MATCH0 OR MATCH1). 3890 * 0b011..Match enabled (any data word equals MATCH0 OR MATCH1). 3891 * 0b100..Match enabled (1st data word equals MATCH0 AND 2nd data word equals MATCH1). 3892 * 0b101..Match enabled (any data word equals MATCH0 AND next data word equals MATCH1). 3893 * 0b110..Match enabled (1st data word AND MATCH1 equals MATCH0 AND MATCH1). 3894 * 0b111..Match enabled (any data word AND MATCH1 equals MATCH0 AND MATCH1). 3895 */ 3896 #define LPI2C_MCFGR1_MATCFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_MATCFG_SHIFT)) & LPI2C_MCFGR1_MATCFG_MASK) 3897 #define LPI2C_MCFGR1_PINCFG_MASK (0x7000000U) 3898 #define LPI2C_MCFGR1_PINCFG_SHIFT (24U) 3899 /*! PINCFG - Pin Configuration 3900 * 0b000..LPI2C configured for 2-pin open drain mode. 3901 * 0b001..LPI2C configured for 2-pin output only mode (ultra-fast mode). 3902 * 0b010..LPI2C configured for 2-pin push-pull mode. 3903 * 0b011..LPI2C configured for 4-pin push-pull mode. 3904 * 0b100..LPI2C configured for 2-pin open drain mode with separate LPI2C slave. 3905 * 0b101..LPI2C configured for 2-pin output only mode (ultra-fast mode) with separate LPI2C slave. 3906 * 0b110..LPI2C configured for 2-pin push-pull mode with separate LPI2C slave. 3907 * 0b111..LPI2C configured for 4-pin push-pull mode (inverted outputs). 3908 */ 3909 #define LPI2C_MCFGR1_PINCFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_PINCFG_SHIFT)) & LPI2C_MCFGR1_PINCFG_MASK) 3910 /*! @} */ 3911 3912 /*! @name MCFGR2 - Master Configuration Register 2 */ 3913 /*! @{ */ 3914 #define LPI2C_MCFGR2_BUSIDLE_MASK (0xFFFU) 3915 #define LPI2C_MCFGR2_BUSIDLE_SHIFT (0U) 3916 /*! BUSIDLE - Bus Idle Timeout 3917 */ 3918 #define LPI2C_MCFGR2_BUSIDLE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR2_BUSIDLE_SHIFT)) & LPI2C_MCFGR2_BUSIDLE_MASK) 3919 #define LPI2C_MCFGR2_FILTSCL_MASK (0xF0000U) 3920 #define LPI2C_MCFGR2_FILTSCL_SHIFT (16U) 3921 /*! FILTSCL - Glitch Filter SCL 3922 */ 3923 #define LPI2C_MCFGR2_FILTSCL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR2_FILTSCL_SHIFT)) & LPI2C_MCFGR2_FILTSCL_MASK) 3924 #define LPI2C_MCFGR2_FILTSDA_MASK (0xF000000U) 3925 #define LPI2C_MCFGR2_FILTSDA_SHIFT (24U) 3926 /*! FILTSDA - Glitch Filter SDA 3927 */ 3928 #define LPI2C_MCFGR2_FILTSDA(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR2_FILTSDA_SHIFT)) & LPI2C_MCFGR2_FILTSDA_MASK) 3929 /*! @} */ 3930 3931 /*! @name MCFGR3 - Master Configuration Register 3 */ 3932 /*! @{ */ 3933 #define LPI2C_MCFGR3_PINLOW_MASK (0xFFF00U) 3934 #define LPI2C_MCFGR3_PINLOW_SHIFT (8U) 3935 /*! PINLOW - Pin Low Timeout 3936 */ 3937 #define LPI2C_MCFGR3_PINLOW(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR3_PINLOW_SHIFT)) & LPI2C_MCFGR3_PINLOW_MASK) 3938 /*! @} */ 3939 3940 /*! @name MDMR - Master Data Match Register */ 3941 /*! @{ */ 3942 #define LPI2C_MDMR_MATCH0_MASK (0xFFU) 3943 #define LPI2C_MDMR_MATCH0_SHIFT (0U) 3944 /*! MATCH0 - Match 0 Value 3945 */ 3946 #define LPI2C_MDMR_MATCH0(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MDMR_MATCH0_SHIFT)) & LPI2C_MDMR_MATCH0_MASK) 3947 #define LPI2C_MDMR_MATCH1_MASK (0xFF0000U) 3948 #define LPI2C_MDMR_MATCH1_SHIFT (16U) 3949 /*! MATCH1 - Match 1 Value 3950 */ 3951 #define LPI2C_MDMR_MATCH1(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MDMR_MATCH1_SHIFT)) & LPI2C_MDMR_MATCH1_MASK) 3952 /*! @} */ 3953 3954 /*! @name MCCR0 - Master Clock Configuration Register 0 */ 3955 /*! @{ */ 3956 #define LPI2C_MCCR0_CLKLO_MASK (0x3FU) 3957 #define LPI2C_MCCR0_CLKLO_SHIFT (0U) 3958 /*! CLKLO - Clock Low Period 3959 */ 3960 #define LPI2C_MCCR0_CLKLO(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR0_CLKLO_SHIFT)) & LPI2C_MCCR0_CLKLO_MASK) 3961 #define LPI2C_MCCR0_CLKHI_MASK (0x3F00U) 3962 #define LPI2C_MCCR0_CLKHI_SHIFT (8U) 3963 /*! CLKHI - Clock High Period 3964 */ 3965 #define LPI2C_MCCR0_CLKHI(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR0_CLKHI_SHIFT)) & LPI2C_MCCR0_CLKHI_MASK) 3966 #define LPI2C_MCCR0_SETHOLD_MASK (0x3F0000U) 3967 #define LPI2C_MCCR0_SETHOLD_SHIFT (16U) 3968 /*! SETHOLD - Setup Hold Delay 3969 */ 3970 #define LPI2C_MCCR0_SETHOLD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR0_SETHOLD_SHIFT)) & LPI2C_MCCR0_SETHOLD_MASK) 3971 #define LPI2C_MCCR0_DATAVD_MASK (0x3F000000U) 3972 #define LPI2C_MCCR0_DATAVD_SHIFT (24U) 3973 /*! DATAVD - Data Valid Delay 3974 */ 3975 #define LPI2C_MCCR0_DATAVD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR0_DATAVD_SHIFT)) & LPI2C_MCCR0_DATAVD_MASK) 3976 /*! @} */ 3977 3978 /*! @name MCCR1 - Master Clock Configuration Register 1 */ 3979 /*! @{ */ 3980 #define LPI2C_MCCR1_CLKLO_MASK (0x3FU) 3981 #define LPI2C_MCCR1_CLKLO_SHIFT (0U) 3982 /*! CLKLO - Clock Low Period 3983 */ 3984 #define LPI2C_MCCR1_CLKLO(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR1_CLKLO_SHIFT)) & LPI2C_MCCR1_CLKLO_MASK) 3985 #define LPI2C_MCCR1_CLKHI_MASK (0x3F00U) 3986 #define LPI2C_MCCR1_CLKHI_SHIFT (8U) 3987 /*! CLKHI - Clock High Period 3988 */ 3989 #define LPI2C_MCCR1_CLKHI(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR1_CLKHI_SHIFT)) & LPI2C_MCCR1_CLKHI_MASK) 3990 #define LPI2C_MCCR1_SETHOLD_MASK (0x3F0000U) 3991 #define LPI2C_MCCR1_SETHOLD_SHIFT (16U) 3992 /*! SETHOLD - Setup Hold Delay 3993 */ 3994 #define LPI2C_MCCR1_SETHOLD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR1_SETHOLD_SHIFT)) & LPI2C_MCCR1_SETHOLD_MASK) 3995 #define LPI2C_MCCR1_DATAVD_MASK (0x3F000000U) 3996 #define LPI2C_MCCR1_DATAVD_SHIFT (24U) 3997 /*! DATAVD - Data Valid Delay 3998 */ 3999 #define LPI2C_MCCR1_DATAVD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR1_DATAVD_SHIFT)) & LPI2C_MCCR1_DATAVD_MASK) 4000 /*! @} */ 4001 4002 /*! @name MFCR - Master FIFO Control Register */ 4003 /*! @{ */ 4004 #define LPI2C_MFCR_TXWATER_MASK (0xFFU) 4005 #define LPI2C_MFCR_TXWATER_SHIFT (0U) 4006 /*! TXWATER - Transmit FIFO Watermark 4007 */ 4008 #define LPI2C_MFCR_TXWATER(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MFCR_TXWATER_SHIFT)) & LPI2C_MFCR_TXWATER_MASK) 4009 #define LPI2C_MFCR_RXWATER_MASK (0xFF0000U) 4010 #define LPI2C_MFCR_RXWATER_SHIFT (16U) 4011 /*! RXWATER - Receive FIFO Watermark 4012 */ 4013 #define LPI2C_MFCR_RXWATER(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MFCR_RXWATER_SHIFT)) & LPI2C_MFCR_RXWATER_MASK) 4014 /*! @} */ 4015 4016 /*! @name MFSR - Master FIFO Status Register */ 4017 /*! @{ */ 4018 #define LPI2C_MFSR_TXCOUNT_MASK (0xFFU) 4019 #define LPI2C_MFSR_TXCOUNT_SHIFT (0U) 4020 /*! TXCOUNT - Transmit FIFO Count 4021 */ 4022 #define LPI2C_MFSR_TXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MFSR_TXCOUNT_SHIFT)) & LPI2C_MFSR_TXCOUNT_MASK) 4023 #define LPI2C_MFSR_RXCOUNT_MASK (0xFF0000U) 4024 #define LPI2C_MFSR_RXCOUNT_SHIFT (16U) 4025 /*! RXCOUNT - Receive FIFO Count 4026 */ 4027 #define LPI2C_MFSR_RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MFSR_RXCOUNT_SHIFT)) & LPI2C_MFSR_RXCOUNT_MASK) 4028 /*! @} */ 4029 4030 /*! @name MTDR - Master Transmit Data Register */ 4031 /*! @{ */ 4032 #define LPI2C_MTDR_DATA_MASK (0xFFU) 4033 #define LPI2C_MTDR_DATA_SHIFT (0U) 4034 /*! DATA - Transmit Data 4035 */ 4036 #define LPI2C_MTDR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MTDR_DATA_SHIFT)) & LPI2C_MTDR_DATA_MASK) 4037 #define LPI2C_MTDR_CMD_MASK (0x700U) 4038 #define LPI2C_MTDR_CMD_SHIFT (8U) 4039 /*! CMD - Command Data 4040 * 0b000..Transmit DATA[7:0]. 4041 * 0b001..Receive (DATA[7:0] + 1) bytes. 4042 * 0b010..Generate STOP condition. 4043 * 0b011..Receive and discard (DATA[7:0] + 1) bytes. 4044 * 0b100..Generate (repeated) START and transmit address in DATA[7:0]. 4045 * 0b101..Generate (repeated) START and transmit address in DATA[7:0]. This transfer expects a NACK to be returned. 4046 * 0b110..Generate (repeated) START and transmit address in DATA[7:0] using high speed mode. 4047 * 0b111..Generate (repeated) START and transmit address in DATA[7:0] using high speed mode. This transfer expects a NACK to be returned. 4048 */ 4049 #define LPI2C_MTDR_CMD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MTDR_CMD_SHIFT)) & LPI2C_MTDR_CMD_MASK) 4050 /*! @} */ 4051 4052 /*! @name MRDR - Master Receive Data Register */ 4053 /*! @{ */ 4054 #define LPI2C_MRDR_DATA_MASK (0xFFU) 4055 #define LPI2C_MRDR_DATA_SHIFT (0U) 4056 /*! DATA - Receive Data 4057 */ 4058 #define LPI2C_MRDR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MRDR_DATA_SHIFT)) & LPI2C_MRDR_DATA_MASK) 4059 #define LPI2C_MRDR_RXEMPTY_MASK (0x4000U) 4060 #define LPI2C_MRDR_RXEMPTY_SHIFT (14U) 4061 /*! RXEMPTY - RX Empty 4062 * 0b0..Receive FIFO is not empty. 4063 * 0b1..Receive FIFO is empty. 4064 */ 4065 #define LPI2C_MRDR_RXEMPTY(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MRDR_RXEMPTY_SHIFT)) & LPI2C_MRDR_RXEMPTY_MASK) 4066 /*! @} */ 4067 4068 /*! @name SCR - Slave Control Register */ 4069 /*! @{ */ 4070 #define LPI2C_SCR_SEN_MASK (0x1U) 4071 #define LPI2C_SCR_SEN_SHIFT (0U) 4072 /*! SEN - Slave Enable 4073 * 0b0..Slave mode is disabled. 4074 * 0b1..Slave mode is enabled. 4075 */ 4076 #define LPI2C_SCR_SEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_SEN_SHIFT)) & LPI2C_SCR_SEN_MASK) 4077 #define LPI2C_SCR_RST_MASK (0x2U) 4078 #define LPI2C_SCR_RST_SHIFT (1U) 4079 /*! RST - Software Reset 4080 * 0b0..Slave logic is not reset. 4081 * 0b1..Slave logic is reset. 4082 */ 4083 #define LPI2C_SCR_RST(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_RST_SHIFT)) & LPI2C_SCR_RST_MASK) 4084 #define LPI2C_SCR_FILTEN_MASK (0x10U) 4085 #define LPI2C_SCR_FILTEN_SHIFT (4U) 4086 /*! FILTEN - Filter Enable 4087 * 0b0..Disable digital filter and output delay counter for slave mode. 4088 * 0b1..Enable digital filter and output delay counter for slave mode. 4089 */ 4090 #define LPI2C_SCR_FILTEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_FILTEN_SHIFT)) & LPI2C_SCR_FILTEN_MASK) 4091 #define LPI2C_SCR_FILTDZ_MASK (0x20U) 4092 #define LPI2C_SCR_FILTDZ_SHIFT (5U) 4093 /*! FILTDZ - Filter Doze Enable 4094 * 0b0..Filter remains enabled in Doze mode. 4095 * 0b1..Filter is disabled in Doze mode. 4096 */ 4097 #define LPI2C_SCR_FILTDZ(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_FILTDZ_SHIFT)) & LPI2C_SCR_FILTDZ_MASK) 4098 #define LPI2C_SCR_RTF_MASK (0x100U) 4099 #define LPI2C_SCR_RTF_SHIFT (8U) 4100 /*! RTF - Reset Transmit FIFO 4101 * 0b0..No effect. 4102 * 0b1..Transmit Data Register is now empty. 4103 */ 4104 #define LPI2C_SCR_RTF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_RTF_SHIFT)) & LPI2C_SCR_RTF_MASK) 4105 #define LPI2C_SCR_RRF_MASK (0x200U) 4106 #define LPI2C_SCR_RRF_SHIFT (9U) 4107 /*! RRF - Reset Receive FIFO 4108 * 0b0..No effect. 4109 * 0b1..Receive Data Register is now empty. 4110 */ 4111 #define LPI2C_SCR_RRF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_RRF_SHIFT)) & LPI2C_SCR_RRF_MASK) 4112 /*! @} */ 4113 4114 /*! @name SSR - Slave Status Register */ 4115 /*! @{ */ 4116 #define LPI2C_SSR_TDF_MASK (0x1U) 4117 #define LPI2C_SSR_TDF_SHIFT (0U) 4118 /*! TDF - Transmit Data Flag 4119 * 0b0..Transmit data not requested. 4120 * 0b1..Transmit data is requested. 4121 */ 4122 #define LPI2C_SSR_TDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_TDF_SHIFT)) & LPI2C_SSR_TDF_MASK) 4123 #define LPI2C_SSR_RDF_MASK (0x2U) 4124 #define LPI2C_SSR_RDF_SHIFT (1U) 4125 /*! RDF - Receive Data Flag 4126 * 0b0..Receive Data is not ready. 4127 * 0b1..Receive data is ready. 4128 */ 4129 #define LPI2C_SSR_RDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_RDF_SHIFT)) & LPI2C_SSR_RDF_MASK) 4130 #define LPI2C_SSR_AVF_MASK (0x4U) 4131 #define LPI2C_SSR_AVF_SHIFT (2U) 4132 /*! AVF - Address Valid Flag 4133 * 0b0..Address Status Register is not valid. 4134 * 0b1..Address Status Register is valid. 4135 */ 4136 #define LPI2C_SSR_AVF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_AVF_SHIFT)) & LPI2C_SSR_AVF_MASK) 4137 #define LPI2C_SSR_TAF_MASK (0x8U) 4138 #define LPI2C_SSR_TAF_SHIFT (3U) 4139 /*! TAF - Transmit ACK Flag 4140 * 0b0..Transmit ACK/NACK is not required. 4141 * 0b1..Transmit ACK/NACK is required. 4142 */ 4143 #define LPI2C_SSR_TAF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_TAF_SHIFT)) & LPI2C_SSR_TAF_MASK) 4144 #define LPI2C_SSR_RSF_MASK (0x100U) 4145 #define LPI2C_SSR_RSF_SHIFT (8U) 4146 /*! RSF - Repeated Start Flag 4147 * 0b0..Slave has not detected a Repeated START condition. 4148 * 0b1..Slave has detected a Repeated START condition. 4149 */ 4150 #define LPI2C_SSR_RSF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_RSF_SHIFT)) & LPI2C_SSR_RSF_MASK) 4151 #define LPI2C_SSR_SDF_MASK (0x200U) 4152 #define LPI2C_SSR_SDF_SHIFT (9U) 4153 /*! SDF - STOP Detect Flag 4154 * 0b0..Slave has not detected a STOP condition. 4155 * 0b1..Slave has detected a STOP condition. 4156 */ 4157 #define LPI2C_SSR_SDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_SDF_SHIFT)) & LPI2C_SSR_SDF_MASK) 4158 #define LPI2C_SSR_BEF_MASK (0x400U) 4159 #define LPI2C_SSR_BEF_SHIFT (10U) 4160 /*! BEF - Bit Error Flag 4161 * 0b0..Slave has not detected a bit error. 4162 * 0b1..Slave has detected a bit error. 4163 */ 4164 #define LPI2C_SSR_BEF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_BEF_SHIFT)) & LPI2C_SSR_BEF_MASK) 4165 #define LPI2C_SSR_FEF_MASK (0x800U) 4166 #define LPI2C_SSR_FEF_SHIFT (11U) 4167 /*! FEF - FIFO Error Flag 4168 * 0b0..FIFO underflow or overflow not detected. 4169 * 0b1..FIFO underflow or overflow detected. 4170 */ 4171 #define LPI2C_SSR_FEF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_FEF_SHIFT)) & LPI2C_SSR_FEF_MASK) 4172 #define LPI2C_SSR_AM0F_MASK (0x1000U) 4173 #define LPI2C_SSR_AM0F_SHIFT (12U) 4174 /*! AM0F - Address Match 0 Flag 4175 * 0b0..Have not received ADDR0 matching address. 4176 * 0b1..Have received ADDR0 matching address. 4177 */ 4178 #define LPI2C_SSR_AM0F(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_AM0F_SHIFT)) & LPI2C_SSR_AM0F_MASK) 4179 #define LPI2C_SSR_AM1F_MASK (0x2000U) 4180 #define LPI2C_SSR_AM1F_SHIFT (13U) 4181 /*! AM1F - Address Match 1 Flag 4182 * 0b0..Have not received ADDR1 or ADDR0/ADDR1 range matching address. 4183 * 0b1..Have received ADDR1 or ADDR0/ADDR1 range matching address. 4184 */ 4185 #define LPI2C_SSR_AM1F(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_AM1F_SHIFT)) & LPI2C_SSR_AM1F_MASK) 4186 #define LPI2C_SSR_GCF_MASK (0x4000U) 4187 #define LPI2C_SSR_GCF_SHIFT (14U) 4188 /*! GCF - General Call Flag 4189 * 0b0..Slave has not detected the General Call Address or General Call Address disabled. 4190 * 0b1..Slave has detected the General Call Address. 4191 */ 4192 #define LPI2C_SSR_GCF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_GCF_SHIFT)) & LPI2C_SSR_GCF_MASK) 4193 #define LPI2C_SSR_SARF_MASK (0x8000U) 4194 #define LPI2C_SSR_SARF_SHIFT (15U) 4195 /*! SARF - SMBus Alert Response Flag 4196 * 0b0..SMBus Alert Response disabled or not detected. 4197 * 0b1..SMBus Alert Response enabled and detected. 4198 */ 4199 #define LPI2C_SSR_SARF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_SARF_SHIFT)) & LPI2C_SSR_SARF_MASK) 4200 #define LPI2C_SSR_SBF_MASK (0x1000000U) 4201 #define LPI2C_SSR_SBF_SHIFT (24U) 4202 /*! SBF - Slave Busy Flag 4203 * 0b0..I2C Slave is idle. 4204 * 0b1..I2C Slave is busy. 4205 */ 4206 #define LPI2C_SSR_SBF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_SBF_SHIFT)) & LPI2C_SSR_SBF_MASK) 4207 #define LPI2C_SSR_BBF_MASK (0x2000000U) 4208 #define LPI2C_SSR_BBF_SHIFT (25U) 4209 /*! BBF - Bus Busy Flag 4210 * 0b0..I2C Bus is idle. 4211 * 0b1..I2C Bus is busy. 4212 */ 4213 #define LPI2C_SSR_BBF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_BBF_SHIFT)) & LPI2C_SSR_BBF_MASK) 4214 /*! @} */ 4215 4216 /*! @name SIER - Slave Interrupt Enable Register */ 4217 /*! @{ */ 4218 #define LPI2C_SIER_TDIE_MASK (0x1U) 4219 #define LPI2C_SIER_TDIE_SHIFT (0U) 4220 /*! TDIE - Transmit Data Interrupt Enable 4221 * 0b0..Interrupt disabled. 4222 * 0b1..Interrupt enabled 4223 */ 4224 #define LPI2C_SIER_TDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_TDIE_SHIFT)) & LPI2C_SIER_TDIE_MASK) 4225 #define LPI2C_SIER_RDIE_MASK (0x2U) 4226 #define LPI2C_SIER_RDIE_SHIFT (1U) 4227 /*! RDIE - Receive Data Interrupt Enable 4228 * 0b0..Interrupt disabled. 4229 * 0b1..Interrupt enabled. 4230 */ 4231 #define LPI2C_SIER_RDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_RDIE_SHIFT)) & LPI2C_SIER_RDIE_MASK) 4232 #define LPI2C_SIER_AVIE_MASK (0x4U) 4233 #define LPI2C_SIER_AVIE_SHIFT (2U) 4234 /*! AVIE - Address Valid Interrupt Enable 4235 * 0b0..Interrupt disabled. 4236 * 0b1..Interrupt enabled. 4237 */ 4238 #define LPI2C_SIER_AVIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_AVIE_SHIFT)) & LPI2C_SIER_AVIE_MASK) 4239 #define LPI2C_SIER_TAIE_MASK (0x8U) 4240 #define LPI2C_SIER_TAIE_SHIFT (3U) 4241 /*! TAIE - Transmit ACK Interrupt Enable 4242 * 0b0..Interrupt disabled. 4243 * 0b1..Interrupt enabled. 4244 */ 4245 #define LPI2C_SIER_TAIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_TAIE_SHIFT)) & LPI2C_SIER_TAIE_MASK) 4246 #define LPI2C_SIER_RSIE_MASK (0x100U) 4247 #define LPI2C_SIER_RSIE_SHIFT (8U) 4248 /*! RSIE - Repeated Start Interrupt Enable 4249 * 0b0..Interrupt disabled. 4250 * 0b1..Interrupt enabled. 4251 */ 4252 #define LPI2C_SIER_RSIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_RSIE_SHIFT)) & LPI2C_SIER_RSIE_MASK) 4253 #define LPI2C_SIER_SDIE_MASK (0x200U) 4254 #define LPI2C_SIER_SDIE_SHIFT (9U) 4255 /*! SDIE - STOP Detect Interrupt Enable 4256 * 0b0..Interrupt disabled. 4257 * 0b1..Interrupt enabled. 4258 */ 4259 #define LPI2C_SIER_SDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_SDIE_SHIFT)) & LPI2C_SIER_SDIE_MASK) 4260 #define LPI2C_SIER_BEIE_MASK (0x400U) 4261 #define LPI2C_SIER_BEIE_SHIFT (10U) 4262 /*! BEIE - Bit Error Interrupt Enable 4263 * 0b0..Interrupt disabled. 4264 * 0b1..Interrupt enabled. 4265 */ 4266 #define LPI2C_SIER_BEIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_BEIE_SHIFT)) & LPI2C_SIER_BEIE_MASK) 4267 #define LPI2C_SIER_FEIE_MASK (0x800U) 4268 #define LPI2C_SIER_FEIE_SHIFT (11U) 4269 /*! FEIE - FIFO Error Interrupt Enable 4270 * 0b0..Interrupt disabled. 4271 * 0b1..Interrupt enabled. 4272 */ 4273 #define LPI2C_SIER_FEIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_FEIE_SHIFT)) & LPI2C_SIER_FEIE_MASK) 4274 #define LPI2C_SIER_AM0IE_MASK (0x1000U) 4275 #define LPI2C_SIER_AM0IE_SHIFT (12U) 4276 /*! AM0IE - Address Match 0 Interrupt Enable 4277 * 0b0..Interrupt enabled. 4278 * 0b1..Interrupt disabled. 4279 */ 4280 #define LPI2C_SIER_AM0IE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_AM0IE_SHIFT)) & LPI2C_SIER_AM0IE_MASK) 4281 #define LPI2C_SIER_AM1F_MASK (0x2000U) 4282 #define LPI2C_SIER_AM1F_SHIFT (13U) 4283 /*! AM1F - Address Match 1 Interrupt Enable 4284 * 0b0..Interrupt disabled. 4285 * 0b1..Interrupt enabled. 4286 */ 4287 #define LPI2C_SIER_AM1F(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_AM1F_SHIFT)) & LPI2C_SIER_AM1F_MASK) 4288 #define LPI2C_SIER_GCIE_MASK (0x4000U) 4289 #define LPI2C_SIER_GCIE_SHIFT (14U) 4290 /*! GCIE - General Call Interrupt Enable 4291 * 0b0..Interrupt disabled. 4292 * 0b1..Interrupt enabled. 4293 */ 4294 #define LPI2C_SIER_GCIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_GCIE_SHIFT)) & LPI2C_SIER_GCIE_MASK) 4295 #define LPI2C_SIER_SARIE_MASK (0x8000U) 4296 #define LPI2C_SIER_SARIE_SHIFT (15U) 4297 /*! SARIE - SMBus Alert Response Interrupt Enable 4298 * 0b0..Interrupt disabled. 4299 * 0b1..Interrupt enabled. 4300 */ 4301 #define LPI2C_SIER_SARIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_SARIE_SHIFT)) & LPI2C_SIER_SARIE_MASK) 4302 /*! @} */ 4303 4304 /*! @name SDER - Slave DMA Enable Register */ 4305 /*! @{ */ 4306 #define LPI2C_SDER_TDDE_MASK (0x1U) 4307 #define LPI2C_SDER_TDDE_SHIFT (0U) 4308 /*! TDDE - Transmit Data DMA Enable 4309 * 0b0..DMA request disabled. 4310 * 0b1..DMA request enabled 4311 */ 4312 #define LPI2C_SDER_TDDE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SDER_TDDE_SHIFT)) & LPI2C_SDER_TDDE_MASK) 4313 #define LPI2C_SDER_RDDE_MASK (0x2U) 4314 #define LPI2C_SDER_RDDE_SHIFT (1U) 4315 /*! RDDE - Receive Data DMA Enable 4316 * 0b0..DMA request disabled. 4317 * 0b1..DMA request enabled. 4318 */ 4319 #define LPI2C_SDER_RDDE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SDER_RDDE_SHIFT)) & LPI2C_SDER_RDDE_MASK) 4320 #define LPI2C_SDER_AVDE_MASK (0x4U) 4321 #define LPI2C_SDER_AVDE_SHIFT (2U) 4322 /*! AVDE - Address Valid DMA Enable 4323 * 0b0..DMA request disabled. 4324 * 0b1..DMA request enabled. 4325 */ 4326 #define LPI2C_SDER_AVDE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SDER_AVDE_SHIFT)) & LPI2C_SDER_AVDE_MASK) 4327 /*! @} */ 4328 4329 /*! @name SCFGR1 - Slave Configuration Register 1 */ 4330 /*! @{ */ 4331 #define LPI2C_SCFGR1_ADRSTALL_MASK (0x1U) 4332 #define LPI2C_SCFGR1_ADRSTALL_SHIFT (0U) 4333 /*! ADRSTALL - Address SCL Stall 4334 * 0b0..Clock stretching disabled. 4335 * 0b1..Clock stretching enabled. 4336 */ 4337 #define LPI2C_SCFGR1_ADRSTALL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_ADRSTALL_SHIFT)) & LPI2C_SCFGR1_ADRSTALL_MASK) 4338 #define LPI2C_SCFGR1_RXSTALL_MASK (0x2U) 4339 #define LPI2C_SCFGR1_RXSTALL_SHIFT (1U) 4340 /*! RXSTALL - RX SCL Stall 4341 * 0b0..Clock stretching disabled. 4342 * 0b1..Clock stretching enabled. 4343 */ 4344 #define LPI2C_SCFGR1_RXSTALL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_RXSTALL_SHIFT)) & LPI2C_SCFGR1_RXSTALL_MASK) 4345 #define LPI2C_SCFGR1_TXDSTALL_MASK (0x4U) 4346 #define LPI2C_SCFGR1_TXDSTALL_SHIFT (2U) 4347 /*! TXDSTALL - TX Data SCL Stall 4348 * 0b0..Clock stretching disabled. 4349 * 0b1..Clock stretching enabled. 4350 */ 4351 #define LPI2C_SCFGR1_TXDSTALL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_TXDSTALL_SHIFT)) & LPI2C_SCFGR1_TXDSTALL_MASK) 4352 #define LPI2C_SCFGR1_ACKSTALL_MASK (0x8U) 4353 #define LPI2C_SCFGR1_ACKSTALL_SHIFT (3U) 4354 /*! ACKSTALL - ACK SCL Stall 4355 * 0b0..Clock stretching disabled. 4356 * 0b1..Clock stretching enabled. 4357 */ 4358 #define LPI2C_SCFGR1_ACKSTALL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_ACKSTALL_SHIFT)) & LPI2C_SCFGR1_ACKSTALL_MASK) 4359 #define LPI2C_SCFGR1_GCEN_MASK (0x100U) 4360 #define LPI2C_SCFGR1_GCEN_SHIFT (8U) 4361 /*! GCEN - General Call Enable 4362 * 0b0..General Call address is disabled. 4363 * 0b1..General call address is enabled. 4364 */ 4365 #define LPI2C_SCFGR1_GCEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_GCEN_SHIFT)) & LPI2C_SCFGR1_GCEN_MASK) 4366 #define LPI2C_SCFGR1_SAEN_MASK (0x200U) 4367 #define LPI2C_SCFGR1_SAEN_SHIFT (9U) 4368 /*! SAEN - SMBus Alert Enable 4369 * 0b0..Disables match on SMBus Alert. 4370 * 0b1..Enables match on SMBus Alert. 4371 */ 4372 #define LPI2C_SCFGR1_SAEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_SAEN_SHIFT)) & LPI2C_SCFGR1_SAEN_MASK) 4373 #define LPI2C_SCFGR1_TXCFG_MASK (0x400U) 4374 #define LPI2C_SCFGR1_TXCFG_SHIFT (10U) 4375 /*! TXCFG - Transmit Flag Configuration 4376 * 0b0..Transmit Data Flag will only assert during a slave-transmit transfer when the transmit data register is empty. 4377 * 0b1..Transmit Data Flag will assert whenever the transmit data register is empty. 4378 */ 4379 #define LPI2C_SCFGR1_TXCFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_TXCFG_SHIFT)) & LPI2C_SCFGR1_TXCFG_MASK) 4380 #define LPI2C_SCFGR1_RXCFG_MASK (0x800U) 4381 #define LPI2C_SCFGR1_RXCFG_SHIFT (11U) 4382 /*! RXCFG - Receive Data Configuration 4383 * 0b0..Reading the receive data register will return receive data and clear the receive data flag. 4384 * 0b1..Reading the receive data register when the address valid flag is set will return the address status 4385 * register and clear the address valid flag. Reading the receive data register when the address valid flag is 4386 * clear will return receive data and clear the receive data flag. 4387 */ 4388 #define LPI2C_SCFGR1_RXCFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_RXCFG_SHIFT)) & LPI2C_SCFGR1_RXCFG_MASK) 4389 #define LPI2C_SCFGR1_IGNACK_MASK (0x1000U) 4390 #define LPI2C_SCFGR1_IGNACK_SHIFT (12U) 4391 /*! IGNACK - Ignore NACK 4392 * 0b0..Slave will end transfer when NACK detected. 4393 * 0b1..Slave will not end transfer when NACK detected. 4394 */ 4395 #define LPI2C_SCFGR1_IGNACK(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_IGNACK_SHIFT)) & LPI2C_SCFGR1_IGNACK_MASK) 4396 #define LPI2C_SCFGR1_HSMEN_MASK (0x2000U) 4397 #define LPI2C_SCFGR1_HSMEN_SHIFT (13U) 4398 /*! HSMEN - High Speed Mode Enable 4399 * 0b0..Disables detection of Hs-mode master code. 4400 * 0b1..Enables detection of Hs-mode master code. 4401 */ 4402 #define LPI2C_SCFGR1_HSMEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_HSMEN_SHIFT)) & LPI2C_SCFGR1_HSMEN_MASK) 4403 #define LPI2C_SCFGR1_ADDRCFG_MASK (0x70000U) 4404 #define LPI2C_SCFGR1_ADDRCFG_SHIFT (16U) 4405 /*! ADDRCFG - Address Configuration 4406 * 0b000..Address match 0 (7-bit). 4407 * 0b001..Address match 0 (10-bit). 4408 * 0b010..Address match 0 (7-bit) or Address match 1 (7-bit). 4409 * 0b011..Address match 0 (10-bit) or Address match 1 (10-bit). 4410 * 0b100..Address match 0 (7-bit) or Address match 1 (10-bit). 4411 * 0b101..Address match 0 (10-bit) or Address match 1 (7-bit). 4412 * 0b110..From Address match 0 (7-bit) to Address match 1 (7-bit). 4413 * 0b111..From Address match 0 (10-bit) to Address match 1 (10-bit). 4414 */ 4415 #define LPI2C_SCFGR1_ADDRCFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_ADDRCFG_SHIFT)) & LPI2C_SCFGR1_ADDRCFG_MASK) 4416 /*! @} */ 4417 4418 /*! @name SCFGR2 - Slave Configuration Register 2 */ 4419 /*! @{ */ 4420 #define LPI2C_SCFGR2_CLKHOLD_MASK (0xFU) 4421 #define LPI2C_SCFGR2_CLKHOLD_SHIFT (0U) 4422 /*! CLKHOLD - Clock Hold Time 4423 */ 4424 #define LPI2C_SCFGR2_CLKHOLD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR2_CLKHOLD_SHIFT)) & LPI2C_SCFGR2_CLKHOLD_MASK) 4425 #define LPI2C_SCFGR2_DATAVD_MASK (0x3F00U) 4426 #define LPI2C_SCFGR2_DATAVD_SHIFT (8U) 4427 /*! DATAVD - Data Valid Delay 4428 */ 4429 #define LPI2C_SCFGR2_DATAVD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR2_DATAVD_SHIFT)) & LPI2C_SCFGR2_DATAVD_MASK) 4430 #define LPI2C_SCFGR2_FILTSCL_MASK (0xF0000U) 4431 #define LPI2C_SCFGR2_FILTSCL_SHIFT (16U) 4432 /*! FILTSCL - Glitch Filter SCL 4433 */ 4434 #define LPI2C_SCFGR2_FILTSCL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR2_FILTSCL_SHIFT)) & LPI2C_SCFGR2_FILTSCL_MASK) 4435 #define LPI2C_SCFGR2_FILTSDA_MASK (0xF000000U) 4436 #define LPI2C_SCFGR2_FILTSDA_SHIFT (24U) 4437 /*! FILTSDA - Glitch Filter SDA 4438 */ 4439 #define LPI2C_SCFGR2_FILTSDA(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR2_FILTSDA_SHIFT)) & LPI2C_SCFGR2_FILTSDA_MASK) 4440 /*! @} */ 4441 4442 /*! @name SAMR - Slave Address Match Register */ 4443 /*! @{ */ 4444 #define LPI2C_SAMR_ADDR0_MASK (0x7FEU) 4445 #define LPI2C_SAMR_ADDR0_SHIFT (1U) 4446 /*! ADDR0 - Address 0 Value 4447 */ 4448 #define LPI2C_SAMR_ADDR0(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SAMR_ADDR0_SHIFT)) & LPI2C_SAMR_ADDR0_MASK) 4449 #define LPI2C_SAMR_ADDR1_MASK (0x7FE0000U) 4450 #define LPI2C_SAMR_ADDR1_SHIFT (17U) 4451 /*! ADDR1 - Address 1 Value 4452 */ 4453 #define LPI2C_SAMR_ADDR1(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SAMR_ADDR1_SHIFT)) & LPI2C_SAMR_ADDR1_MASK) 4454 /*! @} */ 4455 4456 /*! @name SASR - Slave Address Status Register */ 4457 /*! @{ */ 4458 #define LPI2C_SASR_RADDR_MASK (0x7FFU) 4459 #define LPI2C_SASR_RADDR_SHIFT (0U) 4460 /*! RADDR - Received Address 4461 */ 4462 #define LPI2C_SASR_RADDR(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SASR_RADDR_SHIFT)) & LPI2C_SASR_RADDR_MASK) 4463 #define LPI2C_SASR_ANV_MASK (0x4000U) 4464 #define LPI2C_SASR_ANV_SHIFT (14U) 4465 /*! ANV - Address Not Valid 4466 * 0b0..RADDR is valid. 4467 * 0b1..RADDR is not valid. 4468 */ 4469 #define LPI2C_SASR_ANV(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SASR_ANV_SHIFT)) & LPI2C_SASR_ANV_MASK) 4470 /*! @} */ 4471 4472 /*! @name STAR - Slave Transmit ACK Register */ 4473 /*! @{ */ 4474 #define LPI2C_STAR_TXNACK_MASK (0x1U) 4475 #define LPI2C_STAR_TXNACK_SHIFT (0U) 4476 /*! TXNACK - Transmit NACK 4477 * 0b0..Transmit ACK for received word. 4478 * 0b1..Transmit NACK for received word. 4479 */ 4480 #define LPI2C_STAR_TXNACK(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_STAR_TXNACK_SHIFT)) & LPI2C_STAR_TXNACK_MASK) 4481 /*! @} */ 4482 4483 /*! @name STDR - Slave Transmit Data Register */ 4484 /*! @{ */ 4485 #define LPI2C_STDR_DATA_MASK (0xFFU) 4486 #define LPI2C_STDR_DATA_SHIFT (0U) 4487 /*! DATA - Transmit Data 4488 */ 4489 #define LPI2C_STDR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_STDR_DATA_SHIFT)) & LPI2C_STDR_DATA_MASK) 4490 /*! @} */ 4491 4492 /*! @name SRDR - Slave Receive Data Register */ 4493 /*! @{ */ 4494 #define LPI2C_SRDR_DATA_MASK (0xFFU) 4495 #define LPI2C_SRDR_DATA_SHIFT (0U) 4496 /*! DATA - Receive Data 4497 */ 4498 #define LPI2C_SRDR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SRDR_DATA_SHIFT)) & LPI2C_SRDR_DATA_MASK) 4499 #define LPI2C_SRDR_RXEMPTY_MASK (0x4000U) 4500 #define LPI2C_SRDR_RXEMPTY_SHIFT (14U) 4501 /*! RXEMPTY - RX Empty 4502 * 0b0..The Receive Data Register is not empty. 4503 * 0b1..The Receive Data Register is empty. 4504 */ 4505 #define LPI2C_SRDR_RXEMPTY(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SRDR_RXEMPTY_SHIFT)) & LPI2C_SRDR_RXEMPTY_MASK) 4506 #define LPI2C_SRDR_SOF_MASK (0x8000U) 4507 #define LPI2C_SRDR_SOF_SHIFT (15U) 4508 /*! SOF - Start Of Frame 4509 * 0b0..Indicates this is not the first data word since a (repeated) START or STOP condition. 4510 * 0b1..Indicates this is the first data word since a (repeated) START or STOP condition. 4511 */ 4512 #define LPI2C_SRDR_SOF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SRDR_SOF_SHIFT)) & LPI2C_SRDR_SOF_MASK) 4513 /*! @} */ 4514 4515 4516 /*! 4517 * @} 4518 */ /* end of group LPI2C_Register_Masks */ 4519 4520 4521 /* LPI2C - Peripheral instance base addresses */ 4522 /** Peripheral LPI2C0 base address */ 4523 #define LPI2C0_BASE (0x40066000u) 4524 /** Peripheral LPI2C0 base pointer */ 4525 #define LPI2C0 ((LPI2C_Type *)LPI2C0_BASE) 4526 /** Array initializer of LPI2C peripheral base addresses */ 4527 #define LPI2C_BASE_ADDRS { LPI2C0_BASE } 4528 /** Array initializer of LPI2C peripheral base pointers */ 4529 #define LPI2C_BASE_PTRS { LPI2C0 } 4530 /** Interrupt vectors for the LPI2C peripheral type */ 4531 #define LPI2C_IRQS { LPI2C0_IRQn } 4532 4533 /*! 4534 * @} 4535 */ /* end of group LPI2C_Peripheral_Access_Layer */ 4536 4537 4538 /* ---------------------------------------------------------------------------- 4539 -- LPIT Peripheral Access Layer 4540 ---------------------------------------------------------------------------- */ 4541 4542 /*! 4543 * @addtogroup LPIT_Peripheral_Access_Layer LPIT Peripheral Access Layer 4544 * @{ 4545 */ 4546 4547 /** LPIT - Register Layout Typedef */ 4548 typedef struct { 4549 __I uint32_t VERID; /**< Version ID Register, offset: 0x0 */ 4550 __I uint32_t PARAM; /**< Parameter Register, offset: 0x4 */ 4551 __IO uint32_t MCR; /**< Module Control Register, offset: 0x8 */ 4552 __IO uint32_t MSR; /**< Module Status Register, offset: 0xC */ 4553 __IO uint32_t MIER; /**< Module Interrupt Enable Register, offset: 0x10 */ 4554 __IO uint32_t SETTEN; /**< Set Timer Enable Register, offset: 0x14 */ 4555 __O uint32_t CLRTEN; /**< Clear Timer Enable Register, offset: 0x18 */ 4556 uint8_t RESERVED_0[4]; 4557 struct { /* offset: 0x20, array step: 0x10 */ 4558 __IO uint32_t TVAL; /**< Timer Value Register, array offset: 0x20, array step: 0x10 */ 4559 __I uint32_t CVAL; /**< Current Timer Value, array offset: 0x24, array step: 0x10 */ 4560 __IO uint32_t TCTRL; /**< Timer Control Register, array offset: 0x28, array step: 0x10 */ 4561 uint8_t RESERVED_0[4]; 4562 } CHANNEL[2]; 4563 } LPIT_Type; 4564 4565 /* ---------------------------------------------------------------------------- 4566 -- LPIT Register Masks 4567 ---------------------------------------------------------------------------- */ 4568 4569 /*! 4570 * @addtogroup LPIT_Register_Masks LPIT Register Masks 4571 * @{ 4572 */ 4573 4574 /*! @name VERID - Version ID Register */ 4575 /*! @{ */ 4576 #define LPIT_VERID_FEATURE_MASK (0xFFFFU) 4577 #define LPIT_VERID_FEATURE_SHIFT (0U) 4578 /*! FEATURE - Feature Number 4579 */ 4580 #define LPIT_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << LPIT_VERID_FEATURE_SHIFT)) & LPIT_VERID_FEATURE_MASK) 4581 #define LPIT_VERID_MINOR_MASK (0xFF0000U) 4582 #define LPIT_VERID_MINOR_SHIFT (16U) 4583 /*! MINOR - Minor Version Number 4584 */ 4585 #define LPIT_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << LPIT_VERID_MINOR_SHIFT)) & LPIT_VERID_MINOR_MASK) 4586 #define LPIT_VERID_MAJOR_MASK (0xFF000000U) 4587 #define LPIT_VERID_MAJOR_SHIFT (24U) 4588 /*! MAJOR - Major Version Number 4589 */ 4590 #define LPIT_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << LPIT_VERID_MAJOR_SHIFT)) & LPIT_VERID_MAJOR_MASK) 4591 /*! @} */ 4592 4593 /*! @name PARAM - Parameter Register */ 4594 /*! @{ */ 4595 #define LPIT_PARAM_CHANNEL_MASK (0xFFU) 4596 #define LPIT_PARAM_CHANNEL_SHIFT (0U) 4597 /*! CHANNEL - Number of Timer Channels 4598 */ 4599 #define LPIT_PARAM_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << LPIT_PARAM_CHANNEL_SHIFT)) & LPIT_PARAM_CHANNEL_MASK) 4600 #define LPIT_PARAM_EXT_TRIG_MASK (0xFF00U) 4601 #define LPIT_PARAM_EXT_TRIG_SHIFT (8U) 4602 /*! EXT_TRIG - Number of External Trigger Inputs 4603 */ 4604 #define LPIT_PARAM_EXT_TRIG(x) (((uint32_t)(((uint32_t)(x)) << LPIT_PARAM_EXT_TRIG_SHIFT)) & LPIT_PARAM_EXT_TRIG_MASK) 4605 /*! @} */ 4606 4607 /*! @name MCR - Module Control Register */ 4608 /*! @{ */ 4609 #define LPIT_MCR_M_CEN_MASK (0x1U) 4610 #define LPIT_MCR_M_CEN_SHIFT (0U) 4611 /*! M_CEN - Module Clock Enable 4612 * 0b0..Protocol clock to timers is disabled 4613 * 0b1..Protocol clock to timers is enabled 4614 */ 4615 #define LPIT_MCR_M_CEN(x) (((uint32_t)(((uint32_t)(x)) << LPIT_MCR_M_CEN_SHIFT)) & LPIT_MCR_M_CEN_MASK) 4616 #define LPIT_MCR_SW_RST_MASK (0x2U) 4617 #define LPIT_MCR_SW_RST_SHIFT (1U) 4618 /*! SW_RST - Software Reset Bit 4619 * 0b0..Timer channels and registers are not reset 4620 * 0b1..Timer channels and registers are reset 4621 */ 4622 #define LPIT_MCR_SW_RST(x) (((uint32_t)(((uint32_t)(x)) << LPIT_MCR_SW_RST_SHIFT)) & LPIT_MCR_SW_RST_MASK) 4623 #define LPIT_MCR_DOZE_EN_MASK (0x4U) 4624 #define LPIT_MCR_DOZE_EN_SHIFT (2U) 4625 /*! DOZE_EN - DOZE Mode Enable Bit 4626 * 0b0..Timer channels are stopped in DOZE mode 4627 * 0b1..Timer channels continue to run in DOZE mode 4628 */ 4629 #define LPIT_MCR_DOZE_EN(x) (((uint32_t)(((uint32_t)(x)) << LPIT_MCR_DOZE_EN_SHIFT)) & LPIT_MCR_DOZE_EN_MASK) 4630 #define LPIT_MCR_DBG_EN_MASK (0x8U) 4631 #define LPIT_MCR_DBG_EN_SHIFT (3U) 4632 /*! DBG_EN - Debug Enable Bit 4633 * 0b0..Timer channels are stopped in Debug mode 4634 * 0b1..Timer channels continue to run in Debug mode 4635 */ 4636 #define LPIT_MCR_DBG_EN(x) (((uint32_t)(((uint32_t)(x)) << LPIT_MCR_DBG_EN_SHIFT)) & LPIT_MCR_DBG_EN_MASK) 4637 /*! @} */ 4638 4639 /*! @name MSR - Module Status Register */ 4640 /*! @{ */ 4641 #define LPIT_MSR_TIF0_MASK (0x1U) 4642 #define LPIT_MSR_TIF0_SHIFT (0U) 4643 /*! TIF0 - Channel 0 Timer Interrupt Flag 4644 * 0b0..Timer has not timed out 4645 * 0b1..Timeout has occurred 4646 */ 4647 #define LPIT_MSR_TIF0(x) (((uint32_t)(((uint32_t)(x)) << LPIT_MSR_TIF0_SHIFT)) & LPIT_MSR_TIF0_MASK) 4648 #define LPIT_MSR_TIF1_MASK (0x2U) 4649 #define LPIT_MSR_TIF1_SHIFT (1U) 4650 /*! TIF1 - Channel 1 Timer Interrupt Flag 4651 * 0b0..Timer has not timed out 4652 * 0b1..Timeout has occurred 4653 */ 4654 #define LPIT_MSR_TIF1(x) (((uint32_t)(((uint32_t)(x)) << LPIT_MSR_TIF1_SHIFT)) & LPIT_MSR_TIF1_MASK) 4655 #define LPIT_MSR_TIF2_MASK (0x4U) 4656 #define LPIT_MSR_TIF2_SHIFT (2U) 4657 /*! TIF2 - Channel 2 Timer Interrupt Flag 4658 * 0b0..Timer has not timed out 4659 * 0b1..Timeout has occurred 4660 */ 4661 #define LPIT_MSR_TIF2(x) (((uint32_t)(((uint32_t)(x)) << LPIT_MSR_TIF2_SHIFT)) & LPIT_MSR_TIF2_MASK) 4662 #define LPIT_MSR_TIF3_MASK (0x8U) 4663 #define LPIT_MSR_TIF3_SHIFT (3U) 4664 /*! TIF3 - Channel 3 Timer Interrupt Flag 4665 * 0b0..Timer has not timed out 4666 * 0b1..Timeout has occurred 4667 */ 4668 #define LPIT_MSR_TIF3(x) (((uint32_t)(((uint32_t)(x)) << LPIT_MSR_TIF3_SHIFT)) & LPIT_MSR_TIF3_MASK) 4669 /*! @} */ 4670 4671 /*! @name MIER - Module Interrupt Enable Register */ 4672 /*! @{ */ 4673 #define LPIT_MIER_TIE0_MASK (0x1U) 4674 #define LPIT_MIER_TIE0_SHIFT (0U) 4675 /*! TIE0 - Channel 0 Timer Interrupt Enable 4676 * 0b0..Interrupt generation is disabled 4677 * 0b1..Interrupt generation is enabled 4678 */ 4679 #define LPIT_MIER_TIE0(x) (((uint32_t)(((uint32_t)(x)) << LPIT_MIER_TIE0_SHIFT)) & LPIT_MIER_TIE0_MASK) 4680 #define LPIT_MIER_TIE1_MASK (0x2U) 4681 #define LPIT_MIER_TIE1_SHIFT (1U) 4682 /*! TIE1 - Channel 1 Timer Interrupt Enable 4683 * 0b0..Interrupt generation is disabled 4684 * 0b1..Interrupt generation is enabled 4685 */ 4686 #define LPIT_MIER_TIE1(x) (((uint32_t)(((uint32_t)(x)) << LPIT_MIER_TIE1_SHIFT)) & LPIT_MIER_TIE1_MASK) 4687 #define LPIT_MIER_TIE2_MASK (0x4U) 4688 #define LPIT_MIER_TIE2_SHIFT (2U) 4689 /*! TIE2 - Channel 2 Timer Interrupt Enable 4690 * 0b0..Interrupt generation is disabled 4691 * 0b1..Interrupt generation is enabled 4692 */ 4693 #define LPIT_MIER_TIE2(x) (((uint32_t)(((uint32_t)(x)) << LPIT_MIER_TIE2_SHIFT)) & LPIT_MIER_TIE2_MASK) 4694 #define LPIT_MIER_TIE3_MASK (0x8U) 4695 #define LPIT_MIER_TIE3_SHIFT (3U) 4696 /*! TIE3 - Channel 3 Timer Interrupt Enable 4697 * 0b0..Interrupt generation is disabled 4698 * 0b1..Interrupt generation is enabled 4699 */ 4700 #define LPIT_MIER_TIE3(x) (((uint32_t)(((uint32_t)(x)) << LPIT_MIER_TIE3_SHIFT)) & LPIT_MIER_TIE3_MASK) 4701 /*! @} */ 4702 4703 /*! @name SETTEN - Set Timer Enable Register */ 4704 /*! @{ */ 4705 #define LPIT_SETTEN_SET_T_EN_0_MASK (0x1U) 4706 #define LPIT_SETTEN_SET_T_EN_0_SHIFT (0U) 4707 /*! SET_T_EN_0 - Set Timer 0 Enable 4708 * 0b0..No effect 4709 * 0b1..Enables the Timer Channel 0 4710 */ 4711 #define LPIT_SETTEN_SET_T_EN_0(x) (((uint32_t)(((uint32_t)(x)) << LPIT_SETTEN_SET_T_EN_0_SHIFT)) & LPIT_SETTEN_SET_T_EN_0_MASK) 4712 #define LPIT_SETTEN_SET_T_EN_1_MASK (0x2U) 4713 #define LPIT_SETTEN_SET_T_EN_1_SHIFT (1U) 4714 /*! SET_T_EN_1 - Set Timer 1 Enable 4715 * 0b0..No Effect 4716 * 0b1..Enables the Timer Channel 1 4717 */ 4718 #define LPIT_SETTEN_SET_T_EN_1(x) (((uint32_t)(((uint32_t)(x)) << LPIT_SETTEN_SET_T_EN_1_SHIFT)) & LPIT_SETTEN_SET_T_EN_1_MASK) 4719 #define LPIT_SETTEN_SET_T_EN_2_MASK (0x4U) 4720 #define LPIT_SETTEN_SET_T_EN_2_SHIFT (2U) 4721 /*! SET_T_EN_2 - Set Timer 2 Enable 4722 * 0b0..No Effect 4723 * 0b1..Enables the Timer Channel 2 4724 */ 4725 #define LPIT_SETTEN_SET_T_EN_2(x) (((uint32_t)(((uint32_t)(x)) << LPIT_SETTEN_SET_T_EN_2_SHIFT)) & LPIT_SETTEN_SET_T_EN_2_MASK) 4726 #define LPIT_SETTEN_SET_T_EN_3_MASK (0x8U) 4727 #define LPIT_SETTEN_SET_T_EN_3_SHIFT (3U) 4728 /*! SET_T_EN_3 - Set Timer 3 Enable 4729 * 0b0..No effect 4730 * 0b1..Enables the Timer Channel 3 4731 */ 4732 #define LPIT_SETTEN_SET_T_EN_3(x) (((uint32_t)(((uint32_t)(x)) << LPIT_SETTEN_SET_T_EN_3_SHIFT)) & LPIT_SETTEN_SET_T_EN_3_MASK) 4733 /*! @} */ 4734 4735 /*! @name CLRTEN - Clear Timer Enable Register */ 4736 /*! @{ */ 4737 #define LPIT_CLRTEN_CLR_T_EN_0_MASK (0x1U) 4738 #define LPIT_CLRTEN_CLR_T_EN_0_SHIFT (0U) 4739 /*! CLR_T_EN_0 - Clear Timer 0 Enable 4740 * 0b0..No action 4741 * 0b1..Clear T_EN bit for Timer Channel 0 4742 */ 4743 #define LPIT_CLRTEN_CLR_T_EN_0(x) (((uint32_t)(((uint32_t)(x)) << LPIT_CLRTEN_CLR_T_EN_0_SHIFT)) & LPIT_CLRTEN_CLR_T_EN_0_MASK) 4744 #define LPIT_CLRTEN_CLR_T_EN_1_MASK (0x2U) 4745 #define LPIT_CLRTEN_CLR_T_EN_1_SHIFT (1U) 4746 /*! CLR_T_EN_1 - Clear Timer 1 Enable 4747 * 0b0..No Action 4748 * 0b1..Clear T_EN bit for Timer Channel 1 4749 */ 4750 #define LPIT_CLRTEN_CLR_T_EN_1(x) (((uint32_t)(((uint32_t)(x)) << LPIT_CLRTEN_CLR_T_EN_1_SHIFT)) & LPIT_CLRTEN_CLR_T_EN_1_MASK) 4751 #define LPIT_CLRTEN_CLR_T_EN_2_MASK (0x4U) 4752 #define LPIT_CLRTEN_CLR_T_EN_2_SHIFT (2U) 4753 /*! CLR_T_EN_2 - Clear Timer 2 Enable 4754 * 0b0..No Action 4755 * 0b1..Clear T_EN bit for Timer Channel 2 4756 */ 4757 #define LPIT_CLRTEN_CLR_T_EN_2(x) (((uint32_t)(((uint32_t)(x)) << LPIT_CLRTEN_CLR_T_EN_2_SHIFT)) & LPIT_CLRTEN_CLR_T_EN_2_MASK) 4758 #define LPIT_CLRTEN_CLR_T_EN_3_MASK (0x8U) 4759 #define LPIT_CLRTEN_CLR_T_EN_3_SHIFT (3U) 4760 /*! CLR_T_EN_3 - Clear Timer 3 Enable 4761 * 0b0..No Action 4762 * 0b1..Clear T_EN bit for Timer Channel 3 4763 */ 4764 #define LPIT_CLRTEN_CLR_T_EN_3(x) (((uint32_t)(((uint32_t)(x)) << LPIT_CLRTEN_CLR_T_EN_3_SHIFT)) & LPIT_CLRTEN_CLR_T_EN_3_MASK) 4765 /*! @} */ 4766 4767 /*! @name TVAL - Timer Value Register */ 4768 /*! @{ */ 4769 #define LPIT_TVAL_TMR_VAL_MASK (0xFFFFFFFFU) 4770 #define LPIT_TVAL_TMR_VAL_SHIFT (0U) 4771 /*! TMR_VAL - Timer Value 4772 * 0b00000000000000000000000000000000..Invalid load value in compare modes 4773 */ 4774 #define LPIT_TVAL_TMR_VAL(x) (((uint32_t)(((uint32_t)(x)) << LPIT_TVAL_TMR_VAL_SHIFT)) & LPIT_TVAL_TMR_VAL_MASK) 4775 /*! @} */ 4776 4777 /* The count of LPIT_TVAL */ 4778 #define LPIT_TVAL_COUNT (2U) 4779 4780 /*! @name CVAL - Current Timer Value */ 4781 /*! @{ */ 4782 #define LPIT_CVAL_TMR_CUR_VAL_MASK (0xFFFFFFFFU) 4783 #define LPIT_CVAL_TMR_CUR_VAL_SHIFT (0U) 4784 /*! TMR_CUR_VAL - Current Timer Value 4785 */ 4786 #define LPIT_CVAL_TMR_CUR_VAL(x) (((uint32_t)(((uint32_t)(x)) << LPIT_CVAL_TMR_CUR_VAL_SHIFT)) & LPIT_CVAL_TMR_CUR_VAL_MASK) 4787 /*! @} */ 4788 4789 /* The count of LPIT_CVAL */ 4790 #define LPIT_CVAL_COUNT (2U) 4791 4792 /*! @name TCTRL - Timer Control Register */ 4793 /*! @{ */ 4794 #define LPIT_TCTRL_T_EN_MASK (0x1U) 4795 #define LPIT_TCTRL_T_EN_SHIFT (0U) 4796 /*! T_EN - Timer Enable 4797 * 0b0..Timer Channel is disabled 4798 * 0b1..Timer Channel is enabled 4799 */ 4800 #define LPIT_TCTRL_T_EN(x) (((uint32_t)(((uint32_t)(x)) << LPIT_TCTRL_T_EN_SHIFT)) & LPIT_TCTRL_T_EN_MASK) 4801 #define LPIT_TCTRL_CHAIN_MASK (0x2U) 4802 #define LPIT_TCTRL_CHAIN_SHIFT (1U) 4803 /*! CHAIN - Chain Channel 4804 * 0b0..Channel Chaining is disabled. Channel Timer runs independently. 4805 * 0b1..Channel Chaining is enabled. Timer decrements on previous channel's timeout 4806 */ 4807 #define LPIT_TCTRL_CHAIN(x) (((uint32_t)(((uint32_t)(x)) << LPIT_TCTRL_CHAIN_SHIFT)) & LPIT_TCTRL_CHAIN_MASK) 4808 #define LPIT_TCTRL_MODE_MASK (0xCU) 4809 #define LPIT_TCTRL_MODE_SHIFT (2U) 4810 /*! MODE - Timer Operation Mode 4811 * 0b00..32-bit Periodic Counter 4812 * 0b01..Dual 16-bit Periodic Counter 4813 * 0b10..32-bit Trigger Accumulator 4814 * 0b11..32-bit Trigger Input Capture 4815 */ 4816 #define LPIT_TCTRL_MODE(x) (((uint32_t)(((uint32_t)(x)) << LPIT_TCTRL_MODE_SHIFT)) & LPIT_TCTRL_MODE_MASK) 4817 #define LPIT_TCTRL_TSOT_MASK (0x10000U) 4818 #define LPIT_TCTRL_TSOT_SHIFT (16U) 4819 /*! TSOT - Timer Start On Trigger 4820 * 0b0..Timer starts to decrement immediately based on restart condition (controlled by TSOI bit) 4821 * 0b1..Timer starts to decrement when rising edge on selected trigger is detected 4822 */ 4823 #define LPIT_TCTRL_TSOT(x) (((uint32_t)(((uint32_t)(x)) << LPIT_TCTRL_TSOT_SHIFT)) & LPIT_TCTRL_TSOT_MASK) 4824 #define LPIT_TCTRL_TSOI_MASK (0x20000U) 4825 #define LPIT_TCTRL_TSOI_SHIFT (17U) 4826 /*! TSOI - Timer Stop On Interrupt 4827 * 0b0..Timer does not stop after timeout 4828 * 0b1..Timer will stop after timeout and will restart after rising edge on the T_EN bit is detected (i.e. timer 4829 * channel is disabled and then enabled) 4830 */ 4831 #define LPIT_TCTRL_TSOI(x) (((uint32_t)(((uint32_t)(x)) << LPIT_TCTRL_TSOI_SHIFT)) & LPIT_TCTRL_TSOI_MASK) 4832 #define LPIT_TCTRL_TROT_MASK (0x40000U) 4833 #define LPIT_TCTRL_TROT_SHIFT (18U) 4834 /*! TROT - Timer Reload On Trigger 4835 * 0b0..Timer will not reload on selected trigger 4836 * 0b1..Timer will reload on selected trigger 4837 */ 4838 #define LPIT_TCTRL_TROT(x) (((uint32_t)(((uint32_t)(x)) << LPIT_TCTRL_TROT_SHIFT)) & LPIT_TCTRL_TROT_MASK) 4839 #define LPIT_TCTRL_TRG_SRC_MASK (0x800000U) 4840 #define LPIT_TCTRL_TRG_SRC_SHIFT (23U) 4841 /*! TRG_SRC - Trigger Source 4842 * 0b0..Trigger source selected in external 4843 * 0b1..Trigger source selected is the internal trigger 4844 */ 4845 #define LPIT_TCTRL_TRG_SRC(x) (((uint32_t)(((uint32_t)(x)) << LPIT_TCTRL_TRG_SRC_SHIFT)) & LPIT_TCTRL_TRG_SRC_MASK) 4846 #define LPIT_TCTRL_TRG_SEL_MASK (0xF000000U) 4847 #define LPIT_TCTRL_TRG_SEL_SHIFT (24U) 4848 /*! TRG_SEL - Trigger Select 4849 * 0b0000..Timer channel 0 trigger source is selected 4850 * 0b0001..Timer channel 1 trigger source is selected 4851 * 0b0010..Timer channel 2 trigger source is selected 4852 */ 4853 #define LPIT_TCTRL_TRG_SEL(x) (((uint32_t)(((uint32_t)(x)) << LPIT_TCTRL_TRG_SEL_SHIFT)) & LPIT_TCTRL_TRG_SEL_MASK) 4854 /*! @} */ 4855 4856 /* The count of LPIT_TCTRL */ 4857 #define LPIT_TCTRL_COUNT (2U) 4858 4859 4860 /*! 4861 * @} 4862 */ /* end of group LPIT_Register_Masks */ 4863 4864 4865 /* LPIT - Peripheral instance base addresses */ 4866 /** Peripheral LPIT0 base address */ 4867 #define LPIT0_BASE (0x40037000u) 4868 /** Peripheral LPIT0 base pointer */ 4869 #define LPIT0 ((LPIT_Type *)LPIT0_BASE) 4870 /** Array initializer of LPIT peripheral base addresses */ 4871 #define LPIT_BASE_ADDRS { LPIT0_BASE } 4872 /** Array initializer of LPIT peripheral base pointers */ 4873 #define LPIT_BASE_PTRS { LPIT0 } 4874 /** Interrupt vectors for the LPIT peripheral type */ 4875 #define LPIT_IRQS { { LPIT0_IRQn, LPIT0_IRQn, LPIT0_IRQn, LPIT0_IRQn } } 4876 4877 /*! 4878 * @} 4879 */ /* end of group LPIT_Peripheral_Access_Layer */ 4880 4881 4882 /* ---------------------------------------------------------------------------- 4883 -- LPSPI Peripheral Access Layer 4884 ---------------------------------------------------------------------------- */ 4885 4886 /*! 4887 * @addtogroup LPSPI_Peripheral_Access_Layer LPSPI Peripheral Access Layer 4888 * @{ 4889 */ 4890 4891 /** LPSPI - Register Layout Typedef */ 4892 typedef struct { 4893 __I uint32_t VERID; /**< Version ID Register, offset: 0x0 */ 4894 __I uint32_t PARAM; /**< Parameter Register, offset: 0x4 */ 4895 uint8_t RESERVED_0[8]; 4896 __IO uint32_t CR; /**< Control Register, offset: 0x10 */ 4897 __IO uint32_t SR; /**< Status Register, offset: 0x14 */ 4898 __IO uint32_t IER; /**< Interrupt Enable Register, offset: 0x18 */ 4899 __IO uint32_t DER; /**< DMA Enable Register, offset: 0x1C */ 4900 __IO uint32_t CFGR0; /**< Configuration Register 0, offset: 0x20 */ 4901 __IO uint32_t CFGR1; /**< Configuration Register 1, offset: 0x24 */ 4902 uint8_t RESERVED_1[8]; 4903 __IO uint32_t DMR0; /**< Data Match Register 0, offset: 0x30 */ 4904 __IO uint32_t DMR1; /**< Data Match Register 1, offset: 0x34 */ 4905 uint8_t RESERVED_2[8]; 4906 __IO uint32_t CCR; /**< Clock Configuration Register, offset: 0x40 */ 4907 uint8_t RESERVED_3[20]; 4908 __IO uint32_t FCR; /**< FIFO Control Register, offset: 0x58 */ 4909 __I uint32_t FSR; /**< FIFO Status Register, offset: 0x5C */ 4910 __IO uint32_t TCR; /**< Transmit Command Register, offset: 0x60 */ 4911 __O uint32_t TDR; /**< Transmit Data Register, offset: 0x64 */ 4912 uint8_t RESERVED_4[8]; 4913 __I uint32_t RSR; /**< Receive Status Register, offset: 0x70 */ 4914 __I uint32_t RDR; /**< Receive Data Register, offset: 0x74 */ 4915 } LPSPI_Type; 4916 4917 /* ---------------------------------------------------------------------------- 4918 -- LPSPI Register Masks 4919 ---------------------------------------------------------------------------- */ 4920 4921 /*! 4922 * @addtogroup LPSPI_Register_Masks LPSPI Register Masks 4923 * @{ 4924 */ 4925 4926 /*! @name VERID - Version ID Register */ 4927 /*! @{ */ 4928 #define LPSPI_VERID_FEATURE_MASK (0xFFFFU) 4929 #define LPSPI_VERID_FEATURE_SHIFT (0U) 4930 /*! FEATURE - Module Identification Number 4931 * 0b0000000000000100..Standard feature set supporting 32-bit shift register. 4932 */ 4933 #define LPSPI_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_VERID_FEATURE_SHIFT)) & LPSPI_VERID_FEATURE_MASK) 4934 #define LPSPI_VERID_MINOR_MASK (0xFF0000U) 4935 #define LPSPI_VERID_MINOR_SHIFT (16U) 4936 /*! MINOR - Minor Version Number 4937 */ 4938 #define LPSPI_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_VERID_MINOR_SHIFT)) & LPSPI_VERID_MINOR_MASK) 4939 #define LPSPI_VERID_MAJOR_MASK (0xFF000000U) 4940 #define LPSPI_VERID_MAJOR_SHIFT (24U) 4941 /*! MAJOR - Major Version Number 4942 */ 4943 #define LPSPI_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_VERID_MAJOR_SHIFT)) & LPSPI_VERID_MAJOR_MASK) 4944 /*! @} */ 4945 4946 /*! @name PARAM - Parameter Register */ 4947 /*! @{ */ 4948 #define LPSPI_PARAM_TXFIFO_MASK (0xFFU) 4949 #define LPSPI_PARAM_TXFIFO_SHIFT (0U) 4950 /*! TXFIFO - Transmit FIFO Size 4951 */ 4952 #define LPSPI_PARAM_TXFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_PARAM_TXFIFO_SHIFT)) & LPSPI_PARAM_TXFIFO_MASK) 4953 #define LPSPI_PARAM_RXFIFO_MASK (0xFF00U) 4954 #define LPSPI_PARAM_RXFIFO_SHIFT (8U) 4955 /*! RXFIFO - Receive FIFO Size 4956 */ 4957 #define LPSPI_PARAM_RXFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_PARAM_RXFIFO_SHIFT)) & LPSPI_PARAM_RXFIFO_MASK) 4958 /*! @} */ 4959 4960 /*! @name CR - Control Register */ 4961 /*! @{ */ 4962 #define LPSPI_CR_MEN_MASK (0x1U) 4963 #define LPSPI_CR_MEN_SHIFT (0U) 4964 /*! MEN - Module Enable 4965 * 0b0..Module is disabled. 4966 * 0b1..Module is enabled. 4967 */ 4968 #define LPSPI_CR_MEN(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_MEN_SHIFT)) & LPSPI_CR_MEN_MASK) 4969 #define LPSPI_CR_RST_MASK (0x2U) 4970 #define LPSPI_CR_RST_SHIFT (1U) 4971 /*! RST - Software Reset 4972 * 0b0..Master logic is not reset. 4973 * 0b1..Master logic is reset. 4974 */ 4975 #define LPSPI_CR_RST(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_RST_SHIFT)) & LPSPI_CR_RST_MASK) 4976 #define LPSPI_CR_DOZEN_MASK (0x4U) 4977 #define LPSPI_CR_DOZEN_SHIFT (2U) 4978 /*! DOZEN - Doze mode enable 4979 * 0b0..Module is enabled in Doze mode. 4980 * 0b1..Module is disabled in Doze mode. 4981 */ 4982 #define LPSPI_CR_DOZEN(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_DOZEN_SHIFT)) & LPSPI_CR_DOZEN_MASK) 4983 #define LPSPI_CR_DBGEN_MASK (0x8U) 4984 #define LPSPI_CR_DBGEN_SHIFT (3U) 4985 /*! DBGEN - Debug Enable 4986 * 0b0..Module is disabled in debug mode. 4987 * 0b1..Module is enabled in debug mode. 4988 */ 4989 #define LPSPI_CR_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_DBGEN_SHIFT)) & LPSPI_CR_DBGEN_MASK) 4990 #define LPSPI_CR_RTF_MASK (0x100U) 4991 #define LPSPI_CR_RTF_SHIFT (8U) 4992 /*! RTF - Reset Transmit FIFO 4993 * 0b0..No effect. 4994 * 0b1..Transmit FIFO is reset. 4995 */ 4996 #define LPSPI_CR_RTF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_RTF_SHIFT)) & LPSPI_CR_RTF_MASK) 4997 #define LPSPI_CR_RRF_MASK (0x200U) 4998 #define LPSPI_CR_RRF_SHIFT (9U) 4999 /*! RRF - Reset Receive FIFO 5000 * 0b0..No effect. 5001 * 0b1..Receive FIFO is reset. 5002 */ 5003 #define LPSPI_CR_RRF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_RRF_SHIFT)) & LPSPI_CR_RRF_MASK) 5004 /*! @} */ 5005 5006 /*! @name SR - Status Register */ 5007 /*! @{ */ 5008 #define LPSPI_SR_TDF_MASK (0x1U) 5009 #define LPSPI_SR_TDF_SHIFT (0U) 5010 /*! TDF - Transmit Data Flag 5011 * 0b0..Transmit data not requested. 5012 * 0b1..Transmit data is requested. 5013 */ 5014 #define LPSPI_SR_TDF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_TDF_SHIFT)) & LPSPI_SR_TDF_MASK) 5015 #define LPSPI_SR_RDF_MASK (0x2U) 5016 #define LPSPI_SR_RDF_SHIFT (1U) 5017 /*! RDF - Receive Data Flag 5018 * 0b0..Receive Data is not ready. 5019 * 0b1..Receive data is ready. 5020 */ 5021 #define LPSPI_SR_RDF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_RDF_SHIFT)) & LPSPI_SR_RDF_MASK) 5022 #define LPSPI_SR_WCF_MASK (0x100U) 5023 #define LPSPI_SR_WCF_SHIFT (8U) 5024 /*! WCF - Word Complete Flag 5025 * 0b0..Transfer word not completed. 5026 * 0b1..Transfer word completed. 5027 */ 5028 #define LPSPI_SR_WCF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_WCF_SHIFT)) & LPSPI_SR_WCF_MASK) 5029 #define LPSPI_SR_FCF_MASK (0x200U) 5030 #define LPSPI_SR_FCF_SHIFT (9U) 5031 /*! FCF - Frame Complete Flag 5032 * 0b0..Frame transfer has not completed. 5033 * 0b1..Frame transfer has completed. 5034 */ 5035 #define LPSPI_SR_FCF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_FCF_SHIFT)) & LPSPI_SR_FCF_MASK) 5036 #define LPSPI_SR_TCF_MASK (0x400U) 5037 #define LPSPI_SR_TCF_SHIFT (10U) 5038 /*! TCF - Transfer Complete Flag 5039 * 0b0..All transfers have not completed. 5040 * 0b1..All transfers have completed. 5041 */ 5042 #define LPSPI_SR_TCF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_TCF_SHIFT)) & LPSPI_SR_TCF_MASK) 5043 #define LPSPI_SR_TEF_MASK (0x800U) 5044 #define LPSPI_SR_TEF_SHIFT (11U) 5045 /*! TEF - Transmit Error Flag 5046 * 0b0..Transmit FIFO underrun has not occurred. 5047 * 0b1..Transmit FIFO underrun has occurred 5048 */ 5049 #define LPSPI_SR_TEF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_TEF_SHIFT)) & LPSPI_SR_TEF_MASK) 5050 #define LPSPI_SR_REF_MASK (0x1000U) 5051 #define LPSPI_SR_REF_SHIFT (12U) 5052 /*! REF - Receive Error Flag 5053 * 0b0..Receive FIFO has not overflowed. 5054 * 0b1..Receive FIFO has overflowed. 5055 */ 5056 #define LPSPI_SR_REF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_REF_SHIFT)) & LPSPI_SR_REF_MASK) 5057 #define LPSPI_SR_DMF_MASK (0x2000U) 5058 #define LPSPI_SR_DMF_SHIFT (13U) 5059 /*! DMF - Data Match Flag 5060 * 0b0..Have not received matching data. 5061 * 0b1..Have received matching data. 5062 */ 5063 #define LPSPI_SR_DMF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_DMF_SHIFT)) & LPSPI_SR_DMF_MASK) 5064 #define LPSPI_SR_MBF_MASK (0x1000000U) 5065 #define LPSPI_SR_MBF_SHIFT (24U) 5066 /*! MBF - Module Busy Flag 5067 * 0b0..LPSPI is idle. 5068 * 0b1..LPSPI is busy. 5069 */ 5070 #define LPSPI_SR_MBF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_MBF_SHIFT)) & LPSPI_SR_MBF_MASK) 5071 /*! @} */ 5072 5073 /*! @name IER - Interrupt Enable Register */ 5074 /*! @{ */ 5075 #define LPSPI_IER_TDIE_MASK (0x1U) 5076 #define LPSPI_IER_TDIE_SHIFT (0U) 5077 /*! TDIE - Transmit Data Interrupt Enable 5078 * 0b0..Interrupt disabled. 5079 * 0b1..Interrupt enabled 5080 */ 5081 #define LPSPI_IER_TDIE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_TDIE_SHIFT)) & LPSPI_IER_TDIE_MASK) 5082 #define LPSPI_IER_RDIE_MASK (0x2U) 5083 #define LPSPI_IER_RDIE_SHIFT (1U) 5084 /*! RDIE - Receive Data Interrupt Enable 5085 * 0b0..Interrupt disabled. 5086 * 0b1..Interrupt enabled. 5087 */ 5088 #define LPSPI_IER_RDIE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_RDIE_SHIFT)) & LPSPI_IER_RDIE_MASK) 5089 #define LPSPI_IER_WCIE_MASK (0x100U) 5090 #define LPSPI_IER_WCIE_SHIFT (8U) 5091 /*! WCIE - Word Complete Interrupt Enable 5092 * 0b0..Interrupt disabled. 5093 * 0b1..Interrupt enabled. 5094 */ 5095 #define LPSPI_IER_WCIE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_WCIE_SHIFT)) & LPSPI_IER_WCIE_MASK) 5096 #define LPSPI_IER_FCIE_MASK (0x200U) 5097 #define LPSPI_IER_FCIE_SHIFT (9U) 5098 /*! FCIE - Frame Complete Interrupt Enable 5099 * 0b0..Interrupt disabled. 5100 * 0b1..Interrupt enabled. 5101 */ 5102 #define LPSPI_IER_FCIE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_FCIE_SHIFT)) & LPSPI_IER_FCIE_MASK) 5103 #define LPSPI_IER_TCIE_MASK (0x400U) 5104 #define LPSPI_IER_TCIE_SHIFT (10U) 5105 /*! TCIE - Transfer Complete Interrupt Enable 5106 * 0b0..Interrupt disabled. 5107 * 0b1..Interrupt enabled. 5108 */ 5109 #define LPSPI_IER_TCIE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_TCIE_SHIFT)) & LPSPI_IER_TCIE_MASK) 5110 #define LPSPI_IER_TEIE_MASK (0x800U) 5111 #define LPSPI_IER_TEIE_SHIFT (11U) 5112 /*! TEIE - Transmit Error Interrupt Enable 5113 * 0b0..Interrupt disabled. 5114 * 0b1..Interrupt enabled. 5115 */ 5116 #define LPSPI_IER_TEIE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_TEIE_SHIFT)) & LPSPI_IER_TEIE_MASK) 5117 #define LPSPI_IER_REIE_MASK (0x1000U) 5118 #define LPSPI_IER_REIE_SHIFT (12U) 5119 /*! REIE - Receive Error Interrupt Enable 5120 * 0b0..Interrupt disabled. 5121 * 0b1..Interrupt enabled. 5122 */ 5123 #define LPSPI_IER_REIE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_REIE_SHIFT)) & LPSPI_IER_REIE_MASK) 5124 #define LPSPI_IER_DMIE_MASK (0x2000U) 5125 #define LPSPI_IER_DMIE_SHIFT (13U) 5126 /*! DMIE - Data Match Interrupt Enable 5127 * 0b0..Interrupt disabled. 5128 * 0b1..Interrupt enabled. 5129 */ 5130 #define LPSPI_IER_DMIE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_DMIE_SHIFT)) & LPSPI_IER_DMIE_MASK) 5131 /*! @} */ 5132 5133 /*! @name DER - DMA Enable Register */ 5134 /*! @{ */ 5135 #define LPSPI_DER_TDDE_MASK (0x1U) 5136 #define LPSPI_DER_TDDE_SHIFT (0U) 5137 /*! TDDE - Transmit Data DMA Enable 5138 * 0b0..DMA request disabled. 5139 * 0b1..DMA request enabled 5140 */ 5141 #define LPSPI_DER_TDDE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_DER_TDDE_SHIFT)) & LPSPI_DER_TDDE_MASK) 5142 #define LPSPI_DER_RDDE_MASK (0x2U) 5143 #define LPSPI_DER_RDDE_SHIFT (1U) 5144 /*! RDDE - Receive Data DMA Enable 5145 * 0b0..DMA request disabled. 5146 * 0b1..DMA request enabled. 5147 */ 5148 #define LPSPI_DER_RDDE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_DER_RDDE_SHIFT)) & LPSPI_DER_RDDE_MASK) 5149 /*! @} */ 5150 5151 /*! @name CFGR0 - Configuration Register 0 */ 5152 /*! @{ */ 5153 #define LPSPI_CFGR0_HREN_MASK (0x1U) 5154 #define LPSPI_CFGR0_HREN_SHIFT (0U) 5155 /*! HREN - Host Request Enable 5156 * 0b0..Host request is disabled. 5157 * 0b1..Host request is enabled. 5158 */ 5159 #define LPSPI_CFGR0_HREN(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR0_HREN_SHIFT)) & LPSPI_CFGR0_HREN_MASK) 5160 #define LPSPI_CFGR0_HRPOL_MASK (0x2U) 5161 #define LPSPI_CFGR0_HRPOL_SHIFT (1U) 5162 /*! HRPOL - Host Request Polarity 5163 * 0b0..Active low. 5164 * 0b1..Active high. 5165 */ 5166 #define LPSPI_CFGR0_HRPOL(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR0_HRPOL_SHIFT)) & LPSPI_CFGR0_HRPOL_MASK) 5167 #define LPSPI_CFGR0_HRSEL_MASK (0x4U) 5168 #define LPSPI_CFGR0_HRSEL_SHIFT (2U) 5169 /*! HRSEL - Host Request Select 5170 * 0b0..Host request input is pin LPSPI_HREQ. 5171 * 0b1..Host request input is input trigger. 5172 */ 5173 #define LPSPI_CFGR0_HRSEL(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR0_HRSEL_SHIFT)) & LPSPI_CFGR0_HRSEL_MASK) 5174 #define LPSPI_CFGR0_CIRFIFO_MASK (0x100U) 5175 #define LPSPI_CFGR0_CIRFIFO_SHIFT (8U) 5176 /*! CIRFIFO - Circular FIFO Enable 5177 * 0b0..Circular FIFO is disabled. 5178 * 0b1..Circular FIFO is enabled. 5179 */ 5180 #define LPSPI_CFGR0_CIRFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR0_CIRFIFO_SHIFT)) & LPSPI_CFGR0_CIRFIFO_MASK) 5181 #define LPSPI_CFGR0_RDMO_MASK (0x200U) 5182 #define LPSPI_CFGR0_RDMO_SHIFT (9U) 5183 /*! RDMO - Receive Data Match Only 5184 * 0b0..Received data is stored in the receive FIFO as normal. 5185 * 0b1..Received data is discarded unless the DMF is set. 5186 */ 5187 #define LPSPI_CFGR0_RDMO(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR0_RDMO_SHIFT)) & LPSPI_CFGR0_RDMO_MASK) 5188 /*! @} */ 5189 5190 /*! @name CFGR1 - Configuration Register 1 */ 5191 /*! @{ */ 5192 #define LPSPI_CFGR1_MASTER_MASK (0x1U) 5193 #define LPSPI_CFGR1_MASTER_SHIFT (0U) 5194 /*! MASTER - Master Mode 5195 * 0b0..Slave mode. 5196 * 0b1..Master mode. 5197 */ 5198 #define LPSPI_CFGR1_MASTER(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_MASTER_SHIFT)) & LPSPI_CFGR1_MASTER_MASK) 5199 #define LPSPI_CFGR1_SAMPLE_MASK (0x2U) 5200 #define LPSPI_CFGR1_SAMPLE_SHIFT (1U) 5201 /*! SAMPLE - Sample Point 5202 * 0b0..Input data sampled on SCK edge. 5203 * 0b1..Input data sampled on delayed SCK edge. 5204 */ 5205 #define LPSPI_CFGR1_SAMPLE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_SAMPLE_SHIFT)) & LPSPI_CFGR1_SAMPLE_MASK) 5206 #define LPSPI_CFGR1_AUTOPCS_MASK (0x4U) 5207 #define LPSPI_CFGR1_AUTOPCS_SHIFT (2U) 5208 /*! AUTOPCS - Automatic PCS 5209 * 0b0..Automatic PCS generation disabled. 5210 * 0b1..Automatic PCS generation enabled. 5211 */ 5212 #define LPSPI_CFGR1_AUTOPCS(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_AUTOPCS_SHIFT)) & LPSPI_CFGR1_AUTOPCS_MASK) 5213 #define LPSPI_CFGR1_NOSTALL_MASK (0x8U) 5214 #define LPSPI_CFGR1_NOSTALL_SHIFT (3U) 5215 /*! NOSTALL - No Stall 5216 * 0b0..Transfers will stall when transmit FIFO is empty or receive FIFO is full. 5217 * 0b1..Transfers will not stall, allowing transmit FIFO underrun or receive FIFO overrun to occur. 5218 */ 5219 #define LPSPI_CFGR1_NOSTALL(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_NOSTALL_SHIFT)) & LPSPI_CFGR1_NOSTALL_MASK) 5220 #define LPSPI_CFGR1_PCSPOL_MASK (0xF00U) 5221 #define LPSPI_CFGR1_PCSPOL_SHIFT (8U) 5222 /*! PCSPOL - Peripheral Chip Select Polarity 5223 * 0b0000..The PCSx is active low. 5224 * 0b0001..The PCSx is active high. 5225 */ 5226 #define LPSPI_CFGR1_PCSPOL(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_PCSPOL_SHIFT)) & LPSPI_CFGR1_PCSPOL_MASK) 5227 #define LPSPI_CFGR1_MATCFG_MASK (0x70000U) 5228 #define LPSPI_CFGR1_MATCFG_SHIFT (16U) 5229 /*! MATCFG - Match Configuration 5230 * 0b000..Match disabled. 5231 * 0b001..Reserved 5232 * 0b010..Match enabled (1st data word equals MATCH0 OR MATCH1). 5233 * 0b011..Match enabled (any data word equals MATCH0 OR MATCH1). 5234 * 0b100..Match enabled (1st data word equals MATCH0 AND 2nd data word equals MATCH1). 5235 * 0b101..Match enabled (any data word equals MATCH0 AND next data word equals MATCH1) 5236 * 0b110..Match enabled (1st data word AND MATCH1 equals MATCH0 AND MATCH1) 5237 * 0b111..Match enabled (any data word AND MATCH1 equals MATCH0 AND MATCH1). 5238 */ 5239 #define LPSPI_CFGR1_MATCFG(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_MATCFG_SHIFT)) & LPSPI_CFGR1_MATCFG_MASK) 5240 #define LPSPI_CFGR1_PINCFG_MASK (0x3000000U) 5241 #define LPSPI_CFGR1_PINCFG_SHIFT (24U) 5242 /*! PINCFG - Pin Configuration 5243 * 0b00..SIN is used for input data and SOUT for output data. 5244 * 0b01..SIN is used for both input and output data. 5245 * 0b10..SOUT is used for both input and output data. 5246 * 0b11..SOUT is used for input data and SIN for output data. 5247 */ 5248 #define LPSPI_CFGR1_PINCFG(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_PINCFG_SHIFT)) & LPSPI_CFGR1_PINCFG_MASK) 5249 #define LPSPI_CFGR1_OUTCFG_MASK (0x4000000U) 5250 #define LPSPI_CFGR1_OUTCFG_SHIFT (26U) 5251 /*! OUTCFG - Output Config 5252 * 0b0..Output data retains last value when chip select is negated. 5253 * 0b1..Output data is tristated when chip select is negated. 5254 */ 5255 #define LPSPI_CFGR1_OUTCFG(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_OUTCFG_SHIFT)) & LPSPI_CFGR1_OUTCFG_MASK) 5256 #define LPSPI_CFGR1_PCSCFG_MASK (0x8000000U) 5257 #define LPSPI_CFGR1_PCSCFG_SHIFT (27U) 5258 /*! PCSCFG - Peripheral Chip Select Configuration 5259 * 0b0..PCS[3:2] are enabled. 5260 * 0b1..PCS[3:2] are disabled. 5261 */ 5262 #define LPSPI_CFGR1_PCSCFG(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_PCSCFG_SHIFT)) & LPSPI_CFGR1_PCSCFG_MASK) 5263 /*! @} */ 5264 5265 /*! @name DMR0 - Data Match Register 0 */ 5266 /*! @{ */ 5267 #define LPSPI_DMR0_MATCH0_MASK (0xFFFFFFFFU) 5268 #define LPSPI_DMR0_MATCH0_SHIFT (0U) 5269 /*! MATCH0 - Match 0 Value 5270 */ 5271 #define LPSPI_DMR0_MATCH0(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_DMR0_MATCH0_SHIFT)) & LPSPI_DMR0_MATCH0_MASK) 5272 /*! @} */ 5273 5274 /*! @name DMR1 - Data Match Register 1 */ 5275 /*! @{ */ 5276 #define LPSPI_DMR1_MATCH1_MASK (0xFFFFFFFFU) 5277 #define LPSPI_DMR1_MATCH1_SHIFT (0U) 5278 /*! MATCH1 - Match 1 Value 5279 */ 5280 #define LPSPI_DMR1_MATCH1(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_DMR1_MATCH1_SHIFT)) & LPSPI_DMR1_MATCH1_MASK) 5281 /*! @} */ 5282 5283 /*! @name CCR - Clock Configuration Register */ 5284 /*! @{ */ 5285 #define LPSPI_CCR_SCKDIV_MASK (0xFFU) 5286 #define LPSPI_CCR_SCKDIV_SHIFT (0U) 5287 /*! SCKDIV - SCK Divider 5288 */ 5289 #define LPSPI_CCR_SCKDIV(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CCR_SCKDIV_SHIFT)) & LPSPI_CCR_SCKDIV_MASK) 5290 #define LPSPI_CCR_DBT_MASK (0xFF00U) 5291 #define LPSPI_CCR_DBT_SHIFT (8U) 5292 /*! DBT - Delay Between Transfers 5293 */ 5294 #define LPSPI_CCR_DBT(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CCR_DBT_SHIFT)) & LPSPI_CCR_DBT_MASK) 5295 #define LPSPI_CCR_PCSSCK_MASK (0xFF0000U) 5296 #define LPSPI_CCR_PCSSCK_SHIFT (16U) 5297 /*! PCSSCK - PCS to SCK Delay 5298 */ 5299 #define LPSPI_CCR_PCSSCK(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CCR_PCSSCK_SHIFT)) & LPSPI_CCR_PCSSCK_MASK) 5300 #define LPSPI_CCR_SCKPCS_MASK (0xFF000000U) 5301 #define LPSPI_CCR_SCKPCS_SHIFT (24U) 5302 /*! SCKPCS - SCK to PCS Delay 5303 */ 5304 #define LPSPI_CCR_SCKPCS(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CCR_SCKPCS_SHIFT)) & LPSPI_CCR_SCKPCS_MASK) 5305 /*! @} */ 5306 5307 /*! @name FCR - FIFO Control Register */ 5308 /*! @{ */ 5309 #define LPSPI_FCR_TXWATER_MASK (0xFFU) 5310 #define LPSPI_FCR_TXWATER_SHIFT (0U) 5311 /*! TXWATER - Transmit FIFO Watermark 5312 */ 5313 #define LPSPI_FCR_TXWATER(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_FCR_TXWATER_SHIFT)) & LPSPI_FCR_TXWATER_MASK) 5314 #define LPSPI_FCR_RXWATER_MASK (0xFF0000U) 5315 #define LPSPI_FCR_RXWATER_SHIFT (16U) 5316 /*! RXWATER - Receive FIFO Watermark 5317 */ 5318 #define LPSPI_FCR_RXWATER(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_FCR_RXWATER_SHIFT)) & LPSPI_FCR_RXWATER_MASK) 5319 /*! @} */ 5320 5321 /*! @name FSR - FIFO Status Register */ 5322 /*! @{ */ 5323 #define LPSPI_FSR_TXCOUNT_MASK (0xFFU) 5324 #define LPSPI_FSR_TXCOUNT_SHIFT (0U) 5325 /*! TXCOUNT - Transmit FIFO Count 5326 */ 5327 #define LPSPI_FSR_TXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_FSR_TXCOUNT_SHIFT)) & LPSPI_FSR_TXCOUNT_MASK) 5328 #define LPSPI_FSR_RXCOUNT_MASK (0xFF0000U) 5329 #define LPSPI_FSR_RXCOUNT_SHIFT (16U) 5330 /*! RXCOUNT - Receive FIFO Count 5331 */ 5332 #define LPSPI_FSR_RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_FSR_RXCOUNT_SHIFT)) & LPSPI_FSR_RXCOUNT_MASK) 5333 /*! @} */ 5334 5335 /*! @name TCR - Transmit Command Register */ 5336 /*! @{ */ 5337 #define LPSPI_TCR_FRAMESZ_MASK (0xFFFU) 5338 #define LPSPI_TCR_FRAMESZ_SHIFT (0U) 5339 /*! FRAMESZ - Frame Size 5340 */ 5341 #define LPSPI_TCR_FRAMESZ(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_FRAMESZ_SHIFT)) & LPSPI_TCR_FRAMESZ_MASK) 5342 #define LPSPI_TCR_WIDTH_MASK (0x30000U) 5343 #define LPSPI_TCR_WIDTH_SHIFT (16U) 5344 /*! WIDTH - Transfer Width 5345 * 0b00..Single bit transfer. 5346 * 0b01..Two bit transfer. 5347 * 0b10..Four bit transfer. 5348 * 0b11..Reserved. 5349 */ 5350 #define LPSPI_TCR_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_WIDTH_SHIFT)) & LPSPI_TCR_WIDTH_MASK) 5351 #define LPSPI_TCR_TXMSK_MASK (0x40000U) 5352 #define LPSPI_TCR_TXMSK_SHIFT (18U) 5353 /*! TXMSK - Transmit Data Mask 5354 * 0b0..Normal transfer. 5355 * 0b1..Mask transmit data. 5356 */ 5357 #define LPSPI_TCR_TXMSK(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_TXMSK_SHIFT)) & LPSPI_TCR_TXMSK_MASK) 5358 #define LPSPI_TCR_RXMSK_MASK (0x80000U) 5359 #define LPSPI_TCR_RXMSK_SHIFT (19U) 5360 /*! RXMSK - Receive Data Mask 5361 * 0b0..Normal transfer. 5362 * 0b1..Receive data is masked. 5363 */ 5364 #define LPSPI_TCR_RXMSK(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_RXMSK_SHIFT)) & LPSPI_TCR_RXMSK_MASK) 5365 #define LPSPI_TCR_CONTC_MASK (0x100000U) 5366 #define LPSPI_TCR_CONTC_SHIFT (20U) 5367 /*! CONTC - Continuing Command 5368 * 0b0..Command word for start of new transfer. 5369 * 0b1..Command word for continuing transfer. 5370 */ 5371 #define LPSPI_TCR_CONTC(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_CONTC_SHIFT)) & LPSPI_TCR_CONTC_MASK) 5372 #define LPSPI_TCR_CONT_MASK (0x200000U) 5373 #define LPSPI_TCR_CONT_SHIFT (21U) 5374 /*! CONT - Continuous Transfer 5375 * 0b0..Continuous transfer disabled. 5376 * 0b1..Continuous transfer enabled. 5377 */ 5378 #define LPSPI_TCR_CONT(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_CONT_SHIFT)) & LPSPI_TCR_CONT_MASK) 5379 #define LPSPI_TCR_BYSW_MASK (0x400000U) 5380 #define LPSPI_TCR_BYSW_SHIFT (22U) 5381 /*! BYSW - Byte Swap 5382 * 0b0..Byte swap disabled. 5383 * 0b1..Byte swap enabled. 5384 */ 5385 #define LPSPI_TCR_BYSW(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_BYSW_SHIFT)) & LPSPI_TCR_BYSW_MASK) 5386 #define LPSPI_TCR_LSBF_MASK (0x800000U) 5387 #define LPSPI_TCR_LSBF_SHIFT (23U) 5388 /*! LSBF - LSB First 5389 * 0b0..Data is transferred MSB first. 5390 * 0b1..Data is transferred LSB first. 5391 */ 5392 #define LPSPI_TCR_LSBF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_LSBF_SHIFT)) & LPSPI_TCR_LSBF_MASK) 5393 #define LPSPI_TCR_PCS_MASK (0x3000000U) 5394 #define LPSPI_TCR_PCS_SHIFT (24U) 5395 /*! PCS - Peripheral Chip Select 5396 * 0b00..Transfer using LPSPI_PCS[0] 5397 * 0b01..Transfer using LPSPI_PCS[1] 5398 * 0b10..Transfer using LPSPI_PCS[2] 5399 * 0b11..Transfer using LPSPI_PCS[3] 5400 */ 5401 #define LPSPI_TCR_PCS(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_PCS_SHIFT)) & LPSPI_TCR_PCS_MASK) 5402 #define LPSPI_TCR_PRESCALE_MASK (0x38000000U) 5403 #define LPSPI_TCR_PRESCALE_SHIFT (27U) 5404 /*! PRESCALE - Prescaler Value 5405 * 0b000..Divide by 1. 5406 * 0b001..Divide by 2. 5407 * 0b010..Divide by 4. 5408 * 0b011..Divide by 8. 5409 * 0b100..Divide by 16. 5410 * 0b101..Divide by 32. 5411 * 0b110..Divide by 64. 5412 * 0b111..Divide by 128. 5413 */ 5414 #define LPSPI_TCR_PRESCALE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_PRESCALE_SHIFT)) & LPSPI_TCR_PRESCALE_MASK) 5415 #define LPSPI_TCR_CPHA_MASK (0x40000000U) 5416 #define LPSPI_TCR_CPHA_SHIFT (30U) 5417 /*! CPHA - Clock Phase 5418 * 0b0..Data is captured on the leading edge of SCK and changed on the following edge. 5419 * 0b1..Data is changed on the leading edge of SCK and captured on the following edge. 5420 */ 5421 #define LPSPI_TCR_CPHA(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_CPHA_SHIFT)) & LPSPI_TCR_CPHA_MASK) 5422 #define LPSPI_TCR_CPOL_MASK (0x80000000U) 5423 #define LPSPI_TCR_CPOL_SHIFT (31U) 5424 /*! CPOL - Clock Polarity 5425 * 0b0..The inactive state value of SCK is low. 5426 * 0b1..The inactive state value of SCK is high. 5427 */ 5428 #define LPSPI_TCR_CPOL(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_CPOL_SHIFT)) & LPSPI_TCR_CPOL_MASK) 5429 /*! @} */ 5430 5431 /*! @name TDR - Transmit Data Register */ 5432 /*! @{ */ 5433 #define LPSPI_TDR_DATA_MASK (0xFFFFFFFFU) 5434 #define LPSPI_TDR_DATA_SHIFT (0U) 5435 /*! DATA - Transmit Data 5436 */ 5437 #define LPSPI_TDR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TDR_DATA_SHIFT)) & LPSPI_TDR_DATA_MASK) 5438 /*! @} */ 5439 5440 /*! @name RSR - Receive Status Register */ 5441 /*! @{ */ 5442 #define LPSPI_RSR_SOF_MASK (0x1U) 5443 #define LPSPI_RSR_SOF_SHIFT (0U) 5444 /*! SOF - Start Of Frame 5445 * 0b0..Subsequent data word received after LPSPI_PCS assertion. 5446 * 0b1..First data word received after LPSPI_PCS assertion. 5447 */ 5448 #define LPSPI_RSR_SOF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_RSR_SOF_SHIFT)) & LPSPI_RSR_SOF_MASK) 5449 #define LPSPI_RSR_RXEMPTY_MASK (0x2U) 5450 #define LPSPI_RSR_RXEMPTY_SHIFT (1U) 5451 /*! RXEMPTY - RX FIFO Empty 5452 * 0b0..RX FIFO is not empty. 5453 * 0b1..RX FIFO is empty. 5454 */ 5455 #define LPSPI_RSR_RXEMPTY(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_RSR_RXEMPTY_SHIFT)) & LPSPI_RSR_RXEMPTY_MASK) 5456 /*! @} */ 5457 5458 /*! @name RDR - Receive Data Register */ 5459 /*! @{ */ 5460 #define LPSPI_RDR_DATA_MASK (0xFFFFFFFFU) 5461 #define LPSPI_RDR_DATA_SHIFT (0U) 5462 /*! DATA - Receive Data 5463 */ 5464 #define LPSPI_RDR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_RDR_DATA_SHIFT)) & LPSPI_RDR_DATA_MASK) 5465 /*! @} */ 5466 5467 5468 /*! 5469 * @} 5470 */ /* end of group LPSPI_Register_Masks */ 5471 5472 5473 /* LPSPI - Peripheral instance base addresses */ 5474 /** Peripheral LPSPI0 base address */ 5475 #define LPSPI0_BASE (0x4002C000u) 5476 /** Peripheral LPSPI0 base pointer */ 5477 #define LPSPI0 ((LPSPI_Type *)LPSPI0_BASE) 5478 /** Array initializer of LPSPI peripheral base addresses */ 5479 #define LPSPI_BASE_ADDRS { LPSPI0_BASE } 5480 /** Array initializer of LPSPI peripheral base pointers */ 5481 #define LPSPI_BASE_PTRS { LPSPI0 } 5482 /** Interrupt vectors for the LPSPI peripheral type */ 5483 #define LPSPI_IRQS { LPSPI0_IRQn } 5484 5485 /*! 5486 * @} 5487 */ /* end of group LPSPI_Peripheral_Access_Layer */ 5488 5489 5490 /* ---------------------------------------------------------------------------- 5491 -- LPTMR Peripheral Access Layer 5492 ---------------------------------------------------------------------------- */ 5493 5494 /*! 5495 * @addtogroup LPTMR_Peripheral_Access_Layer LPTMR Peripheral Access Layer 5496 * @{ 5497 */ 5498 5499 /** LPTMR - Register Layout Typedef */ 5500 typedef struct { 5501 __IO uint32_t CSR; /**< Low Power Timer Control Status Register, offset: 0x0 */ 5502 __IO uint32_t PSR; /**< Low Power Timer Prescale Register, offset: 0x4 */ 5503 __IO uint32_t CMR; /**< Low Power Timer Compare Register, offset: 0x8 */ 5504 __IO uint32_t CNR; /**< Low Power Timer Counter Register, offset: 0xC */ 5505 } LPTMR_Type; 5506 5507 /* ---------------------------------------------------------------------------- 5508 -- LPTMR Register Masks 5509 ---------------------------------------------------------------------------- */ 5510 5511 /*! 5512 * @addtogroup LPTMR_Register_Masks LPTMR Register Masks 5513 * @{ 5514 */ 5515 5516 /*! @name CSR - Low Power Timer Control Status Register */ 5517 /*! @{ */ 5518 #define LPTMR_CSR_TEN_MASK (0x1U) 5519 #define LPTMR_CSR_TEN_SHIFT (0U) 5520 /*! TEN - Timer Enable 5521 * 0b0..LPTMR is disabled and internal logic is reset. 5522 * 0b1..LPTMR is enabled. 5523 */ 5524 #define LPTMR_CSR_TEN(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TEN_SHIFT)) & LPTMR_CSR_TEN_MASK) 5525 #define LPTMR_CSR_TMS_MASK (0x2U) 5526 #define LPTMR_CSR_TMS_SHIFT (1U) 5527 /*! TMS - Timer Mode Select 5528 * 0b0..Time Counter mode. 5529 * 0b1..Pulse Counter mode. 5530 */ 5531 #define LPTMR_CSR_TMS(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TMS_SHIFT)) & LPTMR_CSR_TMS_MASK) 5532 #define LPTMR_CSR_TFC_MASK (0x4U) 5533 #define LPTMR_CSR_TFC_SHIFT (2U) 5534 /*! TFC - Timer Free-Running Counter 5535 * 0b0..CNR is reset whenever TCF is set. 5536 * 0b1..CNR is reset on overflow. 5537 */ 5538 #define LPTMR_CSR_TFC(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TFC_SHIFT)) & LPTMR_CSR_TFC_MASK) 5539 #define LPTMR_CSR_TPP_MASK (0x8U) 5540 #define LPTMR_CSR_TPP_SHIFT (3U) 5541 /*! TPP - Timer Pin Polarity 5542 * 0b0..Pulse Counter input source is active-high, and the CNR will increment on the rising-edge. 5543 * 0b1..Pulse Counter input source is active-low, and the CNR will increment on the falling-edge. 5544 */ 5545 #define LPTMR_CSR_TPP(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TPP_SHIFT)) & LPTMR_CSR_TPP_MASK) 5546 #define LPTMR_CSR_TPS_MASK (0x30U) 5547 #define LPTMR_CSR_TPS_SHIFT (4U) 5548 /*! TPS - Timer Pin Select 5549 * 0b00..Pulse counter input 0 is selected. 5550 * 0b01..Pulse counter input 1 is selected. 5551 * 0b10..Pulse counter input 2 is selected. 5552 * 0b11..Pulse counter input 3 is selected. 5553 */ 5554 #define LPTMR_CSR_TPS(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TPS_SHIFT)) & LPTMR_CSR_TPS_MASK) 5555 #define LPTMR_CSR_TIE_MASK (0x40U) 5556 #define LPTMR_CSR_TIE_SHIFT (6U) 5557 /*! TIE - Timer Interrupt Enable 5558 * 0b0..Timer interrupt disabled. 5559 * 0b1..Timer interrupt enabled. 5560 */ 5561 #define LPTMR_CSR_TIE(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TIE_SHIFT)) & LPTMR_CSR_TIE_MASK) 5562 #define LPTMR_CSR_TCF_MASK (0x80U) 5563 #define LPTMR_CSR_TCF_SHIFT (7U) 5564 /*! TCF - Timer Compare Flag 5565 * 0b0..The value of CNR is not equal to CMR and increments. 5566 * 0b1..The value of CNR is equal to CMR and increments. 5567 */ 5568 #define LPTMR_CSR_TCF(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TCF_SHIFT)) & LPTMR_CSR_TCF_MASK) 5569 #define LPTMR_CSR_TDRE_MASK (0x100U) 5570 #define LPTMR_CSR_TDRE_SHIFT (8U) 5571 /*! TDRE - Timer DMA Request Enable 5572 * 0b0..Timer DMA Request disabled. 5573 * 0b1..Timer DMA Request enabled. 5574 */ 5575 #define LPTMR_CSR_TDRE(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TDRE_SHIFT)) & LPTMR_CSR_TDRE_MASK) 5576 /*! @} */ 5577 5578 /*! @name PSR - Low Power Timer Prescale Register */ 5579 /*! @{ */ 5580 #define LPTMR_PSR_PCS_MASK (0x3U) 5581 #define LPTMR_PSR_PCS_SHIFT (0U) 5582 /*! PCS - Prescaler Clock Select 5583 * 0b00..Prescaler/glitch filter clock 0 selected. 5584 * 0b01..Prescaler/glitch filter clock 1 selected. 5585 * 0b10..Prescaler/glitch filter clock 2 selected. 5586 * 0b11..Prescaler/glitch filter clock 3 selected. 5587 */ 5588 #define LPTMR_PSR_PCS(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_PSR_PCS_SHIFT)) & LPTMR_PSR_PCS_MASK) 5589 #define LPTMR_PSR_PBYP_MASK (0x4U) 5590 #define LPTMR_PSR_PBYP_SHIFT (2U) 5591 /*! PBYP - Prescaler Bypass 5592 * 0b0..Prescaler/glitch filter is enabled. 5593 * 0b1..Prescaler/glitch filter is bypassed. 5594 */ 5595 #define LPTMR_PSR_PBYP(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_PSR_PBYP_SHIFT)) & LPTMR_PSR_PBYP_MASK) 5596 #define LPTMR_PSR_PRESCALE_MASK (0x78U) 5597 #define LPTMR_PSR_PRESCALE_SHIFT (3U) 5598 /*! PRESCALE - Prescale Value 5599 * 0b0000..Prescaler divides the prescaler clock by 2; glitch filter does not support this configuration. 5600 * 0b0001..Prescaler divides the prescaler clock by 4; glitch filter recognizes change on input pin after 2 rising clock edges. 5601 * 0b0010..Prescaler divides the prescaler clock by 8; glitch filter recognizes change on input pin after 4 rising clock edges. 5602 * 0b0011..Prescaler divides the prescaler clock by 16; glitch filter recognizes change on input pin after 8 rising clock edges. 5603 * 0b0100..Prescaler divides the prescaler clock by 32; glitch filter recognizes change on input pin after 16 rising clock edges. 5604 * 0b0101..Prescaler divides the prescaler clock by 64; glitch filter recognizes change on input pin after 32 rising clock edges. 5605 * 0b0110..Prescaler divides the prescaler clock by 128; glitch filter recognizes change on input pin after 64 rising clock edges. 5606 * 0b0111..Prescaler divides the prescaler clock by 256; glitch filter recognizes change on input pin after 128 rising clock edges. 5607 * 0b1000..Prescaler divides the prescaler clock by 512; glitch filter recognizes change on input pin after 256 rising clock edges. 5608 * 0b1001..Prescaler divides the prescaler clock by 1024; glitch filter recognizes change on input pin after 512 rising clock edges. 5609 * 0b1010..Prescaler divides the prescaler clock by 2048; glitch filter recognizes change on input pin after 1024 rising clock edges. 5610 * 0b1011..Prescaler divides the prescaler clock by 4096; glitch filter recognizes change on input pin after 2048 rising clock edges. 5611 * 0b1100..Prescaler divides the prescaler clock by 8192; glitch filter recognizes change on input pin after 4096 rising clock edges. 5612 * 0b1101..Prescaler divides the prescaler clock by 16,384; glitch filter recognizes change on input pin after 8192 rising clock edges. 5613 * 0b1110..Prescaler divides the prescaler clock by 32,768; glitch filter recognizes change on input pin after 16,384 rising clock edges. 5614 * 0b1111..Prescaler divides the prescaler clock by 65,536; glitch filter recognizes change on input pin after 32,768 rising clock edges. 5615 */ 5616 #define LPTMR_PSR_PRESCALE(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_PSR_PRESCALE_SHIFT)) & LPTMR_PSR_PRESCALE_MASK) 5617 /*! @} */ 5618 5619 /*! @name CMR - Low Power Timer Compare Register */ 5620 /*! @{ */ 5621 #define LPTMR_CMR_COMPARE_MASK (0xFFFFU) 5622 #define LPTMR_CMR_COMPARE_SHIFT (0U) 5623 /*! COMPARE - Compare Value 5624 */ 5625 #define LPTMR_CMR_COMPARE(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CMR_COMPARE_SHIFT)) & LPTMR_CMR_COMPARE_MASK) 5626 /*! @} */ 5627 5628 /*! @name CNR - Low Power Timer Counter Register */ 5629 /*! @{ */ 5630 #define LPTMR_CNR_COUNTER_MASK (0xFFFFU) 5631 #define LPTMR_CNR_COUNTER_SHIFT (0U) 5632 /*! COUNTER - Counter Value 5633 */ 5634 #define LPTMR_CNR_COUNTER(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CNR_COUNTER_SHIFT)) & LPTMR_CNR_COUNTER_MASK) 5635 /*! @} */ 5636 5637 5638 /*! 5639 * @} 5640 */ /* end of group LPTMR_Register_Masks */ 5641 5642 5643 /* LPTMR - Peripheral instance base addresses */ 5644 /** Peripheral LPTMR0 base address */ 5645 #define LPTMR0_BASE (0x40040000u) 5646 /** Peripheral LPTMR0 base pointer */ 5647 #define LPTMR0 ((LPTMR_Type *)LPTMR0_BASE) 5648 /** Array initializer of LPTMR peripheral base addresses */ 5649 #define LPTMR_BASE_ADDRS { LPTMR0_BASE } 5650 /** Array initializer of LPTMR peripheral base pointers */ 5651 #define LPTMR_BASE_PTRS { LPTMR0 } 5652 /** Interrupt vectors for the LPTMR peripheral type */ 5653 #define LPTMR_IRQS { PWT_LPTMR0_IRQn } 5654 5655 /*! 5656 * @} 5657 */ /* end of group LPTMR_Peripheral_Access_Layer */ 5658 5659 5660 /* ---------------------------------------------------------------------------- 5661 -- LPUART Peripheral Access Layer 5662 ---------------------------------------------------------------------------- */ 5663 5664 /*! 5665 * @addtogroup LPUART_Peripheral_Access_Layer LPUART Peripheral Access Layer 5666 * @{ 5667 */ 5668 5669 /** LPUART - Register Layout Typedef */ 5670 typedef struct { 5671 __I uint32_t VERID; /**< Version ID Register, offset: 0x0 */ 5672 __I uint32_t PARAM; /**< Parameter Register, offset: 0x4 */ 5673 __IO uint32_t GLOBAL; /**< LPUART Global Register, offset: 0x8 */ 5674 __IO uint32_t PINCFG; /**< LPUART Pin Configuration Register, offset: 0xC */ 5675 __IO uint32_t BAUD; /**< LPUART Baud Rate Register, offset: 0x10 */ 5676 __IO uint32_t STAT; /**< LPUART Status Register, offset: 0x14 */ 5677 __IO uint32_t CTRL; /**< LPUART Control Register, offset: 0x18 */ 5678 __IO uint32_t DATA; /**< LPUART Data Register, offset: 0x1C */ 5679 __IO uint32_t MATCH; /**< LPUART Match Address Register, offset: 0x20 */ 5680 __IO uint32_t MODIR; /**< LPUART Modem IrDA Register, offset: 0x24 */ 5681 __IO uint32_t FIFO; /**< LPUART FIFO Register, offset: 0x28 */ 5682 __IO uint32_t WATER; /**< LPUART Watermark Register, offset: 0x2C */ 5683 } LPUART_Type; 5684 5685 /* ---------------------------------------------------------------------------- 5686 -- LPUART Register Masks 5687 ---------------------------------------------------------------------------- */ 5688 5689 /*! 5690 * @addtogroup LPUART_Register_Masks LPUART Register Masks 5691 * @{ 5692 */ 5693 5694 /*! @name VERID - Version ID Register */ 5695 /*! @{ */ 5696 #define LPUART_VERID_FEATURE_MASK (0xFFFFU) 5697 #define LPUART_VERID_FEATURE_SHIFT (0U) 5698 /*! FEATURE - Feature Identification Number 5699 * 0b0000000000000001..Standard feature set. 5700 * 0b0000000000000011..Standard feature set with MODEM/IrDA support. 5701 */ 5702 #define LPUART_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_VERID_FEATURE_SHIFT)) & LPUART_VERID_FEATURE_MASK) 5703 #define LPUART_VERID_MINOR_MASK (0xFF0000U) 5704 #define LPUART_VERID_MINOR_SHIFT (16U) 5705 /*! MINOR - Minor Version Number 5706 */ 5707 #define LPUART_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_VERID_MINOR_SHIFT)) & LPUART_VERID_MINOR_MASK) 5708 #define LPUART_VERID_MAJOR_MASK (0xFF000000U) 5709 #define LPUART_VERID_MAJOR_SHIFT (24U) 5710 /*! MAJOR - Major Version Number 5711 */ 5712 #define LPUART_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_VERID_MAJOR_SHIFT)) & LPUART_VERID_MAJOR_MASK) 5713 /*! @} */ 5714 5715 /*! @name PARAM - Parameter Register */ 5716 /*! @{ */ 5717 #define LPUART_PARAM_TXFIFO_MASK (0xFFU) 5718 #define LPUART_PARAM_TXFIFO_SHIFT (0U) 5719 /*! TXFIFO - Transmit FIFO Size 5720 */ 5721 #define LPUART_PARAM_TXFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPUART_PARAM_TXFIFO_SHIFT)) & LPUART_PARAM_TXFIFO_MASK) 5722 #define LPUART_PARAM_RXFIFO_MASK (0xFF00U) 5723 #define LPUART_PARAM_RXFIFO_SHIFT (8U) 5724 /*! RXFIFO - Receive FIFO Size 5725 */ 5726 #define LPUART_PARAM_RXFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPUART_PARAM_RXFIFO_SHIFT)) & LPUART_PARAM_RXFIFO_MASK) 5727 /*! @} */ 5728 5729 /*! @name GLOBAL - LPUART Global Register */ 5730 /*! @{ */ 5731 #define LPUART_GLOBAL_RST_MASK (0x2U) 5732 #define LPUART_GLOBAL_RST_SHIFT (1U) 5733 /*! RST - Software Reset 5734 * 0b0..Module is not reset. 5735 * 0b1..Module is reset. 5736 */ 5737 #define LPUART_GLOBAL_RST(x) (((uint32_t)(((uint32_t)(x)) << LPUART_GLOBAL_RST_SHIFT)) & LPUART_GLOBAL_RST_MASK) 5738 /*! @} */ 5739 5740 /*! @name PINCFG - LPUART Pin Configuration Register */ 5741 /*! @{ */ 5742 #define LPUART_PINCFG_TRGSEL_MASK (0x3U) 5743 #define LPUART_PINCFG_TRGSEL_SHIFT (0U) 5744 /*! TRGSEL - Trigger Select 5745 * 0b00..Input trigger is disabled. 5746 * 0b01..Input trigger is used instead of RXD pin input. 5747 * 0b10..Input trigger is used instead of CTS_B pin input. 5748 * 0b11..Input trigger is used to modulate the TXD pin output. The TXD pin output (after TXINV configuration) is ANDed with the input trigger. 5749 */ 5750 #define LPUART_PINCFG_TRGSEL(x) (((uint32_t)(((uint32_t)(x)) << LPUART_PINCFG_TRGSEL_SHIFT)) & LPUART_PINCFG_TRGSEL_MASK) 5751 /*! @} */ 5752 5753 /*! @name BAUD - LPUART Baud Rate Register */ 5754 /*! @{ */ 5755 #define LPUART_BAUD_SBR_MASK (0x1FFFU) 5756 #define LPUART_BAUD_SBR_SHIFT (0U) 5757 /*! SBR - Baud Rate Modulo Divisor. 5758 */ 5759 #define LPUART_BAUD_SBR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_SBR_SHIFT)) & LPUART_BAUD_SBR_MASK) 5760 #define LPUART_BAUD_SBNS_MASK (0x2000U) 5761 #define LPUART_BAUD_SBNS_SHIFT (13U) 5762 /*! SBNS - Stop Bit Number Select 5763 * 0b0..One stop bit. 5764 * 0b1..Two stop bits. 5765 */ 5766 #define LPUART_BAUD_SBNS(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_SBNS_SHIFT)) & LPUART_BAUD_SBNS_MASK) 5767 #define LPUART_BAUD_RXEDGIE_MASK (0x4000U) 5768 #define LPUART_BAUD_RXEDGIE_SHIFT (14U) 5769 /*! RXEDGIE - RX Input Active Edge Interrupt Enable 5770 * 0b0..Hardware interrupts from STAT[RXEDGIF] are disabled. 5771 * 0b1..Hardware interrupt is requested when STAT[RXEDGIF] flag is 1. 5772 */ 5773 #define LPUART_BAUD_RXEDGIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_RXEDGIE_SHIFT)) & LPUART_BAUD_RXEDGIE_MASK) 5774 #define LPUART_BAUD_LBKDIE_MASK (0x8000U) 5775 #define LPUART_BAUD_LBKDIE_SHIFT (15U) 5776 /*! LBKDIE - LIN Break Detect Interrupt Enable 5777 * 0b0..Hardware interrupts from STAT[LBKDIF] flag are disabled (use polling). 5778 * 0b1..Hardware interrupt requested when STAT[LBKDIF] flag is 1. 5779 */ 5780 #define LPUART_BAUD_LBKDIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_LBKDIE_SHIFT)) & LPUART_BAUD_LBKDIE_MASK) 5781 #define LPUART_BAUD_RESYNCDIS_MASK (0x10000U) 5782 #define LPUART_BAUD_RESYNCDIS_SHIFT (16U) 5783 /*! RESYNCDIS - Resynchronization Disable 5784 * 0b0..Resynchronization during received data word is supported 5785 * 0b1..Resynchronization during received data word is disabled 5786 */ 5787 #define LPUART_BAUD_RESYNCDIS(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_RESYNCDIS_SHIFT)) & LPUART_BAUD_RESYNCDIS_MASK) 5788 #define LPUART_BAUD_BOTHEDGE_MASK (0x20000U) 5789 #define LPUART_BAUD_BOTHEDGE_SHIFT (17U) 5790 /*! BOTHEDGE - Both Edge Sampling 5791 * 0b0..Receiver samples input data using the rising edge of the baud rate clock. 5792 * 0b1..Receiver samples input data using the rising and falling edge of the baud rate clock. 5793 */ 5794 #define LPUART_BAUD_BOTHEDGE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_BOTHEDGE_SHIFT)) & LPUART_BAUD_BOTHEDGE_MASK) 5795 #define LPUART_BAUD_MATCFG_MASK (0xC0000U) 5796 #define LPUART_BAUD_MATCFG_SHIFT (18U) 5797 /*! MATCFG - Match Configuration 5798 * 0b00..Address Match Wakeup 5799 * 0b01..Idle Match Wakeup 5800 * 0b10..Match On and Match Off 5801 * 0b11..Enables RWU on Data Match and Match On/Off for transmitter CTS input 5802 */ 5803 #define LPUART_BAUD_MATCFG(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_MATCFG_SHIFT)) & LPUART_BAUD_MATCFG_MASK) 5804 #define LPUART_BAUD_OSR_MASK (0x1F000000U) 5805 #define LPUART_BAUD_OSR_SHIFT (24U) 5806 /*! OSR - Oversampling Ratio 5807 * 0b00000..Writing 0 to this field will result in an oversampling ratio of 16 5808 * 0b00001..Reserved 5809 * 0b00010..Reserved 5810 * 0b00011..Oversampling ratio of 4, requires BOTHEDGE to be set. 5811 * 0b00100..Oversampling ratio of 5, requires BOTHEDGE to be set. 5812 * 0b00101..Oversampling ratio of 6, requires BOTHEDGE to be set. 5813 * 0b00110..Oversampling ratio of 7, requires BOTHEDGE to be set. 5814 * 0b00111..Oversampling ratio of 8. 5815 * 0b01000..Oversampling ratio of 9. 5816 * 0b01001..Oversampling ratio of 10. 5817 * 0b01010..Oversampling ratio of 11. 5818 * 0b01011..Oversampling ratio of 12. 5819 * 0b01100..Oversampling ratio of 13. 5820 * 0b01101..Oversampling ratio of 14. 5821 * 0b01110..Oversampling ratio of 15. 5822 * 0b01111..Oversampling ratio of 16. 5823 * 0b10000..Oversampling ratio of 17. 5824 * 0b10001..Oversampling ratio of 18. 5825 * 0b10010..Oversampling ratio of 19. 5826 * 0b10011..Oversampling ratio of 20. 5827 * 0b10100..Oversampling ratio of 21. 5828 * 0b10101..Oversampling ratio of 22. 5829 * 0b10110..Oversampling ratio of 23. 5830 * 0b10111..Oversampling ratio of 24. 5831 * 0b11000..Oversampling ratio of 25. 5832 * 0b11001..Oversampling ratio of 26. 5833 * 0b11010..Oversampling ratio of 27. 5834 * 0b11011..Oversampling ratio of 28. 5835 * 0b11100..Oversampling ratio of 29. 5836 * 0b11101..Oversampling ratio of 30. 5837 * 0b11110..Oversampling ratio of 31. 5838 * 0b11111..Oversampling ratio of 32. 5839 */ 5840 #define LPUART_BAUD_OSR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_OSR_SHIFT)) & LPUART_BAUD_OSR_MASK) 5841 #define LPUART_BAUD_M10_MASK (0x20000000U) 5842 #define LPUART_BAUD_M10_SHIFT (29U) 5843 /*! M10 - 10-bit Mode select 5844 * 0b0..Receiver and transmitter use 7-bit to 9-bit data characters. 5845 * 0b1..Receiver and transmitter use 10-bit data characters. 5846 */ 5847 #define LPUART_BAUD_M10(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_M10_SHIFT)) & LPUART_BAUD_M10_MASK) 5848 #define LPUART_BAUD_MAEN2_MASK (0x40000000U) 5849 #define LPUART_BAUD_MAEN2_SHIFT (30U) 5850 /*! MAEN2 - Match Address Mode Enable 2 5851 * 0b0..Normal operation. 5852 * 0b1..Enables automatic address matching or data matching mode for MATCH[MA2]. 5853 */ 5854 #define LPUART_BAUD_MAEN2(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_MAEN2_SHIFT)) & LPUART_BAUD_MAEN2_MASK) 5855 #define LPUART_BAUD_MAEN1_MASK (0x80000000U) 5856 #define LPUART_BAUD_MAEN1_SHIFT (31U) 5857 /*! MAEN1 - Match Address Mode Enable 1 5858 * 0b0..Normal operation. 5859 * 0b1..Enables automatic address matching or data matching mode for MATCH[MA1]. 5860 */ 5861 #define LPUART_BAUD_MAEN1(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_MAEN1_SHIFT)) & LPUART_BAUD_MAEN1_MASK) 5862 /*! @} */ 5863 5864 /*! @name STAT - LPUART Status Register */ 5865 /*! @{ */ 5866 #define LPUART_STAT_MA2F_MASK (0x4000U) 5867 #define LPUART_STAT_MA2F_SHIFT (14U) 5868 /*! MA2F - Match 2 Flag 5869 * 0b0..Received data is not equal to MA2 5870 * 0b1..Received data is equal to MA2 5871 */ 5872 #define LPUART_STAT_MA2F(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_MA2F_SHIFT)) & LPUART_STAT_MA2F_MASK) 5873 #define LPUART_STAT_MA1F_MASK (0x8000U) 5874 #define LPUART_STAT_MA1F_SHIFT (15U) 5875 /*! MA1F - Match 1 Flag 5876 * 0b0..Received data is not equal to MA1 5877 * 0b1..Received data is equal to MA1 5878 */ 5879 #define LPUART_STAT_MA1F(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_MA1F_SHIFT)) & LPUART_STAT_MA1F_MASK) 5880 #define LPUART_STAT_PF_MASK (0x10000U) 5881 #define LPUART_STAT_PF_SHIFT (16U) 5882 /*! PF - Parity Error Flag 5883 * 0b0..No parity error. 5884 * 0b1..Parity error. 5885 */ 5886 #define LPUART_STAT_PF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_PF_SHIFT)) & LPUART_STAT_PF_MASK) 5887 #define LPUART_STAT_FE_MASK (0x20000U) 5888 #define LPUART_STAT_FE_SHIFT (17U) 5889 /*! FE - Framing Error Flag 5890 * 0b0..No framing error detected. This does not guarantee the framing is correct. 5891 * 0b1..Framing error. 5892 */ 5893 #define LPUART_STAT_FE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_FE_SHIFT)) & LPUART_STAT_FE_MASK) 5894 #define LPUART_STAT_NF_MASK (0x40000U) 5895 #define LPUART_STAT_NF_SHIFT (18U) 5896 /*! NF - Noise Flag 5897 * 0b0..No noise detected. 5898 * 0b1..Noise detected in the received character in the DATA register. 5899 */ 5900 #define LPUART_STAT_NF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_NF_SHIFT)) & LPUART_STAT_NF_MASK) 5901 #define LPUART_STAT_OR_MASK (0x80000U) 5902 #define LPUART_STAT_OR_SHIFT (19U) 5903 /*! OR - Receiver Overrun Flag 5904 * 0b0..No overrun. 5905 * 0b1..Receive overrun (new LPUART data lost). 5906 */ 5907 #define LPUART_STAT_OR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_OR_SHIFT)) & LPUART_STAT_OR_MASK) 5908 #define LPUART_STAT_IDLE_MASK (0x100000U) 5909 #define LPUART_STAT_IDLE_SHIFT (20U) 5910 /*! IDLE - Idle Line Flag 5911 * 0b0..No idle line detected. 5912 * 0b1..Idle line was detected. 5913 */ 5914 #define LPUART_STAT_IDLE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_IDLE_SHIFT)) & LPUART_STAT_IDLE_MASK) 5915 #define LPUART_STAT_RDRF_MASK (0x200000U) 5916 #define LPUART_STAT_RDRF_SHIFT (21U) 5917 /*! RDRF - Receive Data Register Full Flag 5918 * 0b0..Receive data buffer empty. 5919 * 0b1..Receive data buffer full. 5920 */ 5921 #define LPUART_STAT_RDRF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RDRF_SHIFT)) & LPUART_STAT_RDRF_MASK) 5922 #define LPUART_STAT_TC_MASK (0x400000U) 5923 #define LPUART_STAT_TC_SHIFT (22U) 5924 /*! TC - Transmission Complete Flag 5925 * 0b0..Transmitter active (sending data, a preamble, or a break). 5926 * 0b1..Transmitter idle (transmission activity complete). 5927 */ 5928 #define LPUART_STAT_TC(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_TC_SHIFT)) & LPUART_STAT_TC_MASK) 5929 #define LPUART_STAT_TDRE_MASK (0x800000U) 5930 #define LPUART_STAT_TDRE_SHIFT (23U) 5931 /*! TDRE - Transmit Data Register Empty Flag 5932 * 0b0..Transmit data buffer full. 5933 * 0b1..Transmit data buffer empty. 5934 */ 5935 #define LPUART_STAT_TDRE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_TDRE_SHIFT)) & LPUART_STAT_TDRE_MASK) 5936 #define LPUART_STAT_RAF_MASK (0x1000000U) 5937 #define LPUART_STAT_RAF_SHIFT (24U) 5938 /*! RAF - Receiver Active Flag 5939 * 0b0..LPUART receiver idle waiting for a start bit. 5940 * 0b1..LPUART receiver active (RXD input not idle). 5941 */ 5942 #define LPUART_STAT_RAF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RAF_SHIFT)) & LPUART_STAT_RAF_MASK) 5943 #define LPUART_STAT_LBKDE_MASK (0x2000000U) 5944 #define LPUART_STAT_LBKDE_SHIFT (25U) 5945 /*! LBKDE - LIN Break Detection Enable 5946 * 0b0..LIN break detect is disabled, normal break character can be detected. 5947 * 0b1..LIN break detect is enabled. LIN break character is detected at length of 11 bit times (if M = 0) or 12 (if M = 1) or 13 (M10 = 1). 5948 */ 5949 #define LPUART_STAT_LBKDE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_LBKDE_SHIFT)) & LPUART_STAT_LBKDE_MASK) 5950 #define LPUART_STAT_BRK13_MASK (0x4000000U) 5951 #define LPUART_STAT_BRK13_SHIFT (26U) 5952 /*! BRK13 - Break Character Generation Length 5953 * 0b0..Break character is transmitted with length of 9 to 13 bit times. 5954 * 0b1..Break character is transmitted with length of 12 to 15 bit times. 5955 */ 5956 #define LPUART_STAT_BRK13(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_BRK13_SHIFT)) & LPUART_STAT_BRK13_MASK) 5957 #define LPUART_STAT_RWUID_MASK (0x8000000U) 5958 #define LPUART_STAT_RWUID_SHIFT (27U) 5959 /*! RWUID - Receive Wake Up Idle Detect 5960 * 0b0..During receive standby state (RWU = 1), the IDLE bit does not get set upon detection of an idle 5961 * character. During address match wakeup, the IDLE bit does not set when an address does not match. 5962 * 0b1..During receive standby state (RWU = 1), the IDLE bit gets set upon detection of an idle character. During 5963 * address match wakeup, the IDLE bit does set when an address does not match. 5964 */ 5965 #define LPUART_STAT_RWUID(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RWUID_SHIFT)) & LPUART_STAT_RWUID_MASK) 5966 #define LPUART_STAT_RXINV_MASK (0x10000000U) 5967 #define LPUART_STAT_RXINV_SHIFT (28U) 5968 /*! RXINV - Receive Data Inversion 5969 * 0b0..Receive data not inverted. 5970 * 0b1..Receive data inverted. 5971 */ 5972 #define LPUART_STAT_RXINV(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RXINV_SHIFT)) & LPUART_STAT_RXINV_MASK) 5973 #define LPUART_STAT_MSBF_MASK (0x20000000U) 5974 #define LPUART_STAT_MSBF_SHIFT (29U) 5975 /*! MSBF - MSB First 5976 * 0b0..LSB (bit0) is the first bit that is transmitted following the start bit. Further, the first bit received 5977 * after the start bit is identified as bit0. 5978 * 0b1..MSB (bit9, bit8, bit7 or bit6) is the first bit that is transmitted following the start bit depending on 5979 * the setting of CTRL[M], CTRL[PE] and BAUD[M10]. Further, the first bit received after the start bit is 5980 * identified as bit9, bit8, bit7 or bit6 depending on the setting of CTRL[M] and CTRL[PE]. 5981 */ 5982 #define LPUART_STAT_MSBF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_MSBF_SHIFT)) & LPUART_STAT_MSBF_MASK) 5983 #define LPUART_STAT_RXEDGIF_MASK (0x40000000U) 5984 #define LPUART_STAT_RXEDGIF_SHIFT (30U) 5985 /*! RXEDGIF - RXD Pin Active Edge Interrupt Flag 5986 * 0b0..No active edge on the receive pin has occurred. 5987 * 0b1..An active edge on the receive pin has occurred. 5988 */ 5989 #define LPUART_STAT_RXEDGIF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RXEDGIF_SHIFT)) & LPUART_STAT_RXEDGIF_MASK) 5990 #define LPUART_STAT_LBKDIF_MASK (0x80000000U) 5991 #define LPUART_STAT_LBKDIF_SHIFT (31U) 5992 /*! LBKDIF - LIN Break Detect Interrupt Flag 5993 * 0b0..No LIN break character has been detected. 5994 * 0b1..LIN break character has been detected. 5995 */ 5996 #define LPUART_STAT_LBKDIF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_LBKDIF_SHIFT)) & LPUART_STAT_LBKDIF_MASK) 5997 /*! @} */ 5998 5999 /*! @name CTRL - LPUART Control Register */ 6000 /*! @{ */ 6001 #define LPUART_CTRL_PT_MASK (0x1U) 6002 #define LPUART_CTRL_PT_SHIFT (0U) 6003 /*! PT - Parity Type 6004 * 0b0..Even parity. 6005 * 0b1..Odd parity. 6006 */ 6007 #define LPUART_CTRL_PT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_PT_SHIFT)) & LPUART_CTRL_PT_MASK) 6008 #define LPUART_CTRL_PE_MASK (0x2U) 6009 #define LPUART_CTRL_PE_SHIFT (1U) 6010 /*! PE - Parity Enable 6011 * 0b0..No hardware parity generation or checking. 6012 * 0b1..Parity enabled. 6013 */ 6014 #define LPUART_CTRL_PE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_PE_SHIFT)) & LPUART_CTRL_PE_MASK) 6015 #define LPUART_CTRL_ILT_MASK (0x4U) 6016 #define LPUART_CTRL_ILT_SHIFT (2U) 6017 /*! ILT - Idle Line Type Select 6018 * 0b0..Idle character bit count starts after start bit. 6019 * 0b1..Idle character bit count starts after stop bit. 6020 */ 6021 #define LPUART_CTRL_ILT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_ILT_SHIFT)) & LPUART_CTRL_ILT_MASK) 6022 #define LPUART_CTRL_WAKE_MASK (0x8U) 6023 #define LPUART_CTRL_WAKE_SHIFT (3U) 6024 /*! WAKE - Receiver Wakeup Method Select 6025 * 0b0..Configures RWU for idle-line wakeup. 6026 * 0b1..Configures RWU with address-mark wakeup. 6027 */ 6028 #define LPUART_CTRL_WAKE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_WAKE_SHIFT)) & LPUART_CTRL_WAKE_MASK) 6029 #define LPUART_CTRL_M_MASK (0x10U) 6030 #define LPUART_CTRL_M_SHIFT (4U) 6031 /*! M - 9-Bit or 8-Bit Mode Select 6032 * 0b0..Receiver and transmitter use 8-bit data characters. 6033 * 0b1..Receiver and transmitter use 9-bit data characters. 6034 */ 6035 #define LPUART_CTRL_M(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_M_SHIFT)) & LPUART_CTRL_M_MASK) 6036 #define LPUART_CTRL_RSRC_MASK (0x20U) 6037 #define LPUART_CTRL_RSRC_SHIFT (5U) 6038 /*! RSRC - Receiver Source Select 6039 * 0b0..Provided LOOPS is set, RSRC is cleared, selects internal loop back mode and the LPUART does not use the RXD pin. 6040 * 0b1..Single-wire LPUART mode where the TXD pin is connected to the transmitter output and receiver input. 6041 */ 6042 #define LPUART_CTRL_RSRC(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_RSRC_SHIFT)) & LPUART_CTRL_RSRC_MASK) 6043 #define LPUART_CTRL_DOZEEN_MASK (0x40U) 6044 #define LPUART_CTRL_DOZEEN_SHIFT (6U) 6045 /*! DOZEEN - Doze Enable 6046 * 0b0..LPUART is enabled in Doze mode. 6047 * 0b1..LPUART is disabled in Doze mode. 6048 */ 6049 #define LPUART_CTRL_DOZEEN(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_DOZEEN_SHIFT)) & LPUART_CTRL_DOZEEN_MASK) 6050 #define LPUART_CTRL_LOOPS_MASK (0x80U) 6051 #define LPUART_CTRL_LOOPS_SHIFT (7U) 6052 /*! LOOPS - Loop Mode Select 6053 * 0b0..Normal operation - RXD and TXD use separate pins. 6054 * 0b1..Loop mode or single-wire mode where transmitter outputs are internally connected to receiver input (see RSRC bit). 6055 */ 6056 #define LPUART_CTRL_LOOPS(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_LOOPS_SHIFT)) & LPUART_CTRL_LOOPS_MASK) 6057 #define LPUART_CTRL_IDLECFG_MASK (0x700U) 6058 #define LPUART_CTRL_IDLECFG_SHIFT (8U) 6059 /*! IDLECFG - Idle Configuration 6060 * 0b000..1 idle character 6061 * 0b001..2 idle characters 6062 * 0b010..4 idle characters 6063 * 0b011..8 idle characters 6064 * 0b100..16 idle characters 6065 * 0b101..32 idle characters 6066 * 0b110..64 idle characters 6067 * 0b111..128 idle characters 6068 */ 6069 #define LPUART_CTRL_IDLECFG(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_IDLECFG_SHIFT)) & LPUART_CTRL_IDLECFG_MASK) 6070 #define LPUART_CTRL_M7_MASK (0x800U) 6071 #define LPUART_CTRL_M7_SHIFT (11U) 6072 /*! M7 - 7-Bit Mode Select 6073 * 0b0..Receiver and transmitter use 8-bit to 10-bit data characters. 6074 * 0b1..Receiver and transmitter use 7-bit data characters. 6075 */ 6076 #define LPUART_CTRL_M7(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_M7_SHIFT)) & LPUART_CTRL_M7_MASK) 6077 #define LPUART_CTRL_MA2IE_MASK (0x4000U) 6078 #define LPUART_CTRL_MA2IE_SHIFT (14U) 6079 /*! MA2IE - Match 2 Interrupt Enable 6080 * 0b0..MA2F interrupt disabled 6081 * 0b1..MA2F interrupt enabled 6082 */ 6083 #define LPUART_CTRL_MA2IE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_MA2IE_SHIFT)) & LPUART_CTRL_MA2IE_MASK) 6084 #define LPUART_CTRL_MA1IE_MASK (0x8000U) 6085 #define LPUART_CTRL_MA1IE_SHIFT (15U) 6086 /*! MA1IE - Match 1 Interrupt Enable 6087 * 0b0..MA1F interrupt disabled 6088 * 0b1..MA1F interrupt enabled 6089 */ 6090 #define LPUART_CTRL_MA1IE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_MA1IE_SHIFT)) & LPUART_CTRL_MA1IE_MASK) 6091 #define LPUART_CTRL_SBK_MASK (0x10000U) 6092 #define LPUART_CTRL_SBK_SHIFT (16U) 6093 /*! SBK - Send Break 6094 * 0b0..Normal transmitter operation. 6095 * 0b1..Queue break character(s) to be sent. 6096 */ 6097 #define LPUART_CTRL_SBK(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_SBK_SHIFT)) & LPUART_CTRL_SBK_MASK) 6098 #define LPUART_CTRL_RWU_MASK (0x20000U) 6099 #define LPUART_CTRL_RWU_SHIFT (17U) 6100 /*! RWU - Receiver Wakeup Control 6101 * 0b0..Normal receiver operation. 6102 * 0b1..LPUART receiver in standby waiting for wakeup condition. 6103 */ 6104 #define LPUART_CTRL_RWU(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_RWU_SHIFT)) & LPUART_CTRL_RWU_MASK) 6105 #define LPUART_CTRL_RE_MASK (0x40000U) 6106 #define LPUART_CTRL_RE_SHIFT (18U) 6107 /*! RE - Receiver Enable 6108 * 0b0..Receiver disabled. 6109 * 0b1..Receiver enabled. 6110 */ 6111 #define LPUART_CTRL_RE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_RE_SHIFT)) & LPUART_CTRL_RE_MASK) 6112 #define LPUART_CTRL_TE_MASK (0x80000U) 6113 #define LPUART_CTRL_TE_SHIFT (19U) 6114 /*! TE - Transmitter Enable 6115 * 0b0..Transmitter disabled. 6116 * 0b1..Transmitter enabled. 6117 */ 6118 #define LPUART_CTRL_TE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TE_SHIFT)) & LPUART_CTRL_TE_MASK) 6119 #define LPUART_CTRL_ILIE_MASK (0x100000U) 6120 #define LPUART_CTRL_ILIE_SHIFT (20U) 6121 /*! ILIE - Idle Line Interrupt Enable 6122 * 0b0..Hardware interrupts from IDLE disabled; use polling. 6123 * 0b1..Hardware interrupt requested when IDLE flag is 1. 6124 */ 6125 #define LPUART_CTRL_ILIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_ILIE_SHIFT)) & LPUART_CTRL_ILIE_MASK) 6126 #define LPUART_CTRL_RIE_MASK (0x200000U) 6127 #define LPUART_CTRL_RIE_SHIFT (21U) 6128 /*! RIE - Receiver Interrupt Enable 6129 * 0b0..Hardware interrupts from RDRF disabled; use polling. 6130 * 0b1..Hardware interrupt requested when RDRF flag is 1. 6131 */ 6132 #define LPUART_CTRL_RIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_RIE_SHIFT)) & LPUART_CTRL_RIE_MASK) 6133 #define LPUART_CTRL_TCIE_MASK (0x400000U) 6134 #define LPUART_CTRL_TCIE_SHIFT (22U) 6135 /*! TCIE - Transmission Complete Interrupt Enable for 6136 * 0b0..Hardware interrupts from TC disabled; use polling. 6137 * 0b1..Hardware interrupt requested when TC flag is 1. 6138 */ 6139 #define LPUART_CTRL_TCIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TCIE_SHIFT)) & LPUART_CTRL_TCIE_MASK) 6140 #define LPUART_CTRL_TIE_MASK (0x800000U) 6141 #define LPUART_CTRL_TIE_SHIFT (23U) 6142 /*! TIE - Transmit Interrupt Enable 6143 * 0b0..Hardware interrupts from TDRE disabled; use polling. 6144 * 0b1..Hardware interrupt requested when TDRE flag is 1. 6145 */ 6146 #define LPUART_CTRL_TIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TIE_SHIFT)) & LPUART_CTRL_TIE_MASK) 6147 #define LPUART_CTRL_PEIE_MASK (0x1000000U) 6148 #define LPUART_CTRL_PEIE_SHIFT (24U) 6149 /*! PEIE - Parity Error Interrupt Enable 6150 * 0b0..PF interrupts disabled; use polling). 6151 * 0b1..Hardware interrupt requested when PF is set. 6152 */ 6153 #define LPUART_CTRL_PEIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_PEIE_SHIFT)) & LPUART_CTRL_PEIE_MASK) 6154 #define LPUART_CTRL_FEIE_MASK (0x2000000U) 6155 #define LPUART_CTRL_FEIE_SHIFT (25U) 6156 /*! FEIE - Framing Error Interrupt Enable 6157 * 0b0..FE interrupts disabled; use polling. 6158 * 0b1..Hardware interrupt requested when FE is set. 6159 */ 6160 #define LPUART_CTRL_FEIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_FEIE_SHIFT)) & LPUART_CTRL_FEIE_MASK) 6161 #define LPUART_CTRL_NEIE_MASK (0x4000000U) 6162 #define LPUART_CTRL_NEIE_SHIFT (26U) 6163 /*! NEIE - Noise Error Interrupt Enable 6164 * 0b0..NF interrupts disabled; use polling. 6165 * 0b1..Hardware interrupt requested when NF is set. 6166 */ 6167 #define LPUART_CTRL_NEIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_NEIE_SHIFT)) & LPUART_CTRL_NEIE_MASK) 6168 #define LPUART_CTRL_ORIE_MASK (0x8000000U) 6169 #define LPUART_CTRL_ORIE_SHIFT (27U) 6170 /*! ORIE - Overrun Interrupt Enable 6171 * 0b0..OR interrupts disabled; use polling. 6172 * 0b1..Hardware interrupt requested when OR is set. 6173 */ 6174 #define LPUART_CTRL_ORIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_ORIE_SHIFT)) & LPUART_CTRL_ORIE_MASK) 6175 #define LPUART_CTRL_TXINV_MASK (0x10000000U) 6176 #define LPUART_CTRL_TXINV_SHIFT (28U) 6177 /*! TXINV - Transmit Data Inversion 6178 * 0b0..Transmit data not inverted. 6179 * 0b1..Transmit data inverted. 6180 */ 6181 #define LPUART_CTRL_TXINV(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TXINV_SHIFT)) & LPUART_CTRL_TXINV_MASK) 6182 #define LPUART_CTRL_TXDIR_MASK (0x20000000U) 6183 #define LPUART_CTRL_TXDIR_SHIFT (29U) 6184 /*! TXDIR - TXD Pin Direction in Single-Wire Mode 6185 * 0b0..TXD pin is an input in single-wire mode. 6186 * 0b1..TXD pin is an output in single-wire mode. 6187 */ 6188 #define LPUART_CTRL_TXDIR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TXDIR_SHIFT)) & LPUART_CTRL_TXDIR_MASK) 6189 #define LPUART_CTRL_R9T8_MASK (0x40000000U) 6190 #define LPUART_CTRL_R9T8_SHIFT (30U) 6191 /*! R9T8 - Receive Bit 9 / Transmit Bit 8 6192 */ 6193 #define LPUART_CTRL_R9T8(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_R9T8_SHIFT)) & LPUART_CTRL_R9T8_MASK) 6194 #define LPUART_CTRL_R8T9_MASK (0x80000000U) 6195 #define LPUART_CTRL_R8T9_SHIFT (31U) 6196 /*! R8T9 - Receive Bit 8 / Transmit Bit 9 6197 */ 6198 #define LPUART_CTRL_R8T9(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_R8T9_SHIFT)) & LPUART_CTRL_R8T9_MASK) 6199 /*! @} */ 6200 6201 /*! @name DATA - LPUART Data Register */ 6202 /*! @{ */ 6203 #define LPUART_DATA_R0T0_MASK (0x1U) 6204 #define LPUART_DATA_R0T0_SHIFT (0U) 6205 /*! R0T0 - R0T0 6206 */ 6207 #define LPUART_DATA_R0T0(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R0T0_SHIFT)) & LPUART_DATA_R0T0_MASK) 6208 #define LPUART_DATA_R1T1_MASK (0x2U) 6209 #define LPUART_DATA_R1T1_SHIFT (1U) 6210 /*! R1T1 - R1T1 6211 */ 6212 #define LPUART_DATA_R1T1(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R1T1_SHIFT)) & LPUART_DATA_R1T1_MASK) 6213 #define LPUART_DATA_R2T2_MASK (0x4U) 6214 #define LPUART_DATA_R2T2_SHIFT (2U) 6215 /*! R2T2 - R2T2 6216 */ 6217 #define LPUART_DATA_R2T2(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R2T2_SHIFT)) & LPUART_DATA_R2T2_MASK) 6218 #define LPUART_DATA_R3T3_MASK (0x8U) 6219 #define LPUART_DATA_R3T3_SHIFT (3U) 6220 /*! R3T3 - R3T3 6221 */ 6222 #define LPUART_DATA_R3T3(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R3T3_SHIFT)) & LPUART_DATA_R3T3_MASK) 6223 #define LPUART_DATA_R4T4_MASK (0x10U) 6224 #define LPUART_DATA_R4T4_SHIFT (4U) 6225 /*! R4T4 - R4T4 6226 */ 6227 #define LPUART_DATA_R4T4(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R4T4_SHIFT)) & LPUART_DATA_R4T4_MASK) 6228 #define LPUART_DATA_R5T5_MASK (0x20U) 6229 #define LPUART_DATA_R5T5_SHIFT (5U) 6230 /*! R5T5 - R5T5 6231 */ 6232 #define LPUART_DATA_R5T5(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R5T5_SHIFT)) & LPUART_DATA_R5T5_MASK) 6233 #define LPUART_DATA_R6T6_MASK (0x40U) 6234 #define LPUART_DATA_R6T6_SHIFT (6U) 6235 /*! R6T6 - R6T6 6236 */ 6237 #define LPUART_DATA_R6T6(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R6T6_SHIFT)) & LPUART_DATA_R6T6_MASK) 6238 #define LPUART_DATA_R7T7_MASK (0x80U) 6239 #define LPUART_DATA_R7T7_SHIFT (7U) 6240 /*! R7T7 - R7T7 6241 */ 6242 #define LPUART_DATA_R7T7(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R7T7_SHIFT)) & LPUART_DATA_R7T7_MASK) 6243 #define LPUART_DATA_R8T8_MASK (0x100U) 6244 #define LPUART_DATA_R8T8_SHIFT (8U) 6245 /*! R8T8 - R8T8 6246 */ 6247 #define LPUART_DATA_R8T8(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R8T8_SHIFT)) & LPUART_DATA_R8T8_MASK) 6248 #define LPUART_DATA_R9T9_MASK (0x200U) 6249 #define LPUART_DATA_R9T9_SHIFT (9U) 6250 /*! R9T9 - R9T9 6251 */ 6252 #define LPUART_DATA_R9T9(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R9T9_SHIFT)) & LPUART_DATA_R9T9_MASK) 6253 #define LPUART_DATA_IDLINE_MASK (0x800U) 6254 #define LPUART_DATA_IDLINE_SHIFT (11U) 6255 /*! IDLINE - Idle Line 6256 * 0b0..Receiver was not idle before receiving this character. 6257 * 0b1..Receiver was idle before receiving this character. 6258 */ 6259 #define LPUART_DATA_IDLINE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_IDLINE_SHIFT)) & LPUART_DATA_IDLINE_MASK) 6260 #define LPUART_DATA_RXEMPT_MASK (0x1000U) 6261 #define LPUART_DATA_RXEMPT_SHIFT (12U) 6262 /*! RXEMPT - Receive Buffer Empty 6263 * 0b0..Receive buffer contains valid data. 6264 * 0b1..Receive buffer is empty, data returned on read is not valid. 6265 */ 6266 #define LPUART_DATA_RXEMPT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_RXEMPT_SHIFT)) & LPUART_DATA_RXEMPT_MASK) 6267 #define LPUART_DATA_FRETSC_MASK (0x2000U) 6268 #define LPUART_DATA_FRETSC_SHIFT (13U) 6269 /*! FRETSC - Frame Error / Transmit Special Character 6270 * 0b0..The dataword was received without a frame error on read, or transmit a normal character on write. 6271 * 0b1..The dataword was received with a frame error, or transmit an idle or break character on transmit. 6272 */ 6273 #define LPUART_DATA_FRETSC(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_FRETSC_SHIFT)) & LPUART_DATA_FRETSC_MASK) 6274 #define LPUART_DATA_PARITYE_MASK (0x4000U) 6275 #define LPUART_DATA_PARITYE_SHIFT (14U) 6276 /*! PARITYE - PARITYE 6277 * 0b0..The dataword was received without a parity error. 6278 * 0b1..The dataword was received with a parity error. 6279 */ 6280 #define LPUART_DATA_PARITYE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_PARITYE_SHIFT)) & LPUART_DATA_PARITYE_MASK) 6281 #define LPUART_DATA_NOISY_MASK (0x8000U) 6282 #define LPUART_DATA_NOISY_SHIFT (15U) 6283 /*! NOISY - NOISY 6284 * 0b0..The dataword was received without noise. 6285 * 0b1..The data was received with noise. 6286 */ 6287 #define LPUART_DATA_NOISY(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_NOISY_SHIFT)) & LPUART_DATA_NOISY_MASK) 6288 /*! @} */ 6289 6290 /*! @name MATCH - LPUART Match Address Register */ 6291 /*! @{ */ 6292 #define LPUART_MATCH_MA1_MASK (0x3FFU) 6293 #define LPUART_MATCH_MA1_SHIFT (0U) 6294 /*! MA1 - Match Address 1 6295 */ 6296 #define LPUART_MATCH_MA1(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MATCH_MA1_SHIFT)) & LPUART_MATCH_MA1_MASK) 6297 #define LPUART_MATCH_MA2_MASK (0x3FF0000U) 6298 #define LPUART_MATCH_MA2_SHIFT (16U) 6299 /*! MA2 - Match Address 2 6300 */ 6301 #define LPUART_MATCH_MA2(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MATCH_MA2_SHIFT)) & LPUART_MATCH_MA2_MASK) 6302 /*! @} */ 6303 6304 /*! @name MODIR - LPUART Modem IrDA Register */ 6305 /*! @{ */ 6306 #define LPUART_MODIR_TXCTSE_MASK (0x1U) 6307 #define LPUART_MODIR_TXCTSE_SHIFT (0U) 6308 /*! TXCTSE - Transmitter clear-to-send enable 6309 * 0b0..CTS has no effect on the transmitter. 6310 * 0b1..Enables clear-to-send operation. The transmitter checks the state of CTS each time it is ready to send a 6311 * character. If CTS is asserted, the character is sent. If CTS is deasserted, the signal TXD remains in the 6312 * mark state and transmission is delayed until CTS is asserted. Changes in CTS as a character is being sent 6313 * do not affect its transmission. 6314 */ 6315 #define LPUART_MODIR_TXCTSE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXCTSE_SHIFT)) & LPUART_MODIR_TXCTSE_MASK) 6316 #define LPUART_MODIR_TXRTSE_MASK (0x2U) 6317 #define LPUART_MODIR_TXRTSE_SHIFT (1U) 6318 /*! TXRTSE - Transmitter request-to-send enable 6319 * 0b0..The transmitter has no effect on RTS. 6320 * 0b1..When a character is placed into an empty transmitter data buffer , RTS asserts one bit time before the 6321 * start bit is transmitted. RTS deasserts one bit time after all characters in the transmitter data buffer and 6322 * shift register are completely sent, including the last stop bit. 6323 */ 6324 #define LPUART_MODIR_TXRTSE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXRTSE_SHIFT)) & LPUART_MODIR_TXRTSE_MASK) 6325 #define LPUART_MODIR_TXRTSPOL_MASK (0x4U) 6326 #define LPUART_MODIR_TXRTSPOL_SHIFT (2U) 6327 /*! TXRTSPOL - Transmitter request-to-send polarity 6328 * 0b0..Transmitter RTS is active low. 6329 * 0b1..Transmitter RTS is active high. 6330 */ 6331 #define LPUART_MODIR_TXRTSPOL(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXRTSPOL_SHIFT)) & LPUART_MODIR_TXRTSPOL_MASK) 6332 #define LPUART_MODIR_RXRTSE_MASK (0x8U) 6333 #define LPUART_MODIR_RXRTSE_SHIFT (3U) 6334 /*! RXRTSE - Receiver request-to-send enable 6335 * 0b0..The receiver has no effect on RTS. 6336 * 0b1..RTS is deasserted if the receiver data register is full or a start bit has been detected that would cause 6337 * the receiver data register to become full. RTS is asserted if the receiver data register is not full and 6338 * has not detected a start bit that would cause the receiver data register to become full. 6339 */ 6340 #define LPUART_MODIR_RXRTSE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_RXRTSE_SHIFT)) & LPUART_MODIR_RXRTSE_MASK) 6341 #define LPUART_MODIR_TXCTSC_MASK (0x10U) 6342 #define LPUART_MODIR_TXCTSC_SHIFT (4U) 6343 /*! TXCTSC - Transmit CTS Configuration 6344 * 0b0..CTS input is sampled at the start of each character. 6345 * 0b1..CTS input is sampled when the transmitter is idle. 6346 */ 6347 #define LPUART_MODIR_TXCTSC(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXCTSC_SHIFT)) & LPUART_MODIR_TXCTSC_MASK) 6348 #define LPUART_MODIR_TXCTSSRC_MASK (0x20U) 6349 #define LPUART_MODIR_TXCTSSRC_SHIFT (5U) 6350 /*! TXCTSSRC - Transmit CTS Source 6351 * 0b0..CTS input is the CTS_B pin. 6352 * 0b1..CTS input is the inverted Receiver Match result. 6353 */ 6354 #define LPUART_MODIR_TXCTSSRC(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXCTSSRC_SHIFT)) & LPUART_MODIR_TXCTSSRC_MASK) 6355 #define LPUART_MODIR_RTSWATER_MASK (0x300U) 6356 #define LPUART_MODIR_RTSWATER_SHIFT (8U) 6357 /*! RTSWATER - Receive RTS Configuration 6358 */ 6359 #define LPUART_MODIR_RTSWATER(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_RTSWATER_SHIFT)) & LPUART_MODIR_RTSWATER_MASK) 6360 #define LPUART_MODIR_TNP_MASK (0x30000U) 6361 #define LPUART_MODIR_TNP_SHIFT (16U) 6362 /*! TNP - Transmitter narrow pulse 6363 * 0b00..1/OSR. 6364 * 0b01..2/OSR. 6365 * 0b10..3/OSR. 6366 * 0b11..4/OSR. 6367 */ 6368 #define LPUART_MODIR_TNP(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TNP_SHIFT)) & LPUART_MODIR_TNP_MASK) 6369 #define LPUART_MODIR_IREN_MASK (0x40000U) 6370 #define LPUART_MODIR_IREN_SHIFT (18U) 6371 /*! IREN - Infrared enable 6372 * 0b0..IR disabled. 6373 * 0b1..IR enabled. 6374 */ 6375 #define LPUART_MODIR_IREN(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_IREN_SHIFT)) & LPUART_MODIR_IREN_MASK) 6376 /*! @} */ 6377 6378 /*! @name FIFO - LPUART FIFO Register */ 6379 /*! @{ */ 6380 #define LPUART_FIFO_RXFIFOSIZE_MASK (0x7U) 6381 #define LPUART_FIFO_RXFIFOSIZE_SHIFT (0U) 6382 /*! RXFIFOSIZE - Receive FIFO Buffer Depth 6383 * 0b000..Receive FIFO/Buffer depth = 1 dataword. 6384 * 0b001..Receive FIFO/Buffer depth = 4 datawords. 6385 * 0b010..Receive FIFO/Buffer depth = 8 datawords. 6386 * 0b011..Receive FIFO/Buffer depth = 16 datawords. 6387 * 0b100..Receive FIFO/Buffer depth = 32 datawords. 6388 * 0b101..Receive FIFO/Buffer depth = 64 datawords. 6389 * 0b110..Receive FIFO/Buffer depth = 128 datawords. 6390 * 0b111..Receive FIFO/Buffer depth = 256 datawords. 6391 */ 6392 #define LPUART_FIFO_RXFIFOSIZE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXFIFOSIZE_SHIFT)) & LPUART_FIFO_RXFIFOSIZE_MASK) 6393 #define LPUART_FIFO_RXFE_MASK (0x8U) 6394 #define LPUART_FIFO_RXFE_SHIFT (3U) 6395 /*! RXFE - Receive FIFO Enable 6396 * 0b0..Receive FIFO is not enabled. Buffer is depth 1. 6397 * 0b1..Receive FIFO is enabled. Buffer is depth indicted by RXFIFOSIZE. 6398 */ 6399 #define LPUART_FIFO_RXFE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXFE_SHIFT)) & LPUART_FIFO_RXFE_MASK) 6400 #define LPUART_FIFO_TXFIFOSIZE_MASK (0x70U) 6401 #define LPUART_FIFO_TXFIFOSIZE_SHIFT (4U) 6402 /*! TXFIFOSIZE - Transmit FIFO Buffer Depth 6403 * 0b000..Transmit FIFO/Buffer depth = 1 dataword. 6404 * 0b001..Transmit FIFO/Buffer depth = 4 datawords. 6405 * 0b010..Transmit FIFO/Buffer depth = 8 datawords. 6406 * 0b011..Transmit FIFO/Buffer depth = 16 datawords. 6407 * 0b100..Transmit FIFO/Buffer depth = 32 datawords. 6408 * 0b101..Transmit FIFO/Buffer depth = 64 datawords. 6409 * 0b110..Transmit FIFO/Buffer depth = 128 datawords. 6410 * 0b111..Transmit FIFO/Buffer depth = 256 datawords 6411 */ 6412 #define LPUART_FIFO_TXFIFOSIZE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXFIFOSIZE_SHIFT)) & LPUART_FIFO_TXFIFOSIZE_MASK) 6413 #define LPUART_FIFO_TXFE_MASK (0x80U) 6414 #define LPUART_FIFO_TXFE_SHIFT (7U) 6415 /*! TXFE - Transmit FIFO Enable 6416 * 0b0..Transmit FIFO is not enabled. Buffer is depth 1. 6417 * 0b1..Transmit FIFO is enabled. Buffer is depth indicated by TXFIFOSIZE. 6418 */ 6419 #define LPUART_FIFO_TXFE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXFE_SHIFT)) & LPUART_FIFO_TXFE_MASK) 6420 #define LPUART_FIFO_RXUFE_MASK (0x100U) 6421 #define LPUART_FIFO_RXUFE_SHIFT (8U) 6422 /*! RXUFE - Receive FIFO Underflow Interrupt Enable 6423 * 0b0..RXUF flag does not generate an interrupt to the host. 6424 * 0b1..RXUF flag generates an interrupt to the host. 6425 */ 6426 #define LPUART_FIFO_RXUFE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXUFE_SHIFT)) & LPUART_FIFO_RXUFE_MASK) 6427 #define LPUART_FIFO_TXOFE_MASK (0x200U) 6428 #define LPUART_FIFO_TXOFE_SHIFT (9U) 6429 /*! TXOFE - Transmit FIFO Overflow Interrupt Enable 6430 * 0b0..TXOF flag does not generate an interrupt to the host. 6431 * 0b1..TXOF flag generates an interrupt to the host. 6432 */ 6433 #define LPUART_FIFO_TXOFE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXOFE_SHIFT)) & LPUART_FIFO_TXOFE_MASK) 6434 #define LPUART_FIFO_RXIDEN_MASK (0x1C00U) 6435 #define LPUART_FIFO_RXIDEN_SHIFT (10U) 6436 /*! RXIDEN - Receiver Idle Empty Enable 6437 * 0b000..Disable RDRF assertion due to partially filled FIFO when receiver is idle. 6438 * 0b001..Enable RDRF assertion due to partially filled FIFO when receiver is idle for 1 character. 6439 * 0b010..Enable RDRF assertion due to partially filled FIFO when receiver is idle for 2 characters. 6440 * 0b011..Enable RDRF assertion due to partially filled FIFO when receiver is idle for 4 characters. 6441 * 0b100..Enable RDRF assertion due to partially filled FIFO when receiver is idle for 8 characters. 6442 * 0b101..Enable RDRF assertion due to partially filled FIFO when receiver is idle for 16 characters. 6443 * 0b110..Enable RDRF assertion due to partially filled FIFO when receiver is idle for 32 characters. 6444 * 0b111..Enable RDRF assertion due to partially filled FIFO when receiver is idle for 64 characters. 6445 */ 6446 #define LPUART_FIFO_RXIDEN(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXIDEN_SHIFT)) & LPUART_FIFO_RXIDEN_MASK) 6447 #define LPUART_FIFO_RXFLUSH_MASK (0x4000U) 6448 #define LPUART_FIFO_RXFLUSH_SHIFT (14U) 6449 /*! RXFLUSH - Receive FIFO/Buffer Flush 6450 * 0b0..No flush operation occurs. 6451 * 0b1..All data in the receive FIFO/buffer is cleared out. 6452 */ 6453 #define LPUART_FIFO_RXFLUSH(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXFLUSH_SHIFT)) & LPUART_FIFO_RXFLUSH_MASK) 6454 #define LPUART_FIFO_TXFLUSH_MASK (0x8000U) 6455 #define LPUART_FIFO_TXFLUSH_SHIFT (15U) 6456 /*! TXFLUSH - Transmit FIFO/Buffer Flush 6457 * 0b0..No flush operation occurs. 6458 * 0b1..All data in the transmit FIFO/Buffer is cleared out. 6459 */ 6460 #define LPUART_FIFO_TXFLUSH(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXFLUSH_SHIFT)) & LPUART_FIFO_TXFLUSH_MASK) 6461 #define LPUART_FIFO_RXUF_MASK (0x10000U) 6462 #define LPUART_FIFO_RXUF_SHIFT (16U) 6463 /*! RXUF - Receiver Buffer Underflow Flag 6464 * 0b0..No receive buffer underflow has occurred since the last time the flag was cleared. 6465 * 0b1..At least one receive buffer underflow has occurred since the last time the flag was cleared. 6466 */ 6467 #define LPUART_FIFO_RXUF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXUF_SHIFT)) & LPUART_FIFO_RXUF_MASK) 6468 #define LPUART_FIFO_TXOF_MASK (0x20000U) 6469 #define LPUART_FIFO_TXOF_SHIFT (17U) 6470 /*! TXOF - Transmitter Buffer Overflow Flag 6471 * 0b0..No transmit buffer overflow has occurred since the last time the flag was cleared. 6472 * 0b1..At least one transmit buffer overflow has occurred since the last time the flag was cleared. 6473 */ 6474 #define LPUART_FIFO_TXOF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXOF_SHIFT)) & LPUART_FIFO_TXOF_MASK) 6475 #define LPUART_FIFO_RXEMPT_MASK (0x400000U) 6476 #define LPUART_FIFO_RXEMPT_SHIFT (22U) 6477 /*! RXEMPT - Receive Buffer/FIFO Empty 6478 * 0b0..Receive buffer is not empty. 6479 * 0b1..Receive buffer is empty. 6480 */ 6481 #define LPUART_FIFO_RXEMPT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXEMPT_SHIFT)) & LPUART_FIFO_RXEMPT_MASK) 6482 #define LPUART_FIFO_TXEMPT_MASK (0x800000U) 6483 #define LPUART_FIFO_TXEMPT_SHIFT (23U) 6484 /*! TXEMPT - Transmit Buffer/FIFO Empty 6485 * 0b0..Transmit buffer is not empty. 6486 * 0b1..Transmit buffer is empty. 6487 */ 6488 #define LPUART_FIFO_TXEMPT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXEMPT_SHIFT)) & LPUART_FIFO_TXEMPT_MASK) 6489 /*! @} */ 6490 6491 /*! @name WATER - LPUART Watermark Register */ 6492 /*! @{ */ 6493 #define LPUART_WATER_TXWATER_MASK (0x3U) 6494 #define LPUART_WATER_TXWATER_SHIFT (0U) 6495 /*! TXWATER - Transmit Watermark 6496 */ 6497 #define LPUART_WATER_TXWATER(x) (((uint32_t)(((uint32_t)(x)) << LPUART_WATER_TXWATER_SHIFT)) & LPUART_WATER_TXWATER_MASK) 6498 #define LPUART_WATER_TXCOUNT_MASK (0x700U) 6499 #define LPUART_WATER_TXCOUNT_SHIFT (8U) 6500 /*! TXCOUNT - Transmit Counter 6501 */ 6502 #define LPUART_WATER_TXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_WATER_TXCOUNT_SHIFT)) & LPUART_WATER_TXCOUNT_MASK) 6503 #define LPUART_WATER_RXWATER_MASK (0x30000U) 6504 #define LPUART_WATER_RXWATER_SHIFT (16U) 6505 /*! RXWATER - Receive Watermark 6506 */ 6507 #define LPUART_WATER_RXWATER(x) (((uint32_t)(((uint32_t)(x)) << LPUART_WATER_RXWATER_SHIFT)) & LPUART_WATER_RXWATER_MASK) 6508 #define LPUART_WATER_RXCOUNT_MASK (0x7000000U) 6509 #define LPUART_WATER_RXCOUNT_SHIFT (24U) 6510 /*! RXCOUNT - Receive Counter 6511 */ 6512 #define LPUART_WATER_RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_WATER_RXCOUNT_SHIFT)) & LPUART_WATER_RXCOUNT_MASK) 6513 /*! @} */ 6514 6515 6516 /*! 6517 * @} 6518 */ /* end of group LPUART_Register_Masks */ 6519 6520 6521 /* LPUART - Peripheral instance base addresses */ 6522 /** Peripheral LPUART0 base address */ 6523 #define LPUART0_BASE (0x4006A000u) 6524 /** Peripheral LPUART0 base pointer */ 6525 #define LPUART0 ((LPUART_Type *)LPUART0_BASE) 6526 /** Peripheral LPUART1 base address */ 6527 #define LPUART1_BASE (0x4006B000u) 6528 /** Peripheral LPUART1 base pointer */ 6529 #define LPUART1 ((LPUART_Type *)LPUART1_BASE) 6530 /** Peripheral LPUART2 base address */ 6531 #define LPUART2_BASE (0x4006C000u) 6532 /** Peripheral LPUART2 base pointer */ 6533 #define LPUART2 ((LPUART_Type *)LPUART2_BASE) 6534 /** Array initializer of LPUART peripheral base addresses */ 6535 #define LPUART_BASE_ADDRS { LPUART0_BASE, LPUART1_BASE, LPUART2_BASE } 6536 /** Array initializer of LPUART peripheral base pointers */ 6537 #define LPUART_BASE_PTRS { LPUART0, LPUART1, LPUART2 } 6538 /** Interrupt vectors for the LPUART peripheral type */ 6539 #define LPUART_RX_TX_IRQS { LPUART0_IRQn, LPUART1_IRQn, LPUART2_IRQn } 6540 #define LPUART_ERR_IRQS { LPUART0_IRQn, LPUART1_IRQn, LPUART2_IRQn } 6541 6542 /*! 6543 * @} 6544 */ /* end of group LPUART_Peripheral_Access_Layer */ 6545 6546 6547 /* ---------------------------------------------------------------------------- 6548 -- MCM Peripheral Access Layer 6549 ---------------------------------------------------------------------------- */ 6550 6551 /*! 6552 * @addtogroup MCM_Peripheral_Access_Layer MCM Peripheral Access Layer 6553 * @{ 6554 */ 6555 6556 /** MCM - Register Layout Typedef */ 6557 typedef struct { 6558 uint8_t RESERVED_0[8]; 6559 __I uint16_t PLASC; /**< Crossbar Switch (AXBS) Slave Configuration, offset: 0x8 */ 6560 __I uint16_t PLAMC; /**< Crossbar Switch (AXBS) Master Configuration, offset: 0xA */ 6561 __IO uint32_t PLACR; /**< Platform Control Register, offset: 0xC */ 6562 uint8_t RESERVED_1[48]; 6563 __IO uint32_t CPO; /**< Compute Operation Control Register, offset: 0x40 */ 6564 } MCM_Type; 6565 6566 /* ---------------------------------------------------------------------------- 6567 -- MCM Register Masks 6568 ---------------------------------------------------------------------------- */ 6569 6570 /*! 6571 * @addtogroup MCM_Register_Masks MCM Register Masks 6572 * @{ 6573 */ 6574 6575 /*! @name PLASC - Crossbar Switch (AXBS) Slave Configuration */ 6576 /*! @{ */ 6577 #define MCM_PLASC_ASC_MASK (0xFFU) 6578 #define MCM_PLASC_ASC_SHIFT (0U) 6579 /*! ASC - Each bit in the ASC field indicates whether there is a corresponding connection to the 6580 * crossbar switch's slave input port. 6581 * 0b00000000..A bus slave connection to AXBS input port n is absent. 6582 * 0b00000001..A bus slave connection to AXBS input port n is present. 6583 */ 6584 #define MCM_PLASC_ASC(x) (((uint16_t)(((uint16_t)(x)) << MCM_PLASC_ASC_SHIFT)) & MCM_PLASC_ASC_MASK) 6585 /*! @} */ 6586 6587 /*! @name PLAMC - Crossbar Switch (AXBS) Master Configuration */ 6588 /*! @{ */ 6589 #define MCM_PLAMC_AMC_MASK (0xFFU) 6590 #define MCM_PLAMC_AMC_SHIFT (0U) 6591 /*! AMC - Each bit in the AMC field indicates whether there is a corresponding connection to the AXBS master input port. 6592 * 0b00000000..A bus master connection to AXBS input port n is absent 6593 * 0b00000001..A bus master connection to AXBS input port n is present 6594 */ 6595 #define MCM_PLAMC_AMC(x) (((uint16_t)(((uint16_t)(x)) << MCM_PLAMC_AMC_SHIFT)) & MCM_PLAMC_AMC_MASK) 6596 /*! @} */ 6597 6598 /*! @name PLACR - Platform Control Register */ 6599 /*! @{ */ 6600 #define MCM_PLACR_ARB_MASK (0x200U) 6601 #define MCM_PLACR_ARB_SHIFT (9U) 6602 /*! ARB - Arbitration select 6603 * 0b0..Fixed-priority arbitration for the crossbar masters 6604 * 0b1..Round-robin arbitration for the crossbar masters 6605 */ 6606 #define MCM_PLACR_ARB(x) (((uint32_t)(((uint32_t)(x)) << MCM_PLACR_ARB_SHIFT)) & MCM_PLACR_ARB_MASK) 6607 #define MCM_PLACR_CFCC_MASK (0x400U) 6608 #define MCM_PLACR_CFCC_SHIFT (10U) 6609 /*! CFCC - Clear Flash Controller Cache 6610 */ 6611 #define MCM_PLACR_CFCC(x) (((uint32_t)(((uint32_t)(x)) << MCM_PLACR_CFCC_SHIFT)) & MCM_PLACR_CFCC_MASK) 6612 #define MCM_PLACR_DFCDA_MASK (0x800U) 6613 #define MCM_PLACR_DFCDA_SHIFT (11U) 6614 /*! DFCDA - Disable Flash Controller Data Caching 6615 * 0b0..Enable flash controller data caching 6616 * 0b1..Disable flash controller data caching. 6617 */ 6618 #define MCM_PLACR_DFCDA(x) (((uint32_t)(((uint32_t)(x)) << MCM_PLACR_DFCDA_SHIFT)) & MCM_PLACR_DFCDA_MASK) 6619 #define MCM_PLACR_DFCIC_MASK (0x1000U) 6620 #define MCM_PLACR_DFCIC_SHIFT (12U) 6621 /*! DFCIC - Disable Flash Controller Instruction Caching 6622 * 0b0..Enable flash controller instruction caching. 6623 * 0b1..Disable flash controller instruction caching. 6624 */ 6625 #define MCM_PLACR_DFCIC(x) (((uint32_t)(((uint32_t)(x)) << MCM_PLACR_DFCIC_SHIFT)) & MCM_PLACR_DFCIC_MASK) 6626 #define MCM_PLACR_DFCC_MASK (0x2000U) 6627 #define MCM_PLACR_DFCC_SHIFT (13U) 6628 /*! DFCC - Disable Flash Controller Cache 6629 * 0b0..Enable flash controller cache. 6630 * 0b1..Disable flash controller cache. 6631 */ 6632 #define MCM_PLACR_DFCC(x) (((uint32_t)(((uint32_t)(x)) << MCM_PLACR_DFCC_SHIFT)) & MCM_PLACR_DFCC_MASK) 6633 #define MCM_PLACR_EFDS_MASK (0x4000U) 6634 #define MCM_PLACR_EFDS_SHIFT (14U) 6635 /*! EFDS - Enable Flash Data Speculation 6636 * 0b0..Disable flash data speculation. 6637 * 0b1..Enable flash data speculation. 6638 */ 6639 #define MCM_PLACR_EFDS(x) (((uint32_t)(((uint32_t)(x)) << MCM_PLACR_EFDS_SHIFT)) & MCM_PLACR_EFDS_MASK) 6640 #define MCM_PLACR_DFCS_MASK (0x8000U) 6641 #define MCM_PLACR_DFCS_SHIFT (15U) 6642 /*! DFCS - Disable Flash Controller Speculation 6643 * 0b0..Enable flash controller speculation. 6644 * 0b1..Disable flash controller speculation. 6645 */ 6646 #define MCM_PLACR_DFCS(x) (((uint32_t)(((uint32_t)(x)) << MCM_PLACR_DFCS_SHIFT)) & MCM_PLACR_DFCS_MASK) 6647 #define MCM_PLACR_ESFC_MASK (0x10000U) 6648 #define MCM_PLACR_ESFC_SHIFT (16U) 6649 /*! ESFC - Enable Stalling Flash Controller 6650 * 0b0..Disable stalling flash controller when flash is busy. 6651 * 0b1..Enable stalling flash controller when flash is busy. 6652 */ 6653 #define MCM_PLACR_ESFC(x) (((uint32_t)(((uint32_t)(x)) << MCM_PLACR_ESFC_SHIFT)) & MCM_PLACR_ESFC_MASK) 6654 /*! @} */ 6655 6656 /*! @name CPO - Compute Operation Control Register */ 6657 /*! @{ */ 6658 #define MCM_CPO_CPOREQ_MASK (0x1U) 6659 #define MCM_CPO_CPOREQ_SHIFT (0U) 6660 /*! CPOREQ - Compute Operation Request 6661 * 0b0..Request is cleared. 6662 * 0b1..Request Compute Operation. 6663 */ 6664 #define MCM_CPO_CPOREQ(x) (((uint32_t)(((uint32_t)(x)) << MCM_CPO_CPOREQ_SHIFT)) & MCM_CPO_CPOREQ_MASK) 6665 #define MCM_CPO_CPOACK_MASK (0x2U) 6666 #define MCM_CPO_CPOACK_SHIFT (1U) 6667 /*! CPOACK - Compute Operation Acknowledge 6668 * 0b0..Compute operation entry has not completed or compute operation exit has completed. 6669 * 0b1..Compute operation entry has completed or compute operation exit has not completed. 6670 */ 6671 #define MCM_CPO_CPOACK(x) (((uint32_t)(((uint32_t)(x)) << MCM_CPO_CPOACK_SHIFT)) & MCM_CPO_CPOACK_MASK) 6672 #define MCM_CPO_CPOWOI_MASK (0x4U) 6673 #define MCM_CPO_CPOWOI_SHIFT (2U) 6674 /*! CPOWOI - Compute Operation Wake-up on Interrupt 6675 * 0b0..No effect. 6676 * 0b1..When set, the CPOREQ is cleared on any interrupt or exception vector fetch. 6677 */ 6678 #define MCM_CPO_CPOWOI(x) (((uint32_t)(((uint32_t)(x)) << MCM_CPO_CPOWOI_SHIFT)) & MCM_CPO_CPOWOI_MASK) 6679 /*! @} */ 6680 6681 6682 /*! 6683 * @} 6684 */ /* end of group MCM_Register_Masks */ 6685 6686 6687 /* MCM - Peripheral instance base addresses */ 6688 /** Peripheral MCM base address */ 6689 #define MCM_BASE (0xF0003000u) 6690 /** Peripheral MCM base pointer */ 6691 #define MCM ((MCM_Type *)MCM_BASE) 6692 /** Array initializer of MCM peripheral base addresses */ 6693 #define MCM_BASE_ADDRS { MCM_BASE } 6694 /** Array initializer of MCM peripheral base pointers */ 6695 #define MCM_BASE_PTRS { MCM } 6696 6697 /*! 6698 * @} 6699 */ /* end of group MCM_Peripheral_Access_Layer */ 6700 6701 6702 /* ---------------------------------------------------------------------------- 6703 -- MMDVSQ Peripheral Access Layer 6704 ---------------------------------------------------------------------------- */ 6705 6706 /*! 6707 * @addtogroup MMDVSQ_Peripheral_Access_Layer MMDVSQ Peripheral Access Layer 6708 * @{ 6709 */ 6710 6711 /** MMDVSQ - Register Layout Typedef */ 6712 typedef struct { 6713 __IO uint32_t DEND; /**< Dividend Register, offset: 0x0 */ 6714 __IO uint32_t DSOR; /**< Divisor Register, offset: 0x4 */ 6715 __IO uint32_t CSR; /**< Control/Status Register, offset: 0x8 */ 6716 __IO uint32_t RES; /**< Result Register, offset: 0xC */ 6717 __O uint32_t RCND; /**< Radicand Register, offset: 0x10 */ 6718 } MMDVSQ_Type; 6719 6720 /* ---------------------------------------------------------------------------- 6721 -- MMDVSQ Register Masks 6722 ---------------------------------------------------------------------------- */ 6723 6724 /*! 6725 * @addtogroup MMDVSQ_Register_Masks MMDVSQ Register Masks 6726 * @{ 6727 */ 6728 6729 /*! @name DEND - Dividend Register */ 6730 /*! @{ */ 6731 #define MMDVSQ_DEND_DIVIDEND_MASK (0xFFFFFFFFU) 6732 #define MMDVSQ_DEND_DIVIDEND_SHIFT (0U) 6733 /*! DIVIDEND - Dividend 6734 */ 6735 #define MMDVSQ_DEND_DIVIDEND(x) (((uint32_t)(((uint32_t)(x)) << MMDVSQ_DEND_DIVIDEND_SHIFT)) & MMDVSQ_DEND_DIVIDEND_MASK) 6736 /*! @} */ 6737 6738 /*! @name DSOR - Divisor Register */ 6739 /*! @{ */ 6740 #define MMDVSQ_DSOR_DIVISOR_MASK (0xFFFFFFFFU) 6741 #define MMDVSQ_DSOR_DIVISOR_SHIFT (0U) 6742 /*! DIVISOR - Divisor 6743 */ 6744 #define MMDVSQ_DSOR_DIVISOR(x) (((uint32_t)(((uint32_t)(x)) << MMDVSQ_DSOR_DIVISOR_SHIFT)) & MMDVSQ_DSOR_DIVISOR_MASK) 6745 /*! @} */ 6746 6747 /*! @name CSR - Control/Status Register */ 6748 /*! @{ */ 6749 #define MMDVSQ_CSR_SRT_MASK (0x1U) 6750 #define MMDVSQ_CSR_SRT_SHIFT (0U) 6751 /*! SRT - Start 6752 * 0b0..No operation initiated 6753 * 0b1..If CSR[DFS] = 1, then initiate a divide calculation, else ignore 6754 */ 6755 #define MMDVSQ_CSR_SRT(x) (((uint32_t)(((uint32_t)(x)) << MMDVSQ_CSR_SRT_SHIFT)) & MMDVSQ_CSR_SRT_MASK) 6756 #define MMDVSQ_CSR_USGN_MASK (0x2U) 6757 #define MMDVSQ_CSR_USGN_SHIFT (1U) 6758 /*! USGN - Unsigned calculation 6759 * 0b0..Perform a signed divide 6760 * 0b1..Perform an unsigned divide 6761 */ 6762 #define MMDVSQ_CSR_USGN(x) (((uint32_t)(((uint32_t)(x)) << MMDVSQ_CSR_USGN_SHIFT)) & MMDVSQ_CSR_USGN_MASK) 6763 #define MMDVSQ_CSR_REM_MASK (0x4U) 6764 #define MMDVSQ_CSR_REM_SHIFT (2U) 6765 /*! REM - REMainder calculation 6766 * 0b0..Return the quotient in the RES for the divide calculation 6767 * 0b1..Return the remainder in the RES for the divide calculation 6768 */ 6769 #define MMDVSQ_CSR_REM(x) (((uint32_t)(((uint32_t)(x)) << MMDVSQ_CSR_REM_SHIFT)) & MMDVSQ_CSR_REM_MASK) 6770 #define MMDVSQ_CSR_DZE_MASK (0x8U) 6771 #define MMDVSQ_CSR_DZE_SHIFT (3U) 6772 /*! DZE - Divide-by-Zero-Enable 6773 * 0b0..Reads of the RES register return the register contents 6774 * 0b1..If CSR[DZ] = 1, an attempted read of RES register is error terminated to signal a divide-by-zero, else the register contents are returned 6775 */ 6776 #define MMDVSQ_CSR_DZE(x) (((uint32_t)(((uint32_t)(x)) << MMDVSQ_CSR_DZE_SHIFT)) & MMDVSQ_CSR_DZE_MASK) 6777 #define MMDVSQ_CSR_DZ_MASK (0x10U) 6778 #define MMDVSQ_CSR_DZ_SHIFT (4U) 6779 /*! DZ - Divide-by-Zero 6780 * 0b0..The last divide operation had a non-zero divisor, that is, DSOR != 0 6781 * 0b1..The last divide operation had a zero divisor, that is, DSOR = 0 6782 */ 6783 #define MMDVSQ_CSR_DZ(x) (((uint32_t)(((uint32_t)(x)) << MMDVSQ_CSR_DZ_SHIFT)) & MMDVSQ_CSR_DZ_MASK) 6784 #define MMDVSQ_CSR_DFS_MASK (0x20U) 6785 #define MMDVSQ_CSR_DFS_SHIFT (5U) 6786 /*! DFS - Disable Fast Start 6787 * 0b0..A divide operation is initiated by a write to the DSOR register 6788 * 0b1..A divide operation is initiated by a write to the CSR register with CSR[SRT] = 1 6789 */ 6790 #define MMDVSQ_CSR_DFS(x) (((uint32_t)(((uint32_t)(x)) << MMDVSQ_CSR_DFS_SHIFT)) & MMDVSQ_CSR_DFS_MASK) 6791 #define MMDVSQ_CSR_SQRT_MASK (0x20000000U) 6792 #define MMDVSQ_CSR_SQRT_SHIFT (29U) 6793 /*! SQRT - SQUARE ROOT 6794 * 0b0..Current or last MMDVSQ operation was not a square root 6795 * 0b1..Current or last MMDVSQ operation was a square root 6796 */ 6797 #define MMDVSQ_CSR_SQRT(x) (((uint32_t)(((uint32_t)(x)) << MMDVSQ_CSR_SQRT_SHIFT)) & MMDVSQ_CSR_SQRT_MASK) 6798 #define MMDVSQ_CSR_DIV_MASK (0x40000000U) 6799 #define MMDVSQ_CSR_DIV_SHIFT (30U) 6800 /*! DIV - DIVIDE 6801 * 0b0..Current or last MMDVSQ operation was not a divide 6802 * 0b1..Current or last MMDVSQ operation was a divide 6803 */ 6804 #define MMDVSQ_CSR_DIV(x) (((uint32_t)(((uint32_t)(x)) << MMDVSQ_CSR_DIV_SHIFT)) & MMDVSQ_CSR_DIV_MASK) 6805 #define MMDVSQ_CSR_BUSY_MASK (0x80000000U) 6806 #define MMDVSQ_CSR_BUSY_SHIFT (31U) 6807 /*! BUSY - BUSY 6808 * 0b0..MMDVSQ is idle 6809 * 0b1..MMDVSQ is busy performing a divide or square root calculation 6810 */ 6811 #define MMDVSQ_CSR_BUSY(x) (((uint32_t)(((uint32_t)(x)) << MMDVSQ_CSR_BUSY_SHIFT)) & MMDVSQ_CSR_BUSY_MASK) 6812 /*! @} */ 6813 6814 /*! @name RES - Result Register */ 6815 /*! @{ */ 6816 #define MMDVSQ_RES_RESULT_MASK (0xFFFFFFFFU) 6817 #define MMDVSQ_RES_RESULT_SHIFT (0U) 6818 /*! RESULT - Result 6819 */ 6820 #define MMDVSQ_RES_RESULT(x) (((uint32_t)(((uint32_t)(x)) << MMDVSQ_RES_RESULT_SHIFT)) & MMDVSQ_RES_RESULT_MASK) 6821 /*! @} */ 6822 6823 /*! @name RCND - Radicand Register */ 6824 /*! @{ */ 6825 #define MMDVSQ_RCND_RADICAND_MASK (0xFFFFFFFFU) 6826 #define MMDVSQ_RCND_RADICAND_SHIFT (0U) 6827 /*! RADICAND - Radicand 6828 */ 6829 #define MMDVSQ_RCND_RADICAND(x) (((uint32_t)(((uint32_t)(x)) << MMDVSQ_RCND_RADICAND_SHIFT)) & MMDVSQ_RCND_RADICAND_MASK) 6830 /*! @} */ 6831 6832 6833 /*! 6834 * @} 6835 */ /* end of group MMDVSQ_Register_Masks */ 6836 6837 6838 /* MMDVSQ - Peripheral instance base addresses */ 6839 /** Peripheral MMDVSQ base address */ 6840 #define MMDVSQ_BASE (0xF0004000u) 6841 /** Peripheral MMDVSQ base pointer */ 6842 #define MMDVSQ ((MMDVSQ_Type *)MMDVSQ_BASE) 6843 /** Array initializer of MMDVSQ peripheral base addresses */ 6844 #define MMDVSQ_BASE_ADDRS { MMDVSQ_BASE } 6845 /** Array initializer of MMDVSQ peripheral base pointers */ 6846 #define MMDVSQ_BASE_PTRS { MMDVSQ } 6847 6848 /*! 6849 * @} 6850 */ /* end of group MMDVSQ_Peripheral_Access_Layer */ 6851 6852 6853 /* ---------------------------------------------------------------------------- 6854 -- MSCAN Peripheral Access Layer 6855 ---------------------------------------------------------------------------- */ 6856 6857 /*! 6858 * @addtogroup MSCAN_Peripheral_Access_Layer MSCAN Peripheral Access Layer 6859 * @{ 6860 */ 6861 6862 /** MSCAN - Register Layout Typedef */ 6863 typedef struct { 6864 __IO uint8_t CANCTL0; /**< MSCAN Control Register 0, offset: 0x0 */ 6865 __IO uint8_t CANCTL1; /**< MSCAN Control Register 1, offset: 0x1 */ 6866 __IO uint8_t CANBTR0; /**< MSCAN Bus Timing Register 0, offset: 0x2 */ 6867 __IO uint8_t CANBTR1; /**< MSCAN Bus Timing Register 1, offset: 0x3 */ 6868 __IO uint8_t CANRFLG; /**< MSCAN Receiver Flag Register, offset: 0x4 */ 6869 __IO uint8_t CANRIER; /**< MSCAN Receiver Interrupt Enable Register, offset: 0x5 */ 6870 __IO uint8_t CANTFLG; /**< MSCAN Transmitter Flag Register, offset: 0x6 */ 6871 __IO uint8_t CANTIER; /**< MSCAN Transmitter Interrupt Enable Register, offset: 0x7 */ 6872 __IO uint8_t CANTARQ; /**< MSCAN Transmitter Message Abort Request Register, offset: 0x8 */ 6873 __I uint8_t CANTAAK; /**< MSCAN Transmitter Message Abort Acknowledge Register, offset: 0x9 */ 6874 __IO uint8_t CANTBSEL; /**< MSCAN Transmit Buffer Selection Register, offset: 0xA */ 6875 __IO uint8_t CANIDAC; /**< MSCAN Identifier Acceptance Control Register, offset: 0xB */ 6876 uint8_t RESERVED_0[1]; 6877 __IO uint8_t CANMISC; /**< MSCAN Miscellaneous Register, offset: 0xD */ 6878 __I uint8_t CANRXERR; /**< MSCAN Receive Error Counter, offset: 0xE */ 6879 __I uint8_t CANTXERR; /**< MSCAN Transmit Error Counter, offset: 0xF */ 6880 __IO uint8_t CANIDAR_BANK_1[4]; /**< MSCAN Identifier Acceptance Register n of First Bank, array offset: 0x10, array step: 0x1 */ 6881 __IO uint8_t CANIDMR_BANK_1[4]; /**< MSCAN Identifier Mask Register n of First Bank, array offset: 0x14, array step: 0x1 */ 6882 __IO uint8_t CANIDAR_BANK_2[4]; /**< MSCAN Identifier Acceptance Register n of Second Bank, array offset: 0x18, array step: 0x1 */ 6883 __IO uint8_t CANIDMR_BANK_2[4]; /**< MSCAN Identifier Mask Register n of Second Bank, array offset: 0x1C, array step: 0x1 */ 6884 union { /* offset: 0x20 */ 6885 __I uint8_t REIDR0; /**< Receive Extended Identifier Register 0, offset: 0x20 */ 6886 __I uint8_t RSIDR0; /**< Receive Standard Identifier Register 0, offset: 0x20 */ 6887 }; 6888 union { /* offset: 0x21 */ 6889 __I uint8_t REIDR1; /**< Receive Extended Identifier Register 1, offset: 0x21 */ 6890 __I uint8_t RSIDR1; /**< Receive Standard Identifier Register 1, offset: 0x21 */ 6891 }; 6892 __I uint8_t REIDR2; /**< Receive Extended Identifier Register 2, offset: 0x22 */ 6893 __I uint8_t REIDR3; /**< Receive Extended Identifier Register 3, offset: 0x23 */ 6894 __I uint8_t REDSR[8]; /**< Receive Extended Data Segment Register N, array offset: 0x24, array step: 0x1 */ 6895 __I uint8_t RDLR; /**< Receive Data Length Register, offset: 0x2C */ 6896 uint8_t RESERVED_1[1]; 6897 __I uint8_t RTSRH; /**< Receive Time Stamp Register High, offset: 0x2E */ 6898 __I uint8_t RTSRL; /**< Receive Time Stamp Register Low, offset: 0x2F */ 6899 union { /* offset: 0x30 */ 6900 __IO uint8_t TEIDR0; /**< Transmit Extended Identifier Register 0, offset: 0x30 */ 6901 __IO uint8_t TSIDR0; /**< Transmit Standard Identifier Register 0, offset: 0x30 */ 6902 }; 6903 union { /* offset: 0x31 */ 6904 __IO uint8_t TEIDR1; /**< Transmit Extended Identifier Register 1, offset: 0x31 */ 6905 __IO uint8_t TSIDR1; /**< Transmit Standard Identifier Register 1, offset: 0x31 */ 6906 }; 6907 __IO uint8_t TEIDR2; /**< Transmit Extended Identifier Register 2, offset: 0x32 */ 6908 __IO uint8_t TEIDR3; /**< Transmit Extended Identifier Register 3, offset: 0x33 */ 6909 __IO uint8_t TEDSR[8]; /**< Transmit Extended Data Segment Register N, array offset: 0x34, array step: 0x1 */ 6910 __IO uint8_t TDLR; /**< Transmit Data Length Register, offset: 0x3C */ 6911 __IO uint8_t TBPR; /**< Transmit Buffer Priority Register, offset: 0x3D */ 6912 __I uint8_t TTSRH; /**< Transmit Time Stamp Register High, offset: 0x3E */ 6913 __I uint8_t TTSRL; /**< Transmit Time Stamp Register Low, offset: 0x3F */ 6914 } MSCAN_Type; 6915 6916 /* ---------------------------------------------------------------------------- 6917 -- MSCAN Register Masks 6918 ---------------------------------------------------------------------------- */ 6919 6920 /*! 6921 * @addtogroup MSCAN_Register_Masks MSCAN Register Masks 6922 * @{ 6923 */ 6924 6925 /*! @name CANCTL0 - MSCAN Control Register 0 */ 6926 /*! @{ */ 6927 #define MSCAN_CANCTL0_INITRQ_MASK (0x1U) 6928 #define MSCAN_CANCTL0_INITRQ_SHIFT (0U) 6929 /*! INITRQ - Initialization Mode Request 6930 * 0b0..Normal operation. 6931 * 0b1..MSCAN in initialization mode. 6932 */ 6933 #define MSCAN_CANCTL0_INITRQ(x) (((uint8_t)(((uint8_t)(x)) << MSCAN_CANCTL0_INITRQ_SHIFT)) & MSCAN_CANCTL0_INITRQ_MASK) 6934 #define MSCAN_CANCTL0_SLPRQ_MASK (0x2U) 6935 #define MSCAN_CANCTL0_SLPRQ_SHIFT (1U) 6936 /*! SLPRQ - Sleep Mode Request 6937 * 0b0..Running - The MSCAN functions normally. 6938 * 0b1..Sleep mode request - The MSCAN enters sleep mode when CAN bus idle. 6939 */ 6940 #define MSCAN_CANCTL0_SLPRQ(x) (((uint8_t)(((uint8_t)(x)) << MSCAN_CANCTL0_SLPRQ_SHIFT)) & MSCAN_CANCTL0_SLPRQ_MASK) 6941 #define MSCAN_CANCTL0_WUPE_MASK (0x4U) 6942 #define MSCAN_CANCTL0_WUPE_SHIFT (2U) 6943 /*! WUPE - WakeUp Enable 6944 * 0b0..Wakeup disabled - The MSCAN ignores traffic on CAN. 6945 * 0b1..Wakeup enabled - The MSCAN is able to restart. 6946 */ 6947 #define MSCAN_CANCTL0_WUPE(x) (((uint8_t)(((uint8_t)(x)) << MSCAN_CANCTL0_WUPE_SHIFT)) & MSCAN_CANCTL0_WUPE_MASK) 6948 #define MSCAN_CANCTL0_TIME_MASK (0x8U) 6949 #define MSCAN_CANCTL0_TIME_SHIFT (3U) 6950 /*! TIME - Timer Enable 6951 * 0b0..Disable internal MSCAN timer. 6952 * 0b1..Enable internal MSCAN timer. 6953 */ 6954 #define MSCAN_CANCTL0_TIME(x) (((uint8_t)(((uint8_t)(x)) << MSCAN_CANCTL0_TIME_SHIFT)) & MSCAN_CANCTL0_TIME_MASK) 6955 #define MSCAN_CANCTL0_SYNCH_MASK (0x10U) 6956 #define MSCAN_CANCTL0_SYNCH_SHIFT (4U) 6957 /*! SYNCH - Synchronized Status 6958 * 0b0..MSCAN is not synchronized to the CAN bus. 6959 * 0b1..MSCAN is synchronized to the CAN bus. 6960 */ 6961 #define MSCAN_CANCTL0_SYNCH(x) (((uint8_t)(((uint8_t)(x)) << MSCAN_CANCTL0_SYNCH_SHIFT)) & MSCAN_CANCTL0_SYNCH_MASK) 6962 #define MSCAN_CANCTL0_CSWAI_MASK (0x20U) 6963 #define MSCAN_CANCTL0_CSWAI_SHIFT (5U) 6964 /*! CSWAI - CAN Stops in Wait Mode 6965 * 0b0..The module is not affected during wait mode. 6966 * 0b1..The module ceases to be clocked during wait mode. 6967 */ 6968 #define MSCAN_CANCTL0_CSWAI(x) (((uint8_t)(((uint8_t)(x)) << MSCAN_CANCTL0_CSWAI_SHIFT)) & MSCAN_CANCTL0_CSWAI_MASK) 6969 #define MSCAN_CANCTL0_RXACT_MASK (0x40U) 6970 #define MSCAN_CANCTL0_RXACT_SHIFT (6U) 6971 /*! RXACT - Receiver Active Status 6972 * 0b0..MSCAN is transmitting or idle. 6973 * 0b1..MSCAN is receiving a message, including when arbitration is lost. 6974 */ 6975 #define MSCAN_CANCTL0_RXACT(x) (((uint8_t)(((uint8_t)(x)) << MSCAN_CANCTL0_RXACT_SHIFT)) & MSCAN_CANCTL0_RXACT_MASK) 6976 #define MSCAN_CANCTL0_RXFRM_MASK (0x80U) 6977 #define MSCAN_CANCTL0_RXFRM_SHIFT (7U) 6978 /*! RXFRM - Received Frame Flag 6979 * 0b0..No valid message was received since last clearing this flag. 6980 * 0b1..A valid message was received since last clearing of this flag. 6981 */ 6982 #define MSCAN_CANCTL0_RXFRM(x) (((uint8_t)(((uint8_t)(x)) << MSCAN_CANCTL0_RXFRM_SHIFT)) & MSCAN_CANCTL0_RXFRM_MASK) 6983 /*! @} */ 6984 6985 /*! @name CANCTL1 - MSCAN Control Register 1 */ 6986 /*! @{ */ 6987 #define MSCAN_CANCTL1_INITAK_MASK (0x1U) 6988 #define MSCAN_CANCTL1_INITAK_SHIFT (0U) 6989 /*! INITAK - Initialization Mode Acknowledge 6990 * 0b0..Running - The MSCAN operates normally. 6991 * 0b1..Initialization mode active - The MSCAN has entered initialization mode. 6992 */ 6993 #define MSCAN_CANCTL1_INITAK(x) (((uint8_t)(((uint8_t)(x)) << MSCAN_CANCTL1_INITAK_SHIFT)) & MSCAN_CANCTL1_INITAK_MASK) 6994 #define MSCAN_CANCTL1_SLPAK_MASK (0x2U) 6995 #define MSCAN_CANCTL1_SLPAK_SHIFT (1U) 6996 /*! SLPAK - Sleep Mode Acknowledge 6997 * 0b0..Running - The MSCAN operates normally. 6998 * 0b1..Sleep mode active - The MSCAN has entered sleep mode. 6999 */ 7000 #define MSCAN_CANCTL1_SLPAK(x) (((uint8_t)(((uint8_t)(x)) << MSCAN_CANCTL1_SLPAK_SHIFT)) & MSCAN_CANCTL1_SLPAK_MASK) 7001 #define MSCAN_CANCTL1_WUPM_MASK (0x4U) 7002 #define MSCAN_CANCTL1_WUPM_SHIFT (2U) 7003 /*! WUPM - WakeUp Mode 7004 * 0b0..MSCAN wakes on any dominant level on the CAN bus. 7005 * 0b1..MSCAN wakes only in case of a dominant pulse on the CAN bus that has a length of Twup. 7006 */ 7007 #define MSCAN_CANCTL1_WUPM(x) (((uint8_t)(((uint8_t)(x)) << MSCAN_CANCTL1_WUPM_SHIFT)) & MSCAN_CANCTL1_WUPM_MASK) 7008 #define MSCAN_CANCTL1_BORM_MASK (0x8U) 7009 #define MSCAN_CANCTL1_BORM_SHIFT (3U) 7010 /*! BORM - Bus-Off Recovery Mode 7011 * 0b0..Automatic bus-off recovery (see Bosch CAN 2.0A/B protocol specification). 7012 * 0b1..Bus-off recovery upon user request. 7013 */ 7014 #define MSCAN_CANCTL1_BORM(x) (((uint8_t)(((uint8_t)(x)) << MSCAN_CANCTL1_BORM_SHIFT)) & MSCAN_CANCTL1_BORM_MASK) 7015 #define MSCAN_CANCTL1_LISTEN_MASK (0x10U) 7016 #define MSCAN_CANCTL1_LISTEN_SHIFT (4U) 7017 /*! LISTEN - Listen Only Mode 7018 * 0b0..Normal operation. 7019 * 0b1..Listen only mode activated. 7020 */ 7021 #define MSCAN_CANCTL1_LISTEN(x) (((uint8_t)(((uint8_t)(x)) << MSCAN_CANCTL1_LISTEN_SHIFT)) & MSCAN_CANCTL1_LISTEN_MASK) 7022 #define MSCAN_CANCTL1_LOOPB_MASK (0x20U) 7023 #define MSCAN_CANCTL1_LOOPB_SHIFT (5U) 7024 /*! LOOPB - Loopback Self Test Mode 7025 * 0b0..Loopback self test disabled. 7026 * 0b1..Loopback self test enabled. 7027 */ 7028 #define MSCAN_CANCTL1_LOOPB(x) (((uint8_t)(((uint8_t)(x)) << MSCAN_CANCTL1_LOOPB_SHIFT)) & MSCAN_CANCTL1_LOOPB_MASK) 7029 #define MSCAN_CANCTL1_CLKSRC_MASK (0x40U) 7030 #define MSCAN_CANCTL1_CLKSRC_SHIFT (6U) 7031 /*! CLKSRC - MSCAN Clock Source 7032 * 0b0..MSCAN clock source is the oscillator clock. 7033 * 0b1..MSCAN clock source is the bus clock. 7034 */ 7035 #define MSCAN_CANCTL1_CLKSRC(x) (((uint8_t)(((uint8_t)(x)) << MSCAN_CANCTL1_CLKSRC_SHIFT)) & MSCAN_CANCTL1_CLKSRC_MASK) 7036 #define MSCAN_CANCTL1_CANE_MASK (0x80U) 7037 #define MSCAN_CANCTL1_CANE_SHIFT (7U) 7038 /*! CANE - MSCAN Enable 7039 * 0b0..MSCAN module is disabled. 7040 * 0b1..MSCAN module is enabled. 7041 */ 7042 #define MSCAN_CANCTL1_CANE(x) (((uint8_t)(((uint8_t)(x)) << MSCAN_CANCTL1_CANE_SHIFT)) & MSCAN_CANCTL1_CANE_MASK) 7043 /*! @} */ 7044 7045 /*! @name CANBTR0 - MSCAN Bus Timing Register 0 */ 7046 /*! @{ */ 7047 #define MSCAN_CANBTR0_BRP_MASK (0x3FU) 7048 #define MSCAN_CANBTR0_BRP_SHIFT (0U) 7049 /*! BRP - Baud Rate Prescaler 7050 * 0b000000..1 7051 * 0b000001..2 7052 * 0b000010........ 7053 * 0b000011........ 7054 * 0b111110..63 7055 * 0b111111..64 7056 */ 7057 #define MSCAN_CANBTR0_BRP(x) (((uint8_t)(((uint8_t)(x)) << MSCAN_CANBTR0_BRP_SHIFT)) & MSCAN_CANBTR0_BRP_MASK) 7058 #define MSCAN_CANBTR0_SJW_MASK (0xC0U) 7059 #define MSCAN_CANBTR0_SJW_SHIFT (6U) 7060 /*! SJW - Synchronization Jump Width 7061 * 0b00..1 Tq clock cycle. 7062 * 0b01..2 Tq clock cycles. 7063 * 0b10..3 Tq clock cycle. 7064 * 0b11..4 Tq clock cycles. 7065 */ 7066 #define MSCAN_CANBTR0_SJW(x) (((uint8_t)(((uint8_t)(x)) << MSCAN_CANBTR0_SJW_SHIFT)) & MSCAN_CANBTR0_SJW_MASK) 7067 /*! @} */ 7068 7069 /*! @name CANBTR1 - MSCAN Bus Timing Register 1 */ 7070 /*! @{ */ 7071 #define MSCAN_CANBTR1_TSEG1_MASK (0xFU) 7072 #define MSCAN_CANBTR1_TSEG1_SHIFT (0U) 7073 /*! TSEG1 - Time Segment 1 7074 * 0b0000..1 Tq clock cycle (not valid) 7075 * 0b0001..2 Tq clock cycles (not valid) 7076 * 0b0010..3 Tq clock cycles (not valid) 7077 * 0b0011..4 Tq clock cycles 7078 * 0b1110..15 Tq clock cycles 7079 * 0b1111..16 Tq clock cycles 7080 */ 7081 #define MSCAN_CANBTR1_TSEG1(x) (((uint8_t)(((uint8_t)(x)) << MSCAN_CANBTR1_TSEG1_SHIFT)) & MSCAN_CANBTR1_TSEG1_MASK) 7082 #define MSCAN_CANBTR1_TSEG2_MASK (0x70U) 7083 #define MSCAN_CANBTR1_TSEG2_SHIFT (4U) 7084 /*! TSEG2 - Time Segment 2 7085 * 0b000..1 Tq clock cycle (not valid) 7086 * 0b001..2 Tq clock cycles 7087 * 0b010..3 Tq clock cycles 7088 * 0b011..4 Tq clock cycles 7089 * 0b100..5 Tq clock cycles 7090 * 0b101..6 Tq clock cycles 7091 * 0b110..7 Tq clock cycles 7092 * 0b111..8 Tq clock cycles 7093 */ 7094 #define MSCAN_CANBTR1_TSEG2(x) (((uint8_t)(((uint8_t)(x)) << MSCAN_CANBTR1_TSEG2_SHIFT)) & MSCAN_CANBTR1_TSEG2_MASK) 7095 #define MSCAN_CANBTR1_SAMP_MASK (0x80U) 7096 #define MSCAN_CANBTR1_SAMP_SHIFT (7U) 7097 /*! SAMP - Sampling 7098 * 0b0..One sample per bit. 7099 * 0b1..Three samples per bit. In this case, PHASE_SEG1 must be at least 2 time quanta (Tq). 7100 */ 7101 #define MSCAN_CANBTR1_SAMP(x) (((uint8_t)(((uint8_t)(x)) << MSCAN_CANBTR1_SAMP_SHIFT)) & MSCAN_CANBTR1_SAMP_MASK) 7102 /*! @} */ 7103 7104 /*! @name CANRFLG - MSCAN Receiver Flag Register */ 7105 /*! @{ */ 7106 #define MSCAN_CANRFLG_RXF_MASK (0x1U) 7107 #define MSCAN_CANRFLG_RXF_SHIFT (0U) 7108 /*! RXF - Receive Buffer Full Flag 7109 * 0b0..No new message available within the RxFG. 7110 * 0b1..The receiver FIFO is not empty. A new message is available in the RxFG. 7111 */ 7112 #define MSCAN_CANRFLG_RXF(x) (((uint8_t)(((uint8_t)(x)) << MSCAN_CANRFLG_RXF_SHIFT)) & MSCAN_CANRFLG_RXF_MASK) 7113 #define MSCAN_CANRFLG_OVRIF_MASK (0x2U) 7114 #define MSCAN_CANRFLG_OVRIF_SHIFT (1U) 7115 /*! OVRIF - Overrun Interrupt Flag 7116 * 0b0..No data overrun condition. 7117 * 0b1..A data overrun detected. 7118 */ 7119 #define MSCAN_CANRFLG_OVRIF(x) (((uint8_t)(((uint8_t)(x)) << MSCAN_CANRFLG_OVRIF_SHIFT)) & MSCAN_CANRFLG_OVRIF_MASK) 7120 #define MSCAN_CANRFLG_TSTAT_MASK (0xCU) 7121 #define MSCAN_CANRFLG_TSTAT_SHIFT (2U) 7122 /*! TSTAT - Transmitter Status 7123 * 0b00..TxOK: 0<=transmit error counter<96 7124 * 0b01..TxWRN: 96<=transmit error counter<128 7125 * 0b10..TxERR: 128<=transmit error counter<256 7126 * 0b11..Bus-off: 256<=transmit error counter 7127 */ 7128 #define MSCAN_CANRFLG_TSTAT(x) (((uint8_t)(((uint8_t)(x)) << MSCAN_CANRFLG_TSTAT_SHIFT)) & MSCAN_CANRFLG_TSTAT_MASK) 7129 #define MSCAN_CANRFLG_RSTAT_MASK (0x30U) 7130 #define MSCAN_CANRFLG_RSTAT_SHIFT (4U) 7131 /*! RSTAT - Receiver Status 7132 * 0b00..RxOK: 0<=receive error counter<96 7133 * 0b01..RxWRN: 96<=receive error counter<128 7134 * 0b10..RxERR: 128<=receive error counter 7135 * 0b11..Bus-off: 256<=transmit error counter (Redundant Information for the most critical CAN bus status which 7136 * is "bus-off". This only occurs if the Tx error counter exceeds a number of 255 errors. Bus-off affects the 7137 * receiver state. As soon as the transmitter leaves its bus-off state the receiver state skips to RxOK 7138 * too. Refer also to TSTAT[1:0] coding in this register. ) 7139 */ 7140 #define MSCAN_CANRFLG_RSTAT(x) (((uint8_t)(((uint8_t)(x)) << MSCAN_CANRFLG_RSTAT_SHIFT)) & MSCAN_CANRFLG_RSTAT_MASK) 7141 #define MSCAN_CANRFLG_CSCIF_MASK (0x40U) 7142 #define MSCAN_CANRFLG_CSCIF_SHIFT (6U) 7143 /*! CSCIF - CAN Status Change Interrupt Flag 7144 * 0b0..No change in CAN bus status occurred since last interrupt. 7145 * 0b1..MSCAN changed current CAN bus status. 7146 */ 7147 #define MSCAN_CANRFLG_CSCIF(x) (((uint8_t)(((uint8_t)(x)) << MSCAN_CANRFLG_CSCIF_SHIFT)) & MSCAN_CANRFLG_CSCIF_MASK) 7148 #define MSCAN_CANRFLG_WUPIF_MASK (0x80U) 7149 #define MSCAN_CANRFLG_WUPIF_SHIFT (7U) 7150 /*! WUPIF - Wake-Up Interrupt Flag 7151 * 0b0..No wakeup activity observed while in sleep mode. 7152 * 0b1..MSCAN detected activity on the CAN bus and requested wakeup. 7153 */ 7154 #define MSCAN_CANRFLG_WUPIF(x) (((uint8_t)(((uint8_t)(x)) << MSCAN_CANRFLG_WUPIF_SHIFT)) & MSCAN_CANRFLG_WUPIF_MASK) 7155 /*! @} */ 7156 7157 /*! @name CANRIER - MSCAN Receiver Interrupt Enable Register */ 7158 /*! @{ */ 7159 #define MSCAN_CANRIER_RXFIE_MASK (0x1U) 7160 #define MSCAN_CANRIER_RXFIE_SHIFT (0U) 7161 /*! RXFIE - Receiver Full Interrupt Enable 7162 * 0b0..No interrupt request is generated from this event. 7163 * 0b1..A receive buffer full (successful message reception) event causes a receiver interrupt request. 7164 */ 7165 #define MSCAN_CANRIER_RXFIE(x) (((uint8_t)(((uint8_t)(x)) << MSCAN_CANRIER_RXFIE_SHIFT)) & MSCAN_CANRIER_RXFIE_MASK) 7166 #define MSCAN_CANRIER_OVRIE_MASK (0x2U) 7167 #define MSCAN_CANRIER_OVRIE_SHIFT (1U) 7168 /*! OVRIE - Overrun Interrupt Enable 7169 * 0b0..No interrupt request is generated from this event. 7170 * 0b1..An overrun event causes an error interrupt request. 7171 */ 7172 #define MSCAN_CANRIER_OVRIE(x) (((uint8_t)(((uint8_t)(x)) << MSCAN_CANRIER_OVRIE_SHIFT)) & MSCAN_CANRIER_OVRIE_MASK) 7173 #define MSCAN_CANRIER_TSTATE_MASK (0xCU) 7174 #define MSCAN_CANRIER_TSTATE_SHIFT (2U) 7175 /*! TSTATE - Transmitter Status Change Enable 7176 * 0b00..Do not generate any CSCIF interrupt caused by transmitter state changes. 7177 * 0b01..Generate CSCIF interrupt only if the transmitter enters or leaves "bus-off" state. Discard other 7178 * transmitter state changes for generating CSCIF interrupt. 7179 * 0b10..Generate CSCIF interrupt only if the transmitter enters or leaves "TxErr" or "bus-off" state. Discard 7180 * other transmitter state changes for generating CSCIF interrupt. 7181 * 0b11..Generate CSCIF interrupt on all state changes. 7182 */ 7183 #define MSCAN_CANRIER_TSTATE(x) (((uint8_t)(((uint8_t)(x)) << MSCAN_CANRIER_TSTATE_SHIFT)) & MSCAN_CANRIER_TSTATE_MASK) 7184 #define MSCAN_CANRIER_RSTATE_MASK (0x30U) 7185 #define MSCAN_CANRIER_RSTATE_SHIFT (4U) 7186 /*! RSTATE - Receiver Status Change Enable 7187 * 0b00..Do not generate any CSCIF interrupt caused by receiver state changes. 7188 * 0b01..Generate CSCIF interrupt only if the receiver enters or leaves "bus-off" state. Discard other receiver 7189 * state changes for generating CSCIF interrupt. 7190 * 0b10..Generate CSCIF interrupt only if the receiver enters or leaves "RxErr" or "bus-off"Bus-off state is only 7191 * defined for transmitters by the CAN standard (see Bosch CAN 2.0A/B protocol specification). Because the 7192 * only possible state change for the transmitter from bus-off to TxOK also forces the receiver to skip its 7193 * current state to RxOK, the coding of the RXSTAT[1:0] flags define an additional bus-off state for the 7194 * receiver state. Discard other receiver state changes for generating CSCIF interrupt. 7195 * 0b11..Generate CSCIF interrupt on all state changes. 7196 */ 7197 #define MSCAN_CANRIER_RSTATE(x) (((uint8_t)(((uint8_t)(x)) << MSCAN_CANRIER_RSTATE_SHIFT)) & MSCAN_CANRIER_RSTATE_MASK) 7198 #define MSCAN_CANRIER_CSCIE_MASK (0x40U) 7199 #define MSCAN_CANRIER_CSCIE_SHIFT (6U) 7200 /*! CSCIE - CAN Status Change Interrupt Enable 7201 * 0b0..No interrupt request is generated from this event. 7202 * 0b1..A CAN Status Change event causes an error interrupt request. 7203 */ 7204 #define MSCAN_CANRIER_CSCIE(x) (((uint8_t)(((uint8_t)(x)) << MSCAN_CANRIER_CSCIE_SHIFT)) & MSCAN_CANRIER_CSCIE_MASK) 7205 #define MSCAN_CANRIER_WUPIE_MASK (0x80U) 7206 #define MSCAN_CANRIER_WUPIE_SHIFT (7U) 7207 /*! WUPIE - WakeUp Interrupt Enable 7208 * 0b0..No interrupt request is generated from this event. 7209 * 0b1..A wake-up event causes a Wake-Up interrupt request. 7210 */ 7211 #define MSCAN_CANRIER_WUPIE(x) (((uint8_t)(((uint8_t)(x)) << MSCAN_CANRIER_WUPIE_SHIFT)) & MSCAN_CANRIER_WUPIE_MASK) 7212 /*! @} */ 7213 7214 /*! @name CANTFLG - MSCAN Transmitter Flag Register */ 7215 /*! @{ */ 7216 #define MSCAN_CANTFLG_TXE_MASK (0x7U) 7217 #define MSCAN_CANTFLG_TXE_SHIFT (0U) 7218 /*! TXE - Transmitter Buffer Empty 7219 * 0b000..The associated message buffer is full (loaded with a message due for transmission). 7220 * 0b001..The associated message buffer is empty (not scheduled). 7221 */ 7222 #define MSCAN_CANTFLG_TXE(x) (((uint8_t)(((uint8_t)(x)) << MSCAN_CANTFLG_TXE_SHIFT)) & MSCAN_CANTFLG_TXE_MASK) 7223 /*! @} */ 7224 7225 /*! @name CANTIER - MSCAN Transmitter Interrupt Enable Register */ 7226 /*! @{ */ 7227 #define MSCAN_CANTIER_TXEIE_MASK (0x7U) 7228 #define MSCAN_CANTIER_TXEIE_SHIFT (0U) 7229 /*! TXEIE - Transmitter Empty Interrupt Enable 7230 * 0b000..No interrupt request is generated from this event. 7231 * 0b001..A transmitter empty (transmit buffer available for transmission) event causes a transmitter empty interrupt request. 7232 */ 7233 #define MSCAN_CANTIER_TXEIE(x) (((uint8_t)(((uint8_t)(x)) << MSCAN_CANTIER_TXEIE_SHIFT)) & MSCAN_CANTIER_TXEIE_MASK) 7234 /*! @} */ 7235 7236 /*! @name CANTARQ - MSCAN Transmitter Message Abort Request Register */ 7237 /*! @{ */ 7238 #define MSCAN_CANTARQ_ABTRQ_MASK (0x7U) 7239 #define MSCAN_CANTARQ_ABTRQ_SHIFT (0U) 7240 /*! ABTRQ - Abort Request 7241 * 0b000..No abort request. 7242 * 0b001..Abort request pending. 7243 */ 7244 #define MSCAN_CANTARQ_ABTRQ(x) (((uint8_t)(((uint8_t)(x)) << MSCAN_CANTARQ_ABTRQ_SHIFT)) & MSCAN_CANTARQ_ABTRQ_MASK) 7245 /*! @} */ 7246 7247 /*! @name CANTAAK - MSCAN Transmitter Message Abort Acknowledge Register */ 7248 /*! @{ */ 7249 #define MSCAN_CANTAAK_ABTAK_MASK (0x7U) 7250 #define MSCAN_CANTAAK_ABTAK_SHIFT (0U) 7251 /*! ABTAK - Abort Acknowledge 7252 * 0b000..The message was not aborted. 7253 * 0b001..The message was aborted. 7254 */ 7255 #define MSCAN_CANTAAK_ABTAK(x) (((uint8_t)(((uint8_t)(x)) << MSCAN_CANTAAK_ABTAK_SHIFT)) & MSCAN_CANTAAK_ABTAK_MASK) 7256 /*! @} */ 7257 7258 /*! @name CANTBSEL - MSCAN Transmit Buffer Selection Register */ 7259 /*! @{ */ 7260 #define MSCAN_CANTBSEL_TX_MASK (0x7U) 7261 #define MSCAN_CANTBSEL_TX_SHIFT (0U) 7262 /*! TX - Transmit Buffer Select 7263 * 0b000..The associated message buffer is deselected. 7264 * 0b001..The associated message buffer is selected, if lowest numbered bit. 7265 */ 7266 #define MSCAN_CANTBSEL_TX(x) (((uint8_t)(((uint8_t)(x)) << MSCAN_CANTBSEL_TX_SHIFT)) & MSCAN_CANTBSEL_TX_MASK) 7267 /*! @} */ 7268 7269 /*! @name CANIDAC - MSCAN Identifier Acceptance Control Register */ 7270 /*! @{ */ 7271 #define MSCAN_CANIDAC_IDHIT_MASK (0x7U) 7272 #define MSCAN_CANIDAC_IDHIT_SHIFT (0U) 7273 /*! IDHIT - Identifier Acceptance Hit Indicator 7274 * 0b000..Filter 0 hit. 7275 * 0b001..Filter 1 hit. 7276 * 0b010..Filter 2 hit. 7277 * 0b011..Filter 3 hit. 7278 * 0b100..Filter 4 hit. 7279 * 0b101..Filter 5 hit. 7280 * 0b110..Filter 6 hit. 7281 * 0b111..Filter 7 hit. 7282 */ 7283 #define MSCAN_CANIDAC_IDHIT(x) (((uint8_t)(((uint8_t)(x)) << MSCAN_CANIDAC_IDHIT_SHIFT)) & MSCAN_CANIDAC_IDHIT_MASK) 7284 #define MSCAN_CANIDAC_IDAM_MASK (0x30U) 7285 #define MSCAN_CANIDAC_IDAM_SHIFT (4U) 7286 /*! IDAM - Identifier Acceptance Mode 7287 * 0b00..Two 32-bit acceptance filters. 7288 * 0b01..Four 16-bit acceptance filters. 7289 * 0b10..Eight 8-bit acceptance filters. 7290 * 0b11..Filter closed. 7291 */ 7292 #define MSCAN_CANIDAC_IDAM(x) (((uint8_t)(((uint8_t)(x)) << MSCAN_CANIDAC_IDAM_SHIFT)) & MSCAN_CANIDAC_IDAM_MASK) 7293 /*! @} */ 7294 7295 /*! @name CANMISC - MSCAN Miscellaneous Register */ 7296 /*! @{ */ 7297 #define MSCAN_CANMISC_BOHOLD_MASK (0x1U) 7298 #define MSCAN_CANMISC_BOHOLD_SHIFT (0U) 7299 /*! BOHOLD - Bus-off State Hold Until User Request 7300 * 0b0..Module is not bus-off or recovery has been requested by user in bus-off state. 7301 * 0b1..Module is bus-off and holds this state until user request. 7302 */ 7303 #define MSCAN_CANMISC_BOHOLD(x) (((uint8_t)(((uint8_t)(x)) << MSCAN_CANMISC_BOHOLD_SHIFT)) & MSCAN_CANMISC_BOHOLD_MASK) 7304 /*! @} */ 7305 7306 /*! @name CANRXERR - MSCAN Receive Error Counter */ 7307 /*! @{ */ 7308 #define MSCAN_CANRXERR_RXERR_MASK (0xFFU) 7309 #define MSCAN_CANRXERR_RXERR_SHIFT (0U) 7310 /*! RXERR - Receive Error Counter 7311 */ 7312 #define MSCAN_CANRXERR_RXERR(x) (((uint8_t)(((uint8_t)(x)) << MSCAN_CANRXERR_RXERR_SHIFT)) & MSCAN_CANRXERR_RXERR_MASK) 7313 /*! @} */ 7314 7315 /*! @name CANTXERR - MSCAN Transmit Error Counter */ 7316 /*! @{ */ 7317 #define MSCAN_CANTXERR_TXERR_MASK (0xFFU) 7318 #define MSCAN_CANTXERR_TXERR_SHIFT (0U) 7319 /*! TXERR - Transmit Error Counter 7320 */ 7321 #define MSCAN_CANTXERR_TXERR(x) (((uint8_t)(((uint8_t)(x)) << MSCAN_CANTXERR_TXERR_SHIFT)) & MSCAN_CANTXERR_TXERR_MASK) 7322 /*! @} */ 7323 7324 /*! @name CANIDAR_BANK_1 - MSCAN Identifier Acceptance Register n of First Bank */ 7325 /*! @{ */ 7326 #define MSCAN_CANIDAR_BANK_1_AC_MASK (0xFFU) 7327 #define MSCAN_CANIDAR_BANK_1_AC_SHIFT (0U) 7328 /*! AC - Acceptance Code Bits 7329 */ 7330 #define MSCAN_CANIDAR_BANK_1_AC(x) (((uint8_t)(((uint8_t)(x)) << MSCAN_CANIDAR_BANK_1_AC_SHIFT)) & MSCAN_CANIDAR_BANK_1_AC_MASK) 7331 /*! @} */ 7332 7333 /* The count of MSCAN_CANIDAR_BANK_1 */ 7334 #define MSCAN_CANIDAR_BANK_1_COUNT (4U) 7335 7336 /*! @name CANIDMR_BANK_1 - MSCAN Identifier Mask Register n of First Bank */ 7337 /*! @{ */ 7338 #define MSCAN_CANIDMR_BANK_1_AM_MASK (0xFFU) 7339 #define MSCAN_CANIDMR_BANK_1_AM_SHIFT (0U) 7340 /*! AM - Acceptance Mask Bits 7341 * 0b00000000..Match corresponding acceptance code register and identifier bits. 7342 * 0b00000001..Ignore corresponding acceptance code register bit. 7343 */ 7344 #define MSCAN_CANIDMR_BANK_1_AM(x) (((uint8_t)(((uint8_t)(x)) << MSCAN_CANIDMR_BANK_1_AM_SHIFT)) & MSCAN_CANIDMR_BANK_1_AM_MASK) 7345 /*! @} */ 7346 7347 /* The count of MSCAN_CANIDMR_BANK_1 */ 7348 #define MSCAN_CANIDMR_BANK_1_COUNT (4U) 7349 7350 /*! @name CANIDAR_BANK_2 - MSCAN Identifier Acceptance Register n of Second Bank */ 7351 /*! @{ */ 7352 #define MSCAN_CANIDAR_BANK_2_AC_MASK (0xFFU) 7353 #define MSCAN_CANIDAR_BANK_2_AC_SHIFT (0U) 7354 /*! AC - Acceptance Code Bits 7355 */ 7356 #define MSCAN_CANIDAR_BANK_2_AC(x) (((uint8_t)(((uint8_t)(x)) << MSCAN_CANIDAR_BANK_2_AC_SHIFT)) & MSCAN_CANIDAR_BANK_2_AC_MASK) 7357 /*! @} */ 7358 7359 /* The count of MSCAN_CANIDAR_BANK_2 */ 7360 #define MSCAN_CANIDAR_BANK_2_COUNT (4U) 7361 7362 /*! @name CANIDMR_BANK_2 - MSCAN Identifier Mask Register n of Second Bank */ 7363 /*! @{ */ 7364 #define MSCAN_CANIDMR_BANK_2_AM_MASK (0xFFU) 7365 #define MSCAN_CANIDMR_BANK_2_AM_SHIFT (0U) 7366 /*! AM - Acceptance Mask Bits 7367 * 0b00000000..Match corresponding acceptance code register and identifier bits. 7368 * 0b00000001..Ignore corresponding acceptance code register bit. 7369 */ 7370 #define MSCAN_CANIDMR_BANK_2_AM(x) (((uint8_t)(((uint8_t)(x)) << MSCAN_CANIDMR_BANK_2_AM_SHIFT)) & MSCAN_CANIDMR_BANK_2_AM_MASK) 7371 /*! @} */ 7372 7373 /* The count of MSCAN_CANIDMR_BANK_2 */ 7374 #define MSCAN_CANIDMR_BANK_2_COUNT (4U) 7375 7376 /*! @name REIDR0 - Receive Extended Identifier Register 0 */ 7377 /*! @{ */ 7378 #define MSCAN_REIDR0_REID28_REID21_MASK (0xFFU) 7379 #define MSCAN_REIDR0_REID28_REID21_SHIFT (0U) 7380 /*! REID28_REID21 - Extended Format Identifier 7381 */ 7382 #define MSCAN_REIDR0_REID28_REID21(x) (((uint8_t)(((uint8_t)(x)) << MSCAN_REIDR0_REID28_REID21_SHIFT)) & MSCAN_REIDR0_REID28_REID21_MASK) 7383 /*! @} */ 7384 7385 /*! @name RSIDR0 - Receive Standard Identifier Register 0 */ 7386 /*! @{ */ 7387 #define MSCAN_RSIDR0_RSID10_RSID3_MASK (0xFFU) 7388 #define MSCAN_RSIDR0_RSID10_RSID3_SHIFT (0U) 7389 /*! RSID10_RSID3 - Standard Format Identifier 7390 */ 7391 #define MSCAN_RSIDR0_RSID10_RSID3(x) (((uint8_t)(((uint8_t)(x)) << MSCAN_RSIDR0_RSID10_RSID3_SHIFT)) & MSCAN_RSIDR0_RSID10_RSID3_MASK) 7392 /*! @} */ 7393 7394 /*! @name REIDR1 - Receive Extended Identifier Register 1 */ 7395 /*! @{ */ 7396 #define MSCAN_REIDR1_REID17_REID15_MASK (0x7U) 7397 #define MSCAN_REIDR1_REID17_REID15_SHIFT (0U) 7398 /*! REID17_REID15 - Extended Format Identifier 17-15 7399 */ 7400 #define MSCAN_REIDR1_REID17_REID15(x) (((uint8_t)(((uint8_t)(x)) << MSCAN_REIDR1_REID17_REID15_SHIFT)) & MSCAN_REIDR1_REID17_REID15_MASK) 7401 #define MSCAN_REIDR1_REIDE_MASK (0x8U) 7402 #define MSCAN_REIDR1_REIDE_SHIFT (3U) 7403 /*! REIDE - ID Extended 7404 * 0b0..Standard format (11 bit). 7405 * 0b1..Extended format (29 bit). 7406 */ 7407 #define MSCAN_REIDR1_REIDE(x) (((uint8_t)(((uint8_t)(x)) << MSCAN_REIDR1_REIDE_SHIFT)) & MSCAN_REIDR1_REIDE_MASK) 7408 #define MSCAN_REIDR1_RSRR_MASK (0x10U) 7409 #define MSCAN_REIDR1_RSRR_SHIFT (4U) 7410 /*! RSRR - Substitute Remote Request 7411 */ 7412 #define MSCAN_REIDR1_RSRR(x) (((uint8_t)(((uint8_t)(x)) << MSCAN_REIDR1_RSRR_SHIFT)) & MSCAN_REIDR1_RSRR_MASK) 7413 #define MSCAN_REIDR1_REID20_REID18_MASK (0xE0U) 7414 #define MSCAN_REIDR1_REID20_REID18_SHIFT (5U) 7415 /*! REID20_REID18 - Extended Format Identifier 20-18 7416 */ 7417 #define MSCAN_REIDR1_REID20_REID18(x) (((uint8_t)(((uint8_t)(x)) << MSCAN_REIDR1_REID20_REID18_SHIFT)) & MSCAN_REIDR1_REID20_REID18_MASK) 7418 /*! @} */ 7419 7420 /*! @name RSIDR1 - Receive Standard Identifier Register 1 */ 7421 /*! @{ */ 7422 #define MSCAN_RSIDR1_RSIDE_MASK (0x8U) 7423 #define MSCAN_RSIDR1_RSIDE_SHIFT (3U) 7424 /*! RSIDE - ID Extended 7425 * 0b0..Standard format (11 bit). 7426 * 0b1..Extended format (29 bit). 7427 */ 7428 #define MSCAN_RSIDR1_RSIDE(x) (((uint8_t)(((uint8_t)(x)) << MSCAN_RSIDR1_RSIDE_SHIFT)) & MSCAN_RSIDR1_RSIDE_MASK) 7429 #define MSCAN_RSIDR1_RSRTR_MASK (0x10U) 7430 #define MSCAN_RSIDR1_RSRTR_SHIFT (4U) 7431 /*! RSRTR - Remote Transmission Request 7432 * 0b0..Data frame. 7433 * 0b1..Remote frame. 7434 */ 7435 #define MSCAN_RSIDR1_RSRTR(x) (((uint8_t)(((uint8_t)(x)) << MSCAN_RSIDR1_RSRTR_SHIFT)) & MSCAN_RSIDR1_RSRTR_MASK) 7436 #define MSCAN_RSIDR1_RSID2_RSID0_MASK (0xE0U) 7437 #define MSCAN_RSIDR1_RSID2_RSID0_SHIFT (5U) 7438 /*! RSID2_RSID0 - Standard Format Identifier 2-0 7439 */ 7440 #define MSCAN_RSIDR1_RSID2_RSID0(x) (((uint8_t)(((uint8_t)(x)) << MSCAN_RSIDR1_RSID2_RSID0_SHIFT)) & MSCAN_RSIDR1_RSID2_RSID0_MASK) 7441 /*! @} */ 7442 7443 /*! @name REIDR2 - Receive Extended Identifier Register 2 */ 7444 /*! @{ */ 7445 #define MSCAN_REIDR2_REID14_REID7_MASK (0xFFU) 7446 #define MSCAN_REIDR2_REID14_REID7_SHIFT (0U) 7447 /*! REID14_REID7 - Extended Format Identifier 14-7 7448 */ 7449 #define MSCAN_REIDR2_REID14_REID7(x) (((uint8_t)(((uint8_t)(x)) << MSCAN_REIDR2_REID14_REID7_SHIFT)) & MSCAN_REIDR2_REID14_REID7_MASK) 7450 /*! @} */ 7451 7452 /*! @name REIDR3 - Receive Extended Identifier Register 3 */ 7453 /*! @{ */ 7454 #define MSCAN_REIDR3_RERTR_MASK (0x1U) 7455 #define MSCAN_REIDR3_RERTR_SHIFT (0U) 7456 /*! RERTR - Remote Transmission Request 7457 * 0b0..Data frame. 7458 * 0b1..Remote frame. 7459 */ 7460 #define MSCAN_REIDR3_RERTR(x) (((uint8_t)(((uint8_t)(x)) << MSCAN_REIDR3_RERTR_SHIFT)) & MSCAN_REIDR3_RERTR_MASK) 7461 #define MSCAN_REIDR3_REID6_REID0_MASK (0xFEU) 7462 #define MSCAN_REIDR3_REID6_REID0_SHIFT (1U) 7463 /*! REID6_REID0 - Extended Format Identifier 6-0 7464 */ 7465 #define MSCAN_REIDR3_REID6_REID0(x) (((uint8_t)(((uint8_t)(x)) << MSCAN_REIDR3_REID6_REID0_SHIFT)) & MSCAN_REIDR3_REID6_REID0_MASK) 7466 /*! @} */ 7467 7468 /*! @name REDSR - Receive Extended Data Segment Register N */ 7469 /*! @{ */ 7470 #define MSCAN_REDSR_RDB_MASK (0xFFU) 7471 #define MSCAN_REDSR_RDB_SHIFT (0U) 7472 /*! RDB - Data Bits 7473 */ 7474 #define MSCAN_REDSR_RDB(x) (((uint8_t)(((uint8_t)(x)) << MSCAN_REDSR_RDB_SHIFT)) & MSCAN_REDSR_RDB_MASK) 7475 /*! @} */ 7476 7477 /* The count of MSCAN_REDSR */ 7478 #define MSCAN_REDSR_COUNT (8U) 7479 7480 /*! @name RDLR - Receive Data Length Register */ 7481 /*! @{ */ 7482 #define MSCAN_RDLR_RDLC_MASK (0xFU) 7483 #define MSCAN_RDLR_RDLC_SHIFT (0U) 7484 /*! RDLC - Data Length Code Bits 7485 * 0b0000..0 7486 * 0b0001..1 7487 * 0b0010..2 7488 * 0b0011..3 7489 * 0b0100..4 7490 * 0b0101..5 7491 * 0b0110..6 7492 * 0b0111..7 7493 * 0b1000..8 7494 */ 7495 #define MSCAN_RDLR_RDLC(x) (((uint8_t)(((uint8_t)(x)) << MSCAN_RDLR_RDLC_SHIFT)) & MSCAN_RDLR_RDLC_MASK) 7496 /*! @} */ 7497 7498 /*! @name RTSRH - Receive Time Stamp Register High */ 7499 /*! @{ */ 7500 #define MSCAN_RTSRH_RTS_MASK (0xFFU) 7501 #define MSCAN_RTSRH_RTS_SHIFT (0U) 7502 /*! RTS - Time Stamp 7503 */ 7504 #define MSCAN_RTSRH_RTS(x) (((uint8_t)(((uint8_t)(x)) << MSCAN_RTSRH_RTS_SHIFT)) & MSCAN_RTSRH_RTS_MASK) 7505 /*! @} */ 7506 7507 /*! @name RTSRL - Receive Time Stamp Register Low */ 7508 /*! @{ */ 7509 #define MSCAN_RTSRL_RTS_MASK (0xFFU) 7510 #define MSCAN_RTSRL_RTS_SHIFT (0U) 7511 /*! RTS - Time Stamp 7512 */ 7513 #define MSCAN_RTSRL_RTS(x) (((uint8_t)(((uint8_t)(x)) << MSCAN_RTSRL_RTS_SHIFT)) & MSCAN_RTSRL_RTS_MASK) 7514 /*! @} */ 7515 7516 /*! @name TEIDR0 - Transmit Extended Identifier Register 0 */ 7517 /*! @{ */ 7518 #define MSCAN_TEIDR0_TEID28_TEID21_MASK (0xFFU) 7519 #define MSCAN_TEIDR0_TEID28_TEID21_SHIFT (0U) 7520 /*! TEID28_TEID21 - Extended Format Identifier 7521 */ 7522 #define MSCAN_TEIDR0_TEID28_TEID21(x) (((uint8_t)(((uint8_t)(x)) << MSCAN_TEIDR0_TEID28_TEID21_SHIFT)) & MSCAN_TEIDR0_TEID28_TEID21_MASK) 7523 /*! @} */ 7524 7525 /*! @name TSIDR0 - Transmit Standard Identifier Register 0 */ 7526 /*! @{ */ 7527 #define MSCAN_TSIDR0_TSID10_TSID3_MASK (0xFFU) 7528 #define MSCAN_TSIDR0_TSID10_TSID3_SHIFT (0U) 7529 /*! TSID10_TSID3 - Standard Format Identifier 7530 */ 7531 #define MSCAN_TSIDR0_TSID10_TSID3(x) (((uint8_t)(((uint8_t)(x)) << MSCAN_TSIDR0_TSID10_TSID3_SHIFT)) & MSCAN_TSIDR0_TSID10_TSID3_MASK) 7532 /*! @} */ 7533 7534 /*! @name TEIDR1 - Transmit Extended Identifier Register 1 */ 7535 /*! @{ */ 7536 #define MSCAN_TEIDR1_TEID17_TEID15_MASK (0x7U) 7537 #define MSCAN_TEIDR1_TEID17_TEID15_SHIFT (0U) 7538 /*! TEID17_TEID15 - Extended Format Identifier 17-15 7539 */ 7540 #define MSCAN_TEIDR1_TEID17_TEID15(x) (((uint8_t)(((uint8_t)(x)) << MSCAN_TEIDR1_TEID17_TEID15_SHIFT)) & MSCAN_TEIDR1_TEID17_TEID15_MASK) 7541 #define MSCAN_TEIDR1_TEIDE_MASK (0x8U) 7542 #define MSCAN_TEIDR1_TEIDE_SHIFT (3U) 7543 /*! TEIDE - ID Extended 7544 * 0b0..Standard format (11 bit). 7545 * 0b1..Extended format (29 bit). 7546 */ 7547 #define MSCAN_TEIDR1_TEIDE(x) (((uint8_t)(((uint8_t)(x)) << MSCAN_TEIDR1_TEIDE_SHIFT)) & MSCAN_TEIDR1_TEIDE_MASK) 7548 #define MSCAN_TEIDR1_TSRR_MASK (0x10U) 7549 #define MSCAN_TEIDR1_TSRR_SHIFT (4U) 7550 /*! TSRR - Substitute Remote Request 7551 */ 7552 #define MSCAN_TEIDR1_TSRR(x) (((uint8_t)(((uint8_t)(x)) << MSCAN_TEIDR1_TSRR_SHIFT)) & MSCAN_TEIDR1_TSRR_MASK) 7553 #define MSCAN_TEIDR1_TEID20_TEID18_MASK (0xE0U) 7554 #define MSCAN_TEIDR1_TEID20_TEID18_SHIFT (5U) 7555 /*! TEID20_TEID18 - Extended Format Identifier 20-18 7556 */ 7557 #define MSCAN_TEIDR1_TEID20_TEID18(x) (((uint8_t)(((uint8_t)(x)) << MSCAN_TEIDR1_TEID20_TEID18_SHIFT)) & MSCAN_TEIDR1_TEID20_TEID18_MASK) 7558 /*! @} */ 7559 7560 /*! @name TSIDR1 - Transmit Standard Identifier Register 1 */ 7561 /*! @{ */ 7562 #define MSCAN_TSIDR1_TSIDE_MASK (0x8U) 7563 #define MSCAN_TSIDR1_TSIDE_SHIFT (3U) 7564 /*! TSIDE - ID Extended 7565 * 0b0..Standard format (11 bit). 7566 * 0b1..Extended format (29 bit). 7567 */ 7568 #define MSCAN_TSIDR1_TSIDE(x) (((uint8_t)(((uint8_t)(x)) << MSCAN_TSIDR1_TSIDE_SHIFT)) & MSCAN_TSIDR1_TSIDE_MASK) 7569 #define MSCAN_TSIDR1_TSRTR_MASK (0x10U) 7570 #define MSCAN_TSIDR1_TSRTR_SHIFT (4U) 7571 /*! TSRTR - Remote Transmission Request 7572 * 0b0..Data frame. 7573 * 0b1..Remote frame. 7574 */ 7575 #define MSCAN_TSIDR1_TSRTR(x) (((uint8_t)(((uint8_t)(x)) << MSCAN_TSIDR1_TSRTR_SHIFT)) & MSCAN_TSIDR1_TSRTR_MASK) 7576 #define MSCAN_TSIDR1_TSID2_TSID0_MASK (0xE0U) 7577 #define MSCAN_TSIDR1_TSID2_TSID0_SHIFT (5U) 7578 /*! TSID2_TSID0 - Standard Format Identifier 2-0 7579 */ 7580 #define MSCAN_TSIDR1_TSID2_TSID0(x) (((uint8_t)(((uint8_t)(x)) << MSCAN_TSIDR1_TSID2_TSID0_SHIFT)) & MSCAN_TSIDR1_TSID2_TSID0_MASK) 7581 /*! @} */ 7582 7583 /*! @name TEIDR2 - Transmit Extended Identifier Register 2 */ 7584 /*! @{ */ 7585 #define MSCAN_TEIDR2_TEID14_TEID7_MASK (0xFFU) 7586 #define MSCAN_TEIDR2_TEID14_TEID7_SHIFT (0U) 7587 /*! TEID14_TEID7 - Extended Format Identifier 14-7 7588 */ 7589 #define MSCAN_TEIDR2_TEID14_TEID7(x) (((uint8_t)(((uint8_t)(x)) << MSCAN_TEIDR2_TEID14_TEID7_SHIFT)) & MSCAN_TEIDR2_TEID14_TEID7_MASK) 7590 /*! @} */ 7591 7592 /*! @name TEIDR3 - Transmit Extended Identifier Register 3 */ 7593 /*! @{ */ 7594 #define MSCAN_TEIDR3_TERTR_MASK (0x1U) 7595 #define MSCAN_TEIDR3_TERTR_SHIFT (0U) 7596 /*! TERTR - Remote Transmission Request 7597 * 0b0..Data frame. 7598 * 0b1..Remote frame. 7599 */ 7600 #define MSCAN_TEIDR3_TERTR(x) (((uint8_t)(((uint8_t)(x)) << MSCAN_TEIDR3_TERTR_SHIFT)) & MSCAN_TEIDR3_TERTR_MASK) 7601 #define MSCAN_TEIDR3_TEID6_TEID0_MASK (0xFEU) 7602 #define MSCAN_TEIDR3_TEID6_TEID0_SHIFT (1U) 7603 /*! TEID6_TEID0 - Extended Format Identifier 6-0 7604 */ 7605 #define MSCAN_TEIDR3_TEID6_TEID0(x) (((uint8_t)(((uint8_t)(x)) << MSCAN_TEIDR3_TEID6_TEID0_SHIFT)) & MSCAN_TEIDR3_TEID6_TEID0_MASK) 7606 /*! @} */ 7607 7608 /*! @name TEDSR - Transmit Extended Data Segment Register N */ 7609 /*! @{ */ 7610 #define MSCAN_TEDSR_TDB_MASK (0xFFU) 7611 #define MSCAN_TEDSR_TDB_SHIFT (0U) 7612 /*! TDB - Data Bits 7613 */ 7614 #define MSCAN_TEDSR_TDB(x) (((uint8_t)(((uint8_t)(x)) << MSCAN_TEDSR_TDB_SHIFT)) & MSCAN_TEDSR_TDB_MASK) 7615 /*! @} */ 7616 7617 /* The count of MSCAN_TEDSR */ 7618 #define MSCAN_TEDSR_COUNT (8U) 7619 7620 /*! @name TDLR - Transmit Data Length Register */ 7621 /*! @{ */ 7622 #define MSCAN_TDLR_TDLC_MASK (0xFU) 7623 #define MSCAN_TDLR_TDLC_SHIFT (0U) 7624 /*! TDLC - Data Length Code Bits 7625 * 0b0000..0 7626 * 0b0001..1 7627 * 0b0010..2 7628 * 0b0011..3 7629 * 0b0100..4 7630 * 0b0101..5 7631 * 0b0110..6 7632 * 0b0111..7 7633 * 0b1000..8 7634 */ 7635 #define MSCAN_TDLR_TDLC(x) (((uint8_t)(((uint8_t)(x)) << MSCAN_TDLR_TDLC_SHIFT)) & MSCAN_TDLR_TDLC_MASK) 7636 /*! @} */ 7637 7638 /*! @name TBPR - Transmit Buffer Priority Register */ 7639 /*! @{ */ 7640 #define MSCAN_TBPR_PRIO_MASK (0xFFU) 7641 #define MSCAN_TBPR_PRIO_SHIFT (0U) 7642 /*! PRIO - Priority 7643 */ 7644 #define MSCAN_TBPR_PRIO(x) (((uint8_t)(((uint8_t)(x)) << MSCAN_TBPR_PRIO_SHIFT)) & MSCAN_TBPR_PRIO_MASK) 7645 /*! @} */ 7646 7647 /*! @name TTSRH - Transmit Time Stamp Register High */ 7648 /*! @{ */ 7649 #define MSCAN_TTSRH_TTS_MASK (0xFFU) 7650 #define MSCAN_TTSRH_TTS_SHIFT (0U) 7651 /*! TTS - Time Stamp 7652 */ 7653 #define MSCAN_TTSRH_TTS(x) (((uint8_t)(((uint8_t)(x)) << MSCAN_TTSRH_TTS_SHIFT)) & MSCAN_TTSRH_TTS_MASK) 7654 /*! @} */ 7655 7656 /*! @name TTSRL - Transmit Time Stamp Register Low */ 7657 /*! @{ */ 7658 #define MSCAN_TTSRL_TTS_MASK (0xFFU) 7659 #define MSCAN_TTSRL_TTS_SHIFT (0U) 7660 /*! TTS - Time Stamp 7661 */ 7662 #define MSCAN_TTSRL_TTS(x) (((uint8_t)(((uint8_t)(x)) << MSCAN_TTSRL_TTS_SHIFT)) & MSCAN_TTSRL_TTS_MASK) 7663 /*! @} */ 7664 7665 7666 /*! 7667 * @} 7668 */ /* end of group MSCAN_Register_Masks */ 7669 7670 7671 /* MSCAN - Peripheral instance base addresses */ 7672 /** Peripheral MSCAN base address */ 7673 #define MSCAN_BASE (0x40024000u) 7674 /** Peripheral MSCAN base pointer */ 7675 #define MSCAN ((MSCAN_Type *)MSCAN_BASE) 7676 /** Array initializer of MSCAN peripheral base addresses */ 7677 #define MSCAN_BASE_ADDRS { MSCAN_BASE } 7678 /** Array initializer of MSCAN peripheral base pointers */ 7679 #define MSCAN_BASE_PTRS { MSCAN } 7680 /** Interrupt vectors for the MSCAN peripheral type */ 7681 #define MSCAN_RX_IRQS { MSCAN_Rx_IRQn } 7682 #define MSCAN_TX_IRQS { MSCAN_ORed_IRQn } 7683 #define MSCAN_ERR_IRQS { MSCAN_ORed_IRQn } 7684 #define MSCAN_WAKE_UP_IRQS { MSCAN_ORed_IRQn } 7685 7686 /*! 7687 * @} 7688 */ /* end of group MSCAN_Peripheral_Access_Layer */ 7689 7690 7691 /* ---------------------------------------------------------------------------- 7692 -- MTB Peripheral Access Layer 7693 ---------------------------------------------------------------------------- */ 7694 7695 /*! 7696 * @addtogroup MTB_Peripheral_Access_Layer MTB Peripheral Access Layer 7697 * @{ 7698 */ 7699 7700 /** MTB - Register Layout Typedef */ 7701 typedef struct { 7702 __IO uint32_t POSITION; /**< MTB Position Register, offset: 0x0 */ 7703 __IO uint32_t MASTER; /**< MTB Master Register, offset: 0x4 */ 7704 __IO uint32_t FLOW; /**< MTB Flow Register, offset: 0x8 */ 7705 __I uint32_t BASE; /**< MTB Base Register, offset: 0xC */ 7706 uint8_t RESERVED_0[3824]; 7707 __I uint32_t MODECTRL; /**< Integration Mode Control Register, offset: 0xF00 */ 7708 uint8_t RESERVED_1[156]; 7709 __I uint32_t TAGSET; /**< Claim TAG Set Register, offset: 0xFA0 */ 7710 __I uint32_t TAGCLEAR; /**< Claim TAG Clear Register, offset: 0xFA4 */ 7711 uint8_t RESERVED_2[8]; 7712 __I uint32_t LOCKACCESS; /**< Lock Access Register, offset: 0xFB0 */ 7713 __I uint32_t LOCKSTAT; /**< Lock Status Register, offset: 0xFB4 */ 7714 __I uint32_t AUTHSTAT; /**< Authentication Status Register, offset: 0xFB8 */ 7715 __I uint32_t DEVICEARCH; /**< Device Architecture Register, offset: 0xFBC */ 7716 uint8_t RESERVED_3[8]; 7717 __I uint32_t DEVICECFG; /**< Device Configuration Register, offset: 0xFC8 */ 7718 __I uint32_t DEVICETYPID; /**< Device Type Identifier Register, offset: 0xFCC */ 7719 __I uint32_t PERIPHID4; /**< Peripheral ID Register, offset: 0xFD0 */ 7720 __I uint32_t PERIPHID5; /**< Peripheral ID Register, offset: 0xFD4 */ 7721 __I uint32_t PERIPHID6; /**< Peripheral ID Register, offset: 0xFD8 */ 7722 __I uint32_t PERIPHID7; /**< Peripheral ID Register, offset: 0xFDC */ 7723 __I uint32_t PERIPHID0; /**< Peripheral ID Register, offset: 0xFE0 */ 7724 __I uint32_t PERIPHID1; /**< Peripheral ID Register, offset: 0xFE4 */ 7725 __I uint32_t PERIPHID2; /**< Peripheral ID Register, offset: 0xFE8 */ 7726 __I uint32_t PERIPHID3; /**< Peripheral ID Register, offset: 0xFEC */ 7727 __I uint32_t COMPID[4]; /**< Component ID Register, array offset: 0xFF0, array step: 0x4 */ 7728 } MTB_Type; 7729 7730 /* ---------------------------------------------------------------------------- 7731 -- MTB Register Masks 7732 ---------------------------------------------------------------------------- */ 7733 7734 /*! 7735 * @addtogroup MTB_Register_Masks MTB Register Masks 7736 * @{ 7737 */ 7738 7739 /*! @name POSITION - MTB Position Register */ 7740 /*! @{ */ 7741 #define MTB_POSITION_WRAP_MASK (0x4U) 7742 #define MTB_POSITION_WRAP_SHIFT (2U) 7743 /*! WRAP - WRAP 7744 */ 7745 #define MTB_POSITION_WRAP(x) (((uint32_t)(((uint32_t)(x)) << MTB_POSITION_WRAP_SHIFT)) & MTB_POSITION_WRAP_MASK) 7746 #define MTB_POSITION_POINTER_MASK (0xFFFFFFF8U) 7747 #define MTB_POSITION_POINTER_SHIFT (3U) 7748 /*! POINTER - Trace Packet Address Pointer[28:0] 7749 */ 7750 #define MTB_POSITION_POINTER(x) (((uint32_t)(((uint32_t)(x)) << MTB_POSITION_POINTER_SHIFT)) & MTB_POSITION_POINTER_MASK) 7751 /*! @} */ 7752 7753 /*! @name MASTER - MTB Master Register */ 7754 /*! @{ */ 7755 #define MTB_MASTER_MASK_MASK (0x1FU) 7756 #define MTB_MASTER_MASK_SHIFT (0U) 7757 /*! MASK - Mask 7758 */ 7759 #define MTB_MASTER_MASK(x) (((uint32_t)(((uint32_t)(x)) << MTB_MASTER_MASK_SHIFT)) & MTB_MASTER_MASK_MASK) 7760 #define MTB_MASTER_TSTARTEN_MASK (0x20U) 7761 #define MTB_MASTER_TSTARTEN_SHIFT (5U) 7762 /*! TSTARTEN - Trace Start Input Enable 7763 */ 7764 #define MTB_MASTER_TSTARTEN(x) (((uint32_t)(((uint32_t)(x)) << MTB_MASTER_TSTARTEN_SHIFT)) & MTB_MASTER_TSTARTEN_MASK) 7765 #define MTB_MASTER_TSTOPEN_MASK (0x40U) 7766 #define MTB_MASTER_TSTOPEN_SHIFT (6U) 7767 /*! TSTOPEN - Trace Stop Input Enable 7768 */ 7769 #define MTB_MASTER_TSTOPEN(x) (((uint32_t)(((uint32_t)(x)) << MTB_MASTER_TSTOPEN_SHIFT)) & MTB_MASTER_TSTOPEN_MASK) 7770 #define MTB_MASTER_SFRWPRIV_MASK (0x80U) 7771 #define MTB_MASTER_SFRWPRIV_SHIFT (7U) 7772 /*! SFRWPRIV - Special Function Register Write Privilege 7773 */ 7774 #define MTB_MASTER_SFRWPRIV(x) (((uint32_t)(((uint32_t)(x)) << MTB_MASTER_SFRWPRIV_SHIFT)) & MTB_MASTER_SFRWPRIV_MASK) 7775 #define MTB_MASTER_RAMPRIV_MASK (0x100U) 7776 #define MTB_MASTER_RAMPRIV_SHIFT (8U) 7777 /*! RAMPRIV - RAM Privilege 7778 */ 7779 #define MTB_MASTER_RAMPRIV(x) (((uint32_t)(((uint32_t)(x)) << MTB_MASTER_RAMPRIV_SHIFT)) & MTB_MASTER_RAMPRIV_MASK) 7780 #define MTB_MASTER_HALTREQ_MASK (0x200U) 7781 #define MTB_MASTER_HALTREQ_SHIFT (9U) 7782 /*! HALTREQ - Halt Request 7783 */ 7784 #define MTB_MASTER_HALTREQ(x) (((uint32_t)(((uint32_t)(x)) << MTB_MASTER_HALTREQ_SHIFT)) & MTB_MASTER_HALTREQ_MASK) 7785 #define MTB_MASTER_EN_MASK (0x80000000U) 7786 #define MTB_MASTER_EN_SHIFT (31U) 7787 /*! EN - Main Trace Enable 7788 */ 7789 #define MTB_MASTER_EN(x) (((uint32_t)(((uint32_t)(x)) << MTB_MASTER_EN_SHIFT)) & MTB_MASTER_EN_MASK) 7790 /*! @} */ 7791 7792 /*! @name FLOW - MTB Flow Register */ 7793 /*! @{ */ 7794 #define MTB_FLOW_AUTOSTOP_MASK (0x1U) 7795 #define MTB_FLOW_AUTOSTOP_SHIFT (0U) 7796 /*! AUTOSTOP - AUTOSTOP 7797 */ 7798 #define MTB_FLOW_AUTOSTOP(x) (((uint32_t)(((uint32_t)(x)) << MTB_FLOW_AUTOSTOP_SHIFT)) & MTB_FLOW_AUTOSTOP_MASK) 7799 #define MTB_FLOW_AUTOHALT_MASK (0x2U) 7800 #define MTB_FLOW_AUTOHALT_SHIFT (1U) 7801 /*! AUTOHALT - AUTOHALT 7802 */ 7803 #define MTB_FLOW_AUTOHALT(x) (((uint32_t)(((uint32_t)(x)) << MTB_FLOW_AUTOHALT_SHIFT)) & MTB_FLOW_AUTOHALT_MASK) 7804 #define MTB_FLOW_WATERMARK_MASK (0xFFFFFFF8U) 7805 #define MTB_FLOW_WATERMARK_SHIFT (3U) 7806 /*! WATERMARK - WATERMARK[28:0] 7807 */ 7808 #define MTB_FLOW_WATERMARK(x) (((uint32_t)(((uint32_t)(x)) << MTB_FLOW_WATERMARK_SHIFT)) & MTB_FLOW_WATERMARK_MASK) 7809 /*! @} */ 7810 7811 /*! @name BASE - MTB Base Register */ 7812 /*! @{ */ 7813 #define MTB_BASE_BASEADDR_MASK (0xFFFFFFFFU) 7814 #define MTB_BASE_BASEADDR_SHIFT (0U) 7815 /*! BASEADDR - BASEADDR 7816 */ 7817 #define MTB_BASE_BASEADDR(x) (((uint32_t)(((uint32_t)(x)) << MTB_BASE_BASEADDR_SHIFT)) & MTB_BASE_BASEADDR_MASK) 7818 /*! @} */ 7819 7820 /*! @name MODECTRL - Integration Mode Control Register */ 7821 /*! @{ */ 7822 #define MTB_MODECTRL_MODECTRL_MASK (0xFFFFFFFFU) 7823 #define MTB_MODECTRL_MODECTRL_SHIFT (0U) 7824 /*! MODECTRL - MODECTRL 7825 */ 7826 #define MTB_MODECTRL_MODECTRL(x) (((uint32_t)(((uint32_t)(x)) << MTB_MODECTRL_MODECTRL_SHIFT)) & MTB_MODECTRL_MODECTRL_MASK) 7827 /*! @} */ 7828 7829 /*! @name TAGSET - Claim TAG Set Register */ 7830 /*! @{ */ 7831 #define MTB_TAGSET_TAGSET_MASK (0xFFFFFFFFU) 7832 #define MTB_TAGSET_TAGSET_SHIFT (0U) 7833 /*! TAGSET - TAGSET 7834 */ 7835 #define MTB_TAGSET_TAGSET(x) (((uint32_t)(((uint32_t)(x)) << MTB_TAGSET_TAGSET_SHIFT)) & MTB_TAGSET_TAGSET_MASK) 7836 /*! @} */ 7837 7838 /*! @name TAGCLEAR - Claim TAG Clear Register */ 7839 /*! @{ */ 7840 #define MTB_TAGCLEAR_TAGCLEAR_MASK (0xFFFFFFFFU) 7841 #define MTB_TAGCLEAR_TAGCLEAR_SHIFT (0U) 7842 /*! TAGCLEAR - TAGCLEAR 7843 */ 7844 #define MTB_TAGCLEAR_TAGCLEAR(x) (((uint32_t)(((uint32_t)(x)) << MTB_TAGCLEAR_TAGCLEAR_SHIFT)) & MTB_TAGCLEAR_TAGCLEAR_MASK) 7845 /*! @} */ 7846 7847 /*! @name LOCKACCESS - Lock Access Register */ 7848 /*! @{ */ 7849 #define MTB_LOCKACCESS_LOCKACCESS_MASK (0xFFFFFFFFU) 7850 #define MTB_LOCKACCESS_LOCKACCESS_SHIFT (0U) 7851 #define MTB_LOCKACCESS_LOCKACCESS(x) (((uint32_t)(((uint32_t)(x)) << MTB_LOCKACCESS_LOCKACCESS_SHIFT)) & MTB_LOCKACCESS_LOCKACCESS_MASK) 7852 /*! @} */ 7853 7854 /*! @name LOCKSTAT - Lock Status Register */ 7855 /*! @{ */ 7856 #define MTB_LOCKSTAT_LOCKSTAT_MASK (0xFFFFFFFFU) 7857 #define MTB_LOCKSTAT_LOCKSTAT_SHIFT (0U) 7858 /*! LOCKSTAT - LOCKSTAT 7859 */ 7860 #define MTB_LOCKSTAT_LOCKSTAT(x) (((uint32_t)(((uint32_t)(x)) << MTB_LOCKSTAT_LOCKSTAT_SHIFT)) & MTB_LOCKSTAT_LOCKSTAT_MASK) 7861 /*! @} */ 7862 7863 /*! @name AUTHSTAT - Authentication Status Register */ 7864 /*! @{ */ 7865 #define MTB_AUTHSTAT_BIT0_MASK (0x1U) 7866 #define MTB_AUTHSTAT_BIT0_SHIFT (0U) 7867 #define MTB_AUTHSTAT_BIT0(x) (((uint32_t)(((uint32_t)(x)) << MTB_AUTHSTAT_BIT0_SHIFT)) & MTB_AUTHSTAT_BIT0_MASK) 7868 #define MTB_AUTHSTAT_BIT2_MASK (0x4U) 7869 #define MTB_AUTHSTAT_BIT2_SHIFT (2U) 7870 /*! BIT2 - BIT2 7871 */ 7872 #define MTB_AUTHSTAT_BIT2(x) (((uint32_t)(((uint32_t)(x)) << MTB_AUTHSTAT_BIT2_SHIFT)) & MTB_AUTHSTAT_BIT2_MASK) 7873 /*! @} */ 7874 7875 /*! @name DEVICEARCH - Device Architecture Register */ 7876 /*! @{ */ 7877 #define MTB_DEVICEARCH_DEVICEARCH_MASK (0xFFFFFFFFU) 7878 #define MTB_DEVICEARCH_DEVICEARCH_SHIFT (0U) 7879 /*! DEVICEARCH - DEVICEARCH 7880 */ 7881 #define MTB_DEVICEARCH_DEVICEARCH(x) (((uint32_t)(((uint32_t)(x)) << MTB_DEVICEARCH_DEVICEARCH_SHIFT)) & MTB_DEVICEARCH_DEVICEARCH_MASK) 7882 /*! @} */ 7883 7884 /*! @name DEVICECFG - Device Configuration Register */ 7885 /*! @{ */ 7886 #define MTB_DEVICECFG_DEVICECFG_MASK (0xFFFFFFFFU) 7887 #define MTB_DEVICECFG_DEVICECFG_SHIFT (0U) 7888 /*! DEVICECFG - DEVICECFG 7889 */ 7890 #define MTB_DEVICECFG_DEVICECFG(x) (((uint32_t)(((uint32_t)(x)) << MTB_DEVICECFG_DEVICECFG_SHIFT)) & MTB_DEVICECFG_DEVICECFG_MASK) 7891 /*! @} */ 7892 7893 /*! @name DEVICETYPID - Device Type Identifier Register */ 7894 /*! @{ */ 7895 #define MTB_DEVICETYPID_DEVICETYPID_MASK (0xFFFFFFFFU) 7896 #define MTB_DEVICETYPID_DEVICETYPID_SHIFT (0U) 7897 /*! DEVICETYPID - DEVICETYPID 7898 */ 7899 #define MTB_DEVICETYPID_DEVICETYPID(x) (((uint32_t)(((uint32_t)(x)) << MTB_DEVICETYPID_DEVICETYPID_SHIFT)) & MTB_DEVICETYPID_DEVICETYPID_MASK) 7900 /*! @} */ 7901 7902 /*! @name PERIPHID4 - Peripheral ID Register */ 7903 /*! @{ */ 7904 #define MTB_PERIPHID4_PERIPHID_MASK (0xFFFFFFFFU) 7905 #define MTB_PERIPHID4_PERIPHID_SHIFT (0U) 7906 /*! PERIPHID - PERIPHID 7907 */ 7908 #define MTB_PERIPHID4_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << MTB_PERIPHID4_PERIPHID_SHIFT)) & MTB_PERIPHID4_PERIPHID_MASK) 7909 /*! @} */ 7910 7911 /*! @name PERIPHID5 - Peripheral ID Register */ 7912 /*! @{ */ 7913 #define MTB_PERIPHID5_PERIPHID_MASK (0xFFFFFFFFU) 7914 #define MTB_PERIPHID5_PERIPHID_SHIFT (0U) 7915 /*! PERIPHID - PERIPHID 7916 */ 7917 #define MTB_PERIPHID5_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << MTB_PERIPHID5_PERIPHID_SHIFT)) & MTB_PERIPHID5_PERIPHID_MASK) 7918 /*! @} */ 7919 7920 /*! @name PERIPHID6 - Peripheral ID Register */ 7921 /*! @{ */ 7922 #define MTB_PERIPHID6_PERIPHID_MASK (0xFFFFFFFFU) 7923 #define MTB_PERIPHID6_PERIPHID_SHIFT (0U) 7924 /*! PERIPHID - PERIPHID 7925 */ 7926 #define MTB_PERIPHID6_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << MTB_PERIPHID6_PERIPHID_SHIFT)) & MTB_PERIPHID6_PERIPHID_MASK) 7927 /*! @} */ 7928 7929 /*! @name PERIPHID7 - Peripheral ID Register */ 7930 /*! @{ */ 7931 #define MTB_PERIPHID7_PERIPHID_MASK (0xFFFFFFFFU) 7932 #define MTB_PERIPHID7_PERIPHID_SHIFT (0U) 7933 /*! PERIPHID - PERIPHID 7934 */ 7935 #define MTB_PERIPHID7_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << MTB_PERIPHID7_PERIPHID_SHIFT)) & MTB_PERIPHID7_PERIPHID_MASK) 7936 /*! @} */ 7937 7938 /*! @name PERIPHID0 - Peripheral ID Register */ 7939 /*! @{ */ 7940 #define MTB_PERIPHID0_PERIPHID_MASK (0xFFFFFFFFU) 7941 #define MTB_PERIPHID0_PERIPHID_SHIFT (0U) 7942 /*! PERIPHID - PERIPHID 7943 */ 7944 #define MTB_PERIPHID0_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << MTB_PERIPHID0_PERIPHID_SHIFT)) & MTB_PERIPHID0_PERIPHID_MASK) 7945 /*! @} */ 7946 7947 /*! @name PERIPHID1 - Peripheral ID Register */ 7948 /*! @{ */ 7949 #define MTB_PERIPHID1_PERIPHID_MASK (0xFFFFFFFFU) 7950 #define MTB_PERIPHID1_PERIPHID_SHIFT (0U) 7951 /*! PERIPHID - PERIPHID 7952 */ 7953 #define MTB_PERIPHID1_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << MTB_PERIPHID1_PERIPHID_SHIFT)) & MTB_PERIPHID1_PERIPHID_MASK) 7954 /*! @} */ 7955 7956 /*! @name PERIPHID2 - Peripheral ID Register */ 7957 /*! @{ */ 7958 #define MTB_PERIPHID2_PERIPHID_MASK (0xFFFFFFFFU) 7959 #define MTB_PERIPHID2_PERIPHID_SHIFT (0U) 7960 /*! PERIPHID - PERIPHID 7961 */ 7962 #define MTB_PERIPHID2_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << MTB_PERIPHID2_PERIPHID_SHIFT)) & MTB_PERIPHID2_PERIPHID_MASK) 7963 /*! @} */ 7964 7965 /*! @name PERIPHID3 - Peripheral ID Register */ 7966 /*! @{ */ 7967 #define MTB_PERIPHID3_PERIPHID_MASK (0xFFFFFFFFU) 7968 #define MTB_PERIPHID3_PERIPHID_SHIFT (0U) 7969 /*! PERIPHID - PERIPHID 7970 */ 7971 #define MTB_PERIPHID3_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << MTB_PERIPHID3_PERIPHID_SHIFT)) & MTB_PERIPHID3_PERIPHID_MASK) 7972 /*! @} */ 7973 7974 /*! @name COMPID - Component ID Register */ 7975 /*! @{ */ 7976 #define MTB_COMPID_COMPID_MASK (0xFFFFFFFFU) 7977 #define MTB_COMPID_COMPID_SHIFT (0U) 7978 /*! COMPID - Component ID 7979 */ 7980 #define MTB_COMPID_COMPID(x) (((uint32_t)(((uint32_t)(x)) << MTB_COMPID_COMPID_SHIFT)) & MTB_COMPID_COMPID_MASK) 7981 /*! @} */ 7982 7983 /* The count of MTB_COMPID */ 7984 #define MTB_COMPID_COUNT (4U) 7985 7986 7987 /*! 7988 * @} 7989 */ /* end of group MTB_Register_Masks */ 7990 7991 7992 /* MTB - Peripheral instance base addresses */ 7993 /** Peripheral MTB base address */ 7994 #define MTB_BASE (0xF0000000u) 7995 /** Peripheral MTB base pointer */ 7996 #define MTB ((MTB_Type *)MTB_BASE) 7997 /** Array initializer of MTB peripheral base addresses */ 7998 #define MTB_BASE_ADDRS { MTB_BASE } 7999 /** Array initializer of MTB peripheral base pointers */ 8000 #define MTB_BASE_PTRS { MTB } 8001 8002 /*! 8003 * @} 8004 */ /* end of group MTB_Peripheral_Access_Layer */ 8005 8006 8007 /* ---------------------------------------------------------------------------- 8008 -- MTBDWT Peripheral Access Layer 8009 ---------------------------------------------------------------------------- */ 8010 8011 /*! 8012 * @addtogroup MTBDWT_Peripheral_Access_Layer MTBDWT Peripheral Access Layer 8013 * @{ 8014 */ 8015 8016 /** MTBDWT - Register Layout Typedef */ 8017 typedef struct { 8018 __I uint32_t CTRL; /**< MTB DWT Control Register, offset: 0x0 */ 8019 uint8_t RESERVED_0[28]; 8020 struct { /* offset: 0x20, array step: 0x10 */ 8021 __IO uint32_t COMP; /**< MTB_DWT Comparator Register, array offset: 0x20, array step: 0x10 */ 8022 __IO uint32_t MASK; /**< MTB_DWT Comparator Mask Register, array offset: 0x24, array step: 0x10 */ 8023 __IO uint32_t FCT; /**< MTB_DWT Comparator Function Register 0..MTB_DWT Comparator Function Register 1, array offset: 0x28, array step: 0x10 */ 8024 uint8_t RESERVED_0[4]; 8025 } COMPARATOR[2]; 8026 uint8_t RESERVED_1[448]; 8027 __IO uint32_t TBCTRL; /**< MTB_DWT Trace Buffer Control Register, offset: 0x200 */ 8028 uint8_t RESERVED_2[3524]; 8029 __I uint32_t DEVICECFG; /**< Device Configuration Register, offset: 0xFC8 */ 8030 __I uint32_t DEVICETYPID; /**< Device Type Identifier Register, offset: 0xFCC */ 8031 __I uint32_t PERIPHID4; /**< Peripheral ID Register, offset: 0xFD0 */ 8032 __I uint32_t PERIPHID5; /**< Peripheral ID Register, offset: 0xFD4 */ 8033 __I uint32_t PERIPHID6; /**< Peripheral ID Register, offset: 0xFD8 */ 8034 __I uint32_t PERIPHID7; /**< Peripheral ID Register, offset: 0xFDC */ 8035 __I uint32_t PERIPHID0; /**< Peripheral ID Register, offset: 0xFE0 */ 8036 __I uint32_t PERIPHID1; /**< Peripheral ID Register, offset: 0xFE4 */ 8037 __I uint32_t PERIPHID2; /**< Peripheral ID Register, offset: 0xFE8 */ 8038 __I uint32_t PERIPHID3; /**< Peripheral ID Register, offset: 0xFEC */ 8039 __I uint32_t COMPID[4]; /**< Component ID Register, array offset: 0xFF0, array step: 0x4 */ 8040 } MTBDWT_Type; 8041 8042 /* ---------------------------------------------------------------------------- 8043 -- MTBDWT Register Masks 8044 ---------------------------------------------------------------------------- */ 8045 8046 /*! 8047 * @addtogroup MTBDWT_Register_Masks MTBDWT Register Masks 8048 * @{ 8049 */ 8050 8051 /*! @name CTRL - MTB DWT Control Register */ 8052 /*! @{ */ 8053 #define MTBDWT_CTRL_DWTCFGCTRL_MASK (0xFFFFFFFU) 8054 #define MTBDWT_CTRL_DWTCFGCTRL_SHIFT (0U) 8055 /*! DWTCFGCTRL - DWT configuration controls 8056 */ 8057 #define MTBDWT_CTRL_DWTCFGCTRL(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_CTRL_DWTCFGCTRL_SHIFT)) & MTBDWT_CTRL_DWTCFGCTRL_MASK) 8058 #define MTBDWT_CTRL_NUMCMP_MASK (0xF0000000U) 8059 #define MTBDWT_CTRL_NUMCMP_SHIFT (28U) 8060 /*! NUMCMP - Number of comparators 8061 */ 8062 #define MTBDWT_CTRL_NUMCMP(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_CTRL_NUMCMP_SHIFT)) & MTBDWT_CTRL_NUMCMP_MASK) 8063 /*! @} */ 8064 8065 /*! @name COMP - MTB_DWT Comparator Register */ 8066 /*! @{ */ 8067 #define MTBDWT_COMP_COMP_MASK (0xFFFFFFFFU) 8068 #define MTBDWT_COMP_COMP_SHIFT (0U) 8069 /*! COMP - Reference value for comparison 8070 */ 8071 #define MTBDWT_COMP_COMP(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_COMP_COMP_SHIFT)) & MTBDWT_COMP_COMP_MASK) 8072 /*! @} */ 8073 8074 /* The count of MTBDWT_COMP */ 8075 #define MTBDWT_COMP_COUNT (2U) 8076 8077 /*! @name MASK - MTB_DWT Comparator Mask Register */ 8078 /*! @{ */ 8079 #define MTBDWT_MASK_MASK_MASK (0x1FU) 8080 #define MTBDWT_MASK_MASK_SHIFT (0U) 8081 /*! MASK - MASK 8082 */ 8083 #define MTBDWT_MASK_MASK(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_MASK_MASK_SHIFT)) & MTBDWT_MASK_MASK_MASK) 8084 /*! @} */ 8085 8086 /* The count of MTBDWT_MASK */ 8087 #define MTBDWT_MASK_COUNT (2U) 8088 8089 /*! @name FCT - MTB_DWT Comparator Function Register 0..MTB_DWT Comparator Function Register 1 */ 8090 /*! @{ */ 8091 #define MTBDWT_FCT_FUNCTION_MASK (0xFU) 8092 #define MTBDWT_FCT_FUNCTION_SHIFT (0U) 8093 /*! FUNCTION - Function 8094 * 0b0000..Disabled. 8095 * 0b0100..Instruction fetch. 8096 * 0b0101..Data operand read. 8097 * 0b0110..Data operand write. 8098 * 0b0111..Data operand (read + write). 8099 */ 8100 #define MTBDWT_FCT_FUNCTION(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_FCT_FUNCTION_SHIFT)) & MTBDWT_FCT_FUNCTION_MASK) 8101 #define MTBDWT_FCT_DATAVMATCH_MASK (0x100U) 8102 #define MTBDWT_FCT_DATAVMATCH_SHIFT (8U) 8103 /*! DATAVMATCH - Data Value Match 8104 * 0b0..Perform address comparison. 8105 * 0b1..Perform data value comparison. 8106 */ 8107 #define MTBDWT_FCT_DATAVMATCH(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_FCT_DATAVMATCH_SHIFT)) & MTBDWT_FCT_DATAVMATCH_MASK) 8108 #define MTBDWT_FCT_DATAVSIZE_MASK (0xC00U) 8109 #define MTBDWT_FCT_DATAVSIZE_SHIFT (10U) 8110 /*! DATAVSIZE - Data Value Size 8111 * 0b00..Byte. 8112 * 0b01..Halfword. 8113 * 0b10..Word. 8114 * 0b11..Reserved. Any attempts to use this value results in UNPREDICTABLE behavior. 8115 */ 8116 #define MTBDWT_FCT_DATAVSIZE(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_FCT_DATAVSIZE_SHIFT)) & MTBDWT_FCT_DATAVSIZE_MASK) 8117 #define MTBDWT_FCT_DATAVADDR0_MASK (0xF000U) 8118 #define MTBDWT_FCT_DATAVADDR0_SHIFT (12U) 8119 /*! DATAVADDR0 - Data Value Address 0 8120 */ 8121 #define MTBDWT_FCT_DATAVADDR0(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_FCT_DATAVADDR0_SHIFT)) & MTBDWT_FCT_DATAVADDR0_MASK) 8122 #define MTBDWT_FCT_MATCHED_MASK (0x1000000U) 8123 #define MTBDWT_FCT_MATCHED_SHIFT (24U) 8124 /*! MATCHED - Comparator match 8125 * 0b0..No match. 8126 * 0b1..Match occurred. 8127 */ 8128 #define MTBDWT_FCT_MATCHED(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_FCT_MATCHED_SHIFT)) & MTBDWT_FCT_MATCHED_MASK) 8129 /*! @} */ 8130 8131 /* The count of MTBDWT_FCT */ 8132 #define MTBDWT_FCT_COUNT (2U) 8133 8134 /*! @name TBCTRL - MTB_DWT Trace Buffer Control Register */ 8135 /*! @{ */ 8136 #define MTBDWT_TBCTRL_ACOMP0_MASK (0x1U) 8137 #define MTBDWT_TBCTRL_ACOMP0_SHIFT (0U) 8138 /*! ACOMP0 - Action based on Comparator 0 match 8139 * 0b0..Trigger TSTOP based on the assertion of MTBDWT_FCT0[MATCHED]. 8140 * 0b1..Trigger TSTART based on the assertion of MTBDWT_FCT0[MATCHED]. 8141 */ 8142 #define MTBDWT_TBCTRL_ACOMP0(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_TBCTRL_ACOMP0_SHIFT)) & MTBDWT_TBCTRL_ACOMP0_MASK) 8143 #define MTBDWT_TBCTRL_ACOMP1_MASK (0x2U) 8144 #define MTBDWT_TBCTRL_ACOMP1_SHIFT (1U) 8145 /*! ACOMP1 - Action based on Comparator 1 match 8146 * 0b0..Trigger TSTOP based on the assertion of MTBDWT_FCT1[MATCHED]. 8147 * 0b1..Trigger TSTART based on the assertion of MTBDWT_FCT1[MATCHED]. 8148 */ 8149 #define MTBDWT_TBCTRL_ACOMP1(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_TBCTRL_ACOMP1_SHIFT)) & MTBDWT_TBCTRL_ACOMP1_MASK) 8150 #define MTBDWT_TBCTRL_NUMCOMP_MASK (0xF0000000U) 8151 #define MTBDWT_TBCTRL_NUMCOMP_SHIFT (28U) 8152 /*! NUMCOMP - Number of Comparators 8153 */ 8154 #define MTBDWT_TBCTRL_NUMCOMP(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_TBCTRL_NUMCOMP_SHIFT)) & MTBDWT_TBCTRL_NUMCOMP_MASK) 8155 /*! @} */ 8156 8157 /*! @name DEVICECFG - Device Configuration Register */ 8158 /*! @{ */ 8159 #define MTBDWT_DEVICECFG_DEVICECFG_MASK (0xFFFFFFFFU) 8160 #define MTBDWT_DEVICECFG_DEVICECFG_SHIFT (0U) 8161 /*! DEVICECFG - DEVICECFG 8162 */ 8163 #define MTBDWT_DEVICECFG_DEVICECFG(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_DEVICECFG_DEVICECFG_SHIFT)) & MTBDWT_DEVICECFG_DEVICECFG_MASK) 8164 /*! @} */ 8165 8166 /*! @name DEVICETYPID - Device Type Identifier Register */ 8167 /*! @{ */ 8168 #define MTBDWT_DEVICETYPID_DEVICETYPID_MASK (0xFFFFFFFFU) 8169 #define MTBDWT_DEVICETYPID_DEVICETYPID_SHIFT (0U) 8170 /*! DEVICETYPID - DEVICETYPID 8171 */ 8172 #define MTBDWT_DEVICETYPID_DEVICETYPID(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_DEVICETYPID_DEVICETYPID_SHIFT)) & MTBDWT_DEVICETYPID_DEVICETYPID_MASK) 8173 /*! @} */ 8174 8175 /*! @name PERIPHID4 - Peripheral ID Register */ 8176 /*! @{ */ 8177 #define MTBDWT_PERIPHID4_PERIPHID_MASK (0xFFFFFFFFU) 8178 #define MTBDWT_PERIPHID4_PERIPHID_SHIFT (0U) 8179 /*! PERIPHID - PERIPHID 8180 */ 8181 #define MTBDWT_PERIPHID4_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_PERIPHID4_PERIPHID_SHIFT)) & MTBDWT_PERIPHID4_PERIPHID_MASK) 8182 /*! @} */ 8183 8184 /*! @name PERIPHID5 - Peripheral ID Register */ 8185 /*! @{ */ 8186 #define MTBDWT_PERIPHID5_PERIPHID_MASK (0xFFFFFFFFU) 8187 #define MTBDWT_PERIPHID5_PERIPHID_SHIFT (0U) 8188 /*! PERIPHID - PERIPHID 8189 */ 8190 #define MTBDWT_PERIPHID5_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_PERIPHID5_PERIPHID_SHIFT)) & MTBDWT_PERIPHID5_PERIPHID_MASK) 8191 /*! @} */ 8192 8193 /*! @name PERIPHID6 - Peripheral ID Register */ 8194 /*! @{ */ 8195 #define MTBDWT_PERIPHID6_PERIPHID_MASK (0xFFFFFFFFU) 8196 #define MTBDWT_PERIPHID6_PERIPHID_SHIFT (0U) 8197 /*! PERIPHID - PERIPHID 8198 */ 8199 #define MTBDWT_PERIPHID6_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_PERIPHID6_PERIPHID_SHIFT)) & MTBDWT_PERIPHID6_PERIPHID_MASK) 8200 /*! @} */ 8201 8202 /*! @name PERIPHID7 - Peripheral ID Register */ 8203 /*! @{ */ 8204 #define MTBDWT_PERIPHID7_PERIPHID_MASK (0xFFFFFFFFU) 8205 #define MTBDWT_PERIPHID7_PERIPHID_SHIFT (0U) 8206 /*! PERIPHID - PERIPHID 8207 */ 8208 #define MTBDWT_PERIPHID7_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_PERIPHID7_PERIPHID_SHIFT)) & MTBDWT_PERIPHID7_PERIPHID_MASK) 8209 /*! @} */ 8210 8211 /*! @name PERIPHID0 - Peripheral ID Register */ 8212 /*! @{ */ 8213 #define MTBDWT_PERIPHID0_PERIPHID_MASK (0xFFFFFFFFU) 8214 #define MTBDWT_PERIPHID0_PERIPHID_SHIFT (0U) 8215 /*! PERIPHID - PERIPHID 8216 */ 8217 #define MTBDWT_PERIPHID0_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_PERIPHID0_PERIPHID_SHIFT)) & MTBDWT_PERIPHID0_PERIPHID_MASK) 8218 /*! @} */ 8219 8220 /*! @name PERIPHID1 - Peripheral ID Register */ 8221 /*! @{ */ 8222 #define MTBDWT_PERIPHID1_PERIPHID_MASK (0xFFFFFFFFU) 8223 #define MTBDWT_PERIPHID1_PERIPHID_SHIFT (0U) 8224 /*! PERIPHID - PERIPHID 8225 */ 8226 #define MTBDWT_PERIPHID1_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_PERIPHID1_PERIPHID_SHIFT)) & MTBDWT_PERIPHID1_PERIPHID_MASK) 8227 /*! @} */ 8228 8229 /*! @name PERIPHID2 - Peripheral ID Register */ 8230 /*! @{ */ 8231 #define MTBDWT_PERIPHID2_PERIPHID_MASK (0xFFFFFFFFU) 8232 #define MTBDWT_PERIPHID2_PERIPHID_SHIFT (0U) 8233 /*! PERIPHID - PERIPHID 8234 */ 8235 #define MTBDWT_PERIPHID2_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_PERIPHID2_PERIPHID_SHIFT)) & MTBDWT_PERIPHID2_PERIPHID_MASK) 8236 /*! @} */ 8237 8238 /*! @name PERIPHID3 - Peripheral ID Register */ 8239 /*! @{ */ 8240 #define MTBDWT_PERIPHID3_PERIPHID_MASK (0xFFFFFFFFU) 8241 #define MTBDWT_PERIPHID3_PERIPHID_SHIFT (0U) 8242 /*! PERIPHID - PERIPHID 8243 */ 8244 #define MTBDWT_PERIPHID3_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_PERIPHID3_PERIPHID_SHIFT)) & MTBDWT_PERIPHID3_PERIPHID_MASK) 8245 /*! @} */ 8246 8247 /*! @name COMPID - Component ID Register */ 8248 /*! @{ */ 8249 #define MTBDWT_COMPID_COMPID_MASK (0xFFFFFFFFU) 8250 #define MTBDWT_COMPID_COMPID_SHIFT (0U) 8251 /*! COMPID - Component ID 8252 */ 8253 #define MTBDWT_COMPID_COMPID(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_COMPID_COMPID_SHIFT)) & MTBDWT_COMPID_COMPID_MASK) 8254 /*! @} */ 8255 8256 /* The count of MTBDWT_COMPID */ 8257 #define MTBDWT_COMPID_COUNT (4U) 8258 8259 8260 /*! 8261 * @} 8262 */ /* end of group MTBDWT_Register_Masks */ 8263 8264 8265 /* MTBDWT - Peripheral instance base addresses */ 8266 /** Peripheral MTBDWT base address */ 8267 #define MTBDWT_BASE (0xF0001000u) 8268 /** Peripheral MTBDWT base pointer */ 8269 #define MTBDWT ((MTBDWT_Type *)MTBDWT_BASE) 8270 /** Array initializer of MTBDWT peripheral base addresses */ 8271 #define MTBDWT_BASE_ADDRS { MTBDWT_BASE } 8272 /** Array initializer of MTBDWT peripheral base pointers */ 8273 #define MTBDWT_BASE_PTRS { MTBDWT } 8274 8275 /*! 8276 * @} 8277 */ /* end of group MTBDWT_Peripheral_Access_Layer */ 8278 8279 8280 /* ---------------------------------------------------------------------------- 8281 -- NV Peripheral Access Layer 8282 ---------------------------------------------------------------------------- */ 8283 8284 /*! 8285 * @addtogroup NV_Peripheral_Access_Layer NV Peripheral Access Layer 8286 * @{ 8287 */ 8288 8289 /** NV - Register Layout Typedef */ 8290 typedef struct { 8291 __I uint8_t BACKKEY3; /**< Backdoor Comparison Key 3., offset: 0x0 */ 8292 __I uint8_t BACKKEY2; /**< Backdoor Comparison Key 2., offset: 0x1 */ 8293 __I uint8_t BACKKEY1; /**< Backdoor Comparison Key 1., offset: 0x2 */ 8294 __I uint8_t BACKKEY0; /**< Backdoor Comparison Key 0., offset: 0x3 */ 8295 __I uint8_t BACKKEY7; /**< Backdoor Comparison Key 7., offset: 0x4 */ 8296 __I uint8_t BACKKEY6; /**< Backdoor Comparison Key 6., offset: 0x5 */ 8297 __I uint8_t BACKKEY5; /**< Backdoor Comparison Key 5., offset: 0x6 */ 8298 __I uint8_t BACKKEY4; /**< Backdoor Comparison Key 4., offset: 0x7 */ 8299 __I uint8_t FPROT3; /**< Non-volatile P-Flash Protection 1 - Low Register, offset: 0x8 */ 8300 __I uint8_t FPROT2; /**< Non-volatile P-Flash Protection 1 - High Register, offset: 0x9 */ 8301 __I uint8_t FPROT1; /**< Non-volatile P-Flash Protection 0 - Low Register, offset: 0xA */ 8302 __I uint8_t FPROT0; /**< Non-volatile P-Flash Protection 0 - High Register, offset: 0xB */ 8303 __I uint8_t FSEC; /**< Non-volatile Flash Security Register, offset: 0xC */ 8304 __I uint8_t FOPT; /**< Non-volatile Flash Option Register, offset: 0xD */ 8305 } NV_Type; 8306 8307 /* ---------------------------------------------------------------------------- 8308 -- NV Register Masks 8309 ---------------------------------------------------------------------------- */ 8310 8311 /*! 8312 * @addtogroup NV_Register_Masks NV Register Masks 8313 * @{ 8314 */ 8315 8316 /*! @name BACKKEY3 - Backdoor Comparison Key 3. */ 8317 /*! @{ */ 8318 #define NV_BACKKEY3_KEY_MASK (0xFFU) 8319 #define NV_BACKKEY3_KEY_SHIFT (0U) 8320 /*! KEY - Backdoor Comparison Key. 8321 */ 8322 #define NV_BACKKEY3_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY3_KEY_SHIFT)) & NV_BACKKEY3_KEY_MASK) 8323 /*! @} */ 8324 8325 /*! @name BACKKEY2 - Backdoor Comparison Key 2. */ 8326 /*! @{ */ 8327 #define NV_BACKKEY2_KEY_MASK (0xFFU) 8328 #define NV_BACKKEY2_KEY_SHIFT (0U) 8329 /*! KEY - Backdoor Comparison Key. 8330 */ 8331 #define NV_BACKKEY2_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY2_KEY_SHIFT)) & NV_BACKKEY2_KEY_MASK) 8332 /*! @} */ 8333 8334 /*! @name BACKKEY1 - Backdoor Comparison Key 1. */ 8335 /*! @{ */ 8336 #define NV_BACKKEY1_KEY_MASK (0xFFU) 8337 #define NV_BACKKEY1_KEY_SHIFT (0U) 8338 /*! KEY - Backdoor Comparison Key. 8339 */ 8340 #define NV_BACKKEY1_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY1_KEY_SHIFT)) & NV_BACKKEY1_KEY_MASK) 8341 /*! @} */ 8342 8343 /*! @name BACKKEY0 - Backdoor Comparison Key 0. */ 8344 /*! @{ */ 8345 #define NV_BACKKEY0_KEY_MASK (0xFFU) 8346 #define NV_BACKKEY0_KEY_SHIFT (0U) 8347 /*! KEY - Backdoor Comparison Key. 8348 */ 8349 #define NV_BACKKEY0_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY0_KEY_SHIFT)) & NV_BACKKEY0_KEY_MASK) 8350 /*! @} */ 8351 8352 /*! @name BACKKEY7 - Backdoor Comparison Key 7. */ 8353 /*! @{ */ 8354 #define NV_BACKKEY7_KEY_MASK (0xFFU) 8355 #define NV_BACKKEY7_KEY_SHIFT (0U) 8356 /*! KEY - Backdoor Comparison Key. 8357 */ 8358 #define NV_BACKKEY7_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY7_KEY_SHIFT)) & NV_BACKKEY7_KEY_MASK) 8359 /*! @} */ 8360 8361 /*! @name BACKKEY6 - Backdoor Comparison Key 6. */ 8362 /*! @{ */ 8363 #define NV_BACKKEY6_KEY_MASK (0xFFU) 8364 #define NV_BACKKEY6_KEY_SHIFT (0U) 8365 /*! KEY - Backdoor Comparison Key. 8366 */ 8367 #define NV_BACKKEY6_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY6_KEY_SHIFT)) & NV_BACKKEY6_KEY_MASK) 8368 /*! @} */ 8369 8370 /*! @name BACKKEY5 - Backdoor Comparison Key 5. */ 8371 /*! @{ */ 8372 #define NV_BACKKEY5_KEY_MASK (0xFFU) 8373 #define NV_BACKKEY5_KEY_SHIFT (0U) 8374 /*! KEY - Backdoor Comparison Key. 8375 */ 8376 #define NV_BACKKEY5_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY5_KEY_SHIFT)) & NV_BACKKEY5_KEY_MASK) 8377 /*! @} */ 8378 8379 /*! @name BACKKEY4 - Backdoor Comparison Key 4. */ 8380 /*! @{ */ 8381 #define NV_BACKKEY4_KEY_MASK (0xFFU) 8382 #define NV_BACKKEY4_KEY_SHIFT (0U) 8383 /*! KEY - Backdoor Comparison Key. 8384 */ 8385 #define NV_BACKKEY4_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY4_KEY_SHIFT)) & NV_BACKKEY4_KEY_MASK) 8386 /*! @} */ 8387 8388 /*! @name FPROT3 - Non-volatile P-Flash Protection 1 - Low Register */ 8389 /*! @{ */ 8390 #define NV_FPROT3_PROT_MASK (0xFFU) 8391 #define NV_FPROT3_PROT_SHIFT (0U) 8392 /*! PROT - P-Flash Region Protect 8393 */ 8394 #define NV_FPROT3_PROT(x) (((uint8_t)(((uint8_t)(x)) << NV_FPROT3_PROT_SHIFT)) & NV_FPROT3_PROT_MASK) 8395 /*! @} */ 8396 8397 /*! @name FPROT2 - Non-volatile P-Flash Protection 1 - High Register */ 8398 /*! @{ */ 8399 #define NV_FPROT2_PROT_MASK (0xFFU) 8400 #define NV_FPROT2_PROT_SHIFT (0U) 8401 /*! PROT - P-Flash Region Protect 8402 */ 8403 #define NV_FPROT2_PROT(x) (((uint8_t)(((uint8_t)(x)) << NV_FPROT2_PROT_SHIFT)) & NV_FPROT2_PROT_MASK) 8404 /*! @} */ 8405 8406 /*! @name FPROT1 - Non-volatile P-Flash Protection 0 - Low Register */ 8407 /*! @{ */ 8408 #define NV_FPROT1_PROT_MASK (0xFFU) 8409 #define NV_FPROT1_PROT_SHIFT (0U) 8410 /*! PROT - P-Flash Region Protect 8411 */ 8412 #define NV_FPROT1_PROT(x) (((uint8_t)(((uint8_t)(x)) << NV_FPROT1_PROT_SHIFT)) & NV_FPROT1_PROT_MASK) 8413 /*! @} */ 8414 8415 /*! @name FPROT0 - Non-volatile P-Flash Protection 0 - High Register */ 8416 /*! @{ */ 8417 #define NV_FPROT0_PROT_MASK (0xFFU) 8418 #define NV_FPROT0_PROT_SHIFT (0U) 8419 /*! PROT - P-Flash Region Protect 8420 */ 8421 #define NV_FPROT0_PROT(x) (((uint8_t)(((uint8_t)(x)) << NV_FPROT0_PROT_SHIFT)) & NV_FPROT0_PROT_MASK) 8422 /*! @} */ 8423 8424 /*! @name FSEC - Non-volatile Flash Security Register */ 8425 /*! @{ */ 8426 #define NV_FSEC_SEC_MASK (0x3U) 8427 #define NV_FSEC_SEC_SHIFT (0U) 8428 /*! SEC - Flash Security 8429 * 0b10..MCU security status is unsecure 8430 * 0b11..MCU security status is secure 8431 */ 8432 #define NV_FSEC_SEC(x) (((uint8_t)(((uint8_t)(x)) << NV_FSEC_SEC_SHIFT)) & NV_FSEC_SEC_MASK) 8433 #define NV_FSEC_FSLACC_MASK (0xCU) 8434 #define NV_FSEC_FSLACC_SHIFT (2U) 8435 /*! FSLACC - Freescale Failure Analysis Access Code 8436 * 0b10..Freescale factory access denied 8437 * 0b11..Freescale factory access granted 8438 */ 8439 #define NV_FSEC_FSLACC(x) (((uint8_t)(((uint8_t)(x)) << NV_FSEC_FSLACC_SHIFT)) & NV_FSEC_FSLACC_MASK) 8440 #define NV_FSEC_MEEN_MASK (0x30U) 8441 #define NV_FSEC_MEEN_SHIFT (4U) 8442 /*! MEEN 8443 * 0b10..Mass erase is disabled 8444 * 0b11..Mass erase is enabled 8445 */ 8446 #define NV_FSEC_MEEN(x) (((uint8_t)(((uint8_t)(x)) << NV_FSEC_MEEN_SHIFT)) & NV_FSEC_MEEN_MASK) 8447 #define NV_FSEC_KEYEN_MASK (0xC0U) 8448 #define NV_FSEC_KEYEN_SHIFT (6U) 8449 /*! KEYEN - Backdoor Key Security Enable 8450 * 0b10..Backdoor key access enabled 8451 * 0b11..Backdoor key access disabled 8452 */ 8453 #define NV_FSEC_KEYEN(x) (((uint8_t)(((uint8_t)(x)) << NV_FSEC_KEYEN_SHIFT)) & NV_FSEC_KEYEN_MASK) 8454 /*! @} */ 8455 8456 /*! @name FOPT - Non-volatile Flash Option Register */ 8457 /*! @{ */ 8458 #define NV_FOPT_LPBOOT_MASK (0x1U) 8459 #define NV_FOPT_LPBOOT_SHIFT (0U) 8460 /*! LPBOOT 8461 * 0b0..Low-power boot 8462 * 0b1..Normal boot 8463 */ 8464 #define NV_FOPT_LPBOOT(x) (((uint8_t)(((uint8_t)(x)) << NV_FOPT_LPBOOT_SHIFT)) & NV_FOPT_LPBOOT_MASK) 8465 #define NV_FOPT_NMI_DIS_MASK (0x4U) 8466 #define NV_FOPT_NMI_DIS_SHIFT (2U) 8467 /*! NMI_DIS 8468 * 0b0..NMI interrupts are always blocked 8469 * 0b1..NMI_b pin/interrupts reset default to enabled 8470 */ 8471 #define NV_FOPT_NMI_DIS(x) (((uint8_t)(((uint8_t)(x)) << NV_FOPT_NMI_DIS_SHIFT)) & NV_FOPT_NMI_DIS_MASK) 8472 #define NV_FOPT_RESET_PIN_CFG_MASK (0x8U) 8473 #define NV_FOPT_RESET_PIN_CFG_SHIFT (3U) 8474 /*! RESET_PIN_CFG 8475 * 0b0..RESET pin is disabled following a POR and cannot be enabled as reset function 8476 * 0b1..RESET_b pin is dedicated 8477 */ 8478 #define NV_FOPT_RESET_PIN_CFG(x) (((uint8_t)(((uint8_t)(x)) << NV_FOPT_RESET_PIN_CFG_SHIFT)) & NV_FOPT_RESET_PIN_CFG_MASK) 8479 /*! @} */ 8480 8481 8482 /*! 8483 * @} 8484 */ /* end of group NV_Register_Masks */ 8485 8486 8487 /* NV - Peripheral instance base addresses */ 8488 /** Peripheral FTFA_FlashConfig base address */ 8489 #define FTFA_FlashConfig_BASE (0x400u) 8490 /** Peripheral FTFA_FlashConfig base pointer */ 8491 #define FTFA_FlashConfig ((NV_Type *)FTFA_FlashConfig_BASE) 8492 /** Array initializer of NV peripheral base addresses */ 8493 #define NV_BASE_ADDRS { FTFA_FlashConfig_BASE } 8494 /** Array initializer of NV peripheral base pointers */ 8495 #define NV_BASE_PTRS { FTFA_FlashConfig } 8496 8497 /*! 8498 * @} 8499 */ /* end of group NV_Peripheral_Access_Layer */ 8500 8501 8502 /* ---------------------------------------------------------------------------- 8503 -- PCC Peripheral Access Layer 8504 ---------------------------------------------------------------------------- */ 8505 8506 /*! 8507 * @addtogroup PCC_Peripheral_Access_Layer PCC Peripheral Access Layer 8508 * @{ 8509 */ 8510 8511 /** PCC - Register Layout Typedef */ 8512 typedef struct { 8513 __IO uint32_t CLKCFG[116]; /**< PCC FLASH Register..PCC CMP0 Register, array offset: 0x0, array step: 0x4 */ 8514 } PCC_Type; 8515 8516 /* ---------------------------------------------------------------------------- 8517 -- PCC Register Masks 8518 ---------------------------------------------------------------------------- */ 8519 8520 /*! 8521 * @addtogroup PCC_Register_Masks PCC Register Masks 8522 * @{ 8523 */ 8524 8525 /*! @name CLKCFG - PCC FLASH Register..PCC CMP0 Register */ 8526 /*! @{ */ 8527 #define PCC_CLKCFG_PCS_MASK (0x7000000U) 8528 #define PCC_CLKCFG_PCS_SHIFT (24U) 8529 /*! PCS - Peripheral Clock Source Select 8530 * 0b000..Clock is off. 8531 * 0b001..Clock option 1 8532 * 0b010..Clock option 2 8533 * 0b011..Clock option 3 8534 * 0b100..Clock option 4 8535 * 0b101..Clock option 5 8536 * 0b110..Clock option 6 8537 * 0b111..Clock option 7 8538 */ 8539 #define PCC_CLKCFG_PCS(x) (((uint32_t)(((uint32_t)(x)) << PCC_CLKCFG_PCS_SHIFT)) & PCC_CLKCFG_PCS_MASK) 8540 #define PCC_CLKCFG_CGC_MASK (0x40000000U) 8541 #define PCC_CLKCFG_CGC_SHIFT (30U) 8542 /*! CGC - Clock Gate Control 8543 * 0b0..Clock disabled 8544 * 0b1..Clock enabled. The current clock selection and divider options are locked. 8545 */ 8546 #define PCC_CLKCFG_CGC(x) (((uint32_t)(((uint32_t)(x)) << PCC_CLKCFG_CGC_SHIFT)) & PCC_CLKCFG_CGC_MASK) 8547 #define PCC_CLKCFG_PR_MASK (0x80000000U) 8548 #define PCC_CLKCFG_PR_SHIFT (31U) 8549 /*! PR - Present 8550 * 0b0..Peripheral is not present. 8551 * 0b1..Peripheral is present. 8552 */ 8553 #define PCC_CLKCFG_PR(x) (((uint32_t)(((uint32_t)(x)) << PCC_CLKCFG_PR_SHIFT)) & PCC_CLKCFG_PR_MASK) 8554 /*! @} */ 8555 8556 /* The count of PCC_CLKCFG */ 8557 #define PCC_CLKCFG_COUNT (116U) 8558 8559 8560 /*! 8561 * @} 8562 */ /* end of group PCC_Register_Masks */ 8563 8564 8565 /* PCC - Peripheral instance base addresses */ 8566 /** Peripheral PCC base address */ 8567 #define PCC_BASE (0x40065000u) 8568 /** Peripheral PCC base pointer */ 8569 #define PCC ((PCC_Type *)PCC_BASE) 8570 /** Array initializer of PCC peripheral base addresses */ 8571 #define PCC_BASE_ADDRS { PCC_BASE } 8572 /** Array initializer of PCC peripheral base pointers */ 8573 #define PCC_BASE_PTRS { PCC } 8574 #define PCC_INSTANCE_MASK 0xF 8575 #define PCC_INSTANCE_SHIFT 12 8576 #define PCC_PERIPHERAL_MASK 0xFFF 8577 #define PCC_PERIPHERAL_SHIFT 0 8578 #define PCC_INSTANCE_0 0 8579 8580 #define PCC_FLASH_INDEX 32 8581 #define PCC_MSCAN0_INDEX 36 8582 #define PCC_LPSPI0_INDEX 44 8583 #define PCC_CRC_INDEX 50 8584 #define PCC_PDB0_INDEX 54 8585 #define PCC_LPIT0_INDEX 55 8586 #define PCC_FLEXTMR0_INDEX 56 8587 #define PCC_FLEXTMR1_INDEX 57 8588 #define PCC_ADC0_INDEX 59 8589 #define PCC_RTC_INDEX 61 8590 #define PCC_LPTMR0_INDEX 64 8591 #define PCC_TSI_INDEX 69 8592 #define PCC_PORTA_INDEX 73 8593 #define PCC_PORTB_INDEX 74 8594 #define PCC_PORTC_INDEX 75 8595 #define PCC_PORTD_INDEX 76 8596 #define PCC_PORTE_INDEX 77 8597 #define PCC_PWT_INDEX 86 8598 #define PCC_EWM_INDEX 97 8599 #define PCC_LPI2C0_INDEX 102 8600 #define PCC_LPUART0_INDEX 106 8601 #define PCC_LPUART1_INDEX 107 8602 #define PCC_LPUART2_INDEX 108 8603 #define PCC_CMP0_INDEX 115 8604 8605 8606 /*! 8607 * @} 8608 */ /* end of group PCC_Peripheral_Access_Layer */ 8609 8610 8611 /* ---------------------------------------------------------------------------- 8612 -- PDB Peripheral Access Layer 8613 ---------------------------------------------------------------------------- */ 8614 8615 /*! 8616 * @addtogroup PDB_Peripheral_Access_Layer PDB Peripheral Access Layer 8617 * @{ 8618 */ 8619 8620 /** PDB - Register Layout Typedef */ 8621 typedef struct { 8622 __IO uint32_t SC; /**< Status and Control register, offset: 0x0 */ 8623 __IO uint32_t MOD; /**< Modulus register, offset: 0x4 */ 8624 __I uint32_t CNT; /**< Counter register, offset: 0x8 */ 8625 __IO uint32_t IDLY; /**< Interrupt Delay register, offset: 0xC */ 8626 struct { /* offset: 0x10, array step: 0x18 */ 8627 __IO uint32_t C1; /**< Channel n Control register 1, array offset: 0x10, array step: 0x18 */ 8628 __IO uint32_t S; /**< Channel n Status register, array offset: 0x14, array step: 0x18 */ 8629 __IO uint32_t DLY[4]; /**< Channel n Delay 0 register..Channel n Delay 3 register, array offset: 0x18, array step: index*0x18, index2*0x4 */ 8630 } CH[1]; 8631 uint8_t RESERVED_0[360]; 8632 __IO uint32_t POEN; /**< Pulse-Out n Enable register, offset: 0x190 */ 8633 __IO uint32_t PODLY[1]; /**< Pulse-Out n Delay register, array offset: 0x194, array step: 0x4 */ 8634 } PDB_Type; 8635 8636 /* ---------------------------------------------------------------------------- 8637 -- PDB Register Masks 8638 ---------------------------------------------------------------------------- */ 8639 8640 /*! 8641 * @addtogroup PDB_Register_Masks PDB Register Masks 8642 * @{ 8643 */ 8644 8645 /*! @name SC - Status and Control register */ 8646 /*! @{ */ 8647 #define PDB_SC_LDOK_MASK (0x1U) 8648 #define PDB_SC_LDOK_SHIFT (0U) 8649 /*! LDOK - Load OK 8650 */ 8651 #define PDB_SC_LDOK(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_LDOK_SHIFT)) & PDB_SC_LDOK_MASK) 8652 #define PDB_SC_CONT_MASK (0x2U) 8653 #define PDB_SC_CONT_SHIFT (1U) 8654 /*! CONT - Continuous Mode Enable 8655 * 0b0..PDB operation in One-Shot mode 8656 * 0b1..PDB operation in Continuous mode 8657 */ 8658 #define PDB_SC_CONT(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_CONT_SHIFT)) & PDB_SC_CONT_MASK) 8659 #define PDB_SC_MULT_MASK (0xCU) 8660 #define PDB_SC_MULT_SHIFT (2U) 8661 /*! MULT - Multiplication Factor Select for Prescaler 8662 * 0b00..Multiplication factor is 1. 8663 * 0b01..Multiplication factor is 10. 8664 * 0b10..Multiplication factor is 20. 8665 * 0b11..Multiplication factor is 40. 8666 */ 8667 #define PDB_SC_MULT(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_MULT_SHIFT)) & PDB_SC_MULT_MASK) 8668 #define PDB_SC_PDBIE_MASK (0x20U) 8669 #define PDB_SC_PDBIE_SHIFT (5U) 8670 /*! PDBIE - PDB Interrupt Enable 8671 * 0b0..PDB interrupt disabled. 8672 * 0b1..PDB interrupt enabled. 8673 */ 8674 #define PDB_SC_PDBIE(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_PDBIE_SHIFT)) & PDB_SC_PDBIE_MASK) 8675 #define PDB_SC_PDBIF_MASK (0x40U) 8676 #define PDB_SC_PDBIF_SHIFT (6U) 8677 /*! PDBIF - PDB Interrupt Flag 8678 */ 8679 #define PDB_SC_PDBIF(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_PDBIF_SHIFT)) & PDB_SC_PDBIF_MASK) 8680 #define PDB_SC_PDBEN_MASK (0x80U) 8681 #define PDB_SC_PDBEN_SHIFT (7U) 8682 /*! PDBEN - PDB Enable 8683 * 0b0..PDB disabled. Counter is off. 8684 * 0b1..PDB enabled. 8685 */ 8686 #define PDB_SC_PDBEN(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_PDBEN_SHIFT)) & PDB_SC_PDBEN_MASK) 8687 #define PDB_SC_TRGSEL_MASK (0xF00U) 8688 #define PDB_SC_TRGSEL_SHIFT (8U) 8689 /*! TRGSEL - Trigger Input Source Select 8690 * 0b0000..Trigger-In 0 is selected. 8691 * 0b0001..Trigger-In 1 is selected. 8692 * 0b0010..Trigger-In 2 is selected. 8693 * 0b0011..Trigger-In 3 is selected. 8694 * 0b0100..Trigger-In 4 is selected. 8695 * 0b0101..Trigger-In 5 is selected. 8696 * 0b0110..Trigger-In 6 is selected. 8697 * 0b0111..Trigger-In 7 is selected. 8698 * 0b1000..Trigger-In 8 is selected. 8699 * 0b1001..Trigger-In 9 is selected. 8700 * 0b1010..Trigger-In 10 is selected. 8701 * 0b1011..Trigger-In 11 is selected. 8702 * 0b1100..Trigger-In 12 is selected. 8703 * 0b1101..Trigger-In 13 is selected. 8704 * 0b1110..Trigger-In 14 is selected. 8705 * 0b1111..Software trigger is selected. 8706 */ 8707 #define PDB_SC_TRGSEL(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_TRGSEL_SHIFT)) & PDB_SC_TRGSEL_MASK) 8708 #define PDB_SC_PRESCALER_MASK (0x7000U) 8709 #define PDB_SC_PRESCALER_SHIFT (12U) 8710 /*! PRESCALER - Prescaler Divider Select 8711 * 0b000..Counting uses the peripheral clock divided by MULT (the multiplication factor). 8712 * 0b001..Counting uses the peripheral clock divided by 2 x MULT (the multiplication factor). 8713 * 0b010..Counting uses the peripheral clock divided by 4 x MULT (the multiplication factor). 8714 * 0b011..Counting uses the peripheral clock divided by 8 x MULT (the multiplication factor). 8715 * 0b100..Counting uses the peripheral clock divided by 16 x MULT (the multiplication factor). 8716 * 0b101..Counting uses the peripheral clock divided by 32 x MULT (the multiplication factor). 8717 * 0b110..Counting uses the peripheral clock divided by 64 x MULT (the multiplication factor). 8718 * 0b111..Counting uses the peripheral clock divided by 128 x MULT (the multiplication factor). 8719 */ 8720 #define PDB_SC_PRESCALER(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_PRESCALER_SHIFT)) & PDB_SC_PRESCALER_MASK) 8721 #define PDB_SC_DMAEN_MASK (0x8000U) 8722 #define PDB_SC_DMAEN_SHIFT (15U) 8723 /*! DMAEN - DMA Enable 8724 * 0b0..DMA disabled. 8725 * 0b1..DMA enabled. 8726 */ 8727 #define PDB_SC_DMAEN(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_DMAEN_SHIFT)) & PDB_SC_DMAEN_MASK) 8728 #define PDB_SC_SWTRIG_MASK (0x10000U) 8729 #define PDB_SC_SWTRIG_SHIFT (16U) 8730 /*! SWTRIG - Software Trigger 8731 */ 8732 #define PDB_SC_SWTRIG(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_SWTRIG_SHIFT)) & PDB_SC_SWTRIG_MASK) 8733 #define PDB_SC_PDBEIE_MASK (0x20000U) 8734 #define PDB_SC_PDBEIE_SHIFT (17U) 8735 /*! PDBEIE - PDB Sequence Error Interrupt Enable 8736 * 0b0..PDB sequence error interrupt disabled. 8737 * 0b1..PDB sequence error interrupt enabled. 8738 */ 8739 #define PDB_SC_PDBEIE(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_PDBEIE_SHIFT)) & PDB_SC_PDBEIE_MASK) 8740 #define PDB_SC_LDMOD_MASK (0xC0000U) 8741 #define PDB_SC_LDMOD_SHIFT (18U) 8742 /*! LDMOD - Load Mode Select 8743 * 0b00..The internal registers are loaded with the values from their buffers, immediately after 1 is written to LDOK. 8744 * 0b01..The internal registers are loaded with the values from their buffers when the PDB counter (CNT) = MOD + 8745 * 1 CNT delay elapsed, after 1 is written to LDOK. 8746 * 0b10..The internal registers are loaded with the values from their buffers when a trigger input event is detected, after 1 is written to LDOK. 8747 * 0b11..The internal registers are loaded with the values from their buffers when either the PDB counter (CNT) = 8748 * MOD + 1 CNT delay elapsed, or a trigger input event is detected, after 1 is written to LDOK. 8749 */ 8750 #define PDB_SC_LDMOD(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_LDMOD_SHIFT)) & PDB_SC_LDMOD_MASK) 8751 /*! @} */ 8752 8753 /*! @name MOD - Modulus register */ 8754 /*! @{ */ 8755 #define PDB_MOD_MOD_MASK (0xFFFFU) 8756 #define PDB_MOD_MOD_SHIFT (0U) 8757 /*! MOD - PDB Modulus 8758 */ 8759 #define PDB_MOD_MOD(x) (((uint32_t)(((uint32_t)(x)) << PDB_MOD_MOD_SHIFT)) & PDB_MOD_MOD_MASK) 8760 /*! @} */ 8761 8762 /*! @name CNT - Counter register */ 8763 /*! @{ */ 8764 #define PDB_CNT_CNT_MASK (0xFFFFU) 8765 #define PDB_CNT_CNT_SHIFT (0U) 8766 /*! CNT - PDB Counter 8767 */ 8768 #define PDB_CNT_CNT(x) (((uint32_t)(((uint32_t)(x)) << PDB_CNT_CNT_SHIFT)) & PDB_CNT_CNT_MASK) 8769 /*! @} */ 8770 8771 /*! @name IDLY - Interrupt Delay register */ 8772 /*! @{ */ 8773 #define PDB_IDLY_IDLY_MASK (0xFFFFU) 8774 #define PDB_IDLY_IDLY_SHIFT (0U) 8775 /*! IDLY - PDB Interrupt Delay 8776 */ 8777 #define PDB_IDLY_IDLY(x) (((uint32_t)(((uint32_t)(x)) << PDB_IDLY_IDLY_SHIFT)) & PDB_IDLY_IDLY_MASK) 8778 /*! @} */ 8779 8780 /*! @name C1 - Channel n Control register 1 */ 8781 /*! @{ */ 8782 #define PDB_C1_EN_MASK (0xFFU) 8783 #define PDB_C1_EN_SHIFT (0U) 8784 /*! EN - PDB Channel Pre-Trigger Enable 8785 * 0b00000000..PDB channel's corresponding pre-trigger disabled. 8786 * 0b00000001..PDB channel's corresponding pre-trigger enabled. 8787 */ 8788 #define PDB_C1_EN(x) (((uint32_t)(((uint32_t)(x)) << PDB_C1_EN_SHIFT)) & PDB_C1_EN_MASK) 8789 #define PDB_C1_TOS_MASK (0xFF00U) 8790 #define PDB_C1_TOS_SHIFT (8U) 8791 /*! TOS - PDB Channel Pre-Trigger Output Select 8792 * 0b00000000..PDB channel's corresponding pre-trigger is in bypassed mode. The pre-trigger asserts one 8793 * peripheral clock cycle after a rising edge is detected on selected trigger input source or software trigger 8794 * is selected and SWTRIG is written with 1. 8795 * 0b00000001..PDB channel's corresponding pre-trigger asserts when the counter reaches the channel delay 8796 * register plus one peripheral clock cycle after a rising edge is detected on selected trigger input source 8797 * or software trigger is selected and SWTRIG is written with 1. 8798 */ 8799 #define PDB_C1_TOS(x) (((uint32_t)(((uint32_t)(x)) << PDB_C1_TOS_SHIFT)) & PDB_C1_TOS_MASK) 8800 #define PDB_C1_BB_MASK (0xFF0000U) 8801 #define PDB_C1_BB_SHIFT (16U) 8802 /*! BB - PDB Channel Pre-Trigger Back-to-Back Operation Enable 8803 * 0b00000000..PDB channel's corresponding pre-trigger back-to-back operation disabled. 8804 * 0b00000001..PDB channel's corresponding pre-trigger back-to-back operation enabled. 8805 */ 8806 #define PDB_C1_BB(x) (((uint32_t)(((uint32_t)(x)) << PDB_C1_BB_SHIFT)) & PDB_C1_BB_MASK) 8807 /*! @} */ 8808 8809 /* The count of PDB_C1 */ 8810 #define PDB_C1_COUNT (1U) 8811 8812 /*! @name S - Channel n Status register */ 8813 /*! @{ */ 8814 #define PDB_S_ERR_MASK (0xFFU) 8815 #define PDB_S_ERR_SHIFT (0U) 8816 /*! ERR - PDB Channel Sequence Error Flags 8817 * 0b00000000..Sequence error not detected on PDB channel's corresponding pre-trigger. 8818 * 0b00000001..Sequence error detected on PDB channel's corresponding pre-trigger. ADCn block can be triggered 8819 * for a conversion by one pre-trigger from PDB channel n. When one conversion, which is triggered by 8820 * one of the pre-triggers from PDB channel n, is in progress, new trigger from PDB channel's 8821 * corresponding pre-trigger m cannot be accepted by ADCn, and ERR[m] is set. Writing 0's to clear the sequence 8822 * error flags. 8823 */ 8824 #define PDB_S_ERR(x) (((uint32_t)(((uint32_t)(x)) << PDB_S_ERR_SHIFT)) & PDB_S_ERR_MASK) 8825 #define PDB_S_CF_MASK (0xFF0000U) 8826 #define PDB_S_CF_SHIFT (16U) 8827 /*! CF - PDB Channel Flags 8828 */ 8829 #define PDB_S_CF(x) (((uint32_t)(((uint32_t)(x)) << PDB_S_CF_SHIFT)) & PDB_S_CF_MASK) 8830 /*! @} */ 8831 8832 /* The count of PDB_S */ 8833 #define PDB_S_COUNT (1U) 8834 8835 /*! @name DLY - Channel n Delay 0 register..Channel n Delay 3 register */ 8836 /*! @{ */ 8837 #define PDB_DLY_DLY_MASK (0xFFFFU) 8838 #define PDB_DLY_DLY_SHIFT (0U) 8839 /*! DLY - PDB Channel Delay 8840 */ 8841 #define PDB_DLY_DLY(x) (((uint32_t)(((uint32_t)(x)) << PDB_DLY_DLY_SHIFT)) & PDB_DLY_DLY_MASK) 8842 /*! @} */ 8843 8844 /* The count of PDB_DLY */ 8845 #define PDB_DLY_COUNT (1U) 8846 8847 /* The count of PDB_DLY */ 8848 #define PDB_DLY_COUNT2 (4U) 8849 8850 /*! @name POEN - Pulse-Out n Enable register */ 8851 /*! @{ */ 8852 #define PDB_POEN_POEN_MASK (0xFFU) 8853 #define PDB_POEN_POEN_SHIFT (0U) 8854 /*! POEN - PDB Pulse-Out Enable 8855 * 0b00000000..PDB Pulse-Out disabled 8856 * 0b00000001..PDB Pulse-Out enabled 8857 */ 8858 #define PDB_POEN_POEN(x) (((uint32_t)(((uint32_t)(x)) << PDB_POEN_POEN_SHIFT)) & PDB_POEN_POEN_MASK) 8859 /*! @} */ 8860 8861 /*! @name PODLY - Pulse-Out n Delay register */ 8862 /*! @{ */ 8863 #define PDB_PODLY_DLY2_MASK (0xFFFFU) 8864 #define PDB_PODLY_DLY2_SHIFT (0U) 8865 /*! DLY2 - PDB Pulse-Out Delay 2 8866 */ 8867 #define PDB_PODLY_DLY2(x) (((uint32_t)(((uint32_t)(x)) << PDB_PODLY_DLY2_SHIFT)) & PDB_PODLY_DLY2_MASK) 8868 #define PDB_PODLY_DLY1_MASK (0xFFFF0000U) 8869 #define PDB_PODLY_DLY1_SHIFT (16U) 8870 /*! DLY1 - PDB Pulse-Out Delay 1 8871 */ 8872 #define PDB_PODLY_DLY1(x) (((uint32_t)(((uint32_t)(x)) << PDB_PODLY_DLY1_SHIFT)) & PDB_PODLY_DLY1_MASK) 8873 /*! @} */ 8874 8875 /* The count of PDB_PODLY */ 8876 #define PDB_PODLY_COUNT (1U) 8877 8878 8879 /*! 8880 * @} 8881 */ /* end of group PDB_Register_Masks */ 8882 8883 8884 /* PDB - Peripheral instance base addresses */ 8885 /** Peripheral PDB0 base address */ 8886 #define PDB0_BASE (0x40036000u) 8887 /** Peripheral PDB0 base pointer */ 8888 #define PDB0 ((PDB_Type *)PDB0_BASE) 8889 /** Array initializer of PDB peripheral base addresses */ 8890 #define PDB_BASE_ADDRS { PDB0_BASE } 8891 /** Array initializer of PDB peripheral base pointers */ 8892 #define PDB_BASE_PTRS { PDB0 } 8893 /** Interrupt vectors for the PDB peripheral type */ 8894 #define PDB_IRQS { PDB0_IRQn } 8895 8896 /*! 8897 * @} 8898 */ /* end of group PDB_Peripheral_Access_Layer */ 8899 8900 8901 /* ---------------------------------------------------------------------------- 8902 -- PMC Peripheral Access Layer 8903 ---------------------------------------------------------------------------- */ 8904 8905 /*! 8906 * @addtogroup PMC_Peripheral_Access_Layer PMC Peripheral Access Layer 8907 * @{ 8908 */ 8909 8910 /** PMC - Register Layout Typedef */ 8911 typedef struct { 8912 __IO uint8_t LVDSC1; /**< Low Voltage Detect Status and Control 1 Register, offset: 0x0 */ 8913 __IO uint8_t LVDSC2; /**< Low Voltage Detect Status and Control 2 Register, offset: 0x1 */ 8914 __IO uint8_t REGSC; /**< Regulator Status and Control Register, offset: 0x2 */ 8915 uint8_t RESERVED_0[1]; 8916 __IO uint8_t LPOTRIM; /**< Low Power Oscillator Trim Register, offset: 0x4 */ 8917 } PMC_Type; 8918 8919 /* ---------------------------------------------------------------------------- 8920 -- PMC Register Masks 8921 ---------------------------------------------------------------------------- */ 8922 8923 /*! 8924 * @addtogroup PMC_Register_Masks PMC Register Masks 8925 * @{ 8926 */ 8927 8928 /*! @name LVDSC1 - Low Voltage Detect Status and Control 1 Register */ 8929 /*! @{ */ 8930 #define PMC_LVDSC1_LVDRE_MASK (0x10U) 8931 #define PMC_LVDSC1_LVDRE_SHIFT (4U) 8932 /*! LVDRE - Low Voltage Detect Reset Enable 8933 * 0b0..No system resets on low voltage detect events. 8934 * 0b1..If the supply voltage falls below VLVD, a system reset will be generated. 8935 */ 8936 #define PMC_LVDSC1_LVDRE(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC1_LVDRE_SHIFT)) & PMC_LVDSC1_LVDRE_MASK) 8937 #define PMC_LVDSC1_LVDIE_MASK (0x20U) 8938 #define PMC_LVDSC1_LVDIE_SHIFT (5U) 8939 /*! LVDIE - Low Voltage Detect Interrupt Enable 8940 * 0b0..Hardware interrupt disabled (use polling) 8941 * 0b1..Request a hardware interrupt when LVDF = 1 8942 */ 8943 #define PMC_LVDSC1_LVDIE(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC1_LVDIE_SHIFT)) & PMC_LVDSC1_LVDIE_MASK) 8944 #define PMC_LVDSC1_LVDACK_MASK (0x40U) 8945 #define PMC_LVDSC1_LVDACK_SHIFT (6U) 8946 /*! LVDACK - Low Voltage Detect Acknowledge 8947 */ 8948 #define PMC_LVDSC1_LVDACK(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC1_LVDACK_SHIFT)) & PMC_LVDSC1_LVDACK_MASK) 8949 #define PMC_LVDSC1_LVDF_MASK (0x80U) 8950 #define PMC_LVDSC1_LVDF_SHIFT (7U) 8951 /*! LVDF - Low Voltage Detect Flag 8952 * 0b0..Low-voltage event not detected 8953 * 0b1..Low-voltage event detected 8954 */ 8955 #define PMC_LVDSC1_LVDF(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC1_LVDF_SHIFT)) & PMC_LVDSC1_LVDF_MASK) 8956 /*! @} */ 8957 8958 /*! @name LVDSC2 - Low Voltage Detect Status and Control 2 Register */ 8959 /*! @{ */ 8960 #define PMC_LVDSC2_LVWIE_MASK (0x20U) 8961 #define PMC_LVDSC2_LVWIE_SHIFT (5U) 8962 /*! LVWIE - Low-Voltage Warning Interrupt Enable 8963 * 0b0..Hardware interrupt disabled (use polling) 8964 * 0b1..Request a hardware interrupt when LVWF=1 8965 */ 8966 #define PMC_LVDSC2_LVWIE(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC2_LVWIE_SHIFT)) & PMC_LVDSC2_LVWIE_MASK) 8967 #define PMC_LVDSC2_LVWACK_MASK (0x40U) 8968 #define PMC_LVDSC2_LVWACK_SHIFT (6U) 8969 /*! LVWACK - Low-Voltage Warning Acknowledge 8970 */ 8971 #define PMC_LVDSC2_LVWACK(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC2_LVWACK_SHIFT)) & PMC_LVDSC2_LVWACK_MASK) 8972 #define PMC_LVDSC2_LVWF_MASK (0x80U) 8973 #define PMC_LVDSC2_LVWF_SHIFT (7U) 8974 /*! LVWF - Low-Voltage Warning Flag 8975 * 0b0..Low-voltage warning event not detected 8976 * 0b1..Low-voltage warning event detected 8977 */ 8978 #define PMC_LVDSC2_LVWF(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC2_LVWF_SHIFT)) & PMC_LVDSC2_LVWF_MASK) 8979 /*! @} */ 8980 8981 /*! @name REGSC - Regulator Status and Control Register */ 8982 /*! @{ */ 8983 #define PMC_REGSC_BIASEN_MASK (0x1U) 8984 #define PMC_REGSC_BIASEN_SHIFT (0U) 8985 /*! BIASEN - Bias Enable Bit 8986 * 0b0..Biasing disabled, core logic can run in full performance 8987 * 0b1..Biasing enabled, core logic is slower and there are restrictions in allowed system clock speed (see Data Sheet for details) 8988 */ 8989 #define PMC_REGSC_BIASEN(x) (((uint8_t)(((uint8_t)(x)) << PMC_REGSC_BIASEN_SHIFT)) & PMC_REGSC_BIASEN_MASK) 8990 #define PMC_REGSC_CLKBIASDIS_MASK (0x2U) 8991 #define PMC_REGSC_CLKBIASDIS_SHIFT (1U) 8992 /*! CLKBIASDIS - Clock Bias Disable Bit 8993 * 0b0..No effect 8994 * 0b1..In STOP or VLPS mode the bias currents and reference voltages for the following clock modules are 8995 * disabled: SIRC, FIRC, PLL. (if available on device) 8996 */ 8997 #define PMC_REGSC_CLKBIASDIS(x) (((uint8_t)(((uint8_t)(x)) << PMC_REGSC_CLKBIASDIS_SHIFT)) & PMC_REGSC_CLKBIASDIS_MASK) 8998 #define PMC_REGSC_REGFPM_MASK (0x4U) 8999 #define PMC_REGSC_REGFPM_SHIFT (2U) 9000 /*! REGFPM - Regulator in Full Performance Mode Status Bit 9001 * 0b0..Regulator is in low power mode or transition to/from 9002 * 0b1..Regulator is in full performance mode 9003 */ 9004 #define PMC_REGSC_REGFPM(x) (((uint8_t)(((uint8_t)(x)) << PMC_REGSC_REGFPM_SHIFT)) & PMC_REGSC_REGFPM_MASK) 9005 #define PMC_REGSC_LPOSTAT_MASK (0x40U) 9006 #define PMC_REGSC_LPOSTAT_SHIFT (6U) 9007 /*! LPOSTAT - LPO Status Bit 9008 * 0b0..Low power oscillator in low phase 9009 * 0b1..Low power oscillator in high phase 9010 */ 9011 #define PMC_REGSC_LPOSTAT(x) (((uint8_t)(((uint8_t)(x)) << PMC_REGSC_LPOSTAT_SHIFT)) & PMC_REGSC_LPOSTAT_MASK) 9012 #define PMC_REGSC_LPODIS_MASK (0x80U) 9013 #define PMC_REGSC_LPODIS_SHIFT (7U) 9014 /*! LPODIS - LPO Disable Bit 9015 * 0b0..Low power oscillator enabled 9016 * 0b1..Low power oscillator disabled 9017 */ 9018 #define PMC_REGSC_LPODIS(x) (((uint8_t)(((uint8_t)(x)) << PMC_REGSC_LPODIS_SHIFT)) & PMC_REGSC_LPODIS_MASK) 9019 /*! @} */ 9020 9021 /*! @name LPOTRIM - Low Power Oscillator Trim Register */ 9022 /*! @{ */ 9023 #define PMC_LPOTRIM_LPOTRIM_MASK (0x1FU) 9024 #define PMC_LPOTRIM_LPOTRIM_SHIFT (0U) 9025 /*! LPOTRIM - LPO trimming bits 9026 */ 9027 #define PMC_LPOTRIM_LPOTRIM(x) (((uint8_t)(((uint8_t)(x)) << PMC_LPOTRIM_LPOTRIM_SHIFT)) & PMC_LPOTRIM_LPOTRIM_MASK) 9028 /*! @} */ 9029 9030 9031 /*! 9032 * @} 9033 */ /* end of group PMC_Register_Masks */ 9034 9035 9036 /* PMC - Peripheral instance base addresses */ 9037 /** Peripheral PMC base address */ 9038 #define PMC_BASE (0x4007D000u) 9039 /** Peripheral PMC base pointer */ 9040 #define PMC ((PMC_Type *)PMC_BASE) 9041 /** Array initializer of PMC peripheral base addresses */ 9042 #define PMC_BASE_ADDRS { PMC_BASE } 9043 /** Array initializer of PMC peripheral base pointers */ 9044 #define PMC_BASE_PTRS { PMC } 9045 /** Interrupt vectors for the PMC peripheral type */ 9046 #define PMC_IRQS { LVD_LVW_IRQn } 9047 9048 /*! 9049 * @} 9050 */ /* end of group PMC_Peripheral_Access_Layer */ 9051 9052 9053 /* ---------------------------------------------------------------------------- 9054 -- PORT Peripheral Access Layer 9055 ---------------------------------------------------------------------------- */ 9056 9057 /*! 9058 * @addtogroup PORT_Peripheral_Access_Layer PORT Peripheral Access Layer 9059 * @{ 9060 */ 9061 9062 /** PORT - Register Layout Typedef */ 9063 typedef struct { 9064 __IO uint32_t PCR[32]; /**< Pin Control Register n, array offset: 0x0, array step: 0x4 */ 9065 __O uint32_t GPCLR; /**< Global Pin Control Low Register, offset: 0x80 */ 9066 __O uint32_t GPCHR; /**< Global Pin Control High Register, offset: 0x84 */ 9067 uint8_t RESERVED_0[24]; 9068 __IO uint32_t ISFR; /**< Interrupt Status Flag Register, offset: 0xA0 */ 9069 uint8_t RESERVED_1[28]; 9070 __IO uint32_t DFER; /**< Digital Filter Enable Register, offset: 0xC0 */ 9071 __IO uint32_t DFCR; /**< Digital Filter Clock Register, offset: 0xC4 */ 9072 __IO uint32_t DFWR; /**< Digital Filter Width Register, offset: 0xC8 */ 9073 } PORT_Type; 9074 9075 /* ---------------------------------------------------------------------------- 9076 -- PORT Register Masks 9077 ---------------------------------------------------------------------------- */ 9078 9079 /*! 9080 * @addtogroup PORT_Register_Masks PORT Register Masks 9081 * @{ 9082 */ 9083 9084 /*! @name PCR - Pin Control Register n */ 9085 /*! @{ */ 9086 #define PORT_PCR_PS_MASK (0x1U) 9087 #define PORT_PCR_PS_SHIFT (0U) 9088 /*! PS - Pull Select 9089 * 0b0..Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. 9090 * 0b1..Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. 9091 */ 9092 #define PORT_PCR_PS(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_PS_SHIFT)) & PORT_PCR_PS_MASK) 9093 #define PORT_PCR_PE_MASK (0x2U) 9094 #define PORT_PCR_PE_SHIFT (1U) 9095 /*! PE - Pull Enable 9096 * 0b0..Internal pullup or pulldown resistor is not enabled on the corresponding pin. 9097 * 0b1..Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. 9098 */ 9099 #define PORT_PCR_PE(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_PE_SHIFT)) & PORT_PCR_PE_MASK) 9100 #define PORT_PCR_PFE_MASK (0x10U) 9101 #define PORT_PCR_PFE_SHIFT (4U) 9102 /*! PFE - Passive Filter Enable 9103 * 0b0..Passive input filter is disabled on the corresponding pin. 9104 * 0b1..Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. 9105 * Refer to the device data sheet for filter characteristics. 9106 */ 9107 #define PORT_PCR_PFE(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_PFE_SHIFT)) & PORT_PCR_PFE_MASK) 9108 #define PORT_PCR_DSE_MASK (0x40U) 9109 #define PORT_PCR_DSE_SHIFT (6U) 9110 /*! DSE - Drive Strength Enable 9111 * 0b0..Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. 9112 * 0b1..High drive strength is configured on the corresponding pin, if pin is configured as a digital output. 9113 */ 9114 #define PORT_PCR_DSE(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_DSE_SHIFT)) & PORT_PCR_DSE_MASK) 9115 #define PORT_PCR_MUX_MASK (0x700U) 9116 #define PORT_PCR_MUX_SHIFT (8U) 9117 /*! MUX - Pin Mux Control 9118 * 0b000..Pin disabled (Alternative 0) (analog). 9119 * 0b001..Alternative 1 (GPIO). 9120 * 0b010..Alternative 2 (chip-specific). 9121 * 0b011..Alternative 3 (chip-specific). 9122 * 0b100..Alternative 4 (chip-specific). 9123 * 0b101..Alternative 5 (chip-specific). 9124 * 0b110..Alternative 6 (chip-specific). 9125 * 0b111..Alternative 7 (chip-specific). 9126 */ 9127 #define PORT_PCR_MUX(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_MUX_SHIFT)) & PORT_PCR_MUX_MASK) 9128 #define PORT_PCR_LK_MASK (0x8000U) 9129 #define PORT_PCR_LK_SHIFT (15U) 9130 /*! LK - Lock Register 9131 * 0b0..Pin Control Register fields [15:0] are not locked. 9132 * 0b1..Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset. 9133 */ 9134 #define PORT_PCR_LK(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_LK_SHIFT)) & PORT_PCR_LK_MASK) 9135 #define PORT_PCR_IRQC_MASK (0xF0000U) 9136 #define PORT_PCR_IRQC_SHIFT (16U) 9137 /*! IRQC - Interrupt Configuration 9138 * 0b0000..Interrupt Status Flag (ISF) is disabled. 9139 * 0b0100..Reserved. 9140 * 0b0101..Reserved. 9141 * 0b0110..Reserved. 9142 * 0b0111..Reserved. 9143 * 0b1000..ISF flag and Interrupt when logic 0. 9144 * 0b1001..ISF flag and Interrupt on rising-edge. 9145 * 0b1010..ISF flag and Interrupt on falling-edge. 9146 * 0b1011..ISF flag and Interrupt on either edge. 9147 * 0b1100..ISF flag and Interrupt when logic 1. 9148 * 0b1101..Reserved. 9149 * 0b1110..Reserved. 9150 * 0b1111..Reserved. 9151 */ 9152 #define PORT_PCR_IRQC(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_IRQC_SHIFT)) & PORT_PCR_IRQC_MASK) 9153 #define PORT_PCR_ISF_MASK (0x1000000U) 9154 #define PORT_PCR_ISF_SHIFT (24U) 9155 /*! ISF - Interrupt Status Flag 9156 * 0b0..Configured interrupt is not detected. 9157 * 0b1..Configured interrupt is detected. The flag remains set until a logic 1 is written to the flag. If the pin 9158 * is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again 9159 * immediately after it is cleared. 9160 */ 9161 #define PORT_PCR_ISF(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_ISF_SHIFT)) & PORT_PCR_ISF_MASK) 9162 /*! @} */ 9163 9164 /* The count of PORT_PCR */ 9165 #define PORT_PCR_COUNT (32U) 9166 9167 /*! @name GPCLR - Global Pin Control Low Register */ 9168 /*! @{ */ 9169 #define PORT_GPCLR_GPWD_MASK (0xFFFFU) 9170 #define PORT_GPCLR_GPWD_SHIFT (0U) 9171 /*! GPWD - Global Pin Write Data 9172 */ 9173 #define PORT_GPCLR_GPWD(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCLR_GPWD_SHIFT)) & PORT_GPCLR_GPWD_MASK) 9174 #define PORT_GPCLR_GPWE_MASK (0xFFFF0000U) 9175 #define PORT_GPCLR_GPWE_SHIFT (16U) 9176 /*! GPWE - Global Pin Write Enable 9177 * 0b0000000000000000..Corresponding Pin Control Register is not updated with the value in GPWD. 9178 * 0b0000000000000001..Corresponding Pin Control Register is updated with the value in GPWD. 9179 */ 9180 #define PORT_GPCLR_GPWE(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCLR_GPWE_SHIFT)) & PORT_GPCLR_GPWE_MASK) 9181 /*! @} */ 9182 9183 /*! @name GPCHR - Global Pin Control High Register */ 9184 /*! @{ */ 9185 #define PORT_GPCHR_GPWD_MASK (0xFFFFU) 9186 #define PORT_GPCHR_GPWD_SHIFT (0U) 9187 /*! GPWD - Global Pin Write Data 9188 */ 9189 #define PORT_GPCHR_GPWD(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCHR_GPWD_SHIFT)) & PORT_GPCHR_GPWD_MASK) 9190 #define PORT_GPCHR_GPWE_MASK (0xFFFF0000U) 9191 #define PORT_GPCHR_GPWE_SHIFT (16U) 9192 /*! GPWE - Global Pin Write Enable 9193 * 0b0000000000000000..Corresponding Pin Control Register is not updated with the value in GPWD. 9194 * 0b0000000000000001..Corresponding Pin Control Register is updated with the value in GPWD. 9195 */ 9196 #define PORT_GPCHR_GPWE(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCHR_GPWE_SHIFT)) & PORT_GPCHR_GPWE_MASK) 9197 /*! @} */ 9198 9199 /*! @name ISFR - Interrupt Status Flag Register */ 9200 /*! @{ */ 9201 #define PORT_ISFR_ISF_MASK (0xFFFFFFFFU) 9202 #define PORT_ISFR_ISF_SHIFT (0U) 9203 /*! ISF - Interrupt Status Flag 9204 * 0b00000000000000000000000000000000..Configured interrupt is not detected. 9205 * 0b00000000000000000000000000000001..Configured interrupt is detected. The flag remains set until a logic 1 is 9206 * written to the flag. If the pin is configured for a level sensitive 9207 * interrupt and the pin remains asserted, then the flag is set again immediately 9208 * after it is cleared. 9209 */ 9210 #define PORT_ISFR_ISF(x) (((uint32_t)(((uint32_t)(x)) << PORT_ISFR_ISF_SHIFT)) & PORT_ISFR_ISF_MASK) 9211 /*! @} */ 9212 9213 /*! @name DFER - Digital Filter Enable Register */ 9214 /*! @{ */ 9215 #define PORT_DFER_DFE_MASK (0xFFFFFFFFU) 9216 #define PORT_DFER_DFE_SHIFT (0U) 9217 /*! DFE - Digital Filter Enable 9218 * 0b00000000000000000000000000000000..Digital filter is disabled on the corresponding pin and output of the digital filter is reset to zero. 9219 * 0b00000000000000000000000000000001..Digital filter is enabled on the corresponding pin, if the pin is configured as a digital input. 9220 */ 9221 #define PORT_DFER_DFE(x) (((uint32_t)(((uint32_t)(x)) << PORT_DFER_DFE_SHIFT)) & PORT_DFER_DFE_MASK) 9222 /*! @} */ 9223 9224 /*! @name DFCR - Digital Filter Clock Register */ 9225 /*! @{ */ 9226 #define PORT_DFCR_CS_MASK (0x1U) 9227 #define PORT_DFCR_CS_SHIFT (0U) 9228 /*! CS - Clock Source 9229 * 0b0..Digital filters are clocked by the bus clock. 9230 * 0b1..Digital filters are clocked by the LPO clock. 9231 */ 9232 #define PORT_DFCR_CS(x) (((uint32_t)(((uint32_t)(x)) << PORT_DFCR_CS_SHIFT)) & PORT_DFCR_CS_MASK) 9233 /*! @} */ 9234 9235 /*! @name DFWR - Digital Filter Width Register */ 9236 /*! @{ */ 9237 #define PORT_DFWR_FILT_MASK (0x1FU) 9238 #define PORT_DFWR_FILT_SHIFT (0U) 9239 /*! FILT - Filter Length 9240 */ 9241 #define PORT_DFWR_FILT(x) (((uint32_t)(((uint32_t)(x)) << PORT_DFWR_FILT_SHIFT)) & PORT_DFWR_FILT_MASK) 9242 /*! @} */ 9243 9244 9245 /*! 9246 * @} 9247 */ /* end of group PORT_Register_Masks */ 9248 9249 9250 /* PORT - Peripheral instance base addresses */ 9251 /** Peripheral PORTA base address */ 9252 #define PORTA_BASE (0x40049000u) 9253 /** Peripheral PORTA base pointer */ 9254 #define PORTA ((PORT_Type *)PORTA_BASE) 9255 /** Peripheral PORTB base address */ 9256 #define PORTB_BASE (0x4004A000u) 9257 /** Peripheral PORTB base pointer */ 9258 #define PORTB ((PORT_Type *)PORTB_BASE) 9259 /** Peripheral PORTC base address */ 9260 #define PORTC_BASE (0x4004B000u) 9261 /** Peripheral PORTC base pointer */ 9262 #define PORTC ((PORT_Type *)PORTC_BASE) 9263 /** Peripheral PORTD base address */ 9264 #define PORTD_BASE (0x4004C000u) 9265 /** Peripheral PORTD base pointer */ 9266 #define PORTD ((PORT_Type *)PORTD_BASE) 9267 /** Peripheral PORTE base address */ 9268 #define PORTE_BASE (0x4004D000u) 9269 /** Peripheral PORTE base pointer */ 9270 #define PORTE ((PORT_Type *)PORTE_BASE) 9271 /** Array initializer of PORT peripheral base addresses */ 9272 #define PORT_BASE_ADDRS { PORTA_BASE, PORTB_BASE, PORTC_BASE, PORTD_BASE, PORTE_BASE } 9273 /** Array initializer of PORT peripheral base pointers */ 9274 #define PORT_BASE_PTRS { PORTA, PORTB, PORTC, PORTD, PORTE } 9275 /** Interrupt vectors for the PORT peripheral type */ 9276 #define PORT_IRQS { PORTAE_IRQn, PORTBCD_IRQn, PORTBCD_IRQn, PORTBCD_IRQn, PORTAE_IRQn } 9277 9278 /*! 9279 * @} 9280 */ /* end of group PORT_Peripheral_Access_Layer */ 9281 9282 9283 /* ---------------------------------------------------------------------------- 9284 -- PWT Peripheral Access Layer 9285 ---------------------------------------------------------------------------- */ 9286 9287 /*! 9288 * @addtogroup PWT_Peripheral_Access_Layer PWT Peripheral Access Layer 9289 * @{ 9290 */ 9291 9292 /** PWT - Register Layout Typedef */ 9293 typedef struct { 9294 __IO uint8_t CS; /**< Pulse Width Timer Control and Status Register, offset: 0x0 */ 9295 __IO uint8_t CR; /**< Pulse Width Timer Control Register, offset: 0x1 */ 9296 __I uint8_t PPH; /**< Pulse Width Timer Positive Pulse Width Register: High, offset: 0x2 */ 9297 __I uint8_t PPL; /**< Pulse Width Timer Positive Pulse Width Register: Loq, offset: 0x3 */ 9298 __I uint8_t NPH; /**< Pulse Width Timer Negative Pulse Width Register: High, offset: 0x4 */ 9299 __I uint8_t NPL; /**< Pulse Width Timer Negative Pulse Width Register: Low, offset: 0x5 */ 9300 __I uint8_t CNTH; /**< Pulse Width Timer Counter Register: High, offset: 0x6 */ 9301 __I uint8_t CNTL; /**< Pulse Width Timer Counter Register: Low, offset: 0x7 */ 9302 } PWT_Type; 9303 9304 /* ---------------------------------------------------------------------------- 9305 -- PWT Register Masks 9306 ---------------------------------------------------------------------------- */ 9307 9308 /*! 9309 * @addtogroup PWT_Register_Masks PWT Register Masks 9310 * @{ 9311 */ 9312 9313 /*! @name CS - Pulse Width Timer Control and Status Register */ 9314 /*! @{ */ 9315 #define PWT_CS_PWTOV_MASK (0x1U) 9316 #define PWT_CS_PWTOV_SHIFT (0U) 9317 /*! PWTOV - PWT Counter Overflow 9318 * 0b0..PWT counter no overflow. 9319 * 0b1..PWT counter runs from 0xFFFF to 0x0000. 9320 */ 9321 #define PWT_CS_PWTOV(x) (((uint8_t)(((uint8_t)(x)) << PWT_CS_PWTOV_SHIFT)) & PWT_CS_PWTOV_MASK) 9322 #define PWT_CS_PWTRDY_MASK (0x2U) 9323 #define PWT_CS_PWTRDY_SHIFT (1U) 9324 /*! PWTRDY - PWT Pulse Width Valid 9325 * 0b0..PWT pulse width register(s) is not up-to-date. 9326 * 0b1..PWT pulse width register(s) has been updated. 9327 */ 9328 #define PWT_CS_PWTRDY(x) (((uint8_t)(((uint8_t)(x)) << PWT_CS_PWTRDY_SHIFT)) & PWT_CS_PWTRDY_MASK) 9329 #define PWT_CS_FCTLE_MASK (0x4U) 9330 #define PWT_CS_FCTLE_SHIFT (2U) 9331 /*! FCTLE - First counter load enable after enable 9332 * 0b0..Do not load the first counter values to corresponding registers 9333 * 0b1..Load the first coutner value to corresponding registers depended by the PWTIN level 9334 */ 9335 #define PWT_CS_FCTLE(x) (((uint8_t)(((uint8_t)(x)) << PWT_CS_FCTLE_SHIFT)) & PWT_CS_FCTLE_MASK) 9336 #define PWT_CS_PWTSR_MASK (0x8U) 9337 #define PWT_CS_PWTSR_SHIFT (3U) 9338 /*! PWTSR - PWT Soft Reset 9339 * 0b0..No action taken. 9340 * 0b1..Writing 1 to this field will perform soft reset to PWT. 9341 */ 9342 #define PWT_CS_PWTSR(x) (((uint8_t)(((uint8_t)(x)) << PWT_CS_PWTSR_SHIFT)) & PWT_CS_PWTSR_MASK) 9343 #define PWT_CS_POVIE_MASK (0x10U) 9344 #define PWT_CS_POVIE_SHIFT (4U) 9345 /*! POVIE - PWT Counter Overflow Interrupt Enable 9346 * 0b0..Disable PWT to generate interrupt when PWTOV is set. 9347 * 0b1..Enable PWT to generate interrupt when PWTOV is set. 9348 */ 9349 #define PWT_CS_POVIE(x) (((uint8_t)(((uint8_t)(x)) << PWT_CS_POVIE_SHIFT)) & PWT_CS_POVIE_MASK) 9350 #define PWT_CS_PRDYIE_MASK (0x20U) 9351 #define PWT_CS_PRDYIE_SHIFT (5U) 9352 /*! PRDYIE - PWT Pulse Width Data Ready Interrupt Enable 9353 * 0b0..Disable PWT to generate interrupt when PWTRDY is set. 9354 * 0b1..Enable PWT to generate interrupt when PWTRDY is set. 9355 */ 9356 #define PWT_CS_PRDYIE(x) (((uint8_t)(((uint8_t)(x)) << PWT_CS_PRDYIE_SHIFT)) & PWT_CS_PRDYIE_MASK) 9357 #define PWT_CS_PWTIE_MASK (0x40U) 9358 #define PWT_CS_PWTIE_SHIFT (6U) 9359 /*! PWTIE - PWT Module Interrupt Enable 9360 * 0b0..Disables the PWT to generate interrupt. 9361 * 0b1..Enables the PWT to generate interrupt. 9362 */ 9363 #define PWT_CS_PWTIE(x) (((uint8_t)(((uint8_t)(x)) << PWT_CS_PWTIE_SHIFT)) & PWT_CS_PWTIE_MASK) 9364 #define PWT_CS_PWTEN_MASK (0x80U) 9365 #define PWT_CS_PWTEN_SHIFT (7U) 9366 /*! PWTEN - PWT Module Enable 9367 * 0b0..The PWT is disabled. 9368 * 0b1..The PWT is enabled. 9369 */ 9370 #define PWT_CS_PWTEN(x) (((uint8_t)(((uint8_t)(x)) << PWT_CS_PWTEN_SHIFT)) & PWT_CS_PWTEN_MASK) 9371 /*! @} */ 9372 9373 /*! @name CR - Pulse Width Timer Control Register */ 9374 /*! @{ */ 9375 #define PWT_CR_PRE_MASK (0x7U) 9376 #define PWT_CR_PRE_SHIFT (0U) 9377 /*! PRE - PWT Clock Prescaler (CLKPRE) Setting 9378 * 0b000..Clock divided by 1. 9379 * 0b001..Clock divided by 2. 9380 * 0b010..Clock divided by 4. 9381 * 0b011..Clock divided by 8. 9382 * 0b100..Clock divided by 16. 9383 * 0b101..Clock divided by 32. 9384 * 0b110..Clock divided by 64. 9385 * 0b111..Clock divided by 128. 9386 */ 9387 #define PWT_CR_PRE(x) (((uint8_t)(((uint8_t)(x)) << PWT_CR_PRE_SHIFT)) & PWT_CR_PRE_MASK) 9388 #define PWT_CR_LVL_MASK (0x8U) 9389 #define PWT_CR_LVL_SHIFT (3U) 9390 /*! LVL - PWTIN Level when Overflows 9391 */ 9392 #define PWT_CR_LVL(x) (((uint8_t)(((uint8_t)(x)) << PWT_CR_LVL_SHIFT)) & PWT_CR_LVL_MASK) 9393 #define PWT_CR_TGL_MASK (0x10U) 9394 #define PWT_CR_TGL_SHIFT (4U) 9395 /*! TGL - PWTIN states Toggled from last state 9396 * 0b0..The selected PWTIN hasn't changed its original states from last time. 9397 * 0b1..The selected PWTIN has toggled its states. 9398 */ 9399 #define PWT_CR_TGL(x) (((uint8_t)(((uint8_t)(x)) << PWT_CR_TGL_SHIFT)) & PWT_CR_TGL_MASK) 9400 #define PWT_CR_PINSEL_MASK (0x60U) 9401 #define PWT_CR_PINSEL_SHIFT (5U) 9402 /*! PINSEL - PWT Pulse Inputs Selection 9403 * 0b00..PWTIN[0] is enabled. 9404 * 0b01..PWTIN[1] is enabled. 9405 * 0b10..PWTIN[2] enabled. 9406 * 0b11..PWTIN[3] enabled. 9407 */ 9408 #define PWT_CR_PINSEL(x) (((uint8_t)(((uint8_t)(x)) << PWT_CR_PINSEL_SHIFT)) & PWT_CR_PINSEL_MASK) 9409 #define PWT_CR_PCLKS_MASK (0x80U) 9410 #define PWT_CR_PCLKS_SHIFT (7U) 9411 /*! PCLKS - PWT Clock Source Selection 9412 * 0b0..BUS_CLK is selected as the clock source of PWT counter. 9413 * 0b1..Alternative clock is selected as the clock source of PWT counter. 9414 */ 9415 #define PWT_CR_PCLKS(x) (((uint8_t)(((uint8_t)(x)) << PWT_CR_PCLKS_SHIFT)) & PWT_CR_PCLKS_MASK) 9416 /*! @} */ 9417 9418 /*! @name PPH - Pulse Width Timer Positive Pulse Width Register: High */ 9419 /*! @{ */ 9420 #define PWT_PPH_PPWH_MASK (0xFFU) 9421 #define PWT_PPH_PPWH_SHIFT (0U) 9422 /*! PPWH - Positive Pulse Width[15:8] 9423 */ 9424 #define PWT_PPH_PPWH(x) (((uint8_t)(((uint8_t)(x)) << PWT_PPH_PPWH_SHIFT)) & PWT_PPH_PPWH_MASK) 9425 /*! @} */ 9426 9427 /*! @name PPL - Pulse Width Timer Positive Pulse Width Register: Loq */ 9428 /*! @{ */ 9429 #define PWT_PPL_PPWL_MASK (0xFFU) 9430 #define PWT_PPL_PPWL_SHIFT (0U) 9431 /*! PPWL - Positive Pulse Width[7:0] 9432 */ 9433 #define PWT_PPL_PPWL(x) (((uint8_t)(((uint8_t)(x)) << PWT_PPL_PPWL_SHIFT)) & PWT_PPL_PPWL_MASK) 9434 /*! @} */ 9435 9436 /*! @name NPH - Pulse Width Timer Negative Pulse Width Register: High */ 9437 /*! @{ */ 9438 #define PWT_NPH_NPWH_MASK (0xFFU) 9439 #define PWT_NPH_NPWH_SHIFT (0U) 9440 /*! NPWH - Negative Pulse Width[15:8] 9441 */ 9442 #define PWT_NPH_NPWH(x) (((uint8_t)(((uint8_t)(x)) << PWT_NPH_NPWH_SHIFT)) & PWT_NPH_NPWH_MASK) 9443 /*! @} */ 9444 9445 /*! @name NPL - Pulse Width Timer Negative Pulse Width Register: Low */ 9446 /*! @{ */ 9447 #define PWT_NPL_NPWL_MASK (0xFFU) 9448 #define PWT_NPL_NPWL_SHIFT (0U) 9449 /*! NPWL - Negative Pulse Width[7:0] 9450 */ 9451 #define PWT_NPL_NPWL(x) (((uint8_t)(((uint8_t)(x)) << PWT_NPL_NPWL_SHIFT)) & PWT_NPL_NPWL_MASK) 9452 /*! @} */ 9453 9454 /*! @name CNTH - Pulse Width Timer Counter Register: High */ 9455 /*! @{ */ 9456 #define PWT_CNTH_PWTH_MASK (0xFFU) 9457 #define PWT_CNTH_PWTH_SHIFT (0U) 9458 /*! PWTH - PWT counter[15:8] 9459 */ 9460 #define PWT_CNTH_PWTH(x) (((uint8_t)(((uint8_t)(x)) << PWT_CNTH_PWTH_SHIFT)) & PWT_CNTH_PWTH_MASK) 9461 /*! @} */ 9462 9463 /*! @name CNTL - Pulse Width Timer Counter Register: Low */ 9464 /*! @{ */ 9465 #define PWT_CNTL_PWTL_MASK (0xFFU) 9466 #define PWT_CNTL_PWTL_SHIFT (0U) 9467 /*! PWTL - PWT counter[7:0] 9468 */ 9469 #define PWT_CNTL_PWTL(x) (((uint8_t)(((uint8_t)(x)) << PWT_CNTL_PWTL_SHIFT)) & PWT_CNTL_PWTL_MASK) 9470 /*! @} */ 9471 9472 9473 /*! 9474 * @} 9475 */ /* end of group PWT_Register_Masks */ 9476 9477 9478 /* PWT - Peripheral instance base addresses */ 9479 /** Peripheral PWT base address */ 9480 #define PWT_BASE (0x40056000u) 9481 /** Peripheral PWT base pointer */ 9482 #define PWT ((PWT_Type *)PWT_BASE) 9483 /** Array initializer of PWT peripheral base addresses */ 9484 #define PWT_BASE_ADDRS { PWT_BASE } 9485 /** Array initializer of PWT peripheral base pointers */ 9486 #define PWT_BASE_PTRS { PWT } 9487 /** Interrupt vectors for the PWT peripheral type */ 9488 #define PWT_IRQS { PWT_LPTMR0_IRQn } 9489 9490 /*! 9491 * @} 9492 */ /* end of group PWT_Peripheral_Access_Layer */ 9493 9494 9495 /* ---------------------------------------------------------------------------- 9496 -- RCM Peripheral Access Layer 9497 ---------------------------------------------------------------------------- */ 9498 9499 /*! 9500 * @addtogroup RCM_Peripheral_Access_Layer RCM Peripheral Access Layer 9501 * @{ 9502 */ 9503 9504 /** RCM - Register Layout Typedef */ 9505 typedef struct { 9506 __I uint32_t VERID; /**< Version ID Register, offset: 0x0 */ 9507 uint8_t RESERVED_0[4]; 9508 __I uint32_t SRS; /**< System Reset Status Register, offset: 0x8 */ 9509 __IO uint32_t RPC; /**< Reset Pin Control register, offset: 0xC */ 9510 __IO uint32_t MR; /**< Mode Register, offset: 0x10 */ 9511 __IO uint32_t FM; /**< Force Mode Register, offset: 0x14 */ 9512 __IO uint32_t SSRS; /**< Sticky System Reset Status Register, offset: 0x18 */ 9513 __IO uint32_t SRIE; /**< System Reset Interrupt Enable Register, offset: 0x1C */ 9514 } RCM_Type; 9515 9516 /* ---------------------------------------------------------------------------- 9517 -- RCM Register Masks 9518 ---------------------------------------------------------------------------- */ 9519 9520 /*! 9521 * @addtogroup RCM_Register_Masks RCM Register Masks 9522 * @{ 9523 */ 9524 9525 /*! @name VERID - Version ID Register */ 9526 /*! @{ */ 9527 #define RCM_VERID_FEATURE_MASK (0xFFFFU) 9528 #define RCM_VERID_FEATURE_SHIFT (0U) 9529 /*! FEATURE - Feature Specification Number 9530 * 0b0000000000000011..Standard feature set. 9531 */ 9532 #define RCM_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << RCM_VERID_FEATURE_SHIFT)) & RCM_VERID_FEATURE_MASK) 9533 #define RCM_VERID_MINOR_MASK (0xFF0000U) 9534 #define RCM_VERID_MINOR_SHIFT (16U) 9535 /*! MINOR - Minor Version Number 9536 */ 9537 #define RCM_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << RCM_VERID_MINOR_SHIFT)) & RCM_VERID_MINOR_MASK) 9538 #define RCM_VERID_MAJOR_MASK (0xFF000000U) 9539 #define RCM_VERID_MAJOR_SHIFT (24U) 9540 /*! MAJOR - Major Version Number 9541 */ 9542 #define RCM_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << RCM_VERID_MAJOR_SHIFT)) & RCM_VERID_MAJOR_MASK) 9543 /*! @} */ 9544 9545 /*! @name SRS - System Reset Status Register */ 9546 /*! @{ */ 9547 #define RCM_SRS_LVD_MASK (0x2U) 9548 #define RCM_SRS_LVD_SHIFT (1U) 9549 /*! LVD - Low-Voltage Detect Reset or High-Voltage Detect Reset 9550 * 0b0..Reset not caused by LVD trip, HVD trip or POR 9551 * 0b1..Reset caused by LVD trip, HVD trip or POR 9552 */ 9553 #define RCM_SRS_LVD(x) (((uint32_t)(((uint32_t)(x)) << RCM_SRS_LVD_SHIFT)) & RCM_SRS_LVD_MASK) 9554 #define RCM_SRS_LOC_MASK (0x4U) 9555 #define RCM_SRS_LOC_SHIFT (2U) 9556 /*! LOC - Loss-of-Clock Reset 9557 * 0b0..Reset not caused by a loss of external clock. 9558 * 0b1..Reset caused by a loss of external clock. 9559 */ 9560 #define RCM_SRS_LOC(x) (((uint32_t)(((uint32_t)(x)) << RCM_SRS_LOC_SHIFT)) & RCM_SRS_LOC_MASK) 9561 #define RCM_SRS_LOL_MASK (0x8U) 9562 #define RCM_SRS_LOL_SHIFT (3U) 9563 /*! LOL - Loss-of-Lock Reset 9564 * 0b0..Reset not caused by a loss of lock in the PLL/FLL 9565 * 0b1..Reset caused by a loss of lock in the PLL/FLL 9566 */ 9567 #define RCM_SRS_LOL(x) (((uint32_t)(((uint32_t)(x)) << RCM_SRS_LOL_SHIFT)) & RCM_SRS_LOL_MASK) 9568 #define RCM_SRS_WDOG_MASK (0x20U) 9569 #define RCM_SRS_WDOG_SHIFT (5U) 9570 /*! WDOG - Watchdog 9571 * 0b0..Reset not caused by watchdog timeout 9572 * 0b1..Reset caused by watchdog timeout 9573 */ 9574 #define RCM_SRS_WDOG(x) (((uint32_t)(((uint32_t)(x)) << RCM_SRS_WDOG_SHIFT)) & RCM_SRS_WDOG_MASK) 9575 #define RCM_SRS_PIN_MASK (0x40U) 9576 #define RCM_SRS_PIN_SHIFT (6U) 9577 /*! PIN - External Reset Pin 9578 * 0b0..Reset not caused by external reset pin 9579 * 0b1..Reset caused by external reset pin 9580 */ 9581 #define RCM_SRS_PIN(x) (((uint32_t)(((uint32_t)(x)) << RCM_SRS_PIN_SHIFT)) & RCM_SRS_PIN_MASK) 9582 #define RCM_SRS_POR_MASK (0x80U) 9583 #define RCM_SRS_POR_SHIFT (7U) 9584 /*! POR - Power-On Reset 9585 * 0b0..Reset not caused by POR 9586 * 0b1..Reset caused by POR 9587 */ 9588 #define RCM_SRS_POR(x) (((uint32_t)(((uint32_t)(x)) << RCM_SRS_POR_SHIFT)) & RCM_SRS_POR_MASK) 9589 #define RCM_SRS_LOCKUP_MASK (0x200U) 9590 #define RCM_SRS_LOCKUP_SHIFT (9U) 9591 /*! LOCKUP - Core Lockup 9592 * 0b0..Reset not caused by core LOCKUP event 9593 * 0b1..Reset caused by core LOCKUP event 9594 */ 9595 #define RCM_SRS_LOCKUP(x) (((uint32_t)(((uint32_t)(x)) << RCM_SRS_LOCKUP_SHIFT)) & RCM_SRS_LOCKUP_MASK) 9596 #define RCM_SRS_SW_MASK (0x400U) 9597 #define RCM_SRS_SW_SHIFT (10U) 9598 /*! SW - Software 9599 * 0b0..Reset not caused by software setting of SYSRESETREQ bit 9600 * 0b1..Reset caused by software setting of SYSRESETREQ bit 9601 */ 9602 #define RCM_SRS_SW(x) (((uint32_t)(((uint32_t)(x)) << RCM_SRS_SW_SHIFT)) & RCM_SRS_SW_MASK) 9603 #define RCM_SRS_MDM_AP_MASK (0x800U) 9604 #define RCM_SRS_MDM_AP_SHIFT (11U) 9605 /*! MDM_AP - MDM-AP System Reset Request 9606 * 0b0..Reset was not caused by host debugger system setting of the System Reset Request bit 9607 * 0b1..Reset was caused by host debugger system setting of the System Reset Request bit 9608 */ 9609 #define RCM_SRS_MDM_AP(x) (((uint32_t)(((uint32_t)(x)) << RCM_SRS_MDM_AP_SHIFT)) & RCM_SRS_MDM_AP_MASK) 9610 #define RCM_SRS_SACKERR_MASK (0x2000U) 9611 #define RCM_SRS_SACKERR_SHIFT (13U) 9612 /*! SACKERR - Stop Acknowledge Error 9613 * 0b0..Reset not caused by peripheral failure to acknowledge attempt to enter stop mode 9614 * 0b1..Reset caused by peripheral failure to acknowledge attempt to enter stop mode 9615 */ 9616 #define RCM_SRS_SACKERR(x) (((uint32_t)(((uint32_t)(x)) << RCM_SRS_SACKERR_SHIFT)) & RCM_SRS_SACKERR_MASK) 9617 /*! @} */ 9618 9619 /*! @name RPC - Reset Pin Control register */ 9620 /*! @{ */ 9621 #define RCM_RPC_RSTFLTSRW_MASK (0x3U) 9622 #define RCM_RPC_RSTFLTSRW_SHIFT (0U) 9623 /*! RSTFLTSRW - Reset Pin Filter Select in Run and Wait Modes 9624 * 0b00..All filtering disabled 9625 * 0b01..Bus clock filter enabled for normal operation 9626 * 0b10..LPO clock filter enabled for normal operation 9627 * 0b11..Reserved 9628 */ 9629 #define RCM_RPC_RSTFLTSRW(x) (((uint32_t)(((uint32_t)(x)) << RCM_RPC_RSTFLTSRW_SHIFT)) & RCM_RPC_RSTFLTSRW_MASK) 9630 #define RCM_RPC_RSTFLTSS_MASK (0x4U) 9631 #define RCM_RPC_RSTFLTSS_SHIFT (2U) 9632 /*! RSTFLTSS - Reset Pin Filter Select in Stop Mode 9633 * 0b0..All filtering disabled 9634 * 0b1..LPO clock filter enabled 9635 */ 9636 #define RCM_RPC_RSTFLTSS(x) (((uint32_t)(((uint32_t)(x)) << RCM_RPC_RSTFLTSS_SHIFT)) & RCM_RPC_RSTFLTSS_MASK) 9637 #define RCM_RPC_RSTFLTSEL_MASK (0x1F00U) 9638 #define RCM_RPC_RSTFLTSEL_SHIFT (8U) 9639 /*! RSTFLTSEL - Reset Pin Filter Bus Clock Select 9640 */ 9641 #define RCM_RPC_RSTFLTSEL(x) (((uint32_t)(((uint32_t)(x)) << RCM_RPC_RSTFLTSEL_SHIFT)) & RCM_RPC_RSTFLTSEL_MASK) 9642 /*! @} */ 9643 9644 /*! @name MR - Mode Register */ 9645 /*! @{ */ 9646 #define RCM_MR_BOOTROM_MASK (0x6U) 9647 #define RCM_MR_BOOTROM_SHIFT (1U) 9648 /*! BOOTROM - Boot ROM Configuration 9649 * 0b00..Boot from Flash 9650 * 0b01..Boot from ROM due to BOOTCFG0 pin assertion / Reserved if no Boot pin 9651 * 0b10..Boot form ROM due to FOPT[7] configuration 9652 * 0b11..Boot from ROM due to both BOOTCFG0 pin assertion and FOPT[7] configuration 9653 */ 9654 #define RCM_MR_BOOTROM(x) (((uint32_t)(((uint32_t)(x)) << RCM_MR_BOOTROM_SHIFT)) & RCM_MR_BOOTROM_MASK) 9655 /*! @} */ 9656 9657 /*! @name FM - Force Mode Register */ 9658 /*! @{ */ 9659 #define RCM_FM_FORCEROM_MASK (0x6U) 9660 #define RCM_FM_FORCEROM_SHIFT (1U) 9661 /*! FORCEROM - Force ROM Boot 9662 * 0b00..No effect 9663 * 0b01..Force boot from ROM with RCM_MR[1] set. 9664 * 0b10..Force boot from ROM with RCM_MR[2] set. 9665 * 0b11..Force boot from ROM with RCM_MR[2:1] set. 9666 */ 9667 #define RCM_FM_FORCEROM(x) (((uint32_t)(((uint32_t)(x)) << RCM_FM_FORCEROM_SHIFT)) & RCM_FM_FORCEROM_MASK) 9668 /*! @} */ 9669 9670 /*! @name SSRS - Sticky System Reset Status Register */ 9671 /*! @{ */ 9672 #define RCM_SSRS_SLVD_MASK (0x2U) 9673 #define RCM_SSRS_SLVD_SHIFT (1U) 9674 /*! SLVD - Sticky Low-Voltage Detect Reset 9675 * 0b0..Reset not caused by LVD trip or POR 9676 * 0b1..Reset caused by LVD trip or POR 9677 */ 9678 #define RCM_SSRS_SLVD(x) (((uint32_t)(((uint32_t)(x)) << RCM_SSRS_SLVD_SHIFT)) & RCM_SSRS_SLVD_MASK) 9679 #define RCM_SSRS_SLOC_MASK (0x4U) 9680 #define RCM_SSRS_SLOC_SHIFT (2U) 9681 /*! SLOC - Sticky Loss-of-Clock Reset 9682 * 0b0..Reset not caused by a loss of external clock. 9683 * 0b1..Reset caused by a loss of external clock. 9684 */ 9685 #define RCM_SSRS_SLOC(x) (((uint32_t)(((uint32_t)(x)) << RCM_SSRS_SLOC_SHIFT)) & RCM_SSRS_SLOC_MASK) 9686 #define RCM_SSRS_SLOL_MASK (0x8U) 9687 #define RCM_SSRS_SLOL_SHIFT (3U) 9688 /*! SLOL - Sticky Loss-of-Lock Reset 9689 * 0b0..Reset not caused by a loss of lock in the PLL/FLL 9690 * 0b1..Reset caused by a loss of lock in the PLL/FLL 9691 */ 9692 #define RCM_SSRS_SLOL(x) (((uint32_t)(((uint32_t)(x)) << RCM_SSRS_SLOL_SHIFT)) & RCM_SSRS_SLOL_MASK) 9693 #define RCM_SSRS_SWDOG_MASK (0x20U) 9694 #define RCM_SSRS_SWDOG_SHIFT (5U) 9695 /*! SWDOG - Sticky Watchdog 9696 * 0b0..Reset not caused by watchdog timeout 9697 * 0b1..Reset caused by watchdog timeout 9698 */ 9699 #define RCM_SSRS_SWDOG(x) (((uint32_t)(((uint32_t)(x)) << RCM_SSRS_SWDOG_SHIFT)) & RCM_SSRS_SWDOG_MASK) 9700 #define RCM_SSRS_SPIN_MASK (0x40U) 9701 #define RCM_SSRS_SPIN_SHIFT (6U) 9702 /*! SPIN - Sticky External Reset Pin 9703 * 0b0..Reset not caused by external reset pin 9704 * 0b1..Reset caused by external reset pin 9705 */ 9706 #define RCM_SSRS_SPIN(x) (((uint32_t)(((uint32_t)(x)) << RCM_SSRS_SPIN_SHIFT)) & RCM_SSRS_SPIN_MASK) 9707 #define RCM_SSRS_SPOR_MASK (0x80U) 9708 #define RCM_SSRS_SPOR_SHIFT (7U) 9709 /*! SPOR - Sticky Power-On Reset 9710 * 0b0..Reset not caused by POR 9711 * 0b1..Reset caused by POR 9712 */ 9713 #define RCM_SSRS_SPOR(x) (((uint32_t)(((uint32_t)(x)) << RCM_SSRS_SPOR_SHIFT)) & RCM_SSRS_SPOR_MASK) 9714 #define RCM_SSRS_SLOCKUP_MASK (0x200U) 9715 #define RCM_SSRS_SLOCKUP_SHIFT (9U) 9716 /*! SLOCKUP - Sticky Core Lockup 9717 * 0b0..Reset not caused by core LOCKUP event 9718 * 0b1..Reset caused by core LOCKUP event 9719 */ 9720 #define RCM_SSRS_SLOCKUP(x) (((uint32_t)(((uint32_t)(x)) << RCM_SSRS_SLOCKUP_SHIFT)) & RCM_SSRS_SLOCKUP_MASK) 9721 #define RCM_SSRS_SSW_MASK (0x400U) 9722 #define RCM_SSRS_SSW_SHIFT (10U) 9723 /*! SSW - Sticky Software 9724 * 0b0..Reset not caused by software setting of SYSRESETREQ bit 9725 * 0b1..Reset caused by software setting of SYSRESETREQ bit 9726 */ 9727 #define RCM_SSRS_SSW(x) (((uint32_t)(((uint32_t)(x)) << RCM_SSRS_SSW_SHIFT)) & RCM_SSRS_SSW_MASK) 9728 #define RCM_SSRS_SMDM_AP_MASK (0x800U) 9729 #define RCM_SSRS_SMDM_AP_SHIFT (11U) 9730 /*! SMDM_AP - Sticky MDM-AP System Reset Request 9731 * 0b0..Reset was not caused by host debugger system setting of the System Reset Request bit 9732 * 0b1..Reset was caused by host debugger system setting of the System Reset Request bit 9733 */ 9734 #define RCM_SSRS_SMDM_AP(x) (((uint32_t)(((uint32_t)(x)) << RCM_SSRS_SMDM_AP_SHIFT)) & RCM_SSRS_SMDM_AP_MASK) 9735 #define RCM_SSRS_SSACKERR_MASK (0x2000U) 9736 #define RCM_SSRS_SSACKERR_SHIFT (13U) 9737 /*! SSACKERR - Sticky Stop Acknowledge Error 9738 * 0b0..Reset not caused by peripheral failure to acknowledge attempt to enter stop mode 9739 * 0b1..Reset caused by peripheral failure to acknowledge attempt to enter stop mode 9740 */ 9741 #define RCM_SSRS_SSACKERR(x) (((uint32_t)(((uint32_t)(x)) << RCM_SSRS_SSACKERR_SHIFT)) & RCM_SSRS_SSACKERR_MASK) 9742 /*! @} */ 9743 9744 /*! @name SRIE - System Reset Interrupt Enable Register */ 9745 /*! @{ */ 9746 #define RCM_SRIE_DELAY_MASK (0x3U) 9747 #define RCM_SRIE_DELAY_SHIFT (0U) 9748 /*! DELAY - Reset Delay Time 9749 * 0b00..10 LPO cycles 9750 * 0b01..34 LPO cycles 9751 * 0b10..130 LPO cycles 9752 * 0b11..514 LPO cycles 9753 */ 9754 #define RCM_SRIE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << RCM_SRIE_DELAY_SHIFT)) & RCM_SRIE_DELAY_MASK) 9755 #define RCM_SRIE_LOC_MASK (0x4U) 9756 #define RCM_SRIE_LOC_SHIFT (2U) 9757 /*! LOC - Loss-of-Clock Interrupt 9758 * 0b0..Interrupt disabled. 9759 * 0b1..Interrupt enabled. 9760 */ 9761 #define RCM_SRIE_LOC(x) (((uint32_t)(((uint32_t)(x)) << RCM_SRIE_LOC_SHIFT)) & RCM_SRIE_LOC_MASK) 9762 #define RCM_SRIE_LOL_MASK (0x8U) 9763 #define RCM_SRIE_LOL_SHIFT (3U) 9764 /*! LOL - Loss-of-Lock Interrupt 9765 * 0b0..Interrupt disabled. 9766 * 0b1..Interrupt enabled. 9767 */ 9768 #define RCM_SRIE_LOL(x) (((uint32_t)(((uint32_t)(x)) << RCM_SRIE_LOL_SHIFT)) & RCM_SRIE_LOL_MASK) 9769 #define RCM_SRIE_WDOG_MASK (0x20U) 9770 #define RCM_SRIE_WDOG_SHIFT (5U) 9771 /*! WDOG - Watchdog Interrupt 9772 * 0b0..Interrupt disabled. 9773 * 0b1..Interrupt enabled. 9774 */ 9775 #define RCM_SRIE_WDOG(x) (((uint32_t)(((uint32_t)(x)) << RCM_SRIE_WDOG_SHIFT)) & RCM_SRIE_WDOG_MASK) 9776 #define RCM_SRIE_PIN_MASK (0x40U) 9777 #define RCM_SRIE_PIN_SHIFT (6U) 9778 /*! PIN - External Reset Pin Interrupt 9779 * 0b0..Reset not caused by external reset pin 9780 * 0b1..Reset caused by external reset pin 9781 */ 9782 #define RCM_SRIE_PIN(x) (((uint32_t)(((uint32_t)(x)) << RCM_SRIE_PIN_SHIFT)) & RCM_SRIE_PIN_MASK) 9783 #define RCM_SRIE_GIE_MASK (0x80U) 9784 #define RCM_SRIE_GIE_SHIFT (7U) 9785 /*! GIE - Global Interrupt Enable 9786 * 0b0..All interrupt sources disabled. 9787 * 0b1..All interrupt sources enabled. Note that the individual interrupt-enable bits still need to be set to generate interrupts. 9788 */ 9789 #define RCM_SRIE_GIE(x) (((uint32_t)(((uint32_t)(x)) << RCM_SRIE_GIE_SHIFT)) & RCM_SRIE_GIE_MASK) 9790 #define RCM_SRIE_LOCKUP_MASK (0x200U) 9791 #define RCM_SRIE_LOCKUP_SHIFT (9U) 9792 /*! LOCKUP - Core Lockup Interrupt 9793 * 0b0..Interrupt disabled. 9794 * 0b1..Interrupt enabled. 9795 */ 9796 #define RCM_SRIE_LOCKUP(x) (((uint32_t)(((uint32_t)(x)) << RCM_SRIE_LOCKUP_SHIFT)) & RCM_SRIE_LOCKUP_MASK) 9797 #define RCM_SRIE_SW_MASK (0x400U) 9798 #define RCM_SRIE_SW_SHIFT (10U) 9799 /*! SW - Software Interrupt 9800 * 0b0..Interrupt disabled. 9801 * 0b1..Interrupt enabled. 9802 */ 9803 #define RCM_SRIE_SW(x) (((uint32_t)(((uint32_t)(x)) << RCM_SRIE_SW_SHIFT)) & RCM_SRIE_SW_MASK) 9804 #define RCM_SRIE_MDM_AP_MASK (0x800U) 9805 #define RCM_SRIE_MDM_AP_SHIFT (11U) 9806 /*! MDM_AP - MDM-AP System Reset Request 9807 * 0b0..Interrupt disabled. 9808 * 0b1..Interrupt enabled. 9809 */ 9810 #define RCM_SRIE_MDM_AP(x) (((uint32_t)(((uint32_t)(x)) << RCM_SRIE_MDM_AP_SHIFT)) & RCM_SRIE_MDM_AP_MASK) 9811 #define RCM_SRIE_SACKERR_MASK (0x2000U) 9812 #define RCM_SRIE_SACKERR_SHIFT (13U) 9813 /*! SACKERR - Stop Acknowledge Error Interrupt 9814 * 0b0..Interrupt disabled. 9815 * 0b1..Interrupt enabled. 9816 */ 9817 #define RCM_SRIE_SACKERR(x) (((uint32_t)(((uint32_t)(x)) << RCM_SRIE_SACKERR_SHIFT)) & RCM_SRIE_SACKERR_MASK) 9818 /*! @} */ 9819 9820 9821 /*! 9822 * @} 9823 */ /* end of group RCM_Register_Masks */ 9824 9825 9826 /* RCM - Peripheral instance base addresses */ 9827 /** Peripheral RCM base address */ 9828 #define RCM_BASE (0x4007F000u) 9829 /** Peripheral RCM base pointer */ 9830 #define RCM ((RCM_Type *)RCM_BASE) 9831 /** Array initializer of RCM peripheral base addresses */ 9832 #define RCM_BASE_ADDRS { RCM_BASE } 9833 /** Array initializer of RCM peripheral base pointers */ 9834 #define RCM_BASE_PTRS { RCM } 9835 /** Interrupt vectors for the RCM peripheral type */ 9836 #define RCM_IRQS { SCG_RCM_IRQn } 9837 9838 /*! 9839 * @} 9840 */ /* end of group RCM_Peripheral_Access_Layer */ 9841 9842 9843 /* ---------------------------------------------------------------------------- 9844 -- ROM Peripheral Access Layer 9845 ---------------------------------------------------------------------------- */ 9846 9847 /*! 9848 * @addtogroup ROM_Peripheral_Access_Layer ROM Peripheral Access Layer 9849 * @{ 9850 */ 9851 9852 /** ROM - Register Layout Typedef */ 9853 typedef struct { 9854 __I uint32_t ENTRY[3]; /**< Entry, array offset: 0x0, array step: 0x4 */ 9855 __I uint32_t TABLEMARK; /**< End of Table Marker Register, offset: 0xC */ 9856 uint8_t RESERVED_0[4028]; 9857 __I uint32_t SYSACCESS; /**< System Access Register, offset: 0xFCC */ 9858 __I uint32_t PERIPHID4; /**< Peripheral ID Register, offset: 0xFD0 */ 9859 __I uint32_t PERIPHID5; /**< Peripheral ID Register, offset: 0xFD4 */ 9860 __I uint32_t PERIPHID6; /**< Peripheral ID Register, offset: 0xFD8 */ 9861 __I uint32_t PERIPHID7; /**< Peripheral ID Register, offset: 0xFDC */ 9862 __I uint32_t PERIPHID0; /**< Peripheral ID Register, offset: 0xFE0 */ 9863 __I uint32_t PERIPHID1; /**< Peripheral ID Register, offset: 0xFE4 */ 9864 __I uint32_t PERIPHID2; /**< Peripheral ID Register, offset: 0xFE8 */ 9865 __I uint32_t PERIPHID3; /**< Peripheral ID Register, offset: 0xFEC */ 9866 __I uint32_t COMPID[4]; /**< Component ID Register, array offset: 0xFF0, array step: 0x4 */ 9867 } ROM_Type; 9868 9869 /* ---------------------------------------------------------------------------- 9870 -- ROM Register Masks 9871 ---------------------------------------------------------------------------- */ 9872 9873 /*! 9874 * @addtogroup ROM_Register_Masks ROM Register Masks 9875 * @{ 9876 */ 9877 9878 /*! @name ENTRY - Entry */ 9879 /*! @{ */ 9880 #define ROM_ENTRY_ENTRY_MASK (0xFFFFFFFFU) 9881 #define ROM_ENTRY_ENTRY_SHIFT (0U) 9882 /*! ENTRY - ENTRY 9883 */ 9884 #define ROM_ENTRY_ENTRY(x) (((uint32_t)(((uint32_t)(x)) << ROM_ENTRY_ENTRY_SHIFT)) & ROM_ENTRY_ENTRY_MASK) 9885 /*! @} */ 9886 9887 /* The count of ROM_ENTRY */ 9888 #define ROM_ENTRY_COUNT (3U) 9889 9890 /*! @name TABLEMARK - End of Table Marker Register */ 9891 /*! @{ */ 9892 #define ROM_TABLEMARK_MARK_MASK (0xFFFFFFFFU) 9893 #define ROM_TABLEMARK_MARK_SHIFT (0U) 9894 /*! MARK - MARK 9895 */ 9896 #define ROM_TABLEMARK_MARK(x) (((uint32_t)(((uint32_t)(x)) << ROM_TABLEMARK_MARK_SHIFT)) & ROM_TABLEMARK_MARK_MASK) 9897 /*! @} */ 9898 9899 /*! @name SYSACCESS - System Access Register */ 9900 /*! @{ */ 9901 #define ROM_SYSACCESS_SYSACCESS_MASK (0xFFFFFFFFU) 9902 #define ROM_SYSACCESS_SYSACCESS_SHIFT (0U) 9903 /*! SYSACCESS - SYSACCESS 9904 */ 9905 #define ROM_SYSACCESS_SYSACCESS(x) (((uint32_t)(((uint32_t)(x)) << ROM_SYSACCESS_SYSACCESS_SHIFT)) & ROM_SYSACCESS_SYSACCESS_MASK) 9906 /*! @} */ 9907 9908 /*! @name PERIPHID4 - Peripheral ID Register */ 9909 /*! @{ */ 9910 #define ROM_PERIPHID4_PERIPHID_MASK (0xFFFFFFFFU) 9911 #define ROM_PERIPHID4_PERIPHID_SHIFT (0U) 9912 /*! PERIPHID - PERIPHID 9913 */ 9914 #define ROM_PERIPHID4_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << ROM_PERIPHID4_PERIPHID_SHIFT)) & ROM_PERIPHID4_PERIPHID_MASK) 9915 /*! @} */ 9916 9917 /*! @name PERIPHID5 - Peripheral ID Register */ 9918 /*! @{ */ 9919 #define ROM_PERIPHID5_PERIPHID_MASK (0xFFFFFFFFU) 9920 #define ROM_PERIPHID5_PERIPHID_SHIFT (0U) 9921 /*! PERIPHID - PERIPHID 9922 */ 9923 #define ROM_PERIPHID5_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << ROM_PERIPHID5_PERIPHID_SHIFT)) & ROM_PERIPHID5_PERIPHID_MASK) 9924 /*! @} */ 9925 9926 /*! @name PERIPHID6 - Peripheral ID Register */ 9927 /*! @{ */ 9928 #define ROM_PERIPHID6_PERIPHID_MASK (0xFFFFFFFFU) 9929 #define ROM_PERIPHID6_PERIPHID_SHIFT (0U) 9930 /*! PERIPHID - PERIPHID 9931 */ 9932 #define ROM_PERIPHID6_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << ROM_PERIPHID6_PERIPHID_SHIFT)) & ROM_PERIPHID6_PERIPHID_MASK) 9933 /*! @} */ 9934 9935 /*! @name PERIPHID7 - Peripheral ID Register */ 9936 /*! @{ */ 9937 #define ROM_PERIPHID7_PERIPHID_MASK (0xFFFFFFFFU) 9938 #define ROM_PERIPHID7_PERIPHID_SHIFT (0U) 9939 /*! PERIPHID - PERIPHID 9940 */ 9941 #define ROM_PERIPHID7_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << ROM_PERIPHID7_PERIPHID_SHIFT)) & ROM_PERIPHID7_PERIPHID_MASK) 9942 /*! @} */ 9943 9944 /*! @name PERIPHID0 - Peripheral ID Register */ 9945 /*! @{ */ 9946 #define ROM_PERIPHID0_PERIPHID_MASK (0xFFFFFFFFU) 9947 #define ROM_PERIPHID0_PERIPHID_SHIFT (0U) 9948 /*! PERIPHID - PERIPHID 9949 */ 9950 #define ROM_PERIPHID0_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << ROM_PERIPHID0_PERIPHID_SHIFT)) & ROM_PERIPHID0_PERIPHID_MASK) 9951 /*! @} */ 9952 9953 /*! @name PERIPHID1 - Peripheral ID Register */ 9954 /*! @{ */ 9955 #define ROM_PERIPHID1_PERIPHID_MASK (0xFFFFFFFFU) 9956 #define ROM_PERIPHID1_PERIPHID_SHIFT (0U) 9957 /*! PERIPHID - PERIPHID 9958 */ 9959 #define ROM_PERIPHID1_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << ROM_PERIPHID1_PERIPHID_SHIFT)) & ROM_PERIPHID1_PERIPHID_MASK) 9960 /*! @} */ 9961 9962 /*! @name PERIPHID2 - Peripheral ID Register */ 9963 /*! @{ */ 9964 #define ROM_PERIPHID2_PERIPHID_MASK (0xFFFFFFFFU) 9965 #define ROM_PERIPHID2_PERIPHID_SHIFT (0U) 9966 /*! PERIPHID - PERIPHID 9967 */ 9968 #define ROM_PERIPHID2_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << ROM_PERIPHID2_PERIPHID_SHIFT)) & ROM_PERIPHID2_PERIPHID_MASK) 9969 /*! @} */ 9970 9971 /*! @name PERIPHID3 - Peripheral ID Register */ 9972 /*! @{ */ 9973 #define ROM_PERIPHID3_PERIPHID_MASK (0xFFFFFFFFU) 9974 #define ROM_PERIPHID3_PERIPHID_SHIFT (0U) 9975 /*! PERIPHID - PERIPHID 9976 */ 9977 #define ROM_PERIPHID3_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << ROM_PERIPHID3_PERIPHID_SHIFT)) & ROM_PERIPHID3_PERIPHID_MASK) 9978 /*! @} */ 9979 9980 /*! @name COMPID - Component ID Register */ 9981 /*! @{ */ 9982 #define ROM_COMPID_COMPID_MASK (0xFFFFFFFFU) 9983 #define ROM_COMPID_COMPID_SHIFT (0U) 9984 /*! COMPID - Component ID 9985 */ 9986 #define ROM_COMPID_COMPID(x) (((uint32_t)(((uint32_t)(x)) << ROM_COMPID_COMPID_SHIFT)) & ROM_COMPID_COMPID_MASK) 9987 /*! @} */ 9988 9989 /* The count of ROM_COMPID */ 9990 #define ROM_COMPID_COUNT (4U) 9991 9992 9993 /*! 9994 * @} 9995 */ /* end of group ROM_Register_Masks */ 9996 9997 9998 /* ROM - Peripheral instance base addresses */ 9999 /** Peripheral ROM base address */ 10000 #define ROM_BASE (0xF0002000u) 10001 /** Peripheral ROM base pointer */ 10002 #define ROM ((ROM_Type *)ROM_BASE) 10003 /** Array initializer of ROM peripheral base addresses */ 10004 #define ROM_BASE_ADDRS { ROM_BASE } 10005 /** Array initializer of ROM peripheral base pointers */ 10006 #define ROM_BASE_PTRS { ROM } 10007 10008 /*! 10009 * @} 10010 */ /* end of group ROM_Peripheral_Access_Layer */ 10011 10012 10013 /* ---------------------------------------------------------------------------- 10014 -- RTC Peripheral Access Layer 10015 ---------------------------------------------------------------------------- */ 10016 10017 /*! 10018 * @addtogroup RTC_Peripheral_Access_Layer RTC Peripheral Access Layer 10019 * @{ 10020 */ 10021 10022 /** RTC - Register Layout Typedef */ 10023 typedef struct { 10024 __IO uint32_t TSR; /**< RTC Time Seconds Register, offset: 0x0 */ 10025 __IO uint32_t TPR; /**< RTC Time Prescaler Register, offset: 0x4 */ 10026 __IO uint32_t TAR; /**< RTC Time Alarm Register, offset: 0x8 */ 10027 __IO uint32_t TCR; /**< RTC Time Compensation Register, offset: 0xC */ 10028 __IO uint32_t CR; /**< RTC Control Register, offset: 0x10 */ 10029 __IO uint32_t SR; /**< RTC Status Register, offset: 0x14 */ 10030 __IO uint32_t LR; /**< RTC Lock Register, offset: 0x18 */ 10031 __IO uint32_t IER; /**< RTC Interrupt Enable Register, offset: 0x1C */ 10032 uint8_t RESERVED_0[2016]; 10033 __IO uint32_t WAR; /**< RTC Write Access Register, offset: 0x800 */ 10034 __IO uint32_t RAR; /**< RTC Read Access Register, offset: 0x804 */ 10035 } RTC_Type; 10036 10037 /* ---------------------------------------------------------------------------- 10038 -- RTC Register Masks 10039 ---------------------------------------------------------------------------- */ 10040 10041 /*! 10042 * @addtogroup RTC_Register_Masks RTC Register Masks 10043 * @{ 10044 */ 10045 10046 /*! @name TSR - RTC Time Seconds Register */ 10047 /*! @{ */ 10048 #define RTC_TSR_TSR_MASK (0xFFFFFFFFU) 10049 #define RTC_TSR_TSR_SHIFT (0U) 10050 /*! TSR - Time Seconds Register 10051 */ 10052 #define RTC_TSR_TSR(x) (((uint32_t)(((uint32_t)(x)) << RTC_TSR_TSR_SHIFT)) & RTC_TSR_TSR_MASK) 10053 /*! @} */ 10054 10055 /*! @name TPR - RTC Time Prescaler Register */ 10056 /*! @{ */ 10057 #define RTC_TPR_TPR_MASK (0xFFFFU) 10058 #define RTC_TPR_TPR_SHIFT (0U) 10059 /*! TPR - Time Prescaler Register 10060 */ 10061 #define RTC_TPR_TPR(x) (((uint32_t)(((uint32_t)(x)) << RTC_TPR_TPR_SHIFT)) & RTC_TPR_TPR_MASK) 10062 /*! @} */ 10063 10064 /*! @name TAR - RTC Time Alarm Register */ 10065 /*! @{ */ 10066 #define RTC_TAR_TAR_MASK (0xFFFFFFFFU) 10067 #define RTC_TAR_TAR_SHIFT (0U) 10068 /*! TAR - Time Alarm Register 10069 */ 10070 #define RTC_TAR_TAR(x) (((uint32_t)(((uint32_t)(x)) << RTC_TAR_TAR_SHIFT)) & RTC_TAR_TAR_MASK) 10071 /*! @} */ 10072 10073 /*! @name TCR - RTC Time Compensation Register */ 10074 /*! @{ */ 10075 #define RTC_TCR_TCR_MASK (0xFFU) 10076 #define RTC_TCR_TCR_SHIFT (0U) 10077 /*! TCR - Time Compensation Register 10078 * 0b10000000..Time Prescaler Register overflows every 32896 clock cycles. 10079 * 0b11111111..Time Prescaler Register overflows every 32769 clock cycles. 10080 * 0b00000000..Time Prescaler Register overflows every 32768 clock cycles. 10081 * 0b00000001..Time Prescaler Register overflows every 32767 clock cycles. 10082 * 0b01111111..Time Prescaler Register overflows every 32641 clock cycles. 10083 */ 10084 #define RTC_TCR_TCR(x) (((uint32_t)(((uint32_t)(x)) << RTC_TCR_TCR_SHIFT)) & RTC_TCR_TCR_MASK) 10085 #define RTC_TCR_CIR_MASK (0xFF00U) 10086 #define RTC_TCR_CIR_SHIFT (8U) 10087 /*! CIR - Compensation Interval Register 10088 */ 10089 #define RTC_TCR_CIR(x) (((uint32_t)(((uint32_t)(x)) << RTC_TCR_CIR_SHIFT)) & RTC_TCR_CIR_MASK) 10090 #define RTC_TCR_TCV_MASK (0xFF0000U) 10091 #define RTC_TCR_TCV_SHIFT (16U) 10092 /*! TCV - Time Compensation Value 10093 */ 10094 #define RTC_TCR_TCV(x) (((uint32_t)(((uint32_t)(x)) << RTC_TCR_TCV_SHIFT)) & RTC_TCR_TCV_MASK) 10095 #define RTC_TCR_CIC_MASK (0xFF000000U) 10096 #define RTC_TCR_CIC_SHIFT (24U) 10097 /*! CIC - Compensation Interval Counter 10098 */ 10099 #define RTC_TCR_CIC(x) (((uint32_t)(((uint32_t)(x)) << RTC_TCR_CIC_SHIFT)) & RTC_TCR_CIC_MASK) 10100 /*! @} */ 10101 10102 /*! @name CR - RTC Control Register */ 10103 /*! @{ */ 10104 #define RTC_CR_SWR_MASK (0x1U) 10105 #define RTC_CR_SWR_SHIFT (0U) 10106 /*! SWR - Software Reset 10107 * 0b0..No effect. 10108 * 0b1..Resets all RTC registers except for the SWR bit and the RTC_WAR and RTC_RAR registers . The SWR bit is 10109 * cleared by POR and by software explicitly clearing it. 10110 */ 10111 #define RTC_CR_SWR(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_SWR_SHIFT)) & RTC_CR_SWR_MASK) 10112 #define RTC_CR_WPE_MASK (0x2U) 10113 #define RTC_CR_WPE_SHIFT (1U) 10114 /*! WPE - Wakeup Pin Enable 10115 * 0b0..Wakeup pin is disabled. 10116 * 0b1..Wakeup pin is enabled and wakeup pin asserts if the RTC interrupt asserts or the wakeup pin is turned on. 10117 */ 10118 #define RTC_CR_WPE(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_WPE_SHIFT)) & RTC_CR_WPE_MASK) 10119 #define RTC_CR_SUP_MASK (0x4U) 10120 #define RTC_CR_SUP_SHIFT (2U) 10121 /*! SUP - Supervisor Access 10122 * 0b0..Non-supervisor mode write accesses are not supported and generate a bus error. 10123 * 0b1..Non-supervisor mode write accesses are supported. 10124 */ 10125 #define RTC_CR_SUP(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_SUP_SHIFT)) & RTC_CR_SUP_MASK) 10126 #define RTC_CR_UM_MASK (0x8U) 10127 #define RTC_CR_UM_SHIFT (3U) 10128 /*! UM - Update Mode 10129 * 0b0..Registers cannot be written when locked. 10130 * 0b1..Registers can be written when locked under limited conditions. 10131 */ 10132 #define RTC_CR_UM(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_UM_SHIFT)) & RTC_CR_UM_MASK) 10133 #define RTC_CR_WPS_MASK (0x10U) 10134 #define RTC_CR_WPS_SHIFT (4U) 10135 /*! WPS - Wakeup Pin Select 10136 * 0b0..Wakeup pin asserts (active low, open drain) if the RTC interrupt asserts or the wakeup pin is turned on. 10137 * 0b1..Wakeup pin instead outputs the RTC 32kHz clock, provided the wakeup pin is turned on and the 32kHz clock is output to other peripherals. 10138 */ 10139 #define RTC_CR_WPS(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_WPS_SHIFT)) & RTC_CR_WPS_MASK) 10140 #define RTC_CR_CPS_MASK (0x20U) 10141 #define RTC_CR_CPS_SHIFT (5U) 10142 /*! CPS - Clock Pin Select 10143 * 0b0..The prescaler output clock (as configured by TSIC) is output on RTC_CLKOUT. 10144 * 0b1..The RTC 32kHz clock is output on RTC_CLKOUT. 10145 */ 10146 #define RTC_CR_CPS(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_CPS_SHIFT)) & RTC_CR_CPS_MASK) 10147 #define RTC_CR_LPOS_MASK (0x80U) 10148 #define RTC_CR_LPOS_SHIFT (7U) 10149 /*! LPOS - LPO Select 10150 * 0b0..RTC prescaler increments using 32 kHz clock. 10151 * 0b1..RTC prescaler increments using LPO, bits [4:0] of the prescaler are bypassed. 10152 */ 10153 #define RTC_CR_LPOS(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_LPOS_SHIFT)) & RTC_CR_LPOS_MASK) 10154 #define RTC_CR_OSCE_MASK (0x100U) 10155 #define RTC_CR_OSCE_SHIFT (8U) 10156 /*! OSCE - Oscillator Enable 10157 * 0b0..32.768 kHz oscillator is disabled. 10158 * 0b1..32.768 kHz oscillator is enabled. After setting this bit, wait the oscillator startup time before 10159 * enabling the time counter to allow the 32.768 kHz clock time to stabilize. 10160 */ 10161 #define RTC_CR_OSCE(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_OSCE_SHIFT)) & RTC_CR_OSCE_MASK) 10162 #define RTC_CR_CLKO_MASK (0x200U) 10163 #define RTC_CR_CLKO_SHIFT (9U) 10164 /*! CLKO - Clock Output 10165 * 0b0..The 32 kHz clock is allowed to output on RTC_CLKOUT. 10166 * 0b1..The 32 kHz clock is not allowed to output on RTC_CLKOUT. 10167 */ 10168 #define RTC_CR_CLKO(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_CLKO_SHIFT)) & RTC_CR_CLKO_MASK) 10169 #define RTC_CR_CPE_MASK (0x3000000U) 10170 #define RTC_CR_CPE_SHIFT (24U) 10171 /*! CPE - Clock Pin Enable 10172 * 0b00..RTC_CLKOUT is disabled. 10173 * 0b01..RTC_CLKOUT is enabled. 10174 * 0b10..Reserved. 10175 * 0b11..Reserved. 10176 */ 10177 #define RTC_CR_CPE(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_CPE_SHIFT)) & RTC_CR_CPE_MASK) 10178 /*! @} */ 10179 10180 /*! @name SR - RTC Status Register */ 10181 /*! @{ */ 10182 #define RTC_SR_TIF_MASK (0x1U) 10183 #define RTC_SR_TIF_SHIFT (0U) 10184 /*! TIF - Time Invalid Flag 10185 * 0b0..Time is valid. 10186 * 0b1..Time is invalid and time counter is read as zero. 10187 */ 10188 #define RTC_SR_TIF(x) (((uint32_t)(((uint32_t)(x)) << RTC_SR_TIF_SHIFT)) & RTC_SR_TIF_MASK) 10189 #define RTC_SR_TOF_MASK (0x2U) 10190 #define RTC_SR_TOF_SHIFT (1U) 10191 /*! TOF - Time Overflow Flag 10192 * 0b0..Time overflow has not occurred. 10193 * 0b1..Time overflow has occurred and time counter is read as zero. 10194 */ 10195 #define RTC_SR_TOF(x) (((uint32_t)(((uint32_t)(x)) << RTC_SR_TOF_SHIFT)) & RTC_SR_TOF_MASK) 10196 #define RTC_SR_TAF_MASK (0x4U) 10197 #define RTC_SR_TAF_SHIFT (2U) 10198 /*! TAF - Time Alarm Flag 10199 * 0b0..Time alarm has not occurred. 10200 * 0b1..Time alarm has occurred. 10201 */ 10202 #define RTC_SR_TAF(x) (((uint32_t)(((uint32_t)(x)) << RTC_SR_TAF_SHIFT)) & RTC_SR_TAF_MASK) 10203 #define RTC_SR_TCE_MASK (0x10U) 10204 #define RTC_SR_TCE_SHIFT (4U) 10205 /*! TCE - Time Counter Enable 10206 * 0b0..Time counter is disabled. 10207 * 0b1..Time counter is enabled. 10208 */ 10209 #define RTC_SR_TCE(x) (((uint32_t)(((uint32_t)(x)) << RTC_SR_TCE_SHIFT)) & RTC_SR_TCE_MASK) 10210 /*! @} */ 10211 10212 /*! @name LR - RTC Lock Register */ 10213 /*! @{ */ 10214 #define RTC_LR_TCL_MASK (0x8U) 10215 #define RTC_LR_TCL_SHIFT (3U) 10216 /*! TCL - Time Compensation Lock 10217 * 0b0..Time Compensation Register is locked and writes are ignored. 10218 * 0b1..Time Compensation Register is not locked and writes complete as normal. 10219 */ 10220 #define RTC_LR_TCL(x) (((uint32_t)(((uint32_t)(x)) << RTC_LR_TCL_SHIFT)) & RTC_LR_TCL_MASK) 10221 #define RTC_LR_CRL_MASK (0x10U) 10222 #define RTC_LR_CRL_SHIFT (4U) 10223 /*! CRL - Control Register Lock 10224 * 0b0..Control Register is locked and writes are ignored. 10225 * 0b1..Control Register is not locked and writes complete as normal. 10226 */ 10227 #define RTC_LR_CRL(x) (((uint32_t)(((uint32_t)(x)) << RTC_LR_CRL_SHIFT)) & RTC_LR_CRL_MASK) 10228 #define RTC_LR_SRL_MASK (0x20U) 10229 #define RTC_LR_SRL_SHIFT (5U) 10230 /*! SRL - Status Register Lock 10231 * 0b0..Status Register is locked and writes are ignored. 10232 * 0b1..Status Register is not locked and writes complete as normal. 10233 */ 10234 #define RTC_LR_SRL(x) (((uint32_t)(((uint32_t)(x)) << RTC_LR_SRL_SHIFT)) & RTC_LR_SRL_MASK) 10235 #define RTC_LR_LRL_MASK (0x40U) 10236 #define RTC_LR_LRL_SHIFT (6U) 10237 /*! LRL - Lock Register Lock 10238 * 0b0..Lock Register is locked and writes are ignored. 10239 * 0b1..Lock Register is not locked and writes complete as normal. 10240 */ 10241 #define RTC_LR_LRL(x) (((uint32_t)(((uint32_t)(x)) << RTC_LR_LRL_SHIFT)) & RTC_LR_LRL_MASK) 10242 /*! @} */ 10243 10244 /*! @name IER - RTC Interrupt Enable Register */ 10245 /*! @{ */ 10246 #define RTC_IER_TIIE_MASK (0x1U) 10247 #define RTC_IER_TIIE_SHIFT (0U) 10248 /*! TIIE - Time Invalid Interrupt Enable 10249 * 0b0..Time invalid flag does not generate an interrupt. 10250 * 0b1..Time invalid flag does generate an interrupt. 10251 */ 10252 #define RTC_IER_TIIE(x) (((uint32_t)(((uint32_t)(x)) << RTC_IER_TIIE_SHIFT)) & RTC_IER_TIIE_MASK) 10253 #define RTC_IER_TOIE_MASK (0x2U) 10254 #define RTC_IER_TOIE_SHIFT (1U) 10255 /*! TOIE - Time Overflow Interrupt Enable 10256 * 0b0..Time overflow flag does not generate an interrupt. 10257 * 0b1..Time overflow flag does generate an interrupt. 10258 */ 10259 #define RTC_IER_TOIE(x) (((uint32_t)(((uint32_t)(x)) << RTC_IER_TOIE_SHIFT)) & RTC_IER_TOIE_MASK) 10260 #define RTC_IER_TAIE_MASK (0x4U) 10261 #define RTC_IER_TAIE_SHIFT (2U) 10262 /*! TAIE - Time Alarm Interrupt Enable 10263 * 0b0..Time alarm flag does not generate an interrupt. 10264 * 0b1..Time alarm flag does generate an interrupt. 10265 */ 10266 #define RTC_IER_TAIE(x) (((uint32_t)(((uint32_t)(x)) << RTC_IER_TAIE_SHIFT)) & RTC_IER_TAIE_MASK) 10267 #define RTC_IER_TSIE_MASK (0x10U) 10268 #define RTC_IER_TSIE_SHIFT (4U) 10269 /*! TSIE - Time Seconds Interrupt Enable 10270 * 0b0..Seconds interrupt is disabled. 10271 * 0b1..Seconds interrupt is enabled. 10272 */ 10273 #define RTC_IER_TSIE(x) (((uint32_t)(((uint32_t)(x)) << RTC_IER_TSIE_SHIFT)) & RTC_IER_TSIE_MASK) 10274 #define RTC_IER_WPON_MASK (0x80U) 10275 #define RTC_IER_WPON_SHIFT (7U) 10276 /*! WPON - Wakeup Pin On 10277 * 0b0..No effect. 10278 * 0b1..If the wakeup pin is enabled, then the wakeup pin will assert. 10279 */ 10280 #define RTC_IER_WPON(x) (((uint32_t)(((uint32_t)(x)) << RTC_IER_WPON_SHIFT)) & RTC_IER_WPON_MASK) 10281 #define RTC_IER_TSIC_MASK (0x70000U) 10282 #define RTC_IER_TSIC_SHIFT (16U) 10283 /*! TSIC - Timer Seconds Interrupt Configuration 10284 * 0b000..1 Hz. 10285 * 0b001..2 Hz. 10286 * 0b010..4 Hz. 10287 * 0b011..8 Hz. 10288 * 0b100..16 Hz. 10289 * 0b101..32 Hz. 10290 * 0b110..64 Hz. 10291 * 0b111..128 Hz. 10292 */ 10293 #define RTC_IER_TSIC(x) (((uint32_t)(((uint32_t)(x)) << RTC_IER_TSIC_SHIFT)) & RTC_IER_TSIC_MASK) 10294 /*! @} */ 10295 10296 /*! @name WAR - RTC Write Access Register */ 10297 /*! @{ */ 10298 #define RTC_WAR_TSRW_MASK (0x1U) 10299 #define RTC_WAR_TSRW_SHIFT (0U) 10300 /*! TSRW - Time Seconds Register Write 10301 * 0b0..Writes to the Time Seconds Register are ignored. 10302 * 0b1..Writes to the Time Seconds Register complete as normal. 10303 */ 10304 #define RTC_WAR_TSRW(x) (((uint32_t)(((uint32_t)(x)) << RTC_WAR_TSRW_SHIFT)) & RTC_WAR_TSRW_MASK) 10305 #define RTC_WAR_TPRW_MASK (0x2U) 10306 #define RTC_WAR_TPRW_SHIFT (1U) 10307 /*! TPRW - Time Prescaler Register Write 10308 * 0b0..Writes to the Time Prescaler Register are ignored. 10309 * 0b1..Writes to the Time Prescaler Register complete as normal. 10310 */ 10311 #define RTC_WAR_TPRW(x) (((uint32_t)(((uint32_t)(x)) << RTC_WAR_TPRW_SHIFT)) & RTC_WAR_TPRW_MASK) 10312 #define RTC_WAR_TARW_MASK (0x4U) 10313 #define RTC_WAR_TARW_SHIFT (2U) 10314 /*! TARW - Time Alarm Register Write 10315 * 0b0..Writes to the Time Alarm Register are ignored. 10316 * 0b1..Writes to the Time Alarm Register complete as normal. 10317 */ 10318 #define RTC_WAR_TARW(x) (((uint32_t)(((uint32_t)(x)) << RTC_WAR_TARW_SHIFT)) & RTC_WAR_TARW_MASK) 10319 #define RTC_WAR_TCRW_MASK (0x8U) 10320 #define RTC_WAR_TCRW_SHIFT (3U) 10321 /*! TCRW - Time Compensation Register Write 10322 * 0b0..Writes to the Time Compensation Register are ignored. 10323 * 0b1..Writes to the Time Compensation Register complete as normal. 10324 */ 10325 #define RTC_WAR_TCRW(x) (((uint32_t)(((uint32_t)(x)) << RTC_WAR_TCRW_SHIFT)) & RTC_WAR_TCRW_MASK) 10326 #define RTC_WAR_CRW_MASK (0x10U) 10327 #define RTC_WAR_CRW_SHIFT (4U) 10328 /*! CRW - Control Register Write 10329 * 0b0..Writes to the Control Register are ignored. 10330 * 0b1..Writes to the Control Register complete as normal. 10331 */ 10332 #define RTC_WAR_CRW(x) (((uint32_t)(((uint32_t)(x)) << RTC_WAR_CRW_SHIFT)) & RTC_WAR_CRW_MASK) 10333 #define RTC_WAR_SRW_MASK (0x20U) 10334 #define RTC_WAR_SRW_SHIFT (5U) 10335 /*! SRW - Status Register Write 10336 * 0b0..Writes to the Status Register are ignored. 10337 * 0b1..Writes to the Status Register complete as normal. 10338 */ 10339 #define RTC_WAR_SRW(x) (((uint32_t)(((uint32_t)(x)) << RTC_WAR_SRW_SHIFT)) & RTC_WAR_SRW_MASK) 10340 #define RTC_WAR_LRW_MASK (0x40U) 10341 #define RTC_WAR_LRW_SHIFT (6U) 10342 /*! LRW - Lock Register Write 10343 * 0b0..Writes to the Lock Register are ignored. 10344 * 0b1..Writes to the Lock Register complete as normal. 10345 */ 10346 #define RTC_WAR_LRW(x) (((uint32_t)(((uint32_t)(x)) << RTC_WAR_LRW_SHIFT)) & RTC_WAR_LRW_MASK) 10347 #define RTC_WAR_IERW_MASK (0x80U) 10348 #define RTC_WAR_IERW_SHIFT (7U) 10349 /*! IERW - Interrupt Enable Register Write 10350 * 0b0..Writes to the Interupt Enable Register are ignored. 10351 * 0b1..Writes to the Interrupt Enable Register complete as normal. 10352 */ 10353 #define RTC_WAR_IERW(x) (((uint32_t)(((uint32_t)(x)) << RTC_WAR_IERW_SHIFT)) & RTC_WAR_IERW_MASK) 10354 /*! @} */ 10355 10356 /*! @name RAR - RTC Read Access Register */ 10357 /*! @{ */ 10358 #define RTC_RAR_TSRR_MASK (0x1U) 10359 #define RTC_RAR_TSRR_SHIFT (0U) 10360 /*! TSRR - Time Seconds Register Read 10361 * 0b0..Reads to the Time Seconds Register are ignored. 10362 * 0b1..Reads to the Time Seconds Register complete as normal. 10363 */ 10364 #define RTC_RAR_TSRR(x) (((uint32_t)(((uint32_t)(x)) << RTC_RAR_TSRR_SHIFT)) & RTC_RAR_TSRR_MASK) 10365 #define RTC_RAR_TPRR_MASK (0x2U) 10366 #define RTC_RAR_TPRR_SHIFT (1U) 10367 /*! TPRR - Time Prescaler Register Read 10368 * 0b0..Reads to the Time Pprescaler Register are ignored. 10369 * 0b1..Reads to the Time Prescaler Register complete as normal. 10370 */ 10371 #define RTC_RAR_TPRR(x) (((uint32_t)(((uint32_t)(x)) << RTC_RAR_TPRR_SHIFT)) & RTC_RAR_TPRR_MASK) 10372 #define RTC_RAR_TARR_MASK (0x4U) 10373 #define RTC_RAR_TARR_SHIFT (2U) 10374 /*! TARR - Time Alarm Register Read 10375 * 0b0..Reads to the Time Alarm Register are ignored. 10376 * 0b1..Reads to the Time Alarm Register complete as normal. 10377 */ 10378 #define RTC_RAR_TARR(x) (((uint32_t)(((uint32_t)(x)) << RTC_RAR_TARR_SHIFT)) & RTC_RAR_TARR_MASK) 10379 #define RTC_RAR_TCRR_MASK (0x8U) 10380 #define RTC_RAR_TCRR_SHIFT (3U) 10381 /*! TCRR - Time Compensation Register Read 10382 * 0b0..Reads to the Time Compensation Register are ignored. 10383 * 0b1..Reads to the Time Compensation Register complete as normal. 10384 */ 10385 #define RTC_RAR_TCRR(x) (((uint32_t)(((uint32_t)(x)) << RTC_RAR_TCRR_SHIFT)) & RTC_RAR_TCRR_MASK) 10386 #define RTC_RAR_CRR_MASK (0x10U) 10387 #define RTC_RAR_CRR_SHIFT (4U) 10388 /*! CRR - Control Register Read 10389 * 0b0..Reads to the Control Register are ignored. 10390 * 0b1..Reads to the Control Register complete as normal. 10391 */ 10392 #define RTC_RAR_CRR(x) (((uint32_t)(((uint32_t)(x)) << RTC_RAR_CRR_SHIFT)) & RTC_RAR_CRR_MASK) 10393 #define RTC_RAR_SRR_MASK (0x20U) 10394 #define RTC_RAR_SRR_SHIFT (5U) 10395 /*! SRR - Status Register Read 10396 * 0b0..Reads to the Status Register are ignored. 10397 * 0b1..Reads to the Status Register complete as normal. 10398 */ 10399 #define RTC_RAR_SRR(x) (((uint32_t)(((uint32_t)(x)) << RTC_RAR_SRR_SHIFT)) & RTC_RAR_SRR_MASK) 10400 #define RTC_RAR_LRR_MASK (0x40U) 10401 #define RTC_RAR_LRR_SHIFT (6U) 10402 /*! LRR - Lock Register Read 10403 * 0b0..Reads to the Lock Register are ignored. 10404 * 0b1..Reads to the Lock Register complete as normal. 10405 */ 10406 #define RTC_RAR_LRR(x) (((uint32_t)(((uint32_t)(x)) << RTC_RAR_LRR_SHIFT)) & RTC_RAR_LRR_MASK) 10407 #define RTC_RAR_IERR_MASK (0x80U) 10408 #define RTC_RAR_IERR_SHIFT (7U) 10409 /*! IERR - Interrupt Enable Register Read 10410 * 0b0..Reads to the Interrupt Enable Register are ignored. 10411 * 0b1..Reads to the Interrupt Enable Register complete as normal. 10412 */ 10413 #define RTC_RAR_IERR(x) (((uint32_t)(((uint32_t)(x)) << RTC_RAR_IERR_SHIFT)) & RTC_RAR_IERR_MASK) 10414 /*! @} */ 10415 10416 10417 /*! 10418 * @} 10419 */ /* end of group RTC_Register_Masks */ 10420 10421 10422 /* RTC - Peripheral instance base addresses */ 10423 /** Peripheral RTC base address */ 10424 #define RTC_BASE (0x4003D000u) 10425 /** Peripheral RTC base pointer */ 10426 #define RTC ((RTC_Type *)RTC_BASE) 10427 /** Array initializer of RTC peripheral base addresses */ 10428 #define RTC_BASE_ADDRS { RTC_BASE } 10429 /** Array initializer of RTC peripheral base pointers */ 10430 #define RTC_BASE_PTRS { RTC } 10431 /** Interrupt vectors for the RTC peripheral type */ 10432 #define RTC_IRQS { RTC_IRQn } 10433 #define RTC_SECONDS_IRQS { RTC_IRQn } 10434 10435 /*! 10436 * @} 10437 */ /* end of group RTC_Peripheral_Access_Layer */ 10438 10439 10440 /* ---------------------------------------------------------------------------- 10441 -- SCG Peripheral Access Layer 10442 ---------------------------------------------------------------------------- */ 10443 10444 /*! 10445 * @addtogroup SCG_Peripheral_Access_Layer SCG Peripheral Access Layer 10446 * @{ 10447 */ 10448 10449 /** SCG - Register Layout Typedef */ 10450 typedef struct { 10451 __I uint32_t VERID; /**< Version ID Register, offset: 0x0 */ 10452 __I uint32_t PARAM; /**< Parameter Register, offset: 0x4 */ 10453 uint8_t RESERVED_0[8]; 10454 __I uint32_t CSR; /**< Clock Status Register, offset: 0x10 */ 10455 __IO uint32_t RCCR; /**< Run Clock Control Register, offset: 0x14 */ 10456 __IO uint32_t VCCR; /**< VLPR Clock Control Register, offset: 0x18 */ 10457 uint8_t RESERVED_1[4]; 10458 __IO uint32_t CLKOUTCNFG; /**< SCG CLKOUT Configuration Register, offset: 0x20 */ 10459 uint8_t RESERVED_2[220]; 10460 __IO uint32_t SOSCCSR; /**< System OSC Control Status Register, offset: 0x100 */ 10461 __IO uint32_t SOSCDIV; /**< System OSC Divide Register, offset: 0x104 */ 10462 __IO uint32_t SOSCCFG; /**< System Oscillator Configuration Register, offset: 0x108 */ 10463 uint8_t RESERVED_3[244]; 10464 __IO uint32_t SIRCCSR; /**< Slow IRC Control Status Register, offset: 0x200 */ 10465 __IO uint32_t SIRCDIV; /**< Slow IRC Divide Register, offset: 0x204 */ 10466 __IO uint32_t SIRCCFG; /**< Slow IRC Configuration Register, offset: 0x208 */ 10467 uint8_t RESERVED_4[244]; 10468 __IO uint32_t FIRCCSR; /**< Fast IRC Control Status Register, offset: 0x300 */ 10469 __IO uint32_t FIRCDIV; /**< Fast IRC Divide Register, offset: 0x304 */ 10470 __IO uint32_t FIRCCFG; /**< Fast IRC Configuration Register, offset: 0x308 */ 10471 __IO uint32_t FIRCTCFG; /**< Fast IRC Trim Configuration Register, offset: 0x30C */ 10472 uint8_t RESERVED_5[8]; 10473 __IO uint32_t FIRCSTAT; /**< Fast IRC Status Register, offset: 0x318 */ 10474 uint8_t RESERVED_6[484]; 10475 __IO uint32_t LPFLLCSR; /**< Low Power FLL Control Status Register, offset: 0x500 */ 10476 __IO uint32_t LPFLLDIV; /**< Low Power FLL Divide Register, offset: 0x504 */ 10477 __IO uint32_t LPFLLCFG; /**< Low Power FLL Configuration Register, offset: 0x508 */ 10478 __IO uint32_t LPFLLTCFG; /**< Low Power FLL Trim Configuration Register, offset: 0x50C */ 10479 uint8_t RESERVED_7[4]; 10480 __IO uint32_t LPFLLSTAT; /**< Low Power FLL Status Register, offset: 0x514 */ 10481 } SCG_Type; 10482 10483 /* ---------------------------------------------------------------------------- 10484 -- SCG Register Masks 10485 ---------------------------------------------------------------------------- */ 10486 10487 /*! 10488 * @addtogroup SCG_Register_Masks SCG Register Masks 10489 * @{ 10490 */ 10491 10492 /*! @name VERID - Version ID Register */ 10493 /*! @{ */ 10494 #define SCG_VERID_VERSION_MASK (0xFFFFFFFFU) 10495 #define SCG_VERID_VERSION_SHIFT (0U) 10496 /*! VERSION - SCG Version Number 10497 */ 10498 #define SCG_VERID_VERSION(x) (((uint32_t)(((uint32_t)(x)) << SCG_VERID_VERSION_SHIFT)) & SCG_VERID_VERSION_MASK) 10499 /*! @} */ 10500 10501 /*! @name PARAM - Parameter Register */ 10502 /*! @{ */ 10503 #define SCG_PARAM_CLKPRES_MASK (0xFFU) 10504 #define SCG_PARAM_CLKPRES_SHIFT (0U) 10505 /*! CLKPRES - Clock Present 10506 */ 10507 #define SCG_PARAM_CLKPRES(x) (((uint32_t)(((uint32_t)(x)) << SCG_PARAM_CLKPRES_SHIFT)) & SCG_PARAM_CLKPRES_MASK) 10508 #define SCG_PARAM_DIVPRES_MASK (0xF8000000U) 10509 #define SCG_PARAM_DIVPRES_SHIFT (27U) 10510 /*! DIVPRES - Divider Present 10511 */ 10512 #define SCG_PARAM_DIVPRES(x) (((uint32_t)(((uint32_t)(x)) << SCG_PARAM_DIVPRES_SHIFT)) & SCG_PARAM_DIVPRES_MASK) 10513 /*! @} */ 10514 10515 /*! @name CSR - Clock Status Register */ 10516 /*! @{ */ 10517 #define SCG_CSR_DIVSLOW_MASK (0xFU) 10518 #define SCG_CSR_DIVSLOW_SHIFT (0U) 10519 /*! DIVSLOW - Slow Clock Divide Ratio 10520 * 0b0000..Reserved 10521 * 0b0001..Divide-by-2 10522 * 0b0010..Divide-by-3 10523 * 0b0011..Divide-by-4 10524 * 0b0100..Divide-by-5 10525 * 0b0101..Divide-by-6 10526 * 0b0110..Divide-by-7 10527 * 0b0111..Divide-by-8 10528 * 0b1000..Reserved 10529 * 0b1001..Reserved 10530 * 0b1010..Reserved 10531 * 0b1011..Reserved 10532 * 0b1100..Reserved 10533 * 0b1101..Reserved 10534 * 0b1110..Reserved 10535 * 0b1111..Reserved 10536 */ 10537 #define SCG_CSR_DIVSLOW(x) (((uint32_t)(((uint32_t)(x)) << SCG_CSR_DIVSLOW_SHIFT)) & SCG_CSR_DIVSLOW_MASK) 10538 #define SCG_CSR_DIVCORE_MASK (0xF0000U) 10539 #define SCG_CSR_DIVCORE_SHIFT (16U) 10540 /*! DIVCORE - Core Clock Divide Ratio 10541 * 0b0000..Divide-by-1 10542 * 0b0001..Divide-by-2 10543 * 0b0010..Divide-by-3 10544 * 0b0011..Divide-by-4 10545 * 0b0100..Divide-by-5 10546 * 0b0101..Divide-by-6 10547 * 0b0110..Divide-by-7 10548 * 0b0111..Divide-by-8 10549 * 0b1000..Divide-by-9 10550 * 0b1001..Divide-by-10 10551 * 0b1010..Divide-by-11 10552 * 0b1011..Divide-by-12 10553 * 0b1100..Divide-by-13 10554 * 0b1101..Divide-by-14 10555 * 0b1110..Divide-by-15 10556 * 0b1111..Divide-by-16 10557 */ 10558 #define SCG_CSR_DIVCORE(x) (((uint32_t)(((uint32_t)(x)) << SCG_CSR_DIVCORE_SHIFT)) & SCG_CSR_DIVCORE_MASK) 10559 #define SCG_CSR_SCS_MASK (0xF000000U) 10560 #define SCG_CSR_SCS_SHIFT (24U) 10561 /*! SCS - System Clock Source 10562 * 0b0000..Reserved 10563 * 0b0001..System OSC (SOSC_CLK) 10564 * 0b0010..Slow IRC (SIRC_CLK) 10565 * 0b0011..Fast IRC (FIRC_CLK) 10566 * 0b0100..Reserved 10567 * 0b0101..Low Power FLL (LPFLL_CLK) 10568 * 0b0110..Reserved 10569 * 0b0111..Reserved 10570 */ 10571 #define SCG_CSR_SCS(x) (((uint32_t)(((uint32_t)(x)) << SCG_CSR_SCS_SHIFT)) & SCG_CSR_SCS_MASK) 10572 /*! @} */ 10573 10574 /*! @name RCCR - Run Clock Control Register */ 10575 /*! @{ */ 10576 #define SCG_RCCR_DIVSLOW_MASK (0xFU) 10577 #define SCG_RCCR_DIVSLOW_SHIFT (0U) 10578 /*! DIVSLOW - Slow Clock Divide Ratio 10579 * 0b0000..Reserved 10580 * 0b0001..Divide-by-2 10581 * 0b0010..Divide-by-3 10582 * 0b0011..Divide-by-4 10583 * 0b0100..Divide-by-5 10584 * 0b0101..Divide-by-6 10585 * 0b0110..Divide-by-7 10586 * 0b0111..Divide-by-8 10587 * 0b1000..Reserved 10588 * 0b1001..Reserved 10589 * 0b1010..Reserved 10590 * 0b1011..Reserved 10591 * 0b1100..Reserved 10592 * 0b1101..Reserved 10593 * 0b1110..Reserved 10594 * 0b1111..Reserved 10595 */ 10596 #define SCG_RCCR_DIVSLOW(x) (((uint32_t)(((uint32_t)(x)) << SCG_RCCR_DIVSLOW_SHIFT)) & SCG_RCCR_DIVSLOW_MASK) 10597 #define SCG_RCCR_DIVCORE_MASK (0xF0000U) 10598 #define SCG_RCCR_DIVCORE_SHIFT (16U) 10599 /*! DIVCORE - Core Clock Divide Ratio 10600 * 0b0000..Divide-by-1 10601 * 0b0001..Divide-by-2 10602 * 0b0010..Divide-by-3 10603 * 0b0011..Divide-by-4 10604 * 0b0100..Divide-by-5 10605 * 0b0101..Divide-by-6 10606 * 0b0110..Divide-by-7 10607 * 0b0111..Divide-by-8 10608 * 0b1000..Divide-by-9 10609 * 0b1001..Divide-by-10 10610 * 0b1010..Divide-by-11 10611 * 0b1011..Divide-by-12 10612 * 0b1100..Divide-by-13 10613 * 0b1101..Divide-by-14 10614 * 0b1110..Divide-by-15 10615 * 0b1111..Divide-by-16 10616 */ 10617 #define SCG_RCCR_DIVCORE(x) (((uint32_t)(((uint32_t)(x)) << SCG_RCCR_DIVCORE_SHIFT)) & SCG_RCCR_DIVCORE_MASK) 10618 #define SCG_RCCR_SCS_MASK (0xF000000U) 10619 #define SCG_RCCR_SCS_SHIFT (24U) 10620 /*! SCS - System Clock Source 10621 * 0b0000..Reserved 10622 * 0b0001..System OSC (SOSC_CLK) 10623 * 0b0010..Slow IRC (SIRC_CLK) 10624 * 0b0011..Fast IRC (FIRC_CLK) 10625 * 0b0100..Reserved 10626 * 0b0101..Low Power FLL (LPFLL_CLK) 10627 * 0b0110..Reserved 10628 * 0b0111..Reserved 10629 */ 10630 #define SCG_RCCR_SCS(x) (((uint32_t)(((uint32_t)(x)) << SCG_RCCR_SCS_SHIFT)) & SCG_RCCR_SCS_MASK) 10631 /*! @} */ 10632 10633 /*! @name VCCR - VLPR Clock Control Register */ 10634 /*! @{ */ 10635 #define SCG_VCCR_DIVSLOW_MASK (0xFU) 10636 #define SCG_VCCR_DIVSLOW_SHIFT (0U) 10637 /*! DIVSLOW - Slow Clock Divide Ratio 10638 * 0b0000..Reserved 10639 * 0b0001..Divide-by-2 10640 * 0b0010..Divide-by-3 10641 * 0b0011..Divide-by-4 10642 * 0b0100..Divide-by-5 10643 * 0b0101..Divide-by-6 10644 * 0b0110..Divide-by-7 10645 * 0b0111..Divide-by-8 10646 * 0b1000..Reserved 10647 * 0b1001..Reserved 10648 * 0b1010..Reserved 10649 * 0b1011..Reserved 10650 * 0b1100..Reserved 10651 * 0b1101..Reserved 10652 * 0b1110..Reserved 10653 * 0b1111..Reserved 10654 */ 10655 #define SCG_VCCR_DIVSLOW(x) (((uint32_t)(((uint32_t)(x)) << SCG_VCCR_DIVSLOW_SHIFT)) & SCG_VCCR_DIVSLOW_MASK) 10656 #define SCG_VCCR_DIVCORE_MASK (0xF0000U) 10657 #define SCG_VCCR_DIVCORE_SHIFT (16U) 10658 /*! DIVCORE - Core Clock Divide Ratio 10659 * 0b0000..Divide-by-1 10660 * 0b0001..Divide-by-2 10661 * 0b0010..Divide-by-3 10662 * 0b0011..Divide-by-4 10663 * 0b0100..Divide-by-5 10664 * 0b0101..Divide-by-6 10665 * 0b0110..Divide-by-7 10666 * 0b0111..Divide-by-8 10667 * 0b1000..Divide-by-9 10668 * 0b1001..Divide-by-10 10669 * 0b1010..Divide-by-11 10670 * 0b1011..Divide-by-12 10671 * 0b1100..Divide-by-13 10672 * 0b1101..Divide-by-14 10673 * 0b1110..Divide-by-15 10674 * 0b1111..Divide-by-16 10675 */ 10676 #define SCG_VCCR_DIVCORE(x) (((uint32_t)(((uint32_t)(x)) << SCG_VCCR_DIVCORE_SHIFT)) & SCG_VCCR_DIVCORE_MASK) 10677 #define SCG_VCCR_SCS_MASK (0xF000000U) 10678 #define SCG_VCCR_SCS_SHIFT (24U) 10679 /*! SCS - System Clock Source 10680 * 0b0000..Reserved 10681 * 0b0001..System OSC (SOSC_CLK) 10682 * 0b0010..Slow IRC (SIRC_CLK) 10683 * 0b0011..Reserved 10684 * 0b0100..Reserved 10685 * 0b0101..Reserved 10686 * 0b0110..Reserved 10687 * 0b0111..Reserved 10688 */ 10689 #define SCG_VCCR_SCS(x) (((uint32_t)(((uint32_t)(x)) << SCG_VCCR_SCS_SHIFT)) & SCG_VCCR_SCS_MASK) 10690 /*! @} */ 10691 10692 /*! @name CLKOUTCNFG - SCG CLKOUT Configuration Register */ 10693 /*! @{ */ 10694 #define SCG_CLKOUTCNFG_CLKOUTSEL_MASK (0xF000000U) 10695 #define SCG_CLKOUTCNFG_CLKOUTSEL_SHIFT (24U) 10696 /*! CLKOUTSEL - SCG Clkout Select 10697 * 0b0000..SCG SLOW Clock 10698 * 0b0001..System OSC (SOSC_CLK) 10699 * 0b0010..Slow IRC (SIRC_CLK) 10700 * 0b0011..Fast IRC (FIRC_CLK) 10701 * 0b0100..Reserved 10702 * 0b0101..Low Power FLL (LPFLL_CLK) 10703 * 0b0110..Reserved 10704 * 0b0111..Reserved 10705 * 0b1111..Reserved 10706 */ 10707 #define SCG_CLKOUTCNFG_CLKOUTSEL(x) (((uint32_t)(((uint32_t)(x)) << SCG_CLKOUTCNFG_CLKOUTSEL_SHIFT)) & SCG_CLKOUTCNFG_CLKOUTSEL_MASK) 10708 /*! @} */ 10709 10710 /*! @name SOSCCSR - System OSC Control Status Register */ 10711 /*! @{ */ 10712 #define SCG_SOSCCSR_SOSCEN_MASK (0x1U) 10713 #define SCG_SOSCCSR_SOSCEN_SHIFT (0U) 10714 /*! SOSCEN - System OSC Enable 10715 * 0b0..System OSC is disabled 10716 * 0b1..System OSC is enabled 10717 */ 10718 #define SCG_SOSCCSR_SOSCEN(x) (((uint32_t)(((uint32_t)(x)) << SCG_SOSCCSR_SOSCEN_SHIFT)) & SCG_SOSCCSR_SOSCEN_MASK) 10719 #define SCG_SOSCCSR_SOSCSTEN_MASK (0x2U) 10720 #define SCG_SOSCCSR_SOSCSTEN_SHIFT (1U) 10721 /*! SOSCSTEN - System OSC Stop Enable 10722 * 0b0..System OSC is disabled in Stop modes 10723 * 0b1..System OSC is enabled in Stop modes if SOSCEN=1. 10724 */ 10725 #define SCG_SOSCCSR_SOSCSTEN(x) (((uint32_t)(((uint32_t)(x)) << SCG_SOSCCSR_SOSCSTEN_SHIFT)) & SCG_SOSCCSR_SOSCSTEN_MASK) 10726 #define SCG_SOSCCSR_SOSCLPEN_MASK (0x4U) 10727 #define SCG_SOSCCSR_SOSCLPEN_SHIFT (2U) 10728 /*! SOSCLPEN - System OSC Low Power Enable 10729 * 0b0..System OSC is disabled in VLP modes 10730 * 0b1..System OSC is enabled in VLP modes 10731 */ 10732 #define SCG_SOSCCSR_SOSCLPEN(x) (((uint32_t)(((uint32_t)(x)) << SCG_SOSCCSR_SOSCLPEN_SHIFT)) & SCG_SOSCCSR_SOSCLPEN_MASK) 10733 #define SCG_SOSCCSR_SOSCERCLKEN_MASK (0x8U) 10734 #define SCG_SOSCCSR_SOSCERCLKEN_SHIFT (3U) 10735 /*! SOSCERCLKEN - System OSC 3V ERCLK Enable 10736 * 0b0..System OSC 3V ERCLK output clock is disabled. 10737 * 0b1..System OSC 3V ERCLK output clock is enabled when SYSOSC is enabled. 10738 */ 10739 #define SCG_SOSCCSR_SOSCERCLKEN(x) (((uint32_t)(((uint32_t)(x)) << SCG_SOSCCSR_SOSCERCLKEN_SHIFT)) & SCG_SOSCCSR_SOSCERCLKEN_MASK) 10740 #define SCG_SOSCCSR_SOSCCM_MASK (0x10000U) 10741 #define SCG_SOSCCSR_SOSCCM_SHIFT (16U) 10742 /*! SOSCCM - System OSC Clock Monitor 10743 * 0b0..System OSC Clock Monitor is disabled 10744 * 0b1..System OSC Clock Monitor is enabled 10745 */ 10746 #define SCG_SOSCCSR_SOSCCM(x) (((uint32_t)(((uint32_t)(x)) << SCG_SOSCCSR_SOSCCM_SHIFT)) & SCG_SOSCCSR_SOSCCM_MASK) 10747 #define SCG_SOSCCSR_SOSCCMRE_MASK (0x20000U) 10748 #define SCG_SOSCCSR_SOSCCMRE_SHIFT (17U) 10749 /*! SOSCCMRE - System OSC Clock Monitor Reset Enable 10750 * 0b0..Clock Monitor generates interrupt when error detected 10751 * 0b1..Clock Monitor generates reset when error detected 10752 */ 10753 #define SCG_SOSCCSR_SOSCCMRE(x) (((uint32_t)(((uint32_t)(x)) << SCG_SOSCCSR_SOSCCMRE_SHIFT)) & SCG_SOSCCSR_SOSCCMRE_MASK) 10754 #define SCG_SOSCCSR_LK_MASK (0x800000U) 10755 #define SCG_SOSCCSR_LK_SHIFT (23U) 10756 /*! LK - Lock Register 10757 * 0b0..This Control Status Register can be written. 10758 * 0b1..This Control Status Register cannot be written. 10759 */ 10760 #define SCG_SOSCCSR_LK(x) (((uint32_t)(((uint32_t)(x)) << SCG_SOSCCSR_LK_SHIFT)) & SCG_SOSCCSR_LK_MASK) 10761 #define SCG_SOSCCSR_SOSCVLD_MASK (0x1000000U) 10762 #define SCG_SOSCCSR_SOSCVLD_SHIFT (24U) 10763 /*! SOSCVLD - System OSC Valid 10764 * 0b0..System OSC is not enabled or clock is not valid 10765 * 0b1..System OSC is enabled and output clock is valid 10766 */ 10767 #define SCG_SOSCCSR_SOSCVLD(x) (((uint32_t)(((uint32_t)(x)) << SCG_SOSCCSR_SOSCVLD_SHIFT)) & SCG_SOSCCSR_SOSCVLD_MASK) 10768 #define SCG_SOSCCSR_SOSCSEL_MASK (0x2000000U) 10769 #define SCG_SOSCCSR_SOSCSEL_SHIFT (25U) 10770 /*! SOSCSEL - System OSC Selected 10771 * 0b0..System OSC is not the system clock source 10772 * 0b1..System OSC is the system clock source 10773 */ 10774 #define SCG_SOSCCSR_SOSCSEL(x) (((uint32_t)(((uint32_t)(x)) << SCG_SOSCCSR_SOSCSEL_SHIFT)) & SCG_SOSCCSR_SOSCSEL_MASK) 10775 #define SCG_SOSCCSR_SOSCERR_MASK (0x4000000U) 10776 #define SCG_SOSCCSR_SOSCERR_SHIFT (26U) 10777 /*! SOSCERR - System OSC Clock Error 10778 * 0b0..System OSC Clock Monitor is disabled or has not detected an error 10779 * 0b1..System OSC Clock Monitor is enabled and detected an error 10780 */ 10781 #define SCG_SOSCCSR_SOSCERR(x) (((uint32_t)(((uint32_t)(x)) << SCG_SOSCCSR_SOSCERR_SHIFT)) & SCG_SOSCCSR_SOSCERR_MASK) 10782 /*! @} */ 10783 10784 /*! @name SOSCDIV - System OSC Divide Register */ 10785 /*! @{ */ 10786 #define SCG_SOSCDIV_SOSCDIV2_MASK (0x700U) 10787 #define SCG_SOSCDIV_SOSCDIV2_SHIFT (8U) 10788 /*! SOSCDIV2 - System OSC Clock Divide 2 10789 * 0b000..Output disabled 10790 * 0b001..Divide by 1 10791 * 0b010..Divide by 2 10792 * 0b011..Divide by 4 10793 * 0b100..Divide by 8 10794 * 0b101..Divide by 16 10795 * 0b110..Divide by 32 10796 * 0b111..Divide by 64 10797 */ 10798 #define SCG_SOSCDIV_SOSCDIV2(x) (((uint32_t)(((uint32_t)(x)) << SCG_SOSCDIV_SOSCDIV2_SHIFT)) & SCG_SOSCDIV_SOSCDIV2_MASK) 10799 /*! @} */ 10800 10801 /*! @name SOSCCFG - System Oscillator Configuration Register */ 10802 /*! @{ */ 10803 #define SCG_SOSCCFG_EREFS_MASK (0x4U) 10804 #define SCG_SOSCCFG_EREFS_SHIFT (2U) 10805 /*! EREFS - External Reference Select 10806 * 0b0..External reference clock selected 10807 * 0b1..Internal crystal oscillator of OSC selected. 10808 */ 10809 #define SCG_SOSCCFG_EREFS(x) (((uint32_t)(((uint32_t)(x)) << SCG_SOSCCFG_EREFS_SHIFT)) & SCG_SOSCCFG_EREFS_MASK) 10810 #define SCG_SOSCCFG_HGO_MASK (0x8U) 10811 #define SCG_SOSCCFG_HGO_SHIFT (3U) 10812 /*! HGO - High Gain Oscillator Select 10813 * 0b0..Configure crystal oscillator for low-gain operation 10814 * 0b1..Configure crystal oscillator for high-gain operation 10815 */ 10816 #define SCG_SOSCCFG_HGO(x) (((uint32_t)(((uint32_t)(x)) << SCG_SOSCCFG_HGO_SHIFT)) & SCG_SOSCCFG_HGO_MASK) 10817 #define SCG_SOSCCFG_RANGE_MASK (0x30U) 10818 #define SCG_SOSCCFG_RANGE_SHIFT (4U) 10819 /*! RANGE - System OSC Range Select 10820 * 0b00..Reserved 10821 * 0b01..Low frequency range selected for the crystal oscillator 10822 * 0b10..Medium frequency range selected for the crytstal oscillator 10823 * 0b11..High frequency range selected for the crystal oscillator 10824 */ 10825 #define SCG_SOSCCFG_RANGE(x) (((uint32_t)(((uint32_t)(x)) << SCG_SOSCCFG_RANGE_SHIFT)) & SCG_SOSCCFG_RANGE_MASK) 10826 /*! @} */ 10827 10828 /*! @name SIRCCSR - Slow IRC Control Status Register */ 10829 /*! @{ */ 10830 #define SCG_SIRCCSR_SIRCEN_MASK (0x1U) 10831 #define SCG_SIRCCSR_SIRCEN_SHIFT (0U) 10832 /*! SIRCEN - Slow IRC Enable 10833 * 0b0..Slow IRC is disabled 10834 * 0b1..Slow IRC is enabled 10835 */ 10836 #define SCG_SIRCCSR_SIRCEN(x) (((uint32_t)(((uint32_t)(x)) << SCG_SIRCCSR_SIRCEN_SHIFT)) & SCG_SIRCCSR_SIRCEN_MASK) 10837 #define SCG_SIRCCSR_SIRCSTEN_MASK (0x2U) 10838 #define SCG_SIRCCSR_SIRCSTEN_SHIFT (1U) 10839 /*! SIRCSTEN - Slow IRC Stop Enable 10840 * 0b0..Slow IRC is disabled in supported Stop modes 10841 * 0b1..Slow IRC is enabled in supported Stop modes 10842 */ 10843 #define SCG_SIRCCSR_SIRCSTEN(x) (((uint32_t)(((uint32_t)(x)) << SCG_SIRCCSR_SIRCSTEN_SHIFT)) & SCG_SIRCCSR_SIRCSTEN_MASK) 10844 #define SCG_SIRCCSR_SIRCLPEN_MASK (0x4U) 10845 #define SCG_SIRCCSR_SIRCLPEN_SHIFT (2U) 10846 /*! SIRCLPEN - Slow IRC Low Power Enable 10847 * 0b0..Slow IRC is disabled in VLP modes 10848 * 0b1..Slow IRC is enabled in VLP modes 10849 */ 10850 #define SCG_SIRCCSR_SIRCLPEN(x) (((uint32_t)(((uint32_t)(x)) << SCG_SIRCCSR_SIRCLPEN_SHIFT)) & SCG_SIRCCSR_SIRCLPEN_MASK) 10851 #define SCG_SIRCCSR_LK_MASK (0x800000U) 10852 #define SCG_SIRCCSR_LK_SHIFT (23U) 10853 /*! LK - Lock Register 10854 * 0b0..Control Status Register can be written. 10855 * 0b1..Control Status Register cannot be written. 10856 */ 10857 #define SCG_SIRCCSR_LK(x) (((uint32_t)(((uint32_t)(x)) << SCG_SIRCCSR_LK_SHIFT)) & SCG_SIRCCSR_LK_MASK) 10858 #define SCG_SIRCCSR_SIRCVLD_MASK (0x1000000U) 10859 #define SCG_SIRCCSR_SIRCVLD_SHIFT (24U) 10860 /*! SIRCVLD - Slow IRC Valid 10861 * 0b0..Slow IRC is not enabled or clock is not valid 10862 * 0b1..Slow IRC is enabled and output clock is valid 10863 */ 10864 #define SCG_SIRCCSR_SIRCVLD(x) (((uint32_t)(((uint32_t)(x)) << SCG_SIRCCSR_SIRCVLD_SHIFT)) & SCG_SIRCCSR_SIRCVLD_MASK) 10865 #define SCG_SIRCCSR_SIRCSEL_MASK (0x2000000U) 10866 #define SCG_SIRCCSR_SIRCSEL_SHIFT (25U) 10867 /*! SIRCSEL - Slow IRC Selected 10868 * 0b0..Slow IRC is not the system clock source 10869 * 0b1..Slow IRC is the system clock source 10870 */ 10871 #define SCG_SIRCCSR_SIRCSEL(x) (((uint32_t)(((uint32_t)(x)) << SCG_SIRCCSR_SIRCSEL_SHIFT)) & SCG_SIRCCSR_SIRCSEL_MASK) 10872 /*! @} */ 10873 10874 /*! @name SIRCDIV - Slow IRC Divide Register */ 10875 /*! @{ */ 10876 #define SCG_SIRCDIV_SIRCDIV2_MASK (0x700U) 10877 #define SCG_SIRCDIV_SIRCDIV2_SHIFT (8U) 10878 /*! SIRCDIV2 - Slow IRC Clock Divide 2 10879 * 0b000..Output disabled 10880 * 0b001..Divide by 1 10881 * 0b010..Divide by 2 10882 * 0b011..Divide by 4 10883 * 0b100..Divide by 8 10884 * 0b101..Divide by 16 10885 * 0b110..Divide by 32 10886 * 0b111..Divide by 64 10887 */ 10888 #define SCG_SIRCDIV_SIRCDIV2(x) (((uint32_t)(((uint32_t)(x)) << SCG_SIRCDIV_SIRCDIV2_SHIFT)) & SCG_SIRCDIV_SIRCDIV2_MASK) 10889 /*! @} */ 10890 10891 /*! @name SIRCCFG - Slow IRC Configuration Register */ 10892 /*! @{ */ 10893 #define SCG_SIRCCFG_RANGE_MASK (0x1U) 10894 #define SCG_SIRCCFG_RANGE_SHIFT (0U) 10895 /*! RANGE - Frequency Range 10896 * 0b0..Slow IRC low range clock (2 MHz) 10897 * 0b1..Slow IRC high range clock (8 MHz ) 10898 */ 10899 #define SCG_SIRCCFG_RANGE(x) (((uint32_t)(((uint32_t)(x)) << SCG_SIRCCFG_RANGE_SHIFT)) & SCG_SIRCCFG_RANGE_MASK) 10900 /*! @} */ 10901 10902 /*! @name FIRCCSR - Fast IRC Control Status Register */ 10903 /*! @{ */ 10904 #define SCG_FIRCCSR_FIRCEN_MASK (0x1U) 10905 #define SCG_FIRCCSR_FIRCEN_SHIFT (0U) 10906 /*! FIRCEN - Fast IRC Enable 10907 * 0b0..Fast IRC is disabled 10908 * 0b1..Fast IRC is enabled 10909 */ 10910 #define SCG_FIRCCSR_FIRCEN(x) (((uint32_t)(((uint32_t)(x)) << SCG_FIRCCSR_FIRCEN_SHIFT)) & SCG_FIRCCSR_FIRCEN_MASK) 10911 #define SCG_FIRCCSR_FIRCSTEN_MASK (0x2U) 10912 #define SCG_FIRCCSR_FIRCSTEN_SHIFT (1U) 10913 /*! FIRCSTEN - Fast IRC Stop Enable 10914 * 0b0..Fast IRC is disabled in Stop modes. 10915 * 0b1..Fast IRC is enabled in Stop modes 10916 */ 10917 #define SCG_FIRCCSR_FIRCSTEN(x) (((uint32_t)(((uint32_t)(x)) << SCG_FIRCCSR_FIRCSTEN_SHIFT)) & SCG_FIRCCSR_FIRCSTEN_MASK) 10918 #define SCG_FIRCCSR_FIRCLPEN_MASK (0x4U) 10919 #define SCG_FIRCCSR_FIRCLPEN_SHIFT (2U) 10920 /*! FIRCLPEN - Fast IRC Low Power Enable 10921 * 0b0..Fast IRC is disabled in VLP modes 10922 * 0b1..Fast IRC is enabled in VLP modes 10923 */ 10924 #define SCG_FIRCCSR_FIRCLPEN(x) (((uint32_t)(((uint32_t)(x)) << SCG_FIRCCSR_FIRCLPEN_SHIFT)) & SCG_FIRCCSR_FIRCLPEN_MASK) 10925 #define SCG_FIRCCSR_FIRCREGOFF_MASK (0x8U) 10926 #define SCG_FIRCCSR_FIRCREGOFF_SHIFT (3U) 10927 /*! FIRCREGOFF - Fast IRC Regulator Enable 10928 * 0b0..Fast IRC Regulator is enabled. 10929 * 0b1..Fast IRC Regulator is disabled. 10930 */ 10931 #define SCG_FIRCCSR_FIRCREGOFF(x) (((uint32_t)(((uint32_t)(x)) << SCG_FIRCCSR_FIRCREGOFF_SHIFT)) & SCG_FIRCCSR_FIRCREGOFF_MASK) 10932 #define SCG_FIRCCSR_FIRCTREN_MASK (0x100U) 10933 #define SCG_FIRCCSR_FIRCTREN_SHIFT (8U) 10934 /*! FIRCTREN - Fast IRC Trim Enable 10935 * 0b0..Disable trimming Fast IRC to an external clock source 10936 * 0b1..Enable trimming Fast IRC to an external clock source 10937 */ 10938 #define SCG_FIRCCSR_FIRCTREN(x) (((uint32_t)(((uint32_t)(x)) << SCG_FIRCCSR_FIRCTREN_SHIFT)) & SCG_FIRCCSR_FIRCTREN_MASK) 10939 #define SCG_FIRCCSR_FIRCTRUP_MASK (0x200U) 10940 #define SCG_FIRCCSR_FIRCTRUP_SHIFT (9U) 10941 /*! FIRCTRUP - Fast IRC Trim Update 10942 * 0b0..Disable Fast IRC trimming updates 10943 * 0b1..Enable Fast IRC trimming updates 10944 */ 10945 #define SCG_FIRCCSR_FIRCTRUP(x) (((uint32_t)(((uint32_t)(x)) << SCG_FIRCCSR_FIRCTRUP_SHIFT)) & SCG_FIRCCSR_FIRCTRUP_MASK) 10946 #define SCG_FIRCCSR_LK_MASK (0x800000U) 10947 #define SCG_FIRCCSR_LK_SHIFT (23U) 10948 /*! LK - Lock Register 10949 * 0b0..Control Status Register can be written. 10950 * 0b1..Control Status Register cannot be written. 10951 */ 10952 #define SCG_FIRCCSR_LK(x) (((uint32_t)(((uint32_t)(x)) << SCG_FIRCCSR_LK_SHIFT)) & SCG_FIRCCSR_LK_MASK) 10953 #define SCG_FIRCCSR_FIRCVLD_MASK (0x1000000U) 10954 #define SCG_FIRCCSR_FIRCVLD_SHIFT (24U) 10955 /*! FIRCVLD - Fast IRC Valid status 10956 * 0b0..Fast IRC is not enabled or clock is not valid. 10957 * 0b1..Fast IRC is enabled and output clock is valid. The clock is valid once there is an output clock from the FIRC analog. 10958 */ 10959 #define SCG_FIRCCSR_FIRCVLD(x) (((uint32_t)(((uint32_t)(x)) << SCG_FIRCCSR_FIRCVLD_SHIFT)) & SCG_FIRCCSR_FIRCVLD_MASK) 10960 #define SCG_FIRCCSR_FIRCSEL_MASK (0x2000000U) 10961 #define SCG_FIRCCSR_FIRCSEL_SHIFT (25U) 10962 /*! FIRCSEL - Fast IRC Selected status 10963 * 0b0..Fast IRC is not the system clock source 10964 * 0b1..Fast IRC is the system clock source 10965 */ 10966 #define SCG_FIRCCSR_FIRCSEL(x) (((uint32_t)(((uint32_t)(x)) << SCG_FIRCCSR_FIRCSEL_SHIFT)) & SCG_FIRCCSR_FIRCSEL_MASK) 10967 #define SCG_FIRCCSR_FIRCERR_MASK (0x4000000U) 10968 #define SCG_FIRCCSR_FIRCERR_SHIFT (26U) 10969 /*! FIRCERR - Fast IRC Clock Error 10970 * 0b0..Error not detected with the Fast IRC trimming. 10971 * 0b1..Error detected with the Fast IRC trimming. 10972 */ 10973 #define SCG_FIRCCSR_FIRCERR(x) (((uint32_t)(((uint32_t)(x)) << SCG_FIRCCSR_FIRCERR_SHIFT)) & SCG_FIRCCSR_FIRCERR_MASK) 10974 /*! @} */ 10975 10976 /*! @name FIRCDIV - Fast IRC Divide Register */ 10977 /*! @{ */ 10978 #define SCG_FIRCDIV_FIRCDIV2_MASK (0x700U) 10979 #define SCG_FIRCDIV_FIRCDIV2_SHIFT (8U) 10980 /*! FIRCDIV2 - Fast IRC Clock Divide 2 10981 * 0b000..Output disabled 10982 * 0b001..Divide by 1 10983 * 0b010..Divide by 2 10984 * 0b011..Divide by 4 10985 * 0b100..Divide by 8 10986 * 0b101..Divide by 16 10987 * 0b110..Divide by 32 10988 * 0b111..Divide by 64 10989 */ 10990 #define SCG_FIRCDIV_FIRCDIV2(x) (((uint32_t)(((uint32_t)(x)) << SCG_FIRCDIV_FIRCDIV2_SHIFT)) & SCG_FIRCDIV_FIRCDIV2_MASK) 10991 /*! @} */ 10992 10993 /*! @name FIRCCFG - Fast IRC Configuration Register */ 10994 /*! @{ */ 10995 #define SCG_FIRCCFG_RANGE_MASK (0x3U) 10996 #define SCG_FIRCCFG_RANGE_SHIFT (0U) 10997 /*! RANGE - Frequency Range 10998 * 0b00..Fast IRC is trimmed to 48 MHz 10999 * 0b01..Reserved 11000 * 0b10..Reserved 11001 * 0b11..Reserved 11002 */ 11003 #define SCG_FIRCCFG_RANGE(x) (((uint32_t)(((uint32_t)(x)) << SCG_FIRCCFG_RANGE_SHIFT)) & SCG_FIRCCFG_RANGE_MASK) 11004 /*! @} */ 11005 11006 /*! @name FIRCTCFG - Fast IRC Trim Configuration Register */ 11007 /*! @{ */ 11008 #define SCG_FIRCTCFG_TRIMSRC_MASK (0x3U) 11009 #define SCG_FIRCTCFG_TRIMSRC_SHIFT (0U) 11010 /*! TRIMSRC - Trim Source 11011 * 0b00..Reserved 11012 * 0b01..Reserved 11013 * 0b10..System OSC 11014 * 0b11..Reserved 11015 */ 11016 #define SCG_FIRCTCFG_TRIMSRC(x) (((uint32_t)(((uint32_t)(x)) << SCG_FIRCTCFG_TRIMSRC_SHIFT)) & SCG_FIRCTCFG_TRIMSRC_MASK) 11017 #define SCG_FIRCTCFG_TRIMDIV_MASK (0x700U) 11018 #define SCG_FIRCTCFG_TRIMDIV_SHIFT (8U) 11019 /*! TRIMDIV - Fast IRC Trim Predivide 11020 * 0b000..Divide by 1 11021 * 0b001..Divide by 128 11022 * 0b010..Divide by 256 11023 * 0b011..Divide by 512 11024 * 0b100..Divide by 1024 11025 * 0b101..Divide by 2048 11026 * 0b110..Reserved. Writing this value will result in Divide by 1. 11027 * 0b111..Reserved. Writing this value will result in a Divide by 1. 11028 */ 11029 #define SCG_FIRCTCFG_TRIMDIV(x) (((uint32_t)(((uint32_t)(x)) << SCG_FIRCTCFG_TRIMDIV_SHIFT)) & SCG_FIRCTCFG_TRIMDIV_MASK) 11030 /*! @} */ 11031 11032 /*! @name FIRCSTAT - Fast IRC Status Register */ 11033 /*! @{ */ 11034 #define SCG_FIRCSTAT_TRIMFINE_MASK (0x7FU) 11035 #define SCG_FIRCSTAT_TRIMFINE_SHIFT (0U) 11036 /*! TRIMFINE - Trim Fine Status 11037 */ 11038 #define SCG_FIRCSTAT_TRIMFINE(x) (((uint32_t)(((uint32_t)(x)) << SCG_FIRCSTAT_TRIMFINE_SHIFT)) & SCG_FIRCSTAT_TRIMFINE_MASK) 11039 #define SCG_FIRCSTAT_TRIMCOAR_MASK (0x3F00U) 11040 #define SCG_FIRCSTAT_TRIMCOAR_SHIFT (8U) 11041 /*! TRIMCOAR - Trim Coarse 11042 */ 11043 #define SCG_FIRCSTAT_TRIMCOAR(x) (((uint32_t)(((uint32_t)(x)) << SCG_FIRCSTAT_TRIMCOAR_SHIFT)) & SCG_FIRCSTAT_TRIMCOAR_MASK) 11044 /*! @} */ 11045 11046 /*! @name LPFLLCSR - Low Power FLL Control Status Register */ 11047 /*! @{ */ 11048 #define SCG_LPFLLCSR_LPFLLEN_MASK (0x1U) 11049 #define SCG_LPFLLCSR_LPFLLEN_SHIFT (0U) 11050 /*! LPFLLEN - LPFLL Enable 11051 * 0b0..LPFLL is disabled 11052 * 0b1..LPFLL is enabled 11053 */ 11054 #define SCG_LPFLLCSR_LPFLLEN(x) (((uint32_t)(((uint32_t)(x)) << SCG_LPFLLCSR_LPFLLEN_SHIFT)) & SCG_LPFLLCSR_LPFLLEN_MASK) 11055 #define SCG_LPFLLCSR_LPFLLTREN_MASK (0x100U) 11056 #define SCG_LPFLLCSR_LPFLLTREN_SHIFT (8U) 11057 /*! LPFLLTREN - LPFLL Trim Enable 11058 * 0b0..Disable trimming LPFLL to an reference clock source 11059 * 0b1..Enable trimming LPFLL to an reference clock source 11060 */ 11061 #define SCG_LPFLLCSR_LPFLLTREN(x) (((uint32_t)(((uint32_t)(x)) << SCG_LPFLLCSR_LPFLLTREN_SHIFT)) & SCG_LPFLLCSR_LPFLLTREN_MASK) 11062 #define SCG_LPFLLCSR_LPFLLTRUP_MASK (0x200U) 11063 #define SCG_LPFLLCSR_LPFLLTRUP_SHIFT (9U) 11064 /*! LPFLLTRUP - LPFLL Trim Update 11065 * 0b0..Disable LPFLL trimming updates. LPFLL frequency determined by AUTOTRIM written value. 11066 * 0b1..Enable LPFLL trimming updates. LPFLL frequency determined by reference clock multiplication 11067 */ 11068 #define SCG_LPFLLCSR_LPFLLTRUP(x) (((uint32_t)(((uint32_t)(x)) << SCG_LPFLLCSR_LPFLLTRUP_SHIFT)) & SCG_LPFLLCSR_LPFLLTRUP_MASK) 11069 #define SCG_LPFLLCSR_LPFLLTRMLOCK_MASK (0x400U) 11070 #define SCG_LPFLLCSR_LPFLLTRMLOCK_SHIFT (10U) 11071 /*! LPFLLTRMLOCK - LPFLL Trim LOCK 11072 * 0b0..LPFLL not Locked 11073 * 0b1..LPFLL trimmed and Locked 11074 */ 11075 #define SCG_LPFLLCSR_LPFLLTRMLOCK(x) (((uint32_t)(((uint32_t)(x)) << SCG_LPFLLCSR_LPFLLTRMLOCK_SHIFT)) & SCG_LPFLLCSR_LPFLLTRMLOCK_MASK) 11076 #define SCG_LPFLLCSR_LPFLLCM_MASK (0x10000U) 11077 #define SCG_LPFLLCSR_LPFLLCM_SHIFT (16U) 11078 /*! LPFLLCM - LPFLL Clock Monitor 11079 * 0b0..LPFLL Clock Monitor is disabled 11080 * 0b1..LPFLL Clock Monitor is enabled 11081 */ 11082 #define SCG_LPFLLCSR_LPFLLCM(x) (((uint32_t)(((uint32_t)(x)) << SCG_LPFLLCSR_LPFLLCM_SHIFT)) & SCG_LPFLLCSR_LPFLLCM_MASK) 11083 #define SCG_LPFLLCSR_LPFLLCMRE_MASK (0x20000U) 11084 #define SCG_LPFLLCSR_LPFLLCMRE_SHIFT (17U) 11085 /*! LPFLLCMRE - LPFLL Clock Monitor Reset Enable 11086 * 0b0..Clock Monitor generates interrupt when error detected 11087 * 0b1..Clock Monitor generates reset when error detected 11088 */ 11089 #define SCG_LPFLLCSR_LPFLLCMRE(x) (((uint32_t)(((uint32_t)(x)) << SCG_LPFLLCSR_LPFLLCMRE_SHIFT)) & SCG_LPFLLCSR_LPFLLCMRE_MASK) 11090 #define SCG_LPFLLCSR_LK_MASK (0x800000U) 11091 #define SCG_LPFLLCSR_LK_SHIFT (23U) 11092 /*! LK - Lock Register 11093 * 0b0..Control Status Register can be written. 11094 * 0b1..Control Status Register cannot be written. 11095 */ 11096 #define SCG_LPFLLCSR_LK(x) (((uint32_t)(((uint32_t)(x)) << SCG_LPFLLCSR_LK_SHIFT)) & SCG_LPFLLCSR_LK_MASK) 11097 #define SCG_LPFLLCSR_LPFLLVLD_MASK (0x1000000U) 11098 #define SCG_LPFLLCSR_LPFLLVLD_SHIFT (24U) 11099 /*! LPFLLVLD - LPFLL Valid 11100 * 0b0..LPFLL is not enabled or clock is not valid. 11101 * 0b1..LPFLL is enabled and output clock is valid. 11102 */ 11103 #define SCG_LPFLLCSR_LPFLLVLD(x) (((uint32_t)(((uint32_t)(x)) << SCG_LPFLLCSR_LPFLLVLD_SHIFT)) & SCG_LPFLLCSR_LPFLLVLD_MASK) 11104 #define SCG_LPFLLCSR_LPFLLSEL_MASK (0x2000000U) 11105 #define SCG_LPFLLCSR_LPFLLSEL_SHIFT (25U) 11106 /*! LPFLLSEL - LPFLL Selected 11107 * 0b0..LPFLL is not the system clock source 11108 * 0b1..LPFLL is the system clock source 11109 */ 11110 #define SCG_LPFLLCSR_LPFLLSEL(x) (((uint32_t)(((uint32_t)(x)) << SCG_LPFLLCSR_LPFLLSEL_SHIFT)) & SCG_LPFLLCSR_LPFLLSEL_MASK) 11111 #define SCG_LPFLLCSR_LPFLLERR_MASK (0x4000000U) 11112 #define SCG_LPFLLCSR_LPFLLERR_SHIFT (26U) 11113 /*! LPFLLERR - LPFLL Clock Error 11114 * 0b0..Error not detected with the LPFLL trimming. 11115 * 0b1..Error detected with the LPFLL trimming. 11116 */ 11117 #define SCG_LPFLLCSR_LPFLLERR(x) (((uint32_t)(((uint32_t)(x)) << SCG_LPFLLCSR_LPFLLERR_SHIFT)) & SCG_LPFLLCSR_LPFLLERR_MASK) 11118 /*! @} */ 11119 11120 /*! @name LPFLLDIV - Low Power FLL Divide Register */ 11121 /*! @{ */ 11122 #define SCG_LPFLLDIV_LPFLLDIV2_MASK (0x700U) 11123 #define SCG_LPFLLDIV_LPFLLDIV2_SHIFT (8U) 11124 /*! LPFLLDIV2 - LPFLL Clock Divide 2 11125 * 0b000..Output disabled 11126 * 0b001..Divide by 1 11127 * 0b010..Divide by 2 11128 * 0b011..Divide by 4 11129 * 0b100..Divide by 8 11130 * 0b101..Divide by 16 11131 * 0b110..Divide by 32 11132 * 0b111..Divide by 64 11133 */ 11134 #define SCG_LPFLLDIV_LPFLLDIV2(x) (((uint32_t)(((uint32_t)(x)) << SCG_LPFLLDIV_LPFLLDIV2_SHIFT)) & SCG_LPFLLDIV_LPFLLDIV2_MASK) 11135 /*! @} */ 11136 11137 /*! @name LPFLLCFG - Low Power FLL Configuration Register */ 11138 /*! @{ */ 11139 #define SCG_LPFLLCFG_FSEL_MASK (0x3U) 11140 #define SCG_LPFLLCFG_FSEL_SHIFT (0U) 11141 /*! FSEL - Frequency Select 11142 * 0b00..LPFLL is trimmed to 48 MHz 11143 * 0b01..Reserved 11144 * 0b10..Reserved 11145 * 0b11..Reserved 11146 */ 11147 #define SCG_LPFLLCFG_FSEL(x) (((uint32_t)(((uint32_t)(x)) << SCG_LPFLLCFG_FSEL_SHIFT)) & SCG_LPFLLCFG_FSEL_MASK) 11148 /*! @} */ 11149 11150 /*! @name LPFLLTCFG - Low Power FLL Trim Configuration Register */ 11151 /*! @{ */ 11152 #define SCG_LPFLLTCFG_TRIMSRC_MASK (0x3U) 11153 #define SCG_LPFLLTCFG_TRIMSRC_SHIFT (0U) 11154 /*! TRIMSRC - Trim Source 11155 * 0b00..SIRC 11156 * 0b01..FIRC 11157 * 0b10..System OSC 11158 * 0b11..RTC OSC 11159 */ 11160 #define SCG_LPFLLTCFG_TRIMSRC(x) (((uint32_t)(((uint32_t)(x)) << SCG_LPFLLTCFG_TRIMSRC_SHIFT)) & SCG_LPFLLTCFG_TRIMSRC_MASK) 11161 #define SCG_LPFLLTCFG_TRIMDIV_MASK (0x1F00U) 11162 #define SCG_LPFLLTCFG_TRIMDIV_SHIFT (8U) 11163 /*! TRIMDIV - LPFLL Trim Predivide 11164 */ 11165 #define SCG_LPFLLTCFG_TRIMDIV(x) (((uint32_t)(((uint32_t)(x)) << SCG_LPFLLTCFG_TRIMDIV_SHIFT)) & SCG_LPFLLTCFG_TRIMDIV_MASK) 11166 #define SCG_LPFLLTCFG_LOCKW2LSB_MASK (0x10000U) 11167 #define SCG_LPFLLTCFG_LOCKW2LSB_SHIFT (16U) 11168 /*! LOCKW2LSB - Lock LPFLL with 2 LSBS 11169 * 0b0..LPFLL locks within 1LSB (0.4%) 11170 * 0b1..LPFLL locks within 2LSB (0.8%) 11171 */ 11172 #define SCG_LPFLLTCFG_LOCKW2LSB(x) (((uint32_t)(((uint32_t)(x)) << SCG_LPFLLTCFG_LOCKW2LSB_SHIFT)) & SCG_LPFLLTCFG_LOCKW2LSB_MASK) 11173 /*! @} */ 11174 11175 /*! @name LPFLLSTAT - Low Power FLL Status Register */ 11176 /*! @{ */ 11177 #define SCG_LPFLLSTAT_AUTOTRIM_MASK (0xFFU) 11178 #define SCG_LPFLLSTAT_AUTOTRIM_SHIFT (0U) 11179 /*! AUTOTRIM - Auto Tune Trim Status 11180 */ 11181 #define SCG_LPFLLSTAT_AUTOTRIM(x) (((uint32_t)(((uint32_t)(x)) << SCG_LPFLLSTAT_AUTOTRIM_SHIFT)) & SCG_LPFLLSTAT_AUTOTRIM_MASK) 11182 /*! @} */ 11183 11184 11185 /*! 11186 * @} 11187 */ /* end of group SCG_Register_Masks */ 11188 11189 11190 /* SCG - Peripheral instance base addresses */ 11191 /** Peripheral SCG base address */ 11192 #define SCG_BASE (0x40064000u) 11193 /** Peripheral SCG base pointer */ 11194 #define SCG ((SCG_Type *)SCG_BASE) 11195 /** Array initializer of SCG peripheral base addresses */ 11196 #define SCG_BASE_ADDRS { SCG_BASE } 11197 /** Array initializer of SCG peripheral base pointers */ 11198 #define SCG_BASE_PTRS { SCG } 11199 /** Interrupt vectors for the SCG peripheral type */ 11200 #define SCG_IRQS { SCG_RCM_IRQn } 11201 11202 /*! 11203 * @} 11204 */ /* end of group SCG_Peripheral_Access_Layer */ 11205 11206 11207 /* ---------------------------------------------------------------------------- 11208 -- SIM Peripheral Access Layer 11209 ---------------------------------------------------------------------------- */ 11210 11211 /*! 11212 * @addtogroup SIM_Peripheral_Access_Layer SIM Peripheral Access Layer 11213 * @{ 11214 */ 11215 11216 /** SIM - Register Layout Typedef */ 11217 typedef struct { 11218 uint8_t RESERVED_0[4]; 11219 __IO uint32_t CHIPCTL; /**< Chip Control register, offset: 0x4 */ 11220 uint8_t RESERVED_1[4]; 11221 __IO uint32_t FTMOPT0; /**< FTM Option Register 0, offset: 0xC */ 11222 uint8_t RESERVED_2[8]; 11223 __IO uint32_t ADCOPT; /**< ADC Options Register, offset: 0x18 */ 11224 __IO uint32_t FTMOPT1; /**< FTM Option Register 1, offset: 0x1C */ 11225 uint8_t RESERVED_3[4]; 11226 __I uint32_t SDID; /**< System Device Identification Register, offset: 0x24 */ 11227 uint8_t RESERVED_4[36]; 11228 __IO uint32_t FCFG1; /**< Flash Configuration Register 1, offset: 0x4C */ 11229 __I uint32_t FCFG2; /**< Flash Configuration Register 2, offset: 0x50 */ 11230 __I uint32_t UIDH; /**< Unique Identification Register High, offset: 0x54 */ 11231 __I uint32_t UIDMH; /**< Unique Identification Register Mid-High, offset: 0x58 */ 11232 __I uint32_t UIDML; /**< Unique Identification Register Mid Low, offset: 0x5C */ 11233 __I uint32_t UIDL; /**< Unique Identification Register Low, offset: 0x60 */ 11234 uint8_t RESERVED_5[8]; 11235 __IO uint32_t MISCTRL; /**< Miscellaneous Control register, offset: 0x6C */ 11236 } SIM_Type; 11237 11238 /* ---------------------------------------------------------------------------- 11239 -- SIM Register Masks 11240 ---------------------------------------------------------------------------- */ 11241 11242 /*! 11243 * @addtogroup SIM_Register_Masks SIM Register Masks 11244 * @{ 11245 */ 11246 11247 /*! @name CHIPCTL - Chip Control register */ 11248 /*! @{ */ 11249 #define SIM_CHIPCTL_CLKOUTDIV_MASK (0x30U) 11250 #define SIM_CHIPCTL_CLKOUTDIV_SHIFT (4U) 11251 /*! CLKOUTDIV - CLKOUT divider ratio 11252 * 0b00..Divided by 1 11253 * 0b01..Divided by 2 11254 * 0b10..Divided by 4 11255 * 0b11..Divided by 8 11256 */ 11257 #define SIM_CHIPCTL_CLKOUTDIV(x) (((uint32_t)(((uint32_t)(x)) << SIM_CHIPCTL_CLKOUTDIV_SHIFT)) & SIM_CHIPCTL_CLKOUTDIV_MASK) 11258 #define SIM_CHIPCTL_CLKOUTSEL_MASK (0xC0U) 11259 #define SIM_CHIPCTL_CLKOUTSEL_SHIFT (6U) 11260 /*! CLKOUTSEL - CLKOUT Select 11261 * 0b00..Reserved 11262 * 0b01..SCGCLKOUT(SIRC/FIRC/SOSC/LPFLL), see SCG_CLKOUTCNFG register. 11263 * 0b10..Reserved 11264 * 0b11..LPO clock (128 kHz) 11265 */ 11266 #define SIM_CHIPCTL_CLKOUTSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_CHIPCTL_CLKOUTSEL_SHIFT)) & SIM_CHIPCTL_CLKOUTSEL_MASK) 11267 #define SIM_CHIPCTL_PWTCLKSEL_MASK (0x30000U) 11268 #define SIM_CHIPCTL_PWTCLKSEL_SHIFT (16U) 11269 /*! PWTCLKSEL - PWT clock source select 11270 * 0b00..PWT alternative clock is from the TCLK0 pin. 11271 * 0b01..PWT alternative clock is from the TCLK1 pin. 11272 * 0b10..PWT alternative clock is from the TCLK2 pin. 11273 * 0b11..Reserved 11274 */ 11275 #define SIM_CHIPCTL_PWTCLKSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_CHIPCTL_PWTCLKSEL_SHIFT)) & SIM_CHIPCTL_PWTCLKSEL_MASK) 11276 #define SIM_CHIPCTL_RTC32KCLKSEL_MASK (0xC0000U) 11277 #define SIM_CHIPCTL_RTC32KCLKSEL_SHIFT (18U) 11278 /*! RTC32KCLKSEL - RTC 32K clock input select 11279 * 0b00..SOSC 32 kHZ high gain clock 11280 * 0b01..RTC_CLKIN 11281 * 0b10..LPO 32 kHZ clock output 11282 * 0b11..Reserved 11283 */ 11284 #define SIM_CHIPCTL_RTC32KCLKSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_CHIPCTL_RTC32KCLKSEL_SHIFT)) & SIM_CHIPCTL_RTC32KCLKSEL_MASK) 11285 /*! @} */ 11286 11287 /*! @name FTMOPT0 - FTM Option Register 0 */ 11288 /*! @{ */ 11289 #define SIM_FTMOPT0_FTM0FLTxSEL_MASK (0x7U) 11290 #define SIM_FTMOPT0_FTM0FLTxSEL_SHIFT (0U) 11291 /*! FTM0FLTxSEL - FTM0 Fault x Select 11292 */ 11293 #define SIM_FTMOPT0_FTM0FLTxSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_FTMOPT0_FTM0FLTxSEL_SHIFT)) & SIM_FTMOPT0_FTM0FLTxSEL_MASK) 11294 #define SIM_FTMOPT0_FTM0CLKSEL_MASK (0x3000000U) 11295 #define SIM_FTMOPT0_FTM0CLKSEL_SHIFT (24U) 11296 /*! FTM0CLKSEL - FTM0 External Clock Pin Select 11297 * 0b00..FTM0 external clock driven by TCLK0 pin. 11298 * 0b01..FTM0 external clock driven by TCLK1 pin. 11299 * 0b10..FTM0 external clock driven by TCLK2 pin. 11300 * 0b11..No clock input 11301 */ 11302 #define SIM_FTMOPT0_FTM0CLKSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_FTMOPT0_FTM0CLKSEL_SHIFT)) & SIM_FTMOPT0_FTM0CLKSEL_MASK) 11303 #define SIM_FTMOPT0_FTM1CLKSEL_MASK (0xC000000U) 11304 #define SIM_FTMOPT0_FTM1CLKSEL_SHIFT (26U) 11305 /*! FTM1CLKSEL - FTM1 External Clock Pin Select 11306 * 0b00..FTM1 external clock driven by TCLK0 pin. 11307 * 0b01..FTM1 external clock driven by TCLK1 pin. 11308 * 0b10..FTM1 external clock driven by TCLK2 pin. 11309 * 0b11..No clock input 11310 */ 11311 #define SIM_FTMOPT0_FTM1CLKSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_FTMOPT0_FTM1CLKSEL_SHIFT)) & SIM_FTMOPT0_FTM1CLKSEL_MASK) 11312 /*! @} */ 11313 11314 /*! @name ADCOPT - ADC Options Register */ 11315 /*! @{ */ 11316 #define SIM_ADCOPT_ADC0TRGSEL_MASK (0x1U) 11317 #define SIM_ADCOPT_ADC0TRGSEL_SHIFT (0U) 11318 /*! ADC0TRGSEL - ADC0 trigger source select 11319 * 0b0..PDB output 11320 * 0b1..TRGMUX output 11321 */ 11322 #define SIM_ADCOPT_ADC0TRGSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_ADCOPT_ADC0TRGSEL_SHIFT)) & SIM_ADCOPT_ADC0TRGSEL_MASK) 11323 #define SIM_ADCOPT_ADC0SWPRETRG_MASK (0xEU) 11324 #define SIM_ADCOPT_ADC0SWPRETRG_SHIFT (1U) 11325 /*! ADC0SWPRETRG - ADC0 software pre-trigger sources 11326 * 0b000..software pre-trigger disabled 11327 * 0b100..software pre-trigger 0 11328 * 0b101..software pre-trigger 1 11329 * 0b110..software pre-trigger 2 11330 * 0b111..software pre-trigger 3 11331 */ 11332 #define SIM_ADCOPT_ADC0SWPRETRG(x) (((uint32_t)(((uint32_t)(x)) << SIM_ADCOPT_ADC0SWPRETRG_SHIFT)) & SIM_ADCOPT_ADC0SWPRETRG_MASK) 11333 #define SIM_ADCOPT_ADC0PRETRGSEL_MASK (0x30U) 11334 #define SIM_ADCOPT_ADC0PRETRGSEL_SHIFT (4U) 11335 /*! ADC0PRETRGSEL - ADC0 pre-trigger source select 11336 * 0b00..PDB output 11337 * 0b01..TRGMUX output 11338 * 0b10..ADC0 software pre-trigger 11339 * 0b11..Reserved 11340 */ 11341 #define SIM_ADCOPT_ADC0PRETRGSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_ADCOPT_ADC0PRETRGSEL_SHIFT)) & SIM_ADCOPT_ADC0PRETRGSEL_MASK) 11342 /*! @} */ 11343 11344 /*! @name FTMOPT1 - FTM Option Register 1 */ 11345 /*! @{ */ 11346 #define SIM_FTMOPT1_FTM0SYNCBIT_MASK (0x1U) 11347 #define SIM_FTMOPT1_FTM0SYNCBIT_SHIFT (0U) 11348 /*! FTM0SYNCBIT - FTM0 Sync Bit 11349 * 0b0..No effect. 11350 * 0b1..Write 1 to assert the TRIG1 input to FTM0. Software must clear this bit to allow other trigger sources to assert. 11351 */ 11352 #define SIM_FTMOPT1_FTM0SYNCBIT(x) (((uint32_t)(((uint32_t)(x)) << SIM_FTMOPT1_FTM0SYNCBIT_SHIFT)) & SIM_FTMOPT1_FTM0SYNCBIT_MASK) 11353 #define SIM_FTMOPT1_FTM1SYNCBIT_MASK (0x2U) 11354 #define SIM_FTMOPT1_FTM1SYNCBIT_SHIFT (1U) 11355 /*! FTM1SYNCBIT - FTM1 Sync Bit 11356 * 0b0..No effect. 11357 * 0b1..Write 1 to assert the TRIG1 input to FTM1. Software must clear this bit to allow other trigger sources to assert. 11358 */ 11359 #define SIM_FTMOPT1_FTM1SYNCBIT(x) (((uint32_t)(((uint32_t)(x)) << SIM_FTMOPT1_FTM1SYNCBIT_SHIFT)) & SIM_FTMOPT1_FTM1SYNCBIT_MASK) 11360 #define SIM_FTMOPT1_FTM1CH0SEL_MASK (0x30U) 11361 #define SIM_FTMOPT1_FTM1CH0SEL_SHIFT (4U) 11362 /*! FTM1CH0SEL - FTM1 CH0 Select 11363 * 0b00..FTM1_CH0 input 11364 * 0b01..CMP0 output 11365 * 0b10..Reserved 11366 * 0b11..Reserved 11367 */ 11368 #define SIM_FTMOPT1_FTM1CH0SEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_FTMOPT1_FTM1CH0SEL_SHIFT)) & SIM_FTMOPT1_FTM1CH0SEL_MASK) 11369 #define SIM_FTMOPT1_FTM0_OUTSEL_MASK (0x3F0000U) 11370 #define SIM_FTMOPT1_FTM0_OUTSEL_SHIFT (16U) 11371 /*! FTM0_OUTSEL - FTM0 channel modulation select with FTM1_CH1 11372 * 0b000000..No modulation with FTM1_CH1 11373 * 0b000001..Modulation with FTM1_CH1 11374 */ 11375 #define SIM_FTMOPT1_FTM0_OUTSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_FTMOPT1_FTM0_OUTSEL_SHIFT)) & SIM_FTMOPT1_FTM0_OUTSEL_MASK) 11376 /*! @} */ 11377 11378 /*! @name SDID - System Device Identification Register */ 11379 /*! @{ */ 11380 #define SIM_SDID_PINID_MASK (0x7FU) 11381 #define SIM_SDID_PINID_SHIFT (0U) 11382 /*! PINID - Pin identification 11383 * 0b0000100..32-pin 11384 * 0b0000101..44-pin 11385 * 0b0000110..48-pin 11386 */ 11387 #define SIM_SDID_PINID(x) (((uint32_t)(((uint32_t)(x)) << SIM_SDID_PINID_SHIFT)) & SIM_SDID_PINID_MASK) 11388 #define SIM_SDID_PROJECTID_MASK (0xF80U) 11389 #define SIM_SDID_PROJECTID_SHIFT (7U) 11390 /*! PROJECTID - Project ID 11391 */ 11392 #define SIM_SDID_PROJECTID(x) (((uint32_t)(((uint32_t)(x)) << SIM_SDID_PROJECTID_SHIFT)) & SIM_SDID_PROJECTID_MASK) 11393 #define SIM_SDID_REVID_MASK (0xF000U) 11394 #define SIM_SDID_REVID_SHIFT (12U) 11395 /*! REVID - Device revision number 11396 */ 11397 #define SIM_SDID_REVID(x) (((uint32_t)(((uint32_t)(x)) << SIM_SDID_REVID_SHIFT)) & SIM_SDID_REVID_MASK) 11398 #define SIM_SDID_RAMSIZE_MASK (0xF0000U) 11399 #define SIM_SDID_RAMSIZE_SHIFT (16U) 11400 /*! RAMSIZE - RAM size 11401 * 0b0011..4 KB 11402 * 0b0100..8 KB 11403 */ 11404 #define SIM_SDID_RAMSIZE(x) (((uint32_t)(((uint32_t)(x)) << SIM_SDID_RAMSIZE_SHIFT)) & SIM_SDID_RAMSIZE_MASK) 11405 #define SIM_SDID_SERIESID_MASK (0xF00000U) 11406 #define SIM_SDID_SERIESID_SHIFT (20U) 11407 /*! SERIESID - Kinetis Series ID 11408 * 0b0010..Kinetis E+ series 11409 */ 11410 #define SIM_SDID_SERIESID(x) (((uint32_t)(((uint32_t)(x)) << SIM_SDID_SERIESID_SHIFT)) & SIM_SDID_SERIESID_MASK) 11411 #define SIM_SDID_SUBFAMID_MASK (0xF000000U) 11412 #define SIM_SDID_SUBFAMID_SHIFT (24U) 11413 /*! SUBFAMID - Kinetis E-series Sub-Family ID 11414 */ 11415 #define SIM_SDID_SUBFAMID(x) (((uint32_t)(((uint32_t)(x)) << SIM_SDID_SUBFAMID_SHIFT)) & SIM_SDID_SUBFAMID_MASK) 11416 #define SIM_SDID_FAMILYID_MASK (0xF0000000U) 11417 #define SIM_SDID_FAMILYID_SHIFT (28U) 11418 /*! FAMILYID - Kinetis E-series Family ID 11419 * 0b0001..KE1x Family (Enhanced features) 11420 */ 11421 #define SIM_SDID_FAMILYID(x) (((uint32_t)(((uint32_t)(x)) << SIM_SDID_FAMILYID_SHIFT)) & SIM_SDID_FAMILYID_MASK) 11422 /*! @} */ 11423 11424 /*! @name FCFG1 - Flash Configuration Register 1 */ 11425 /*! @{ */ 11426 #define SIM_FCFG1_FLASHDIS_MASK (0x1U) 11427 #define SIM_FCFG1_FLASHDIS_SHIFT (0U) 11428 /*! FLASHDIS - Flash Disable 11429 * 0b0..Flash is enabled 11430 * 0b1..Flash is disabled 11431 */ 11432 #define SIM_FCFG1_FLASHDIS(x) (((uint32_t)(((uint32_t)(x)) << SIM_FCFG1_FLASHDIS_SHIFT)) & SIM_FCFG1_FLASHDIS_MASK) 11433 #define SIM_FCFG1_FLASHDOZE_MASK (0x2U) 11434 #define SIM_FCFG1_FLASHDOZE_SHIFT (1U) 11435 /*! FLASHDOZE - Flash Doze 11436 * 0b0..Flash remains enabled during Doze mode 11437 * 0b1..Flash is disabled for the duration of Doze mode 11438 */ 11439 #define SIM_FCFG1_FLASHDOZE(x) (((uint32_t)(((uint32_t)(x)) << SIM_FCFG1_FLASHDOZE_SHIFT)) & SIM_FCFG1_FLASHDOZE_MASK) 11440 #define SIM_FCFG1_PFSIZE_MASK (0xF000000U) 11441 #define SIM_FCFG1_PFSIZE_SHIFT (24U) 11442 /*! PFSIZE - Program flash size 11443 * 0b0000..8 KB of program flash memory, 1 KB protection region 11444 * 0b0001..16 KB of program flash memory, 1 KB protection region 11445 * 0b0011..32 KB of program flash memory, 1 KB protection region 11446 * 0b0101..64 KB of program flash memory, 2 KB protection region 11447 */ 11448 #define SIM_FCFG1_PFSIZE(x) (((uint32_t)(((uint32_t)(x)) << SIM_FCFG1_PFSIZE_SHIFT)) & SIM_FCFG1_PFSIZE_MASK) 11449 /*! @} */ 11450 11451 /*! @name FCFG2 - Flash Configuration Register 2 */ 11452 /*! @{ */ 11453 #define SIM_FCFG2_MAXADDR0_MASK (0x7F000000U) 11454 #define SIM_FCFG2_MAXADDR0_SHIFT (24U) 11455 /*! MAXADDR0 - Max address block 0 11456 */ 11457 #define SIM_FCFG2_MAXADDR0(x) (((uint32_t)(((uint32_t)(x)) << SIM_FCFG2_MAXADDR0_SHIFT)) & SIM_FCFG2_MAXADDR0_MASK) 11458 /*! @} */ 11459 11460 /*! @name UIDH - Unique Identification Register High */ 11461 /*! @{ */ 11462 #define SIM_UIDH_UID127_96_MASK (0xFFFFFFFFU) 11463 #define SIM_UIDH_UID127_96_SHIFT (0U) 11464 /*! UID127_96 - Unique Identification 11465 */ 11466 #define SIM_UIDH_UID127_96(x) (((uint32_t)(((uint32_t)(x)) << SIM_UIDH_UID127_96_SHIFT)) & SIM_UIDH_UID127_96_MASK) 11467 /*! @} */ 11468 11469 /*! @name UIDMH - Unique Identification Register Mid-High */ 11470 /*! @{ */ 11471 #define SIM_UIDMH_UID95_64_MASK (0xFFFFFFFFU) 11472 #define SIM_UIDMH_UID95_64_SHIFT (0U) 11473 /*! UID95_64 - Unique Identification 11474 */ 11475 #define SIM_UIDMH_UID95_64(x) (((uint32_t)(((uint32_t)(x)) << SIM_UIDMH_UID95_64_SHIFT)) & SIM_UIDMH_UID95_64_MASK) 11476 /*! @} */ 11477 11478 /*! @name UIDML - Unique Identification Register Mid Low */ 11479 /*! @{ */ 11480 #define SIM_UIDML_UID63_32_MASK (0xFFFFFFFFU) 11481 #define SIM_UIDML_UID63_32_SHIFT (0U) 11482 /*! UID63_32 - Unique Identification 11483 */ 11484 #define SIM_UIDML_UID63_32(x) (((uint32_t)(((uint32_t)(x)) << SIM_UIDML_UID63_32_SHIFT)) & SIM_UIDML_UID63_32_MASK) 11485 /*! @} */ 11486 11487 /*! @name UIDL - Unique Identification Register Low */ 11488 /*! @{ */ 11489 #define SIM_UIDL_UID31_0_MASK (0xFFFFFFFFU) 11490 #define SIM_UIDL_UID31_0_SHIFT (0U) 11491 /*! UID31_0 - Unique Identification 11492 */ 11493 #define SIM_UIDL_UID31_0(x) (((uint32_t)(((uint32_t)(x)) << SIM_UIDL_UID31_0_SHIFT)) & SIM_UIDL_UID31_0_MASK) 11494 /*! @} */ 11495 11496 /*! @name MISCTRL - Miscellaneous Control register */ 11497 /*! @{ */ 11498 #define SIM_MISCTRL_SW_TRG_MASK (0x1U) 11499 #define SIM_MISCTRL_SW_TRG_SHIFT (0U) 11500 /*! SW_TRG - Software Trigger bit to TRGMUX 11501 */ 11502 #define SIM_MISCTRL_SW_TRG(x) (((uint32_t)(((uint32_t)(x)) << SIM_MISCTRL_SW_TRG_SHIFT)) & SIM_MISCTRL_SW_TRG_MASK) 11503 /*! @} */ 11504 11505 11506 /*! 11507 * @} 11508 */ /* end of group SIM_Register_Masks */ 11509 11510 11511 /* SIM - Peripheral instance base addresses */ 11512 /** Peripheral SIM base address */ 11513 #define SIM_BASE (0x40048000u) 11514 /** Peripheral SIM base pointer */ 11515 #define SIM ((SIM_Type *)SIM_BASE) 11516 /** Array initializer of SIM peripheral base addresses */ 11517 #define SIM_BASE_ADDRS { SIM_BASE } 11518 /** Array initializer of SIM peripheral base pointers */ 11519 #define SIM_BASE_PTRS { SIM } 11520 11521 /*! 11522 * @} 11523 */ /* end of group SIM_Peripheral_Access_Layer */ 11524 11525 11526 /* ---------------------------------------------------------------------------- 11527 -- SMC Peripheral Access Layer 11528 ---------------------------------------------------------------------------- */ 11529 11530 /*! 11531 * @addtogroup SMC_Peripheral_Access_Layer SMC Peripheral Access Layer 11532 * @{ 11533 */ 11534 11535 /** SMC - Register Layout Typedef */ 11536 typedef struct { 11537 __I uint32_t VERID; /**< SMC Version ID Register, offset: 0x0 */ 11538 __I uint32_t PARAM; /**< SMC Parameter Register, offset: 0x4 */ 11539 __IO uint32_t PMPROT; /**< Power Mode Protection register, offset: 0x8 */ 11540 __IO uint32_t PMCTRL; /**< Power Mode Control register, offset: 0xC */ 11541 __IO uint32_t STOPCTRL; /**< Stop Control Register, offset: 0x10 */ 11542 __I uint32_t PMSTAT; /**< Power Mode Status register, offset: 0x14 */ 11543 } SMC_Type; 11544 11545 /* ---------------------------------------------------------------------------- 11546 -- SMC Register Masks 11547 ---------------------------------------------------------------------------- */ 11548 11549 /*! 11550 * @addtogroup SMC_Register_Masks SMC Register Masks 11551 * @{ 11552 */ 11553 11554 /*! @name VERID - SMC Version ID Register */ 11555 /*! @{ */ 11556 #define SMC_VERID_FEATURE_MASK (0xFFFFU) 11557 #define SMC_VERID_FEATURE_SHIFT (0U) 11558 /*! FEATURE - Feature Specification Number 11559 * 0b0000000000000000..Standard features implemented 11560 */ 11561 #define SMC_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << SMC_VERID_FEATURE_SHIFT)) & SMC_VERID_FEATURE_MASK) 11562 #define SMC_VERID_MINOR_MASK (0xFF0000U) 11563 #define SMC_VERID_MINOR_SHIFT (16U) 11564 /*! MINOR - Minor Version Number 11565 */ 11566 #define SMC_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << SMC_VERID_MINOR_SHIFT)) & SMC_VERID_MINOR_MASK) 11567 #define SMC_VERID_MAJOR_MASK (0xFF000000U) 11568 #define SMC_VERID_MAJOR_SHIFT (24U) 11569 /*! MAJOR - Major Version Number 11570 */ 11571 #define SMC_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << SMC_VERID_MAJOR_SHIFT)) & SMC_VERID_MAJOR_MASK) 11572 /*! @} */ 11573 11574 /*! @name PARAM - SMC Parameter Register */ 11575 /*! @{ */ 11576 #define SMC_PARAM_EHSRUN_MASK (0x1U) 11577 #define SMC_PARAM_EHSRUN_SHIFT (0U) 11578 /*! EHSRUN - Existence of HSRUN feature 11579 * 0b0..The feature is not available. 11580 * 0b1..The feature is available. 11581 */ 11582 #define SMC_PARAM_EHSRUN(x) (((uint32_t)(((uint32_t)(x)) << SMC_PARAM_EHSRUN_SHIFT)) & SMC_PARAM_EHSRUN_MASK) 11583 #define SMC_PARAM_ELLS_MASK (0x8U) 11584 #define SMC_PARAM_ELLS_SHIFT (3U) 11585 /*! ELLS - Existence of LLS feature 11586 * 0b0..The feature is not available. 11587 * 0b1..The feature is available. 11588 */ 11589 #define SMC_PARAM_ELLS(x) (((uint32_t)(((uint32_t)(x)) << SMC_PARAM_ELLS_SHIFT)) & SMC_PARAM_ELLS_MASK) 11590 #define SMC_PARAM_ELLS2_MASK (0x20U) 11591 #define SMC_PARAM_ELLS2_SHIFT (5U) 11592 /*! ELLS2 - Existence of LLS2 feature 11593 * 0b0..The feature is not available. 11594 * 0b1..The feature is available. 11595 */ 11596 #define SMC_PARAM_ELLS2(x) (((uint32_t)(((uint32_t)(x)) << SMC_PARAM_ELLS2_SHIFT)) & SMC_PARAM_ELLS2_MASK) 11597 #define SMC_PARAM_EVLLS0_MASK (0x40U) 11598 #define SMC_PARAM_EVLLS0_SHIFT (6U) 11599 /*! EVLLS0 - Existence of VLLS0 feature 11600 * 0b0..The feature is not available. 11601 * 0b1..The feature is available. 11602 */ 11603 #define SMC_PARAM_EVLLS0(x) (((uint32_t)(((uint32_t)(x)) << SMC_PARAM_EVLLS0_SHIFT)) & SMC_PARAM_EVLLS0_MASK) 11604 /*! @} */ 11605 11606 /*! @name PMPROT - Power Mode Protection register */ 11607 /*! @{ */ 11608 #define SMC_PMPROT_AVLP_MASK (0x20U) 11609 #define SMC_PMPROT_AVLP_SHIFT (5U) 11610 /*! AVLP - Allow Very-Low-Power Modes 11611 * 0b0..VLPR, VLPW, and VLPS are not allowed. 11612 * 0b1..VLPR, VLPW, and VLPS are allowed. 11613 */ 11614 #define SMC_PMPROT_AVLP(x) (((uint32_t)(((uint32_t)(x)) << SMC_PMPROT_AVLP_SHIFT)) & SMC_PMPROT_AVLP_MASK) 11615 /*! @} */ 11616 11617 /*! @name PMCTRL - Power Mode Control register */ 11618 /*! @{ */ 11619 #define SMC_PMCTRL_STOPM_MASK (0x7U) 11620 #define SMC_PMCTRL_STOPM_SHIFT (0U) 11621 /*! STOPM - Stop Mode Control 11622 * 0b000..Normal Stop (STOP) 11623 * 0b001..Reserved 11624 * 0b010..Very-Low-Power Stop (VLPS) 11625 * 0b011..Reserved 11626 * 0b101..Reserved 11627 * 0b110..Reseved 11628 * 0b111..Reserved 11629 */ 11630 #define SMC_PMCTRL_STOPM(x) (((uint32_t)(((uint32_t)(x)) << SMC_PMCTRL_STOPM_SHIFT)) & SMC_PMCTRL_STOPM_MASK) 11631 #define SMC_PMCTRL_STOPA_MASK (0x8U) 11632 #define SMC_PMCTRL_STOPA_SHIFT (3U) 11633 /*! STOPA - Stop Aborted 11634 * 0b0..The previous stop mode entry was successful. 11635 * 0b1..The previous stop mode entry was aborted. 11636 */ 11637 #define SMC_PMCTRL_STOPA(x) (((uint32_t)(((uint32_t)(x)) << SMC_PMCTRL_STOPA_SHIFT)) & SMC_PMCTRL_STOPA_MASK) 11638 #define SMC_PMCTRL_RUNM_MASK (0x60U) 11639 #define SMC_PMCTRL_RUNM_SHIFT (5U) 11640 /*! RUNM - Run Mode Control 11641 * 0b00..Normal Run mode (RUN) 11642 * 0b01..Reserved 11643 * 0b10..Very-Low-Power Run mode (VLPR) 11644 * 0b11..Reserved 11645 */ 11646 #define SMC_PMCTRL_RUNM(x) (((uint32_t)(((uint32_t)(x)) << SMC_PMCTRL_RUNM_SHIFT)) & SMC_PMCTRL_RUNM_MASK) 11647 /*! @} */ 11648 11649 /*! @name STOPCTRL - Stop Control Register */ 11650 /*! @{ */ 11651 #define SMC_STOPCTRL_PSTOPO_MASK (0xC0U) 11652 #define SMC_STOPCTRL_PSTOPO_SHIFT (6U) 11653 /*! PSTOPO - Partial Stop Option 11654 * 0b00..STOP - Normal Stop mode 11655 * 0b01..PSTOP1 - Partial Stop with both system and bus clocks disabled 11656 * 0b10..PSTOP2 - Partial Stop with system clock disabled and bus clock enabled 11657 * 0b11..Reserved 11658 */ 11659 #define SMC_STOPCTRL_PSTOPO(x) (((uint32_t)(((uint32_t)(x)) << SMC_STOPCTRL_PSTOPO_SHIFT)) & SMC_STOPCTRL_PSTOPO_MASK) 11660 /*! @} */ 11661 11662 /*! @name PMSTAT - Power Mode Status register */ 11663 /*! @{ */ 11664 #define SMC_PMSTAT_PMSTAT_MASK (0xFFU) 11665 #define SMC_PMSTAT_PMSTAT_SHIFT (0U) 11666 /*! PMSTAT - Power Mode Status 11667 */ 11668 #define SMC_PMSTAT_PMSTAT(x) (((uint32_t)(((uint32_t)(x)) << SMC_PMSTAT_PMSTAT_SHIFT)) & SMC_PMSTAT_PMSTAT_MASK) 11669 /*! @} */ 11670 11671 11672 /*! 11673 * @} 11674 */ /* end of group SMC_Register_Masks */ 11675 11676 11677 /* SMC - Peripheral instance base addresses */ 11678 /** Peripheral SMC base address */ 11679 #define SMC_BASE (0x4007E000u) 11680 /** Peripheral SMC base pointer */ 11681 #define SMC ((SMC_Type *)SMC_BASE) 11682 /** Array initializer of SMC peripheral base addresses */ 11683 #define SMC_BASE_ADDRS { SMC_BASE } 11684 /** Array initializer of SMC peripheral base pointers */ 11685 #define SMC_BASE_PTRS { SMC } 11686 11687 /*! 11688 * @} 11689 */ /* end of group SMC_Peripheral_Access_Layer */ 11690 11691 11692 /* ---------------------------------------------------------------------------- 11693 -- TRGMUX Peripheral Access Layer 11694 ---------------------------------------------------------------------------- */ 11695 11696 /*! 11697 * @addtogroup TRGMUX_Peripheral_Access_Layer TRGMUX Peripheral Access Layer 11698 * @{ 11699 */ 11700 11701 /** TRGMUX - Register Layout Typedef */ 11702 typedef struct { 11703 __IO uint32_t TRGCFG[28]; /**< TRGMUX EXTOUT0 Register..TRGMUX CTRL0 Register, array offset: 0x0, array step: 0x4 */ 11704 } TRGMUX_Type; 11705 11706 /* ---------------------------------------------------------------------------- 11707 -- TRGMUX Register Masks 11708 ---------------------------------------------------------------------------- */ 11709 11710 /*! 11711 * @addtogroup TRGMUX_Register_Masks TRGMUX Register Masks 11712 * @{ 11713 */ 11714 11715 /*! @name TRGCFG - TRGMUX EXTOUT0 Register..TRGMUX CTRL0 Register */ 11716 /*! @{ */ 11717 #define TRGMUX_TRGCFG_SEL0_MASK (0x1FU) 11718 #define TRGMUX_TRGCFG_SEL0_SHIFT (0U) 11719 /*! SEL0 - Trigger MUX Input 0 Source Select 11720 */ 11721 #define TRGMUX_TRGCFG_SEL0(x) (((uint32_t)(((uint32_t)(x)) << TRGMUX_TRGCFG_SEL0_SHIFT)) & TRGMUX_TRGCFG_SEL0_MASK) 11722 #define TRGMUX_TRGCFG_SEL1_MASK (0x1F00U) 11723 #define TRGMUX_TRGCFG_SEL1_SHIFT (8U) 11724 /*! SEL1 - Trigger MUX Input 1 Source Select 11725 */ 11726 #define TRGMUX_TRGCFG_SEL1(x) (((uint32_t)(((uint32_t)(x)) << TRGMUX_TRGCFG_SEL1_SHIFT)) & TRGMUX_TRGCFG_SEL1_MASK) 11727 #define TRGMUX_TRGCFG_SEL2_MASK (0x1F0000U) 11728 #define TRGMUX_TRGCFG_SEL2_SHIFT (16U) 11729 /*! SEL2 - Trigger MUX Input 2 Source Select 11730 */ 11731 #define TRGMUX_TRGCFG_SEL2(x) (((uint32_t)(((uint32_t)(x)) << TRGMUX_TRGCFG_SEL2_SHIFT)) & TRGMUX_TRGCFG_SEL2_MASK) 11732 #define TRGMUX_TRGCFG_SEL3_MASK (0x1F000000U) 11733 #define TRGMUX_TRGCFG_SEL3_SHIFT (24U) 11734 /*! SEL3 - Trigger MUX Input 3 Source Select 11735 */ 11736 #define TRGMUX_TRGCFG_SEL3(x) (((uint32_t)(((uint32_t)(x)) << TRGMUX_TRGCFG_SEL3_SHIFT)) & TRGMUX_TRGCFG_SEL3_MASK) 11737 #define TRGMUX_TRGCFG_LK_MASK (0x80000000U) 11738 #define TRGMUX_TRGCFG_LK_SHIFT (31U) 11739 /*! LK - TRGMUX register lock. 11740 * 0b0..Register can be written. 11741 * 0b1..Register cannot be written until the next system Reset. 11742 */ 11743 #define TRGMUX_TRGCFG_LK(x) (((uint32_t)(((uint32_t)(x)) << TRGMUX_TRGCFG_LK_SHIFT)) & TRGMUX_TRGCFG_LK_MASK) 11744 /*! @} */ 11745 11746 /* The count of TRGMUX_TRGCFG */ 11747 #define TRGMUX_TRGCFG_COUNT (28U) 11748 11749 11750 /*! 11751 * @} 11752 */ /* end of group TRGMUX_Register_Masks */ 11753 11754 11755 /* TRGMUX - Peripheral instance base addresses */ 11756 /** Peripheral TRGMUX0 base address */ 11757 #define TRGMUX0_BASE (0x40062000u) 11758 /** Peripheral TRGMUX0 base pointer */ 11759 #define TRGMUX0 ((TRGMUX_Type *)TRGMUX0_BASE) 11760 /** Peripheral TRGMUX1 base address */ 11761 #define TRGMUX1_BASE (0x40063000u) 11762 /** Peripheral TRGMUX1 base pointer */ 11763 #define TRGMUX1 ((TRGMUX_Type *)TRGMUX1_BASE) 11764 /** Array initializer of TRGMUX peripheral base addresses */ 11765 #define TRGMUX_BASE_ADDRS { TRGMUX0_BASE, TRGMUX1_BASE } 11766 /** Array initializer of TRGMUX peripheral base pointers */ 11767 #define TRGMUX_BASE_PTRS { TRGMUX0, TRGMUX1 } 11768 #define TRGMUX_INSTANCE_MASK 0xF 11769 #define TRGMUX_INSTANCE_SHIFT 12 11770 #define TRGMUX_PERIPHERAL_MASK 0xFFF 11771 #define TRGMUX_PERIPHERAL_SHIFT 0 11772 #define TRGMUX_INSTANCE_0 0 11773 #define TRGMUX_INSTANCE_1 1 11774 11775 #define TRGMUX_EXTOUT0_INDEX ((uint16_t)((TRGMUX_INSTANCE_0 & TRGMUX_INSTANCE_MASK) << TRGMUX_INSTANCE_SHIFT) | 1) 11776 #define TRGMUX_ADC0_INDEX ((uint16_t)((TRGMUX_INSTANCE_0 & TRGMUX_INSTANCE_MASK) << TRGMUX_INSTANCE_SHIFT) | 3) 11777 #define TRGMUX_CMP0_INDEX ((uint16_t)((TRGMUX_INSTANCE_0 & TRGMUX_INSTANCE_MASK) << TRGMUX_INSTANCE_SHIFT) | 7) 11778 #define TRGMUX_FTM0_INDEX ((uint16_t)((TRGMUX_INSTANCE_0 & TRGMUX_INSTANCE_MASK) << TRGMUX_INSTANCE_SHIFT) | 10) 11779 #define TRGMUX_FTM1_INDEX ((uint16_t)((TRGMUX_INSTANCE_0 & TRGMUX_INSTANCE_MASK) << TRGMUX_INSTANCE_SHIFT) | 11) 11780 #define TRGMUX_PDB0_INDEX ((uint16_t)((TRGMUX_INSTANCE_0 & TRGMUX_INSTANCE_MASK) << TRGMUX_INSTANCE_SHIFT) | 14) 11781 #define TRGMUX_LPIT0_INDEX ((uint16_t)((TRGMUX_INSTANCE_0 & TRGMUX_INSTANCE_MASK) << TRGMUX_INSTANCE_SHIFT) | 18) 11782 #define TRGMUX_LPUART0_INDEX ((uint16_t)((TRGMUX_INSTANCE_0 & TRGMUX_INSTANCE_MASK) << TRGMUX_INSTANCE_SHIFT) | 19) 11783 #define TRGMUX_LPUART1_INDEX ((uint16_t)((TRGMUX_INSTANCE_0 & TRGMUX_INSTANCE_MASK) << TRGMUX_INSTANCE_SHIFT) | 20) 11784 #define TRGMUX_LPI2C0_INDEX ((uint16_t)((TRGMUX_INSTANCE_0 & TRGMUX_INSTANCE_MASK) << TRGMUX_INSTANCE_SHIFT) | 21) 11785 #define TRGMUX_LPSPI0_INDEX ((uint16_t)((TRGMUX_INSTANCE_0 & TRGMUX_INSTANCE_MASK) << TRGMUX_INSTANCE_SHIFT) | 23) 11786 #define TRGMUX_LPTMR0_INDEX ((uint16_t)((TRGMUX_INSTANCE_0 & TRGMUX_INSTANCE_MASK) << TRGMUX_INSTANCE_SHIFT) | 25) 11787 #define TRGMUX_TSI_INDEX ((uint16_t)((TRGMUX_INSTANCE_0 & TRGMUX_INSTANCE_MASK) << TRGMUX_INSTANCE_SHIFT) | 26) 11788 #define TRGMUX_PWT_INDEX ((uint16_t)((TRGMUX_INSTANCE_0 & TRGMUX_INSTANCE_MASK) << TRGMUX_INSTANCE_SHIFT) | 27) 11789 #define TRGMUX_CTRL0_INDEX ((uint16_t)((TRGMUX_INSTANCE_1 & TRGMUX_INSTANCE_MASK) << TRGMUX_INSTANCE_SHIFT) | 0) 11790 11791 11792 /*! 11793 * @} 11794 */ /* end of group TRGMUX_Peripheral_Access_Layer */ 11795 11796 11797 /* ---------------------------------------------------------------------------- 11798 -- TSI Peripheral Access Layer 11799 ---------------------------------------------------------------------------- */ 11800 11801 /*! 11802 * @addtogroup TSI_Peripheral_Access_Layer TSI Peripheral Access Layer 11803 * @{ 11804 */ 11805 11806 /** TSI - Register Layout Typedef */ 11807 typedef struct { 11808 __IO uint32_t GENCS; /**< TSI General Control and Status Register, offset: 0x0 */ 11809 __IO uint32_t DATA; /**< TSI DATA Register, offset: 0x4 */ 11810 __IO uint32_t TSHD; /**< TSI Threshold Register, offset: 0x8 */ 11811 __IO uint32_t MODE; /**< TSI MODE Register, offset: 0xC */ 11812 __IO uint32_t MUL0; /**< TSI MUTUAL-CAP Register 0, offset: 0x10 */ 11813 __IO uint32_t MUL1; /**< TSI MUTUAL-CAP Register 1, offset: 0x14 */ 11814 __IO uint32_t SINC; /**< TSI SINC filter Register, offset: 0x18 */ 11815 __IO uint32_t SSC0; /**< TSI SSC Register 0, offset: 0x1C */ 11816 __IO uint32_t SSC1; /**< TSI SSC Register 1, offset: 0x20 */ 11817 __IO uint32_t SSC2; /**< TSI SSC Register 2, offset: 0x24 */ 11818 } TSI_Type; 11819 11820 /* ---------------------------------------------------------------------------- 11821 -- TSI Register Masks 11822 ---------------------------------------------------------------------------- */ 11823 11824 /*! 11825 * @addtogroup TSI_Register_Masks TSI Register Masks 11826 * @{ 11827 */ 11828 11829 /*! @name GENCS - TSI General Control and Status Register */ 11830 /*! @{ */ 11831 #define TSI_GENCS_EOSDMEO_MASK (0x1U) 11832 #define TSI_GENCS_EOSDMEO_SHIFT (0U) 11833 /*! EOSDMEO - End-of-Scan DMA Transfer Request Enable Only 11834 * 0b0..Do not enable the End-of-Scan DMA transfer request only. Depending on ESOR state, either Out-of-Range or 11835 * End-of-Scan can trigger a DMA transfer request and interrupt. 11836 * 0b1..Only the End-of-Scan event can trigger a DMA transfer request. The Out-of-Range event only and always triggers an interrupt if TSIIE is set. 11837 */ 11838 #define TSI_GENCS_EOSDMEO(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_EOSDMEO_SHIFT)) & TSI_GENCS_EOSDMEO_MASK) 11839 #define TSI_GENCS_EOSF_MASK (0x4U) 11840 #define TSI_GENCS_EOSF_SHIFT (2U) 11841 /*! EOSF - End of Scan Flag 11842 * 0b0..Scan not complete. 11843 * 0b1..Scan complete. 11844 */ 11845 #define TSI_GENCS_EOSF(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_EOSF_SHIFT)) & TSI_GENCS_EOSF_MASK) 11846 #define TSI_GENCS_SCNIP_MASK (0x8U) 11847 #define TSI_GENCS_SCNIP_SHIFT (3U) 11848 /*! SCNIP - Scan In Progress Status 11849 * 0b0..No scan in progress. 11850 * 0b1..Scan in progress. 11851 */ 11852 #define TSI_GENCS_SCNIP(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_SCNIP_SHIFT)) & TSI_GENCS_SCNIP_MASK) 11853 #define TSI_GENCS_STM_MASK (0x10U) 11854 #define TSI_GENCS_STM_SHIFT (4U) 11855 /*! STM - Scan Trigger Mode 11856 * 0b0..Software trigger scan. 11857 * 0b1..Hardware trigger scan. 11858 */ 11859 #define TSI_GENCS_STM(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_STM_SHIFT)) & TSI_GENCS_STM_MASK) 11860 #define TSI_GENCS_STPE_MASK (0x20U) 11861 #define TSI_GENCS_STPE_SHIFT (5U) 11862 /*! STPE - TSI STOP Enable 11863 * 0b0..TSI is disabled when MCU goes into low power mode. 11864 * 0b1..Allows TSI to continue running in all low power modes. 11865 */ 11866 #define TSI_GENCS_STPE(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_STPE_SHIFT)) & TSI_GENCS_STPE_MASK) 11867 #define TSI_GENCS_TSIIEN_MASK (0x40U) 11868 #define TSI_GENCS_TSIIEN_SHIFT (6U) 11869 /*! TSIIEN - Touch Sensing Input Interrupt Enable 11870 * 0b0..TSI interrupt is disabled. 11871 * 0b1..TSI interrupt is enabled. 11872 */ 11873 #define TSI_GENCS_TSIIEN(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_TSIIEN_SHIFT)) & TSI_GENCS_TSIIEN_MASK) 11874 #define TSI_GENCS_TSIEN_MASK (0x80U) 11875 #define TSI_GENCS_TSIEN_SHIFT (7U) 11876 /*! TSIEN - Touch Sensing Input Module Enable 11877 * 0b0..TSI module disabled. 11878 * 0b1..TSI module enabled. 11879 */ 11880 #define TSI_GENCS_TSIEN(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_TSIEN_SHIFT)) & TSI_GENCS_TSIEN_MASK) 11881 #define TSI_GENCS_CLKSOC_SEL_MASK (0x800U) 11882 #define TSI_GENCS_CLKSOC_SEL_SHIFT (11U) 11883 /*! CLKSOC_SEL - CLKSOC_SEL 11884 */ 11885 #define TSI_GENCS_CLKSOC_SEL(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_CLKSOC_SEL_SHIFT)) & TSI_GENCS_CLKSOC_SEL_MASK) 11886 #define TSI_GENCS_RUN_CTRL_MASK (0x1000U) 11887 #define TSI_GENCS_RUN_CTRL_SHIFT (12U) 11888 /*! RUN_CTRL - RUN_CTRL 11889 */ 11890 #define TSI_GENCS_RUN_CTRL(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_RUN_CTRL_SHIFT)) & TSI_GENCS_RUN_CTRL_MASK) 11891 #define TSI_GENCS_TSI_ANA_TEST_MASK (0xE000U) 11892 #define TSI_GENCS_TSI_ANA_TEST_SHIFT (13U) 11893 /*! TSI_ANA_TEST - TSI_ANA_TEST 11894 */ 11895 #define TSI_GENCS_TSI_ANA_TEST(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_TSI_ANA_TEST_SHIFT)) & TSI_GENCS_TSI_ANA_TEST_MASK) 11896 #define TSI_GENCS_DVOLT_MASK (0x180000U) 11897 #define TSI_GENCS_DVOLT_SHIFT (19U) 11898 /*! DVOLT - DVOLT 11899 * 0b00..Vm=0.3V; Vp=1.3V; dvolt=1.0V. 11900 * 0b01..Vm=0.3V; Vp=1.6V; dvolt=1.3V. 11901 * 0b10..Vm=0.3V; Vp=1.9V; dvolt=1.6V. 11902 * 0b11..Vm=0.3V; Vp=2.3V; dvolt=2.0V. 11903 */ 11904 #define TSI_GENCS_DVOLT(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_DVOLT_SHIFT)) & TSI_GENCS_DVOLT_MASK) 11905 #define TSI_GENCS_ESOR_MASK (0x10000000U) 11906 #define TSI_GENCS_ESOR_SHIFT (28U) 11907 /*! ESOR - End-of-scan or Out-of-Range Interrupt Selection 11908 * 0b0..Out-of-range interrupt is allowed. 11909 * 0b1..End-of-scan interrupt is allowed. 11910 */ 11911 #define TSI_GENCS_ESOR(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_ESOR_SHIFT)) & TSI_GENCS_ESOR_MASK) 11912 #define TSI_GENCS_OUTRGF_MASK (0x80000000U) 11913 #define TSI_GENCS_OUTRGF_SHIFT (31U) 11914 /*! OUTRGF - Out of Range Flag. 11915 */ 11916 #define TSI_GENCS_OUTRGF(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_OUTRGF_SHIFT)) & TSI_GENCS_OUTRGF_MASK) 11917 /*! @} */ 11918 11919 /*! @name DATA - TSI DATA Register */ 11920 /*! @{ */ 11921 #define TSI_DATA_TSICNT_MASK (0xFFFFU) 11922 #define TSI_DATA_TSICNT_SHIFT (0U) 11923 /*! TSICNT - TSI Conversion Counter Value 11924 */ 11925 #define TSI_DATA_TSICNT(x) (((uint32_t)(((uint32_t)(x)) << TSI_DATA_TSICNT_SHIFT)) & TSI_DATA_TSICNT_MASK) 11926 #define TSI_DATA_SWTS_MASK (0x400000U) 11927 #define TSI_DATA_SWTS_SHIFT (22U) 11928 /*! SWTS - Software Trigger Start 11929 * 0b0..No effect. 11930 * 0b1..Start a scan to determine which channel is specified by TSI_DATA[TSICH]. 11931 */ 11932 #define TSI_DATA_SWTS(x) (((uint32_t)(((uint32_t)(x)) << TSI_DATA_SWTS_SHIFT)) & TSI_DATA_SWTS_MASK) 11933 #define TSI_DATA_DMAEN_MASK (0x800000U) 11934 #define TSI_DATA_DMAEN_SHIFT (23U) 11935 /*! DMAEN - DMA Transfer Enabled 11936 * 0b0..Interrupt is selected when the interrupt enable bit is set and the corresponding TSI events assert. 11937 * 0b1..DMA transfer request is selected when the interrupt enable bit is set and the corresponding TSI events assert. 11938 */ 11939 #define TSI_DATA_DMAEN(x) (((uint32_t)(((uint32_t)(x)) << TSI_DATA_DMAEN_SHIFT)) & TSI_DATA_DMAEN_MASK) 11940 #define TSI_DATA_TSICH_MASK (0xF8000000U) 11941 #define TSI_DATA_TSICH_SHIFT (27U) 11942 /*! TSICH - TSICH 11943 * 0b00000..For self-cap mode: Channel 0. 11944 * 0b00001..For self-cap mode: Channel 1. 11945 * 0b00010..For self-cap mode: Channel 2. 11946 * 0b00011..For self-cap mode: Channel 3. 11947 * 0b00100..For self-cap mode: Channel 4. 11948 * 0b00101..For self-cap mode: Channel 5. 11949 * 0b00110..For self-cap mode: Channel 6. 11950 * 0b00111..For self-cap mode: Channel 7. 11951 * 0b01000..For self-cap mode: Channel 8. 11952 * 0b01001..For self-cap mode: Channel 9. 11953 * 0b01010..For self-cap mode: Channel 10. 11954 * 0b01011..For self-cap mode: Channel 11. 11955 * 0b01100..For self-cap mode: Channel 12. 11956 * 0b01101..For self-cap mode: Channel 13. 11957 * 0b01110..For self-cap mode: Channel 14. 11958 * 0b01111..For self-cap mode: Channel 15. 11959 * 0b10000..For self-cap mode: Channel 16. 11960 * 0b10001..For self-cap mode: Channel 17. 11961 * 0b10010..For self-cap mode: Channel 18. 11962 * 0b10011..For self-cap mode: Channel 19. 11963 * 0b10100..For self-cap mode: Channel 20. 11964 * 0b10101..For self-cap mode: Channel 21. 11965 * 0b10110..For self-cap mode: Channel 22. 11966 * 0b10111..For self-cap mode: Channel 23. 11967 * 0b11000..For self-cap mode: Channel 24. 11968 */ 11969 #define TSI_DATA_TSICH(x) (((uint32_t)(((uint32_t)(x)) << TSI_DATA_TSICH_SHIFT)) & TSI_DATA_TSICH_MASK) 11970 /*! @} */ 11971 11972 /*! @name TSHD - TSI Threshold Register */ 11973 /*! @{ */ 11974 #define TSI_TSHD_THRESL_MASK (0xFFFFU) 11975 #define TSI_TSHD_THRESL_SHIFT (0U) 11976 /*! THRESL - TSI Wakeup Channel Low-threshold 11977 */ 11978 #define TSI_TSHD_THRESL(x) (((uint32_t)(((uint32_t)(x)) << TSI_TSHD_THRESL_SHIFT)) & TSI_TSHD_THRESL_MASK) 11979 #define TSI_TSHD_THRESH_MASK (0xFFFF0000U) 11980 #define TSI_TSHD_THRESH_SHIFT (16U) 11981 /*! THRESH - TSI Wakeup Channel High-threshold 11982 */ 11983 #define TSI_TSHD_THRESH(x) (((uint32_t)(((uint32_t)(x)) << TSI_TSHD_THRESH_SHIFT)) & TSI_TSHD_THRESH_MASK) 11984 /*! @} */ 11985 11986 /*! @name MODE - TSI MODE Register */ 11987 /*! @{ */ 11988 #define TSI_MODE_S_NOISE_MASK (0x1U) 11989 #define TSI_MODE_S_NOISE_SHIFT (0U) 11990 /*! S_NOISE - S_NOISE 11991 * 0b0..noise cancellation off. 11992 * 0b1..noise cancellation on. 11993 */ 11994 #define TSI_MODE_S_NOISE(x) (((uint32_t)(((uint32_t)(x)) << TSI_MODE_S_NOISE_SHIFT)) & TSI_MODE_S_NOISE_MASK) 11995 #define TSI_MODE_MODE_MASK (0x2U) 11996 #define TSI_MODE_MODE_SHIFT (1U) 11997 /*! MODE - MODE 11998 * 0b0..self-cap mode. 11999 * 0b1..mutual-cap mode. 12000 */ 12001 #define TSI_MODE_MODE(x) (((uint32_t)(((uint32_t)(x)) << TSI_MODE_MODE_SHIFT)) & TSI_MODE_MODE_MASK) 12002 #define TSI_MODE_SETCLK_MASK (0x60U) 12003 #define TSI_MODE_SETCLK_SHIFT (5U) 12004 /*! SETCLK - SETCLK 12005 * 0b00..20.72MHz. 12006 * 0b01..16.65MHz. 12007 * 0b10..13.87MHz. 12008 * 0b11..11.91MHz. 12009 */ 12010 #define TSI_MODE_SETCLK(x) (((uint32_t)(((uint32_t)(x)) << TSI_MODE_SETCLK_SHIFT)) & TSI_MODE_SETCLK_MASK) 12011 #define TSI_MODE_S_XCH_MASK (0x7000U) 12012 #define TSI_MODE_S_XCH_SHIFT (12U) 12013 /*! S_XCH - S_XCH 12014 * 0b000..1/16. 12015 * 0b001..1/8. 12016 * 0b010..1/4. 12017 * 0b011..1/2. 12018 * 0b100..NA. 12019 * 0b101..NA. 12020 * 0b110..NA. 12021 * 0b111..NA. 12022 */ 12023 #define TSI_MODE_S_XCH(x) (((uint32_t)(((uint32_t)(x)) << TSI_MODE_S_XCH_SHIFT)) & TSI_MODE_S_XCH_MASK) 12024 #define TSI_MODE_S_XIN_MASK (0x40000U) 12025 #define TSI_MODE_S_XIN_SHIFT (18U) 12026 /*! S_XIN - S_XIN 12027 * 0b0..1/8. 12028 * 0b1..1/4. 12029 */ 12030 #define TSI_MODE_S_XIN(x) (((uint32_t)(((uint32_t)(x)) << TSI_MODE_S_XIN_SHIFT)) & TSI_MODE_S_XIN_MASK) 12031 #define TSI_MODE_S_CTRIM_MASK (0x380000U) 12032 #define TSI_MODE_S_CTRIM_SHIFT (19U) 12033 /*! S_CTRIM - Capacitor trim setting 12034 * 0b000..Ctrim=2.5p. 12035 * 0b001..Ctrim=5.0p. 12036 * 0b010..Ctrim=7.5p. 12037 * 0b011..Ctrim=10p. 12038 * 0b100..Ctrim=12.5p. 12039 * 0b101..Ctrim=15p. 12040 * 0b110..Ctrim=17.5p. 12041 * 0b111..Ctrim=20p. 12042 */ 12043 #define TSI_MODE_S_CTRIM(x) (((uint32_t)(((uint32_t)(x)) << TSI_MODE_S_CTRIM_SHIFT)) & TSI_MODE_S_CTRIM_MASK) 12044 #define TSI_MODE_S_SEN_MASK (0x400000U) 12045 #define TSI_MODE_S_SEN_SHIFT (22U) 12046 /*! S_SEN - S_SEN 12047 * 0b0..Sensitivity boost off. 12048 * 0b1..Sensitivity boost on. 12049 */ 12050 #define TSI_MODE_S_SEN(x) (((uint32_t)(((uint32_t)(x)) << TSI_MODE_S_SEN_SHIFT)) & TSI_MODE_S_SEN_MASK) 12051 #define TSI_MODE_S_W_SHIELD_MASK (0x800000U) 12052 #define TSI_MODE_S_W_SHIELD_SHIFT (23U) 12053 /*! S_W_SHIELD - S_W_SHIELD 12054 * 0b0..shield switch off. 12055 * 0b1..shield switch on. 12056 */ 12057 #define TSI_MODE_S_W_SHIELD(x) (((uint32_t)(((uint32_t)(x)) << TSI_MODE_S_W_SHIELD_SHIFT)) & TSI_MODE_S_W_SHIELD_MASK) 12058 #define TSI_MODE_S_XDN_MASK (0x70000000U) 12059 #define TSI_MODE_S_XDN_SHIFT (28U) 12060 /*! S_XDN - S_XDN 12061 * 0b000..1/16. 12062 * 0b001..1/8. 12063 * 0b010..1/4. 12064 * 0b011..1/2. 12065 * 0b100..NA. 12066 * 0b101..NA. 12067 * 0b110..NA. 12068 * 0b111..NA. 12069 */ 12070 #define TSI_MODE_S_XDN(x) (((uint32_t)(((uint32_t)(x)) << TSI_MODE_S_XDN_SHIFT)) & TSI_MODE_S_XDN_MASK) 12071 /*! @} */ 12072 12073 /*! @name MUL0 - TSI MUTUAL-CAP Register 0 */ 12074 /*! @{ */ 12075 #define TSI_MUL0_M_SEL_RX_MASK (0x7U) 12076 #define TSI_MUL0_M_SEL_RX_SHIFT (0U) 12077 /*! M_SEL_RX - M_SEL_RX 12078 * 0b000..select channel 6 as rx6. 12079 * 0b001..select channel 7 as rx7. 12080 * 0b010..select channel 8 as rx8. 12081 * 0b011..select channel 9 as rx9. 12082 * 0b100..select channel 10 as rx10. 12083 * 0b101..select channel 11 as rx11. 12084 * 0b110..NA. 12085 * 0b111..NA. 12086 */ 12087 #define TSI_MUL0_M_SEL_RX(x) (((uint32_t)(((uint32_t)(x)) << TSI_MUL0_M_SEL_RX_SHIFT)) & TSI_MUL0_M_SEL_RX_MASK) 12088 #define TSI_MUL0_M_SEL_TX_MASK (0x70U) 12089 #define TSI_MUL0_M_SEL_TX_SHIFT (4U) 12090 /*! M_SEL_TX - M_SEL_TX 12091 * 0b000..select channel 0 as tx0. 12092 * 0b001..select channel 1 as tx1. 12093 * 0b010..select channel 2 as tx2. 12094 * 0b011..select channel 3 as tx3. 12095 * 0b100..select channel 4 as tx4. 12096 * 0b101..select channel 5 as tx5. 12097 * 0b110..NA. 12098 * 0b111..NA. 12099 */ 12100 #define TSI_MUL0_M_SEL_TX(x) (((uint32_t)(((uint32_t)(x)) << TSI_MUL0_M_SEL_TX_SHIFT)) & TSI_MUL0_M_SEL_TX_MASK) 12101 #define TSI_MUL0_M_SEN_RES_MASK (0xF00U) 12102 #define TSI_MUL0_M_SEN_RES_SHIFT (8U) 12103 /*! M_SEN_RES - M_SEN_RES 12104 * 0b0000..2.5k. 12105 * 0b0001..5k. 12106 * 0b0010..7.5k. 12107 * 0b0011..10k. 12108 * 0b0100..12.5k. 12109 * 0b0101..15k. 12110 * 0b0110..17.5k. 12111 * 0b0111..20k. 12112 * 0b1000..22.5k. 12113 * 0b1001..25k. 12114 * 0b1010..27.5k. 12115 * 0b1011..30k. 12116 * 0b1100..32.5k. 12117 * 0b1101..35k. 12118 * 0b1110..37.5k. 12119 * 0b1111..40k. 12120 */ 12121 #define TSI_MUL0_M_SEN_RES(x) (((uint32_t)(((uint32_t)(x)) << TSI_MUL0_M_SEN_RES_SHIFT)) & TSI_MUL0_M_SEN_RES_MASK) 12122 #define TSI_MUL0_M_PRE_RES_MASK (0xE000U) 12123 #define TSI_MUL0_M_PRE_RES_SHIFT (13U) 12124 /*! M_PRE_RES - M_PRE_RES 12125 * 0b000..1k. 12126 * 0b001..2k. 12127 * 0b010..3k. 12128 * 0b011..4k. 12129 * 0b100..5k. 12130 * 0b101..6k. 12131 * 0b110..7k. 12132 * 0b111..8k. 12133 */ 12134 #define TSI_MUL0_M_PRE_RES(x) (((uint32_t)(((uint32_t)(x)) << TSI_MUL0_M_PRE_RES_SHIFT)) & TSI_MUL0_M_PRE_RES_MASK) 12135 #define TSI_MUL0_M_TX_USED_MASK (0x3F0000U) 12136 #define TSI_MUL0_M_TX_USED_SHIFT (16U) 12137 /*! M_TX_USED - M_TX_USED 12138 */ 12139 #define TSI_MUL0_M_TX_USED(x) (((uint32_t)(((uint32_t)(x)) << TSI_MUL0_M_TX_USED_SHIFT)) & TSI_MUL0_M_TX_USED_MASK) 12140 #define TSI_MUL0_M_PRE_CURRENT_MASK (0xE0000000U) 12141 #define TSI_MUL0_M_PRE_CURRENT_SHIFT (29U) 12142 /*! M_PRE_CURRENT - M_PRE_CURRENT 12143 * 0b000..1uA. 12144 * 0b001..2uA. 12145 * 0b010..3uA. 12146 * 0b011..4uA. 12147 * 0b100..5uA. 12148 * 0b101..6uA. 12149 * 0b110..7uA. 12150 * 0b111..8uA. 12151 */ 12152 #define TSI_MUL0_M_PRE_CURRENT(x) (((uint32_t)(((uint32_t)(x)) << TSI_MUL0_M_PRE_CURRENT_SHIFT)) & TSI_MUL0_M_PRE_CURRENT_MASK) 12153 /*! @} */ 12154 12155 /*! @name MUL1 - TSI MUTUAL-CAP Register 1 */ 12156 /*! @{ */ 12157 #define TSI_MUL1_M_NMIR_CTRL_MASK (0x1U) 12158 #define TSI_MUL1_M_NMIR_CTRL_SHIFT (0U) 12159 /*! M_NMIR_CTRL - M_NMIR_CTRL 12160 * 0b0..Enable NMOS mirror. 12161 * 0b1..Disable NMOS mirror. 12162 */ 12163 #define TSI_MUL1_M_NMIR_CTRL(x) (((uint32_t)(((uint32_t)(x)) << TSI_MUL1_M_NMIR_CTRL_SHIFT)) & TSI_MUL1_M_NMIR_CTRL_MASK) 12164 #define TSI_MUL1_M_NMIRROR_MASK (0x6U) 12165 #define TSI_MUL1_M_NMIRROR_SHIFT (1U) 12166 /*! M_NMIRROR - M_NMIRROR 12167 * 0b00..m=1. 12168 * 0b01..m=2. 12169 * 0b10..m=3. 12170 * 0b11..m=4. 12171 */ 12172 #define TSI_MUL1_M_NMIRROR(x) (((uint32_t)(((uint32_t)(x)) << TSI_MUL1_M_NMIRROR_SHIFT)) & TSI_MUL1_M_NMIRROR_MASK) 12173 #define TSI_MUL1_M_PMIRRORR_MASK (0x18U) 12174 #define TSI_MUL1_M_PMIRRORR_SHIFT (3U) 12175 /*! M_PMIRRORR - M_PMIRRORR 12176 * 0b00..m=1. 12177 * 0b01..m=2. 12178 * 0b10..m=3. 12179 * 0b11..m=4. 12180 */ 12181 #define TSI_MUL1_M_PMIRRORR(x) (((uint32_t)(((uint32_t)(x)) << TSI_MUL1_M_PMIRRORR_SHIFT)) & TSI_MUL1_M_PMIRRORR_MASK) 12182 #define TSI_MUL1_M_PMIRRORL_MASK (0xE0U) 12183 #define TSI_MUL1_M_PMIRRORL_SHIFT (5U) 12184 /*! M_PMIRRORL - M_PMIRRORL 12185 * 0b000..m=4. 12186 * 0b001..m=8. 12187 * 0b010..m=12. 12188 * 0b011..m=16. 12189 * 0b100..m=20. 12190 * 0b101..m=24. 12191 * 0b110..m=28. 12192 * 0b111..m=32. 12193 */ 12194 #define TSI_MUL1_M_PMIRRORL(x) (((uint32_t)(((uint32_t)(x)) << TSI_MUL1_M_PMIRRORL_SHIFT)) & TSI_MUL1_M_PMIRRORL_MASK) 12195 #define TSI_MUL1_M_TRIM2_MASK (0xFF00U) 12196 #define TSI_MUL1_M_TRIM2_SHIFT (8U) 12197 /*! M_TRIM2 - M_TRIM2 12198 */ 12199 #define TSI_MUL1_M_TRIM2(x) (((uint32_t)(((uint32_t)(x)) << TSI_MUL1_M_TRIM2_SHIFT)) & TSI_MUL1_M_TRIM2_MASK) 12200 #define TSI_MUL1_M_VPRE_CHOOSE_MASK (0x10000U) 12201 #define TSI_MUL1_M_VPRE_CHOOSE_SHIFT (16U) 12202 /*! M_VPRE_CHOOSE - M_VPRE_CHOOSE 12203 * 0b0..Internal 1.2V voltage. 12204 * 0b1..1.2V PMC output. 12205 */ 12206 #define TSI_MUL1_M_VPRE_CHOOSE(x) (((uint32_t)(((uint32_t)(x)) << TSI_MUL1_M_VPRE_CHOOSE_SHIFT)) & TSI_MUL1_M_VPRE_CHOOSE_MASK) 12207 #define TSI_MUL1_M_MODE_MASK (0x40000U) 12208 #define TSI_MUL1_M_MODE_SHIFT (18U) 12209 /*! M_MODE - M_MODE 12210 * 0b0..-5V~+5V. 12211 * 0b1..0V~+5V. 12212 */ 12213 #define TSI_MUL1_M_MODE(x) (((uint32_t)(((uint32_t)(x)) << TSI_MUL1_M_MODE_SHIFT)) & TSI_MUL1_M_MODE_MASK) 12214 #define TSI_MUL1_M_SEN_BOOST_MASK (0xF80000U) 12215 #define TSI_MUL1_M_SEN_BOOST_SHIFT (19U) 12216 /*! M_SEN_BOOST - M_SEN_BOOST 12217 * 0b00000..0u. 12218 * 0b00001..2u. 12219 * 0b00010..4u. 12220 * 0b00011..6u. 12221 * 0b00100..8u. 12222 * 0b00101..10u. 12223 * 0b00110..12u. 12224 * 0b00111..14u 12225 * 0b01000..16u. 12226 * 0b01001..18u. 12227 * 0b01010..20u. 12228 * 0b01011..22u. 12229 * 0b01100..24u. 12230 * 0b01101..26u. 12231 * 0b01110..28u. 12232 * 0b01111..30u. 12233 * 0b10000..32u. 12234 * 0b10001..34u. 12235 * 0b10010..36u. 12236 * 0b10011..38u. 12237 * 0b10100..40u. 12238 * 0b10101..42u. 12239 * 0b10110..44u. 12240 * 0b10111..46u. 12241 * 0b11000..48u. 12242 * 0b11001..50u. 12243 * 0b11010..52u. 12244 * 0b11011..54u. 12245 * 0b11100..56u. 12246 * 0b11101..58u. 12247 * 0b11110..60u. 12248 * 0b11111..62u. 12249 */ 12250 #define TSI_MUL1_M_SEN_BOOST(x) (((uint32_t)(((uint32_t)(x)) << TSI_MUL1_M_SEN_BOOST_SHIFT)) & TSI_MUL1_M_SEN_BOOST_MASK) 12251 /*! @} */ 12252 12253 /*! @name SINC - TSI SINC filter Register */ 12254 /*! @{ */ 12255 #define TSI_SINC_SSC_CONTROL_OUT_MASK (0x1U) 12256 #define TSI_SINC_SSC_CONTROL_OUT_SHIFT (0U) 12257 /*! SSC_CONTROL_OUT - SSC_CONTROL_OUT 12258 * 0b0..SSC output value is 0. 12259 * 0b1..SSC output value is 1. 12260 */ 12261 #define TSI_SINC_SSC_CONTROL_OUT(x) (((uint32_t)(((uint32_t)(x)) << TSI_SINC_SSC_CONTROL_OUT_SHIFT)) & TSI_SINC_SSC_CONTROL_OUT_MASK) 12262 #define TSI_SINC_SINC_VALID_MASK (0x2U) 12263 #define TSI_SINC_SINC_VALID_SHIFT (1U) 12264 /*! SINC_VALID - SINC_VALID 12265 * 0b0..SINC filter is disabled. 12266 * 0b1..SINC filter is enabled. 12267 */ 12268 #define TSI_SINC_SINC_VALID(x) (((uint32_t)(((uint32_t)(x)) << TSI_SINC_SINC_VALID_SHIFT)) & TSI_SINC_SINC_VALID_MASK) 12269 #define TSI_SINC_SINC_OVERFLOW_FLAG_MASK (0x4U) 12270 #define TSI_SINC_SINC_OVERFLOW_FLAG_SHIFT (2U) 12271 /*! SINC_OVERFLOW_FLAG - SINC_OVERFLOW_FLAG 12272 * 0b0..The counter result has no overflow occurrence in the last scan process. 12273 * 0b1..The counter result has an overflow occurrence in the last scan process. 12274 */ 12275 #define TSI_SINC_SINC_OVERFLOW_FLAG(x) (((uint32_t)(((uint32_t)(x)) << TSI_SINC_SINC_OVERFLOW_FLAG_SHIFT)) & TSI_SINC_SINC_OVERFLOW_FLAG_MASK) 12276 #define TSI_SINC_SWITCH_ENABLE_MASK (0x8U) 12277 #define TSI_SINC_SWITCH_ENABLE_SHIFT (3U) 12278 /*! SWITCH_ENABLE - SWITCH_ENABLE 12279 * 0b0..SSC function is disabled. 12280 * 0b1..SSC function is enabled. 12281 */ 12282 #define TSI_SINC_SWITCH_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << TSI_SINC_SWITCH_ENABLE_SHIFT)) & TSI_SINC_SWITCH_ENABLE_MASK) 12283 #define TSI_SINC_DECIMATION_MASK (0x1F0000U) 12284 #define TSI_SINC_DECIMATION_SHIFT (16U) 12285 /*! DECIMATION - DECIMATION 12286 * 0b00000..The TSI_DATA[TSICNT] bits is the counter value of 1 scan period. 12287 * 0b00001..The TSI_DATA[TSICNT] bits is the counter value of 2 scan periods. 12288 * 0b00010..The TSI_DATA[TSICNT] bits is the counter value of 3 scan periods. 12289 * 0b00011..The TSI_DATA[TSICNT] bits is the counter value of 4 scan periods. 12290 * 0b00100..The TSI_DATA[TSICNT] bits is the counter value of 5 scan periods. 12291 * 0b00101..The TSI_DATA[TSICNT] bits is the counter value of 6 scan periods. 12292 * 0b00110..The TSI_DATA[TSICNT] bits is the counter value of 7 scan periods. 12293 * 0b00111..The TSI_DATA[TSICNT] bits is the counter value of 8 scan periods. 12294 * 0b01000..The TSI_DATA[TSICNT] bits is the counter value of 9 scan periods. 12295 * 0b01001..The TSI_DATA[TSICNT] bits is the counter value of 10 scan periods. 12296 * 0b01010..The TSI_DATA[TSICNT] bits is the counter value of 11 scan periods. 12297 * 0b01011..The TSI_DATA[TSICNT] bits is the counter value of 12 scan periods. 12298 * 0b01100..The TSI_DATA[TSICNT] bits is the counter value of 13 scan periods. 12299 * 0b01101..The TSI_DATA[TSICNT] bits is the counter value of 14 scan periods. 12300 * 0b01110..The TSI_DATA[TSICNT] bits is the counter value of 15 scan periods. 12301 * 0b01111..The TSI_DATA[TSICNT] bits is the counter value of 16 scan periods. 12302 * 0b10000..The TSI_DATA[TSICNT] bits is the counter value of 17 scan periods. 12303 * 0b10001..The TSI_DATA[TSICNT] bits is the counter value of 18 scan periods. 12304 * 0b10010..The TSI_DATA[TSICNT] bits is the counter value of 19 scan periods. 12305 * 0b10011..The TSI_DATA[TSICNT] bits is the counter value of 20 scan periods. 12306 * 0b10100..The TSI_DATA[TSICNT] bits is the counter value of 21 scan periods. 12307 * 0b10101..The TSI_DATA[TSICNT] bits is the counter value of 22 scan periods. 12308 * 0b10110..The TSI_DATA[TSICNT] bits is the counter value of 23 scan periods. 12309 * 0b10111..The TSI_DATA[TSICNT] bits is the counter value of 24 scan periods. 12310 * 0b11000..The TSI_DATA[TSICNT] bits is the counter value of 25 scan periods. 12311 * 0b11001..The TSI_DATA[TSICNT] bits is the counter value of 26 scan periods. 12312 * 0b11010..The TSI_DATA[TSICNT] bits is the counter value of 27 scan periods. 12313 * 0b11011..The TSI_DATA[TSICNT] bits is the counter value of 28 scan periods. 12314 * 0b11100..The TSI_DATA[TSICNT] bits is the counter value of 29 scan periods. 12315 * 0b11101..The TSI_DATA[TSICNT] bits is the counter value of 30 scan periods. 12316 * 0b11110..The TSI_DATA[TSICNT] bits is the counter value of 31 scan periods. 12317 * 0b11111..The TSI_DATA[TSICNT] bits is the counter value of 32 scan periods. 12318 */ 12319 #define TSI_SINC_DECIMATION(x) (((uint32_t)(((uint32_t)(x)) << TSI_SINC_DECIMATION_SHIFT)) & TSI_SINC_DECIMATION_MASK) 12320 #define TSI_SINC_ORDER_MASK (0x200000U) 12321 #define TSI_SINC_ORDER_SHIFT (21U) 12322 /*! ORDER - ORDER 12323 * 0b0..Using 1 order SINC filter. 12324 * 0b1..Using 2 order SINC filter. 12325 */ 12326 #define TSI_SINC_ORDER(x) (((uint32_t)(((uint32_t)(x)) << TSI_SINC_ORDER_SHIFT)) & TSI_SINC_ORDER_MASK) 12327 #define TSI_SINC_CUTOFF_MASK (0xF000000U) 12328 #define TSI_SINC_CUTOFF_SHIFT (24U) 12329 /*! CUTOFF - CUTOFF 12330 * 0b0000..div=1. 12331 * 0b0001..div=2. 12332 * 0b0010..div=4. 12333 * 0b0011..div=8. 12334 * 0b0100..div=16. 12335 * 0b0101..div=32. 12336 * 0b0110..div=64. 12337 * 0b0111..div=128. 12338 * 0b1000..NC. 12339 * 0b1001..NC. 12340 * 0b1010..NC. 12341 * 0b1011..NC. 12342 * 0b1100..NC. 12343 * 0b1101..NC 12344 * 0b1110..NC. 12345 * 0b1111..NC. 12346 */ 12347 #define TSI_SINC_CUTOFF(x) (((uint32_t)(((uint32_t)(x)) << TSI_SINC_CUTOFF_SHIFT)) & TSI_SINC_CUTOFF_MASK) 12348 /*! @} */ 12349 12350 /*! @name SSC0 - TSI SSC Register 0 */ 12351 /*! @{ */ 12352 #define TSI_SSC0_SSC_PRESCALE_NUM_MASK (0xFFU) 12353 #define TSI_SSC0_SSC_PRESCALE_NUM_SHIFT (0U) 12354 /*! SSC_PRESCALE_NUM - SSC_PRESCALE_NUM 12355 * 0b00000000..div1 12356 * 0b00000001..div2 12357 * 0b00000011..div4 12358 * 0b00000111..div8 12359 * 0b00001111..div16 12360 * 0b00011111..div32 12361 * 0b00111111..div64 12362 * 0b01111111..div128 12363 * 0b11111111..div256 12364 */ 12365 #define TSI_SSC0_SSC_PRESCALE_NUM(x) (((uint32_t)(((uint32_t)(x)) << TSI_SSC0_SSC_PRESCALE_NUM_SHIFT)) & TSI_SSC0_SSC_PRESCALE_NUM_MASK) 12366 #define TSI_SSC0_BASE_NOCHARGE_NUM_MASK (0xF0000U) 12367 #define TSI_SSC0_BASE_NOCHARGE_NUM_SHIFT (16U) 12368 /*! BASE_NOCHARGE_NUM - BASE_NOCHARGE_NUM 12369 * 0b0000..The SSC output bit 1's basic period will be 1 clock cycle of system clock. 12370 * 0b0001..The SSC output bit 1's basic period will be 2 clock cycles of system clock. 12371 * 0b0010..The SSC output bit 1's basic period will be 3 clock cycles of system clock. 12372 * 0b0011..The SSC output bit 1's basic period will be 4 clock cycles of system clock. 12373 * 0b0100..The SSC output bit 1's basic period will be 5 clock cycles of system clock. 12374 * 0b0101..The SSC output bit 1's basic period will be 6 clock cycles of system clock. 12375 * 0b0110..The SSC output bit 1's basic period will be 7 clock cycles of system clock. 12376 * 0b0111..The SSC output bit 1's basic period will be 8 clock cycles of system clock. 12377 * 0b1000..The SSC output bit 1's basic period will be 9 clock cycles of system clock. 12378 * 0b1001..The SSC output bit 1's basic period will be 10 clock cycles of system clock. 12379 * 0b1010..The SSC output bit 1's basic period will be 11 clock cycles of system clock. 12380 * 0b1011..The SSC output bit 1's basic period will be 12 clock cycles of system clock. 12381 * 0b1100..The SSC output bit 1's basic period will be 13 clock cycles of system clock. 12382 * 0b1101..The SSC output bit 1's basic period will be 14 clock cycles of system clock. 12383 * 0b1110..The SSC output bit 1's basic period will be 15 clock cycles of system clock. 12384 * 0b1111..The SSC output bit 1's basic period will be 16 clock cycles of system clock. 12385 */ 12386 #define TSI_SSC0_BASE_NOCHARGE_NUM(x) (((uint32_t)(((uint32_t)(x)) << TSI_SSC0_BASE_NOCHARGE_NUM_SHIFT)) & TSI_SSC0_BASE_NOCHARGE_NUM_MASK) 12387 #define TSI_SSC0_CHARGE_NUM_MASK (0xF00000U) 12388 #define TSI_SSC0_CHARGE_NUM_SHIFT (20U) 12389 /*! CHARGE_NUM - CHARGE_NUM 12390 * 0b0000..The SSC output bit 0's period will be 1 clock cycle of system clock. 12391 * 0b0001..The SSC output bit 0's period will be 2 clock cycles of system clock. 12392 * 0b0010..The SSC output bit 0's period will be 3 clock cycles of system clock. 12393 * 0b0011..The SSC output bit 0's period will be 4 clock cycles of system clock. 12394 * 0b0100..The SSC output bit 0's period will be 5 clock cycles of system clock. 12395 * 0b0101..The SSC output bit 0's period will be 6 clock cycles of system clock. 12396 * 0b0110..The SSC output bit 0's period will be 7 clock cycles of system clock. 12397 * 0b0111..The SSC output bit 0's period will be 8 clock cycles of system clock. 12398 * 0b1000..The SSC output bit 0's period will be 9 clock cycles of system clock. 12399 * 0b1001..The SSC output bit 0's period will be 10 clock cycles of system clock. 12400 * 0b1010..The SSC output bit 0's period will be 11 clock cycles of system clock. 12401 * 0b1011..The SSC output bit 0's period will be 12 clock cycles of system clock. 12402 * 0b1100..The SSC output bit 0's period will be 13 clock cycles of system clock. 12403 * 0b1101..The SSC output bit 0's period will be 14 clock cycles of system clock. 12404 * 0b1110..The SSC output bit 0's period will be 15 clock cycles of system clock. 12405 * 0b1111..The SSC output bit 0's period will be 16 clock cycles of system clock. 12406 */ 12407 #define TSI_SSC0_CHARGE_NUM(x) (((uint32_t)(((uint32_t)(x)) << TSI_SSC0_CHARGE_NUM_SHIFT)) & TSI_SSC0_CHARGE_NUM_MASK) 12408 #define TSI_SSC0_SSC_CONTROL_REVERSE_MASK (0x1000000U) 12409 #define TSI_SSC0_SSC_CONTROL_REVERSE_SHIFT (24U) 12410 /*! SSC_CONTROL_REVERSE - SSC_CONTROL_REVERSE 12411 * 0b0..Keep the polarity of the SSC output bit. 12412 * 0b1..Reverse the polarity of the SSC output bit. 12413 */ 12414 #define TSI_SSC0_SSC_CONTROL_REVERSE(x) (((uint32_t)(((uint32_t)(x)) << TSI_SSC0_SSC_CONTROL_REVERSE_SHIFT)) & TSI_SSC0_SSC_CONTROL_REVERSE_MASK) 12415 #define TSI_SSC0_SSC_MODE_MASK (0x6000000U) 12416 #define TSI_SSC0_SSC_MODE_SHIFT (25U) 12417 /*! SSC_MODE - SSC_MODE 12418 * 0b00..Using PRBS method generating SSC output bit. 12419 * 0b01..Using up-down counter generating SSC output bit. 12420 * 0b10..SSC function is disabled. 12421 * 0b11..NC. 12422 */ 12423 #define TSI_SSC0_SSC_MODE(x) (((uint32_t)(((uint32_t)(x)) << TSI_SSC0_SSC_MODE_SHIFT)) & TSI_SSC0_SSC_MODE_MASK) 12424 #define TSI_SSC0_PRBS_OUTSEL_MASK (0xF0000000U) 12425 #define TSI_SSC0_PRBS_OUTSEL_SHIFT (28U) 12426 /*! PRBS_OUTSEL - PRBS_OUTSEL 12427 * 0b0000..NC. 12428 * 0b0001..NC. 12429 * 0b0010..The length of the PRBS is 2. 12430 * 0b0011..The length of the PRBS is 3. 12431 * 0b0100..The length of the PRBS is 4. 12432 * 0b0101..The length of the PRBS is 5. 12433 * 0b0110..The length of the PRBS is 6. 12434 * 0b0111..The length of the PRBS is 7. 12435 * 0b1000..The length of the PRBS is 8. 12436 * 0b1001..The length of the PRBS is 9. 12437 * 0b1010..The length of the PRBS is 10. 12438 * 0b1011..The length of the PRBS is 11. 12439 * 0b1100..The length of the PRBS is 12. 12440 * 0b1101..The length of the PRBS is 13. 12441 * 0b1110..The length of the PRBS is 14. 12442 * 0b1111..The length of the PRBS is 15. 12443 */ 12444 #define TSI_SSC0_PRBS_OUTSEL(x) (((uint32_t)(((uint32_t)(x)) << TSI_SSC0_PRBS_OUTSEL_SHIFT)) & TSI_SSC0_PRBS_OUTSEL_MASK) 12445 /*! @} */ 12446 12447 /*! @name SSC1 - TSI SSC Register 1 */ 12448 /*! @{ */ 12449 #define TSI_SSC1_PRBS_SEED_LO_MASK (0xFFU) 12450 #define TSI_SSC1_PRBS_SEED_LO_SHIFT (0U) 12451 /*! PRBS_SEED_LO - PRBS_SEED_LO 12452 */ 12453 #define TSI_SSC1_PRBS_SEED_LO(x) (((uint32_t)(((uint32_t)(x)) << TSI_SSC1_PRBS_SEED_LO_SHIFT)) & TSI_SSC1_PRBS_SEED_LO_MASK) 12454 #define TSI_SSC1_PRBS_SEED_HI_MASK (0xFF00U) 12455 #define TSI_SSC1_PRBS_SEED_HI_SHIFT (8U) 12456 /*! PRBS_SEED_HI - PRBS_SEED_HI 12457 */ 12458 #define TSI_SSC1_PRBS_SEED_HI(x) (((uint32_t)(((uint32_t)(x)) << TSI_SSC1_PRBS_SEED_HI_SHIFT)) & TSI_SSC1_PRBS_SEED_HI_MASK) 12459 #define TSI_SSC1_PRBS_WEIGHT_LO_MASK (0xFF0000U) 12460 #define TSI_SSC1_PRBS_WEIGHT_LO_SHIFT (16U) 12461 /*! PRBS_WEIGHT_LO - PRBS_WEIGHT_LO 12462 */ 12463 #define TSI_SSC1_PRBS_WEIGHT_LO(x) (((uint32_t)(((uint32_t)(x)) << TSI_SSC1_PRBS_WEIGHT_LO_SHIFT)) & TSI_SSC1_PRBS_WEIGHT_LO_MASK) 12464 #define TSI_SSC1_PRBS_WEIGHT_HI_MASK (0xFF000000U) 12465 #define TSI_SSC1_PRBS_WEIGHT_HI_SHIFT (24U) 12466 /*! PRBS_WEIGHT_HI - PRBS_WEIGHT_HI 12467 */ 12468 #define TSI_SSC1_PRBS_WEIGHT_HI(x) (((uint32_t)(((uint32_t)(x)) << TSI_SSC1_PRBS_WEIGHT_HI_SHIFT)) & TSI_SSC1_PRBS_WEIGHT_HI_MASK) 12469 /*! @} */ 12470 12471 /*! @name SSC2 - TSI SSC Register 2 */ 12472 /*! @{ */ 12473 #define TSI_SSC2_MOVE_REPEAT_NUM_MASK (0x1FU) 12474 #define TSI_SSC2_MOVE_REPEAT_NUM_SHIFT (0U) 12475 /*! MOVE_REPEAT_NUM - MOVE_REPEAT_NUM 12476 * 0b00000..The up_down counter will be updated for every sample-charge cycle. 12477 * 0b00001..The up_down counter will be updated for every 2 sample-charge cycles. 12478 * 0b00010..The up_down counter will be updated for every 3 sample-charge cycles. 12479 * 0b00011..The up_down counter will be updated for every 4 sample-charge cycles. 12480 * 0b00100..The up_down counter will be updated for every 5 sample-charge cycles. 12481 * 0b00101..The up_down counter will be updated for every 6 sample-charge cycles. 12482 * 0b00110..The up_down counter will be updated for every 7 sample-charge cycles. 12483 */ 12484 #define TSI_SSC2_MOVE_REPEAT_NUM(x) (((uint32_t)(((uint32_t)(x)) << TSI_SSC2_MOVE_REPEAT_NUM_SHIFT)) & TSI_SSC2_MOVE_REPEAT_NUM_MASK) 12485 #define TSI_SSC2_MOVE_STEPS_NUM_MASK (0x700U) 12486 #define TSI_SSC2_MOVE_STEPS_NUM_SHIFT (8U) 12487 /*! MOVE_STEPS_NUM - MOVE_STEPS_NUM 12488 * 0b000..The added value for up-down counter is 0. 12489 * 0b001..The added value for up-down counter is 1. 12490 * 0b010..The added value for up-down counter is 2. 12491 * 0b011..The added value for up-down counter is 3. 12492 * 0b100..The added value for up-down counter is 4. 12493 * 0b101..The added value for up-down counter is 5. 12494 * 0b110..The added value for up-down counter is 6. 12495 * 0b111..The added value for up-down counter is 7. 12496 */ 12497 #define TSI_SSC2_MOVE_STEPS_NUM(x) (((uint32_t)(((uint32_t)(x)) << TSI_SSC2_MOVE_STEPS_NUM_SHIFT)) & TSI_SSC2_MOVE_STEPS_NUM_MASK) 12498 #define TSI_SSC2_MOVE_NOCHARGE_MAX_MASK (0x3F0000U) 12499 #define TSI_SSC2_MOVE_NOCHARGE_MAX_SHIFT (16U) 12500 /*! MOVE_NOCHARGE_MAX - MOVE_NOCHARGE_MAX 12501 */ 12502 #define TSI_SSC2_MOVE_NOCHARGE_MAX(x) (((uint32_t)(((uint32_t)(x)) << TSI_SSC2_MOVE_NOCHARGE_MAX_SHIFT)) & TSI_SSC2_MOVE_NOCHARGE_MAX_MASK) 12503 #define TSI_SSC2_MOVE_NOCHARGE_MIN_MASK (0xF0000000U) 12504 #define TSI_SSC2_MOVE_NOCHARGE_MIN_SHIFT (28U) 12505 /*! MOVE_NOCHARGE_MIN - MOVE_NOCHARGE_MIN 12506 * 0b0000..The SSC output bit 1's min period will be (1 + TSI_SSC0[BASE_ NOCHARGE_NUM]) clock cycle of divided system clock. 12507 * 0b0001..The SSC output bit 1's min period will be (2 + TSI_SSC0[BASE_ NOCHARGE_NUM]) clock cycles of divided system clock. 12508 * 0b0010..The SSC output bit 1's min period will be (3 + TSI_SSC0[BASE_ NOCHARGE_NUM]) clock cycles of divided system clock. 12509 * 0b0011..The SSC output bit 1's min period will be (4 + TSI_SSC0[BASE_ NOCHARGE_NUM]) clock cycles of divided system clock. 12510 * 0b0100..The SSC output bit 1's min period will be (5 + TSI_SSC0[BASE_ NOCHARGE_NUM]) clock cycles of divided system clock. 12511 * 0b0101..The SSC output bit 1's min period will be (6 + TSI_SSC0[BASE_ NOCHARGE_NUM]) clock cycles of divided system clock. 12512 * 0b0110..The SSC output bit 1's min period will be (7 + TSI_SSC0[BASE_ NOCHARGE_NUM]) clock cycles of divided system clock. 12513 * 0b0111..The SSC output bit 1's min period will be (8 + TSI_SSC0[BASE_ NOCHARGE_NUM]) clock cycles of divided system clock. 12514 * 0b1000..The SSC output bit 1's min period will be (9 + TSI_SSC0[BASE_ NOCHARGE_NUM]) clock cycles of divided system clock. 12515 * 0b1001..The SSC output bit 1's min period will be (10 + TSI_SSC0[BASE_ NOCHARGE_NUM]) clock cycles of divided system clock. 12516 * 0b1010..The SSC output bit 1's min period will be (11 + TSI_SSC0[BASE_ NOCHARGE_NUM]) clock cycles of divided system clock. 12517 * 0b1011..The SSC output bit 1's min period will be (12 + TSI_SSC0[BASE_ NOCHARGE_NUM]) clock cycles of divided system clock. 12518 * 0b1100..The SSC output bit 1's min period will be (13 + TSI_SSC0[BASE_ NOCHARGE_NUM]) clock cycles of divided system clock. 12519 * 0b1101..The SSC output bit 1's min period will be (14 + TSI_SSC0[BASE_ NOCHARGE_NUM]) clock cycles of divided system clock. 12520 * 0b1110..The SSC output bit 1's min period will be (15 + TSI_SSC0[BASE_ NOCHARGE_NUM]) clock cycles of divided system clock. 12521 * 0b1111..The SSC output bit 1's min period will be (16 + TSI_SSC0[BASE_ NOCHARGE_NUM]) clock cycles of divided system clock. 12522 */ 12523 #define TSI_SSC2_MOVE_NOCHARGE_MIN(x) (((uint32_t)(((uint32_t)(x)) << TSI_SSC2_MOVE_NOCHARGE_MIN_SHIFT)) & TSI_SSC2_MOVE_NOCHARGE_MIN_MASK) 12524 /*! @} */ 12525 12526 12527 /*! 12528 * @} 12529 */ /* end of group TSI_Register_Masks */ 12530 12531 12532 /* TSI - Peripheral instance base addresses */ 12533 /** Peripheral TSI base address */ 12534 #define TSI_BASE (0x40045000u) 12535 /** Peripheral TSI base pointer */ 12536 #define TSI ((TSI_Type *)TSI_BASE) 12537 /** Array initializer of TSI peripheral base addresses */ 12538 #define TSI_BASE_ADDRS { TSI_BASE } 12539 /** Array initializer of TSI peripheral base pointers */ 12540 #define TSI_BASE_PTRS { TSI } 12541 /** Interrupt vectors for the TSI peripheral type */ 12542 #define TSI_IRQS { TSI_IRQn } 12543 12544 /*! 12545 * @} 12546 */ /* end of group TSI_Peripheral_Access_Layer */ 12547 12548 12549 /* ---------------------------------------------------------------------------- 12550 -- WDOG Peripheral Access Layer 12551 ---------------------------------------------------------------------------- */ 12552 12553 /*! 12554 * @addtogroup WDOG_Peripheral_Access_Layer WDOG Peripheral Access Layer 12555 * @{ 12556 */ 12557 12558 /** WDOG - Register Layout Typedef */ 12559 typedef struct { 12560 __IO uint32_t CS; /**< Watchdog Control and Status Register, offset: 0x0 */ 12561 __IO uint32_t CNT; /**< Watchdog Counter Register, offset: 0x4 */ 12562 __IO uint32_t TOVAL; /**< Watchdog Timeout Value Register, offset: 0x8 */ 12563 __IO uint32_t WIN; /**< Watchdog Window Register, offset: 0xC */ 12564 } WDOG_Type; 12565 12566 /* ---------------------------------------------------------------------------- 12567 -- WDOG Register Masks 12568 ---------------------------------------------------------------------------- */ 12569 12570 /*! 12571 * @addtogroup WDOG_Register_Masks WDOG Register Masks 12572 * @{ 12573 */ 12574 12575 /*! @name CS - Watchdog Control and Status Register */ 12576 /*! @{ */ 12577 #define WDOG_CS_STOP_MASK (0x1U) 12578 #define WDOG_CS_STOP_SHIFT (0U) 12579 /*! STOP - Stop Enable 12580 * 0b0..Watchdog disabled in chip stop mode. 12581 * 0b1..Watchdog enabled in chip stop mode. 12582 */ 12583 #define WDOG_CS_STOP(x) (((uint32_t)(((uint32_t)(x)) << WDOG_CS_STOP_SHIFT)) & WDOG_CS_STOP_MASK) 12584 #define WDOG_CS_WAIT_MASK (0x2U) 12585 #define WDOG_CS_WAIT_SHIFT (1U) 12586 /*! WAIT - Wait Enable 12587 * 0b0..Watchdog disabled in chip wait mode. 12588 * 0b1..Watchdog enabled in chip wait mode. 12589 */ 12590 #define WDOG_CS_WAIT(x) (((uint32_t)(((uint32_t)(x)) << WDOG_CS_WAIT_SHIFT)) & WDOG_CS_WAIT_MASK) 12591 #define WDOG_CS_DBG_MASK (0x4U) 12592 #define WDOG_CS_DBG_SHIFT (2U) 12593 /*! DBG - Debug Enable 12594 * 0b0..Watchdog disabled in chip debug mode. 12595 * 0b1..Watchdog enabled in chip debug mode. 12596 */ 12597 #define WDOG_CS_DBG(x) (((uint32_t)(((uint32_t)(x)) << WDOG_CS_DBG_SHIFT)) & WDOG_CS_DBG_MASK) 12598 #define WDOG_CS_TST_MASK (0x18U) 12599 #define WDOG_CS_TST_SHIFT (3U) 12600 /*! TST - Watchdog Test 12601 * 0b00..Watchdog test mode disabled. 12602 * 0b01..Watchdog user mode enabled. (Watchdog test mode disabled.) After testing the watchdog, software should 12603 * use this setting to indicate that the watchdog is functioning normally in user mode. 12604 * 0b10..Watchdog test mode enabled, only the low byte is used. CNT[CNTLOW] is compared with TOVAL[TOVALLOW]. 12605 * 0b11..Watchdog test mode enabled, only the high byte is used. CNT[CNTHIGH] is compared with TOVAL[TOVALHIGH]. 12606 */ 12607 #define WDOG_CS_TST(x) (((uint32_t)(((uint32_t)(x)) << WDOG_CS_TST_SHIFT)) & WDOG_CS_TST_MASK) 12608 #define WDOG_CS_UPDATE_MASK (0x20U) 12609 #define WDOG_CS_UPDATE_SHIFT (5U) 12610 /*! UPDATE - Allow updates 12611 * 0b0..Updates not allowed. After the initial configuration, the watchdog cannot be later modified without forcing a reset. 12612 * 0b1..Updates allowed. Software can modify the watchdog configuration registers within 128 bus clocks after performing the unlock write sequence. 12613 */ 12614 #define WDOG_CS_UPDATE(x) (((uint32_t)(((uint32_t)(x)) << WDOG_CS_UPDATE_SHIFT)) & WDOG_CS_UPDATE_MASK) 12615 #define WDOG_CS_INT_MASK (0x40U) 12616 #define WDOG_CS_INT_SHIFT (6U) 12617 /*! INT - Watchdog Interrupt 12618 * 0b0..Watchdog interrupts are disabled. Watchdog resets are not delayed. 12619 * 0b1..Watchdog interrupts are enabled. Watchdog resets are delayed by 128 bus clocks from the interrupt vector fetch. 12620 */ 12621 #define WDOG_CS_INT(x) (((uint32_t)(((uint32_t)(x)) << WDOG_CS_INT_SHIFT)) & WDOG_CS_INT_MASK) 12622 #define WDOG_CS_EN_MASK (0x80U) 12623 #define WDOG_CS_EN_SHIFT (7U) 12624 /*! EN - Watchdog Enable 12625 * 0b0..Watchdog disabled. 12626 * 0b1..Watchdog enabled. 12627 */ 12628 #define WDOG_CS_EN(x) (((uint32_t)(((uint32_t)(x)) << WDOG_CS_EN_SHIFT)) & WDOG_CS_EN_MASK) 12629 #define WDOG_CS_CLK_MASK (0x300U) 12630 #define WDOG_CS_CLK_SHIFT (8U) 12631 /*! CLK - Watchdog Clock 12632 * 0b00..Bus clock 12633 * 0b01..LPO clock 12634 * 0b10..System oscillator clock (SOSC, from SCG) 12635 * 0b11..Slow internal reference clock (SIRC, from SCG) 12636 */ 12637 #define WDOG_CS_CLK(x) (((uint32_t)(((uint32_t)(x)) << WDOG_CS_CLK_SHIFT)) & WDOG_CS_CLK_MASK) 12638 #define WDOG_CS_RCS_MASK (0x400U) 12639 #define WDOG_CS_RCS_SHIFT (10U) 12640 /*! RCS - Reconfiguration Success 12641 * 0b0..Reconfiguring WDOG. 12642 * 0b1..Reconfiguration is successful. 12643 */ 12644 #define WDOG_CS_RCS(x) (((uint32_t)(((uint32_t)(x)) << WDOG_CS_RCS_SHIFT)) & WDOG_CS_RCS_MASK) 12645 #define WDOG_CS_ULK_MASK (0x800U) 12646 #define WDOG_CS_ULK_SHIFT (11U) 12647 /*! ULK - Unlock status 12648 * 0b0..WDOG is locked. 12649 * 0b1..WDOG is unlocked. 12650 */ 12651 #define WDOG_CS_ULK(x) (((uint32_t)(((uint32_t)(x)) << WDOG_CS_ULK_SHIFT)) & WDOG_CS_ULK_MASK) 12652 #define WDOG_CS_PRES_MASK (0x1000U) 12653 #define WDOG_CS_PRES_SHIFT (12U) 12654 /*! PRES - Watchdog prescaler 12655 * 0b0..256 prescaler disabled. 12656 * 0b1..256 prescaler enabled. 12657 */ 12658 #define WDOG_CS_PRES(x) (((uint32_t)(((uint32_t)(x)) << WDOG_CS_PRES_SHIFT)) & WDOG_CS_PRES_MASK) 12659 #define WDOG_CS_CMD32EN_MASK (0x2000U) 12660 #define WDOG_CS_CMD32EN_SHIFT (13U) 12661 /*! CMD32EN - Enables or disables WDOG support for 32-bit (otherwise 16-bit or 8-bit) refresh/unlock command write words 12662 * 0b0..Disables support for 32-bit refresh/unlock command write words. Only 16-bit or 8-bit is supported. 12663 * 0b1..Enables support for 32-bit refresh/unlock command write words. 16-bit or 8-bit is NOT supported. 12664 */ 12665 #define WDOG_CS_CMD32EN(x) (((uint32_t)(((uint32_t)(x)) << WDOG_CS_CMD32EN_SHIFT)) & WDOG_CS_CMD32EN_MASK) 12666 #define WDOG_CS_FLG_MASK (0x4000U) 12667 #define WDOG_CS_FLG_SHIFT (14U) 12668 /*! FLG - Watchdog Interrupt Flag 12669 * 0b0..No interrupt occurred. 12670 * 0b1..An interrupt occurred. 12671 */ 12672 #define WDOG_CS_FLG(x) (((uint32_t)(((uint32_t)(x)) << WDOG_CS_FLG_SHIFT)) & WDOG_CS_FLG_MASK) 12673 #define WDOG_CS_WIN_MASK (0x8000U) 12674 #define WDOG_CS_WIN_SHIFT (15U) 12675 /*! WIN - Watchdog Window 12676 * 0b0..Window mode disabled. 12677 * 0b1..Window mode enabled. 12678 */ 12679 #define WDOG_CS_WIN(x) (((uint32_t)(((uint32_t)(x)) << WDOG_CS_WIN_SHIFT)) & WDOG_CS_WIN_MASK) 12680 /*! @} */ 12681 12682 /*! @name CNT - Watchdog Counter Register */ 12683 /*! @{ */ 12684 #define WDOG_CNT_CNTLOW_MASK (0xFFU) 12685 #define WDOG_CNT_CNTLOW_SHIFT (0U) 12686 /*! CNTLOW - Low byte of the Watchdog Counter 12687 */ 12688 #define WDOG_CNT_CNTLOW(x) (((uint32_t)(((uint32_t)(x)) << WDOG_CNT_CNTLOW_SHIFT)) & WDOG_CNT_CNTLOW_MASK) 12689 #define WDOG_CNT_CNTHIGH_MASK (0xFF00U) 12690 #define WDOG_CNT_CNTHIGH_SHIFT (8U) 12691 /*! CNTHIGH - High byte of the Watchdog Counter 12692 */ 12693 #define WDOG_CNT_CNTHIGH(x) (((uint32_t)(((uint32_t)(x)) << WDOG_CNT_CNTHIGH_SHIFT)) & WDOG_CNT_CNTHIGH_MASK) 12694 /*! @} */ 12695 12696 /*! @name TOVAL - Watchdog Timeout Value Register */ 12697 /*! @{ */ 12698 #define WDOG_TOVAL_TOVALLOW_MASK (0xFFU) 12699 #define WDOG_TOVAL_TOVALLOW_SHIFT (0U) 12700 /*! TOVALLOW - Low byte of the timeout value 12701 */ 12702 #define WDOG_TOVAL_TOVALLOW(x) (((uint32_t)(((uint32_t)(x)) << WDOG_TOVAL_TOVALLOW_SHIFT)) & WDOG_TOVAL_TOVALLOW_MASK) 12703 #define WDOG_TOVAL_TOVALHIGH_MASK (0xFF00U) 12704 #define WDOG_TOVAL_TOVALHIGH_SHIFT (8U) 12705 /*! TOVALHIGH - High byte of the timeout value 12706 */ 12707 #define WDOG_TOVAL_TOVALHIGH(x) (((uint32_t)(((uint32_t)(x)) << WDOG_TOVAL_TOVALHIGH_SHIFT)) & WDOG_TOVAL_TOVALHIGH_MASK) 12708 /*! @} */ 12709 12710 /*! @name WIN - Watchdog Window Register */ 12711 /*! @{ */ 12712 #define WDOG_WIN_WINLOW_MASK (0xFFU) 12713 #define WDOG_WIN_WINLOW_SHIFT (0U) 12714 /*! WINLOW - Low byte of Watchdog Window 12715 */ 12716 #define WDOG_WIN_WINLOW(x) (((uint32_t)(((uint32_t)(x)) << WDOG_WIN_WINLOW_SHIFT)) & WDOG_WIN_WINLOW_MASK) 12717 #define WDOG_WIN_WINHIGH_MASK (0xFF00U) 12718 #define WDOG_WIN_WINHIGH_SHIFT (8U) 12719 /*! WINHIGH - High byte of Watchdog Window 12720 */ 12721 #define WDOG_WIN_WINHIGH(x) (((uint32_t)(((uint32_t)(x)) << WDOG_WIN_WINHIGH_SHIFT)) & WDOG_WIN_WINHIGH_MASK) 12722 /*! @} */ 12723 12724 12725 /*! 12726 * @} 12727 */ /* end of group WDOG_Register_Masks */ 12728 12729 12730 /* WDOG - Peripheral instance base addresses */ 12731 /** Peripheral WDOG base address */ 12732 #define WDOG_BASE (0x40052000u) 12733 /** Peripheral WDOG base pointer */ 12734 #define WDOG ((WDOG_Type *)WDOG_BASE) 12735 /** Array initializer of WDOG peripheral base addresses */ 12736 #define WDOG_BASE_ADDRS { WDOG_BASE } 12737 /** Array initializer of WDOG peripheral base pointers */ 12738 #define WDOG_BASE_PTRS { WDOG } 12739 /** Interrupt vectors for the WDOG peripheral type */ 12740 #define WDOG_IRQS { WDOG_EWM_IRQn } 12741 #define WDOG_UPDATE_KEY (0xD928C520U) 12742 #define WDOG_REFRESH_KEY (0xB480A602U) 12743 12744 12745 /*! 12746 * @} 12747 */ /* end of group WDOG_Peripheral_Access_Layer */ 12748 12749 12750 /* 12751 ** End of section using anonymous unions 12752 */ 12753 12754 #if defined(__ARMCC_VERSION) 12755 #if (__ARMCC_VERSION >= 6010050) 12756 #pragma clang diagnostic pop 12757 #else 12758 #pragma pop 12759 #endif 12760 #elif defined(__CWCC__) 12761 #pragma pop 12762 #elif defined(__GNUC__) 12763 /* leave anonymous unions enabled */ 12764 #elif defined(__IAR_SYSTEMS_ICC__) 12765 #pragma language=default 12766 #else 12767 #error Not supported compiler type 12768 #endif 12769 12770 /*! 12771 * @} 12772 */ /* end of group Peripheral_access_layer */ 12773 12774 12775 /* ---------------------------------------------------------------------------- 12776 -- Macros for use with bit field definitions (xxx_SHIFT, xxx_MASK). 12777 ---------------------------------------------------------------------------- */ 12778 12779 /*! 12780 * @addtogroup Bit_Field_Generic_Macros Macros for use with bit field definitions (xxx_SHIFT, xxx_MASK). 12781 * @{ 12782 */ 12783 12784 #if defined(__ARMCC_VERSION) 12785 #if (__ARMCC_VERSION >= 6010050) 12786 #pragma clang system_header 12787 #endif 12788 #elif defined(__IAR_SYSTEMS_ICC__) 12789 #pragma system_include 12790 #endif 12791 12792 /** 12793 * @brief Mask and left-shift a bit field value for use in a register bit range. 12794 * @param field Name of the register bit field. 12795 * @param value Value of the bit field. 12796 * @return Masked and shifted value. 12797 */ 12798 #define NXP_VAL2FLD(field, value) (((value) << (field ## _SHIFT)) & (field ## _MASK)) 12799 /** 12800 * @brief Mask and right-shift a register value to extract a bit field value. 12801 * @param field Name of the register bit field. 12802 * @param value Value of the register. 12803 * @return Masked and shifted bit field value. 12804 */ 12805 #define NXP_FLD2VAL(field, value) (((value) & (field ## _MASK)) >> (field ## _SHIFT)) 12806 12807 /*! 12808 * @} 12809 */ /* end of group Bit_Field_Generic_Macros */ 12810 12811 12812 /* ---------------------------------------------------------------------------- 12813 -- SDK Compatibility 12814 ---------------------------------------------------------------------------- */ 12815 12816 /*! 12817 * @addtogroup SDK_Compatibility_Symbols SDK Compatibility 12818 * @{ 12819 */ 12820 12821 /* No SDK compatibility issues. */ 12822 12823 /*! 12824 * @} 12825 */ /* end of group SDK_Compatibility_Symbols */ 12826 12827 12828 #endif /* _MKE16Z4_H_ */ 12829 12830
