1 /* 2 * Copyright 1997-2016 Freescale Semiconductor, Inc. 3 * Copyright 2016-2022 NXP 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 /*! 9 * @file S32K148_FTM.h 10 * @version 1.1 11 * @date 2022-02-02 12 * @brief Peripheral Access Layer for S32K148_FTM 13 * 14 * This file contains register definitions and macros for easy access to their 15 * bit fields. 16 * 17 * This file assumes LITTLE endian system. 18 */ 19 20 /** 21 * @page misra_violations MISRA-C:2012 violations 22 * 23 * @section [global] 24 * Violates MISRA 2012 Advisory Rule 2.3, local typedef not referenced 25 * The SoC header defines typedef for all modules. 26 * 27 * @section [global] 28 * Violates MISRA 2012 Advisory Rule 2.5, local macro not referenced 29 * The SoC header defines macros for all modules and registers. 30 * 31 * @section [global] 32 * Violates MISRA 2012 Advisory Directive 4.9, Function-like macro 33 * These are generated macros used for accessing the bit-fields from registers. 34 * 35 * @section [global] 36 * Violates MISRA 2012 Required Rule 5.1, identifier clash 37 * The supported compilers use more than 31 significant characters for identifiers. 38 * 39 * @section [global] 40 * Violates MISRA 2012 Required Rule 5.2, identifier clash 41 * The supported compilers use more than 31 significant characters for identifiers. 42 * 43 * @section [global] 44 * Violates MISRA 2012 Required Rule 5.4, identifier clash 45 * The supported compilers use more than 31 significant characters for identifiers. 46 * 47 * @section [global] 48 * Violates MISRA 2012 Required Rule 5.5, identifier clash 49 * The supported compilers use more than 31 significant characters for identifiers. 50 * 51 * @section [global] 52 * Violates MISRA 2012 Required Rule 21.1, defined macro '__I' is reserved to the compiler 53 * This type qualifier is needed to ensure correct I/O access and addressing. 54 */ 55 56 /* Prevention from multiple including the same memory map */ 57 #if !defined(S32K148_FTM_H_) /* Check if memory map has not been already included */ 58 #define S32K148_FTM_H_ 59 60 #include "S32K148_COMMON.h" 61 62 /* ---------------------------------------------------------------------------- 63 -- FTM Peripheral Access Layer 64 ---------------------------------------------------------------------------- */ 65 66 /*! 67 * @addtogroup FTM_Peripheral_Access_Layer FTM Peripheral Access Layer 68 * @{ 69 */ 70 71 /** FTM - Size of Registers Arrays */ 72 #define FTM_CnSC_COUNT 8u 73 #define FTM_CV_MIRROR_COUNT 8u 74 75 /** FTM - Register Layout Typedef */ 76 typedef struct { 77 __IO uint32_t SC; /**< Status And Control, offset: 0x0 */ 78 __IO uint32_t CNT; /**< Counter, offset: 0x4 */ 79 __IO uint32_t MOD; /**< Modulo, offset: 0x8 */ 80 struct { /* offset: 0xC, array step: 0x8 */ 81 __IO uint32_t CnSC; /**< Channel (n) Status And Control, array offset: 0xC, array step: 0x8 */ 82 __IO uint32_t CnV; /**< Channel (n) Value, array offset: 0x10, array step: 0x8 */ 83 } CONTROLS[FTM_CnSC_COUNT]; 84 __IO uint32_t CNTIN; /**< Counter Initial Value, offset: 0x4C */ 85 __IO uint32_t STATUS; /**< Capture And Compare Status, offset: 0x50 */ 86 __IO uint32_t MODE; /**< Features Mode Selection, offset: 0x54 */ 87 __IO uint32_t SYNC; /**< Synchronization, offset: 0x58 */ 88 __IO uint32_t OUTINIT; /**< Initial State For Channels Output, offset: 0x5C */ 89 __IO uint32_t OUTMASK; /**< Output Mask, offset: 0x60 */ 90 __IO uint32_t COMBINE; /**< Function For Linked Channels, offset: 0x64 */ 91 __IO uint32_t DEADTIME; /**< Deadtime Configuration, offset: 0x68 */ 92 __IO uint32_t EXTTRIG; /**< FTM External Trigger, offset: 0x6C */ 93 __IO uint32_t POL; /**< Channels Polarity, offset: 0x70 */ 94 __IO uint32_t FMS; /**< Fault Mode Status, offset: 0x74 */ 95 __IO uint32_t FILTER; /**< Input Capture Filter Control, offset: 0x78 */ 96 __IO uint32_t FLTCTRL; /**< Fault Control, offset: 0x7C */ 97 __IO uint32_t QDCTRL; /**< Quadrature Decoder Control And Status, offset: 0x80 */ 98 __IO uint32_t CONF; /**< Configuration, offset: 0x84 */ 99 __IO uint32_t FLTPOL; /**< FTM Fault Input Polarity, offset: 0x88 */ 100 __IO uint32_t SYNCONF; /**< Synchronization Configuration, offset: 0x8C */ 101 __IO uint32_t INVCTRL; /**< FTM Inverting Control, offset: 0x90 */ 102 __IO uint32_t SWOCTRL; /**< FTM Software Output Control, offset: 0x94 */ 103 __IO uint32_t PWMLOAD; /**< FTM PWM Load, offset: 0x98 */ 104 __IO uint32_t HCR; /**< Half Cycle Register, offset: 0x9C */ 105 __IO uint32_t PAIR0DEADTIME; /**< Pair 0 Deadtime Configuration, offset: 0xA0 */ 106 uint8_t RESERVED_0[4]; 107 __IO uint32_t PAIR1DEADTIME; /**< Pair 1 Deadtime Configuration, offset: 0xA8 */ 108 uint8_t RESERVED_1[4]; 109 __IO uint32_t PAIR2DEADTIME; /**< Pair 2 Deadtime Configuration, offset: 0xB0 */ 110 uint8_t RESERVED_2[4]; 111 __IO uint32_t PAIR3DEADTIME; /**< Pair 3 Deadtime Configuration, offset: 0xB8 */ 112 uint8_t RESERVED_3[324]; 113 __IO uint32_t MOD_MIRROR; /**< Mirror of Modulo Value, offset: 0x200 */ 114 __IO uint32_t CV_MIRROR[FTM_CV_MIRROR_COUNT]; /**< Mirror of Channel (n) Match Value, array offset: 0x204, array step: 0x4 */ 115 } FTM_Type, *FTM_MemMapPtr; 116 117 /** Number of instances of the FTM module. */ 118 #define FTM_INSTANCE_COUNT (8u) 119 120 /* FTM - Peripheral instance base addresses */ 121 /** Peripheral FTM0 base address */ 122 #define IP_FTM0_BASE (0x40038000u) 123 /** Peripheral FTM0 base pointer */ 124 #define IP_FTM0 ((FTM_Type *)IP_FTM0_BASE) 125 /** Peripheral FTM1 base address */ 126 #define IP_FTM1_BASE (0x40039000u) 127 /** Peripheral FTM1 base pointer */ 128 #define IP_FTM1 ((FTM_Type *)IP_FTM1_BASE) 129 /** Peripheral FTM2 base address */ 130 #define IP_FTM2_BASE (0x4003A000u) 131 /** Peripheral FTM2 base pointer */ 132 #define IP_FTM2 ((FTM_Type *)IP_FTM2_BASE) 133 /** Peripheral FTM3 base address */ 134 #define IP_FTM3_BASE (0x40026000u) 135 /** Peripheral FTM3 base pointer */ 136 #define IP_FTM3 ((FTM_Type *)IP_FTM3_BASE) 137 /** Peripheral FTM4 base address */ 138 #define IP_FTM4_BASE (0x4006E000u) 139 /** Peripheral FTM4 base pointer */ 140 #define IP_FTM4 ((FTM_Type *)IP_FTM4_BASE) 141 /** Peripheral FTM5 base address */ 142 #define IP_FTM5_BASE (0x4006F000u) 143 /** Peripheral FTM5 base pointer */ 144 #define IP_FTM5 ((FTM_Type *)IP_FTM5_BASE) 145 /** Peripheral FTM6 base address */ 146 #define IP_FTM6_BASE (0x40070000u) 147 /** Peripheral FTM6 base pointer */ 148 #define IP_FTM6 ((FTM_Type *)IP_FTM6_BASE) 149 /** Peripheral FTM7 base address */ 150 #define IP_FTM7_BASE (0x40071000u) 151 /** Peripheral FTM7 base pointer */ 152 #define IP_FTM7 ((FTM_Type *)IP_FTM7_BASE) 153 /** Array initializer of FTM peripheral base addresses */ 154 #define IP_FTM_BASE_ADDRS { IP_FTM0_BASE, IP_FTM1_BASE, IP_FTM2_BASE, IP_FTM3_BASE, IP_FTM4_BASE, IP_FTM5_BASE, IP_FTM6_BASE, IP_FTM7_BASE } 155 /** Array initializer of FTM peripheral base pointers */ 156 #define IP_FTM_BASE_PTRS { IP_FTM0, IP_FTM1, IP_FTM2, IP_FTM3, IP_FTM4, IP_FTM5, IP_FTM6, IP_FTM7 } 157 158 /* ---------------------------------------------------------------------------- 159 -- FTM Register Masks 160 ---------------------------------------------------------------------------- */ 161 162 /*! 163 * @addtogroup FTM_Register_Masks FTM Register Masks 164 * @{ 165 */ 166 167 /*! @name SC - Status And Control */ 168 /*! @{ */ 169 170 #define FTM_SC_PS_MASK (0x7U) 171 #define FTM_SC_PS_SHIFT (0U) 172 #define FTM_SC_PS_WIDTH (3U) 173 #define FTM_SC_PS(x) (((uint32_t)(((uint32_t)(x)) << FTM_SC_PS_SHIFT)) & FTM_SC_PS_MASK) 174 175 #define FTM_SC_CLKS_MASK (0x18U) 176 #define FTM_SC_CLKS_SHIFT (3U) 177 #define FTM_SC_CLKS_WIDTH (2U) 178 #define FTM_SC_CLKS(x) (((uint32_t)(((uint32_t)(x)) << FTM_SC_CLKS_SHIFT)) & FTM_SC_CLKS_MASK) 179 180 #define FTM_SC_CPWMS_MASK (0x20U) 181 #define FTM_SC_CPWMS_SHIFT (5U) 182 #define FTM_SC_CPWMS_WIDTH (1U) 183 #define FTM_SC_CPWMS(x) (((uint32_t)(((uint32_t)(x)) << FTM_SC_CPWMS_SHIFT)) & FTM_SC_CPWMS_MASK) 184 185 #define FTM_SC_RIE_MASK (0x40U) 186 #define FTM_SC_RIE_SHIFT (6U) 187 #define FTM_SC_RIE_WIDTH (1U) 188 #define FTM_SC_RIE(x) (((uint32_t)(((uint32_t)(x)) << FTM_SC_RIE_SHIFT)) & FTM_SC_RIE_MASK) 189 190 #define FTM_SC_RF_MASK (0x80U) 191 #define FTM_SC_RF_SHIFT (7U) 192 #define FTM_SC_RF_WIDTH (1U) 193 #define FTM_SC_RF(x) (((uint32_t)(((uint32_t)(x)) << FTM_SC_RF_SHIFT)) & FTM_SC_RF_MASK) 194 195 #define FTM_SC_TOIE_MASK (0x100U) 196 #define FTM_SC_TOIE_SHIFT (8U) 197 #define FTM_SC_TOIE_WIDTH (1U) 198 #define FTM_SC_TOIE(x) (((uint32_t)(((uint32_t)(x)) << FTM_SC_TOIE_SHIFT)) & FTM_SC_TOIE_MASK) 199 200 #define FTM_SC_TOF_MASK (0x200U) 201 #define FTM_SC_TOF_SHIFT (9U) 202 #define FTM_SC_TOF_WIDTH (1U) 203 #define FTM_SC_TOF(x) (((uint32_t)(((uint32_t)(x)) << FTM_SC_TOF_SHIFT)) & FTM_SC_TOF_MASK) 204 205 #define FTM_SC_PWMEN0_MASK (0x10000U) 206 #define FTM_SC_PWMEN0_SHIFT (16U) 207 #define FTM_SC_PWMEN0_WIDTH (1U) 208 #define FTM_SC_PWMEN0(x) (((uint32_t)(((uint32_t)(x)) << FTM_SC_PWMEN0_SHIFT)) & FTM_SC_PWMEN0_MASK) 209 210 #define FTM_SC_PWMEN1_MASK (0x20000U) 211 #define FTM_SC_PWMEN1_SHIFT (17U) 212 #define FTM_SC_PWMEN1_WIDTH (1U) 213 #define FTM_SC_PWMEN1(x) (((uint32_t)(((uint32_t)(x)) << FTM_SC_PWMEN1_SHIFT)) & FTM_SC_PWMEN1_MASK) 214 215 #define FTM_SC_PWMEN2_MASK (0x40000U) 216 #define FTM_SC_PWMEN2_SHIFT (18U) 217 #define FTM_SC_PWMEN2_WIDTH (1U) 218 #define FTM_SC_PWMEN2(x) (((uint32_t)(((uint32_t)(x)) << FTM_SC_PWMEN2_SHIFT)) & FTM_SC_PWMEN2_MASK) 219 220 #define FTM_SC_PWMEN3_MASK (0x80000U) 221 #define FTM_SC_PWMEN3_SHIFT (19U) 222 #define FTM_SC_PWMEN3_WIDTH (1U) 223 #define FTM_SC_PWMEN3(x) (((uint32_t)(((uint32_t)(x)) << FTM_SC_PWMEN3_SHIFT)) & FTM_SC_PWMEN3_MASK) 224 225 #define FTM_SC_PWMEN4_MASK (0x100000U) 226 #define FTM_SC_PWMEN4_SHIFT (20U) 227 #define FTM_SC_PWMEN4_WIDTH (1U) 228 #define FTM_SC_PWMEN4(x) (((uint32_t)(((uint32_t)(x)) << FTM_SC_PWMEN4_SHIFT)) & FTM_SC_PWMEN4_MASK) 229 230 #define FTM_SC_PWMEN5_MASK (0x200000U) 231 #define FTM_SC_PWMEN5_SHIFT (21U) 232 #define FTM_SC_PWMEN5_WIDTH (1U) 233 #define FTM_SC_PWMEN5(x) (((uint32_t)(((uint32_t)(x)) << FTM_SC_PWMEN5_SHIFT)) & FTM_SC_PWMEN5_MASK) 234 235 #define FTM_SC_PWMEN6_MASK (0x400000U) 236 #define FTM_SC_PWMEN6_SHIFT (22U) 237 #define FTM_SC_PWMEN6_WIDTH (1U) 238 #define FTM_SC_PWMEN6(x) (((uint32_t)(((uint32_t)(x)) << FTM_SC_PWMEN6_SHIFT)) & FTM_SC_PWMEN6_MASK) 239 240 #define FTM_SC_PWMEN7_MASK (0x800000U) 241 #define FTM_SC_PWMEN7_SHIFT (23U) 242 #define FTM_SC_PWMEN7_WIDTH (1U) 243 #define FTM_SC_PWMEN7(x) (((uint32_t)(((uint32_t)(x)) << FTM_SC_PWMEN7_SHIFT)) & FTM_SC_PWMEN7_MASK) 244 245 #define FTM_SC_FLTPS_MASK (0xF000000U) 246 #define FTM_SC_FLTPS_SHIFT (24U) 247 #define FTM_SC_FLTPS_WIDTH (4U) 248 #define FTM_SC_FLTPS(x) (((uint32_t)(((uint32_t)(x)) << FTM_SC_FLTPS_SHIFT)) & FTM_SC_FLTPS_MASK) 249 /*! @} */ 250 251 /*! @name CNT - Counter */ 252 /*! @{ */ 253 254 #define FTM_CNT_COUNT_MASK (0xFFFFU) 255 #define FTM_CNT_COUNT_SHIFT (0U) 256 #define FTM_CNT_COUNT_WIDTH (16U) 257 #define FTM_CNT_COUNT(x) (((uint32_t)(((uint32_t)(x)) << FTM_CNT_COUNT_SHIFT)) & FTM_CNT_COUNT_MASK) 258 /*! @} */ 259 260 /*! @name MOD - Modulo */ 261 /*! @{ */ 262 263 #define FTM_MOD_MOD_MASK (0xFFFFU) 264 #define FTM_MOD_MOD_SHIFT (0U) 265 #define FTM_MOD_MOD_WIDTH (16U) 266 #define FTM_MOD_MOD(x) (((uint32_t)(((uint32_t)(x)) << FTM_MOD_MOD_SHIFT)) & FTM_MOD_MOD_MASK) 267 /*! @} */ 268 269 /*! @name CnSC - Channel (n) Status And Control */ 270 /*! @{ */ 271 272 #define FTM_CnSC_DMA_MASK (0x1U) 273 #define FTM_CnSC_DMA_SHIFT (0U) 274 #define FTM_CnSC_DMA_WIDTH (1U) 275 #define FTM_CnSC_DMA(x) (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_DMA_SHIFT)) & FTM_CnSC_DMA_MASK) 276 277 #define FTM_CnSC_ICRST_MASK (0x2U) 278 #define FTM_CnSC_ICRST_SHIFT (1U) 279 #define FTM_CnSC_ICRST_WIDTH (1U) 280 #define FTM_CnSC_ICRST(x) (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_ICRST_SHIFT)) & FTM_CnSC_ICRST_MASK) 281 282 #define FTM_CnSC_ELSA_MASK (0x4U) 283 #define FTM_CnSC_ELSA_SHIFT (2U) 284 #define FTM_CnSC_ELSA_WIDTH (1U) 285 #define FTM_CnSC_ELSA(x) (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_ELSA_SHIFT)) & FTM_CnSC_ELSA_MASK) 286 287 #define FTM_CnSC_ELSB_MASK (0x8U) 288 #define FTM_CnSC_ELSB_SHIFT (3U) 289 #define FTM_CnSC_ELSB_WIDTH (1U) 290 #define FTM_CnSC_ELSB(x) (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_ELSB_SHIFT)) & FTM_CnSC_ELSB_MASK) 291 292 #define FTM_CnSC_MSA_MASK (0x10U) 293 #define FTM_CnSC_MSA_SHIFT (4U) 294 #define FTM_CnSC_MSA_WIDTH (1U) 295 #define FTM_CnSC_MSA(x) (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_MSA_SHIFT)) & FTM_CnSC_MSA_MASK) 296 297 #define FTM_CnSC_MSB_MASK (0x20U) 298 #define FTM_CnSC_MSB_SHIFT (5U) 299 #define FTM_CnSC_MSB_WIDTH (1U) 300 #define FTM_CnSC_MSB(x) (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_MSB_SHIFT)) & FTM_CnSC_MSB_MASK) 301 302 #define FTM_CnSC_CHIE_MASK (0x40U) 303 #define FTM_CnSC_CHIE_SHIFT (6U) 304 #define FTM_CnSC_CHIE_WIDTH (1U) 305 #define FTM_CnSC_CHIE(x) (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_CHIE_SHIFT)) & FTM_CnSC_CHIE_MASK) 306 307 #define FTM_CnSC_CHF_MASK (0x80U) 308 #define FTM_CnSC_CHF_SHIFT (7U) 309 #define FTM_CnSC_CHF_WIDTH (1U) 310 #define FTM_CnSC_CHF(x) (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_CHF_SHIFT)) & FTM_CnSC_CHF_MASK) 311 312 #define FTM_CnSC_TRIGMODE_MASK (0x100U) 313 #define FTM_CnSC_TRIGMODE_SHIFT (8U) 314 #define FTM_CnSC_TRIGMODE_WIDTH (1U) 315 #define FTM_CnSC_TRIGMODE(x) (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_TRIGMODE_SHIFT)) & FTM_CnSC_TRIGMODE_MASK) 316 317 #define FTM_CnSC_CHIS_MASK (0x200U) 318 #define FTM_CnSC_CHIS_SHIFT (9U) 319 #define FTM_CnSC_CHIS_WIDTH (1U) 320 #define FTM_CnSC_CHIS(x) (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_CHIS_SHIFT)) & FTM_CnSC_CHIS_MASK) 321 322 #define FTM_CnSC_CHOV_MASK (0x400U) 323 #define FTM_CnSC_CHOV_SHIFT (10U) 324 #define FTM_CnSC_CHOV_WIDTH (1U) 325 #define FTM_CnSC_CHOV(x) (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_CHOV_SHIFT)) & FTM_CnSC_CHOV_MASK) 326 /*! @} */ 327 328 /*! @name CnV - Channel (n) Value */ 329 /*! @{ */ 330 331 #define FTM_CnV_VAL_MASK (0xFFFFU) 332 #define FTM_CnV_VAL_SHIFT (0U) 333 #define FTM_CnV_VAL_WIDTH (16U) 334 #define FTM_CnV_VAL(x) (((uint32_t)(((uint32_t)(x)) << FTM_CnV_VAL_SHIFT)) & FTM_CnV_VAL_MASK) 335 /*! @} */ 336 337 /*! @name CNTIN - Counter Initial Value */ 338 /*! @{ */ 339 340 #define FTM_CNTIN_INIT_MASK (0xFFFFU) 341 #define FTM_CNTIN_INIT_SHIFT (0U) 342 #define FTM_CNTIN_INIT_WIDTH (16U) 343 #define FTM_CNTIN_INIT(x) (((uint32_t)(((uint32_t)(x)) << FTM_CNTIN_INIT_SHIFT)) & FTM_CNTIN_INIT_MASK) 344 /*! @} */ 345 346 /*! @name STATUS - Capture And Compare Status */ 347 /*! @{ */ 348 349 #define FTM_STATUS_CH0F_MASK (0x1U) 350 #define FTM_STATUS_CH0F_SHIFT (0U) 351 #define FTM_STATUS_CH0F_WIDTH (1U) 352 #define FTM_STATUS_CH0F(x) (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH0F_SHIFT)) & FTM_STATUS_CH0F_MASK) 353 354 #define FTM_STATUS_CH1F_MASK (0x2U) 355 #define FTM_STATUS_CH1F_SHIFT (1U) 356 #define FTM_STATUS_CH1F_WIDTH (1U) 357 #define FTM_STATUS_CH1F(x) (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH1F_SHIFT)) & FTM_STATUS_CH1F_MASK) 358 359 #define FTM_STATUS_CH2F_MASK (0x4U) 360 #define FTM_STATUS_CH2F_SHIFT (2U) 361 #define FTM_STATUS_CH2F_WIDTH (1U) 362 #define FTM_STATUS_CH2F(x) (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH2F_SHIFT)) & FTM_STATUS_CH2F_MASK) 363 364 #define FTM_STATUS_CH3F_MASK (0x8U) 365 #define FTM_STATUS_CH3F_SHIFT (3U) 366 #define FTM_STATUS_CH3F_WIDTH (1U) 367 #define FTM_STATUS_CH3F(x) (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH3F_SHIFT)) & FTM_STATUS_CH3F_MASK) 368 369 #define FTM_STATUS_CH4F_MASK (0x10U) 370 #define FTM_STATUS_CH4F_SHIFT (4U) 371 #define FTM_STATUS_CH4F_WIDTH (1U) 372 #define FTM_STATUS_CH4F(x) (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH4F_SHIFT)) & FTM_STATUS_CH4F_MASK) 373 374 #define FTM_STATUS_CH5F_MASK (0x20U) 375 #define FTM_STATUS_CH5F_SHIFT (5U) 376 #define FTM_STATUS_CH5F_WIDTH (1U) 377 #define FTM_STATUS_CH5F(x) (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH5F_SHIFT)) & FTM_STATUS_CH5F_MASK) 378 379 #define FTM_STATUS_CH6F_MASK (0x40U) 380 #define FTM_STATUS_CH6F_SHIFT (6U) 381 #define FTM_STATUS_CH6F_WIDTH (1U) 382 #define FTM_STATUS_CH6F(x) (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH6F_SHIFT)) & FTM_STATUS_CH6F_MASK) 383 384 #define FTM_STATUS_CH7F_MASK (0x80U) 385 #define FTM_STATUS_CH7F_SHIFT (7U) 386 #define FTM_STATUS_CH7F_WIDTH (1U) 387 #define FTM_STATUS_CH7F(x) (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH7F_SHIFT)) & FTM_STATUS_CH7F_MASK) 388 /*! @} */ 389 390 /*! @name MODE - Features Mode Selection */ 391 /*! @{ */ 392 393 #define FTM_MODE_FTMEN_MASK (0x1U) 394 #define FTM_MODE_FTMEN_SHIFT (0U) 395 #define FTM_MODE_FTMEN_WIDTH (1U) 396 #define FTM_MODE_FTMEN(x) (((uint32_t)(((uint32_t)(x)) << FTM_MODE_FTMEN_SHIFT)) & FTM_MODE_FTMEN_MASK) 397 398 #define FTM_MODE_INIT_MASK (0x2U) 399 #define FTM_MODE_INIT_SHIFT (1U) 400 #define FTM_MODE_INIT_WIDTH (1U) 401 #define FTM_MODE_INIT(x) (((uint32_t)(((uint32_t)(x)) << FTM_MODE_INIT_SHIFT)) & FTM_MODE_INIT_MASK) 402 403 #define FTM_MODE_WPDIS_MASK (0x4U) 404 #define FTM_MODE_WPDIS_SHIFT (2U) 405 #define FTM_MODE_WPDIS_WIDTH (1U) 406 #define FTM_MODE_WPDIS(x) (((uint32_t)(((uint32_t)(x)) << FTM_MODE_WPDIS_SHIFT)) & FTM_MODE_WPDIS_MASK) 407 408 #define FTM_MODE_PWMSYNC_MASK (0x8U) 409 #define FTM_MODE_PWMSYNC_SHIFT (3U) 410 #define FTM_MODE_PWMSYNC_WIDTH (1U) 411 #define FTM_MODE_PWMSYNC(x) (((uint32_t)(((uint32_t)(x)) << FTM_MODE_PWMSYNC_SHIFT)) & FTM_MODE_PWMSYNC_MASK) 412 413 #define FTM_MODE_CAPTEST_MASK (0x10U) 414 #define FTM_MODE_CAPTEST_SHIFT (4U) 415 #define FTM_MODE_CAPTEST_WIDTH (1U) 416 #define FTM_MODE_CAPTEST(x) (((uint32_t)(((uint32_t)(x)) << FTM_MODE_CAPTEST_SHIFT)) & FTM_MODE_CAPTEST_MASK) 417 418 #define FTM_MODE_FAULTM_MASK (0x60U) 419 #define FTM_MODE_FAULTM_SHIFT (5U) 420 #define FTM_MODE_FAULTM_WIDTH (2U) 421 #define FTM_MODE_FAULTM(x) (((uint32_t)(((uint32_t)(x)) << FTM_MODE_FAULTM_SHIFT)) & FTM_MODE_FAULTM_MASK) 422 423 #define FTM_MODE_FAULTIE_MASK (0x80U) 424 #define FTM_MODE_FAULTIE_SHIFT (7U) 425 #define FTM_MODE_FAULTIE_WIDTH (1U) 426 #define FTM_MODE_FAULTIE(x) (((uint32_t)(((uint32_t)(x)) << FTM_MODE_FAULTIE_SHIFT)) & FTM_MODE_FAULTIE_MASK) 427 /*! @} */ 428 429 /*! @name SYNC - Synchronization */ 430 /*! @{ */ 431 432 #define FTM_SYNC_CNTMIN_MASK (0x1U) 433 #define FTM_SYNC_CNTMIN_SHIFT (0U) 434 #define FTM_SYNC_CNTMIN_WIDTH (1U) 435 #define FTM_SYNC_CNTMIN(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_CNTMIN_SHIFT)) & FTM_SYNC_CNTMIN_MASK) 436 437 #define FTM_SYNC_CNTMAX_MASK (0x2U) 438 #define FTM_SYNC_CNTMAX_SHIFT (1U) 439 #define FTM_SYNC_CNTMAX_WIDTH (1U) 440 #define FTM_SYNC_CNTMAX(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_CNTMAX_SHIFT)) & FTM_SYNC_CNTMAX_MASK) 441 442 #define FTM_SYNC_REINIT_MASK (0x4U) 443 #define FTM_SYNC_REINIT_SHIFT (2U) 444 #define FTM_SYNC_REINIT_WIDTH (1U) 445 #define FTM_SYNC_REINIT(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_REINIT_SHIFT)) & FTM_SYNC_REINIT_MASK) 446 447 #define FTM_SYNC_SYNCHOM_MASK (0x8U) 448 #define FTM_SYNC_SYNCHOM_SHIFT (3U) 449 #define FTM_SYNC_SYNCHOM_WIDTH (1U) 450 #define FTM_SYNC_SYNCHOM(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_SYNCHOM_SHIFT)) & FTM_SYNC_SYNCHOM_MASK) 451 452 #define FTM_SYNC_TRIG0_MASK (0x10U) 453 #define FTM_SYNC_TRIG0_SHIFT (4U) 454 #define FTM_SYNC_TRIG0_WIDTH (1U) 455 #define FTM_SYNC_TRIG0(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_TRIG0_SHIFT)) & FTM_SYNC_TRIG0_MASK) 456 457 #define FTM_SYNC_TRIG1_MASK (0x20U) 458 #define FTM_SYNC_TRIG1_SHIFT (5U) 459 #define FTM_SYNC_TRIG1_WIDTH (1U) 460 #define FTM_SYNC_TRIG1(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_TRIG1_SHIFT)) & FTM_SYNC_TRIG1_MASK) 461 462 #define FTM_SYNC_TRIG2_MASK (0x40U) 463 #define FTM_SYNC_TRIG2_SHIFT (6U) 464 #define FTM_SYNC_TRIG2_WIDTH (1U) 465 #define FTM_SYNC_TRIG2(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_TRIG2_SHIFT)) & FTM_SYNC_TRIG2_MASK) 466 467 #define FTM_SYNC_SWSYNC_MASK (0x80U) 468 #define FTM_SYNC_SWSYNC_SHIFT (7U) 469 #define FTM_SYNC_SWSYNC_WIDTH (1U) 470 #define FTM_SYNC_SWSYNC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_SWSYNC_SHIFT)) & FTM_SYNC_SWSYNC_MASK) 471 /*! @} */ 472 473 /*! @name OUTINIT - Initial State For Channels Output */ 474 /*! @{ */ 475 476 #define FTM_OUTINIT_CH0OI_MASK (0x1U) 477 #define FTM_OUTINIT_CH0OI_SHIFT (0U) 478 #define FTM_OUTINIT_CH0OI_WIDTH (1U) 479 #define FTM_OUTINIT_CH0OI(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH0OI_SHIFT)) & FTM_OUTINIT_CH0OI_MASK) 480 481 #define FTM_OUTINIT_CH1OI_MASK (0x2U) 482 #define FTM_OUTINIT_CH1OI_SHIFT (1U) 483 #define FTM_OUTINIT_CH1OI_WIDTH (1U) 484 #define FTM_OUTINIT_CH1OI(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH1OI_SHIFT)) & FTM_OUTINIT_CH1OI_MASK) 485 486 #define FTM_OUTINIT_CH2OI_MASK (0x4U) 487 #define FTM_OUTINIT_CH2OI_SHIFT (2U) 488 #define FTM_OUTINIT_CH2OI_WIDTH (1U) 489 #define FTM_OUTINIT_CH2OI(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH2OI_SHIFT)) & FTM_OUTINIT_CH2OI_MASK) 490 491 #define FTM_OUTINIT_CH3OI_MASK (0x8U) 492 #define FTM_OUTINIT_CH3OI_SHIFT (3U) 493 #define FTM_OUTINIT_CH3OI_WIDTH (1U) 494 #define FTM_OUTINIT_CH3OI(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH3OI_SHIFT)) & FTM_OUTINIT_CH3OI_MASK) 495 496 #define FTM_OUTINIT_CH4OI_MASK (0x10U) 497 #define FTM_OUTINIT_CH4OI_SHIFT (4U) 498 #define FTM_OUTINIT_CH4OI_WIDTH (1U) 499 #define FTM_OUTINIT_CH4OI(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH4OI_SHIFT)) & FTM_OUTINIT_CH4OI_MASK) 500 501 #define FTM_OUTINIT_CH5OI_MASK (0x20U) 502 #define FTM_OUTINIT_CH5OI_SHIFT (5U) 503 #define FTM_OUTINIT_CH5OI_WIDTH (1U) 504 #define FTM_OUTINIT_CH5OI(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH5OI_SHIFT)) & FTM_OUTINIT_CH5OI_MASK) 505 506 #define FTM_OUTINIT_CH6OI_MASK (0x40U) 507 #define FTM_OUTINIT_CH6OI_SHIFT (6U) 508 #define FTM_OUTINIT_CH6OI_WIDTH (1U) 509 #define FTM_OUTINIT_CH6OI(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH6OI_SHIFT)) & FTM_OUTINIT_CH6OI_MASK) 510 511 #define FTM_OUTINIT_CH7OI_MASK (0x80U) 512 #define FTM_OUTINIT_CH7OI_SHIFT (7U) 513 #define FTM_OUTINIT_CH7OI_WIDTH (1U) 514 #define FTM_OUTINIT_CH7OI(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH7OI_SHIFT)) & FTM_OUTINIT_CH7OI_MASK) 515 /*! @} */ 516 517 /*! @name OUTMASK - Output Mask */ 518 /*! @{ */ 519 520 #define FTM_OUTMASK_CH0OM_MASK (0x1U) 521 #define FTM_OUTMASK_CH0OM_SHIFT (0U) 522 #define FTM_OUTMASK_CH0OM_WIDTH (1U) 523 #define FTM_OUTMASK_CH0OM(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH0OM_SHIFT)) & FTM_OUTMASK_CH0OM_MASK) 524 525 #define FTM_OUTMASK_CH1OM_MASK (0x2U) 526 #define FTM_OUTMASK_CH1OM_SHIFT (1U) 527 #define FTM_OUTMASK_CH1OM_WIDTH (1U) 528 #define FTM_OUTMASK_CH1OM(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH1OM_SHIFT)) & FTM_OUTMASK_CH1OM_MASK) 529 530 #define FTM_OUTMASK_CH2OM_MASK (0x4U) 531 #define FTM_OUTMASK_CH2OM_SHIFT (2U) 532 #define FTM_OUTMASK_CH2OM_WIDTH (1U) 533 #define FTM_OUTMASK_CH2OM(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH2OM_SHIFT)) & FTM_OUTMASK_CH2OM_MASK) 534 535 #define FTM_OUTMASK_CH3OM_MASK (0x8U) 536 #define FTM_OUTMASK_CH3OM_SHIFT (3U) 537 #define FTM_OUTMASK_CH3OM_WIDTH (1U) 538 #define FTM_OUTMASK_CH3OM(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH3OM_SHIFT)) & FTM_OUTMASK_CH3OM_MASK) 539 540 #define FTM_OUTMASK_CH4OM_MASK (0x10U) 541 #define FTM_OUTMASK_CH4OM_SHIFT (4U) 542 #define FTM_OUTMASK_CH4OM_WIDTH (1U) 543 #define FTM_OUTMASK_CH4OM(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH4OM_SHIFT)) & FTM_OUTMASK_CH4OM_MASK) 544 545 #define FTM_OUTMASK_CH5OM_MASK (0x20U) 546 #define FTM_OUTMASK_CH5OM_SHIFT (5U) 547 #define FTM_OUTMASK_CH5OM_WIDTH (1U) 548 #define FTM_OUTMASK_CH5OM(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH5OM_SHIFT)) & FTM_OUTMASK_CH5OM_MASK) 549 550 #define FTM_OUTMASK_CH6OM_MASK (0x40U) 551 #define FTM_OUTMASK_CH6OM_SHIFT (6U) 552 #define FTM_OUTMASK_CH6OM_WIDTH (1U) 553 #define FTM_OUTMASK_CH6OM(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH6OM_SHIFT)) & FTM_OUTMASK_CH6OM_MASK) 554 555 #define FTM_OUTMASK_CH7OM_MASK (0x80U) 556 #define FTM_OUTMASK_CH7OM_SHIFT (7U) 557 #define FTM_OUTMASK_CH7OM_WIDTH (1U) 558 #define FTM_OUTMASK_CH7OM(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH7OM_SHIFT)) & FTM_OUTMASK_CH7OM_MASK) 559 /*! @} */ 560 561 /*! @name COMBINE - Function For Linked Channels */ 562 /*! @{ */ 563 564 #define FTM_COMBINE_COMBINE0_MASK (0x1U) 565 #define FTM_COMBINE_COMBINE0_SHIFT (0U) 566 #define FTM_COMBINE_COMBINE0_WIDTH (1U) 567 #define FTM_COMBINE_COMBINE0(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMBINE0_SHIFT)) & FTM_COMBINE_COMBINE0_MASK) 568 569 #define FTM_COMBINE_COMP0_MASK (0x2U) 570 #define FTM_COMBINE_COMP0_SHIFT (1U) 571 #define FTM_COMBINE_COMP0_WIDTH (1U) 572 #define FTM_COMBINE_COMP0(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMP0_SHIFT)) & FTM_COMBINE_COMP0_MASK) 573 574 #define FTM_COMBINE_DECAPEN0_MASK (0x4U) 575 #define FTM_COMBINE_DECAPEN0_SHIFT (2U) 576 #define FTM_COMBINE_DECAPEN0_WIDTH (1U) 577 #define FTM_COMBINE_DECAPEN0(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAPEN0_SHIFT)) & FTM_COMBINE_DECAPEN0_MASK) 578 579 #define FTM_COMBINE_DECAP0_MASK (0x8U) 580 #define FTM_COMBINE_DECAP0_SHIFT (3U) 581 #define FTM_COMBINE_DECAP0_WIDTH (1U) 582 #define FTM_COMBINE_DECAP0(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAP0_SHIFT)) & FTM_COMBINE_DECAP0_MASK) 583 584 #define FTM_COMBINE_DTEN0_MASK (0x10U) 585 #define FTM_COMBINE_DTEN0_SHIFT (4U) 586 #define FTM_COMBINE_DTEN0_WIDTH (1U) 587 #define FTM_COMBINE_DTEN0(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DTEN0_SHIFT)) & FTM_COMBINE_DTEN0_MASK) 588 589 #define FTM_COMBINE_SYNCEN0_MASK (0x20U) 590 #define FTM_COMBINE_SYNCEN0_SHIFT (5U) 591 #define FTM_COMBINE_SYNCEN0_WIDTH (1U) 592 #define FTM_COMBINE_SYNCEN0(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_SYNCEN0_SHIFT)) & FTM_COMBINE_SYNCEN0_MASK) 593 594 #define FTM_COMBINE_FAULTEN0_MASK (0x40U) 595 #define FTM_COMBINE_FAULTEN0_SHIFT (6U) 596 #define FTM_COMBINE_FAULTEN0_WIDTH (1U) 597 #define FTM_COMBINE_FAULTEN0(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_FAULTEN0_SHIFT)) & FTM_COMBINE_FAULTEN0_MASK) 598 599 #define FTM_COMBINE_MCOMBINE0_MASK (0x80U) 600 #define FTM_COMBINE_MCOMBINE0_SHIFT (7U) 601 #define FTM_COMBINE_MCOMBINE0_WIDTH (1U) 602 #define FTM_COMBINE_MCOMBINE0(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_MCOMBINE0_SHIFT)) & FTM_COMBINE_MCOMBINE0_MASK) 603 604 #define FTM_COMBINE_COMBINE1_MASK (0x100U) 605 #define FTM_COMBINE_COMBINE1_SHIFT (8U) 606 #define FTM_COMBINE_COMBINE1_WIDTH (1U) 607 #define FTM_COMBINE_COMBINE1(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMBINE1_SHIFT)) & FTM_COMBINE_COMBINE1_MASK) 608 609 #define FTM_COMBINE_COMP1_MASK (0x200U) 610 #define FTM_COMBINE_COMP1_SHIFT (9U) 611 #define FTM_COMBINE_COMP1_WIDTH (1U) 612 #define FTM_COMBINE_COMP1(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMP1_SHIFT)) & FTM_COMBINE_COMP1_MASK) 613 614 #define FTM_COMBINE_DECAPEN1_MASK (0x400U) 615 #define FTM_COMBINE_DECAPEN1_SHIFT (10U) 616 #define FTM_COMBINE_DECAPEN1_WIDTH (1U) 617 #define FTM_COMBINE_DECAPEN1(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAPEN1_SHIFT)) & FTM_COMBINE_DECAPEN1_MASK) 618 619 #define FTM_COMBINE_DECAP1_MASK (0x800U) 620 #define FTM_COMBINE_DECAP1_SHIFT (11U) 621 #define FTM_COMBINE_DECAP1_WIDTH (1U) 622 #define FTM_COMBINE_DECAP1(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAP1_SHIFT)) & FTM_COMBINE_DECAP1_MASK) 623 624 #define FTM_COMBINE_DTEN1_MASK (0x1000U) 625 #define FTM_COMBINE_DTEN1_SHIFT (12U) 626 #define FTM_COMBINE_DTEN1_WIDTH (1U) 627 #define FTM_COMBINE_DTEN1(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DTEN1_SHIFT)) & FTM_COMBINE_DTEN1_MASK) 628 629 #define FTM_COMBINE_SYNCEN1_MASK (0x2000U) 630 #define FTM_COMBINE_SYNCEN1_SHIFT (13U) 631 #define FTM_COMBINE_SYNCEN1_WIDTH (1U) 632 #define FTM_COMBINE_SYNCEN1(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_SYNCEN1_SHIFT)) & FTM_COMBINE_SYNCEN1_MASK) 633 634 #define FTM_COMBINE_FAULTEN1_MASK (0x4000U) 635 #define FTM_COMBINE_FAULTEN1_SHIFT (14U) 636 #define FTM_COMBINE_FAULTEN1_WIDTH (1U) 637 #define FTM_COMBINE_FAULTEN1(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_FAULTEN1_SHIFT)) & FTM_COMBINE_FAULTEN1_MASK) 638 639 #define FTM_COMBINE_MCOMBINE1_MASK (0x8000U) 640 #define FTM_COMBINE_MCOMBINE1_SHIFT (15U) 641 #define FTM_COMBINE_MCOMBINE1_WIDTH (1U) 642 #define FTM_COMBINE_MCOMBINE1(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_MCOMBINE1_SHIFT)) & FTM_COMBINE_MCOMBINE1_MASK) 643 644 #define FTM_COMBINE_COMBINE2_MASK (0x10000U) 645 #define FTM_COMBINE_COMBINE2_SHIFT (16U) 646 #define FTM_COMBINE_COMBINE2_WIDTH (1U) 647 #define FTM_COMBINE_COMBINE2(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMBINE2_SHIFT)) & FTM_COMBINE_COMBINE2_MASK) 648 649 #define FTM_COMBINE_COMP2_MASK (0x20000U) 650 #define FTM_COMBINE_COMP2_SHIFT (17U) 651 #define FTM_COMBINE_COMP2_WIDTH (1U) 652 #define FTM_COMBINE_COMP2(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMP2_SHIFT)) & FTM_COMBINE_COMP2_MASK) 653 654 #define FTM_COMBINE_DECAPEN2_MASK (0x40000U) 655 #define FTM_COMBINE_DECAPEN2_SHIFT (18U) 656 #define FTM_COMBINE_DECAPEN2_WIDTH (1U) 657 #define FTM_COMBINE_DECAPEN2(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAPEN2_SHIFT)) & FTM_COMBINE_DECAPEN2_MASK) 658 659 #define FTM_COMBINE_DECAP2_MASK (0x80000U) 660 #define FTM_COMBINE_DECAP2_SHIFT (19U) 661 #define FTM_COMBINE_DECAP2_WIDTH (1U) 662 #define FTM_COMBINE_DECAP2(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAP2_SHIFT)) & FTM_COMBINE_DECAP2_MASK) 663 664 #define FTM_COMBINE_DTEN2_MASK (0x100000U) 665 #define FTM_COMBINE_DTEN2_SHIFT (20U) 666 #define FTM_COMBINE_DTEN2_WIDTH (1U) 667 #define FTM_COMBINE_DTEN2(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DTEN2_SHIFT)) & FTM_COMBINE_DTEN2_MASK) 668 669 #define FTM_COMBINE_SYNCEN2_MASK (0x200000U) 670 #define FTM_COMBINE_SYNCEN2_SHIFT (21U) 671 #define FTM_COMBINE_SYNCEN2_WIDTH (1U) 672 #define FTM_COMBINE_SYNCEN2(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_SYNCEN2_SHIFT)) & FTM_COMBINE_SYNCEN2_MASK) 673 674 #define FTM_COMBINE_FAULTEN2_MASK (0x400000U) 675 #define FTM_COMBINE_FAULTEN2_SHIFT (22U) 676 #define FTM_COMBINE_FAULTEN2_WIDTH (1U) 677 #define FTM_COMBINE_FAULTEN2(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_FAULTEN2_SHIFT)) & FTM_COMBINE_FAULTEN2_MASK) 678 679 #define FTM_COMBINE_MCOMBINE2_MASK (0x800000U) 680 #define FTM_COMBINE_MCOMBINE2_SHIFT (23U) 681 #define FTM_COMBINE_MCOMBINE2_WIDTH (1U) 682 #define FTM_COMBINE_MCOMBINE2(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_MCOMBINE2_SHIFT)) & FTM_COMBINE_MCOMBINE2_MASK) 683 684 #define FTM_COMBINE_COMBINE3_MASK (0x1000000U) 685 #define FTM_COMBINE_COMBINE3_SHIFT (24U) 686 #define FTM_COMBINE_COMBINE3_WIDTH (1U) 687 #define FTM_COMBINE_COMBINE3(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMBINE3_SHIFT)) & FTM_COMBINE_COMBINE3_MASK) 688 689 #define FTM_COMBINE_COMP3_MASK (0x2000000U) 690 #define FTM_COMBINE_COMP3_SHIFT (25U) 691 #define FTM_COMBINE_COMP3_WIDTH (1U) 692 #define FTM_COMBINE_COMP3(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMP3_SHIFT)) & FTM_COMBINE_COMP3_MASK) 693 694 #define FTM_COMBINE_DECAPEN3_MASK (0x4000000U) 695 #define FTM_COMBINE_DECAPEN3_SHIFT (26U) 696 #define FTM_COMBINE_DECAPEN3_WIDTH (1U) 697 #define FTM_COMBINE_DECAPEN3(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAPEN3_SHIFT)) & FTM_COMBINE_DECAPEN3_MASK) 698 699 #define FTM_COMBINE_DECAP3_MASK (0x8000000U) 700 #define FTM_COMBINE_DECAP3_SHIFT (27U) 701 #define FTM_COMBINE_DECAP3_WIDTH (1U) 702 #define FTM_COMBINE_DECAP3(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAP3_SHIFT)) & FTM_COMBINE_DECAP3_MASK) 703 704 #define FTM_COMBINE_DTEN3_MASK (0x10000000U) 705 #define FTM_COMBINE_DTEN3_SHIFT (28U) 706 #define FTM_COMBINE_DTEN3_WIDTH (1U) 707 #define FTM_COMBINE_DTEN3(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DTEN3_SHIFT)) & FTM_COMBINE_DTEN3_MASK) 708 709 #define FTM_COMBINE_SYNCEN3_MASK (0x20000000U) 710 #define FTM_COMBINE_SYNCEN3_SHIFT (29U) 711 #define FTM_COMBINE_SYNCEN3_WIDTH (1U) 712 #define FTM_COMBINE_SYNCEN3(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_SYNCEN3_SHIFT)) & FTM_COMBINE_SYNCEN3_MASK) 713 714 #define FTM_COMBINE_FAULTEN3_MASK (0x40000000U) 715 #define FTM_COMBINE_FAULTEN3_SHIFT (30U) 716 #define FTM_COMBINE_FAULTEN3_WIDTH (1U) 717 #define FTM_COMBINE_FAULTEN3(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_FAULTEN3_SHIFT)) & FTM_COMBINE_FAULTEN3_MASK) 718 719 #define FTM_COMBINE_MCOMBINE3_MASK (0x80000000U) 720 #define FTM_COMBINE_MCOMBINE3_SHIFT (31U) 721 #define FTM_COMBINE_MCOMBINE3_WIDTH (1U) 722 #define FTM_COMBINE_MCOMBINE3(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_MCOMBINE3_SHIFT)) & FTM_COMBINE_MCOMBINE3_MASK) 723 /*! @} */ 724 725 /*! @name DEADTIME - Deadtime Configuration */ 726 /*! @{ */ 727 728 #define FTM_DEADTIME_DTVAL_MASK (0x3FU) 729 #define FTM_DEADTIME_DTVAL_SHIFT (0U) 730 #define FTM_DEADTIME_DTVAL_WIDTH (6U) 731 #define FTM_DEADTIME_DTVAL(x) (((uint32_t)(((uint32_t)(x)) << FTM_DEADTIME_DTVAL_SHIFT)) & FTM_DEADTIME_DTVAL_MASK) 732 733 #define FTM_DEADTIME_DTPS_MASK (0xC0U) 734 #define FTM_DEADTIME_DTPS_SHIFT (6U) 735 #define FTM_DEADTIME_DTPS_WIDTH (2U) 736 #define FTM_DEADTIME_DTPS(x) (((uint32_t)(((uint32_t)(x)) << FTM_DEADTIME_DTPS_SHIFT)) & FTM_DEADTIME_DTPS_MASK) 737 738 #define FTM_DEADTIME_DTVALEX_MASK (0xF0000U) 739 #define FTM_DEADTIME_DTVALEX_SHIFT (16U) 740 #define FTM_DEADTIME_DTVALEX_WIDTH (4U) 741 #define FTM_DEADTIME_DTVALEX(x) (((uint32_t)(((uint32_t)(x)) << FTM_DEADTIME_DTVALEX_SHIFT)) & FTM_DEADTIME_DTVALEX_MASK) 742 /*! @} */ 743 744 /*! @name EXTTRIG - FTM External Trigger */ 745 /*! @{ */ 746 747 #define FTM_EXTTRIG_CH2TRIG_MASK (0x1U) 748 #define FTM_EXTTRIG_CH2TRIG_SHIFT (0U) 749 #define FTM_EXTTRIG_CH2TRIG_WIDTH (1U) 750 #define FTM_EXTTRIG_CH2TRIG(x) (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_CH2TRIG_SHIFT)) & FTM_EXTTRIG_CH2TRIG_MASK) 751 752 #define FTM_EXTTRIG_CH3TRIG_MASK (0x2U) 753 #define FTM_EXTTRIG_CH3TRIG_SHIFT (1U) 754 #define FTM_EXTTRIG_CH3TRIG_WIDTH (1U) 755 #define FTM_EXTTRIG_CH3TRIG(x) (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_CH3TRIG_SHIFT)) & FTM_EXTTRIG_CH3TRIG_MASK) 756 757 #define FTM_EXTTRIG_CH4TRIG_MASK (0x4U) 758 #define FTM_EXTTRIG_CH4TRIG_SHIFT (2U) 759 #define FTM_EXTTRIG_CH4TRIG_WIDTH (1U) 760 #define FTM_EXTTRIG_CH4TRIG(x) (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_CH4TRIG_SHIFT)) & FTM_EXTTRIG_CH4TRIG_MASK) 761 762 #define FTM_EXTTRIG_CH5TRIG_MASK (0x8U) 763 #define FTM_EXTTRIG_CH5TRIG_SHIFT (3U) 764 #define FTM_EXTTRIG_CH5TRIG_WIDTH (1U) 765 #define FTM_EXTTRIG_CH5TRIG(x) (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_CH5TRIG_SHIFT)) & FTM_EXTTRIG_CH5TRIG_MASK) 766 767 #define FTM_EXTTRIG_CH0TRIG_MASK (0x10U) 768 #define FTM_EXTTRIG_CH0TRIG_SHIFT (4U) 769 #define FTM_EXTTRIG_CH0TRIG_WIDTH (1U) 770 #define FTM_EXTTRIG_CH0TRIG(x) (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_CH0TRIG_SHIFT)) & FTM_EXTTRIG_CH0TRIG_MASK) 771 772 #define FTM_EXTTRIG_CH1TRIG_MASK (0x20U) 773 #define FTM_EXTTRIG_CH1TRIG_SHIFT (5U) 774 #define FTM_EXTTRIG_CH1TRIG_WIDTH (1U) 775 #define FTM_EXTTRIG_CH1TRIG(x) (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_CH1TRIG_SHIFT)) & FTM_EXTTRIG_CH1TRIG_MASK) 776 777 #define FTM_EXTTRIG_INITTRIGEN_MASK (0x40U) 778 #define FTM_EXTTRIG_INITTRIGEN_SHIFT (6U) 779 #define FTM_EXTTRIG_INITTRIGEN_WIDTH (1U) 780 #define FTM_EXTTRIG_INITTRIGEN(x) (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_INITTRIGEN_SHIFT)) & FTM_EXTTRIG_INITTRIGEN_MASK) 781 782 #define FTM_EXTTRIG_TRIGF_MASK (0x80U) 783 #define FTM_EXTTRIG_TRIGF_SHIFT (7U) 784 #define FTM_EXTTRIG_TRIGF_WIDTH (1U) 785 #define FTM_EXTTRIG_TRIGF(x) (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_TRIGF_SHIFT)) & FTM_EXTTRIG_TRIGF_MASK) 786 787 #define FTM_EXTTRIG_CH6TRIG_MASK (0x100U) 788 #define FTM_EXTTRIG_CH6TRIG_SHIFT (8U) 789 #define FTM_EXTTRIG_CH6TRIG_WIDTH (1U) 790 #define FTM_EXTTRIG_CH6TRIG(x) (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_CH6TRIG_SHIFT)) & FTM_EXTTRIG_CH6TRIG_MASK) 791 792 #define FTM_EXTTRIG_CH7TRIG_MASK (0x200U) 793 #define FTM_EXTTRIG_CH7TRIG_SHIFT (9U) 794 #define FTM_EXTTRIG_CH7TRIG_WIDTH (1U) 795 #define FTM_EXTTRIG_CH7TRIG(x) (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_CH7TRIG_SHIFT)) & FTM_EXTTRIG_CH7TRIG_MASK) 796 /*! @} */ 797 798 /*! @name POL - Channels Polarity */ 799 /*! @{ */ 800 801 #define FTM_POL_POL0_MASK (0x1U) 802 #define FTM_POL_POL0_SHIFT (0U) 803 #define FTM_POL_POL0_WIDTH (1U) 804 #define FTM_POL_POL0(x) (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL0_SHIFT)) & FTM_POL_POL0_MASK) 805 806 #define FTM_POL_POL1_MASK (0x2U) 807 #define FTM_POL_POL1_SHIFT (1U) 808 #define FTM_POL_POL1_WIDTH (1U) 809 #define FTM_POL_POL1(x) (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL1_SHIFT)) & FTM_POL_POL1_MASK) 810 811 #define FTM_POL_POL2_MASK (0x4U) 812 #define FTM_POL_POL2_SHIFT (2U) 813 #define FTM_POL_POL2_WIDTH (1U) 814 #define FTM_POL_POL2(x) (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL2_SHIFT)) & FTM_POL_POL2_MASK) 815 816 #define FTM_POL_POL3_MASK (0x8U) 817 #define FTM_POL_POL3_SHIFT (3U) 818 #define FTM_POL_POL3_WIDTH (1U) 819 #define FTM_POL_POL3(x) (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL3_SHIFT)) & FTM_POL_POL3_MASK) 820 821 #define FTM_POL_POL4_MASK (0x10U) 822 #define FTM_POL_POL4_SHIFT (4U) 823 #define FTM_POL_POL4_WIDTH (1U) 824 #define FTM_POL_POL4(x) (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL4_SHIFT)) & FTM_POL_POL4_MASK) 825 826 #define FTM_POL_POL5_MASK (0x20U) 827 #define FTM_POL_POL5_SHIFT (5U) 828 #define FTM_POL_POL5_WIDTH (1U) 829 #define FTM_POL_POL5(x) (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL5_SHIFT)) & FTM_POL_POL5_MASK) 830 831 #define FTM_POL_POL6_MASK (0x40U) 832 #define FTM_POL_POL6_SHIFT (6U) 833 #define FTM_POL_POL6_WIDTH (1U) 834 #define FTM_POL_POL6(x) (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL6_SHIFT)) & FTM_POL_POL6_MASK) 835 836 #define FTM_POL_POL7_MASK (0x80U) 837 #define FTM_POL_POL7_SHIFT (7U) 838 #define FTM_POL_POL7_WIDTH (1U) 839 #define FTM_POL_POL7(x) (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL7_SHIFT)) & FTM_POL_POL7_MASK) 840 /*! @} */ 841 842 /*! @name FMS - Fault Mode Status */ 843 /*! @{ */ 844 845 #define FTM_FMS_FAULTF0_MASK (0x1U) 846 #define FTM_FMS_FAULTF0_SHIFT (0U) 847 #define FTM_FMS_FAULTF0_WIDTH (1U) 848 #define FTM_FMS_FAULTF0(x) (((uint32_t)(((uint32_t)(x)) << FTM_FMS_FAULTF0_SHIFT)) & FTM_FMS_FAULTF0_MASK) 849 850 #define FTM_FMS_FAULTF1_MASK (0x2U) 851 #define FTM_FMS_FAULTF1_SHIFT (1U) 852 #define FTM_FMS_FAULTF1_WIDTH (1U) 853 #define FTM_FMS_FAULTF1(x) (((uint32_t)(((uint32_t)(x)) << FTM_FMS_FAULTF1_SHIFT)) & FTM_FMS_FAULTF1_MASK) 854 855 #define FTM_FMS_FAULTF2_MASK (0x4U) 856 #define FTM_FMS_FAULTF2_SHIFT (2U) 857 #define FTM_FMS_FAULTF2_WIDTH (1U) 858 #define FTM_FMS_FAULTF2(x) (((uint32_t)(((uint32_t)(x)) << FTM_FMS_FAULTF2_SHIFT)) & FTM_FMS_FAULTF2_MASK) 859 860 #define FTM_FMS_FAULTF3_MASK (0x8U) 861 #define FTM_FMS_FAULTF3_SHIFT (3U) 862 #define FTM_FMS_FAULTF3_WIDTH (1U) 863 #define FTM_FMS_FAULTF3(x) (((uint32_t)(((uint32_t)(x)) << FTM_FMS_FAULTF3_SHIFT)) & FTM_FMS_FAULTF3_MASK) 864 865 #define FTM_FMS_FAULTIN_MASK (0x20U) 866 #define FTM_FMS_FAULTIN_SHIFT (5U) 867 #define FTM_FMS_FAULTIN_WIDTH (1U) 868 #define FTM_FMS_FAULTIN(x) (((uint32_t)(((uint32_t)(x)) << FTM_FMS_FAULTIN_SHIFT)) & FTM_FMS_FAULTIN_MASK) 869 870 #define FTM_FMS_WPEN_MASK (0x40U) 871 #define FTM_FMS_WPEN_SHIFT (6U) 872 #define FTM_FMS_WPEN_WIDTH (1U) 873 #define FTM_FMS_WPEN(x) (((uint32_t)(((uint32_t)(x)) << FTM_FMS_WPEN_SHIFT)) & FTM_FMS_WPEN_MASK) 874 875 #define FTM_FMS_FAULTF_MASK (0x80U) 876 #define FTM_FMS_FAULTF_SHIFT (7U) 877 #define FTM_FMS_FAULTF_WIDTH (1U) 878 #define FTM_FMS_FAULTF(x) (((uint32_t)(((uint32_t)(x)) << FTM_FMS_FAULTF_SHIFT)) & FTM_FMS_FAULTF_MASK) 879 /*! @} */ 880 881 /*! @name FILTER - Input Capture Filter Control */ 882 /*! @{ */ 883 884 #define FTM_FILTER_CH0FVAL_MASK (0xFU) 885 #define FTM_FILTER_CH0FVAL_SHIFT (0U) 886 #define FTM_FILTER_CH0FVAL_WIDTH (4U) 887 #define FTM_FILTER_CH0FVAL(x) (((uint32_t)(((uint32_t)(x)) << FTM_FILTER_CH0FVAL_SHIFT)) & FTM_FILTER_CH0FVAL_MASK) 888 889 #define FTM_FILTER_CH1FVAL_MASK (0xF0U) 890 #define FTM_FILTER_CH1FVAL_SHIFT (4U) 891 #define FTM_FILTER_CH1FVAL_WIDTH (4U) 892 #define FTM_FILTER_CH1FVAL(x) (((uint32_t)(((uint32_t)(x)) << FTM_FILTER_CH1FVAL_SHIFT)) & FTM_FILTER_CH1FVAL_MASK) 893 894 #define FTM_FILTER_CH2FVAL_MASK (0xF00U) 895 #define FTM_FILTER_CH2FVAL_SHIFT (8U) 896 #define FTM_FILTER_CH2FVAL_WIDTH (4U) 897 #define FTM_FILTER_CH2FVAL(x) (((uint32_t)(((uint32_t)(x)) << FTM_FILTER_CH2FVAL_SHIFT)) & FTM_FILTER_CH2FVAL_MASK) 898 899 #define FTM_FILTER_CH3FVAL_MASK (0xF000U) 900 #define FTM_FILTER_CH3FVAL_SHIFT (12U) 901 #define FTM_FILTER_CH3FVAL_WIDTH (4U) 902 #define FTM_FILTER_CH3FVAL(x) (((uint32_t)(((uint32_t)(x)) << FTM_FILTER_CH3FVAL_SHIFT)) & FTM_FILTER_CH3FVAL_MASK) 903 /*! @} */ 904 905 /*! @name FLTCTRL - Fault Control */ 906 /*! @{ */ 907 908 #define FTM_FLTCTRL_FAULT0EN_MASK (0x1U) 909 #define FTM_FLTCTRL_FAULT0EN_SHIFT (0U) 910 #define FTM_FLTCTRL_FAULT0EN_WIDTH (1U) 911 #define FTM_FLTCTRL_FAULT0EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FAULT0EN_SHIFT)) & FTM_FLTCTRL_FAULT0EN_MASK) 912 913 #define FTM_FLTCTRL_FAULT1EN_MASK (0x2U) 914 #define FTM_FLTCTRL_FAULT1EN_SHIFT (1U) 915 #define FTM_FLTCTRL_FAULT1EN_WIDTH (1U) 916 #define FTM_FLTCTRL_FAULT1EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FAULT1EN_SHIFT)) & FTM_FLTCTRL_FAULT1EN_MASK) 917 918 #define FTM_FLTCTRL_FAULT2EN_MASK (0x4U) 919 #define FTM_FLTCTRL_FAULT2EN_SHIFT (2U) 920 #define FTM_FLTCTRL_FAULT2EN_WIDTH (1U) 921 #define FTM_FLTCTRL_FAULT2EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FAULT2EN_SHIFT)) & FTM_FLTCTRL_FAULT2EN_MASK) 922 923 #define FTM_FLTCTRL_FAULT3EN_MASK (0x8U) 924 #define FTM_FLTCTRL_FAULT3EN_SHIFT (3U) 925 #define FTM_FLTCTRL_FAULT3EN_WIDTH (1U) 926 #define FTM_FLTCTRL_FAULT3EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FAULT3EN_SHIFT)) & FTM_FLTCTRL_FAULT3EN_MASK) 927 928 #define FTM_FLTCTRL_FFLTR0EN_MASK (0x10U) 929 #define FTM_FLTCTRL_FFLTR0EN_SHIFT (4U) 930 #define FTM_FLTCTRL_FFLTR0EN_WIDTH (1U) 931 #define FTM_FLTCTRL_FFLTR0EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FFLTR0EN_SHIFT)) & FTM_FLTCTRL_FFLTR0EN_MASK) 932 933 #define FTM_FLTCTRL_FFLTR1EN_MASK (0x20U) 934 #define FTM_FLTCTRL_FFLTR1EN_SHIFT (5U) 935 #define FTM_FLTCTRL_FFLTR1EN_WIDTH (1U) 936 #define FTM_FLTCTRL_FFLTR1EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FFLTR1EN_SHIFT)) & FTM_FLTCTRL_FFLTR1EN_MASK) 937 938 #define FTM_FLTCTRL_FFLTR2EN_MASK (0x40U) 939 #define FTM_FLTCTRL_FFLTR2EN_SHIFT (6U) 940 #define FTM_FLTCTRL_FFLTR2EN_WIDTH (1U) 941 #define FTM_FLTCTRL_FFLTR2EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FFLTR2EN_SHIFT)) & FTM_FLTCTRL_FFLTR2EN_MASK) 942 943 #define FTM_FLTCTRL_FFLTR3EN_MASK (0x80U) 944 #define FTM_FLTCTRL_FFLTR3EN_SHIFT (7U) 945 #define FTM_FLTCTRL_FFLTR3EN_WIDTH (1U) 946 #define FTM_FLTCTRL_FFLTR3EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FFLTR3EN_SHIFT)) & FTM_FLTCTRL_FFLTR3EN_MASK) 947 948 #define FTM_FLTCTRL_FFVAL_MASK (0xF00U) 949 #define FTM_FLTCTRL_FFVAL_SHIFT (8U) 950 #define FTM_FLTCTRL_FFVAL_WIDTH (4U) 951 #define FTM_FLTCTRL_FFVAL(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FFVAL_SHIFT)) & FTM_FLTCTRL_FFVAL_MASK) 952 953 #define FTM_FLTCTRL_FSTATE_MASK (0x8000U) 954 #define FTM_FLTCTRL_FSTATE_SHIFT (15U) 955 #define FTM_FLTCTRL_FSTATE_WIDTH (1U) 956 #define FTM_FLTCTRL_FSTATE(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FSTATE_SHIFT)) & FTM_FLTCTRL_FSTATE_MASK) 957 /*! @} */ 958 959 /*! @name QDCTRL - Quadrature Decoder Control And Status */ 960 /*! @{ */ 961 962 #define FTM_QDCTRL_QUADEN_MASK (0x1U) 963 #define FTM_QDCTRL_QUADEN_SHIFT (0U) 964 #define FTM_QDCTRL_QUADEN_WIDTH (1U) 965 #define FTM_QDCTRL_QUADEN(x) (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_QUADEN_SHIFT)) & FTM_QDCTRL_QUADEN_MASK) 966 967 #define FTM_QDCTRL_TOFDIR_MASK (0x2U) 968 #define FTM_QDCTRL_TOFDIR_SHIFT (1U) 969 #define FTM_QDCTRL_TOFDIR_WIDTH (1U) 970 #define FTM_QDCTRL_TOFDIR(x) (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_TOFDIR_SHIFT)) & FTM_QDCTRL_TOFDIR_MASK) 971 972 #define FTM_QDCTRL_QUADIR_MASK (0x4U) 973 #define FTM_QDCTRL_QUADIR_SHIFT (2U) 974 #define FTM_QDCTRL_QUADIR_WIDTH (1U) 975 #define FTM_QDCTRL_QUADIR(x) (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_QUADIR_SHIFT)) & FTM_QDCTRL_QUADIR_MASK) 976 977 #define FTM_QDCTRL_QUADMODE_MASK (0x8U) 978 #define FTM_QDCTRL_QUADMODE_SHIFT (3U) 979 #define FTM_QDCTRL_QUADMODE_WIDTH (1U) 980 #define FTM_QDCTRL_QUADMODE(x) (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_QUADMODE_SHIFT)) & FTM_QDCTRL_QUADMODE_MASK) 981 982 #define FTM_QDCTRL_PHBPOL_MASK (0x10U) 983 #define FTM_QDCTRL_PHBPOL_SHIFT (4U) 984 #define FTM_QDCTRL_PHBPOL_WIDTH (1U) 985 #define FTM_QDCTRL_PHBPOL(x) (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_PHBPOL_SHIFT)) & FTM_QDCTRL_PHBPOL_MASK) 986 987 #define FTM_QDCTRL_PHAPOL_MASK (0x20U) 988 #define FTM_QDCTRL_PHAPOL_SHIFT (5U) 989 #define FTM_QDCTRL_PHAPOL_WIDTH (1U) 990 #define FTM_QDCTRL_PHAPOL(x) (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_PHAPOL_SHIFT)) & FTM_QDCTRL_PHAPOL_MASK) 991 992 #define FTM_QDCTRL_PHBFLTREN_MASK (0x40U) 993 #define FTM_QDCTRL_PHBFLTREN_SHIFT (6U) 994 #define FTM_QDCTRL_PHBFLTREN_WIDTH (1U) 995 #define FTM_QDCTRL_PHBFLTREN(x) (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_PHBFLTREN_SHIFT)) & FTM_QDCTRL_PHBFLTREN_MASK) 996 997 #define FTM_QDCTRL_PHAFLTREN_MASK (0x80U) 998 #define FTM_QDCTRL_PHAFLTREN_SHIFT (7U) 999 #define FTM_QDCTRL_PHAFLTREN_WIDTH (1U) 1000 #define FTM_QDCTRL_PHAFLTREN(x) (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_PHAFLTREN_SHIFT)) & FTM_QDCTRL_PHAFLTREN_MASK) 1001 /*! @} */ 1002 1003 /*! @name CONF - Configuration */ 1004 /*! @{ */ 1005 1006 #define FTM_CONF_LDFQ_MASK (0x1FU) 1007 #define FTM_CONF_LDFQ_SHIFT (0U) 1008 #define FTM_CONF_LDFQ_WIDTH (5U) 1009 #define FTM_CONF_LDFQ(x) (((uint32_t)(((uint32_t)(x)) << FTM_CONF_LDFQ_SHIFT)) & FTM_CONF_LDFQ_MASK) 1010 1011 #define FTM_CONF_BDMMODE_MASK (0xC0U) 1012 #define FTM_CONF_BDMMODE_SHIFT (6U) 1013 #define FTM_CONF_BDMMODE_WIDTH (2U) 1014 #define FTM_CONF_BDMMODE(x) (((uint32_t)(((uint32_t)(x)) << FTM_CONF_BDMMODE_SHIFT)) & FTM_CONF_BDMMODE_MASK) 1015 1016 #define FTM_CONF_GTBEEN_MASK (0x200U) 1017 #define FTM_CONF_GTBEEN_SHIFT (9U) 1018 #define FTM_CONF_GTBEEN_WIDTH (1U) 1019 #define FTM_CONF_GTBEEN(x) (((uint32_t)(((uint32_t)(x)) << FTM_CONF_GTBEEN_SHIFT)) & FTM_CONF_GTBEEN_MASK) 1020 1021 #define FTM_CONF_GTBEOUT_MASK (0x400U) 1022 #define FTM_CONF_GTBEOUT_SHIFT (10U) 1023 #define FTM_CONF_GTBEOUT_WIDTH (1U) 1024 #define FTM_CONF_GTBEOUT(x) (((uint32_t)(((uint32_t)(x)) << FTM_CONF_GTBEOUT_SHIFT)) & FTM_CONF_GTBEOUT_MASK) 1025 1026 #define FTM_CONF_ITRIGR_MASK (0x800U) 1027 #define FTM_CONF_ITRIGR_SHIFT (11U) 1028 #define FTM_CONF_ITRIGR_WIDTH (1U) 1029 #define FTM_CONF_ITRIGR(x) (((uint32_t)(((uint32_t)(x)) << FTM_CONF_ITRIGR_SHIFT)) & FTM_CONF_ITRIGR_MASK) 1030 /*! @} */ 1031 1032 /*! @name FLTPOL - FTM Fault Input Polarity */ 1033 /*! @{ */ 1034 1035 #define FTM_FLTPOL_FLT0POL_MASK (0x1U) 1036 #define FTM_FLTPOL_FLT0POL_SHIFT (0U) 1037 #define FTM_FLTPOL_FLT0POL_WIDTH (1U) 1038 #define FTM_FLTPOL_FLT0POL(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTPOL_FLT0POL_SHIFT)) & FTM_FLTPOL_FLT0POL_MASK) 1039 1040 #define FTM_FLTPOL_FLT1POL_MASK (0x2U) 1041 #define FTM_FLTPOL_FLT1POL_SHIFT (1U) 1042 #define FTM_FLTPOL_FLT1POL_WIDTH (1U) 1043 #define FTM_FLTPOL_FLT1POL(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTPOL_FLT1POL_SHIFT)) & FTM_FLTPOL_FLT1POL_MASK) 1044 1045 #define FTM_FLTPOL_FLT2POL_MASK (0x4U) 1046 #define FTM_FLTPOL_FLT2POL_SHIFT (2U) 1047 #define FTM_FLTPOL_FLT2POL_WIDTH (1U) 1048 #define FTM_FLTPOL_FLT2POL(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTPOL_FLT2POL_SHIFT)) & FTM_FLTPOL_FLT2POL_MASK) 1049 1050 #define FTM_FLTPOL_FLT3POL_MASK (0x8U) 1051 #define FTM_FLTPOL_FLT3POL_SHIFT (3U) 1052 #define FTM_FLTPOL_FLT3POL_WIDTH (1U) 1053 #define FTM_FLTPOL_FLT3POL(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTPOL_FLT3POL_SHIFT)) & FTM_FLTPOL_FLT3POL_MASK) 1054 /*! @} */ 1055 1056 /*! @name SYNCONF - Synchronization Configuration */ 1057 /*! @{ */ 1058 1059 #define FTM_SYNCONF_HWTRIGMODE_MASK (0x1U) 1060 #define FTM_SYNCONF_HWTRIGMODE_SHIFT (0U) 1061 #define FTM_SYNCONF_HWTRIGMODE_WIDTH (1U) 1062 #define FTM_SYNCONF_HWTRIGMODE(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_HWTRIGMODE_SHIFT)) & FTM_SYNCONF_HWTRIGMODE_MASK) 1063 1064 #define FTM_SYNCONF_CNTINC_MASK (0x4U) 1065 #define FTM_SYNCONF_CNTINC_SHIFT (2U) 1066 #define FTM_SYNCONF_CNTINC_WIDTH (1U) 1067 #define FTM_SYNCONF_CNTINC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_CNTINC_SHIFT)) & FTM_SYNCONF_CNTINC_MASK) 1068 1069 #define FTM_SYNCONF_INVC_MASK (0x10U) 1070 #define FTM_SYNCONF_INVC_SHIFT (4U) 1071 #define FTM_SYNCONF_INVC_WIDTH (1U) 1072 #define FTM_SYNCONF_INVC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_INVC_SHIFT)) & FTM_SYNCONF_INVC_MASK) 1073 1074 #define FTM_SYNCONF_SWOC_MASK (0x20U) 1075 #define FTM_SYNCONF_SWOC_SHIFT (5U) 1076 #define FTM_SYNCONF_SWOC_WIDTH (1U) 1077 #define FTM_SYNCONF_SWOC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_SWOC_SHIFT)) & FTM_SYNCONF_SWOC_MASK) 1078 1079 #define FTM_SYNCONF_SYNCMODE_MASK (0x80U) 1080 #define FTM_SYNCONF_SYNCMODE_SHIFT (7U) 1081 #define FTM_SYNCONF_SYNCMODE_WIDTH (1U) 1082 #define FTM_SYNCONF_SYNCMODE(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_SYNCMODE_SHIFT)) & FTM_SYNCONF_SYNCMODE_MASK) 1083 1084 #define FTM_SYNCONF_SWRSTCNT_MASK (0x100U) 1085 #define FTM_SYNCONF_SWRSTCNT_SHIFT (8U) 1086 #define FTM_SYNCONF_SWRSTCNT_WIDTH (1U) 1087 #define FTM_SYNCONF_SWRSTCNT(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_SWRSTCNT_SHIFT)) & FTM_SYNCONF_SWRSTCNT_MASK) 1088 1089 #define FTM_SYNCONF_SWWRBUF_MASK (0x200U) 1090 #define FTM_SYNCONF_SWWRBUF_SHIFT (9U) 1091 #define FTM_SYNCONF_SWWRBUF_WIDTH (1U) 1092 #define FTM_SYNCONF_SWWRBUF(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_SWWRBUF_SHIFT)) & FTM_SYNCONF_SWWRBUF_MASK) 1093 1094 #define FTM_SYNCONF_SWOM_MASK (0x400U) 1095 #define FTM_SYNCONF_SWOM_SHIFT (10U) 1096 #define FTM_SYNCONF_SWOM_WIDTH (1U) 1097 #define FTM_SYNCONF_SWOM(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_SWOM_SHIFT)) & FTM_SYNCONF_SWOM_MASK) 1098 1099 #define FTM_SYNCONF_SWINVC_MASK (0x800U) 1100 #define FTM_SYNCONF_SWINVC_SHIFT (11U) 1101 #define FTM_SYNCONF_SWINVC_WIDTH (1U) 1102 #define FTM_SYNCONF_SWINVC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_SWINVC_SHIFT)) & FTM_SYNCONF_SWINVC_MASK) 1103 1104 #define FTM_SYNCONF_SWSOC_MASK (0x1000U) 1105 #define FTM_SYNCONF_SWSOC_SHIFT (12U) 1106 #define FTM_SYNCONF_SWSOC_WIDTH (1U) 1107 #define FTM_SYNCONF_SWSOC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_SWSOC_SHIFT)) & FTM_SYNCONF_SWSOC_MASK) 1108 1109 #define FTM_SYNCONF_HWRSTCNT_MASK (0x10000U) 1110 #define FTM_SYNCONF_HWRSTCNT_SHIFT (16U) 1111 #define FTM_SYNCONF_HWRSTCNT_WIDTH (1U) 1112 #define FTM_SYNCONF_HWRSTCNT(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_HWRSTCNT_SHIFT)) & FTM_SYNCONF_HWRSTCNT_MASK) 1113 1114 #define FTM_SYNCONF_HWWRBUF_MASK (0x20000U) 1115 #define FTM_SYNCONF_HWWRBUF_SHIFT (17U) 1116 #define FTM_SYNCONF_HWWRBUF_WIDTH (1U) 1117 #define FTM_SYNCONF_HWWRBUF(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_HWWRBUF_SHIFT)) & FTM_SYNCONF_HWWRBUF_MASK) 1118 1119 #define FTM_SYNCONF_HWOM_MASK (0x40000U) 1120 #define FTM_SYNCONF_HWOM_SHIFT (18U) 1121 #define FTM_SYNCONF_HWOM_WIDTH (1U) 1122 #define FTM_SYNCONF_HWOM(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_HWOM_SHIFT)) & FTM_SYNCONF_HWOM_MASK) 1123 1124 #define FTM_SYNCONF_HWINVC_MASK (0x80000U) 1125 #define FTM_SYNCONF_HWINVC_SHIFT (19U) 1126 #define FTM_SYNCONF_HWINVC_WIDTH (1U) 1127 #define FTM_SYNCONF_HWINVC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_HWINVC_SHIFT)) & FTM_SYNCONF_HWINVC_MASK) 1128 1129 #define FTM_SYNCONF_HWSOC_MASK (0x100000U) 1130 #define FTM_SYNCONF_HWSOC_SHIFT (20U) 1131 #define FTM_SYNCONF_HWSOC_WIDTH (1U) 1132 #define FTM_SYNCONF_HWSOC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_HWSOC_SHIFT)) & FTM_SYNCONF_HWSOC_MASK) 1133 /*! @} */ 1134 1135 /*! @name INVCTRL - FTM Inverting Control */ 1136 /*! @{ */ 1137 1138 #define FTM_INVCTRL_INV0EN_MASK (0x1U) 1139 #define FTM_INVCTRL_INV0EN_SHIFT (0U) 1140 #define FTM_INVCTRL_INV0EN_WIDTH (1U) 1141 #define FTM_INVCTRL_INV0EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_INVCTRL_INV0EN_SHIFT)) & FTM_INVCTRL_INV0EN_MASK) 1142 1143 #define FTM_INVCTRL_INV1EN_MASK (0x2U) 1144 #define FTM_INVCTRL_INV1EN_SHIFT (1U) 1145 #define FTM_INVCTRL_INV1EN_WIDTH (1U) 1146 #define FTM_INVCTRL_INV1EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_INVCTRL_INV1EN_SHIFT)) & FTM_INVCTRL_INV1EN_MASK) 1147 1148 #define FTM_INVCTRL_INV2EN_MASK (0x4U) 1149 #define FTM_INVCTRL_INV2EN_SHIFT (2U) 1150 #define FTM_INVCTRL_INV2EN_WIDTH (1U) 1151 #define FTM_INVCTRL_INV2EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_INVCTRL_INV2EN_SHIFT)) & FTM_INVCTRL_INV2EN_MASK) 1152 1153 #define FTM_INVCTRL_INV3EN_MASK (0x8U) 1154 #define FTM_INVCTRL_INV3EN_SHIFT (3U) 1155 #define FTM_INVCTRL_INV3EN_WIDTH (1U) 1156 #define FTM_INVCTRL_INV3EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_INVCTRL_INV3EN_SHIFT)) & FTM_INVCTRL_INV3EN_MASK) 1157 /*! @} */ 1158 1159 /*! @name SWOCTRL - FTM Software Output Control */ 1160 /*! @{ */ 1161 1162 #define FTM_SWOCTRL_CH0OC_MASK (0x1U) 1163 #define FTM_SWOCTRL_CH0OC_SHIFT (0U) 1164 #define FTM_SWOCTRL_CH0OC_WIDTH (1U) 1165 #define FTM_SWOCTRL_CH0OC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH0OC_SHIFT)) & FTM_SWOCTRL_CH0OC_MASK) 1166 1167 #define FTM_SWOCTRL_CH1OC_MASK (0x2U) 1168 #define FTM_SWOCTRL_CH1OC_SHIFT (1U) 1169 #define FTM_SWOCTRL_CH1OC_WIDTH (1U) 1170 #define FTM_SWOCTRL_CH1OC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH1OC_SHIFT)) & FTM_SWOCTRL_CH1OC_MASK) 1171 1172 #define FTM_SWOCTRL_CH2OC_MASK (0x4U) 1173 #define FTM_SWOCTRL_CH2OC_SHIFT (2U) 1174 #define FTM_SWOCTRL_CH2OC_WIDTH (1U) 1175 #define FTM_SWOCTRL_CH2OC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH2OC_SHIFT)) & FTM_SWOCTRL_CH2OC_MASK) 1176 1177 #define FTM_SWOCTRL_CH3OC_MASK (0x8U) 1178 #define FTM_SWOCTRL_CH3OC_SHIFT (3U) 1179 #define FTM_SWOCTRL_CH3OC_WIDTH (1U) 1180 #define FTM_SWOCTRL_CH3OC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH3OC_SHIFT)) & FTM_SWOCTRL_CH3OC_MASK) 1181 1182 #define FTM_SWOCTRL_CH4OC_MASK (0x10U) 1183 #define FTM_SWOCTRL_CH4OC_SHIFT (4U) 1184 #define FTM_SWOCTRL_CH4OC_WIDTH (1U) 1185 #define FTM_SWOCTRL_CH4OC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH4OC_SHIFT)) & FTM_SWOCTRL_CH4OC_MASK) 1186 1187 #define FTM_SWOCTRL_CH5OC_MASK (0x20U) 1188 #define FTM_SWOCTRL_CH5OC_SHIFT (5U) 1189 #define FTM_SWOCTRL_CH5OC_WIDTH (1U) 1190 #define FTM_SWOCTRL_CH5OC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH5OC_SHIFT)) & FTM_SWOCTRL_CH5OC_MASK) 1191 1192 #define FTM_SWOCTRL_CH6OC_MASK (0x40U) 1193 #define FTM_SWOCTRL_CH6OC_SHIFT (6U) 1194 #define FTM_SWOCTRL_CH6OC_WIDTH (1U) 1195 #define FTM_SWOCTRL_CH6OC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH6OC_SHIFT)) & FTM_SWOCTRL_CH6OC_MASK) 1196 1197 #define FTM_SWOCTRL_CH7OC_MASK (0x80U) 1198 #define FTM_SWOCTRL_CH7OC_SHIFT (7U) 1199 #define FTM_SWOCTRL_CH7OC_WIDTH (1U) 1200 #define FTM_SWOCTRL_CH7OC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH7OC_SHIFT)) & FTM_SWOCTRL_CH7OC_MASK) 1201 1202 #define FTM_SWOCTRL_CH0OCV_MASK (0x100U) 1203 #define FTM_SWOCTRL_CH0OCV_SHIFT (8U) 1204 #define FTM_SWOCTRL_CH0OCV_WIDTH (1U) 1205 #define FTM_SWOCTRL_CH0OCV(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH0OCV_SHIFT)) & FTM_SWOCTRL_CH0OCV_MASK) 1206 1207 #define FTM_SWOCTRL_CH1OCV_MASK (0x200U) 1208 #define FTM_SWOCTRL_CH1OCV_SHIFT (9U) 1209 #define FTM_SWOCTRL_CH1OCV_WIDTH (1U) 1210 #define FTM_SWOCTRL_CH1OCV(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH1OCV_SHIFT)) & FTM_SWOCTRL_CH1OCV_MASK) 1211 1212 #define FTM_SWOCTRL_CH2OCV_MASK (0x400U) 1213 #define FTM_SWOCTRL_CH2OCV_SHIFT (10U) 1214 #define FTM_SWOCTRL_CH2OCV_WIDTH (1U) 1215 #define FTM_SWOCTRL_CH2OCV(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH2OCV_SHIFT)) & FTM_SWOCTRL_CH2OCV_MASK) 1216 1217 #define FTM_SWOCTRL_CH3OCV_MASK (0x800U) 1218 #define FTM_SWOCTRL_CH3OCV_SHIFT (11U) 1219 #define FTM_SWOCTRL_CH3OCV_WIDTH (1U) 1220 #define FTM_SWOCTRL_CH3OCV(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH3OCV_SHIFT)) & FTM_SWOCTRL_CH3OCV_MASK) 1221 1222 #define FTM_SWOCTRL_CH4OCV_MASK (0x1000U) 1223 #define FTM_SWOCTRL_CH4OCV_SHIFT (12U) 1224 #define FTM_SWOCTRL_CH4OCV_WIDTH (1U) 1225 #define FTM_SWOCTRL_CH4OCV(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH4OCV_SHIFT)) & FTM_SWOCTRL_CH4OCV_MASK) 1226 1227 #define FTM_SWOCTRL_CH5OCV_MASK (0x2000U) 1228 #define FTM_SWOCTRL_CH5OCV_SHIFT (13U) 1229 #define FTM_SWOCTRL_CH5OCV_WIDTH (1U) 1230 #define FTM_SWOCTRL_CH5OCV(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH5OCV_SHIFT)) & FTM_SWOCTRL_CH5OCV_MASK) 1231 1232 #define FTM_SWOCTRL_CH6OCV_MASK (0x4000U) 1233 #define FTM_SWOCTRL_CH6OCV_SHIFT (14U) 1234 #define FTM_SWOCTRL_CH6OCV_WIDTH (1U) 1235 #define FTM_SWOCTRL_CH6OCV(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH6OCV_SHIFT)) & FTM_SWOCTRL_CH6OCV_MASK) 1236 1237 #define FTM_SWOCTRL_CH7OCV_MASK (0x8000U) 1238 #define FTM_SWOCTRL_CH7OCV_SHIFT (15U) 1239 #define FTM_SWOCTRL_CH7OCV_WIDTH (1U) 1240 #define FTM_SWOCTRL_CH7OCV(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH7OCV_SHIFT)) & FTM_SWOCTRL_CH7OCV_MASK) 1241 /*! @} */ 1242 1243 /*! @name PWMLOAD - FTM PWM Load */ 1244 /*! @{ */ 1245 1246 #define FTM_PWMLOAD_CH0SEL_MASK (0x1U) 1247 #define FTM_PWMLOAD_CH0SEL_SHIFT (0U) 1248 #define FTM_PWMLOAD_CH0SEL_WIDTH (1U) 1249 #define FTM_PWMLOAD_CH0SEL(x) (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH0SEL_SHIFT)) & FTM_PWMLOAD_CH0SEL_MASK) 1250 1251 #define FTM_PWMLOAD_CH1SEL_MASK (0x2U) 1252 #define FTM_PWMLOAD_CH1SEL_SHIFT (1U) 1253 #define FTM_PWMLOAD_CH1SEL_WIDTH (1U) 1254 #define FTM_PWMLOAD_CH1SEL(x) (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH1SEL_SHIFT)) & FTM_PWMLOAD_CH1SEL_MASK) 1255 1256 #define FTM_PWMLOAD_CH2SEL_MASK (0x4U) 1257 #define FTM_PWMLOAD_CH2SEL_SHIFT (2U) 1258 #define FTM_PWMLOAD_CH2SEL_WIDTH (1U) 1259 #define FTM_PWMLOAD_CH2SEL(x) (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH2SEL_SHIFT)) & FTM_PWMLOAD_CH2SEL_MASK) 1260 1261 #define FTM_PWMLOAD_CH3SEL_MASK (0x8U) 1262 #define FTM_PWMLOAD_CH3SEL_SHIFT (3U) 1263 #define FTM_PWMLOAD_CH3SEL_WIDTH (1U) 1264 #define FTM_PWMLOAD_CH3SEL(x) (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH3SEL_SHIFT)) & FTM_PWMLOAD_CH3SEL_MASK) 1265 1266 #define FTM_PWMLOAD_CH4SEL_MASK (0x10U) 1267 #define FTM_PWMLOAD_CH4SEL_SHIFT (4U) 1268 #define FTM_PWMLOAD_CH4SEL_WIDTH (1U) 1269 #define FTM_PWMLOAD_CH4SEL(x) (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH4SEL_SHIFT)) & FTM_PWMLOAD_CH4SEL_MASK) 1270 1271 #define FTM_PWMLOAD_CH5SEL_MASK (0x20U) 1272 #define FTM_PWMLOAD_CH5SEL_SHIFT (5U) 1273 #define FTM_PWMLOAD_CH5SEL_WIDTH (1U) 1274 #define FTM_PWMLOAD_CH5SEL(x) (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH5SEL_SHIFT)) & FTM_PWMLOAD_CH5SEL_MASK) 1275 1276 #define FTM_PWMLOAD_CH6SEL_MASK (0x40U) 1277 #define FTM_PWMLOAD_CH6SEL_SHIFT (6U) 1278 #define FTM_PWMLOAD_CH6SEL_WIDTH (1U) 1279 #define FTM_PWMLOAD_CH6SEL(x) (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH6SEL_SHIFT)) & FTM_PWMLOAD_CH6SEL_MASK) 1280 1281 #define FTM_PWMLOAD_CH7SEL_MASK (0x80U) 1282 #define FTM_PWMLOAD_CH7SEL_SHIFT (7U) 1283 #define FTM_PWMLOAD_CH7SEL_WIDTH (1U) 1284 #define FTM_PWMLOAD_CH7SEL(x) (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH7SEL_SHIFT)) & FTM_PWMLOAD_CH7SEL_MASK) 1285 1286 #define FTM_PWMLOAD_HCSEL_MASK (0x100U) 1287 #define FTM_PWMLOAD_HCSEL_SHIFT (8U) 1288 #define FTM_PWMLOAD_HCSEL_WIDTH (1U) 1289 #define FTM_PWMLOAD_HCSEL(x) (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_HCSEL_SHIFT)) & FTM_PWMLOAD_HCSEL_MASK) 1290 1291 #define FTM_PWMLOAD_LDOK_MASK (0x200U) 1292 #define FTM_PWMLOAD_LDOK_SHIFT (9U) 1293 #define FTM_PWMLOAD_LDOK_WIDTH (1U) 1294 #define FTM_PWMLOAD_LDOK(x) (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_LDOK_SHIFT)) & FTM_PWMLOAD_LDOK_MASK) 1295 1296 #define FTM_PWMLOAD_GLEN_MASK (0x400U) 1297 #define FTM_PWMLOAD_GLEN_SHIFT (10U) 1298 #define FTM_PWMLOAD_GLEN_WIDTH (1U) 1299 #define FTM_PWMLOAD_GLEN(x) (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_GLEN_SHIFT)) & FTM_PWMLOAD_GLEN_MASK) 1300 1301 #define FTM_PWMLOAD_GLDOK_MASK (0x800U) 1302 #define FTM_PWMLOAD_GLDOK_SHIFT (11U) 1303 #define FTM_PWMLOAD_GLDOK_WIDTH (1U) 1304 #define FTM_PWMLOAD_GLDOK(x) (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_GLDOK_SHIFT)) & FTM_PWMLOAD_GLDOK_MASK) 1305 /*! @} */ 1306 1307 /*! @name HCR - Half Cycle Register */ 1308 /*! @{ */ 1309 1310 #define FTM_HCR_HCVAL_MASK (0xFFFFU) 1311 #define FTM_HCR_HCVAL_SHIFT (0U) 1312 #define FTM_HCR_HCVAL_WIDTH (16U) 1313 #define FTM_HCR_HCVAL(x) (((uint32_t)(((uint32_t)(x)) << FTM_HCR_HCVAL_SHIFT)) & FTM_HCR_HCVAL_MASK) 1314 /*! @} */ 1315 1316 /*! @name PAIR0DEADTIME - Pair 0 Deadtime Configuration */ 1317 /*! @{ */ 1318 1319 #define FTM_PAIR0DEADTIME_DTVAL_MASK (0x3FU) 1320 #define FTM_PAIR0DEADTIME_DTVAL_SHIFT (0U) 1321 #define FTM_PAIR0DEADTIME_DTVAL_WIDTH (6U) 1322 #define FTM_PAIR0DEADTIME_DTVAL(x) (((uint32_t)(((uint32_t)(x)) << FTM_PAIR0DEADTIME_DTVAL_SHIFT)) & FTM_PAIR0DEADTIME_DTVAL_MASK) 1323 1324 #define FTM_PAIR0DEADTIME_DTPS_MASK (0xC0U) 1325 #define FTM_PAIR0DEADTIME_DTPS_SHIFT (6U) 1326 #define FTM_PAIR0DEADTIME_DTPS_WIDTH (2U) 1327 #define FTM_PAIR0DEADTIME_DTPS(x) (((uint32_t)(((uint32_t)(x)) << FTM_PAIR0DEADTIME_DTPS_SHIFT)) & FTM_PAIR0DEADTIME_DTPS_MASK) 1328 1329 #define FTM_PAIR0DEADTIME_DTVALEX_MASK (0xF0000U) 1330 #define FTM_PAIR0DEADTIME_DTVALEX_SHIFT (16U) 1331 #define FTM_PAIR0DEADTIME_DTVALEX_WIDTH (4U) 1332 #define FTM_PAIR0DEADTIME_DTVALEX(x) (((uint32_t)(((uint32_t)(x)) << FTM_PAIR0DEADTIME_DTVALEX_SHIFT)) & FTM_PAIR0DEADTIME_DTVALEX_MASK) 1333 /*! @} */ 1334 1335 /*! @name PAIR1DEADTIME - Pair 1 Deadtime Configuration */ 1336 /*! @{ */ 1337 1338 #define FTM_PAIR1DEADTIME_DTVAL_MASK (0x3FU) 1339 #define FTM_PAIR1DEADTIME_DTVAL_SHIFT (0U) 1340 #define FTM_PAIR1DEADTIME_DTVAL_WIDTH (6U) 1341 #define FTM_PAIR1DEADTIME_DTVAL(x) (((uint32_t)(((uint32_t)(x)) << FTM_PAIR1DEADTIME_DTVAL_SHIFT)) & FTM_PAIR1DEADTIME_DTVAL_MASK) 1342 1343 #define FTM_PAIR1DEADTIME_DTPS_MASK (0xC0U) 1344 #define FTM_PAIR1DEADTIME_DTPS_SHIFT (6U) 1345 #define FTM_PAIR1DEADTIME_DTPS_WIDTH (2U) 1346 #define FTM_PAIR1DEADTIME_DTPS(x) (((uint32_t)(((uint32_t)(x)) << FTM_PAIR1DEADTIME_DTPS_SHIFT)) & FTM_PAIR1DEADTIME_DTPS_MASK) 1347 1348 #define FTM_PAIR1DEADTIME_DTVALEX_MASK (0xF0000U) 1349 #define FTM_PAIR1DEADTIME_DTVALEX_SHIFT (16U) 1350 #define FTM_PAIR1DEADTIME_DTVALEX_WIDTH (4U) 1351 #define FTM_PAIR1DEADTIME_DTVALEX(x) (((uint32_t)(((uint32_t)(x)) << FTM_PAIR1DEADTIME_DTVALEX_SHIFT)) & FTM_PAIR1DEADTIME_DTVALEX_MASK) 1352 /*! @} */ 1353 1354 /*! @name PAIR2DEADTIME - Pair 2 Deadtime Configuration */ 1355 /*! @{ */ 1356 1357 #define FTM_PAIR2DEADTIME_DTVAL_MASK (0x3FU) 1358 #define FTM_PAIR2DEADTIME_DTVAL_SHIFT (0U) 1359 #define FTM_PAIR2DEADTIME_DTVAL_WIDTH (6U) 1360 #define FTM_PAIR2DEADTIME_DTVAL(x) (((uint32_t)(((uint32_t)(x)) << FTM_PAIR2DEADTIME_DTVAL_SHIFT)) & FTM_PAIR2DEADTIME_DTVAL_MASK) 1361 1362 #define FTM_PAIR2DEADTIME_DTPS_MASK (0xC0U) 1363 #define FTM_PAIR2DEADTIME_DTPS_SHIFT (6U) 1364 #define FTM_PAIR2DEADTIME_DTPS_WIDTH (2U) 1365 #define FTM_PAIR2DEADTIME_DTPS(x) (((uint32_t)(((uint32_t)(x)) << FTM_PAIR2DEADTIME_DTPS_SHIFT)) & FTM_PAIR2DEADTIME_DTPS_MASK) 1366 1367 #define FTM_PAIR2DEADTIME_DTVALEX_MASK (0xF0000U) 1368 #define FTM_PAIR2DEADTIME_DTVALEX_SHIFT (16U) 1369 #define FTM_PAIR2DEADTIME_DTVALEX_WIDTH (4U) 1370 #define FTM_PAIR2DEADTIME_DTVALEX(x) (((uint32_t)(((uint32_t)(x)) << FTM_PAIR2DEADTIME_DTVALEX_SHIFT)) & FTM_PAIR2DEADTIME_DTVALEX_MASK) 1371 /*! @} */ 1372 1373 /*! @name PAIR3DEADTIME - Pair 3 Deadtime Configuration */ 1374 /*! @{ */ 1375 1376 #define FTM_PAIR3DEADTIME_DTVAL_MASK (0x3FU) 1377 #define FTM_PAIR3DEADTIME_DTVAL_SHIFT (0U) 1378 #define FTM_PAIR3DEADTIME_DTVAL_WIDTH (6U) 1379 #define FTM_PAIR3DEADTIME_DTVAL(x) (((uint32_t)(((uint32_t)(x)) << FTM_PAIR3DEADTIME_DTVAL_SHIFT)) & FTM_PAIR3DEADTIME_DTVAL_MASK) 1380 1381 #define FTM_PAIR3DEADTIME_DTPS_MASK (0xC0U) 1382 #define FTM_PAIR3DEADTIME_DTPS_SHIFT (6U) 1383 #define FTM_PAIR3DEADTIME_DTPS_WIDTH (2U) 1384 #define FTM_PAIR3DEADTIME_DTPS(x) (((uint32_t)(((uint32_t)(x)) << FTM_PAIR3DEADTIME_DTPS_SHIFT)) & FTM_PAIR3DEADTIME_DTPS_MASK) 1385 1386 #define FTM_PAIR3DEADTIME_DTVALEX_MASK (0xF0000U) 1387 #define FTM_PAIR3DEADTIME_DTVALEX_SHIFT (16U) 1388 #define FTM_PAIR3DEADTIME_DTVALEX_WIDTH (4U) 1389 #define FTM_PAIR3DEADTIME_DTVALEX(x) (((uint32_t)(((uint32_t)(x)) << FTM_PAIR3DEADTIME_DTVALEX_SHIFT)) & FTM_PAIR3DEADTIME_DTVALEX_MASK) 1390 /*! @} */ 1391 1392 /*! @name MOD_MIRROR - Mirror of Modulo Value */ 1393 /*! @{ */ 1394 1395 #define FTM_MOD_MIRROR_FRACMOD_MASK (0xF800U) 1396 #define FTM_MOD_MIRROR_FRACMOD_SHIFT (11U) 1397 #define FTM_MOD_MIRROR_FRACMOD_WIDTH (5U) 1398 #define FTM_MOD_MIRROR_FRACMOD(x) (((uint32_t)(((uint32_t)(x)) << FTM_MOD_MIRROR_FRACMOD_SHIFT)) & FTM_MOD_MIRROR_FRACMOD_MASK) 1399 1400 #define FTM_MOD_MIRROR_MOD_MASK (0xFFFF0000U) 1401 #define FTM_MOD_MIRROR_MOD_SHIFT (16U) 1402 #define FTM_MOD_MIRROR_MOD_WIDTH (16U) 1403 #define FTM_MOD_MIRROR_MOD(x) (((uint32_t)(((uint32_t)(x)) << FTM_MOD_MIRROR_MOD_SHIFT)) & FTM_MOD_MIRROR_MOD_MASK) 1404 /*! @} */ 1405 1406 /*! @name CV_MIRROR - Mirror of Channel (n) Match Value */ 1407 /*! @{ */ 1408 1409 #define FTM_CV_MIRROR_FRACVAL_MASK (0xF800U) 1410 #define FTM_CV_MIRROR_FRACVAL_SHIFT (11U) 1411 #define FTM_CV_MIRROR_FRACVAL_WIDTH (5U) 1412 #define FTM_CV_MIRROR_FRACVAL(x) (((uint32_t)(((uint32_t)(x)) << FTM_CV_MIRROR_FRACVAL_SHIFT)) & FTM_CV_MIRROR_FRACVAL_MASK) 1413 1414 #define FTM_CV_MIRROR_VAL_MASK (0xFFFF0000U) 1415 #define FTM_CV_MIRROR_VAL_SHIFT (16U) 1416 #define FTM_CV_MIRROR_VAL_WIDTH (16U) 1417 #define FTM_CV_MIRROR_VAL(x) (((uint32_t)(((uint32_t)(x)) << FTM_CV_MIRROR_VAL_SHIFT)) & FTM_CV_MIRROR_VAL_MASK) 1418 /*! @} */ 1419 1420 /*! 1421 * @} 1422 */ /* end of group FTM_Register_Masks */ 1423 1424 /*! 1425 * @} 1426 */ /* end of group FTM_Peripheral_Access_Layer */ 1427 1428 #endif /* #if !defined(S32K148_FTM_H_) */ 1429
