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Searched refs:PLLODIV (Results 1 – 8 of 8) sorted by relevance

/hal_nxp-3.5.0/s32/drivers/s32k3/Mcu/src/
DClock_Ip_Divider.c241 …CLOCK_IP_DEV_ASSERT(!(Clock_Ip_apxPll[Instance].PllInstance->PLLODIV[DividerIndex] & PLL_PLLODIV_D… in Clock_Ip_SetPllPll0divDeDivOutput()
245 RegValue = Clock_Ip_apxPll[Instance].PllInstance->PLLODIV[DividerIndex]; in Clock_Ip_SetPllPll0divDeDivOutput()
249 Clock_Ip_apxPll[Instance].PllInstance->PLLODIV[DividerIndex] = RegValue; in Clock_Ip_SetPllPll0divDeDivOutput()
DClock_Ip_Pll.c173 Clock_Ip_apxPll[Instance].PllInstance->PLLODIV[DividerIndex] &= ~PLL_PLLODIV_DE_MASK; in Clock_Ip_ResetPllRdivMfiMfnOdiv2SdmenSsscgbypSpreadctlStepnoStepsize()
310 Clock_Ip_apxPll[Instance].PllInstance->PLLODIV[DividerIndex] &= ~PLL_PLLODIV_DE_MASK; in Clock_Ip_ResetPllRdivMfiMfnOdiv2Sdmen()
DClock_Ip_Frequency.c1850 …Frequency &= Clock_Ip_au32EnableDivider[((IP_PLL->PLLODIV[0U] & PLL_PLLODIV_DE_MASK) >> PLL_PLLODI… in Clock_Ip_Get_PLL_PHI0_Frequency()
1851 …Frequency /= (((IP_PLL->PLLODIV[0U] & PLL_PLLODIV_DIV_MASK) >> PLL_PLLODIV_DIV_SHIFT) + 1U); … in Clock_Ip_Get_PLL_PHI0_Frequency()
1857 …Frequency &= Clock_Ip_au32EnableDivider[((IP_PLL->PLLODIV[1U] & PLL_PLLODIV_DE_MASK) >> PLL_PLLODI… in Clock_Ip_Get_PLL_PHI1_Frequency()
1858 …Frequency /= (((IP_PLL->PLLODIV[1U] & PLL_PLLODIV_DIV_MASK) >> PLL_PLLODIV_DIV_SHIFT) + 1U); … in Clock_Ip_Get_PLL_PHI1_Frequency()
1865 …Frequency &= Clock_Ip_au32EnableDivider[((IP_PLL_AUX->PLLODIV[0U] & PLL_PLLODIV_DE_MASK) >> PLL_PL… in Clock_Ip_Get_PLLAUX_PHI0_Frequency()
1866 …Frequency /= (((IP_PLL_AUX->PLLODIV[0U] & PLL_PLLODIV_DIV_MASK) >> PLL_PLLODIV_DIV_SHIFT) + 1U); … in Clock_Ip_Get_PLLAUX_PHI0_Frequency()
1874 …Frequency &= Clock_Ip_au32EnableDivider[((IP_PLL_AUX->PLLODIV[1U] & PLL_PLLODIV_DE_MASK) >> PLL_PL… in Clock_Ip_Get_PLLAUX_PHI1_Frequency()
1875 …Frequency /= (((IP_PLL_AUX->PLLODIV[1U] & PLL_PLLODIV_DIV_MASK) >> PLL_PLLODIV_DIV_SHIFT) + 1U); … in Clock_Ip_Get_PLLAUX_PHI1_Frequency()
1883 …Frequency &= Clock_Ip_au32EnableDivider[((IP_PLL_AUX->PLLODIV[2U] & PLL_PLLODIV_DE_MASK) >> PLL_PL… in Clock_Ip_Get_PLLAUX_PHI2_Frequency()
1884 …Frequency /= (((IP_PLL_AUX->PLLODIV[2U] & PLL_PLLODIV_DIV_MASK) >> PLL_PLLODIV_DIV_SHIFT) + 1U); … in Clock_Ip_Get_PLLAUX_PHI2_Frequency()
/hal_nxp-3.5.0/s32/drivers/s32ze/Mcu/src/
DClock_Ip_Divider.c273 …CLOCK_IP_DEV_ASSERT(!(Clock_Ip_apxPll[Instance].PllInstance->PLLODIV[DividerIndex] & PLLDIG_PLLODI… in Clock_Ip_SetPlldigPll0divDeDivOutput()
278 RegValue = Clock_Ip_apxPll[Instance].PllInstance->PLLODIV[DividerIndex]; in Clock_Ip_SetPlldigPll0divDeDivOutput()
282 Clock_Ip_apxPll[Instance].PllInstance->PLLODIV[DividerIndex] = RegValue; in Clock_Ip_SetPlldigPll0divDeDivOutput()
DClock_Ip_Frequency.c1414 …Frequency &= Clock_Ip_au32EnableDivider[((IP_CORE_PLL->PLLODIV[0U] & PLLDIG_PLLODIV_DE_MASK) >> PL… in Clock_Ip_Get_COREPLL_PHI0_Frequency()
1415 …Frequency /= (((IP_CORE_PLL->PLLODIV[0U] & PLLDIG_PLLODIV_DIV_MASK) >> PLLDIG_PLLODIV_DIV_SHIFT) +… in Clock_Ip_Get_COREPLL_PHI0_Frequency()
1483 …Frequency &= Clock_Ip_au32EnableDivider[((IP_PERIPH_PLL->PLLODIV[0U] & PLLDIG_PLLODIV_DE_MASK) >> … in Clock_Ip_Get_PERIPHPLL_PHI0_Frequency()
1484 …Frequency /= (((IP_PERIPH_PLL->PLLODIV[0U] & PLLDIG_PLLODIV_DIV_MASK) >> PLLDIG_PLLODIV_DIV_SHIFT)… in Clock_Ip_Get_PERIPHPLL_PHI0_Frequency()
1492 …Frequency &= Clock_Ip_au32EnableDivider[((IP_PERIPH_PLL->PLLODIV[1U] & PLLDIG_PLLODIV_DE_MASK) >> … in Clock_Ip_Get_PERIPHPLL_PHI1_Frequency()
1493 …Frequency /= (((IP_PERIPH_PLL->PLLODIV[1U] & PLLDIG_PLLODIV_DIV_MASK) >> PLLDIG_PLLODIV_DIV_SHIFT)… in Clock_Ip_Get_PERIPHPLL_PHI1_Frequency()
1500 …Frequency &= Clock_Ip_au32EnableDivider[((IP_PERIPH_PLL->PLLODIV[2U] & PLLDIG_PLLODIV_DE_MASK) >> … in Clock_Ip_Get_PERIPHPLL_PHI2_Frequency()
1501 …Frequency /= (((IP_PERIPH_PLL->PLLODIV[2U] & PLLDIG_PLLODIV_DIV_MASK) >> PLLDIG_PLLODIV_DIV_SHIFT)… in Clock_Ip_Get_PERIPHPLL_PHI2_Frequency()
1508 …Frequency &= Clock_Ip_au32EnableDivider[((IP_PERIPH_PLL->PLLODIV[3U] & PLLDIG_PLLODIV_DE_MASK) >> … in Clock_Ip_Get_PERIPHPLL_PHI3_Frequency()
1509 …Frequency /= (((IP_PERIPH_PLL->PLLODIV[3U] & PLLDIG_PLLODIV_DIV_MASK) >> PLLDIG_PLLODIV_DIV_SHIFT)… in Clock_Ip_Get_PERIPHPLL_PHI3_Frequency()
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DClock_Ip_Pll.c176 Clock_Ip_apxPll[Instance].PllInstance->PLLODIV[DividerIndex] &= ~PLLDIG_PLLODIV_DE_MASK; in Clock_Ip_ResetPlldigRdivMfiMfnSdmenSsscgbypSpreadctlStepnoStepsize()
286 Clock_Ip_apxPll[Instance].PllInstance->PLLODIV[DividerIndex] &= ~PLLDIG_PLLODIV_DE_MASK; in Clock_Ip_ResetPlldigRdivMfiMfnSdmen()
/hal_nxp-3.5.0/s32/drivers/s32ze/BaseNXP/header/
DS32Z2_PLLDIG.h84 …__IO uint32_t PLLODIV[PLLDIG_PLLODIV_COUNT]; /**< PLL Output Divider, array offset: 0x80, arra… member
/hal_nxp-3.5.0/s32/drivers/s32k3/BaseNXP/header/
DS32K344_PLL.h84 …__IO uint32_t PLLODIV[PLL_PLLODIV_COUNT]; /**< PLL Output Divider, array offset: 0x80, arra… member