Searched refs:PLLCR (Results 1 – 7 of 7) sorted by relevance
180 Clock_Ip_apxPll[Instance].PllInstance->PLLCR |= PLLDIG_PLLCR_PLLPD_MASK; in Clock_Ip_ResetPlldigRdivMfiMfnSdmenSsscgbypSpreadctlStepnoStepsize()235 if (0U == (Clock_Ip_apxPll[Instance].PllInstance->PLLCR & PLLDIG_PLLCR_PLLPD_MASK)) in Clock_Ip_CompletePlldigRdivMfiMfnSdmenSsscgbypSpreadctlStepnoStepsize()265 Clock_Ip_apxPll[Instance].PllInstance->PLLCR &= ~PLLDIG_PLLCR_PLLPD_MASK; in Clock_Ip_EnablePlldigRdivMfiMfnSdmenSsscgbypSpreadctlStepnoStepsize()290 Clock_Ip_apxPll[Instance].PllInstance->PLLCR |= PLLDIG_PLLCR_PLLPD_MASK; in Clock_Ip_ResetPlldigRdivMfiMfnSdmen()337 if (0U == (Clock_Ip_apxPll[Instance].PllInstance->PLLCR & PLLDIG_PLLCR_PLLPD_MASK)) in Clock_Ip_CompletePlldigRdivMfiMfnSdmen()367 Clock_Ip_apxPll[Instance].PllInstance->PLLCR &= ~PLLDIG_PLLCR_PLLPD_MASK; in Clock_Ip_EnablePlldigRdivMfiMfnSdmen()386 Clock_Ip_apxLfastPll[Instance].PllInstance->PLLCR |= LFAST_PLLCR_SWPOFF(1); in Clock_Ip_ResetLfastPLL()390 Clock_Ip_apxLfastPll[Instance].PllInstance->PLLCR &= (~((uint32)LFAST_PLLCR_FBDIV_MASK)); in Clock_Ip_ResetLfastPLL()392 Clock_Ip_apxLfastPll[Instance].PllInstance->PLLCR &= (~((uint32)LFAST_PLLCR_PREDIV_MASK)); in Clock_Ip_ResetLfastPLL()394 Clock_Ip_apxLfastPll[Instance].PllInstance->PLLCR &= (~((uint32)LFAST_PLLCR_FDIVEN_MASK)); in Clock_Ip_ResetLfastPLL()[all …]
243 if ((IP_CORE_PLL->PLLCR & PLLDIG_PLLCR_PLLPD_MASK) != 0U) /* if CORE_PLL is not enabled */ in Clock_Ip_SpecificPlatformInitClock()248 …IP_CORE_PLL->PLLCR &= ~PLLDIG_PLLCR_PLLPD_MASK; /* Start CORE_PLL */ in Clock_Ip_SpecificPlatformInitClock()251 … if ((IP_PERIPH_PLL->PLLCR & PLLDIG_PLLCR_PLLPD_MASK) != 0U) /* if PERIPH_PLL is not enabled */ in Clock_Ip_SpecificPlatformInitClock()256 …IP_PERIPH_PLL->PLLCR &= ~PLLDIG_PLLCR_PLLPD_MASK; /* Start PERIPH_P… in Clock_Ip_SpecificPlatformInitClock()281 if ((IP_CORE_PLL->PLLCR & PLLDIG_PLLCR_PLLPD_MASK) != 0U) /* if CORE_PLL is not enabled */ in Clock_Ip_SpecificPlatformInitClock()286 …IP_CORE_PLL->PLLCR &= ~PLLDIG_PLLCR_PLLPD_MASK; /* Start CORE_PLL */ in Clock_Ip_SpecificPlatformInitClock()301 … if ((IP_PERIPH_PLL->PLLCR & PLLDIG_PLLCR_PLLPD_MASK) != 0U) /* if PERIPH_PLL is not enabled */ in Clock_Ip_SpecificPlatformInitClock()306 …IP_PERIPH_PLL->PLLCR &= ~PLLDIG_PLLCR_PLLPD_MASK; /* Start PERIPH_P… in Clock_Ip_SpecificPlatformInitClock()
4042 …Prediv = ((Base->PLLCR & LFAST_PLLCR_PREDIV_MASK) >> LFAST_PLLCR_PREDIV_SHIFT) + 1U; … in LFAST_PLL_VCO()4043 …Fbdiv = ((Base->PLLCR & LFAST_PLLCR_FBDIV_MASK) >> LFAST_PLLCR_FBDIV_SHIFT); /* mu… in LFAST_PLL_VCO()4044 …PllMode = ((Base->PLLCR & LFAST_PLLCR_FDIVEN_MASK) >> LFAST_PLLCR_FDIVEN_SHIFT); /* Pl… in LFAST_PLL_VCO()
176 Clock_Ip_apxPll[Instance].PllInstance->PLLCR |= PLL_PLLCR_PLLPD_MASK; in Clock_Ip_ResetPllRdivMfiMfnOdiv2SdmenSsscgbypSpreadctlStepnoStepsize()220 Clock_Ip_apxPll[Instance].PllInstance->PLLCR &= ~PLL_PLLCR_PLLPD_MASK; in Clock_Ip_SetPllRdivMfiMfnOdiv2SdmenSsscgbypSpreadctlStepnoStepsize()241 if (0U == (Clock_Ip_apxPll[Instance].PllInstance->PLLCR & PLL_PLLCR_PLLPD_MASK)) in Clock_Ip_CompletePllRdivMfiMfnOdiv2SdmenSsscgbypSpreadctlStepnoStepsize()278 Clock_Ip_apxPll[Instance].PllInstance->PLLCR &= ~PLL_PLLCR_PLLPD_MASK; in Clock_Ip_EnablePllRdivMfiMfnOdiv2SdmenSsscgbypSpreadctlStepnoStepsize()313 Clock_Ip_apxPll[Instance].PllInstance->PLLCR |= PLL_PLLCR_PLLPD_MASK; in Clock_Ip_ResetPllRdivMfiMfnOdiv2Sdmen()340 Clock_Ip_apxPll[Instance].PllInstance->PLLCR &= ~PLL_PLLCR_PLLPD_MASK; in Clock_Ip_SetPllRdivMfiMfnOdiv2Sdmen()361 if (0U == (Clock_Ip_apxPll[Instance].PllInstance->PLLCR & PLL_PLLCR_PLLPD_MASK)) in Clock_Ip_CompletePllRdivMfiMfnOdiv2Sdmen()397 Clock_Ip_apxPll[Instance].PllInstance->PLLCR &= ~PLL_PLLCR_PLLPD_MASK; in Clock_Ip_EnablePllRdivMfiMfnOdiv2Sdmen()
76 __IO uint32_t PLLCR; /**< PLL Control, offset: 0x0 */ member
92 __IO uint32_t PLLCR; /**< LFAST PLL Control Register, offset: 0x3C */ member
