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Searched refs:MUX_0_DC_0 (Results 1 – 5 of 5) sorted by relevance

/hal_nxp-3.5.0/s32/drivers/s32ze/Mcu/src/
DClock_Ip_Frequency.c2016 …Frequency /= (((IP_MC_CGM_6->MUX_0_DC_0 & MC_CGM_MUX_6_DC_0_DIV_MASK) >> MC_CGM_MUX_6_DC_0_DIV_SHI… in Clock_Ip_Get_DDR_CLK_Frequency()
2147 …Frequency /= (((IP_MC_CGM_5->MUX_0_DC_0 & MC_CGM_MUX_0_DC_0_DIV_MASK) >> MC_CGM_MUX_0_DC_0_DIV_SHI… in Clock_Ip_Get_P5_SYS_CLK_Frequency()
2156 …Frequency /= (((IP_MC_CGM_5->MUX_0_DC_0 & MC_CGM_MUX_0_DC_0_DIV_MASK) >> MC_CGM_MUX_0_DC_0_DIV_SHI… in Clock_Ip_Get_P5_SYS_DIV2_CLK_Frequency()
2166 …Frequency /= (((IP_MC_CGM_5->MUX_0_DC_0 & MC_CGM_MUX_0_DC_0_DIV_MASK) >> MC_CGM_MUX_0_DC_0_DIV_SHI… in Clock_Ip_Get_P5_SYS_DIV4_CLK_Frequency()
2203 …Frequency &= Clock_Ip_au32EnableDivider[((IP_RTU0__MC_CGM->MUX_0_DC_0 & RTU_MC_CGM_MUX_0_DC_0_DE_M… in Clock_Ip_Get_RTU0_CORE_CLK_Frequency()
2204 …Frequency /= (((IP_RTU0__MC_CGM->MUX_0_DC_0 & RTU_MC_CGM_MUX_0_DC_0_DIV_MASK) >> RTU_MC_CGM_MUX_0_… in Clock_Ip_Get_RTU0_CORE_CLK_Frequency()
2222 …Frequency &= Clock_Ip_au32EnableDivider[((IP_RTU1__MC_CGM->MUX_0_DC_0 & RTU_MC_CGM_MUX_0_DC_0_DE_M… in Clock_Ip_Get_RTU1_CORE_CLK_Frequency()
2223 …Frequency /= (((IP_RTU1__MC_CGM->MUX_0_DC_0 & RTU_MC_CGM_MUX_0_DC_0_DIV_MASK) >> RTU_MC_CGM_MUX_0_… in Clock_Ip_Get_RTU1_CORE_CLK_Frequency()
2418 …Frequency /= (((IP_MC_CGM_5->MUX_0_DC_0 & MC_CGM_MUX_0_DC_0_DIV_MASK) >> MC_CGM_MUX_0_DC_0_DIV_SHI… in Clock_Ip_Get_DMACRC5_CLK_Frequency()
2602 …Frequency /= (((IP_MC_CGM_5->MUX_0_DC_0 & MC_CGM_MUX_0_DC_0_DIV_MASK) >> MC_CGM_MUX_0_DC_0_DIV_SHI… in Clock_Ip_Get_EDMA5_CLK_Frequency()
/hal_nxp-3.5.0/s32/drivers/s32ze/BaseNXP/header/
DS32Z2_RTU_MC_CGM.h87 …__IO uint32_t MUX_0_DC_0; /**< Clock Mux 0 Divider 0 Control Register, offs… member
DS32Z2_MC_CGM.h89 …__IO uint32_t MUX_0_DC_0; /**< Clock Mux 0 Divider 0 Control Register, offs… member
/hal_nxp-3.5.0/s32/drivers/s32k3/BaseNXP/header/
DS32K344_MC_CGM.h81 …__IO uint32_t MUX_0_DC_0; /**< Clock Mux 0 Divider 0 Control Register, offs… member
/hal_nxp-3.5.0/s32/drivers/s32k3/Mcu/src/
DClock_Ip_Frequency.c1942 …Frequency &= Clock_Ip_au32EnableDivider[((IP_MC_CGM->MUX_0_DC_0 & MC_CGM_MUX_0_DC_0_DE_MASK) >> MC… in Clock_Ip_Get_CORE_CLK_Frequency()
1943 …Frequency /= (((IP_MC_CGM->MUX_0_DC_0 & MC_CGM_MUX_0_DC_0_DIV_MASK) >> MC_CGM_MUX_0_DC_0_DIV_SHIFT… in Clock_Ip_Get_CORE_CLK_Frequency()