1 /* 2 * Copyright 1997-2016 Freescale Semiconductor, Inc. 3 * Copyright 2016-2022 NXP 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 /*! 9 * @file S32Z2_RTU_MC_CGM.h 10 * @version 1.8 11 * @date 2022-07-13 12 * @brief Peripheral Access Layer for S32Z2_RTU_MC_CGM 13 * 14 * This file contains register definitions and macros for easy access to their 15 * bit fields. 16 * 17 * This file assumes LITTLE endian system. 18 */ 19 20 /** 21 * @page misra_violations MISRA-C:2012 violations 22 * 23 * @section [global] 24 * Violates MISRA 2012 Advisory Rule 2.3, local typedef not referenced 25 * The SoC header defines typedef for all modules. 26 * 27 * @section [global] 28 * Violates MISRA 2012 Advisory Rule 2.5, local macro not referenced 29 * The SoC header defines macros for all modules and registers. 30 * 31 * @section [global] 32 * Violates MISRA 2012 Advisory Directive 4.9, Function-like macro 33 * These are generated macros used for accessing the bit-fields from registers. 34 * 35 * @section [global] 36 * Violates MISRA 2012 Required Rule 5.1, identifier clash 37 * The supported compilers use more than 31 significant characters for identifiers. 38 * 39 * @section [global] 40 * Violates MISRA 2012 Required Rule 5.2, identifier clash 41 * The supported compilers use more than 31 significant characters for identifiers. 42 * 43 * @section [global] 44 * Violates MISRA 2012 Required Rule 5.4, identifier clash 45 * The supported compilers use more than 31 significant characters for identifiers. 46 * 47 * @section [global] 48 * Violates MISRA 2012 Required Rule 5.5, identifier clash 49 * The supported compilers use more than 31 significant characters for identifiers. 50 * 51 * @section [global] 52 * Violates MISRA 2012 Required Rule 21.1, defined macro '__I' is reserved to the compiler 53 * This type qualifier is needed to ensure correct I/O access and addressing. 54 */ 55 56 /* Prevention from multiple including the same memory map */ 57 #if !defined(S32Z2_RTU_MC_CGM_H_) /* Check if memory map has not been already included */ 58 #define S32Z2_RTU_MC_CGM_H_ 59 60 #include "S32Z2_COMMON.h" 61 62 /* ---------------------------------------------------------------------------- 63 -- RTU_MC_CGM Peripheral Access Layer 64 ---------------------------------------------------------------------------- */ 65 66 /*! 67 * @addtogroup RTU_MC_CGM_Peripheral_Access_Layer RTU_MC_CGM Peripheral Access Layer 68 * @{ 69 */ 70 71 /** RTU_MC_CGM - Register Layout Typedef */ 72 typedef struct { 73 __IO uint32_t PCFS_SDUR; /**< PCFS Step Duration, offset: 0x0 */ 74 uint8_t RESERVED_0[108]; 75 __IO uint32_t PCFS_DIVC10; /**< PCFS Divider Change 10 Register, offset: 0x70 */ 76 __IO uint32_t PCFS_DIVE10; /**< PCFS Divider End 10 Register, offset: 0x74 */ 77 __IO uint32_t PCFS_DIVS10; /**< PCFS Divider Start 10 Register, offset: 0x78 */ 78 __IO uint32_t PCFS_DIVC11; /**< PCFS Divider Change 11 Register, offset: 0x7C */ 79 __IO uint32_t PCFS_DIVE11; /**< PCFS Divider End 11 Register, offset: 0x80 */ 80 __IO uint32_t PCFS_DIVS11; /**< PCFS Divider Start 11 Register, offset: 0x84 */ 81 __IO uint32_t PCFS_DIVC12; /**< PCFS Divider Change 12 Register, offset: 0x88 */ 82 __IO uint32_t PCFS_DIVE12; /**< PCFS Divider End 12 Register, offset: 0x8C */ 83 __IO uint32_t PCFS_DIVS12; /**< PCFS Divider Start 12 Register, offset: 0x90 */ 84 uint8_t RESERVED_1[620]; 85 __IO uint32_t MUX_0_CSC; /**< Clock Mux 0 Select Control Register, offset: 0x300 */ 86 __I uint32_t MUX_0_CSS; /**< Clock Mux 0 Select Status Register, offset: 0x304 */ 87 __IO uint32_t MUX_0_DC_0; /**< Clock Mux 0 Divider 0 Control Register, offset: 0x308 */ 88 uint8_t RESERVED_2[48]; 89 __I uint32_t MUX_0_DIV_UPD_STAT; /**< Clock Mux 0 Divider Update Status Register, offset: 0x33C */ 90 __IO uint32_t MUX_1_CSC; /**< Clock Mux 1 Select Control Register, offset: 0x340 */ 91 __I uint32_t MUX_1_CSS; /**< Clock Mux 1 Select Status Register, offset: 0x344 */ 92 __IO uint32_t MUX_1_DC_0; /**< Clock Mux 1 Divider 0 Control Register, offset: 0x348 */ 93 uint8_t RESERVED_3[48]; 94 __I uint32_t MUX_1_DIV_UPD_STAT; /**< Clock Mux 1 Divider Update Status Register, offset: 0x37C */ 95 } RTU_MC_CGM_Type, *RTU_MC_CGM_MemMapPtr; 96 97 /** Number of instances of the RTU_MC_CGM module. */ 98 #define RTU_MC_CGM_INSTANCE_COUNT (2u) 99 100 /* RTU_MC_CGM - Peripheral instance base addresses */ 101 /** Peripheral RTU0__MC_CGM base address */ 102 #define IP_RTU0__MC_CGM_BASE (0x762C0000u) 103 /** Peripheral RTU0__MC_CGM base pointer */ 104 #define IP_RTU0__MC_CGM ((RTU_MC_CGM_Type *)IP_RTU0__MC_CGM_BASE) 105 /** Peripheral RTU1__MC_CGM base address */ 106 #define IP_RTU1__MC_CGM_BASE (0x76AC0000u) 107 /** Peripheral RTU1__MC_CGM base pointer */ 108 #define IP_RTU1__MC_CGM ((RTU_MC_CGM_Type *)IP_RTU1__MC_CGM_BASE) 109 /** Array initializer of RTU_MC_CGM peripheral base addresses */ 110 #define IP_RTU_MC_CGM_BASE_ADDRS { IP_RTU0__MC_CGM_BASE, IP_RTU1__MC_CGM_BASE } 111 /** Array initializer of RTU_MC_CGM peripheral base pointers */ 112 #define IP_RTU_MC_CGM_BASE_PTRS { IP_RTU0__MC_CGM, IP_RTU1__MC_CGM } 113 114 /* ---------------------------------------------------------------------------- 115 -- RTU_MC_CGM Register Masks 116 ---------------------------------------------------------------------------- */ 117 118 /*! 119 * @addtogroup RTU_MC_CGM_Register_Masks RTU_MC_CGM Register Masks 120 * @{ 121 */ 122 123 /*! @name PCFS_SDUR - PCFS Step Duration */ 124 /*! @{ */ 125 126 #define RTU_MC_CGM_PCFS_SDUR_SDUR_MASK (0xFFFFU) 127 #define RTU_MC_CGM_PCFS_SDUR_SDUR_SHIFT (0U) 128 #define RTU_MC_CGM_PCFS_SDUR_SDUR_WIDTH (16U) 129 #define RTU_MC_CGM_PCFS_SDUR_SDUR(x) (((uint32_t)(((uint32_t)(x)) << RTU_MC_CGM_PCFS_SDUR_SDUR_SHIFT)) & RTU_MC_CGM_PCFS_SDUR_SDUR_MASK) 130 /*! @} */ 131 132 /*! @name PCFS_DIVC10 - PCFS Divider Change 10 Register */ 133 /*! @{ */ 134 135 #define RTU_MC_CGM_PCFS_DIVC10_RATE_MASK (0xFFU) 136 #define RTU_MC_CGM_PCFS_DIVC10_RATE_SHIFT (0U) 137 #define RTU_MC_CGM_PCFS_DIVC10_RATE_WIDTH (8U) 138 #define RTU_MC_CGM_PCFS_DIVC10_RATE(x) (((uint32_t)(((uint32_t)(x)) << RTU_MC_CGM_PCFS_DIVC10_RATE_SHIFT)) & RTU_MC_CGM_PCFS_DIVC10_RATE_MASK) 139 140 #define RTU_MC_CGM_PCFS_DIVC10_INIT_MASK (0xFFFF0000U) 141 #define RTU_MC_CGM_PCFS_DIVC10_INIT_SHIFT (16U) 142 #define RTU_MC_CGM_PCFS_DIVC10_INIT_WIDTH (16U) 143 #define RTU_MC_CGM_PCFS_DIVC10_INIT(x) (((uint32_t)(((uint32_t)(x)) << RTU_MC_CGM_PCFS_DIVC10_INIT_SHIFT)) & RTU_MC_CGM_PCFS_DIVC10_INIT_MASK) 144 /*! @} */ 145 146 /*! @name PCFS_DIVE10 - PCFS Divider End 10 Register */ 147 /*! @{ */ 148 149 #define RTU_MC_CGM_PCFS_DIVE10_DIVE_MASK (0xFFFFFU) 150 #define RTU_MC_CGM_PCFS_DIVE10_DIVE_SHIFT (0U) 151 #define RTU_MC_CGM_PCFS_DIVE10_DIVE_WIDTH (20U) 152 #define RTU_MC_CGM_PCFS_DIVE10_DIVE(x) (((uint32_t)(((uint32_t)(x)) << RTU_MC_CGM_PCFS_DIVE10_DIVE_SHIFT)) & RTU_MC_CGM_PCFS_DIVE10_DIVE_MASK) 153 /*! @} */ 154 155 /*! @name PCFS_DIVS10 - PCFS Divider Start 10 Register */ 156 /*! @{ */ 157 158 #define RTU_MC_CGM_PCFS_DIVS10_DIVS_MASK (0xFFFFFU) 159 #define RTU_MC_CGM_PCFS_DIVS10_DIVS_SHIFT (0U) 160 #define RTU_MC_CGM_PCFS_DIVS10_DIVS_WIDTH (20U) 161 #define RTU_MC_CGM_PCFS_DIVS10_DIVS(x) (((uint32_t)(((uint32_t)(x)) << RTU_MC_CGM_PCFS_DIVS10_DIVS_SHIFT)) & RTU_MC_CGM_PCFS_DIVS10_DIVS_MASK) 162 /*! @} */ 163 164 /*! @name PCFS_DIVC11 - PCFS Divider Change 11 Register */ 165 /*! @{ */ 166 167 #define RTU_MC_CGM_PCFS_DIVC11_RATE_MASK (0xFFU) 168 #define RTU_MC_CGM_PCFS_DIVC11_RATE_SHIFT (0U) 169 #define RTU_MC_CGM_PCFS_DIVC11_RATE_WIDTH (8U) 170 #define RTU_MC_CGM_PCFS_DIVC11_RATE(x) (((uint32_t)(((uint32_t)(x)) << RTU_MC_CGM_PCFS_DIVC11_RATE_SHIFT)) & RTU_MC_CGM_PCFS_DIVC11_RATE_MASK) 171 172 #define RTU_MC_CGM_PCFS_DIVC11_INIT_MASK (0xFFFF0000U) 173 #define RTU_MC_CGM_PCFS_DIVC11_INIT_SHIFT (16U) 174 #define RTU_MC_CGM_PCFS_DIVC11_INIT_WIDTH (16U) 175 #define RTU_MC_CGM_PCFS_DIVC11_INIT(x) (((uint32_t)(((uint32_t)(x)) << RTU_MC_CGM_PCFS_DIVC11_INIT_SHIFT)) & RTU_MC_CGM_PCFS_DIVC11_INIT_MASK) 176 /*! @} */ 177 178 /*! @name PCFS_DIVE11 - PCFS Divider End 11 Register */ 179 /*! @{ */ 180 181 #define RTU_MC_CGM_PCFS_DIVE11_DIVE_MASK (0xFFFFFU) 182 #define RTU_MC_CGM_PCFS_DIVE11_DIVE_SHIFT (0U) 183 #define RTU_MC_CGM_PCFS_DIVE11_DIVE_WIDTH (20U) 184 #define RTU_MC_CGM_PCFS_DIVE11_DIVE(x) (((uint32_t)(((uint32_t)(x)) << RTU_MC_CGM_PCFS_DIVE11_DIVE_SHIFT)) & RTU_MC_CGM_PCFS_DIVE11_DIVE_MASK) 185 /*! @} */ 186 187 /*! @name PCFS_DIVS11 - PCFS Divider Start 11 Register */ 188 /*! @{ */ 189 190 #define RTU_MC_CGM_PCFS_DIVS11_DIVS_MASK (0xFFFFFU) 191 #define RTU_MC_CGM_PCFS_DIVS11_DIVS_SHIFT (0U) 192 #define RTU_MC_CGM_PCFS_DIVS11_DIVS_WIDTH (20U) 193 #define RTU_MC_CGM_PCFS_DIVS11_DIVS(x) (((uint32_t)(((uint32_t)(x)) << RTU_MC_CGM_PCFS_DIVS11_DIVS_SHIFT)) & RTU_MC_CGM_PCFS_DIVS11_DIVS_MASK) 194 /*! @} */ 195 196 /*! @name PCFS_DIVC12 - PCFS Divider Change 12 Register */ 197 /*! @{ */ 198 199 #define RTU_MC_CGM_PCFS_DIVC12_RATE_MASK (0xFFU) 200 #define RTU_MC_CGM_PCFS_DIVC12_RATE_SHIFT (0U) 201 #define RTU_MC_CGM_PCFS_DIVC12_RATE_WIDTH (8U) 202 #define RTU_MC_CGM_PCFS_DIVC12_RATE(x) (((uint32_t)(((uint32_t)(x)) << RTU_MC_CGM_PCFS_DIVC12_RATE_SHIFT)) & RTU_MC_CGM_PCFS_DIVC12_RATE_MASK) 203 204 #define RTU_MC_CGM_PCFS_DIVC12_INIT_MASK (0xFFFF0000U) 205 #define RTU_MC_CGM_PCFS_DIVC12_INIT_SHIFT (16U) 206 #define RTU_MC_CGM_PCFS_DIVC12_INIT_WIDTH (16U) 207 #define RTU_MC_CGM_PCFS_DIVC12_INIT(x) (((uint32_t)(((uint32_t)(x)) << RTU_MC_CGM_PCFS_DIVC12_INIT_SHIFT)) & RTU_MC_CGM_PCFS_DIVC12_INIT_MASK) 208 /*! @} */ 209 210 /*! @name PCFS_DIVE12 - PCFS Divider End 12 Register */ 211 /*! @{ */ 212 213 #define RTU_MC_CGM_PCFS_DIVE12_DIVE_MASK (0xFFFFFU) 214 #define RTU_MC_CGM_PCFS_DIVE12_DIVE_SHIFT (0U) 215 #define RTU_MC_CGM_PCFS_DIVE12_DIVE_WIDTH (20U) 216 #define RTU_MC_CGM_PCFS_DIVE12_DIVE(x) (((uint32_t)(((uint32_t)(x)) << RTU_MC_CGM_PCFS_DIVE12_DIVE_SHIFT)) & RTU_MC_CGM_PCFS_DIVE12_DIVE_MASK) 217 /*! @} */ 218 219 /*! @name PCFS_DIVS12 - PCFS Divider Start 12 Register */ 220 /*! @{ */ 221 222 #define RTU_MC_CGM_PCFS_DIVS12_DIVS_MASK (0xFFFFFU) 223 #define RTU_MC_CGM_PCFS_DIVS12_DIVS_SHIFT (0U) 224 #define RTU_MC_CGM_PCFS_DIVS12_DIVS_WIDTH (20U) 225 #define RTU_MC_CGM_PCFS_DIVS12_DIVS(x) (((uint32_t)(((uint32_t)(x)) << RTU_MC_CGM_PCFS_DIVS12_DIVS_SHIFT)) & RTU_MC_CGM_PCFS_DIVS12_DIVS_MASK) 226 /*! @} */ 227 228 /*! @name MUX_0_CSC - Clock Mux 0 Select Control Register */ 229 /*! @{ */ 230 231 #define RTU_MC_CGM_MUX_0_CSC_RAMPUP_MASK (0x1U) 232 #define RTU_MC_CGM_MUX_0_CSC_RAMPUP_SHIFT (0U) 233 #define RTU_MC_CGM_MUX_0_CSC_RAMPUP_WIDTH (1U) 234 #define RTU_MC_CGM_MUX_0_CSC_RAMPUP(x) (((uint32_t)(((uint32_t)(x)) << RTU_MC_CGM_MUX_0_CSC_RAMPUP_SHIFT)) & RTU_MC_CGM_MUX_0_CSC_RAMPUP_MASK) 235 236 #define RTU_MC_CGM_MUX_0_CSC_RAMPDOWN_MASK (0x2U) 237 #define RTU_MC_CGM_MUX_0_CSC_RAMPDOWN_SHIFT (1U) 238 #define RTU_MC_CGM_MUX_0_CSC_RAMPDOWN_WIDTH (1U) 239 #define RTU_MC_CGM_MUX_0_CSC_RAMPDOWN(x) (((uint32_t)(((uint32_t)(x)) << RTU_MC_CGM_MUX_0_CSC_RAMPDOWN_SHIFT)) & RTU_MC_CGM_MUX_0_CSC_RAMPDOWN_MASK) 240 241 #define RTU_MC_CGM_MUX_0_CSC_CLK_SW_MASK (0x4U) 242 #define RTU_MC_CGM_MUX_0_CSC_CLK_SW_SHIFT (2U) 243 #define RTU_MC_CGM_MUX_0_CSC_CLK_SW_WIDTH (1U) 244 #define RTU_MC_CGM_MUX_0_CSC_CLK_SW(x) (((uint32_t)(((uint32_t)(x)) << RTU_MC_CGM_MUX_0_CSC_CLK_SW_SHIFT)) & RTU_MC_CGM_MUX_0_CSC_CLK_SW_MASK) 245 246 #define RTU_MC_CGM_MUX_0_CSC_SAFE_SW_MASK (0x8U) 247 #define RTU_MC_CGM_MUX_0_CSC_SAFE_SW_SHIFT (3U) 248 #define RTU_MC_CGM_MUX_0_CSC_SAFE_SW_WIDTH (1U) 249 #define RTU_MC_CGM_MUX_0_CSC_SAFE_SW(x) (((uint32_t)(((uint32_t)(x)) << RTU_MC_CGM_MUX_0_CSC_SAFE_SW_SHIFT)) & RTU_MC_CGM_MUX_0_CSC_SAFE_SW_MASK) 250 251 #define RTU_MC_CGM_MUX_0_CSC_SELCTL_MASK (0xF000000U) 252 #define RTU_MC_CGM_MUX_0_CSC_SELCTL_SHIFT (24U) 253 #define RTU_MC_CGM_MUX_0_CSC_SELCTL_WIDTH (4U) 254 #define RTU_MC_CGM_MUX_0_CSC_SELCTL(x) (((uint32_t)(((uint32_t)(x)) << RTU_MC_CGM_MUX_0_CSC_SELCTL_SHIFT)) & RTU_MC_CGM_MUX_0_CSC_SELCTL_MASK) 255 /*! @} */ 256 257 /*! @name MUX_0_CSS - Clock Mux 0 Select Status Register */ 258 /*! @{ */ 259 260 #define RTU_MC_CGM_MUX_0_CSS_RAMPUP_MASK (0x1U) 261 #define RTU_MC_CGM_MUX_0_CSS_RAMPUP_SHIFT (0U) 262 #define RTU_MC_CGM_MUX_0_CSS_RAMPUP_WIDTH (1U) 263 #define RTU_MC_CGM_MUX_0_CSS_RAMPUP(x) (((uint32_t)(((uint32_t)(x)) << RTU_MC_CGM_MUX_0_CSS_RAMPUP_SHIFT)) & RTU_MC_CGM_MUX_0_CSS_RAMPUP_MASK) 264 265 #define RTU_MC_CGM_MUX_0_CSS_RAMPDOWN_MASK (0x2U) 266 #define RTU_MC_CGM_MUX_0_CSS_RAMPDOWN_SHIFT (1U) 267 #define RTU_MC_CGM_MUX_0_CSS_RAMPDOWN_WIDTH (1U) 268 #define RTU_MC_CGM_MUX_0_CSS_RAMPDOWN(x) (((uint32_t)(((uint32_t)(x)) << RTU_MC_CGM_MUX_0_CSS_RAMPDOWN_SHIFT)) & RTU_MC_CGM_MUX_0_CSS_RAMPDOWN_MASK) 269 270 #define RTU_MC_CGM_MUX_0_CSS_CLK_SW_MASK (0x4U) 271 #define RTU_MC_CGM_MUX_0_CSS_CLK_SW_SHIFT (2U) 272 #define RTU_MC_CGM_MUX_0_CSS_CLK_SW_WIDTH (1U) 273 #define RTU_MC_CGM_MUX_0_CSS_CLK_SW(x) (((uint32_t)(((uint32_t)(x)) << RTU_MC_CGM_MUX_0_CSS_CLK_SW_SHIFT)) & RTU_MC_CGM_MUX_0_CSS_CLK_SW_MASK) 274 275 #define RTU_MC_CGM_MUX_0_CSS_SAFE_SW_MASK (0x8U) 276 #define RTU_MC_CGM_MUX_0_CSS_SAFE_SW_SHIFT (3U) 277 #define RTU_MC_CGM_MUX_0_CSS_SAFE_SW_WIDTH (1U) 278 #define RTU_MC_CGM_MUX_0_CSS_SAFE_SW(x) (((uint32_t)(((uint32_t)(x)) << RTU_MC_CGM_MUX_0_CSS_SAFE_SW_SHIFT)) & RTU_MC_CGM_MUX_0_CSS_SAFE_SW_MASK) 279 280 #define RTU_MC_CGM_MUX_0_CSS_SWIP_MASK (0x10000U) 281 #define RTU_MC_CGM_MUX_0_CSS_SWIP_SHIFT (16U) 282 #define RTU_MC_CGM_MUX_0_CSS_SWIP_WIDTH (1U) 283 #define RTU_MC_CGM_MUX_0_CSS_SWIP(x) (((uint32_t)(((uint32_t)(x)) << RTU_MC_CGM_MUX_0_CSS_SWIP_SHIFT)) & RTU_MC_CGM_MUX_0_CSS_SWIP_MASK) 284 285 #define RTU_MC_CGM_MUX_0_CSS_SWTRG_MASK (0xE0000U) 286 #define RTU_MC_CGM_MUX_0_CSS_SWTRG_SHIFT (17U) 287 #define RTU_MC_CGM_MUX_0_CSS_SWTRG_WIDTH (3U) 288 #define RTU_MC_CGM_MUX_0_CSS_SWTRG(x) (((uint32_t)(((uint32_t)(x)) << RTU_MC_CGM_MUX_0_CSS_SWTRG_SHIFT)) & RTU_MC_CGM_MUX_0_CSS_SWTRG_MASK) 289 290 #define RTU_MC_CGM_MUX_0_CSS_SELSTAT_MASK (0xF000000U) 291 #define RTU_MC_CGM_MUX_0_CSS_SELSTAT_SHIFT (24U) 292 #define RTU_MC_CGM_MUX_0_CSS_SELSTAT_WIDTH (4U) 293 #define RTU_MC_CGM_MUX_0_CSS_SELSTAT(x) (((uint32_t)(((uint32_t)(x)) << RTU_MC_CGM_MUX_0_CSS_SELSTAT_SHIFT)) & RTU_MC_CGM_MUX_0_CSS_SELSTAT_MASK) 294 /*! @} */ 295 296 /*! @name MUX_0_DC_0 - Clock Mux 0 Divider 0 Control Register */ 297 /*! @{ */ 298 299 #define RTU_MC_CGM_MUX_0_DC_0_DIV_MASK (0xFF0000U) 300 #define RTU_MC_CGM_MUX_0_DC_0_DIV_SHIFT (16U) 301 #define RTU_MC_CGM_MUX_0_DC_0_DIV_WIDTH (8U) 302 #define RTU_MC_CGM_MUX_0_DC_0_DIV(x) (((uint32_t)(((uint32_t)(x)) << RTU_MC_CGM_MUX_0_DC_0_DIV_SHIFT)) & RTU_MC_CGM_MUX_0_DC_0_DIV_MASK) 303 304 #define RTU_MC_CGM_MUX_0_DC_0_DE_MASK (0x80000000U) 305 #define RTU_MC_CGM_MUX_0_DC_0_DE_SHIFT (31U) 306 #define RTU_MC_CGM_MUX_0_DC_0_DE_WIDTH (1U) 307 #define RTU_MC_CGM_MUX_0_DC_0_DE(x) (((uint32_t)(((uint32_t)(x)) << RTU_MC_CGM_MUX_0_DC_0_DE_SHIFT)) & RTU_MC_CGM_MUX_0_DC_0_DE_MASK) 308 /*! @} */ 309 310 /*! @name MUX_0_DIV_UPD_STAT - Clock Mux 0 Divider Update Status Register */ 311 /*! @{ */ 312 313 #define RTU_MC_CGM_MUX_0_DIV_UPD_STAT_DIV_STAT_MASK (0x1U) 314 #define RTU_MC_CGM_MUX_0_DIV_UPD_STAT_DIV_STAT_SHIFT (0U) 315 #define RTU_MC_CGM_MUX_0_DIV_UPD_STAT_DIV_STAT_WIDTH (1U) 316 #define RTU_MC_CGM_MUX_0_DIV_UPD_STAT_DIV_STAT(x) (((uint32_t)(((uint32_t)(x)) << RTU_MC_CGM_MUX_0_DIV_UPD_STAT_DIV_STAT_SHIFT)) & RTU_MC_CGM_MUX_0_DIV_UPD_STAT_DIV_STAT_MASK) 317 /*! @} */ 318 319 /*! @name MUX_1_CSC - Clock Mux 1 Select Control Register */ 320 /*! @{ */ 321 322 #define RTU_MC_CGM_MUX_1_CSC_CLK_SW_MASK (0x4U) 323 #define RTU_MC_CGM_MUX_1_CSC_CLK_SW_SHIFT (2U) 324 #define RTU_MC_CGM_MUX_1_CSC_CLK_SW_WIDTH (1U) 325 #define RTU_MC_CGM_MUX_1_CSC_CLK_SW(x) (((uint32_t)(((uint32_t)(x)) << RTU_MC_CGM_MUX_1_CSC_CLK_SW_SHIFT)) & RTU_MC_CGM_MUX_1_CSC_CLK_SW_MASK) 326 327 #define RTU_MC_CGM_MUX_1_CSC_SAFE_SW_MASK (0x8U) 328 #define RTU_MC_CGM_MUX_1_CSC_SAFE_SW_SHIFT (3U) 329 #define RTU_MC_CGM_MUX_1_CSC_SAFE_SW_WIDTH (1U) 330 #define RTU_MC_CGM_MUX_1_CSC_SAFE_SW(x) (((uint32_t)(((uint32_t)(x)) << RTU_MC_CGM_MUX_1_CSC_SAFE_SW_SHIFT)) & RTU_MC_CGM_MUX_1_CSC_SAFE_SW_MASK) 331 332 #define RTU_MC_CGM_MUX_1_CSC_SELCTL_MASK (0xF000000U) 333 #define RTU_MC_CGM_MUX_1_CSC_SELCTL_SHIFT (24U) 334 #define RTU_MC_CGM_MUX_1_CSC_SELCTL_WIDTH (4U) 335 #define RTU_MC_CGM_MUX_1_CSC_SELCTL(x) (((uint32_t)(((uint32_t)(x)) << RTU_MC_CGM_MUX_1_CSC_SELCTL_SHIFT)) & RTU_MC_CGM_MUX_1_CSC_SELCTL_MASK) 336 /*! @} */ 337 338 /*! @name MUX_1_CSS - Clock Mux 1 Select Status Register */ 339 /*! @{ */ 340 341 #define RTU_MC_CGM_MUX_1_CSS_CLK_SW_MASK (0x4U) 342 #define RTU_MC_CGM_MUX_1_CSS_CLK_SW_SHIFT (2U) 343 #define RTU_MC_CGM_MUX_1_CSS_CLK_SW_WIDTH (1U) 344 #define RTU_MC_CGM_MUX_1_CSS_CLK_SW(x) (((uint32_t)(((uint32_t)(x)) << RTU_MC_CGM_MUX_1_CSS_CLK_SW_SHIFT)) & RTU_MC_CGM_MUX_1_CSS_CLK_SW_MASK) 345 346 #define RTU_MC_CGM_MUX_1_CSS_SAFE_SW_MASK (0x8U) 347 #define RTU_MC_CGM_MUX_1_CSS_SAFE_SW_SHIFT (3U) 348 #define RTU_MC_CGM_MUX_1_CSS_SAFE_SW_WIDTH (1U) 349 #define RTU_MC_CGM_MUX_1_CSS_SAFE_SW(x) (((uint32_t)(((uint32_t)(x)) << RTU_MC_CGM_MUX_1_CSS_SAFE_SW_SHIFT)) & RTU_MC_CGM_MUX_1_CSS_SAFE_SW_MASK) 350 351 #define RTU_MC_CGM_MUX_1_CSS_SWIP_MASK (0x10000U) 352 #define RTU_MC_CGM_MUX_1_CSS_SWIP_SHIFT (16U) 353 #define RTU_MC_CGM_MUX_1_CSS_SWIP_WIDTH (1U) 354 #define RTU_MC_CGM_MUX_1_CSS_SWIP(x) (((uint32_t)(((uint32_t)(x)) << RTU_MC_CGM_MUX_1_CSS_SWIP_SHIFT)) & RTU_MC_CGM_MUX_1_CSS_SWIP_MASK) 355 356 #define RTU_MC_CGM_MUX_1_CSS_SWTRG_MASK (0xE0000U) 357 #define RTU_MC_CGM_MUX_1_CSS_SWTRG_SHIFT (17U) 358 #define RTU_MC_CGM_MUX_1_CSS_SWTRG_WIDTH (3U) 359 #define RTU_MC_CGM_MUX_1_CSS_SWTRG(x) (((uint32_t)(((uint32_t)(x)) << RTU_MC_CGM_MUX_1_CSS_SWTRG_SHIFT)) & RTU_MC_CGM_MUX_1_CSS_SWTRG_MASK) 360 361 #define RTU_MC_CGM_MUX_1_CSS_SELSTAT_MASK (0xF000000U) 362 #define RTU_MC_CGM_MUX_1_CSS_SELSTAT_SHIFT (24U) 363 #define RTU_MC_CGM_MUX_1_CSS_SELSTAT_WIDTH (4U) 364 #define RTU_MC_CGM_MUX_1_CSS_SELSTAT(x) (((uint32_t)(((uint32_t)(x)) << RTU_MC_CGM_MUX_1_CSS_SELSTAT_SHIFT)) & RTU_MC_CGM_MUX_1_CSS_SELSTAT_MASK) 365 /*! @} */ 366 367 /*! @name MUX_1_DC_0 - Clock Mux 1 Divider 0 Control Register */ 368 /*! @{ */ 369 370 #define RTU_MC_CGM_MUX_1_DC_0_DIV_MASK (0xFF0000U) 371 #define RTU_MC_CGM_MUX_1_DC_0_DIV_SHIFT (16U) 372 #define RTU_MC_CGM_MUX_1_DC_0_DIV_WIDTH (8U) 373 #define RTU_MC_CGM_MUX_1_DC_0_DIV(x) (((uint32_t)(((uint32_t)(x)) << RTU_MC_CGM_MUX_1_DC_0_DIV_SHIFT)) & RTU_MC_CGM_MUX_1_DC_0_DIV_MASK) 374 375 #define RTU_MC_CGM_MUX_1_DC_0_DE_MASK (0x80000000U) 376 #define RTU_MC_CGM_MUX_1_DC_0_DE_SHIFT (31U) 377 #define RTU_MC_CGM_MUX_1_DC_0_DE_WIDTH (1U) 378 #define RTU_MC_CGM_MUX_1_DC_0_DE(x) (((uint32_t)(((uint32_t)(x)) << RTU_MC_CGM_MUX_1_DC_0_DE_SHIFT)) & RTU_MC_CGM_MUX_1_DC_0_DE_MASK) 379 /*! @} */ 380 381 /*! @name MUX_1_DIV_UPD_STAT - Clock Mux 1 Divider Update Status Register */ 382 /*! @{ */ 383 384 #define RTU_MC_CGM_MUX_1_DIV_UPD_STAT_DIV_STAT_MASK (0x1U) 385 #define RTU_MC_CGM_MUX_1_DIV_UPD_STAT_DIV_STAT_SHIFT (0U) 386 #define RTU_MC_CGM_MUX_1_DIV_UPD_STAT_DIV_STAT_WIDTH (1U) 387 #define RTU_MC_CGM_MUX_1_DIV_UPD_STAT_DIV_STAT(x) (((uint32_t)(((uint32_t)(x)) << RTU_MC_CGM_MUX_1_DIV_UPD_STAT_DIV_STAT_SHIFT)) & RTU_MC_CGM_MUX_1_DIV_UPD_STAT_DIV_STAT_MASK) 388 /*! @} */ 389 390 /*! 391 * @} 392 */ /* end of group RTU_MC_CGM_Register_Masks */ 393 394 /*! 395 * @} 396 */ /* end of group RTU_MC_CGM_Peripheral_Access_Layer */ 397 398 #endif /* #if !defined(S32Z2_RTU_MC_CGM_H_) */ 399
