Home
last modified time | relevance | path

Searched refs:SIM_BASE (Results 1 – 25 of 30) sorted by relevance

12

/hal_nxp-2.7.6/mcux/devices/MKW41Z4/
Dfsl_clock.h582 uint32_t regAddr = SIM_BASE + CLK_GATE_ABSTRACT_REG_OFFSET((uint32_t)name); in CLOCK_EnableClock()
593 uint32_t regAddr = SIM_BASE + CLK_GATE_ABSTRACT_REG_OFFSET((uint32_t)name); in CLOCK_DisableClock()
DMKW41Z4.h6567 #define SIM_BASE (0x40047000u) macro
6569 #define SIM ((SIM_Type *)SIM_BASE)
6571 #define SIM_BASE_ADDRS { SIM_BASE }
/hal_nxp-2.7.6/mcux/devices/MKL25Z4/
Dfsl_clock.h586 uint32_t regAddr = SIM_BASE + CLK_GATE_ABSTRACT_REG_OFFSET((uint32_t)name); in CLOCK_EnableClock()
597 uint32_t regAddr = SIM_BASE + CLK_GATE_ABSTRACT_REG_OFFSET((uint32_t)name); in CLOCK_DisableClock()
DMKL25Z4.h3924 #define SIM_BASE (0x40047000u) macro
3926 #define SIM ((SIM_Type *)SIM_BASE)
3928 #define SIM_BASE_ADDRS { SIM_BASE }
/hal_nxp-2.7.6/mcux/devices/MKW22D5/
Dfsl_clock.h617 uint32_t regAddr = SIM_BASE + CLK_GATE_ABSTRACT_REG_OFFSET((uint32_t)name); in CLOCK_EnableClock()
628 uint32_t regAddr = SIM_BASE + CLK_GATE_ABSTRACT_REG_OFFSET((uint32_t)name); in CLOCK_DisableClock()
DMKW22D5.h6745 #define SIM_BASE (0x40047000u) macro
6747 #define SIM ((SIM_Type *)SIM_BASE)
6749 #define SIM_BASE_ADDRS { SIM_BASE }
/hal_nxp-2.7.6/mcux/devices/MKW24D5/
Dfsl_clock.h617 uint32_t regAddr = SIM_BASE + CLK_GATE_ABSTRACT_REG_OFFSET((uint32_t)name); in CLOCK_EnableClock()
628 uint32_t regAddr = SIM_BASE + CLK_GATE_ABSTRACT_REG_OFFSET((uint32_t)name); in CLOCK_DisableClock()
DMKW24D5.h6745 #define SIM_BASE (0x40047000u) macro
6747 #define SIM ((SIM_Type *)SIM_BASE)
6749 #define SIM_BASE_ADDRS { SIM_BASE }
/hal_nxp-2.7.6/mcux/devices/MK22F51212/
Dfsl_clock.h629 uint32_t regAddr = SIM_BASE + CLK_GATE_ABSTRACT_REG_OFFSET((uint32_t)name); in CLOCK_EnableClock()
640 uint32_t regAddr = SIM_BASE + CLK_GATE_ABSTRACT_REG_OFFSET((uint32_t)name); in CLOCK_DisableClock()
DMK22F51212.h12493 #define SIM_BASE (0x40047000u) macro
12495 #define SIM ((SIM_Type *)SIM_BASE)
12497 #define SIM_BASE_ADDRS { SIM_BASE }
/hal_nxp-2.7.6/mcux/devices/MKV58F24/
Dfsl_clock.h674 uint32_t regAddr = SIM_BASE + CLK_GATE_ABSTRACT_REG_OFFSET((uint32_t)name); in CLOCK_EnableClock()
685 uint32_t regAddr = SIM_BASE + CLK_GATE_ABSTRACT_REG_OFFSET((uint32_t)name); in CLOCK_DisableClock()
/hal_nxp-2.7.6/mcux/devices/MKV56F24/
Dfsl_clock.h674 uint32_t regAddr = SIM_BASE + CLK_GATE_ABSTRACT_REG_OFFSET((uint32_t)name); in CLOCK_EnableClock()
685 uint32_t regAddr = SIM_BASE + CLK_GATE_ABSTRACT_REG_OFFSET((uint32_t)name); in CLOCK_DisableClock()
/hal_nxp-2.7.6/mcux/devices/MK64F12/
Dfsl_clock.h670 uint32_t regAddr = SIM_BASE + CLK_GATE_ABSTRACT_REG_OFFSET((uint32_t)name); in CLOCK_EnableClock()
681 uint32_t regAddr = SIM_BASE + CLK_GATE_ABSTRACT_REG_OFFSET((uint32_t)name); in CLOCK_DisableClock()
DMK64F12.h22239 #define SIM_BASE (0x40047000u) macro
22241 #define SIM ((SIM_Type *)SIM_BASE)
22243 #define SIM_BASE_ADDRS { SIM_BASE }
/hal_nxp-2.7.6/mcux/devices/MK80F25615/
Dfsl_clock.h695 uint32_t regAddr = SIM_BASE + CLK_GATE_ABSTRACT_REG_OFFSET((uint32_t)name); in CLOCK_EnableClock()
706 uint32_t regAddr = SIM_BASE + CLK_GATE_ABSTRACT_REG_OFFSET((uint32_t)name); in CLOCK_DisableClock()
/hal_nxp-2.7.6/mcux/devices/MK82F25615/
Dfsl_clock.h702 uint32_t regAddr = SIM_BASE + CLK_GATE_ABSTRACT_REG_OFFSET((uint32_t)name); in CLOCK_EnableClock()
713 uint32_t regAddr = SIM_BASE + CLK_GATE_ABSTRACT_REG_OFFSET((uint32_t)name); in CLOCK_DisableClock()
/hal_nxp-2.7.6/mcux/devices/MK66F18/
Dfsl_clock.h727 uint32_t regAddr = SIM_BASE + CLK_GATE_ABSTRACT_REG_OFFSET((uint32_t)name); in CLOCK_EnableClock()
738 uint32_t regAddr = SIM_BASE + CLK_GATE_ABSTRACT_REG_OFFSET((uint32_t)name); in CLOCK_DisableClock()
/hal_nxp-2.7.6/mcux/devices/MKE14F16/
DMKE14F16.h14568 #define SIM_BASE (0x40048000u) macro
14570 #define SIM ((SIM_Type *)SIM_BASE)
14572 #define SIM_BASE_ADDRS { SIM_BASE }
/hal_nxp-2.7.6/mcux/devices/MKE16F16/
DMKE16F16.h15373 #define SIM_BASE (0x40048000u) macro
15375 #define SIM ((SIM_Type *)SIM_BASE)
15377 #define SIM_BASE_ADDRS { SIM_BASE }
/hal_nxp-2.7.6/mcux/devices/MKE18F16/
DMKE18F16.h15379 #define SIM_BASE (0x40048000u) macro
15381 #define SIM ((SIM_Type *)SIM_BASE)
15383 #define SIM_BASE_ADDRS { SIM_BASE }
/hal_nxp-2.7.6/mcux/devices/MKW31Z4/
DMKW31Z4.h6567 #define SIM_BASE (0x40047000u) macro
6569 #define SIM ((SIM_Type *)SIM_BASE)
6571 #define SIM_BASE_ADDRS { SIM_BASE }
/hal_nxp-2.7.6/mcux/devices/MKW40Z4/
DMKW40Z4.h7153 #define SIM_BASE (0x40047000u) macro
7155 #define SIM ((SIM_Type *)SIM_BASE)
7158 #define SIM_BASE_ADDRS { SIM_BASE }
/hal_nxp-2.7.6/mcux/devices/MKW21Z4/
DMKW21Z4.h6496 #define SIM_BASE (0x40047000u) macro
6498 #define SIM ((SIM_Type *)SIM_BASE)
6500 #define SIM_BASE_ADDRS { SIM_BASE }
/hal_nxp-2.7.6/mcux/devices/MKW20Z4/
DMKW20Z4.h7153 #define SIM_BASE (0x40047000u) macro
7155 #define SIM ((SIM_Type *)SIM_BASE)
7158 #define SIM_BASE_ADDRS { SIM_BASE }
/hal_nxp-2.7.6/mcux/devices/MKW30Z4/
DMKW30Z4.h7153 #define SIM_BASE (0x40047000u) macro
7155 #define SIM ((SIM_Type *)SIM_BASE)
7158 #define SIM_BASE_ADDRS { SIM_BASE }

12