1 /*
2 * Copyright (c) 2015, Freescale Semiconductor, Inc.
3 * Copyright 2016 - 2020, NXP
4 * All rights reserved.
5 *
6 * SPDX-License-Identifier: BSD-3-Clause
7 */
8
9 #ifndef _FSL_CLOCK_H_
10 #define _FSL_CLOCK_H_
11
12 #include "fsl_common.h"
13
14 /*! @addtogroup clock */
15 /*! @{ */
16
17 /*! @file */
18
19 /*******************************************************************************
20 * Configurations
21 ******************************************************************************/
22
23 /*! @brief Configures whether to check a parameter in a function.
24 *
25 * Some MCG settings must be changed with conditions, for example:
26 * 1. MCGIRCLK settings, such as the source, divider, and the trim value should not change when
27 * MCGIRCLK is used as a system clock source.
28 * 2. MCG_C7[OSCSEL] should not be changed when the external reference clock is used
29 * as a system clock source. For example, in FBE/BLPE/PBE modes.
30 * 3. The users should only switch between the supported clock modes.
31 *
32 * MCG functions check the parameter and MCG status before setting, if not allowed
33 * to change, the functions return error. The parameter checking increases code size,
34 * if code size is a critical requirement, change #MCG_CONFIG_CHECK_PARAM to 0 to
35 * disable parameter checking.
36 */
37 #ifndef MCG_CONFIG_CHECK_PARAM
38 #define MCG_CONFIG_CHECK_PARAM 0U
39 #endif
40
41 /*! @brief Configure whether driver controls clock
42 *
43 * When set to 0, peripheral drivers will enable clock in initialize function
44 * and disable clock in de-initialize function. When set to 1, peripheral
45 * driver will not control the clock, application could control the clock out of
46 * the driver.
47 *
48 * @note All drivers share this feature switcher. If it is set to 1, application
49 * should handle clock enable and disable for all drivers.
50 */
51 #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL))
52 #define FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL 0
53 #endif
54
55 /*******************************************************************************
56 * Definitions
57 ******************************************************************************/
58
59 /*! @name Driver version */
60 /*@{*/
61 /*! @brief CLOCK driver version 2.5.1. */
62 #define FSL_CLOCK_DRIVER_VERSION (MAKE_VERSION(2, 5, 1))
63 /*@}*/
64
65 /*! @brief External XTAL0 (OSC0) clock frequency.
66 *
67 * The XTAL0/EXTAL0 (OSC0) clock frequency in Hz. When the clock is set up, use the
68 * function CLOCK_SetXtal0Freq to set the value in the clock driver. For example,
69 * if XTAL0 is 8 MHz:
70 * @code
71 * Set up the OSC0
72 * CLOCK_InitOsc0(...);
73 * Set the XTAL0 value to the clock driver.
74 * CLOCK_SetXtal0Freq(80000000);
75 * @endcode
76 *
77 * This is important for the multicore platforms where only one core needs to set up the
78 * OSC0 using the CLOCK_InitOsc0. All other cores need to call the CLOCK_SetXtal0Freq
79 * to get a valid clock frequency.
80 */
81 extern volatile uint32_t g_xtal0Freq;
82
83 /*! @brief External XTAL32/EXTAL32/RTC_CLKIN clock frequency.
84 *
85 * The XTAL32/EXTAL32/RTC_CLKIN clock frequency in Hz. When the clock is set up, use the
86 * function CLOCK_SetXtal32Freq to set the value in the clock driver.
87 *
88 * This is important for the multicore platforms where only one core needs to set up
89 * the clock. All other cores need to call the CLOCK_SetXtal32Freq
90 * to get a valid clock frequency.
91 */
92 extern volatile uint32_t g_xtal32Freq;
93
94 /*! @brief IRC48M clock frequency in Hz. */
95 #define MCG_INTERNAL_IRC_48M 48000000U
96
97 #if (defined(OSC) && !(defined(OSC0)))
98 #define OSC0 OSC
99 #endif
100
101 /* Definition for delay API in clock driver, users can redefine it to the real application. */
102 #ifndef SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY
103 #define SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY (120000000UL)
104 #endif
105
106 /*! @brief Clock ip name array for DMAMUX. */
107 #define DMAMUX_CLOCKS \
108 { \
109 kCLOCK_Dmamux0 \
110 }
111
112 /*! @brief Clock ip name array for RTC. */
113 #define RTC_CLOCKS \
114 { \
115 kCLOCK_Rtc0 \
116 }
117
118 /*! @brief Clock ip name array for ENET. */
119 #define ENET_CLOCKS \
120 { \
121 kCLOCK_Enet0 \
122 }
123
124 /*! @brief Clock ip name array for PORT. */
125 #define PORT_CLOCKS \
126 { \
127 kCLOCK_PortA, kCLOCK_PortB, kCLOCK_PortC, kCLOCK_PortD, kCLOCK_PortE \
128 }
129
130 /*! @brief Clock ip name array for SAI. */
131 #define SAI_CLOCKS \
132 { \
133 kCLOCK_Sai0 \
134 }
135
136 /*! @brief Clock ip name array for FLEXBUS. */
137 #define FLEXBUS_CLOCKS \
138 { \
139 kCLOCK_Flexbus0 \
140 }
141
142 /*! @brief Clock ip name array for EWM. */
143 #define EWM_CLOCKS \
144 { \
145 kCLOCK_Ewm0 \
146 }
147
148 /*! @brief Clock ip name array for PIT. */
149 #define PIT_CLOCKS \
150 { \
151 kCLOCK_Pit0 \
152 }
153
154 /*! @brief Clock ip name array for DSPI. */
155 #define DSPI_CLOCKS \
156 { \
157 kCLOCK_Spi0, kCLOCK_Spi1, kCLOCK_Spi2 \
158 }
159
160 /*! @brief Clock ip name array for LPTMR. */
161 #define LPTMR_CLOCKS \
162 { \
163 kCLOCK_Lptmr0 \
164 }
165
166 /*! @brief Clock ip name array for SDHC. */
167 #define SDHC_CLOCKS \
168 { \
169 kCLOCK_Sdhc0 \
170 }
171
172 /*! @brief Clock ip name array for FTM. */
173 #define FTM_CLOCKS \
174 { \
175 kCLOCK_Ftm0, kCLOCK_Ftm1, kCLOCK_Ftm2, kCLOCK_Ftm3 \
176 }
177
178 /*! @brief Clock ip name array for EDMA. */
179 #define EDMA_CLOCKS \
180 { \
181 kCLOCK_Dma0 \
182 }
183
184 /*! @brief Clock ip name array for FLEXCAN. */
185 #define FLEXCAN_CLOCKS \
186 { \
187 kCLOCK_Flexcan0 \
188 }
189
190 /*! @brief Clock ip name array for DAC. */
191 #define DAC_CLOCKS \
192 { \
193 kCLOCK_Dac0, kCLOCK_Dac1 \
194 }
195
196 /*! @brief Clock ip name array for ADC16. */
197 #define ADC16_CLOCKS \
198 { \
199 kCLOCK_Adc0, kCLOCK_Adc1 \
200 }
201
202 /*! @brief Clock ip name array for MPU. */
203 #define SYSMPU_CLOCKS \
204 { \
205 kCLOCK_Sysmpu0 \
206 }
207
208 /*! @brief Clock ip name array for VREF. */
209 #define VREF_CLOCKS \
210 { \
211 kCLOCK_Vref0 \
212 }
213
214 /*! @brief Clock ip name array for CMT. */
215 #define CMT_CLOCKS \
216 { \
217 kCLOCK_Cmt0 \
218 }
219
220 /*! @brief Clock ip name array for UART. */
221 #define UART_CLOCKS \
222 { \
223 kCLOCK_Uart0, kCLOCK_Uart1, kCLOCK_Uart2, kCLOCK_Uart3, kCLOCK_Uart4, kCLOCK_Uart5 \
224 }
225
226 /*! @brief Clock ip name array for RNGA. */
227 #define RNGA_CLOCKS \
228 { \
229 kCLOCK_Rnga0 \
230 }
231
232 /*! @brief Clock ip name array for CRC. */
233 #define CRC_CLOCKS \
234 { \
235 kCLOCK_Crc0 \
236 }
237
238 /*! @brief Clock ip name array for I2C. */
239 #define I2C_CLOCKS \
240 { \
241 kCLOCK_I2c0, kCLOCK_I2c1, kCLOCK_I2c2 \
242 }
243
244 /*! @brief Clock ip name array for PDB. */
245 #define PDB_CLOCKS \
246 { \
247 kCLOCK_Pdb0 \
248 }
249
250 /*! @brief Clock ip name array for FTF. */
251 #define FTF_CLOCKS \
252 { \
253 kCLOCK_Ftf0 \
254 }
255
256 /*! @brief Clock ip name array for CMP. */
257 #define CMP_CLOCKS \
258 { \
259 kCLOCK_Cmp0, kCLOCK_Cmp1, kCLOCK_Cmp2 \
260 }
261
262 /*!
263 * @brief LPO clock frequency.
264 */
265 #define LPO_CLK_FREQ 1000U
266
267 /*! @brief Peripherals clock source definition. */
268 #define SYS_CLK kCLOCK_CoreSysClk
269 #define BUS_CLK kCLOCK_BusClk
270
271 #define I2C0_CLK_SRC BUS_CLK
272 #define I2C1_CLK_SRC BUS_CLK
273 #define I2C2_CLK_SRC BUS_CLK
274 #define DSPI0_CLK_SRC BUS_CLK
275 #define DSPI1_CLK_SRC BUS_CLK
276 #define DSPI2_CLK_SRC BUS_CLK
277 #define UART0_CLK_SRC SYS_CLK
278 #define UART1_CLK_SRC SYS_CLK
279 #define UART2_CLK_SRC BUS_CLK
280 #define UART3_CLK_SRC BUS_CLK
281 #define UART4_CLK_SRC BUS_CLK
282 #define UART5_CLK_SRC BUS_CLK
283
284 /*! @brief Clock name used to get clock frequency. */
285 typedef enum _clock_name
286 {
287
288 /* ----------------------------- System layer clock -------------------------------*/
289 kCLOCK_CoreSysClk, /*!< Core/system clock */
290 kCLOCK_PlatClk, /*!< Platform clock */
291 kCLOCK_BusClk, /*!< Bus clock */
292 kCLOCK_FlexBusClk, /*!< FlexBus clock */
293 kCLOCK_FlashClk, /*!< Flash clock */
294 kCLOCK_FastPeriphClk, /*!< Fast peripheral clock */
295 kCLOCK_PllFllSelClk, /*!< The clock after SIM[PLLFLLSEL]. */
296
297 /* ---------------------------------- OSC clock -----------------------------------*/
298 kCLOCK_Er32kClk, /*!< External reference 32K clock (ERCLK32K) */
299 kCLOCK_Osc0ErClk, /*!< OSC0 external reference clock (OSC0ERCLK) */
300 kCLOCK_Osc1ErClk, /*!< OSC1 external reference clock (OSC1ERCLK) */
301 kCLOCK_Osc0ErClkUndiv, /*!< OSC0 external reference undivided clock(OSC0ERCLK_UNDIV). */
302
303 /* ----------------------------- MCG and MCG-Lite clock ---------------------------*/
304 kCLOCK_McgFixedFreqClk, /*!< MCG fixed frequency clock (MCGFFCLK) */
305 kCLOCK_McgInternalRefClk, /*!< MCG internal reference clock (MCGIRCLK) */
306 kCLOCK_McgFllClk, /*!< MCGFLLCLK */
307 kCLOCK_McgPll0Clk, /*!< MCGPLL0CLK */
308 kCLOCK_McgPll1Clk, /*!< MCGPLL1CLK */
309 kCLOCK_McgExtPllClk, /*!< EXT_PLLCLK */
310 kCLOCK_McgPeriphClk, /*!< MCG peripheral clock (MCGPCLK) */
311 kCLOCK_McgIrc48MClk, /*!< MCG IRC48M clock */
312
313 /* --------------------------------- Other clock ----------------------------------*/
314 kCLOCK_LpoClk, /*!< LPO clock */
315
316 } clock_name_t;
317
318 /*! @brief USB clock source definition. */
319 typedef enum _clock_usb_src
320 {
321 kCLOCK_UsbSrcPll0 = SIM_SOPT2_USBSRC(1U) | SIM_SOPT2_PLLFLLSEL(1U), /*!< Use PLL0. */
322 kCLOCK_UsbSrcIrc48M = SIM_SOPT2_USBSRC(1U) | SIM_SOPT2_PLLFLLSEL(3U), /*!< Use IRC48M. */
323 kCLOCK_UsbSrcExt = SIM_SOPT2_USBSRC(0U) /*!< Use USB_CLKIN. */
324 } clock_usb_src_t;
325
326 /*------------------------------------------------------------------------------
327
328 clock_gate_t definition:
329
330 31 16 0
331 -----------------------------------------------------------------
332 | SIM_SCGC register offset | control bit offset in SCGC |
333 -----------------------------------------------------------------
334
335 For example, the SDHC clock gate is controlled by SIM_SCGC3[17], the
336 SIM_SCGC3 offset in SIM is 0x1030, then kCLOCK_GateSdhc0 is defined as
337
338 kCLOCK_GateSdhc0 = (0x1030 << 16) | 17;
339
340 ------------------------------------------------------------------------------*/
341
342 #define CLK_GATE_REG_OFFSET_SHIFT 16U
343 #define CLK_GATE_REG_OFFSET_MASK 0xFFFF0000U
344 #define CLK_GATE_BIT_SHIFT_SHIFT 0U
345 #define CLK_GATE_BIT_SHIFT_MASK 0x0000FFFFU
346
347 #define CLK_GATE_DEFINE(reg_offset, bit_shift) \
348 ((((reg_offset) << CLK_GATE_REG_OFFSET_SHIFT) & CLK_GATE_REG_OFFSET_MASK) | \
349 (((bit_shift) << CLK_GATE_BIT_SHIFT_SHIFT) & CLK_GATE_BIT_SHIFT_MASK))
350
351 #define CLK_GATE_ABSTRACT_REG_OFFSET(x) (((x)&CLK_GATE_REG_OFFSET_MASK) >> CLK_GATE_REG_OFFSET_SHIFT)
352 #define CLK_GATE_ABSTRACT_BITS_SHIFT(x) (((x)&CLK_GATE_BIT_SHIFT_MASK) >> CLK_GATE_BIT_SHIFT_SHIFT)
353
354 /*! @brief Clock gate name used for CLOCK_EnableClock/CLOCK_DisableClock. */
355 typedef enum _clock_ip_name
356 {
357 kCLOCK_IpInvalid = 0U,
358 kCLOCK_I2c2 = CLK_GATE_DEFINE(0x1028U, 6U),
359 kCLOCK_Uart4 = CLK_GATE_DEFINE(0x1028U, 10U),
360 kCLOCK_Uart5 = CLK_GATE_DEFINE(0x1028U, 11U),
361
362 kCLOCK_Enet0 = CLK_GATE_DEFINE(0x102CU, 0U),
363 kCLOCK_Dac0 = CLK_GATE_DEFINE(0x102CU, 12U),
364 kCLOCK_Dac1 = CLK_GATE_DEFINE(0x102CU, 13U),
365
366 kCLOCK_Spi2 = CLK_GATE_DEFINE(0x1030U, 12U),
367 kCLOCK_Sdhc0 = CLK_GATE_DEFINE(0x1030U, 17U),
368 kCLOCK_Ftm3 = CLK_GATE_DEFINE(0x1030U, 25U),
369 kCLOCK_Adc1 = CLK_GATE_DEFINE(0x1030U, 27U),
370
371 kCLOCK_Ewm0 = CLK_GATE_DEFINE(0x1034U, 1U),
372 kCLOCK_Cmt0 = CLK_GATE_DEFINE(0x1034U, 2U),
373 kCLOCK_I2c0 = CLK_GATE_DEFINE(0x1034U, 6U),
374 kCLOCK_I2c1 = CLK_GATE_DEFINE(0x1034U, 7U),
375 kCLOCK_Uart0 = CLK_GATE_DEFINE(0x1034U, 10U),
376 kCLOCK_Uart1 = CLK_GATE_DEFINE(0x1034U, 11U),
377 kCLOCK_Uart2 = CLK_GATE_DEFINE(0x1034U, 12U),
378 kCLOCK_Uart3 = CLK_GATE_DEFINE(0x1034U, 13U),
379 kCLOCK_Usbfs0 = CLK_GATE_DEFINE(0x1034U, 18U),
380 kCLOCK_Cmp0 = CLK_GATE_DEFINE(0x1034U, 19U),
381 kCLOCK_Cmp1 = CLK_GATE_DEFINE(0x1034U, 19U),
382 kCLOCK_Cmp2 = CLK_GATE_DEFINE(0x1034U, 19U),
383 kCLOCK_Vref0 = CLK_GATE_DEFINE(0x1034U, 20U),
384
385 kCLOCK_Lptmr0 = CLK_GATE_DEFINE(0x1038U, 0U),
386 kCLOCK_PortA = CLK_GATE_DEFINE(0x1038U, 9U),
387 kCLOCK_PortB = CLK_GATE_DEFINE(0x1038U, 10U),
388 kCLOCK_PortC = CLK_GATE_DEFINE(0x1038U, 11U),
389 kCLOCK_PortD = CLK_GATE_DEFINE(0x1038U, 12U),
390 kCLOCK_PortE = CLK_GATE_DEFINE(0x1038U, 13U),
391
392 kCLOCK_Ftf0 = CLK_GATE_DEFINE(0x103CU, 0U),
393 kCLOCK_Dmamux0 = CLK_GATE_DEFINE(0x103CU, 1U),
394 kCLOCK_Flexcan0 = CLK_GATE_DEFINE(0x103CU, 4U),
395 kCLOCK_Rnga0 = CLK_GATE_DEFINE(0x103CU, 9U),
396 kCLOCK_Spi0 = CLK_GATE_DEFINE(0x103CU, 12U),
397 kCLOCK_Spi1 = CLK_GATE_DEFINE(0x103CU, 13U),
398 kCLOCK_Sai0 = CLK_GATE_DEFINE(0x103CU, 15U),
399 kCLOCK_Crc0 = CLK_GATE_DEFINE(0x103CU, 18U),
400 kCLOCK_Usbdcd0 = CLK_GATE_DEFINE(0x103CU, 21U),
401 kCLOCK_Pdb0 = CLK_GATE_DEFINE(0x103CU, 22U),
402 kCLOCK_Pit0 = CLK_GATE_DEFINE(0x103CU, 23U),
403 kCLOCK_Ftm0 = CLK_GATE_DEFINE(0x103CU, 24U),
404 kCLOCK_Ftm1 = CLK_GATE_DEFINE(0x103CU, 25U),
405 kCLOCK_Ftm2 = CLK_GATE_DEFINE(0x103CU, 26U),
406 kCLOCK_Adc0 = CLK_GATE_DEFINE(0x103CU, 27U),
407 kCLOCK_Rtc0 = CLK_GATE_DEFINE(0x103CU, 29U),
408
409 kCLOCK_Flexbus0 = CLK_GATE_DEFINE(0x1040U, 0U),
410 kCLOCK_Dma0 = CLK_GATE_DEFINE(0x1040U, 1U),
411 kCLOCK_Sysmpu0 = CLK_GATE_DEFINE(0x1040U, 2U),
412 } clock_ip_name_t;
413
414 /*!@brief SIM configuration structure for clock setting. */
415 typedef struct _sim_clock_config
416 {
417 uint8_t pllFllSel; /*!< PLL/FLL/IRC48M selection. */
418 uint8_t er32kSrc; /*!< ERCLK32K source selection. */
419 uint32_t clkdiv1; /*!< SIM_CLKDIV1. */
420 } sim_clock_config_t;
421
422 /*! @brief OSC work mode. */
423 typedef enum _osc_mode
424 {
425 kOSC_ModeExt = 0U, /*!< Use an external clock. */
426 #if (defined(MCG_C2_EREFS_MASK) && !(defined(MCG_C2_EREFS0_MASK)))
427 kOSC_ModeOscLowPower = MCG_C2_EREFS_MASK, /*!< Oscillator low power. */
428 #else
429 kOSC_ModeOscLowPower = MCG_C2_EREFS0_MASK, /*!< Oscillator low power. */
430 #endif
431 kOSC_ModeOscHighGain = 0U
432 #if (defined(MCG_C2_EREFS_MASK) && !(defined(MCG_C2_EREFS0_MASK)))
433 | MCG_C2_EREFS_MASK
434 #else
435 | MCG_C2_EREFS0_MASK
436 #endif
437 #if (defined(MCG_C2_HGO_MASK) && !(defined(MCG_C2_HGO0_MASK)))
438 | MCG_C2_HGO_MASK, /*!< Oscillator high gain. */
439 #else
440 | MCG_C2_HGO0_MASK, /*!< Oscillator high gain. */
441 #endif
442 } osc_mode_t;
443
444 /*! @brief Oscillator capacitor load setting.*/
445 enum _osc_cap_load
446 {
447 kOSC_Cap2P = OSC_CR_SC2P_MASK, /*!< 2 pF capacitor load */
448 kOSC_Cap4P = OSC_CR_SC4P_MASK, /*!< 4 pF capacitor load */
449 kOSC_Cap8P = OSC_CR_SC8P_MASK, /*!< 8 pF capacitor load */
450 kOSC_Cap16P = OSC_CR_SC16P_MASK /*!< 16 pF capacitor load */
451 };
452
453 /*! @brief OSCERCLK enable mode. */
454 enum _oscer_enable_mode
455 {
456 kOSC_ErClkEnable = OSC_CR_ERCLKEN_MASK, /*!< Enable. */
457 kOSC_ErClkEnableInStop = OSC_CR_EREFSTEN_MASK /*!< Enable in stop mode. */
458 };
459
460 /*! @brief OSC configuration for OSCERCLK. */
461 typedef struct _oscer_config
462 {
463 uint8_t enableMode; /*!< OSCERCLK enable mode. OR'ed value of @ref _oscer_enable_mode. */
464
465 } oscer_config_t;
466
467 /*!
468 * @brief OSC Initialization Configuration Structure
469 *
470 * Defines the configuration data structure to initialize the OSC.
471 * When porting to a new board, set the following members
472 * according to the board setting:
473 * 1. freq: The external frequency.
474 * 2. workMode: The OSC module mode.
475 */
476 typedef struct _osc_config
477 {
478 uint32_t freq; /*!< External clock frequency. */
479 uint8_t capLoad; /*!< Capacitor load setting. */
480 osc_mode_t workMode; /*!< OSC work mode setting. */
481 oscer_config_t oscerConfig; /*!< Configuration for OSCERCLK. */
482 } osc_config_t;
483
484 /*! @brief MCG FLL reference clock source select. */
485 typedef enum _mcg_fll_src
486 {
487 kMCG_FllSrcExternal, /*!< External reference clock is selected */
488 kMCG_FllSrcInternal /*!< The slow internal reference clock is selected */
489 } mcg_fll_src_t;
490
491 /*! @brief MCG internal reference clock select */
492 typedef enum _mcg_irc_mode
493 {
494 kMCG_IrcSlow, /*!< Slow internal reference clock selected */
495 kMCG_IrcFast /*!< Fast internal reference clock selected */
496 } mcg_irc_mode_t;
497
498 /*! @brief MCG DCO Maximum Frequency with 32.768 kHz Reference */
499 typedef enum _mcg_dmx32
500 {
501 kMCG_Dmx32Default, /*!< DCO has a default range of 25% */
502 kMCG_Dmx32Fine /*!< DCO is fine-tuned for maximum frequency with 32.768 kHz reference */
503 } mcg_dmx32_t;
504
505 /*! @brief MCG DCO range select */
506 typedef enum _mcg_drs
507 {
508 kMCG_DrsLow, /*!< Low frequency range */
509 kMCG_DrsMid, /*!< Mid frequency range */
510 kMCG_DrsMidHigh, /*!< Mid-High frequency range */
511 kMCG_DrsHigh /*!< High frequency range */
512 } mcg_drs_t;
513
514 /*! @brief MCG PLL reference clock select */
515 typedef enum _mcg_pll_ref_src
516 {
517 kMCG_PllRefOsc0, /*!< Selects OSC0 as PLL reference clock */
518 kMCG_PllRefOsc1 /*!< Selects OSC1 as PLL reference clock */
519 } mcg_pll_ref_src_t;
520
521 /*! @brief MCGOUT clock source. */
522 typedef enum _mcg_clkout_src
523 {
524 kMCG_ClkOutSrcOut, /*!< Output of the FLL is selected (reset default) */
525 kMCG_ClkOutSrcInternal, /*!< Internal reference clock is selected */
526 kMCG_ClkOutSrcExternal, /*!< External reference clock is selected */
527 } mcg_clkout_src_t;
528
529 /*! @brief MCG Automatic Trim Machine Select */
530 typedef enum _mcg_atm_select
531 {
532 kMCG_AtmSel32k, /*!< 32 kHz Internal Reference Clock selected */
533 kMCG_AtmSel4m /*!< 4 MHz Internal Reference Clock selected */
534 } mcg_atm_select_t;
535
536 /*! @brief MCG OSC Clock Select */
537 typedef enum _mcg_oscsel
538 {
539 kMCG_OscselOsc, /*!< Selects System Oscillator (OSCCLK) */
540 kMCG_OscselRtc, /*!< Selects 32 kHz RTC Oscillator */
541 kMCG_OscselIrc /*!< Selects 48 MHz IRC Oscillator */
542 } mcg_oscsel_t;
543
544 /*! @brief MCG PLLCS select */
545 typedef enum _mcg_pll_clk_select
546 {
547 kMCG_PllClkSelPll0, /*!< PLL0 output clock is selected */
548 kMCG_PllClkSelPll1 /* PLL1 output clock is selected */
549 } mcg_pll_clk_select_t;
550
551 /*! @brief MCG clock monitor mode. */
552 typedef enum _mcg_monitor_mode
553 {
554 kMCG_MonitorNone, /*!< Clock monitor is disabled. */
555 kMCG_MonitorInt, /*!< Trigger interrupt when clock lost. */
556 kMCG_MonitorReset /*!< System reset when clock lost. */
557 } mcg_monitor_mode_t;
558
559 /*! @brief MCG status. Enumeration _mcg_status */
560 enum
561 {
562 kStatus_MCG_ModeUnreachable = MAKE_STATUS(kStatusGroup_MCG, 0U), /*!< Can't switch to target mode. */
563 kStatus_MCG_ModeInvalid = MAKE_STATUS(kStatusGroup_MCG, 1U), /*!< Current mode invalid for the specific
564 function. */
565 kStatus_MCG_AtmBusClockInvalid = MAKE_STATUS(kStatusGroup_MCG, 2U), /*!< Invalid bus clock for ATM. */
566 kStatus_MCG_AtmDesiredFreqInvalid = MAKE_STATUS(kStatusGroup_MCG, 3U), /*!< Invalid desired frequency for ATM. */
567 kStatus_MCG_AtmIrcUsed = MAKE_STATUS(kStatusGroup_MCG, 4U), /*!< IRC is used when using ATM. */
568 kStatus_MCG_AtmHardwareFail = MAKE_STATUS(kStatusGroup_MCG, 5U), /*!< Hardware fail occurs during ATM. */
569 kStatus_MCG_SourceUsed = MAKE_STATUS(kStatusGroup_MCG, 6U) /*!< Can't change the clock source because
570 it is in use. */
571 };
572
573 /*! @brief MCG status flags. Enumeration _mcg_status_flags_t */
574 enum
575 {
576 kMCG_Osc0LostFlag = (1U << 0U), /*!< OSC0 lost. */
577 kMCG_Osc0InitFlag = (1U << 1U), /*!< OSC0 crystal initialized. */
578 kMCG_RtcOscLostFlag = (1U << 4U), /*!< RTC OSC lost. */
579 kMCG_Pll0LostFlag = (1U << 5U), /*!< PLL0 lost. */
580 kMCG_Pll0LockFlag = (1U << 6U), /*!< PLL0 locked. */
581 };
582
583 /*! @brief MCG internal reference clock (MCGIRCLK) enable mode definition. Enumeration _mcg_irclk_enable_mode */
584 enum
585 {
586 kMCG_IrclkEnable = MCG_C1_IRCLKEN_MASK, /*!< MCGIRCLK enable. */
587 kMCG_IrclkEnableInStop = MCG_C1_IREFSTEN_MASK /*!< MCGIRCLK enable in stop mode. */
588 };
589
590 /*! @brief MCG PLL clock enable mode definition. Enumeration _mcg_pll_enable_mode */
591 enum
592 {
593 kMCG_PllEnableIndependent = MCG_C5_PLLCLKEN0_MASK, /*!< MCGPLLCLK enable independent of the
594 MCG clock mode. Generally, the PLL
595 is disabled in FLL modes
596 (FEI/FBI/FEE/FBE). Setting the PLL clock
597 enable independent, enables the
598 PLL in the FLL modes. */
599 kMCG_PllEnableInStop = MCG_C5_PLLSTEN0_MASK /*!< MCGPLLCLK enable in STOP mode. */
600 };
601
602 /*! @brief MCG mode definitions */
603 typedef enum _mcg_mode
604 {
605 kMCG_ModeFEI = 0U, /*!< FEI - FLL Engaged Internal */
606 kMCG_ModeFBI, /*!< FBI - FLL Bypassed Internal */
607 kMCG_ModeBLPI, /*!< BLPI - Bypassed Low Power Internal */
608 kMCG_ModeFEE, /*!< FEE - FLL Engaged External */
609 kMCG_ModeFBE, /*!< FBE - FLL Bypassed External */
610 kMCG_ModeBLPE, /*!< BLPE - Bypassed Low Power External */
611 kMCG_ModePBE, /*!< PBE - PLL Bypassed External */
612 kMCG_ModePEE, /*!< PEE - PLL Engaged External */
613 kMCG_ModeError /*!< Unknown mode */
614 } mcg_mode_t;
615
616 /*! @brief MCG PLL configuration. */
617 typedef struct _mcg_pll_config
618 {
619 uint8_t enableMode; /*!< Enable mode. OR'ed value of enumeration _mcg_pll_enable_mode. */
620 uint8_t prdiv; /*!< Reference divider PRDIV. */
621 uint8_t vdiv; /*!< VCO divider VDIV. */
622 } mcg_pll_config_t;
623
624 /*! @brief MCG mode change configuration structure
625 *
626 * When porting to a new board, set the following members
627 * according to the board setting:
628 * 1. frdiv: If the FLL uses the external reference clock, set this
629 * value to ensure that the external reference clock divided by frdiv is
630 * in the 31.25 kHz to 39.0625 kHz range.
631 * 2. The PLL reference clock divider PRDIV: PLL reference clock frequency after
632 * PRDIV should be in the FSL_FEATURE_MCG_PLL_REF_MIN to
633 * FSL_FEATURE_MCG_PLL_REF_MAX range.
634 */
635 typedef struct _mcg_config
636 {
637 mcg_mode_t mcgMode; /*!< MCG mode. */
638
639 /* ----------------------- MCGIRCCLK settings ------------------------ */
640 uint8_t irclkEnableMode; /*!< MCGIRCLK enable mode. */
641 mcg_irc_mode_t ircs; /*!< Source, MCG_C2[IRCS]. */
642 uint8_t fcrdiv; /*!< Divider, MCG_SC[FCRDIV]. */
643
644 /* ------------------------ MCG FLL settings ------------------------- */
645 uint8_t frdiv; /*!< Divider MCG_C1[FRDIV]. */
646 mcg_drs_t drs; /*!< DCO range MCG_C4[DRST_DRS]. */
647 mcg_dmx32_t dmx32; /*!< MCG_C4[DMX32]. */
648 mcg_oscsel_t oscsel; /*!< OSC select MCG_C7[OSCSEL]. */
649
650 /* ------------------------ MCG PLL settings ------------------------- */
651 mcg_pll_config_t pll0Config; /*!< MCGPLL0CLK configuration. */
652
653 } mcg_config_t;
654
655 /*******************************************************************************
656 * API
657 ******************************************************************************/
658
659 #if defined(__cplusplus)
660 extern "C" {
661 #endif /* __cplusplus */
662
663 /*!
664 * @brief Enable the clock for specific IP.
665 *
666 * @param name Which clock to enable, see \ref clock_ip_name_t.
667 */
CLOCK_EnableClock(clock_ip_name_t name)668 static inline void CLOCK_EnableClock(clock_ip_name_t name)
669 {
670 uint32_t regAddr = SIM_BASE + CLK_GATE_ABSTRACT_REG_OFFSET((uint32_t)name);
671 (*(volatile uint32_t *)regAddr) |= (1UL << CLK_GATE_ABSTRACT_BITS_SHIFT((uint32_t)name));
672 }
673
674 /*!
675 * @brief Disable the clock for specific IP.
676 *
677 * @param name Which clock to disable, see \ref clock_ip_name_t.
678 */
CLOCK_DisableClock(clock_ip_name_t name)679 static inline void CLOCK_DisableClock(clock_ip_name_t name)
680 {
681 uint32_t regAddr = SIM_BASE + CLK_GATE_ABSTRACT_REG_OFFSET((uint32_t)name);
682 (*(volatile uint32_t *)regAddr) &= ~(1UL << CLK_GATE_ABSTRACT_BITS_SHIFT((uint32_t)name));
683 }
684
685 /*!
686 * @brief Set ERCLK32K source.
687 *
688 * @param src The value to set ERCLK32K clock source.
689 */
CLOCK_SetEr32kClock(uint32_t src)690 static inline void CLOCK_SetEr32kClock(uint32_t src)
691 {
692 SIM->SOPT1 = ((SIM->SOPT1 & ~SIM_SOPT1_OSC32KSEL_MASK) | SIM_SOPT1_OSC32KSEL(src));
693 }
694
695 /*!
696 * @brief Set SDHC0 clock source.
697 *
698 * @param src The value to set SDHC0 clock source.
699 */
CLOCK_SetSdhc0Clock(uint32_t src)700 static inline void CLOCK_SetSdhc0Clock(uint32_t src)
701 {
702 SIM->SOPT2 = ((SIM->SOPT2 & ~SIM_SOPT2_SDHCSRC_MASK) | SIM_SOPT2_SDHCSRC(src));
703 }
704
705 /*!
706 * @brief Set enet timestamp clock source.
707 *
708 * @param src The value to set enet timestamp clock source.
709 */
CLOCK_SetEnetTime0Clock(uint32_t src)710 static inline void CLOCK_SetEnetTime0Clock(uint32_t src)
711 {
712 SIM->SOPT2 = ((SIM->SOPT2 & ~SIM_SOPT2_TIMESRC_MASK) | SIM_SOPT2_TIMESRC(src));
713 }
714
715 /*!
716 * @brief Set RMII clock source.
717 *
718 * @param src The value to set RMII clock source.
719 */
CLOCK_SetRmii0Clock(uint32_t src)720 static inline void CLOCK_SetRmii0Clock(uint32_t src)
721 {
722 SIM->SOPT2 = ((SIM->SOPT2 & ~SIM_SOPT2_RMIISRC_MASK) | SIM_SOPT2_RMIISRC(src));
723 }
724
725 /*!
726 * @brief Set debug trace clock source.
727 *
728 * @param src The value to set debug trace clock source.
729 */
CLOCK_SetTraceClock(uint32_t src)730 static inline void CLOCK_SetTraceClock(uint32_t src)
731 {
732 SIM->SOPT2 = ((SIM->SOPT2 & ~SIM_SOPT2_TRACECLKSEL_MASK) | SIM_SOPT2_TRACECLKSEL(src));
733 }
734
735 /*!
736 * @brief Set PLLFLLSEL clock source.
737 *
738 * @param src The value to set PLLFLLSEL clock source.
739 */
CLOCK_SetPllFllSelClock(uint32_t src)740 static inline void CLOCK_SetPllFllSelClock(uint32_t src)
741 {
742 SIM->SOPT2 = ((SIM->SOPT2 & ~SIM_SOPT2_PLLFLLSEL_MASK) | SIM_SOPT2_PLLFLLSEL(src));
743 }
744
745 /*!
746 * @brief Set CLKOUT source.
747 *
748 * @param src The value to set CLKOUT source.
749 */
CLOCK_SetClkOutClock(uint32_t src)750 static inline void CLOCK_SetClkOutClock(uint32_t src)
751 {
752 SIM->SOPT2 = ((SIM->SOPT2 & ~SIM_SOPT2_CLKOUTSEL_MASK) | SIM_SOPT2_CLKOUTSEL(src));
753 }
754
755 /*!
756 * @brief Set RTC_CLKOUT source.
757 *
758 * @param src The value to set RTC_CLKOUT source.
759 */
CLOCK_SetRtcClkOutClock(uint32_t src)760 static inline void CLOCK_SetRtcClkOutClock(uint32_t src)
761 {
762 SIM->SOPT2 = ((SIM->SOPT2 & ~SIM_SOPT2_RTCCLKOUTSEL_MASK) | SIM_SOPT2_RTCCLKOUTSEL(src));
763 }
764
765 /*! @brief Enable USB FS clock.
766 *
767 * @param src USB FS clock source.
768 * @param freq The frequency specified by src.
769 * @retval true The clock is set successfully.
770 * @retval false The clock source is invalid to get proper USB FS clock.
771 */
772 bool CLOCK_EnableUsbfs0Clock(clock_usb_src_t src, uint32_t freq);
773
774 /*! @brief Disable USB FS clock.
775 *
776 * Disable USB FS clock.
777 */
CLOCK_DisableUsbfs0Clock(void)778 static inline void CLOCK_DisableUsbfs0Clock(void)
779 {
780 CLOCK_DisableClock(kCLOCK_Usbfs0);
781 }
782
783 /*!
784 * @brief System clock divider
785 *
786 * Set the SIM_CLKDIV1[OUTDIV1], SIM_CLKDIV1[OUTDIV2], SIM_CLKDIV1[OUTDIV3], SIM_CLKDIV1[OUTDIV4].
787 *
788 * @param outdiv1 Clock 1 output divider value.
789 *
790 * @param outdiv2 Clock 2 output divider value.
791 *
792 * @param outdiv3 Clock 3 output divider value.
793 *
794 * @param outdiv4 Clock 4 output divider value.
795 */
CLOCK_SetOutDiv(uint32_t outdiv1,uint32_t outdiv2,uint32_t outdiv3,uint32_t outdiv4)796 static inline void CLOCK_SetOutDiv(uint32_t outdiv1, uint32_t outdiv2, uint32_t outdiv3, uint32_t outdiv4)
797 {
798 SIM->CLKDIV1 = SIM_CLKDIV1_OUTDIV1(outdiv1) | SIM_CLKDIV1_OUTDIV2(outdiv2) | SIM_CLKDIV1_OUTDIV3(outdiv3) |
799 SIM_CLKDIV1_OUTDIV4(outdiv4);
800 }
801
802 /*!
803 * @brief Gets the clock frequency for a specific clock name.
804 *
805 * This function checks the current clock configurations and then calculates
806 * the clock frequency for a specific clock name defined in clock_name_t.
807 * The MCG must be properly configured before using this function.
808 *
809 * @param clockName Clock names defined in clock_name_t
810 * @return Clock frequency value in Hertz
811 */
812 uint32_t CLOCK_GetFreq(clock_name_t clockName);
813
814 /*!
815 * @brief Get the core clock or system clock frequency.
816 *
817 * @return Clock frequency in Hz.
818 */
819 uint32_t CLOCK_GetCoreSysClkFreq(void);
820
821 /*!
822 * @brief Get the platform clock frequency.
823 *
824 * @return Clock frequency in Hz.
825 */
826 uint32_t CLOCK_GetPlatClkFreq(void);
827
828 /*!
829 * @brief Get the bus clock frequency.
830 *
831 * @return Clock frequency in Hz.
832 */
833 uint32_t CLOCK_GetBusClkFreq(void);
834
835 /*!
836 * @brief Get the flexbus clock frequency.
837 *
838 * @return Clock frequency in Hz.
839 */
840 uint32_t CLOCK_GetFlexBusClkFreq(void);
841
842 /*!
843 * @brief Get the flash clock frequency.
844 *
845 * @return Clock frequency in Hz.
846 */
847 uint32_t CLOCK_GetFlashClkFreq(void);
848
849 /*!
850 * @brief Get the output clock frequency selected by SIM[PLLFLLSEL].
851 *
852 * @return Clock frequency in Hz.
853 */
854 uint32_t CLOCK_GetPllFllSelClkFreq(void);
855
856 /*!
857 * @brief Get the external reference 32K clock frequency (ERCLK32K).
858 *
859 * @return Clock frequency in Hz.
860 */
861 uint32_t CLOCK_GetEr32kClkFreq(void);
862
863 /*!
864 * @brief Get the OSC0 external reference clock frequency (OSC0ERCLK).
865 *
866 * @return Clock frequency in Hz.
867 */
868 uint32_t CLOCK_GetOsc0ErClkFreq(void);
869
870 /*!
871 * @brief Set the clock configure in SIM module.
872 *
873 * This function sets system layer clock settings in SIM module.
874 *
875 * @param config Pointer to the configure structure.
876 */
877 void CLOCK_SetSimConfig(sim_clock_config_t const *config);
878
879 /*!
880 * @brief Set the system clock dividers in SIM to safe value.
881 *
882 * The system level clocks (core clock, bus clock, flexbus clock and flash clock)
883 * must be in allowed ranges. During MCG clock mode switch, the MCG output clock
884 * changes then the system level clocks may be out of range. This function could
885 * be used before MCG mode change, to make sure system level clocks are in allowed
886 * range.
887 *
888 */
CLOCK_SetSimSafeDivs(void)889 static inline void CLOCK_SetSimSafeDivs(void)
890 {
891 SIM->CLKDIV1 = 0x01240000U;
892 }
893
894 /*! @name MCG frequency functions. */
895 /*@{*/
896
897 /*!
898 * @brief Gets the MCG output clock (MCGOUTCLK) frequency.
899 *
900 * This function gets the MCG output clock frequency in Hz based on the current MCG
901 * register value.
902 *
903 * @return The frequency of MCGOUTCLK.
904 */
905 uint32_t CLOCK_GetOutClkFreq(void);
906
907 /*!
908 * @brief Gets the MCG FLL clock (MCGFLLCLK) frequency.
909 *
910 * This function gets the MCG FLL clock frequency in Hz based on the current MCG
911 * register value. The FLL is enabled in FEI/FBI/FEE/FBE mode and
912 * disabled in low power state in other modes.
913 *
914 * @return The frequency of MCGFLLCLK.
915 */
916 uint32_t CLOCK_GetFllFreq(void);
917
918 /*!
919 * @brief Gets the MCG internal reference clock (MCGIRCLK) frequency.
920 *
921 * This function gets the MCG internal reference clock frequency in Hz based
922 * on the current MCG register value.
923 *
924 * @return The frequency of MCGIRCLK.
925 */
926 uint32_t CLOCK_GetInternalRefClkFreq(void);
927
928 /*!
929 * @brief Gets the MCG fixed frequency clock (MCGFFCLK) frequency.
930 *
931 * This function gets the MCG fixed frequency clock frequency in Hz based
932 * on the current MCG register value.
933 *
934 * @return The frequency of MCGFFCLK.
935 */
936 uint32_t CLOCK_GetFixedFreqClkFreq(void);
937
938 /*!
939 * @brief Gets the MCG PLL0 clock (MCGPLL0CLK) frequency.
940 *
941 * This function gets the MCG PLL0 clock frequency in Hz based on the current MCG
942 * register value.
943 *
944 * @return The frequency of MCGPLL0CLK.
945 */
946 uint32_t CLOCK_GetPll0Freq(void);
947
948 /*@}*/
949
950 /*! @name MCG clock configuration. */
951 /*@{*/
952
953 /*!
954 * @brief Enables or disables the MCG low power.
955 *
956 * Enabling the MCG low power disables the PLL and FLL in bypass modes. In other words,
957 * in FBE and PBE modes, enabling low power sets the MCG to BLPE mode. In FBI and
958 * PBI modes, enabling low power sets the MCG to BLPI mode.
959 * When disabling the MCG low power, the PLL or FLL are enabled based on MCG settings.
960 *
961 * @param enable True to enable MCG low power, false to disable MCG low power.
962 */
CLOCK_SetLowPowerEnable(bool enable)963 static inline void CLOCK_SetLowPowerEnable(bool enable)
964 {
965 if (enable)
966 {
967 MCG->C2 |= MCG_C2_LP_MASK;
968 }
969 else
970 {
971 MCG->C2 &= ~(uint8_t)MCG_C2_LP_MASK;
972 }
973 }
974
975 /*!
976 * @brief Configures the Internal Reference clock (MCGIRCLK).
977 *
978 * This function sets the \c MCGIRCLK base on parameters. It also selects the IRC
979 * source. If the fast IRC is used, this function sets the fast IRC divider.
980 * This function also sets whether the \c MCGIRCLK is enabled in stop mode.
981 * Calling this function in FBI/PBI/BLPI modes may change the system clock. As a result,
982 * using the function in these modes it is not allowed.
983 *
984 * @param enableMode MCGIRCLK enable mode, OR'ed value of the enumeration _mcg_irclk_enable_mode.
985 * @param ircs MCGIRCLK clock source, choose fast or slow.
986 * @param fcrdiv Fast IRC divider setting (\c FCRDIV).
987 * @retval kStatus_MCG_SourceUsed Because the internal reference clock is used as a clock source,
988 * the configuration should not be changed. Otherwise, a glitch occurs.
989 * @retval kStatus_Success MCGIRCLK configuration finished successfully.
990 */
991 status_t CLOCK_SetInternalRefClkConfig(uint8_t enableMode, mcg_irc_mode_t ircs, uint8_t fcrdiv);
992
993 /*!
994 * @brief Selects the MCG external reference clock.
995 *
996 * Selects the MCG external reference clock source, changes the MCG_C7[OSCSEL],
997 * and waits for the clock source to be stable. Because the external reference
998 * clock should not be changed in FEE/FBE/BLPE/PBE/PEE modes, do not call this function in these modes.
999 *
1000 * @param oscsel MCG external reference clock source, MCG_C7[OSCSEL].
1001 * @retval kStatus_MCG_SourceUsed Because the external reference clock is used as a clock source,
1002 * the configuration should not be changed. Otherwise, a glitch occurs.
1003 * @retval kStatus_Success External reference clock set successfully.
1004 */
1005 status_t CLOCK_SetExternalRefClkConfig(mcg_oscsel_t oscsel);
1006
1007 /*!
1008 * @brief Set the FLL external reference clock divider value.
1009 *
1010 * Sets the FLL external reference clock divider value, the register MCG_C1[FRDIV].
1011 *
1012 * @param frdiv The FLL external reference clock divider value, MCG_C1[FRDIV].
1013 */
CLOCK_SetFllExtRefDiv(uint8_t frdiv)1014 static inline void CLOCK_SetFllExtRefDiv(uint8_t frdiv)
1015 {
1016 MCG->C1 = (uint8_t)((MCG->C1 & ~MCG_C1_FRDIV_MASK) | MCG_C1_FRDIV(frdiv));
1017 }
1018
1019 /*!
1020 * @brief Enables the PLL0 in FLL mode.
1021 *
1022 * This function sets us the PLL0 in FLL mode and reconfigures
1023 * the PLL0. Ensure that the PLL reference
1024 * clock is enabled before calling this function and that the PLL0 is not used as a clock source.
1025 * The function CLOCK_CalcPllDiv gets the correct PLL
1026 * divider values.
1027 *
1028 * @param config Pointer to the configuration structure.
1029 */
1030 void CLOCK_EnablePll0(mcg_pll_config_t const *config);
1031
1032 /*!
1033 * @brief Disables the PLL0 in FLL mode.
1034 *
1035 * This function disables the PLL0 in FLL mode. It should be used together with the
1036 * @ref CLOCK_EnablePll0.
1037 */
CLOCK_DisablePll0(void)1038 static inline void CLOCK_DisablePll0(void)
1039 {
1040 MCG->C5 &= (uint8_t)(~(MCG_C5_PLLCLKEN0_MASK | MCG_C5_PLLSTEN0_MASK));
1041 }
1042
1043 /*!
1044 * @brief Calculates the PLL divider setting for a desired output frequency.
1045 *
1046 * This function calculates the correct reference clock divider (\c PRDIV) and
1047 * VCO divider (\c VDIV) to generate a desired PLL output frequency. It returns the
1048 * closest frequency match with the corresponding \c PRDIV/VDIV
1049 * returned from parameters. If a desired frequency is not valid, this function
1050 * returns 0.
1051 *
1052 * @param refFreq PLL reference clock frequency.
1053 * @param desireFreq Desired PLL output frequency.
1054 * @param prdiv PRDIV value to generate desired PLL frequency.
1055 * @param vdiv VDIV value to generate desired PLL frequency.
1056 * @return Closest frequency match that the PLL was able generate.
1057 */
1058 uint32_t CLOCK_CalcPllDiv(uint32_t refFreq, uint32_t desireFreq, uint8_t *prdiv, uint8_t *vdiv);
1059
1060 /*@}*/
1061
1062 /*! @name MCG clock lock monitor functions. */
1063 /*@{*/
1064
1065 /*!
1066 * @brief Sets the OSC0 clock monitor mode.
1067 *
1068 * This function sets the OSC0 clock monitor mode. See @ref mcg_monitor_mode_t for details.
1069 *
1070 * @param mode Monitor mode to set.
1071 */
1072 void CLOCK_SetOsc0MonitorMode(mcg_monitor_mode_t mode);
1073
1074 /*!
1075 * @brief Sets the RTC OSC clock monitor mode.
1076 *
1077 * This function sets the RTC OSC clock monitor mode. See @ref mcg_monitor_mode_t for details.
1078 *
1079 * @param mode Monitor mode to set.
1080 */
1081 void CLOCK_SetRtcOscMonitorMode(mcg_monitor_mode_t mode);
1082
1083 /*!
1084 * @brief Sets the PLL0 clock monitor mode.
1085 *
1086 * This function sets the PLL0 clock monitor mode. See @ref mcg_monitor_mode_t for details.
1087 *
1088 * @param mode Monitor mode to set.
1089 */
1090 void CLOCK_SetPll0MonitorMode(mcg_monitor_mode_t mode);
1091
1092 /*!
1093 * @brief Gets the MCG status flags.
1094 *
1095 * This function gets the MCG clock status flags. All status flags are
1096 * returned as a logical OR of the enumeration refer to _mcg_status_flags_t. To
1097 * check a specific flag, compare the return value with the flag.
1098 *
1099 * Example:
1100 * @code
1101 * To check the clock lost lock status of OSC0 and PLL0.
1102 * uint32_t mcgFlags;
1103 *
1104 * mcgFlags = CLOCK_GetStatusFlags();
1105 *
1106 * if (mcgFlags & kMCG_Osc0LostFlag)
1107 * {
1108 * OSC0 clock lock lost. Do something.
1109 * }
1110 * if (mcgFlags & kMCG_Pll0LostFlag)
1111 * {
1112 * PLL0 clock lock lost. Do something.
1113 * }
1114 * @endcode
1115 *
1116 * @return Logical OR value of the enumeration _mcg_status_flags_t.
1117 */
1118 uint32_t CLOCK_GetStatusFlags(void);
1119
1120 /*!
1121 * @brief Clears the MCG status flags.
1122 *
1123 * This function clears the MCG clock lock lost status. The parameter is a logical
1124 * OR value of the flags to clear. See the enumeration _mcg_status_flags_t.
1125 *
1126 * Example:
1127 * @code
1128 * To clear the clock lost lock status flags of OSC0 and PLL0.
1129 *
1130 * CLOCK_ClearStatusFlags(kMCG_Osc0LostFlag | kMCG_Pll0LostFlag);
1131 * @endcode
1132 *
1133 * @param mask The status flags to clear. This is a logical OR of members of the
1134 * enumeration _mcg_status_flags_t.
1135 */
1136 void CLOCK_ClearStatusFlags(uint32_t mask);
1137
1138 /*@}*/
1139
1140 /*!
1141 * @name OSC configuration
1142 * @{
1143 */
1144
1145 /*!
1146 * @brief Configures the OSC external reference clock (OSCERCLK).
1147 *
1148 * This function configures the OSC external reference clock (OSCERCLK).
1149 * This is an example to enable the OSCERCLK in normal and stop modes and also set
1150 * the output divider to 1:
1151 *
1152 @code
1153 oscer_config_t config =
1154 {
1155 .enableMode = kOSC_ErClkEnable | kOSC_ErClkEnableInStop,
1156 .erclkDiv = 1U,
1157 };
1158
1159 OSC_SetExtRefClkConfig(OSC, &config);
1160 @endcode
1161 *
1162 * @param base OSC peripheral address.
1163 * @param config Pointer to the configuration structure.
1164 */
OSC_SetExtRefClkConfig(OSC_Type * base,oscer_config_t const * config)1165 static inline void OSC_SetExtRefClkConfig(OSC_Type *base, oscer_config_t const *config)
1166 {
1167 uint8_t reg = base->CR;
1168
1169 reg &= (uint8_t)(~(OSC_CR_ERCLKEN_MASK | OSC_CR_EREFSTEN_MASK));
1170 reg |= config->enableMode;
1171
1172 base->CR = reg;
1173 }
1174
1175 /*!
1176 * @brief Sets the capacitor load configuration for the oscillator.
1177 *
1178 * This function sets the specified capacitors configuration for the oscillator.
1179 * This should be done in the early system level initialization function call
1180 * based on the system configuration.
1181 *
1182 * @param base OSC peripheral address.
1183 * @param capLoad OR'ed value for the capacitor load option, see \ref _osc_cap_load.
1184 *
1185 * Example:
1186 @code
1187 To enable only 2 pF and 8 pF capacitor load, please use like this.
1188 OSC_SetCapLoad(OSC, kOSC_Cap2P | kOSC_Cap8P);
1189 @endcode
1190 */
OSC_SetCapLoad(OSC_Type * base,uint8_t capLoad)1191 static inline void OSC_SetCapLoad(OSC_Type *base, uint8_t capLoad)
1192 {
1193 uint8_t reg = base->CR;
1194
1195 reg &= (uint8_t)(~(OSC_CR_SC2P_MASK | OSC_CR_SC4P_MASK | OSC_CR_SC8P_MASK | OSC_CR_SC16P_MASK));
1196 reg |= capLoad;
1197
1198 base->CR = reg;
1199 }
1200
1201 /*!
1202 * @brief Initializes the OSC0.
1203 *
1204 * This function initializes the OSC0 according to the board configuration.
1205 *
1206 * @param config Pointer to the OSC0 configuration structure.
1207 */
1208 void CLOCK_InitOsc0(osc_config_t const *config);
1209
1210 /*!
1211 * @brief Deinitializes the OSC0.
1212 *
1213 * This function deinitializes the OSC0.
1214 */
1215 void CLOCK_DeinitOsc0(void);
1216
1217 /* @} */
1218
1219 /*!
1220 * @name External clock frequency
1221 * @{
1222 */
1223
1224 /*!
1225 * @brief Sets the XTAL0 frequency based on board settings.
1226 *
1227 * @param freq The XTAL0/EXTAL0 input clock frequency in Hz.
1228 */
CLOCK_SetXtal0Freq(uint32_t freq)1229 static inline void CLOCK_SetXtal0Freq(uint32_t freq)
1230 {
1231 g_xtal0Freq = freq;
1232 }
1233
1234 /*!
1235 * @brief Sets the XTAL32/RTC_CLKIN frequency based on board settings.
1236 *
1237 * @param freq The XTAL32/EXTAL32/RTC_CLKIN input clock frequency in Hz.
1238 */
CLOCK_SetXtal32Freq(uint32_t freq)1239 static inline void CLOCK_SetXtal32Freq(uint32_t freq)
1240 {
1241 g_xtal32Freq = freq;
1242 }
1243 /* @} */
1244
1245 /*!
1246 * @name IRCs frequency
1247 * @{
1248 */
1249
1250 /*!
1251 * @brief Set the Slow IRC frequency based on the trimmed value
1252 *
1253 * @param freq The Slow IRC frequency input clock frequency in Hz.
1254 */
1255 void CLOCK_SetSlowIrcFreq(uint32_t freq);
1256
1257 /*!
1258 * @brief Set the Fast IRC frequency based on the trimmed value
1259 *
1260 * @param freq The Fast IRC frequency input clock frequency in Hz.
1261 */
1262 void CLOCK_SetFastIrcFreq(uint32_t freq);
1263 /* @} */
1264
1265 /*!
1266 * @name MCG auto-trim machine.
1267 * @{
1268 */
1269
1270 /*!
1271 * @brief Auto trims the internal reference clock.
1272 *
1273 * This function trims the internal reference clock by using the external clock. If
1274 * successful, it returns the kStatus_Success and the frequency after
1275 * trimming is received in the parameter @p actualFreq. If an error occurs,
1276 * the error code is returned.
1277 *
1278 * @param extFreq External clock frequency, which should be a bus clock.
1279 * @param desireFreq Frequency to trim to.
1280 * @param actualFreq Actual frequency after trimming.
1281 * @param atms Trim fast or slow internal reference clock.
1282 * @retval kStatus_Success ATM success.
1283 * @retval kStatus_MCG_AtmBusClockInvalid The bus clock is not in allowed range for the ATM.
1284 * @retval kStatus_MCG_AtmDesiredFreqInvalid MCGIRCLK could not be trimmed to the desired frequency.
1285 * @retval kStatus_MCG_AtmIrcUsed Could not trim because MCGIRCLK is used as a bus clock source.
1286 * @retval kStatus_MCG_AtmHardwareFail Hardware fails while trimming.
1287 */
1288 status_t CLOCK_TrimInternalRefClk(uint32_t extFreq, uint32_t desireFreq, uint32_t *actualFreq, mcg_atm_select_t atms);
1289 /* @} */
1290
1291 /*! @name MCG mode functions. */
1292 /*@{*/
1293
1294 /*!
1295 * @brief Gets the current MCG mode.
1296 *
1297 * This function checks the MCG registers and determines the current MCG mode.
1298 *
1299 * @return Current MCG mode or error code; See @ref mcg_mode_t.
1300 */
1301 mcg_mode_t CLOCK_GetMode(void);
1302
1303 /*!
1304 * @brief Sets the MCG to FEI mode.
1305 *
1306 * This function sets the MCG to FEI mode. If setting to FEI mode fails
1307 * from the current mode, this function returns an error.
1308 *
1309 * @param dmx32 DMX32 in FEI mode.
1310 * @param drs The DCO range selection.
1311 * @param fllStableDelay Delay function to ensure that the FLL is stable. Passing
1312 * NULL does not cause a delay.
1313 * @retval kStatus_MCG_ModeUnreachable Could not switch to the target mode.
1314 * @retval kStatus_Success Switched to the target mode successfully.
1315 * @note If @p dmx32 is set to kMCG_Dmx32Fine, the slow IRC must not be trimmed
1316 * to a frequency above 32768 Hz.
1317 */
1318 status_t CLOCK_SetFeiMode(mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDelay)(void));
1319
1320 /*!
1321 * @brief Sets the MCG to FEE mode.
1322 *
1323 * This function sets the MCG to FEE mode. If setting to FEE mode fails
1324 * from the current mode, this function returns an error.
1325 *
1326 * @param frdiv FLL reference clock divider setting, FRDIV.
1327 * @param dmx32 DMX32 in FEE mode.
1328 * @param drs The DCO range selection.
1329 * @param fllStableDelay Delay function to make sure FLL is stable. Passing
1330 * NULL does not cause a delay.
1331 *
1332 * @retval kStatus_MCG_ModeUnreachable Could not switch to the target mode.
1333 * @retval kStatus_Success Switched to the target mode successfully.
1334 */
1335 status_t CLOCK_SetFeeMode(uint8_t frdiv, mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDelay)(void));
1336
1337 /*!
1338 * @brief Sets the MCG to FBI mode.
1339 *
1340 * This function sets the MCG to FBI mode. If setting to FBI mode fails
1341 * from the current mode, this function returns an error.
1342 *
1343 * @param dmx32 DMX32 in FBI mode.
1344 * @param drs The DCO range selection.
1345 * @param fllStableDelay Delay function to make sure FLL is stable. If the FLL
1346 * is not used in FBI mode, this parameter can be NULL. Passing
1347 * NULL does not cause a delay.
1348 * @retval kStatus_MCG_ModeUnreachable Could not switch to the target mode.
1349 * @retval kStatus_Success Switched to the target mode successfully.
1350 * @note If @p dmx32 is set to kMCG_Dmx32Fine, the slow IRC must not be trimmed
1351 * to frequency above 32768 Hz.
1352 */
1353 status_t CLOCK_SetFbiMode(mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDelay)(void));
1354
1355 /*!
1356 * @brief Sets the MCG to FBE mode.
1357 *
1358 * This function sets the MCG to FBE mode. If setting to FBE mode fails
1359 * from the current mode, this function returns an error.
1360 *
1361 * @param frdiv FLL reference clock divider setting, FRDIV.
1362 * @param dmx32 DMX32 in FBE mode.
1363 * @param drs The DCO range selection.
1364 * @param fllStableDelay Delay function to make sure FLL is stable. If the FLL
1365 * is not used in FBE mode, this parameter can be NULL. Passing NULL
1366 * does not cause a delay.
1367 * @retval kStatus_MCG_ModeUnreachable Could not switch to the target mode.
1368 * @retval kStatus_Success Switched to the target mode successfully.
1369 */
1370 status_t CLOCK_SetFbeMode(uint8_t frdiv, mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDelay)(void));
1371
1372 /*!
1373 * @brief Sets the MCG to BLPI mode.
1374 *
1375 * This function sets the MCG to BLPI mode. If setting to BLPI mode fails
1376 * from the current mode, this function returns an error.
1377 *
1378 * @retval kStatus_MCG_ModeUnreachable Could not switch to the target mode.
1379 * @retval kStatus_Success Switched to the target mode successfully.
1380 */
1381 status_t CLOCK_SetBlpiMode(void);
1382
1383 /*!
1384 * @brief Sets the MCG to BLPE mode.
1385 *
1386 * This function sets the MCG to BLPE mode. If setting to BLPE mode fails
1387 * from the current mode, this function returns an error.
1388 *
1389 * @retval kStatus_MCG_ModeUnreachable Could not switch to the target mode.
1390 * @retval kStatus_Success Switched to the target mode successfully.
1391 */
1392 status_t CLOCK_SetBlpeMode(void);
1393
1394 /*!
1395 * @brief Sets the MCG to PBE mode.
1396 *
1397 * This function sets the MCG to PBE mode. If setting to PBE mode fails
1398 * from the current mode, this function returns an error.
1399 *
1400 * @param pllcs The PLL selection, PLLCS.
1401 * @param config Pointer to the PLL configuration.
1402 * @retval kStatus_MCG_ModeUnreachable Could not switch to the target mode.
1403 * @retval kStatus_Success Switched to the target mode successfully.
1404 *
1405 * @note
1406 * 1. The parameter \c pllcs selects the PLL. For platforms with
1407 * only one PLL, the parameter pllcs is kept for interface compatibility.
1408 * 2. The parameter \c config is the PLL configuration structure. On some
1409 * platforms, it is possible to choose the external PLL directly, which renders the
1410 * configuration structure not necessary. In this case, pass in NULL.
1411 * For example: CLOCK_SetPbeMode(kMCG_OscselOsc, kMCG_PllClkSelExtPll, NULL);
1412 */
1413 status_t CLOCK_SetPbeMode(mcg_pll_clk_select_t pllcs, mcg_pll_config_t const *config);
1414
1415 /*!
1416 * @brief Sets the MCG to PEE mode.
1417 *
1418 * This function sets the MCG to PEE mode.
1419 *
1420 * @retval kStatus_MCG_ModeUnreachable Could not switch to the target mode.
1421 * @retval kStatus_Success Switched to the target mode successfully.
1422 *
1423 * @note This function only changes the CLKS to use the PLL/FLL output. If the
1424 * PRDIV/VDIV are different than in the PBE mode, set them up
1425 * in PBE mode and wait. When the clock is stable, switch to PEE mode.
1426 */
1427 status_t CLOCK_SetPeeMode(void);
1428
1429 /*!
1430 * @brief Switches the MCG to FBE mode from the external mode.
1431 *
1432 * This function switches the MCG from external modes (PEE/PBE/BLPE/FEE) to the FBE mode quickly.
1433 * The external clock is used as the system clock source and PLL is disabled. However,
1434 * the FLL settings are not configured. This is a lite function with a small code size, which is useful
1435 * during the mode switch. For example, to switch from PEE mode to FEI mode:
1436 *
1437 * @code
1438 * CLOCK_ExternalModeToFbeModeQuick();
1439 * CLOCK_SetFeiMode(...);
1440 * @endcode
1441 *
1442 * @retval kStatus_Success Switched successfully.
1443 * @retval kStatus_MCG_ModeInvalid If the current mode is not an external mode, do not call this function.
1444 */
1445 status_t CLOCK_ExternalModeToFbeModeQuick(void);
1446
1447 /*!
1448 * @brief Switches the MCG to FBI mode from internal modes.
1449 *
1450 * This function switches the MCG from internal modes (PEI/PBI/BLPI/FEI) to the FBI mode quickly.
1451 * The MCGIRCLK is used as the system clock source and PLL is disabled. However,
1452 * FLL settings are not configured. This is a lite function with a small code size, which is useful
1453 * during the mode switch. For example, to switch from PEI mode to FEE mode:
1454 *
1455 * @code
1456 * CLOCK_InternalModeToFbiModeQuick();
1457 * CLOCK_SetFeeMode(...);
1458 * @endcode
1459 *
1460 * @retval kStatus_Success Switched successfully.
1461 * @retval kStatus_MCG_ModeInvalid If the current mode is not an internal mode, do not call this function.
1462 */
1463 status_t CLOCK_InternalModeToFbiModeQuick(void);
1464
1465 /*!
1466 * @brief Sets the MCG to FEI mode during system boot up.
1467 *
1468 * This function sets the MCG to FEI mode from the reset mode. It can also be used to
1469 * set up MCG during system boot up.
1470 *
1471 * @param dmx32 DMX32 in FEI mode.
1472 * @param drs The DCO range selection.
1473 * @param fllStableDelay Delay function to ensure that the FLL is stable.
1474 *
1475 * @retval kStatus_MCG_ModeUnreachable Could not switch to the target mode.
1476 * @retval kStatus_Success Switched to the target mode successfully.
1477 * @note If @p dmx32 is set to kMCG_Dmx32Fine, the slow IRC must not be trimmed
1478 * to frequency above 32768 Hz.
1479 */
1480 status_t CLOCK_BootToFeiMode(mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDelay)(void));
1481
1482 /*!
1483 * @brief Sets the MCG to FEE mode during system bootup.
1484 *
1485 * This function sets MCG to FEE mode from the reset mode. It can also be used to
1486 * set up the MCG during system boot up.
1487 *
1488 * @param oscsel OSC clock select, OSCSEL.
1489 * @param frdiv FLL reference clock divider setting, FRDIV.
1490 * @param dmx32 DMX32 in FEE mode.
1491 * @param drs The DCO range selection.
1492 * @param fllStableDelay Delay function to ensure that the FLL is stable.
1493 *
1494 * @retval kStatus_MCG_ModeUnreachable Could not switch to the target mode.
1495 * @retval kStatus_Success Switched to the target mode successfully.
1496 */
1497 status_t CLOCK_BootToFeeMode(
1498 mcg_oscsel_t oscsel, uint8_t frdiv, mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDelay)(void));
1499
1500 /*!
1501 * @brief Sets the MCG to BLPI mode during system boot up.
1502 *
1503 * This function sets the MCG to BLPI mode from the reset mode. It can also be used to
1504 * set up the MCG during system boot up.
1505 *
1506 * @param fcrdiv Fast IRC divider, FCRDIV.
1507 * @param ircs The internal reference clock to select, IRCS.
1508 * @param ircEnableMode The MCGIRCLK enable mode, OR'ed value of the enumeration _mcg_irclk_enable_mode.
1509 *
1510 * @retval kStatus_MCG_SourceUsed Could not change MCGIRCLK setting.
1511 * @retval kStatus_Success Switched to the target mode successfully.
1512 */
1513 status_t CLOCK_BootToBlpiMode(uint8_t fcrdiv, mcg_irc_mode_t ircs, uint8_t ircEnableMode);
1514
1515 /*!
1516 * @brief Sets the MCG to BLPE mode during system boot up.
1517 *
1518 * This function sets the MCG to BLPE mode from the reset mode. It can also be used to
1519 * set up the MCG during system boot up.
1520 *
1521 * @param oscsel OSC clock select, MCG_C7[OSCSEL].
1522 *
1523 * @retval kStatus_MCG_ModeUnreachable Could not switch to the target mode.
1524 * @retval kStatus_Success Switched to the target mode successfully.
1525 */
1526 status_t CLOCK_BootToBlpeMode(mcg_oscsel_t oscsel);
1527
1528 /*!
1529 * @brief Sets the MCG to PEE mode during system boot up.
1530 *
1531 * This function sets the MCG to PEE mode from reset mode. It can also be used to
1532 * set up the MCG during system boot up.
1533 *
1534 * @param oscsel OSC clock select, MCG_C7[OSCSEL].
1535 * @param pllcs The PLL selection, PLLCS.
1536 * @param config Pointer to the PLL configuration.
1537 *
1538 * @retval kStatus_MCG_ModeUnreachable Could not switch to the target mode.
1539 * @retval kStatus_Success Switched to the target mode successfully.
1540 */
1541 status_t CLOCK_BootToPeeMode(mcg_oscsel_t oscsel, mcg_pll_clk_select_t pllcs, mcg_pll_config_t const *config);
1542
1543 /*!
1544 * @brief Sets the MCG to a target mode.
1545 *
1546 * This function sets MCG to a target mode defined by the configuration
1547 * structure. If switching to the target mode fails, this function
1548 * chooses the correct path.
1549 *
1550 * @param config Pointer to the target MCG mode configuration structure.
1551 * @return Return kStatus_Success if switched successfully; Otherwise, it returns an error code _mcg_status.
1552 *
1553 * @note If the external clock is used in the target mode, ensure that it is
1554 * enabled. For example, if the OSC0 is used, set up OSC0 correctly before calling this
1555 * function.
1556 */
1557 status_t CLOCK_SetMcgConfig(mcg_config_t const *config);
1558
1559 /*@}*/
1560
1561 #if defined(__cplusplus)
1562 }
1563 #endif /* __cplusplus */
1564
1565 /*! @} */
1566
1567 #endif /* _FSL_CLOCK_H_ */
1568
