1 /*
2 * Copyright (c) 2015, Freescale Semiconductor, Inc.
3 * Copyright 2016 - 2020, NXP
4 * All rights reserved.
5 *
6 * SPDX-License-Identifier: BSD-3-Clause
7 */
8
9 #ifndef _FSL_CLOCK_H_
10 #define _FSL_CLOCK_H_
11
12 #include "fsl_common.h"
13
14 /*! @addtogroup clock */
15 /*! @{ */
16
17 /*! @file */
18
19 /*******************************************************************************
20 * Configurations
21 ******************************************************************************/
22
23 /*! @brief Configures whether to check a parameter in a function.
24 *
25 * Some MCG settings must be changed with conditions, for example:
26 * 1. MCGIRCLK settings, such as the source, divider, and the trim value should not change when
27 * MCGIRCLK is used as a system clock source.
28 * 2. MCG_C7[OSCSEL] should not be changed when the external reference clock is used
29 * as a system clock source. For example, in FBE/BLPE/PBE modes.
30 * 3. The users should only switch between the supported clock modes.
31 *
32 * MCG functions check the parameter and MCG status before setting, if not allowed
33 * to change, the functions return error. The parameter checking increases code size,
34 * if code size is a critical requirement, change #MCG_CONFIG_CHECK_PARAM to 0 to
35 * disable parameter checking.
36 */
37 #ifndef MCG_CONFIG_CHECK_PARAM
38 #define MCG_CONFIG_CHECK_PARAM 0U
39 #endif
40
41 /*! @brief Configure whether driver controls clock
42 *
43 * When set to 0, peripheral drivers will enable clock in initialize function
44 * and disable clock in de-initialize function. When set to 1, peripheral
45 * driver will not control the clock, application could control the clock out of
46 * the driver.
47 *
48 * @note All drivers share this feature switcher. If it is set to 1, application
49 * should handle clock enable and disable for all drivers.
50 */
51 #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL))
52 #define FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL 0
53 #endif
54
55 /*******************************************************************************
56 * Definitions
57 ******************************************************************************/
58
59 /*! @name Driver version */
60 /*@{*/
61 /*! @brief CLOCK driver version 2.5.1. */
62 #define FSL_CLOCK_DRIVER_VERSION (MAKE_VERSION(2, 5, 1))
63 /*@}*/
64
65 /*! @brief External XTAL0 (OSC0) clock frequency.
66 *
67 * The XTAL0/EXTAL0 (OSC0) clock frequency in Hz. When the clock is set up, use the
68 * function CLOCK_SetXtal0Freq to set the value in the clock driver. For example,
69 * if XTAL0 is 8 MHz:
70 * @code
71 * Set up the OSC0
72 * CLOCK_InitOsc0(...);
73 * Set the XTAL0 value to the clock driver.
74 * CLOCK_SetXtal0Freq(80000000);
75 * @endcode
76 *
77 * This is important for the multicore platforms where only one core needs to set up the
78 * OSC0 using the CLOCK_InitOsc0. All other cores need to call the CLOCK_SetXtal0Freq
79 * to get a valid clock frequency.
80 */
81 extern volatile uint32_t g_xtal0Freq;
82
83 /*! @brief External XTAL32/EXTAL32/RTC_CLKIN clock frequency.
84 *
85 * The XTAL32/EXTAL32/RTC_CLKIN clock frequency in Hz. When the clock is set up, use the
86 * function CLOCK_SetXtal32Freq to set the value in the clock driver.
87 *
88 * This is important for the multicore platforms where only one core needs to set up
89 * the clock. All other cores need to call the CLOCK_SetXtal32Freq
90 * to get a valid clock frequency.
91 */
92 extern volatile uint32_t g_xtal32Freq;
93
94 #if (defined(OSC) && !(defined(OSC0)))
95 #define OSC0 OSC
96 #endif
97
98 /* Definition for delay API in clock driver, users can redefine it to the real application. */
99 #ifndef SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY
100 #define SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY (240000000UL)
101 #endif
102
103 /*! @brief Clock ip name array for DMAMUX. */
104 #define DMAMUX_CLOCKS \
105 { \
106 kCLOCK_Dmamux0 \
107 }
108
109 /*! @brief Clock ip name array for HSADC. */
110 #define HSADC_CLOCKS \
111 { \
112 kCLOCK_Hsadc0, kCLOCK_Hsadc1 \
113 }
114
115 /*! @brief Clock ip name array for ENET. */
116 #define ENET_CLOCKS \
117 { \
118 kCLOCK_Enet0 \
119 }
120
121 /*! @brief Clock ip name array for PORT. */
122 #define PORT_CLOCKS \
123 { \
124 kCLOCK_PortA, kCLOCK_PortB, kCLOCK_PortC, kCLOCK_PortD, kCLOCK_PortE \
125 }
126
127 /*! @brief Clock ip name array for FLEXBUS. */
128 #define FLEXBUS_CLOCKS \
129 { \
130 kCLOCK_Flexbus0 \
131 }
132
133 /*! @brief Clock ip name array for ENC. */
134 #define ENC_CLOCKS \
135 { \
136 kCLOCK_Enc0 \
137 }
138
139 /*! @brief Clock ip name array for EWM. */
140 #define EWM_CLOCKS \
141 { \
142 kCLOCK_Ewm0 \
143 }
144
145 /*! @brief Clock ip name array for PIT. */
146 #define PIT_CLOCKS \
147 { \
148 kCLOCK_Pit0 \
149 }
150
151 /*! @brief Clock ip name array for DSPI. */
152 #define DSPI_CLOCKS \
153 { \
154 kCLOCK_Spi0, kCLOCK_Spi1, kCLOCK_Spi2 \
155 }
156
157 /*! @brief Clock ip name array for LPTMR. */
158 #define LPTMR_CLOCKS \
159 { \
160 kCLOCK_Lptmr0 \
161 }
162
163 /*! @brief Clock ip name array for FTM. */
164 #define FTM_CLOCKS \
165 { \
166 kCLOCK_Ftm0, kCLOCK_Ftm1, kCLOCK_Ftm2, kCLOCK_Ftm3 \
167 }
168
169 /*! @brief Clock ip name array for EDMA. */
170 #define EDMA_CLOCKS \
171 { \
172 kCLOCK_Dma0 \
173 }
174
175 /*! @brief Clock ip name array for FLEXCAN. */
176 #define FLEXCAN_CLOCKS \
177 { \
178 kCLOCK_Flexcan0, kCLOCK_Flexcan1, kCLOCK_Flexcan2 \
179 }
180
181 /*! @brief Clock ip name array for DAC. */
182 #define DAC_CLOCKS \
183 { \
184 kCLOCK_Dac0 \
185 }
186
187 /*! @brief Clock ip name array for ADC16. */
188 #define ADC16_CLOCKS \
189 { \
190 kCLOCK_Adc0 \
191 }
192
193 /*! @brief Clock ip name array for XBARA. */
194 #define XBARA_CLOCKS \
195 { \
196 kCLOCK_XbarA \
197 }
198
199 /*! @brief Clock ip name array for XBARB. */
200 #define XBARB_CLOCKS \
201 { \
202 kCLOCK_XbarB \
203 }
204
205 /*! @brief Clock ip name array for AOI. */
206 #define AOI_CLOCKS \
207 { \
208 kCLOCK_Aoi0 \
209 }
210
211 /*! @brief Clock ip name array for TRNG. */
212 #define TRNG_CLOCKS \
213 { \
214 kCLOCK_Trng0 \
215 }
216
217 /*! @brief Clock ip name array for MPU. */
218 #define SYSMPU_CLOCKS \
219 { \
220 kCLOCK_Sysmpu0 \
221 }
222
223 /*! @brief Clock ip name array for PWM. */
224 #define PWM_CLOCKS \
225 { \
226 {kCLOCK_Pwm0_Sm0, kCLOCK_Pwm0_Sm1, kCLOCK_Pwm0_Sm2, kCLOCK_Pwm0_Sm3}, \
227 { \
228 kCLOCK_Pwm1_Sm0, kCLOCK_Pwm1_Sm1, kCLOCK_Pwm1_Sm2, kCLOCK_Pwm1_Sm3 \
229 } \
230 }
231
232 /*! @brief Clock ip name array for UART. */
233 #define UART_CLOCKS \
234 { \
235 kCLOCK_Uart0, kCLOCK_Uart1, kCLOCK_Uart2, kCLOCK_Uart3, kCLOCK_Uart4, kCLOCK_Uart5 \
236 }
237
238 /*! @brief Clock ip name array for CRC. */
239 #define CRC_CLOCKS \
240 { \
241 kCLOCK_Crc0 \
242 }
243
244 /*! @brief Clock ip name array for I2C. */
245 #define I2C_CLOCKS \
246 { \
247 kCLOCK_I2c0, kCLOCK_I2c1 \
248 }
249
250 /*! @brief Clock ip name array for PDB. */
251 #define PDB_CLOCKS \
252 { \
253 kCLOCK_Pdb0, kCLOCK_Pdb1 \
254 }
255
256 /*! @brief Clock ip name array for CMP. */
257 #define CMP_CLOCKS \
258 { \
259 kCLOCK_Cmp0, kCLOCK_Cmp1, kCLOCK_Cmp2, kCLOCK_Cmp3 \
260 }
261
262 /*! @brief Clock ip name array for FTF. */
263 #define FTF_CLOCKS \
264 { \
265 kCLOCK_Ftf0 \
266 }
267
268 /*!
269 * @brief LPO clock frequency.
270 */
271 #define LPO_CLK_FREQ 1000U
272
273 /*! @brief Peripherals clock source definition. */
274 #define SYS_CLK kCLOCK_CoreSysClk
275 #define BUS_CLK kCLOCK_BusClk
276 #define FAST_CLK kCLOCK_FastPeriphClk
277
278 #define I2C0_CLK_SRC BUS_CLK
279 #define I2C1_CLK_SRC BUS_CLK
280 #define DSPI0_CLK_SRC FAST_CLK
281 #define DSPI1_CLK_SRC FAST_CLK
282 #define DSPI2_CLK_SRC FAST_CLK
283 #define UART0_CLK_SRC FAST_CLK
284 #define UART1_CLK_SRC FAST_CLK
285 #define UART2_CLK_SRC FAST_CLK
286 #define UART3_CLK_SRC FAST_CLK
287 #define UART4_CLK_SRC FAST_CLK
288 #define UART5_CLK_SRC FAST_CLK
289
290 /*! @brief Clock name used to get clock frequency. */
291 typedef enum _clock_name
292 {
293
294 /* ----------------------------- System layer clock -------------------------------*/
295 kCLOCK_CoreSysClk, /*!< Core/system clock */
296 kCLOCK_PlatClk, /*!< Platform clock */
297 kCLOCK_BusClk, /*!< Bus clock */
298 kCLOCK_FlexBusClk, /*!< FlexBus clock */
299 kCLOCK_FlashClk, /*!< Flash clock */
300 kCLOCK_FastPeriphClk, /*!< Fast peripheral clock */
301 kCLOCK_PllFllSelClk, /*!< The clock after SIM[PLLFLLSEL]. */
302
303 /* ---------------------------------- OSC clock -----------------------------------*/
304 kCLOCK_Er32kClk, /*!< External reference 32K clock (ERCLK32K) */
305 kCLOCK_Osc0ErClk, /*!< OSC0 external reference clock (OSC0ERCLK) */
306 kCLOCK_Osc1ErClk, /*!< OSC1 external reference clock (OSC1ERCLK) */
307 kCLOCK_Osc0ErClkUndiv, /*!< OSC0 external reference undivided clock(OSC0ERCLK_UNDIV). */
308
309 /* ----------------------------- MCG and MCG-Lite clock ---------------------------*/
310 kCLOCK_McgFixedFreqClk, /*!< MCG fixed frequency clock (MCGFFCLK) */
311 kCLOCK_McgInternalRefClk, /*!< MCG internal reference clock (MCGIRCLK) */
312 kCLOCK_McgFllClk, /*!< MCGFLLCLK */
313 kCLOCK_McgPll0Clk, /*!< MCGPLL0CLK */
314 kCLOCK_McgPll1Clk, /*!< MCGPLL1CLK */
315 kCLOCK_McgExtPllClk, /*!< EXT_PLLCLK */
316 kCLOCK_McgPeriphClk, /*!< MCG peripheral clock (MCGPCLK) */
317 kCLOCK_McgIrc48MClk, /*!< MCG IRC48M clock */
318
319 /* --------------------------------- Other clock ----------------------------------*/
320 kCLOCK_LpoClk, /*!< LPO clock */
321
322 } clock_name_t;
323
324 /*------------------------------------------------------------------------------
325
326 clock_gate_t definition:
327
328 31 16 0
329 -----------------------------------------------------------------
330 | SIM_SCGC register offset | control bit offset in SCGC |
331 -----------------------------------------------------------------
332
333 For example, the SDHC clock gate is controlled by SIM_SCGC3[17], the
334 SIM_SCGC3 offset in SIM is 0x1030, then kClockGateSdhc0 is defined as
335
336 kClockGateSdhc0 = (0x1030 << 16) | 17;
337
338 ------------------------------------------------------------------------------*/
339
340 #define CLK_GATE_REG_OFFSET_SHIFT 16U
341 #define CLK_GATE_REG_OFFSET_MASK 0xFFFF0000U
342 #define CLK_GATE_BIT_SHIFT_SHIFT 0U
343 #define CLK_GATE_BIT_SHIFT_MASK 0x0000FFFFU
344
345 #define CLK_GATE_DEFINE(reg_offset, bit_shift) \
346 ((((reg_offset) << CLK_GATE_REG_OFFSET_SHIFT) & CLK_GATE_REG_OFFSET_MASK) | \
347 (((bit_shift) << CLK_GATE_BIT_SHIFT_SHIFT) & CLK_GATE_BIT_SHIFT_MASK))
348
349 #define CLK_GATE_ABSTRACT_REG_OFFSET(x) (((x)&CLK_GATE_REG_OFFSET_MASK) >> CLK_GATE_REG_OFFSET_SHIFT)
350 #define CLK_GATE_ABSTRACT_BITS_SHIFT(x) (((x)&CLK_GATE_BIT_SHIFT_MASK) >> CLK_GATE_BIT_SHIFT_SHIFT)
351
352 /*! @brief Clock gate name used for CLOCK_EnableClock/CLOCK_DisableClock. */
353 typedef enum _clock_ip_name
354 {
355 kCLOCK_IpInvalid = 0U,
356 kCLOCK_Uart4 = CLK_GATE_DEFINE(0x1028U, 10U),
357 kCLOCK_Uart5 = CLK_GATE_DEFINE(0x1028U, 11U),
358 kCLOCK_Pwm1_Sm0 = CLK_GATE_DEFINE(0x1028U, 24U),
359 kCLOCK_Pwm1_Sm1 = CLK_GATE_DEFINE(0x1028U, 25U),
360 kCLOCK_Pwm1_Sm2 = CLK_GATE_DEFINE(0x1028U, 26U),
361 kCLOCK_Pwm1_Sm3 = CLK_GATE_DEFINE(0x1028U, 27U),
362
363 kCLOCK_Enet0 = CLK_GATE_DEFINE(0x102CU, 0U),
364 kCLOCK_Hsadc1 = CLK_GATE_DEFINE(0x102CU, 28U),
365
366 kCLOCK_Trng0 = CLK_GATE_DEFINE(0x1030U, 0U),
367 kCLOCK_Flexcan2 = CLK_GATE_DEFINE(0x1030U, 4U),
368 kCLOCK_Spi2 = CLK_GATE_DEFINE(0x1030U, 12U),
369
370 kCLOCK_Ewm0 = CLK_GATE_DEFINE(0x1034U, 1U),
371 kCLOCK_I2c0 = CLK_GATE_DEFINE(0x1034U, 6U),
372 kCLOCK_I2c1 = CLK_GATE_DEFINE(0x1034U, 7U),
373 kCLOCK_Uart0 = CLK_GATE_DEFINE(0x1034U, 10U),
374 kCLOCK_Uart1 = CLK_GATE_DEFINE(0x1034U, 11U),
375 kCLOCK_Uart2 = CLK_GATE_DEFINE(0x1034U, 12U),
376 kCLOCK_Uart3 = CLK_GATE_DEFINE(0x1034U, 13U),
377 kCLOCK_Cmp0 = CLK_GATE_DEFINE(0x1034U, 19U),
378 kCLOCK_Cmp1 = CLK_GATE_DEFINE(0x1034U, 19U),
379 kCLOCK_Cmp2 = CLK_GATE_DEFINE(0x1034U, 19U),
380 kCLOCK_Cmp3 = CLK_GATE_DEFINE(0x1034U, 19U),
381 kCLOCK_Pwm0_Sm0 = CLK_GATE_DEFINE(0x1034U, 24U),
382 kCLOCK_Pwm0_Sm1 = CLK_GATE_DEFINE(0x1034U, 25U),
383 kCLOCK_Pwm0_Sm2 = CLK_GATE_DEFINE(0x1034U, 26U),
384 kCLOCK_Pwm0_Sm3 = CLK_GATE_DEFINE(0x1034U, 27U),
385
386 kCLOCK_Lptmr0 = CLK_GATE_DEFINE(0x1038U, 0U),
387 kCLOCK_PortA = CLK_GATE_DEFINE(0x1038U, 9U),
388 kCLOCK_PortB = CLK_GATE_DEFINE(0x1038U, 10U),
389 kCLOCK_PortC = CLK_GATE_DEFINE(0x1038U, 11U),
390 kCLOCK_PortD = CLK_GATE_DEFINE(0x1038U, 12U),
391 kCLOCK_PortE = CLK_GATE_DEFINE(0x1038U, 13U),
392 kCLOCK_Enc0 = CLK_GATE_DEFINE(0x1038U, 21U),
393 kCLOCK_XbarA = CLK_GATE_DEFINE(0x1038U, 25U),
394 kCLOCK_XbarB = CLK_GATE_DEFINE(0x1038U, 26U),
395 kCLOCK_Aoi0 = CLK_GATE_DEFINE(0x1038U, 27U),
396 kCLOCK_Hsadc0 = CLK_GATE_DEFINE(0x1038U, 28U),
397
398 kCLOCK_Ftf0 = CLK_GATE_DEFINE(0x103CU, 0U),
399 kCLOCK_Dmamux0 = CLK_GATE_DEFINE(0x103CU, 1U),
400 kCLOCK_Flexcan0 = CLK_GATE_DEFINE(0x103CU, 4U),
401 kCLOCK_Flexcan1 = CLK_GATE_DEFINE(0x103CU, 5U),
402 kCLOCK_Ftm3 = CLK_GATE_DEFINE(0x103CU, 6U),
403 kCLOCK_Spi0 = CLK_GATE_DEFINE(0x103CU, 12U),
404 kCLOCK_Spi1 = CLK_GATE_DEFINE(0x103CU, 13U),
405 kCLOCK_Pdb1 = CLK_GATE_DEFINE(0x103CU, 17U),
406 kCLOCK_Crc0 = CLK_GATE_DEFINE(0x103CU, 18U),
407 kCLOCK_Pdb0 = CLK_GATE_DEFINE(0x103CU, 22U),
408 kCLOCK_Pit0 = CLK_GATE_DEFINE(0x103CU, 23U),
409 kCLOCK_Ftm0 = CLK_GATE_DEFINE(0x103CU, 24U),
410 kCLOCK_Ftm1 = CLK_GATE_DEFINE(0x103CU, 25U),
411 kCLOCK_Ftm2 = CLK_GATE_DEFINE(0x103CU, 26U),
412 kCLOCK_Adc0 = CLK_GATE_DEFINE(0x103CU, 27U),
413 kCLOCK_Dac0 = CLK_GATE_DEFINE(0x103CU, 31U),
414
415 kCLOCK_Flexbus0 = CLK_GATE_DEFINE(0x1040U, 0U),
416 kCLOCK_Sysmpu0 = CLK_GATE_DEFINE(0x1040U, 2U),
417 kCLOCK_Dma0 = CLK_GATE_DEFINE(0x1040U, 8U),
418 } clock_ip_name_t;
419
420 /*!@brief SIM configuration structure for clock setting. */
421 typedef struct _sim_clock_config
422 {
423 uint8_t pllFllSel; /*!< PLL/FLL/IRC48M selection. */
424 uint8_t er32kSrc; /*!< ERCLK32K source selection. */
425 uint32_t clkdiv1; /*!< SIM_CLKDIV1. */
426 } sim_clock_config_t;
427
428 /*! @brief OSC work mode. */
429 typedef enum _osc_mode
430 {
431 kOSC_ModeExt = 0U, /*!< Use an external clock. */
432 #if (defined(MCG_C2_EREFS_MASK) && !(defined(MCG_C2_EREFS0_MASK)))
433 kOSC_ModeOscLowPower = MCG_C2_EREFS_MASK, /*!< Oscillator low power. */
434 #else
435 kOSC_ModeOscLowPower = MCG_C2_EREFS0_MASK, /*!< Oscillator low power. */
436 #endif
437 kOSC_ModeOscHighGain = 0U
438 #if (defined(MCG_C2_EREFS_MASK) && !(defined(MCG_C2_EREFS0_MASK)))
439 | MCG_C2_EREFS_MASK
440 #else
441 | MCG_C2_EREFS0_MASK
442 #endif
443 #if (defined(MCG_C2_HGO_MASK) && !(defined(MCG_C2_HGO0_MASK)))
444 | MCG_C2_HGO_MASK, /*!< Oscillator high gain. */
445 #else
446 | MCG_C2_HGO0_MASK, /*!< Oscillator high gain. */
447 #endif
448 } osc_mode_t;
449
450 /*! @brief Oscillator capacitor load setting.*/
451 enum _osc_cap_load
452 {
453 kOSC_Cap2P = OSC_CR_SC2P_MASK, /*!< 2 pF capacitor load */
454 kOSC_Cap4P = OSC_CR_SC4P_MASK, /*!< 4 pF capacitor load */
455 kOSC_Cap8P = OSC_CR_SC8P_MASK, /*!< 8 pF capacitor load */
456 kOSC_Cap16P = OSC_CR_SC16P_MASK /*!< 16 pF capacitor load */
457 };
458
459 /*! @brief OSCERCLK enable mode. */
460 enum _oscer_enable_mode
461 {
462 kOSC_ErClkEnable = OSC_CR_ERCLKEN_MASK, /*!< Enable. */
463 kOSC_ErClkEnableInStop = OSC_CR_EREFSTEN_MASK /*!< Enable in stop mode. */
464 };
465
466 /*! @brief OSC configuration for OSCERCLK. */
467 typedef struct _oscer_config
468 {
469 uint8_t enableMode; /*!< OSCERCLK enable mode. OR'ed value of @ref _oscer_enable_mode. */
470
471 uint8_t erclkDiv; /*!< Divider for OSCERCLK.*/
472 } oscer_config_t;
473
474 /*!
475 * @brief OSC Initialization Configuration Structure
476 *
477 * Defines the configuration data structure to initialize the OSC.
478 * When porting to a new board, set the following members
479 * according to the board setting:
480 * 1. freq: The external frequency.
481 * 2. workMode: The OSC module mode.
482 */
483 typedef struct _osc_config
484 {
485 uint32_t freq; /*!< External clock frequency. */
486 uint8_t capLoad; /*!< Capacitor load setting. */
487 osc_mode_t workMode; /*!< OSC work mode setting. */
488 oscer_config_t oscerConfig; /*!< Configuration for OSCERCLK. */
489 } osc_config_t;
490
491 /*! @brief MCG FLL reference clock source select. */
492 typedef enum _mcg_fll_src
493 {
494 kMCG_FllSrcExternal, /*!< External reference clock is selected */
495 kMCG_FllSrcInternal /*!< The slow internal reference clock is selected */
496 } mcg_fll_src_t;
497
498 /*! @brief MCG internal reference clock select */
499 typedef enum _mcg_irc_mode
500 {
501 kMCG_IrcSlow, /*!< Slow internal reference clock selected */
502 kMCG_IrcFast /*!< Fast internal reference clock selected */
503 } mcg_irc_mode_t;
504
505 /*! @brief MCG DCO Maximum Frequency with 32.768 kHz Reference */
506 typedef enum _mcg_dmx32
507 {
508 kMCG_Dmx32Default, /*!< DCO has a default range of 25% */
509 kMCG_Dmx32Fine /*!< DCO is fine-tuned for maximum frequency with 32.768 kHz reference */
510 } mcg_dmx32_t;
511
512 /*! @brief MCG DCO range select */
513 typedef enum _mcg_drs
514 {
515 kMCG_DrsLow, /*!< Low frequency range */
516 kMCG_DrsMid, /*!< Mid frequency range */
517 kMCG_DrsMidHigh, /*!< Mid-High frequency range */
518 kMCG_DrsHigh /*!< High frequency range */
519 } mcg_drs_t;
520
521 /*! @brief MCG PLL reference clock select */
522 typedef enum _mcg_pll_ref_src
523 {
524 kMCG_PllRefOsc0, /*!< Selects OSC0 as PLL reference clock */
525 kMCG_PllRefOsc1 /*!< Selects OSC1 as PLL reference clock */
526 } mcg_pll_ref_src_t;
527
528 /*! @brief MCGOUT clock source. */
529 typedef enum _mcg_clkout_src
530 {
531 kMCG_ClkOutSrcOut, /*!< Output of the FLL is selected (reset default) */
532 kMCG_ClkOutSrcInternal, /*!< Internal reference clock is selected */
533 kMCG_ClkOutSrcExternal, /*!< External reference clock is selected */
534 } mcg_clkout_src_t;
535
536 /*! @brief MCG Automatic Trim Machine Select */
537 typedef enum _mcg_atm_select
538 {
539 kMCG_AtmSel32k, /*!< 32 kHz Internal Reference Clock selected */
540 kMCG_AtmSel4m /*!< 4 MHz Internal Reference Clock selected */
541 } mcg_atm_select_t;
542
543 /*! @brief MCG OSC Clock Select */
544 typedef enum _mcg_oscsel
545 {
546 kMCG_OscselOsc, /*!< Selects System Oscillator (OSCCLK) */
547 kMCG_OscselRtc, /*!< Selects 32 kHz RTC Oscillator */
548 } mcg_oscsel_t;
549
550 /*! @brief MCG PLLCS select */
551 typedef enum _mcg_pll_clk_select
552 {
553 kMCG_PllClkSelPll0, /*!< PLL0 output clock is selected */
554 kMCG_PllClkSelPll1 /* PLL1 output clock is selected */
555 } mcg_pll_clk_select_t;
556
557 /*! @brief MCG clock monitor mode. */
558 typedef enum _mcg_monitor_mode
559 {
560 kMCG_MonitorNone, /*!< Clock monitor is disabled. */
561 kMCG_MonitorInt, /*!< Trigger interrupt when clock lost. */
562 kMCG_MonitorReset /*!< System reset when clock lost. */
563 } mcg_monitor_mode_t;
564
565 /*! @brief MCG status. Enumeration _mcg_status */
566 enum
567 {
568 kStatus_MCG_ModeUnreachable = MAKE_STATUS(kStatusGroup_MCG, 0U), /*!< Can't switch to target mode. */
569 kStatus_MCG_ModeInvalid = MAKE_STATUS(kStatusGroup_MCG, 1U), /*!< Current mode invalid for the specific
570 function. */
571 kStatus_MCG_AtmBusClockInvalid = MAKE_STATUS(kStatusGroup_MCG, 2U), /*!< Invalid bus clock for ATM. */
572 kStatus_MCG_AtmDesiredFreqInvalid = MAKE_STATUS(kStatusGroup_MCG, 3U), /*!< Invalid desired frequency for ATM. */
573 kStatus_MCG_AtmIrcUsed = MAKE_STATUS(kStatusGroup_MCG, 4U), /*!< IRC is used when using ATM. */
574 kStatus_MCG_AtmHardwareFail = MAKE_STATUS(kStatusGroup_MCG, 5U), /*!< Hardware fail occurs during ATM. */
575 kStatus_MCG_SourceUsed = MAKE_STATUS(kStatusGroup_MCG, 6U) /*!< Can't change the clock source because
576 it is in use. */
577 };
578
579 /*! @brief MCG status flags. Enumeration _mcg_status_flags_t */
580 enum
581 {
582 kMCG_Osc0LostFlag = (1U << 0U), /*!< OSC0 lost. */
583 kMCG_Osc0InitFlag = (1U << 1U), /*!< OSC0 crystal initialized. */
584 kMCG_Pll0LostFlag = (1U << 5U), /*!< PLL0 lost. */
585 kMCG_Pll0LockFlag = (1U << 6U), /*!< PLL0 locked. */
586 };
587
588 /*! @brief MCG internal reference clock (MCGIRCLK) enable mode definition. Enumeration _mcg_irclk_enable_mode */
589 enum
590 {
591 kMCG_IrclkEnable = MCG_C1_IRCLKEN_MASK, /*!< MCGIRCLK enable. */
592 kMCG_IrclkEnableInStop = MCG_C1_IREFSTEN_MASK /*!< MCGIRCLK enable in stop mode. */
593 };
594
595 /*! @brief MCG PLL clock enable mode definition. Enumeration _mcg_pll_enable_mode */
596 enum
597 {
598 kMCG_PllEnableIndependent = MCG_C5_PLLCLKEN0_MASK, /*!< MCGPLLCLK enable independent of the
599 MCG clock mode. Generally, the PLL
600 is disabled in FLL modes
601 (FEI/FBI/FEE/FBE). Setting the PLL clock
602 enable independent, enables the
603 PLL in the FLL modes. */
604 kMCG_PllEnableInStop = MCG_C5_PLLSTEN0_MASK /*!< MCGPLLCLK enable in STOP mode. */
605 };
606
607 /*! @brief MCG mode definitions */
608 typedef enum _mcg_mode
609 {
610 kMCG_ModeFEI = 0U, /*!< FEI - FLL Engaged Internal */
611 kMCG_ModeFBI, /*!< FBI - FLL Bypassed Internal */
612 kMCG_ModeBLPI, /*!< BLPI - Bypassed Low Power Internal */
613 kMCG_ModeFEE, /*!< FEE - FLL Engaged External */
614 kMCG_ModeFBE, /*!< FBE - FLL Bypassed External */
615 kMCG_ModeBLPE, /*!< BLPE - Bypassed Low Power External */
616 kMCG_ModePBE, /*!< PBE - PLL Bypassed External */
617 kMCG_ModePEE, /*!< PEE - PLL Engaged External */
618 kMCG_ModeError /*!< Unknown mode */
619 } mcg_mode_t;
620
621 /*! @brief MCG PLL configuration. */
622 typedef struct _mcg_pll_config
623 {
624 uint8_t enableMode; /*!< Enable mode. OR'ed value of enumeration _mcg_pll_enable_mode. */
625 uint8_t prdiv; /*!< Reference divider PRDIV. */
626 uint8_t vdiv; /*!< VCO divider VDIV. */
627 } mcg_pll_config_t;
628
629 /*! @brief MCG mode change configuration structure
630 *
631 * When porting to a new board, set the following members
632 * according to the board setting:
633 * 1. frdiv: If the FLL uses the external reference clock, set this
634 * value to ensure that the external reference clock divided by frdiv is
635 * in the 31.25 kHz to 39.0625 kHz range.
636 * 2. The PLL reference clock divider PRDIV: PLL reference clock frequency after
637 * PRDIV should be in the FSL_FEATURE_MCG_PLL_REF_MIN to
638 * FSL_FEATURE_MCG_PLL_REF_MAX range.
639 */
640 typedef struct _mcg_config
641 {
642 mcg_mode_t mcgMode; /*!< MCG mode. */
643
644 /* ----------------------- MCGIRCCLK settings ------------------------ */
645 uint8_t irclkEnableMode; /*!< MCGIRCLK enable mode. */
646 mcg_irc_mode_t ircs; /*!< Source, MCG_C2[IRCS]. */
647 uint8_t fcrdiv; /*!< Divider, MCG_SC[FCRDIV]. */
648
649 /* ------------------------ MCG FLL settings ------------------------- */
650 uint8_t frdiv; /*!< Divider MCG_C1[FRDIV]. */
651 mcg_drs_t drs; /*!< DCO range MCG_C4[DRST_DRS]. */
652 mcg_dmx32_t dmx32; /*!< MCG_C4[DMX32]. */
653
654 /* ------------------------ MCG PLL settings ------------------------- */
655 mcg_pll_config_t pll0Config; /*!< MCGPLL0CLK configuration. */
656
657 } mcg_config_t;
658
659 /*******************************************************************************
660 * API
661 ******************************************************************************/
662
663 #if defined(__cplusplus)
664 extern "C" {
665 #endif /* __cplusplus */
666
667 /*!
668 * @brief Enable the clock for specific IP.
669 *
670 * @param name Which clock to enable, see \ref clock_ip_name_t.
671 */
CLOCK_EnableClock(clock_ip_name_t name)672 static inline void CLOCK_EnableClock(clock_ip_name_t name)
673 {
674 uint32_t regAddr = SIM_BASE + CLK_GATE_ABSTRACT_REG_OFFSET((uint32_t)name);
675 (*(volatile uint32_t *)regAddr) |= (1UL << CLK_GATE_ABSTRACT_BITS_SHIFT((uint32_t)name));
676 }
677
678 /*!
679 * @brief Disable the clock for specific IP.
680 *
681 * @param name Which clock to disable, see \ref clock_ip_name_t.
682 */
CLOCK_DisableClock(clock_ip_name_t name)683 static inline void CLOCK_DisableClock(clock_ip_name_t name)
684 {
685 uint32_t regAddr = SIM_BASE + CLK_GATE_ABSTRACT_REG_OFFSET((uint32_t)name);
686 (*(volatile uint32_t *)regAddr) &= ~(1UL << CLK_GATE_ABSTRACT_BITS_SHIFT((uint32_t)name));
687 }
688
689 /*!
690 * @brief Set ERCLK32K source.
691 *
692 * @param src The value to set ERCLK32K clock source.
693 */
CLOCK_SetEr32kClock(uint32_t src)694 static inline void CLOCK_SetEr32kClock(uint32_t src)
695 {
696 SIM->SOPT1 = ((SIM->SOPT1 & ~SIM_SOPT1_OSC32KSEL_MASK) | SIM_SOPT1_OSC32KSEL(src));
697 }
698
699 /*!
700 * @brief Set EMVSIM clock source.
701 *
702 * @param src The value to set enet timestamp clock source.
703 */
CLOCK_SetEnetTime0Clock(uint32_t src)704 static inline void CLOCK_SetEnetTime0Clock(uint32_t src)
705 {
706 SIM->SOPT2 = ((SIM->SOPT2 & ~SIM_SOPT2_TIMESRC_MASK) | SIM_SOPT2_TIMESRC(src));
707 }
708
709 /*!
710 * @brief Set debug trace clock source.
711 *
712 * @param src The value to set debug trace clock source.
713 * @param divValue
714 * @param fracValue
715 */
CLOCK_SetTraceClock(uint32_t src,uint32_t divValue,uint32_t fracValue)716 static inline void CLOCK_SetTraceClock(uint32_t src, uint32_t divValue, uint32_t fracValue)
717 {
718 SIM->SOPT2 = ((SIM->SOPT2 & ~SIM_SOPT2_TRACECLKSEL_MASK) | SIM_SOPT2_TRACECLKSEL(src));
719 SIM->CLKDIV4 = SIM_CLKDIV4_TRACEDIV(divValue) | SIM_CLKDIV4_TRACEFRAC(fracValue);
720 }
721
722 /*!
723 * @brief Set PLLFLLSEL clock source.
724 *
725 * @param src The value to set PLLFLLSEL clock source.
726 */
CLOCK_SetPllFllSelClock(uint32_t src)727 static inline void CLOCK_SetPllFllSelClock(uint32_t src)
728 {
729 SIM->SOPT2 = ((SIM->SOPT2 & ~SIM_SOPT2_PLLFLLSEL_MASK) | SIM_SOPT2_PLLFLLSEL(src));
730 }
731
732 /*!
733 * @brief Set CLKOUT source.
734 *
735 * @param src The value to set CLKOUT source.
736 */
CLOCK_SetClkOutClock(uint32_t src)737 static inline void CLOCK_SetClkOutClock(uint32_t src)
738 {
739 SIM->SOPT2 = ((SIM->SOPT2 & ~SIM_SOPT2_CLKOUTSEL_MASK) | SIM_SOPT2_CLKOUTSEL(src));
740 }
741
742 /*!
743 * @brief System clock divider
744 *
745 * Set the SIM_CLKDIV1[OUTDIV1], SIM_CLKDIV1[OUTDIV2], SIM_CLKDIV1[OUTDIV3], SIM_CLKDIV1[OUTDIV4].
746 *
747 * @param outdiv1 Clock 1 output divider value.
748 *
749 * @param outdiv2 Clock 2 output divider value.
750 *
751 * @param outdiv3 Clock 3 output divider value.
752 *
753 * @param outdiv4 Clock 4 output divider value.
754 */
CLOCK_SetOutDiv(uint32_t outdiv1,uint32_t outdiv2,uint32_t outdiv3,uint32_t outdiv4)755 static inline void CLOCK_SetOutDiv(uint32_t outdiv1, uint32_t outdiv2, uint32_t outdiv3, uint32_t outdiv4)
756 {
757 SIM->CLKDIV1 = SIM_CLKDIV1_OUTDIV1(outdiv1) | SIM_CLKDIV1_OUTDIV2(outdiv2) | SIM_CLKDIV1_OUTDIV3(outdiv3) |
758 SIM_CLKDIV1_OUTDIV4(outdiv4);
759 }
760
761 /*!
762 * @brief Gets the clock frequency for a specific clock name.
763 *
764 * This function checks the current clock configurations and then calculates
765 * the clock frequency for a specific clock name defined in clock_name_t.
766 * The MCG must be properly configured before using this function.
767 *
768 * @param clockName Clock names defined in clock_name_t
769 * @return Clock frequency value in Hertz
770 */
771 uint32_t CLOCK_GetFreq(clock_name_t clockName);
772
773 /*!
774 * @brief Get the core clock or system clock frequency.
775 *
776 * @return Clock frequency in Hz.
777 */
778 uint32_t CLOCK_GetCoreSysClkFreq(void);
779
780 /*!
781 * @brief Get the fast peripheral clock frequency.
782 *
783 * @return Clock frequency in Hz.
784 */
785 uint32_t CLOCK_GetFastPeriphClkFreq(void);
786
787 /*!
788 * @brief Get the flexbus clock frequency.
789 *
790 * @return Clock frequency in Hz.
791 */
792 uint32_t CLOCK_GetFlexBusClkFreq(void);
793
794 /*!
795 * @brief Get the bus clock frequency.
796 *
797 * @return Clock frequency in Hz.
798 */
799 uint32_t CLOCK_GetBusClkFreq(void);
800
801 /*!
802 * @brief Get the flash clock frequency.
803 *
804 * @return Clock frequency in Hz.
805 */
806 uint32_t CLOCK_GetFlashClkFreq(void);
807
808 /*!
809 * @brief Get the output clock frequency selected by SIM[PLLFLLSEL].
810 *
811 * @return Clock frequency in Hz.
812 */
813 uint32_t CLOCK_GetPllFllSelClkFreq(void);
814
815 /*!
816 * @brief Get the external reference 32K clock frequency (ERCLK32K).
817 *
818 * @return Clock frequency in Hz.
819 */
820 uint32_t CLOCK_GetEr32kClkFreq(void);
821
822 /*!
823 * @brief Get the OSC0 external reference undivided clock frequency (OSC0ERCLK_UNDIV).
824 *
825 * @return Clock frequency in Hz.
826 */
827 uint32_t CLOCK_GetOsc0ErClkUndivFreq(void);
828
829 /*!
830 * @brief Get the OSC0 external reference clock frequency (OSC0ERCLK).
831 *
832 * @return Clock frequency in Hz.
833 */
834 uint32_t CLOCK_GetOsc0ErClkFreq(void);
835
836 /*!
837 * @brief Get the OSC0 external reference divided clock frequency.
838 *
839 * @return Clock frequency in Hz.
840 */
841 uint32_t CLOCK_GetOsc0ErClkDivFreq(void);
842
843 /*!
844 * @brief Set the clock configure in SIM module.
845 *
846 * This function sets system layer clock settings in SIM module.
847 *
848 * @param config Pointer to the configure structure.
849 */
850 void CLOCK_SetSimConfig(sim_clock_config_t const *config);
851
852 /*!
853 * @brief Set the system clock dividers in SIM to safe value.
854 *
855 * The system level clocks (core clock, bus clock, flexbus clock and flash clock)
856 * must be in allowed ranges. During MCG clock mode switch, the MCG output clock
857 * changes then the system level clocks may be out of range. This function could
858 * be used before MCG mode change, to make sure system level clocks are in allowed
859 * range.
860 *
861 */
CLOCK_SetSimSafeDivs(void)862 static inline void CLOCK_SetSimSafeDivs(void)
863 {
864 SIM->CLKDIV1 = 0x01170000U;
865 }
866
867 /*! @name MCG frequency functions. */
868 /*@{*/
869
870 /*!
871 * @brief Gets the MCG output clock (MCGOUTCLK) frequency.
872 *
873 * This function gets the MCG output clock frequency in Hz based on the current MCG
874 * register value.
875 *
876 * @return The frequency of MCGOUTCLK.
877 */
878 uint32_t CLOCK_GetOutClkFreq(void);
879
880 /*!
881 * @brief Gets the MCG FLL clock (MCGFLLCLK) frequency.
882 *
883 * This function gets the MCG FLL clock frequency in Hz based on the current MCG
884 * register value. The FLL is enabled in FEI/FBI/FEE/FBE mode and
885 * disabled in low power state in other modes.
886 *
887 * @return The frequency of MCGFLLCLK.
888 */
889 uint32_t CLOCK_GetFllFreq(void);
890
891 /*!
892 * @brief Gets the MCG internal reference clock (MCGIRCLK) frequency.
893 *
894 * This function gets the MCG internal reference clock frequency in Hz based
895 * on the current MCG register value.
896 *
897 * @return The frequency of MCGIRCLK.
898 */
899 uint32_t CLOCK_GetInternalRefClkFreq(void);
900
901 /*!
902 * @brief Gets the MCG fixed frequency clock (MCGFFCLK) frequency.
903 *
904 * This function gets the MCG fixed frequency clock frequency in Hz based
905 * on the current MCG register value.
906 *
907 * @return The frequency of MCGFFCLK.
908 */
909 uint32_t CLOCK_GetFixedFreqClkFreq(void);
910
911 /*!
912 * @brief Gets the MCG PLL0 clock (MCGPLL0CLK) frequency.
913 *
914 * This function gets the MCG PLL0 clock frequency in Hz based on the current MCG
915 * register value.
916 *
917 * @return The frequency of MCGPLL0CLK.
918 */
919 uint32_t CLOCK_GetPll0Freq(void);
920
921 /*@}*/
922
923 /*! @name MCG clock configuration. */
924 /*@{*/
925
926 /*!
927 * @brief Enables or disables the MCG low power.
928 *
929 * Enabling the MCG low power disables the PLL and FLL in bypass modes. In other words,
930 * in FBE and PBE modes, enabling low power sets the MCG to BLPE mode. In FBI and
931 * PBI modes, enabling low power sets the MCG to BLPI mode.
932 * When disabling the MCG low power, the PLL or FLL are enabled based on MCG settings.
933 *
934 * @param enable True to enable MCG low power, false to disable MCG low power.
935 */
CLOCK_SetLowPowerEnable(bool enable)936 static inline void CLOCK_SetLowPowerEnable(bool enable)
937 {
938 if (enable)
939 {
940 MCG->C2 |= MCG_C2_LP_MASK;
941 }
942 else
943 {
944 MCG->C2 &= ~(uint8_t)MCG_C2_LP_MASK;
945 }
946 }
947
948 /*!
949 * @brief Configures the Internal Reference clock (MCGIRCLK).
950 *
951 * This function sets the \c MCGIRCLK base on parameters. It also selects the IRC
952 * source. If the fast IRC is used, this function sets the fast IRC divider.
953 * This function also sets whether the \c MCGIRCLK is enabled in stop mode.
954 * Calling this function in FBI/PBI/BLPI modes may change the system clock. As a result,
955 * using the function in these modes it is not allowed.
956 *
957 * @param enableMode MCGIRCLK enable mode, OR'ed value of the enumeration _mcg_irclk_enable_mode.
958 * @param ircs MCGIRCLK clock source, choose fast or slow.
959 * @param fcrdiv Fast IRC divider setting (\c FCRDIV).
960 * @retval kStatus_MCG_SourceUsed Because the internal reference clock is used as a clock source,
961 * the configuration should not be changed. Otherwise, a glitch occurs.
962 * @retval kStatus_Success MCGIRCLK configuration finished successfully.
963 */
964 status_t CLOCK_SetInternalRefClkConfig(uint8_t enableMode, mcg_irc_mode_t ircs, uint8_t fcrdiv);
965
966 /*!
967 * @brief Selects the MCG external reference clock.
968 *
969 * Selects the MCG external reference clock source, changes the MCG_C7[OSCSEL],
970 * and waits for the clock source to be stable. Because the external reference
971 * clock should not be changed in FEE/FBE/BLPE/PBE/PEE modes, do not call this function in these modes.
972 *
973 * @param oscsel MCG external reference clock source, MCG_C7[OSCSEL].
974 * @retval kStatus_MCG_SourceUsed Because the external reference clock is used as a clock source,
975 * the configuration should not be changed. Otherwise, a glitch occurs.
976 * @retval kStatus_Success External reference clock set successfully.
977 */
978 status_t CLOCK_SetExternalRefClkConfig(mcg_oscsel_t oscsel);
979
980 /*!
981 * @brief Set the FLL external reference clock divider value.
982 *
983 * Sets the FLL external reference clock divider value, the register MCG_C1[FRDIV].
984 *
985 * @param frdiv The FLL external reference clock divider value, MCG_C1[FRDIV].
986 */
CLOCK_SetFllExtRefDiv(uint8_t frdiv)987 static inline void CLOCK_SetFllExtRefDiv(uint8_t frdiv)
988 {
989 MCG->C1 = (uint8_t)((MCG->C1 & ~MCG_C1_FRDIV_MASK) | MCG_C1_FRDIV(frdiv));
990 }
991
992 /*!
993 * @brief Enables the PLL0 in FLL mode.
994 *
995 * This function sets us the PLL0 in FLL mode and reconfigures
996 * the PLL0. Ensure that the PLL reference
997 * clock is enabled before calling this function and that the PLL0 is not used as a clock source.
998 * The function CLOCK_CalcPllDiv gets the correct PLL
999 * divider values.
1000 *
1001 * @param config Pointer to the configuration structure.
1002 */
1003 void CLOCK_EnablePll0(mcg_pll_config_t const *config);
1004
1005 /*!
1006 * @brief Disables the PLL0 in FLL mode.
1007 *
1008 * This function disables the PLL0 in FLL mode. It should be used together with the
1009 * @ref CLOCK_EnablePll0.
1010 */
CLOCK_DisablePll0(void)1011 static inline void CLOCK_DisablePll0(void)
1012 {
1013 MCG->C5 &= (uint8_t)(~(MCG_C5_PLLCLKEN0_MASK | MCG_C5_PLLSTEN0_MASK));
1014 }
1015
1016 /*!
1017 * @brief Calculates the PLL divider setting for a desired output frequency.
1018 *
1019 * This function calculates the correct reference clock divider (\c PRDIV) and
1020 * VCO divider (\c VDIV) to generate a desired PLL output frequency. It returns the
1021 * closest frequency match with the corresponding \c PRDIV/VDIV
1022 * returned from parameters. If a desired frequency is not valid, this function
1023 * returns 0.
1024 *
1025 * @param refFreq PLL reference clock frequency.
1026 * @param desireFreq Desired PLL output frequency.
1027 * @param prdiv PRDIV value to generate desired PLL frequency.
1028 * @param vdiv VDIV value to generate desired PLL frequency.
1029 * @return Closest frequency match that the PLL was able generate.
1030 */
1031 uint32_t CLOCK_CalcPllDiv(uint32_t refFreq, uint32_t desireFreq, uint8_t *prdiv, uint8_t *vdiv);
1032
1033 /*@}*/
1034
1035 /*! @name MCG clock lock monitor functions. */
1036 /*@{*/
1037
1038 /*!
1039 * @brief Sets the OSC0 clock monitor mode.
1040 *
1041 * This function sets the OSC0 clock monitor mode. See @ref mcg_monitor_mode_t for details.
1042 *
1043 * @param mode Monitor mode to set.
1044 */
1045 void CLOCK_SetOsc0MonitorMode(mcg_monitor_mode_t mode);
1046
1047 /*!
1048 * @brief Sets the PLL0 clock monitor mode.
1049 *
1050 * This function sets the PLL0 clock monitor mode. See @ref mcg_monitor_mode_t for details.
1051 *
1052 * @param mode Monitor mode to set.
1053 */
1054 void CLOCK_SetPll0MonitorMode(mcg_monitor_mode_t mode);
1055
1056 /*!
1057 * @brief Gets the MCG status flags.
1058 *
1059 * This function gets the MCG clock status flags. All status flags are
1060 * returned as a logical OR of the enumeration refer to _mcg_status_flags_t. To
1061 * check a specific flag, compare the return value with the flag.
1062 *
1063 * Example:
1064 * @code
1065 * To check the clock lost lock status of OSC0 and PLL0.
1066 * uint32_t mcgFlags;
1067 *
1068 * mcgFlags = CLOCK_GetStatusFlags();
1069 *
1070 * if (mcgFlags & kMCG_Osc0LostFlag)
1071 * {
1072 * OSC0 clock lock lost. Do something.
1073 * }
1074 * if (mcgFlags & kMCG_Pll0LostFlag)
1075 * {
1076 * PLL0 clock lock lost. Do something.
1077 * }
1078 * @endcode
1079 *
1080 * @return Logical OR value of the enumeration _mcg_status_flags_t.
1081 */
1082 uint32_t CLOCK_GetStatusFlags(void);
1083
1084 /*!
1085 * @brief Clears the MCG status flags.
1086 *
1087 * This function clears the MCG clock lock lost status. The parameter is a logical
1088 * OR value of the flags to clear. See the enumeration _mcg_status_flags_t.
1089 *
1090 * Example:
1091 * @code
1092 * To clear the clock lost lock status flags of OSC0 and PLL0.
1093 *
1094 * CLOCK_ClearStatusFlags(kMCG_Osc0LostFlag | kMCG_Pll0LostFlag);
1095 * @endcode
1096 *
1097 * @param mask The status flags to clear. This is a logical OR of members of the
1098 * enumeration _mcg_status_flags_t.
1099 */
1100 void CLOCK_ClearStatusFlags(uint32_t mask);
1101
1102 /*@}*/
1103
1104 /*!
1105 * @name OSC configuration
1106 * @{
1107 */
1108
1109 /*!
1110 * @brief Configures the OSC external reference clock (OSCERCLK).
1111 *
1112 * This function configures the OSC external reference clock (OSCERCLK).
1113 * This is an example to enable the OSCERCLK in normal and stop modes and also set
1114 * the output divider to 1:
1115 *
1116 @code
1117 oscer_config_t config =
1118 {
1119 .enableMode = kOSC_ErClkEnable | kOSC_ErClkEnableInStop,
1120 .erclkDiv = 1U,
1121 };
1122
1123 OSC_SetExtRefClkConfig(OSC, &config);
1124 @endcode
1125 *
1126 * @param base OSC peripheral address.
1127 * @param config Pointer to the configuration structure.
1128 */
OSC_SetExtRefClkConfig(OSC_Type * base,oscer_config_t const * config)1129 static inline void OSC_SetExtRefClkConfig(OSC_Type *base, oscer_config_t const *config)
1130 {
1131 uint8_t reg = base->CR;
1132
1133 reg &= (uint8_t)(~(OSC_CR_ERCLKEN_MASK | OSC_CR_EREFSTEN_MASK));
1134 reg |= config->enableMode;
1135
1136 base->CR = reg;
1137
1138 base->DIV = OSC_DIV_ERPS(config->erclkDiv);
1139 }
1140
1141 /*!
1142 * @brief Sets the capacitor load configuration for the oscillator.
1143 *
1144 * This function sets the specified capacitors configuration for the oscillator.
1145 * This should be done in the early system level initialization function call
1146 * based on the system configuration.
1147 *
1148 * @param base OSC peripheral address.
1149 * @param capLoad OR'ed value for the capacitor load option, see \ref _osc_cap_load.
1150 *
1151 * Example:
1152 @code
1153 To enable only 2 pF and 8 pF capacitor load, please use like this.
1154 OSC_SetCapLoad(OSC, kOSC_Cap2P | kOSC_Cap8P);
1155 @endcode
1156 */
OSC_SetCapLoad(OSC_Type * base,uint8_t capLoad)1157 static inline void OSC_SetCapLoad(OSC_Type *base, uint8_t capLoad)
1158 {
1159 uint8_t reg = base->CR;
1160
1161 reg &= (uint8_t)(~(OSC_CR_SC2P_MASK | OSC_CR_SC4P_MASK | OSC_CR_SC8P_MASK | OSC_CR_SC16P_MASK));
1162 reg |= capLoad;
1163
1164 base->CR = reg;
1165 }
1166
1167 /*!
1168 * @brief Initializes the OSC0.
1169 *
1170 * This function initializes the OSC0 according to the board configuration.
1171 *
1172 * @param config Pointer to the OSC0 configuration structure.
1173 */
1174 void CLOCK_InitOsc0(osc_config_t const *config);
1175
1176 /*!
1177 * @brief Deinitializes the OSC0.
1178 *
1179 * This function deinitializes the OSC0.
1180 */
1181 void CLOCK_DeinitOsc0(void);
1182
1183 /* @} */
1184
1185 /*!
1186 * @name External clock frequency
1187 * @{
1188 */
1189
1190 /*!
1191 * @brief Sets the XTAL0 frequency based on board settings.
1192 *
1193 * @param freq The XTAL0/EXTAL0 input clock frequency in Hz.
1194 */
CLOCK_SetXtal0Freq(uint32_t freq)1195 static inline void CLOCK_SetXtal0Freq(uint32_t freq)
1196 {
1197 g_xtal0Freq = freq;
1198 }
1199
1200 /*!
1201 * @brief Sets the XTAL32/RTC_CLKIN frequency based on board settings.
1202 *
1203 * @param freq The XTAL32/EXTAL32/RTC_CLKIN input clock frequency in Hz.
1204 */
CLOCK_SetXtal32Freq(uint32_t freq)1205 static inline void CLOCK_SetXtal32Freq(uint32_t freq)
1206 {
1207 g_xtal32Freq = freq;
1208 }
1209 /* @} */
1210
1211 /*!
1212 * @name IRCs frequency
1213 * @{
1214 */
1215
1216 /*!
1217 * @brief Set the Slow IRC frequency based on the trimmed value
1218 *
1219 * @param freq The Slow IRC frequency input clock frequency in Hz.
1220 */
1221 void CLOCK_SetSlowIrcFreq(uint32_t freq);
1222
1223 /*!
1224 * @brief Set the Fast IRC frequency based on the trimmed value
1225 *
1226 * @param freq The Fast IRC frequency input clock frequency in Hz.
1227 */
1228 void CLOCK_SetFastIrcFreq(uint32_t freq);
1229 /* @} */
1230
1231 /*!
1232 * @name MCG auto-trim machine.
1233 * @{
1234 */
1235
1236 /*!
1237 * @brief Auto trims the internal reference clock.
1238 *
1239 * This function trims the internal reference clock by using the external clock. If
1240 * successful, it returns the kStatus_Success and the frequency after
1241 * trimming is received in the parameter @p actualFreq. If an error occurs,
1242 * the error code is returned.
1243 *
1244 * @param extFreq External clock frequency, which should be a bus clock.
1245 * @param desireFreq Frequency to trim to.
1246 * @param actualFreq Actual frequency after trimming.
1247 * @param atms Trim fast or slow internal reference clock.
1248 * @retval kStatus_Success ATM success.
1249 * @retval kStatus_MCG_AtmBusClockInvalid The bus clock is not in allowed range for the ATM.
1250 * @retval kStatus_MCG_AtmDesiredFreqInvalid MCGIRCLK could not be trimmed to the desired frequency.
1251 * @retval kStatus_MCG_AtmIrcUsed Could not trim because MCGIRCLK is used as a bus clock source.
1252 * @retval kStatus_MCG_AtmHardwareFail Hardware fails while trimming.
1253 */
1254 status_t CLOCK_TrimInternalRefClk(uint32_t extFreq, uint32_t desireFreq, uint32_t *actualFreq, mcg_atm_select_t atms);
1255 /* @} */
1256
1257 /*! @name MCG mode functions. */
1258 /*@{*/
1259
1260 /*!
1261 * @brief Gets the current MCG mode.
1262 *
1263 * This function checks the MCG registers and determines the current MCG mode.
1264 *
1265 * @return Current MCG mode or error code; See @ref mcg_mode_t.
1266 */
1267 mcg_mode_t CLOCK_GetMode(void);
1268
1269 /*!
1270 * @brief Sets the MCG to FEI mode.
1271 *
1272 * This function sets the MCG to FEI mode. If setting to FEI mode fails
1273 * from the current mode, this function returns an error.
1274 *
1275 * @param dmx32 DMX32 in FEI mode.
1276 * @param drs The DCO range selection.
1277 * @param fllStableDelay Delay function to ensure that the FLL is stable. Passing
1278 * NULL does not cause a delay.
1279 * @retval kStatus_MCG_ModeUnreachable Could not switch to the target mode.
1280 * @retval kStatus_Success Switched to the target mode successfully.
1281 * @note If @p dmx32 is set to kMCG_Dmx32Fine, the slow IRC must not be trimmed
1282 * to a frequency above 32768 Hz.
1283 */
1284 status_t CLOCK_SetFeiMode(mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDelay)(void));
1285
1286 /*!
1287 * @brief Sets the MCG to FEE mode.
1288 *
1289 * This function sets the MCG to FEE mode. If setting to FEE mode fails
1290 * from the current mode, this function returns an error.
1291 *
1292 * @param frdiv FLL reference clock divider setting, FRDIV.
1293 * @param dmx32 DMX32 in FEE mode.
1294 * @param drs The DCO range selection.
1295 * @param fllStableDelay Delay function to make sure FLL is stable. Passing
1296 * NULL does not cause a delay.
1297 *
1298 * @retval kStatus_MCG_ModeUnreachable Could not switch to the target mode.
1299 * @retval kStatus_Success Switched to the target mode successfully.
1300 */
1301 status_t CLOCK_SetFeeMode(uint8_t frdiv, mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDelay)(void));
1302
1303 /*!
1304 * @brief Sets the MCG to FBI mode.
1305 *
1306 * This function sets the MCG to FBI mode. If setting to FBI mode fails
1307 * from the current mode, this function returns an error.
1308 *
1309 * @param dmx32 DMX32 in FBI mode.
1310 * @param drs The DCO range selection.
1311 * @param fllStableDelay Delay function to make sure FLL is stable. If the FLL
1312 * is not used in FBI mode, this parameter can be NULL. Passing
1313 * NULL does not cause a delay.
1314 * @retval kStatus_MCG_ModeUnreachable Could not switch to the target mode.
1315 * @retval kStatus_Success Switched to the target mode successfully.
1316 * @note If @p dmx32 is set to kMCG_Dmx32Fine, the slow IRC must not be trimmed
1317 * to frequency above 32768 Hz.
1318 */
1319 status_t CLOCK_SetFbiMode(mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDelay)(void));
1320
1321 /*!
1322 * @brief Sets the MCG to FBE mode.
1323 *
1324 * This function sets the MCG to FBE mode. If setting to FBE mode fails
1325 * from the current mode, this function returns an error.
1326 *
1327 * @param frdiv FLL reference clock divider setting, FRDIV.
1328 * @param dmx32 DMX32 in FBE mode.
1329 * @param drs The DCO range selection.
1330 * @param fllStableDelay Delay function to make sure FLL is stable. If the FLL
1331 * is not used in FBE mode, this parameter can be NULL. Passing NULL
1332 * does not cause a delay.
1333 * @retval kStatus_MCG_ModeUnreachable Could not switch to the target mode.
1334 * @retval kStatus_Success Switched to the target mode successfully.
1335 */
1336 status_t CLOCK_SetFbeMode(uint8_t frdiv, mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDelay)(void));
1337
1338 /*!
1339 * @brief Sets the MCG to BLPI mode.
1340 *
1341 * This function sets the MCG to BLPI mode. If setting to BLPI mode fails
1342 * from the current mode, this function returns an error.
1343 *
1344 * @retval kStatus_MCG_ModeUnreachable Could not switch to the target mode.
1345 * @retval kStatus_Success Switched to the target mode successfully.
1346 */
1347 status_t CLOCK_SetBlpiMode(void);
1348
1349 /*!
1350 * @brief Sets the MCG to BLPE mode.
1351 *
1352 * This function sets the MCG to BLPE mode. If setting to BLPE mode fails
1353 * from the current mode, this function returns an error.
1354 *
1355 * @retval kStatus_MCG_ModeUnreachable Could not switch to the target mode.
1356 * @retval kStatus_Success Switched to the target mode successfully.
1357 */
1358 status_t CLOCK_SetBlpeMode(void);
1359
1360 /*!
1361 * @brief Sets the MCG to PBE mode.
1362 *
1363 * This function sets the MCG to PBE mode. If setting to PBE mode fails
1364 * from the current mode, this function returns an error.
1365 *
1366 * @param pllcs The PLL selection, PLLCS.
1367 * @param config Pointer to the PLL configuration.
1368 * @retval kStatus_MCG_ModeUnreachable Could not switch to the target mode.
1369 * @retval kStatus_Success Switched to the target mode successfully.
1370 *
1371 * @note
1372 * 1. The parameter \c pllcs selects the PLL. For platforms with
1373 * only one PLL, the parameter pllcs is kept for interface compatibility.
1374 * 2. The parameter \c config is the PLL configuration structure. On some
1375 * platforms, it is possible to choose the external PLL directly, which renders the
1376 * configuration structure not necessary. In this case, pass in NULL.
1377 * For example: CLOCK_SetPbeMode(kMCG_OscselOsc, kMCG_PllClkSelExtPll, NULL);
1378 */
1379 status_t CLOCK_SetPbeMode(mcg_pll_clk_select_t pllcs, mcg_pll_config_t const *config);
1380
1381 /*!
1382 * @brief Sets the MCG to PEE mode.
1383 *
1384 * This function sets the MCG to PEE mode.
1385 *
1386 * @retval kStatus_MCG_ModeUnreachable Could not switch to the target mode.
1387 * @retval kStatus_Success Switched to the target mode successfully.
1388 *
1389 * @note This function only changes the CLKS to use the PLL/FLL output. If the
1390 * PRDIV/VDIV are different than in the PBE mode, set them up
1391 * in PBE mode and wait. When the clock is stable, switch to PEE mode.
1392 */
1393 status_t CLOCK_SetPeeMode(void);
1394
1395 /*!
1396 * @brief Switches the MCG to FBE mode from the external mode.
1397 *
1398 * This function switches the MCG from external modes (PEE/PBE/BLPE/FEE) to the FBE mode quickly.
1399 * The external clock is used as the system clock source and PLL is disabled. However,
1400 * the FLL settings are not configured. This is a lite function with a small code size, which is useful
1401 * during the mode switch. For example, to switch from PEE mode to FEI mode:
1402 *
1403 * @code
1404 * CLOCK_ExternalModeToFbeModeQuick();
1405 * CLOCK_SetFeiMode(...);
1406 * @endcode
1407 *
1408 * @retval kStatus_Success Switched successfully.
1409 * @retval kStatus_MCG_ModeInvalid If the current mode is not an external mode, do not call this function.
1410 */
1411 status_t CLOCK_ExternalModeToFbeModeQuick(void);
1412
1413 /*!
1414 * @brief Switches the MCG to FBI mode from internal modes.
1415 *
1416 * This function switches the MCG from internal modes (PEI/PBI/BLPI/FEI) to the FBI mode quickly.
1417 * The MCGIRCLK is used as the system clock source and PLL is disabled. However,
1418 * FLL settings are not configured. This is a lite function with a small code size, which is useful
1419 * during the mode switch. For example, to switch from PEI mode to FEE mode:
1420 *
1421 * @code
1422 * CLOCK_InternalModeToFbiModeQuick();
1423 * CLOCK_SetFeeMode(...);
1424 * @endcode
1425 *
1426 * @retval kStatus_Success Switched successfully.
1427 * @retval kStatus_MCG_ModeInvalid If the current mode is not an internal mode, do not call this function.
1428 */
1429 status_t CLOCK_InternalModeToFbiModeQuick(void);
1430
1431 /*!
1432 * @brief Sets the MCG to FEI mode during system boot up.
1433 *
1434 * This function sets the MCG to FEI mode from the reset mode. It can also be used to
1435 * set up MCG during system boot up.
1436 *
1437 * @param dmx32 DMX32 in FEI mode.
1438 * @param drs The DCO range selection.
1439 * @param fllStableDelay Delay function to ensure that the FLL is stable.
1440 *
1441 * @retval kStatus_MCG_ModeUnreachable Could not switch to the target mode.
1442 * @retval kStatus_Success Switched to the target mode successfully.
1443 * @note If @p dmx32 is set to kMCG_Dmx32Fine, the slow IRC must not be trimmed
1444 * to frequency above 32768 Hz.
1445 */
1446 status_t CLOCK_BootToFeiMode(mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDelay)(void));
1447
1448 /*!
1449 * @brief Sets the MCG to FEE mode during system bootup.
1450 *
1451 * This function sets MCG to FEE mode from the reset mode. It can also be used to
1452 * set up the MCG during system boot up.
1453 *
1454 * @param oscsel OSC clock select, OSCSEL.
1455 * @param frdiv FLL reference clock divider setting, FRDIV.
1456 * @param dmx32 DMX32 in FEE mode.
1457 * @param drs The DCO range selection.
1458 * @param fllStableDelay Delay function to ensure that the FLL is stable.
1459 *
1460 * @retval kStatus_MCG_ModeUnreachable Could not switch to the target mode.
1461 * @retval kStatus_Success Switched to the target mode successfully.
1462 */
1463 status_t CLOCK_BootToFeeMode(
1464 mcg_oscsel_t oscsel, uint8_t frdiv, mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDelay)(void));
1465
1466 /*!
1467 * @brief Sets the MCG to BLPI mode during system boot up.
1468 *
1469 * This function sets the MCG to BLPI mode from the reset mode. It can also be used to
1470 * set up the MCG during system boot up.
1471 *
1472 * @param fcrdiv Fast IRC divider, FCRDIV.
1473 * @param ircs The internal reference clock to select, IRCS.
1474 * @param ircEnableMode The MCGIRCLK enable mode, OR'ed value of the enumeration _mcg_irclk_enable_mode.
1475 *
1476 * @retval kStatus_MCG_SourceUsed Could not change MCGIRCLK setting.
1477 * @retval kStatus_Success Switched to the target mode successfully.
1478 */
1479 status_t CLOCK_BootToBlpiMode(uint8_t fcrdiv, mcg_irc_mode_t ircs, uint8_t ircEnableMode);
1480
1481 /*!
1482 * @brief Sets the MCG to BLPE mode during system boot up.
1483 *
1484 * This function sets the MCG to BLPE mode from the reset mode. It can also be used to
1485 * set up the MCG during system boot up.
1486 *
1487 * @param oscsel OSC clock select, MCG_C7[OSCSEL].
1488 *
1489 * @retval kStatus_MCG_ModeUnreachable Could not switch to the target mode.
1490 * @retval kStatus_Success Switched to the target mode successfully.
1491 */
1492 status_t CLOCK_BootToBlpeMode(mcg_oscsel_t oscsel);
1493
1494 /*!
1495 * @brief Sets the MCG to PEE mode during system boot up.
1496 *
1497 * This function sets the MCG to PEE mode from reset mode. It can also be used to
1498 * set up the MCG during system boot up.
1499 *
1500 * @param oscsel OSC clock select, MCG_C7[OSCSEL].
1501 * @param pllcs The PLL selection, PLLCS.
1502 * @param config Pointer to the PLL configuration.
1503 *
1504 * @retval kStatus_MCG_ModeUnreachable Could not switch to the target mode.
1505 * @retval kStatus_Success Switched to the target mode successfully.
1506 */
1507 status_t CLOCK_BootToPeeMode(mcg_oscsel_t oscsel, mcg_pll_clk_select_t pllcs, mcg_pll_config_t const *config);
1508
1509 /*!
1510 * @brief Sets the MCG to a target mode.
1511 *
1512 * This function sets MCG to a target mode defined by the configuration
1513 * structure. If switching to the target mode fails, this function
1514 * chooses the correct path.
1515 *
1516 * @param config Pointer to the target MCG mode configuration structure.
1517 * @return Return kStatus_Success if switched successfully; Otherwise, it returns an error code _mcg_status.
1518 *
1519 * @note If the external clock is used in the target mode, ensure that it is
1520 * enabled. For example, if the OSC0 is used, set up OSC0 correctly before calling this
1521 * function.
1522 */
1523 status_t CLOCK_SetMcgConfig(mcg_config_t const *config);
1524
1525 /*@}*/
1526
1527 #if defined(__cplusplus)
1528 }
1529 #endif /* __cplusplus */
1530
1531 /*! @} */
1532
1533 #endif /* _FSL_CLOCK_H_ */
1534
