1 /*
2 * Copyright (c) 2015, Freescale Semiconductor, Inc.
3 * Copyright 2016 - 2020, NXP
4 * All rights reserved.
5 *
6 * SPDX-License-Identifier: BSD-3-Clause
7 */
8
9 #ifndef _FSL_CLOCK_H_
10 #define _FSL_CLOCK_H_
11
12 #include "fsl_common.h"
13
14 /*! @addtogroup clock */
15 /*! @{ */
16
17 /*! @file */
18
19 /*******************************************************************************
20 * Configurations
21 ******************************************************************************/
22
23 /*! @brief Configures whether to check a parameter in a function.
24 *
25 * Some MCG settings must be changed with conditions, for example:
26 * 1. MCGIRCLK settings, such as the source, divider, and the trim value should not change when
27 * MCGIRCLK is used as a system clock source.
28 * 2. MCG_C7[OSCSEL] should not be changed when the external reference clock is used
29 * as a system clock source. For example, in FBE/BLPE/PBE modes.
30 * 3. The users should only switch between the supported clock modes.
31 *
32 * MCG functions check the parameter and MCG status before setting, if not allowed
33 * to change, the functions return error. The parameter checking increases code size,
34 * if code size is a critical requirement, change #MCG_CONFIG_CHECK_PARAM to 0 to
35 * disable parameter checking.
36 */
37 #ifndef MCG_CONFIG_CHECK_PARAM
38 #define MCG_CONFIG_CHECK_PARAM 0U
39 #endif
40
41 /*! @brief Configure whether driver controls clock
42 *
43 * When set to 0, peripheral drivers will enable clock in initialize function
44 * and disable clock in de-initialize function. When set to 1, peripheral
45 * driver will not control the clock, application could control the clock out of
46 * the driver.
47 *
48 * @note All drivers share this feature switcher. If it is set to 1, application
49 * should handle clock enable and disable for all drivers.
50 */
51 #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL))
52 #define FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL 0
53 #endif
54
55 /*******************************************************************************
56 * Definitions
57 ******************************************************************************/
58
59 /*! @name Driver version */
60 /*@{*/
61 /*! @brief CLOCK driver version 2.5.2. */
62 #define FSL_CLOCK_DRIVER_VERSION (MAKE_VERSION(2, 5, 2))
63 /*@}*/
64
65 /*! @brief External XTAL0 (OSC0) clock frequency.
66 *
67 * The XTAL0/EXTAL0 (OSC0) clock frequency in Hz. When the clock is set up, use the
68 * function CLOCK_SetXtal0Freq to set the value in the clock driver. For example,
69 * if XTAL0 is 8 MHz:
70 * @code
71 * Set up the OSC0
72 * CLOCK_InitOsc0(...);
73 * Set the XTAL0 value to the clock driver.
74 * CLOCK_SetXtal0Freq(80000000);
75 * @endcode
76 *
77 * This is important for the multicore platforms where only one core needs to set up the
78 * OSC0 using the CLOCK_InitOsc0. All other cores need to call the CLOCK_SetXtal0Freq
79 * to get a valid clock frequency.
80 */
81 extern volatile uint32_t g_xtal0Freq;
82
83 /*! @brief External XTAL32/EXTAL32/RTC_CLKIN clock frequency.
84 *
85 * The XTAL32/EXTAL32/RTC_CLKIN clock frequency in Hz. When the clock is set up, use the
86 * function CLOCK_SetXtal32Freq to set the value in the clock driver.
87 *
88 * This is important for the multicore platforms where only one core needs to set up
89 * the clock. All other cores need to call the CLOCK_SetXtal32Freq
90 * to get a valid clock frequency.
91 */
92 extern volatile uint32_t g_xtal32Freq;
93
94 /*! @brief IRC48M clock frequency in Hz. */
95 #define MCG_INTERNAL_IRC_48M 48000000U
96
97 #if (defined(OSC) && !(defined(OSC0)))
98 #define OSC0 OSC
99 #endif
100
101 /* Definition for delay API in clock driver, users can redefine it to the real application. */
102 #ifndef SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY
103 #define SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY (180000000UL)
104 #endif
105 /*! @brief Clock ip name array for DMAMUX. */
106 #define DMAMUX_CLOCKS \
107 { \
108 kCLOCK_Dmamux0 \
109 }
110
111 /*! @brief Clock ip name array for RTC. */
112 #define RTC_CLOCKS \
113 { \
114 kCLOCK_Rtc0 \
115 }
116
117 /*! @brief Clock ip name array for ENET. */
118 #define ENET_CLOCKS \
119 { \
120 kCLOCK_Enet0 \
121 }
122
123 /*! @brief Clock ip name array for PORT. */
124 #define PORT_CLOCKS \
125 { \
126 kCLOCK_PortA, kCLOCK_PortB, kCLOCK_PortC, kCLOCK_PortD, kCLOCK_PortE \
127 }
128
129 /*! @brief Clock ip name array for SAI. */
130 #define SAI_CLOCKS \
131 { \
132 kCLOCK_Sai0 \
133 }
134
135 /*! @brief Clock ip name array for FLEXBUS. */
136 #define FLEXBUS_CLOCKS \
137 { \
138 kCLOCK_Flexbus0 \
139 }
140
141 /*! @brief Clock ip name array for TSI. */
142 #define TSI_CLOCKS \
143 { \
144 kCLOCK_Tsi0 \
145 }
146
147 /*! @brief Clock ip name array for LPUART. */
148 #define LPUART_CLOCKS \
149 { \
150 kCLOCK_Lpuart0 \
151 }
152
153 /*! @brief Clock ip name array for EWM. */
154 #define EWM_CLOCKS \
155 { \
156 kCLOCK_Ewm0 \
157 }
158
159 /*! @brief Clock ip name array for PIT. */
160 #define PIT_CLOCKS \
161 { \
162 kCLOCK_Pit0 \
163 }
164
165 /*! @brief Clock ip name array for DSPI. */
166 #define DSPI_CLOCKS \
167 { \
168 kCLOCK_Spi0, kCLOCK_Spi1, kCLOCK_Spi2 \
169 }
170
171 /*! @brief Clock ip name array for LPTMR. */
172 #define LPTMR_CLOCKS \
173 { \
174 kCLOCK_Lptmr0 \
175 }
176
177 /*! @brief Clock ip name array for SDHC. */
178 #define SDHC_CLOCKS \
179 { \
180 kCLOCK_Sdhc0 \
181 }
182
183 /*! @brief Clock ip name array for FTM. */
184 #define FTM_CLOCKS \
185 { \
186 kCLOCK_Ftm0, kCLOCK_Ftm1, kCLOCK_Ftm2, kCLOCK_Ftm3 \
187 }
188
189 /*! @brief Clock ip name array for EDMA. */
190 #define EDMA_CLOCKS \
191 { \
192 kCLOCK_Dma0 \
193 }
194
195 /*! @brief Clock ip name array for FLEXCAN. */
196 #define FLEXCAN_CLOCKS \
197 { \
198 kCLOCK_Flexcan0, kCLOCK_Flexcan1 \
199 }
200
201 /*! @brief Clock ip name array for DAC. */
202 #define DAC_CLOCKS \
203 { \
204 kCLOCK_Dac0, kCLOCK_Dac1 \
205 }
206
207 /*! @brief Clock ip name array for ADC16. */
208 #define ADC16_CLOCKS \
209 { \
210 kCLOCK_Adc0, kCLOCK_Adc1 \
211 }
212
213 /*! @brief Clock ip name array for SDRAM. */
214 #define SDRAM_CLOCKS \
215 { \
216 kCLOCK_Sdramc0 \
217 }
218
219 /*! @brief Clock ip name array for MPU. */
220 #define SYSMPU_CLOCKS \
221 { \
222 kCLOCK_Sysmpu0 \
223 }
224
225 /*! @brief Clock ip name array for VREF. */
226 #define VREF_CLOCKS \
227 { \
228 kCLOCK_Vref0 \
229 }
230
231 /*! @brief Clock ip name array for CMT. */
232 #define CMT_CLOCKS \
233 { \
234 kCLOCK_Cmt0 \
235 }
236
237 /*! @brief Clock ip name array for UART. */
238 #define UART_CLOCKS \
239 { \
240 kCLOCK_Uart0, kCLOCK_Uart1, kCLOCK_Uart2, kCLOCK_Uart3, kCLOCK_Uart4 \
241 }
242
243 /*! @brief Clock ip name array for TPM. */
244 #define TPM_CLOCKS \
245 { \
246 kCLOCK_IpInvalid, kCLOCK_Tpm1, kCLOCK_Tpm2 \
247 }
248
249 /*! @brief Clock ip name array for RNGA. */
250 #define RNGA_CLOCKS \
251 { \
252 kCLOCK_Rnga0 \
253 }
254
255 /*! @brief Clock ip name array for CRC. */
256 #define CRC_CLOCKS \
257 { \
258 kCLOCK_Crc0 \
259 }
260
261 /*! @brief Clock ip name array for I2C. */
262 #define I2C_CLOCKS \
263 { \
264 kCLOCK_I2c0, kCLOCK_I2c1, kCLOCK_I2c2, kCLOCK_I2c3 \
265 }
266
267 /*! @brief Clock ip name array for PDB. */
268 #define PDB_CLOCKS \
269 { \
270 kCLOCK_Pdb0 \
271 }
272
273 /*! @brief Clock ip name array for FTF. */
274 #define FTF_CLOCKS \
275 { \
276 kCLOCK_Ftf0 \
277 }
278
279 /*! @brief Clock ip name array for CMP. */
280 #define CMP_CLOCKS \
281 { \
282 kCLOCK_Cmp0, kCLOCK_Cmp1, kCLOCK_Cmp2, kCLOCK_Cmp3 \
283 }
284
285 /*!
286 * @brief LPO clock frequency.
287 */
288 #define LPO_CLK_FREQ 1000U
289
290 /*! @brief Peripherals clock source definition. */
291 #define SYS_CLK kCLOCK_CoreSysClk
292 #define BUS_CLK kCLOCK_BusClk
293
294 #define I2C0_CLK_SRC BUS_CLK
295 #define I2C1_CLK_SRC BUS_CLK
296 #define I2C2_CLK_SRC BUS_CLK
297 #define I2C3_CLK_SRC BUS_CLK
298 #define DSPI0_CLK_SRC BUS_CLK
299 #define DSPI1_CLK_SRC BUS_CLK
300 #define DSPI2_CLK_SRC BUS_CLK
301 #define UART0_CLK_SRC SYS_CLK
302 #define UART1_CLK_SRC SYS_CLK
303 #define UART2_CLK_SRC BUS_CLK
304 #define UART3_CLK_SRC BUS_CLK
305 #define UART4_CLK_SRC BUS_CLK
306
307 /*! @brief Clock name used to get clock frequency. */
308 typedef enum _clock_name
309 {
310
311 /* ----------------------------- System layer clock -------------------------------*/
312 kCLOCK_CoreSysClk, /*!< Core/system clock */
313 kCLOCK_PlatClk, /*!< Platform clock */
314 kCLOCK_BusClk, /*!< Bus clock */
315 kCLOCK_FlexBusClk, /*!< FlexBus clock */
316 kCLOCK_FlashClk, /*!< Flash clock */
317 kCLOCK_FastPeriphClk, /*!< Fast peripheral clock */
318 kCLOCK_PllFllSelClk, /*!< The clock after SIM[PLLFLLSEL]. */
319
320 /* ---------------------------------- OSC clock -----------------------------------*/
321 kCLOCK_Er32kClk, /*!< External reference 32K clock (ERCLK32K) */
322 kCLOCK_Osc0ErClk, /*!< OSC0 external reference clock (OSC0ERCLK) */
323 kCLOCK_Osc1ErClk, /*!< OSC1 external reference clock (OSC1ERCLK) */
324 kCLOCK_Osc0ErClkUndiv, /*!< OSC0 external reference undivided clock(OSC0ERCLK_UNDIV). */
325
326 /* ----------------------------- MCG and MCG-Lite clock ---------------------------*/
327 kCLOCK_McgFixedFreqClk, /*!< MCG fixed frequency clock (MCGFFCLK) */
328 kCLOCK_McgInternalRefClk, /*!< MCG internal reference clock (MCGIRCLK) */
329 kCLOCK_McgFllClk, /*!< MCGFLLCLK */
330 kCLOCK_McgPll0Clk, /*!< MCGPLL0CLK */
331 kCLOCK_McgPll1Clk, /*!< MCGPLL1CLK */
332 kCLOCK_McgExtPllClk, /*!< EXT_PLLCLK */
333 kCLOCK_McgPeriphClk, /*!< MCG peripheral clock (MCGPCLK) */
334 kCLOCK_McgIrc48MClk, /*!< MCG IRC48M clock */
335
336 /* --------------------------------- Other clock ----------------------------------*/
337 kCLOCK_LpoClk, /*!< LPO clock */
338
339 } clock_name_t;
340
341 /*! @brief USB clock source definition. */
342 typedef enum _clock_usb_src
343 {
344 kCLOCK_UsbSrcPll0 = SIM_SOPT2_USBSRC(1U) | SIM_SOPT2_PLLFLLSEL(1U), /*!< Use PLL0. */
345 kCLOCK_UsbSrcUsbPfd = SIM_SOPT2_USBSRC(1U) | SIM_SOPT2_PLLFLLSEL(2U), /*!< Use USBPFDCLK. */
346 kCLOCK_UsbSrcIrc48M = SIM_SOPT2_USBSRC(1U) | SIM_SOPT2_PLLFLLSEL(3U), /*!< Use IRC48M. */
347 kCLOCK_UsbSrcExt = SIM_SOPT2_USBSRC(0U), /*!< Use USB_CLKIN. */
348 kCLOCK_UsbSrcUnused = (int)0xFFFFFFFFU, /*!< Used when the function does not
349 care the clock source. */
350 } clock_usb_src_t;
351
352 /*! @brief Source of the USB HS PHY. */
353 typedef enum _clock_usb_phy_src
354 {
355 kCLOCK_UsbPhySrcExt = 0U, /*!< Use external crystal. */
356 } clock_usb_phy_src_t;
357
358 /*! @brief Source of the USB HS PFD clock (USB1PFDCLK) */
359 typedef enum _clock_usb_pfd_src
360 {
361 kCLOCK_UsbPfdSrcExt = 0U, /*!< Use external crystal. */
362 kCLOCK_UsbPfdSrcFracDivBy4 = 1U, /*!< Use PFD_FRAC output divided by 4. */
363 kCLOCK_UsbPfdSrcFracDivBy2 = 2U, /*!< Use PFD_FRAC output divided by 2. */
364 kCLOCK_UsbPfdSrcFrac = 3U, /*!< Use PFD_FRAC output. */
365 } clock_usb_pfd_src_t;
366
367 /*------------------------------------------------------------------------------
368
369 clock_gate_t definition:
370
371 31 16 0
372 -----------------------------------------------------------------
373 | SIM_SCGC register offset | control bit offset in SCGC |
374 -----------------------------------------------------------------
375
376 For example, the SDHC clock gate is controlled by SIM_SCGC3[17], the
377 SIM_SCGC3 offset in SIM is 0x1030, then kClockGateSdhc0 is defined as
378
379 kClockGateSdhc0 = (0x1030 << 16) | 17;
380
381 ------------------------------------------------------------------------------*/
382
383 #define CLK_GATE_REG_OFFSET_SHIFT 16U
384 #define CLK_GATE_REG_OFFSET_MASK 0xFFFF0000U
385 #define CLK_GATE_BIT_SHIFT_SHIFT 0U
386 #define CLK_GATE_BIT_SHIFT_MASK 0x0000FFFFU
387
388 #define CLK_GATE_DEFINE(reg_offset, bit_shift) \
389 ((((reg_offset) << CLK_GATE_REG_OFFSET_SHIFT) & CLK_GATE_REG_OFFSET_MASK) | \
390 (((bit_shift) << CLK_GATE_BIT_SHIFT_SHIFT) & CLK_GATE_BIT_SHIFT_MASK))
391
392 #define CLK_GATE_ABSTRACT_REG_OFFSET(x) (((x)&CLK_GATE_REG_OFFSET_MASK) >> CLK_GATE_REG_OFFSET_SHIFT)
393 #define CLK_GATE_ABSTRACT_BITS_SHIFT(x) (((x)&CLK_GATE_BIT_SHIFT_MASK) >> CLK_GATE_BIT_SHIFT_SHIFT)
394
395 /*! @brief Clock gate name used for CLOCK_EnableClock/CLOCK_DisableClock. */
396 typedef enum _clock_ip_name
397 {
398 kCLOCK_IpInvalid = 0U,
399 kCLOCK_I2c2 = CLK_GATE_DEFINE(0x1028U, 6U),
400 kCLOCK_I2c3 = CLK_GATE_DEFINE(0x1028U, 7U),
401 kCLOCK_Uart4 = CLK_GATE_DEFINE(0x1028U, 10U),
402
403 kCLOCK_Enet0 = CLK_GATE_DEFINE(0x102CU, 0U),
404 kCLOCK_Lpuart0 = CLK_GATE_DEFINE(0x102CU, 4U),
405 kCLOCK_Tpm1 = CLK_GATE_DEFINE(0x102CU, 9U),
406 kCLOCK_Tpm2 = CLK_GATE_DEFINE(0x102CU, 10U),
407 kCLOCK_Dac0 = CLK_GATE_DEFINE(0x102CU, 12U),
408 kCLOCK_Dac1 = CLK_GATE_DEFINE(0x102CU, 13U),
409
410 kCLOCK_Rnga0 = CLK_GATE_DEFINE(0x1030U, 0U),
411 kCLOCK_Usbhs0 = CLK_GATE_DEFINE(0x1030U, 1U),
412 kCLOCK_UsbhsPhy0 = CLK_GATE_DEFINE(0x1030U, 2U),
413 kCLOCK_UsbhsDcd0 = CLK_GATE_DEFINE(0x1030U, 3U),
414 kCLOCK_Flexcan1 = CLK_GATE_DEFINE(0x1030U, 4U),
415 kCLOCK_Spi2 = CLK_GATE_DEFINE(0x1030U, 12U),
416 kCLOCK_Sdhc0 = CLK_GATE_DEFINE(0x1030U, 17U),
417 kCLOCK_Ftm3 = CLK_GATE_DEFINE(0x1030U, 25U),
418 kCLOCK_Adc1 = CLK_GATE_DEFINE(0x1030U, 27U),
419
420 kCLOCK_Ewm0 = CLK_GATE_DEFINE(0x1034U, 1U),
421 kCLOCK_Cmt0 = CLK_GATE_DEFINE(0x1034U, 2U),
422 kCLOCK_I2c0 = CLK_GATE_DEFINE(0x1034U, 6U),
423 kCLOCK_I2c1 = CLK_GATE_DEFINE(0x1034U, 7U),
424 kCLOCK_Uart0 = CLK_GATE_DEFINE(0x1034U, 10U),
425 kCLOCK_Uart1 = CLK_GATE_DEFINE(0x1034U, 11U),
426 kCLOCK_Uart2 = CLK_GATE_DEFINE(0x1034U, 12U),
427 kCLOCK_Uart3 = CLK_GATE_DEFINE(0x1034U, 13U),
428 kCLOCK_Usbfs0 = CLK_GATE_DEFINE(0x1034U, 18U),
429 kCLOCK_Cmp0 = CLK_GATE_DEFINE(0x1034U, 19U),
430 kCLOCK_Cmp1 = CLK_GATE_DEFINE(0x1034U, 19U),
431 kCLOCK_Cmp2 = CLK_GATE_DEFINE(0x1034U, 19U),
432 kCLOCK_Cmp3 = CLK_GATE_DEFINE(0x1034U, 19U),
433 kCLOCK_Vref0 = CLK_GATE_DEFINE(0x1034U, 20U),
434
435 kCLOCK_Lptmr0 = CLK_GATE_DEFINE(0x1038U, 0U),
436 kCLOCK_Tsi0 = CLK_GATE_DEFINE(0x1038U, 5U),
437 kCLOCK_PortA = CLK_GATE_DEFINE(0x1038U, 9U),
438 kCLOCK_PortB = CLK_GATE_DEFINE(0x1038U, 10U),
439 kCLOCK_PortC = CLK_GATE_DEFINE(0x1038U, 11U),
440 kCLOCK_PortD = CLK_GATE_DEFINE(0x1038U, 12U),
441 kCLOCK_PortE = CLK_GATE_DEFINE(0x1038U, 13U),
442
443 kCLOCK_Ftf0 = CLK_GATE_DEFINE(0x103CU, 0U),
444 kCLOCK_Dmamux0 = CLK_GATE_DEFINE(0x103CU, 1U),
445 kCLOCK_Flexcan0 = CLK_GATE_DEFINE(0x103CU, 4U),
446 kCLOCK_Spi0 = CLK_GATE_DEFINE(0x103CU, 12U),
447 kCLOCK_Spi1 = CLK_GATE_DEFINE(0x103CU, 13U),
448 kCLOCK_Sai0 = CLK_GATE_DEFINE(0x103CU, 15U),
449 kCLOCK_Crc0 = CLK_GATE_DEFINE(0x103CU, 18U),
450 kCLOCK_Usbdcd0 = CLK_GATE_DEFINE(0x103CU, 21U),
451 kCLOCK_Pdb0 = CLK_GATE_DEFINE(0x103CU, 22U),
452 kCLOCK_Pit0 = CLK_GATE_DEFINE(0x103CU, 23U),
453 kCLOCK_Ftm0 = CLK_GATE_DEFINE(0x103CU, 24U),
454 kCLOCK_Ftm1 = CLK_GATE_DEFINE(0x103CU, 25U),
455 kCLOCK_Ftm2 = CLK_GATE_DEFINE(0x103CU, 26U),
456 kCLOCK_Adc0 = CLK_GATE_DEFINE(0x103CU, 27U),
457 kCLOCK_Rtc0 = CLK_GATE_DEFINE(0x103CU, 29U),
458
459 kCLOCK_Flexbus0 = CLK_GATE_DEFINE(0x1040U, 0U),
460 kCLOCK_Dma0 = CLK_GATE_DEFINE(0x1040U, 1U),
461 kCLOCK_Sysmpu0 = CLK_GATE_DEFINE(0x1040U, 2U),
462 kCLOCK_Sdramc0 = CLK_GATE_DEFINE(0x1040U, 3U),
463 } clock_ip_name_t;
464
465 /*!@brief SIM configuration structure for clock setting. */
466 typedef struct _sim_clock_config
467 {
468 uint8_t pllFllSel; /*!< PLL/FLL/IRC48M selection. */
469 uint8_t pllFllDiv; /*!< PLLFLLSEL clock divider divisor. */
470 uint8_t pllFllFrac; /*!< PLLFLLSEL clock divider fraction. */
471 uint8_t er32kSrc; /*!< ERCLK32K source selection. */
472 uint32_t clkdiv1; /*!< SIM_CLKDIV1. */
473 } sim_clock_config_t;
474
475 /*! @brief OSC work mode. */
476 typedef enum _osc_mode
477 {
478 kOSC_ModeExt = 0U, /*!< Use an external clock. */
479 #if (defined(MCG_C2_EREFS_MASK) && !(defined(MCG_C2_EREFS0_MASK)))
480 kOSC_ModeOscLowPower = MCG_C2_EREFS_MASK, /*!< Oscillator low power. */
481 #else
482 kOSC_ModeOscLowPower = MCG_C2_EREFS0_MASK, /*!< Oscillator low power. */
483 #endif
484 kOSC_ModeOscHighGain = 0U
485 #if (defined(MCG_C2_EREFS_MASK) && !(defined(MCG_C2_EREFS0_MASK)))
486 | MCG_C2_EREFS_MASK
487 #else
488 | MCG_C2_EREFS0_MASK
489 #endif
490 #if (defined(MCG_C2_HGO_MASK) && !(defined(MCG_C2_HGO0_MASK)))
491 | MCG_C2_HGO_MASK, /*!< Oscillator high gain. */
492 #else
493 | MCG_C2_HGO0_MASK, /*!< Oscillator high gain. */
494 #endif
495 } osc_mode_t;
496
497 /*! @brief Oscillator capacitor load setting.*/
498 enum _osc_cap_load
499 {
500 kOSC_Cap2P = OSC_CR_SC2P_MASK, /*!< 2 pF capacitor load */
501 kOSC_Cap4P = OSC_CR_SC4P_MASK, /*!< 4 pF capacitor load */
502 kOSC_Cap8P = OSC_CR_SC8P_MASK, /*!< 8 pF capacitor load */
503 kOSC_Cap16P = OSC_CR_SC16P_MASK /*!< 16 pF capacitor load */
504 };
505
506 /*! @brief OSCERCLK enable mode. */
507 enum _oscer_enable_mode
508 {
509 kOSC_ErClkEnable = OSC_CR_ERCLKEN_MASK, /*!< Enable. */
510 kOSC_ErClkEnableInStop = OSC_CR_EREFSTEN_MASK /*!< Enable in stop mode. */
511 };
512
513 /*! @brief OSC configuration for OSCERCLK. */
514 typedef struct _oscer_config
515 {
516 uint8_t enableMode; /*!< OSCERCLK enable mode. OR'ed value of @ref _oscer_enable_mode. */
517
518 uint8_t erclkDiv; /*!< Divider for OSCERCLK.*/
519 } oscer_config_t;
520
521 /*!
522 * @brief OSC Initialization Configuration Structure
523 *
524 * Defines the configuration data structure to initialize the OSC.
525 * When porting to a new board, set the following members
526 * according to the board setting:
527 * 1. freq: The external frequency.
528 * 2. workMode: The OSC module mode.
529 */
530 typedef struct _osc_config
531 {
532 uint32_t freq; /*!< External clock frequency. */
533 uint8_t capLoad; /*!< Capacitor load setting. */
534 osc_mode_t workMode; /*!< OSC work mode setting. */
535 oscer_config_t oscerConfig; /*!< Configuration for OSCERCLK. */
536 } osc_config_t;
537
538 /*! @brief MCG FLL reference clock source select. */
539 typedef enum _mcg_fll_src
540 {
541 kMCG_FllSrcExternal, /*!< External reference clock is selected */
542 kMCG_FllSrcInternal /*!< The slow internal reference clock is selected */
543 } mcg_fll_src_t;
544
545 /*! @brief MCG internal reference clock select */
546 typedef enum _mcg_irc_mode
547 {
548 kMCG_IrcSlow, /*!< Slow internal reference clock selected */
549 kMCG_IrcFast /*!< Fast internal reference clock selected */
550 } mcg_irc_mode_t;
551
552 /*! @brief MCG DCO Maximum Frequency with 32.768 kHz Reference */
553 typedef enum _mcg_dmx32
554 {
555 kMCG_Dmx32Default, /*!< DCO has a default range of 25% */
556 kMCG_Dmx32Fine /*!< DCO is fine-tuned for maximum frequency with 32.768 kHz reference */
557 } mcg_dmx32_t;
558
559 /*! @brief MCG DCO range select */
560 typedef enum _mcg_drs
561 {
562 kMCG_DrsLow, /*!< Low frequency range */
563 kMCG_DrsMid, /*!< Mid frequency range */
564 kMCG_DrsMidHigh, /*!< Mid-High frequency range */
565 kMCG_DrsHigh /*!< High frequency range */
566 } mcg_drs_t;
567
568 /*! @brief MCG PLL reference clock select */
569 typedef enum _mcg_pll_ref_src
570 {
571 kMCG_PllRefOsc0, /*!< Selects OSC0 as PLL reference clock */
572 kMCG_PllRefOsc1 /*!< Selects OSC1 as PLL reference clock */
573 } mcg_pll_ref_src_t;
574
575 /*! @brief MCGOUT clock source. */
576 typedef enum _mcg_clkout_src
577 {
578 kMCG_ClkOutSrcOut, /*!< Output of the FLL is selected (reset default) */
579 kMCG_ClkOutSrcInternal, /*!< Internal reference clock is selected */
580 kMCG_ClkOutSrcExternal, /*!< External reference clock is selected */
581 } mcg_clkout_src_t;
582
583 /*! @brief MCG Automatic Trim Machine Select */
584 typedef enum _mcg_atm_select
585 {
586 kMCG_AtmSel32k, /*!< 32 kHz Internal Reference Clock selected */
587 kMCG_AtmSel4m /*!< 4 MHz Internal Reference Clock selected */
588 } mcg_atm_select_t;
589
590 /*! @brief MCG OSC Clock Select */
591 typedef enum _mcg_oscsel
592 {
593 kMCG_OscselOsc, /*!< Selects System Oscillator (OSCCLK) */
594 kMCG_OscselRtc, /*!< Selects 32 kHz RTC Oscillator */
595 kMCG_OscselIrc /*!< Selects 48 MHz IRC Oscillator */
596 } mcg_oscsel_t;
597
598 /*! @brief MCG PLLCS select */
599 typedef enum _mcg_pll_clk_select
600 {
601 kMCG_PllClkSelPll0, /*!< PLL0 output clock is selected */
602 kMCG_PllClkSelExtPll /* The external PLL clock is selected */
603 } mcg_pll_clk_select_t;
604
605 /*! @brief MCG clock monitor mode. */
606 typedef enum _mcg_monitor_mode
607 {
608 kMCG_MonitorNone, /*!< Clock monitor is disabled. */
609 kMCG_MonitorInt, /*!< Trigger interrupt when clock lost. */
610 kMCG_MonitorReset /*!< System reset when clock lost. */
611 } mcg_monitor_mode_t;
612
613 /*! @brief MCG status. Enumeration _mcg_status */
614 enum
615 {
616 kStatus_MCG_ModeUnreachable = MAKE_STATUS(kStatusGroup_MCG, 0U), /*!< Can't switch to target mode. */
617 kStatus_MCG_ModeInvalid = MAKE_STATUS(kStatusGroup_MCG, 1U), /*!< Current mode invalid for the specific
618 function. */
619 kStatus_MCG_AtmBusClockInvalid = MAKE_STATUS(kStatusGroup_MCG, 2U), /*!< Invalid bus clock for ATM. */
620 kStatus_MCG_AtmDesiredFreqInvalid = MAKE_STATUS(kStatusGroup_MCG, 3U), /*!< Invalid desired frequency for ATM. */
621 kStatus_MCG_AtmIrcUsed = MAKE_STATUS(kStatusGroup_MCG, 4U), /*!< IRC is used when using ATM. */
622 kStatus_MCG_AtmHardwareFail = MAKE_STATUS(kStatusGroup_MCG, 5U), /*!< Hardware fail occurs during ATM. */
623 kStatus_MCG_SourceUsed = MAKE_STATUS(kStatusGroup_MCG, 6U) /*!< Can't change the clock source because
624 it is in use. */
625 };
626
627 /*! @brief MCG status flags. Enumeration _mcg_status_flags_t */
628 enum
629 {
630 kMCG_Osc0LostFlag = (1U << 0U), /*!< OSC0 lost. */
631 kMCG_Osc0InitFlag = (1U << 1U), /*!< OSC0 crystal initialized. */
632 kMCG_RtcOscLostFlag = (1U << 4U), /*!< RTC OSC lost. */
633 kMCG_Pll0LostFlag = (1U << 5U), /*!< PLL0 lost. */
634 kMCG_Pll0LockFlag = (1U << 6U), /*!< PLL0 locked. */
635 kMCG_ExtPllLostFlag = (1U << 9U), /*!< External PLL lost. */
636 };
637
638 /*! @brief MCG internal reference clock (MCGIRCLK) enable mode definition. Enumeration _mcg_irclk_enable_mode */
639 enum
640 {
641 kMCG_IrclkEnable = MCG_C1_IRCLKEN_MASK, /*!< MCGIRCLK enable. */
642 kMCG_IrclkEnableInStop = MCG_C1_IREFSTEN_MASK /*!< MCGIRCLK enable in stop mode. */
643 };
644
645 /*! @brief MCG PLL clock enable mode definition. Enumeration _mcg_pll_enable_mode */
646 enum
647 {
648 kMCG_PllEnableIndependent = MCG_C5_PLLCLKEN0_MASK, /*!< MCGPLLCLK enable independent of the
649 MCG clock mode. Generally, the PLL
650 is disabled in FLL modes
651 (FEI/FBI/FEE/FBE). Setting the PLL clock
652 enable independent, enables the
653 PLL in the FLL modes. */
654 kMCG_PllEnableInStop = MCG_C5_PLLSTEN0_MASK /*!< MCGPLLCLK enable in STOP mode. */
655 };
656
657 /*! @brief MCG mode definitions */
658 typedef enum _mcg_mode
659 {
660 kMCG_ModeFEI = 0U, /*!< FEI - FLL Engaged Internal */
661 kMCG_ModeFBI, /*!< FBI - FLL Bypassed Internal */
662 kMCG_ModeBLPI, /*!< BLPI - Bypassed Low Power Internal */
663 kMCG_ModeFEE, /*!< FEE - FLL Engaged External */
664 kMCG_ModeFBE, /*!< FBE - FLL Bypassed External */
665 kMCG_ModeBLPE, /*!< BLPE - Bypassed Low Power External */
666 kMCG_ModePBE, /*!< PBE - PLL Bypassed External */
667 kMCG_ModePEE, /*!< PEE - PLL Engaged External */
668 kMCG_ModeError /*!< Unknown mode */
669 } mcg_mode_t;
670
671 /*! @brief MCG PLL configuration. */
672 typedef struct _mcg_pll_config
673 {
674 uint8_t enableMode; /*!< Enable mode. OR'ed value of enumeration _mcg_pll_enable_mode. */
675 uint8_t prdiv; /*!< Reference divider PRDIV. */
676 uint8_t vdiv; /*!< VCO divider VDIV. */
677 } mcg_pll_config_t;
678
679 /*! @brief MCG mode change configuration structure
680 *
681 * When porting to a new board, set the following members
682 * according to the board setting:
683 * 1. frdiv: If the FLL uses the external reference clock, set this
684 * value to ensure that the external reference clock divided by frdiv is
685 * in the 31.25 kHz to 39.0625 kHz range.
686 * 2. The PLL reference clock divider PRDIV: PLL reference clock frequency after
687 * PRDIV should be in the FSL_FEATURE_MCG_PLL_REF_MIN to
688 * FSL_FEATURE_MCG_PLL_REF_MAX range.
689 */
690 typedef struct _mcg_config
691 {
692 mcg_mode_t mcgMode; /*!< MCG mode. */
693
694 /* ----------------------- MCGIRCCLK settings ------------------------ */
695 uint8_t irclkEnableMode; /*!< MCGIRCLK enable mode. */
696 mcg_irc_mode_t ircs; /*!< Source, MCG_C2[IRCS]. */
697 uint8_t fcrdiv; /*!< Divider, MCG_SC[FCRDIV]. */
698
699 /* ------------------------ MCG FLL settings ------------------------- */
700 uint8_t frdiv; /*!< Divider MCG_C1[FRDIV]. */
701 mcg_drs_t drs; /*!< DCO range MCG_C4[DRST_DRS]. */
702 mcg_dmx32_t dmx32; /*!< MCG_C4[DMX32]. */
703 mcg_oscsel_t oscsel; /*!< OSC select MCG_C7[OSCSEL]. */
704
705 /* ------------------------ MCG PLL settings ------------------------- */
706 mcg_pll_config_t pll0Config; /*!< MCGPLL0CLK configuration. */
707
708 mcg_pll_clk_select_t pllcs; /*!< PLL select as output, PLLCS.*/
709
710 } mcg_config_t;
711
712 /*******************************************************************************
713 * API
714 ******************************************************************************/
715
716 #if defined(__cplusplus)
717 extern "C" {
718 #endif /* __cplusplus */
719
720 /*!
721 * @brief Enable the clock for specific IP.
722 *
723 * @param name Which clock to enable, see \ref clock_ip_name_t.
724 */
CLOCK_EnableClock(clock_ip_name_t name)725 static inline void CLOCK_EnableClock(clock_ip_name_t name)
726 {
727 uint32_t regAddr = SIM_BASE + CLK_GATE_ABSTRACT_REG_OFFSET((uint32_t)name);
728 (*(volatile uint32_t *)regAddr) |= (1UL << CLK_GATE_ABSTRACT_BITS_SHIFT((uint32_t)name));
729 }
730
731 /*!
732 * @brief Disable the clock for specific IP.
733 *
734 * @param name Which clock to disable, see \ref clock_ip_name_t.
735 */
CLOCK_DisableClock(clock_ip_name_t name)736 static inline void CLOCK_DisableClock(clock_ip_name_t name)
737 {
738 uint32_t regAddr = SIM_BASE + CLK_GATE_ABSTRACT_REG_OFFSET((uint32_t)name);
739 (*(volatile uint32_t *)regAddr) &= ~(1UL << CLK_GATE_ABSTRACT_BITS_SHIFT((uint32_t)name));
740 }
741
742 /*!
743 * @brief Set ERCLK32K source.
744 *
745 * @param src The value to set ERCLK32K clock source.
746 */
CLOCK_SetEr32kClock(uint32_t src)747 static inline void CLOCK_SetEr32kClock(uint32_t src)
748 {
749 SIM->SOPT1 = ((SIM->SOPT1 & ~SIM_SOPT1_OSC32KSEL_MASK) | SIM_SOPT1_OSC32KSEL(src));
750 }
751
752 /*!
753 * @brief Set SDHC0 clock source.
754 *
755 * @param src The value to set SDHC0 clock source.
756 */
CLOCK_SetSdhc0Clock(uint32_t src)757 static inline void CLOCK_SetSdhc0Clock(uint32_t src)
758 {
759 SIM->SOPT2 = ((SIM->SOPT2 & ~SIM_SOPT2_SDHCSRC_MASK) | SIM_SOPT2_SDHCSRC(src));
760 }
761
762 /*!
763 * @brief Set enet timestamp clock source.
764 *
765 * @param src The value to set enet timestamp clock source.
766 */
CLOCK_SetEnetTime0Clock(uint32_t src)767 static inline void CLOCK_SetEnetTime0Clock(uint32_t src)
768 {
769 SIM->SOPT2 = ((SIM->SOPT2 & ~SIM_SOPT2_TIMESRC_MASK) | SIM_SOPT2_TIMESRC(src));
770 }
771
772 /*!
773 * @brief Set RMII clock source.
774 *
775 * @param src The value to set RMII clock source.
776 */
CLOCK_SetRmii0Clock(uint32_t src)777 static inline void CLOCK_SetRmii0Clock(uint32_t src)
778 {
779 SIM->SOPT2 = ((SIM->SOPT2 & ~SIM_SOPT2_RMIISRC_MASK) | SIM_SOPT2_RMIISRC(src));
780 }
781
782 /*!
783 * @brief Set LPUART clock source.
784 *
785 * @param src The value to set LPUART clock source.
786 */
CLOCK_SetLpuartClock(uint32_t src)787 static inline void CLOCK_SetLpuartClock(uint32_t src)
788 {
789 SIM->SOPT2 = ((SIM->SOPT2 & ~SIM_SOPT2_LPUARTSRC_MASK) | SIM_SOPT2_LPUARTSRC(src));
790 }
791
792 /*!
793 * @brief Set TPM clock source.
794 *
795 * @param src The value to set TPM clock source.
796 */
CLOCK_SetTpmClock(uint32_t src)797 static inline void CLOCK_SetTpmClock(uint32_t src)
798 {
799 SIM->SOPT2 = ((SIM->SOPT2 & ~SIM_SOPT2_TPMSRC_MASK) | SIM_SOPT2_TPMSRC(src));
800 }
801
802 /*!
803 * @brief Set debug trace clock source.
804 *
805 * @param src The value to set debug trace clock source.
806 * @param divValue PLLFLL clock divider divisor.
807 * @param fracValue PLLFLL clock divider fraction.
808 */
CLOCK_SetTraceClock(uint32_t src,uint32_t divValue,uint32_t fracValue)809 static inline void CLOCK_SetTraceClock(uint32_t src, uint32_t divValue, uint32_t fracValue)
810 {
811 SIM->SOPT2 = ((SIM->SOPT2 & ~SIM_SOPT2_TRACECLKSEL_MASK) | SIM_SOPT2_TRACECLKSEL(src));
812 SIM->CLKDIV4 = SIM_CLKDIV4_TRACEDIV(divValue) | SIM_CLKDIV4_TRACEFRAC(fracValue);
813 }
814
815 /*!
816 * @brief Set PLLFLLSEL clock source.
817 *
818 * @param src The value to set PLLFLLSEL clock source.
819 * @param divValue PLLFLL clock divider divisor.
820 * @param fracValue PLLFLL clock divider fraction.
821 */
CLOCK_SetPllFllSelClock(uint32_t src,uint32_t divValue,uint32_t fracValue)822 static inline void CLOCK_SetPllFllSelClock(uint32_t src, uint32_t divValue, uint32_t fracValue)
823 {
824 SIM->SOPT2 = ((SIM->SOPT2 & ~SIM_SOPT2_PLLFLLSEL_MASK) | SIM_SOPT2_PLLFLLSEL(src));
825 SIM->CLKDIV3 = SIM_CLKDIV3_PLLFLLDIV(divValue) | SIM_CLKDIV3_PLLFLLFRAC(fracValue);
826 }
827
828 /*!
829 * @brief Set CLKOUT source.
830 *
831 * @param src The value to set CLKOUT source.
832 */
CLOCK_SetClkOutClock(uint32_t src)833 static inline void CLOCK_SetClkOutClock(uint32_t src)
834 {
835 SIM->SOPT2 = ((SIM->SOPT2 & ~SIM_SOPT2_CLKOUTSEL_MASK) | SIM_SOPT2_CLKOUTSEL(src));
836 }
837
838 /*!
839 * @brief Set RTC_CLKOUT source.
840 *
841 * @param src The value to set RTC_CLKOUT source.
842 */
CLOCK_SetRtcClkOutClock(uint32_t src)843 static inline void CLOCK_SetRtcClkOutClock(uint32_t src)
844 {
845 SIM->SOPT2 = ((SIM->SOPT2 & ~SIM_SOPT2_RTCCLKOUTSEL_MASK) | SIM_SOPT2_RTCCLKOUTSEL(src));
846 }
847
848 /*! @brief Enable USB HS clock.
849 *
850 * This function only enables the access to USB HS prepheral, upper layer
851 * should first call the @ref CLOCK_EnableUsbhs0PhyPllClock to enable the PHY
852 * clock to use USB HS.
853 *
854 * @param src USB HS does not care about the clock source, here must be @ref kCLOCK_UsbSrcUnused.
855 * @param freq USB HS does not care about the clock source, so this parameter is ignored.
856 * @retval true The clock is set successfully.
857 * @retval false The clock source is invalid to get proper USB HS clock.
858 */
859 bool CLOCK_EnableUsbhs0Clock(clock_usb_src_t src, uint32_t freq);
860
861 /*! @brief Disable USB HS clock.
862 *
863 * Disable USB HS clock, this function should not be called after
864 * @ref CLOCK_DisableUsbhs0PhyPllClock.
865 */
866 void CLOCK_DisableUsbhs0Clock(void);
867
868 /*! @brief Enable USB HS PHY PLL clock.
869 *
870 * This function enables the internal 480MHz USB PHY PLL clock.
871 *
872 * @param src USB HS PHY PLL clock source.
873 * @param freq The frequency specified by src.
874 * @retval true The clock is set successfully.
875 * @retval false The clock source is invalid to get proper USB HS clock.
876 */
877 bool CLOCK_EnableUsbhs0PhyPllClock(clock_usb_phy_src_t src, uint32_t freq);
878
879 /*! @brief Disable USB HS PHY PLL clock.
880 *
881 * This function disables USB HS PHY PLL clock.
882 */
883 void CLOCK_DisableUsbhs0PhyPllClock(void);
884
885 /*! @brief Enable USB HS PFD clock.
886 *
887 * This function enables USB HS PFD clock. It should be called after function
888 * @ref CLOCK_EnableUsbhs0PhyPllClock.
889 * The PFD output clock is selected by the parameter @p src. When the @p src is
890 * @ref kCLOCK_UsbPfdSrcExt, then the PFD outout is from external crystal
891 * directly, in this case, the @p frac is not used. In other cases, the PFD_FRAC
892 * output clock frequency is 480MHz*18/frac, the PFD output frequency is based
893 * on the PFD_FRAC output.
894 *
895 * @param frac The value set to PFD_FRAC, it must be in the range of 18 to 35.
896 * @param src Source of the USB HS PFD clock (USB1PFDCLK).
897 */
898 void CLOCK_EnableUsbhs0PfdClock(uint8_t frac, clock_usb_pfd_src_t src);
899
900 /*! @brief Disable USB HS PFD clock.
901 *
902 * This function disables USB HS PFD clock. It should be called before function
903 * @ref CLOCK_DisableUsbhs0PhyPllClock.
904 */
905 void CLOCK_DisableUsbhs0PfdClock(void);
906
907 /*! @brief Enable USB FS clock.
908 *
909 * @param src USB FS clock source.
910 * @param freq The frequency specified by src.
911 * @retval true The clock is set successfully.
912 * @retval false The clock source is invalid to get proper USB FS clock.
913 */
914 bool CLOCK_EnableUsbfs0Clock(clock_usb_src_t src, uint32_t freq);
915
916 /*! @brief Disable USB FS clock.
917 *
918 * Disable USB FS clock.
919 */
CLOCK_DisableUsbfs0Clock(void)920 static inline void CLOCK_DisableUsbfs0Clock(void)
921 {
922 CLOCK_DisableClock(kCLOCK_Usbfs0);
923 }
924
925 /*!
926 * @brief System clock divider
927 *
928 * Set the SIM_CLKDIV1[OUTDIV1], SIM_CLKDIV1[OUTDIV2], SIM_CLKDIV1[OUTDIV3], SIM_CLKDIV1[OUTDIV4].
929 *
930 * @param outdiv1 Clock 1 output divider value.
931 *
932 * @param outdiv2 Clock 2 output divider value.
933 *
934 * @param outdiv3 Clock 3 output divider value.
935 *
936 * @param outdiv4 Clock 4 output divider value.
937 */
CLOCK_SetOutDiv(uint32_t outdiv1,uint32_t outdiv2,uint32_t outdiv3,uint32_t outdiv4)938 static inline void CLOCK_SetOutDiv(uint32_t outdiv1, uint32_t outdiv2, uint32_t outdiv3, uint32_t outdiv4)
939 {
940 SIM->CLKDIV1 = SIM_CLKDIV1_OUTDIV1(outdiv1) | SIM_CLKDIV1_OUTDIV2(outdiv2) | SIM_CLKDIV1_OUTDIV3(outdiv3) |
941 SIM_CLKDIV1_OUTDIV4(outdiv4);
942 }
943
944 /*!
945 * @brief Gets the clock frequency for a specific clock name.
946 *
947 * This function checks the current clock configurations and then calculates
948 * the clock frequency for a specific clock name defined in clock_name_t.
949 * The MCG must be properly configured before using this function.
950 *
951 * @param clockName Clock names defined in clock_name_t
952 * @return Clock frequency value in Hertz
953 */
954 uint32_t CLOCK_GetFreq(clock_name_t clockName);
955
956 /*!
957 * @brief Get the core clock or system clock frequency.
958 *
959 * @return Clock frequency in Hz.
960 */
961 uint32_t CLOCK_GetCoreSysClkFreq(void);
962
963 /*!
964 * @brief Get the platform clock frequency.
965 *
966 * @return Clock frequency in Hz.
967 */
968 uint32_t CLOCK_GetPlatClkFreq(void);
969
970 /*!
971 * @brief Get the bus clock frequency.
972 *
973 * @return Clock frequency in Hz.
974 */
975 uint32_t CLOCK_GetBusClkFreq(void);
976
977 /*!
978 * @brief Get the flexbus clock frequency.
979 *
980 * @return Clock frequency in Hz.
981 */
982 uint32_t CLOCK_GetFlexBusClkFreq(void);
983
984 /*!
985 * @brief Get the flash clock frequency.
986 *
987 * @return Clock frequency in Hz.
988 */
989 uint32_t CLOCK_GetFlashClkFreq(void);
990
991 /*!
992 * @brief Get the output clock frequency selected by SIM[PLLFLLSEL].
993 *
994 * @return Clock frequency in Hz.
995 */
996 uint32_t CLOCK_GetPllFllSelClkFreq(void);
997
998 /*!
999 * @brief Get the external reference 32K clock frequency (ERCLK32K).
1000 *
1001 * @return Clock frequency in Hz.
1002 */
1003 uint32_t CLOCK_GetEr32kClkFreq(void);
1004
1005 /*!
1006 * @brief Get the OSC0 external reference clock frequency (OSC0ERCLK).
1007 *
1008 * @return Clock frequency in Hz.
1009 */
1010 uint32_t CLOCK_GetOsc0ErClkFreq(void);
1011
1012 /*!
1013 * @brief Get the OSC0 external reference divided clock frequency.
1014 *
1015 * @return Clock frequency in Hz.
1016 */
1017 uint32_t CLOCK_GetOsc0ErClkDivFreq(void);
1018
1019 /*!
1020 * @brief Get the OSC0 external reference undivided clock frequency (OSC0ERCLK_UNDIV).
1021 *
1022 * @return Clock frequency in Hz.
1023 */
1024 uint32_t CLOCK_GetOsc0ErClkUndivFreq(void);
1025
1026 /*!
1027 * @brief Set the clock configure in SIM module.
1028 *
1029 * This function sets system layer clock settings in SIM module.
1030 *
1031 * @param config Pointer to the configure structure.
1032 */
1033 void CLOCK_SetSimConfig(sim_clock_config_t const *config);
1034
1035 /*!
1036 * @brief Set the system clock dividers in SIM to safe value.
1037 *
1038 * The system level clocks (core clock, bus clock, flexbus clock and flash clock)
1039 * must be in allowed ranges. During MCG clock mode switch, the MCG output clock
1040 * changes then the system level clocks may be out of range. This function could
1041 * be used before MCG mode change, to make sure system level clocks are in allowed
1042 * range.
1043 *
1044 */
CLOCK_SetSimSafeDivs(void)1045 static inline void CLOCK_SetSimSafeDivs(void)
1046 {
1047 SIM->CLKDIV1 = 0x02260000U;
1048 }
1049
1050 /*! @name MCG frequency functions. */
1051 /*@{*/
1052
1053 /*!
1054 * @brief Gets the MCG output clock (MCGOUTCLK) frequency.
1055 *
1056 * This function gets the MCG output clock frequency in Hz based on the current MCG
1057 * register value.
1058 *
1059 * @return The frequency of MCGOUTCLK.
1060 */
1061 uint32_t CLOCK_GetOutClkFreq(void);
1062
1063 /*!
1064 * @brief Gets the MCG FLL clock (MCGFLLCLK) frequency.
1065 *
1066 * This function gets the MCG FLL clock frequency in Hz based on the current MCG
1067 * register value. The FLL is enabled in FEI/FBI/FEE/FBE mode and
1068 * disabled in low power state in other modes.
1069 *
1070 * @return The frequency of MCGFLLCLK.
1071 */
1072 uint32_t CLOCK_GetFllFreq(void);
1073
1074 /*!
1075 * @brief Gets the MCG internal reference clock (MCGIRCLK) frequency.
1076 *
1077 * This function gets the MCG internal reference clock frequency in Hz based
1078 * on the current MCG register value.
1079 *
1080 * @return The frequency of MCGIRCLK.
1081 */
1082 uint32_t CLOCK_GetInternalRefClkFreq(void);
1083
1084 /*!
1085 * @brief Gets the MCG fixed frequency clock (MCGFFCLK) frequency.
1086 *
1087 * This function gets the MCG fixed frequency clock frequency in Hz based
1088 * on the current MCG register value.
1089 *
1090 * @return The frequency of MCGFFCLK.
1091 */
1092 uint32_t CLOCK_GetFixedFreqClkFreq(void);
1093
1094 /*!
1095 * @brief Gets the MCG PLL0 clock (MCGPLL0CLK) frequency.
1096 *
1097 * This function gets the MCG PLL0 clock frequency in Hz based on the current MCG
1098 * register value.
1099 *
1100 * @return The frequency of MCGPLL0CLK.
1101 */
1102 uint32_t CLOCK_GetPll0Freq(void);
1103
1104 /*!
1105 * @brief Gets the MCG external PLL frequency.
1106 *
1107 * This function gets the MCG external PLL frequency in Hz.
1108 *
1109 * @return The frequency of the MCG external PLL.
1110 */
1111 uint32_t CLOCK_GetExtPllFreq(void);
1112
1113 /*!
1114 * @brief Sets the MCG external PLL frequency.
1115 *
1116 * This function sets the MCG external PLL frequency in Hz. The MCG external PLL
1117 * frequency is passed to the MCG driver using this function. Call this
1118 * function after the external PLL frequency is changed. Otherwise, the APIs, which are used to get
1119 * the frequency, may return an incorrect value.
1120 *
1121 * @param freq The frequency of MCG external PLL.
1122 */
1123 void CLOCK_SetExtPllFreq(uint32_t freq);
1124
1125 /*@}*/
1126
1127 /*! @name MCG clock configuration. */
1128 /*@{*/
1129
1130 /*!
1131 * @brief Enables or disables the MCG low power.
1132 *
1133 * Enabling the MCG low power disables the PLL and FLL in bypass modes. In other words,
1134 * in FBE and PBE modes, enabling low power sets the MCG to BLPE mode. In FBI and
1135 * PBI modes, enabling low power sets the MCG to BLPI mode.
1136 * When disabling the MCG low power, the PLL or FLL are enabled based on MCG settings.
1137 *
1138 * @param enable True to enable MCG low power, false to disable MCG low power.
1139 */
CLOCK_SetLowPowerEnable(bool enable)1140 static inline void CLOCK_SetLowPowerEnable(bool enable)
1141 {
1142 if (enable)
1143 {
1144 MCG->C2 |= MCG_C2_LP_MASK;
1145 }
1146 else
1147 {
1148 MCG->C2 &= ~(uint8_t)MCG_C2_LP_MASK;
1149 }
1150 }
1151
1152 /*!
1153 * @brief Configures the Internal Reference clock (MCGIRCLK).
1154 *
1155 * This function sets the \c MCGIRCLK base on parameters. It also selects the IRC
1156 * source. If the fast IRC is used, this function sets the fast IRC divider.
1157 * This function also sets whether the \c MCGIRCLK is enabled in stop mode.
1158 * Calling this function in FBI/PBI/BLPI modes may change the system clock. As a result,
1159 * using the function in these modes it is not allowed.
1160 *
1161 * @param enableMode MCGIRCLK enable mode, OR'ed value of the enumeration _mcg_irclk_enable_mode.
1162 * @param ircs MCGIRCLK clock source, choose fast or slow.
1163 * @param fcrdiv Fast IRC divider setting (\c FCRDIV).
1164 * @retval kStatus_MCG_SourceUsed Because the internal reference clock is used as a clock source,
1165 * the configuration should not be changed. Otherwise, a glitch occurs.
1166 * @retval kStatus_Success MCGIRCLK configuration finished successfully.
1167 */
1168 status_t CLOCK_SetInternalRefClkConfig(uint8_t enableMode, mcg_irc_mode_t ircs, uint8_t fcrdiv);
1169
1170 /*!
1171 * @brief Selects the MCG external reference clock.
1172 *
1173 * Selects the MCG external reference clock source, changes the MCG_C7[OSCSEL],
1174 * and waits for the clock source to be stable. Because the external reference
1175 * clock should not be changed in FEE/FBE/BLPE/PBE/PEE modes, do not call this function in these modes.
1176 *
1177 * @param oscsel MCG external reference clock source, MCG_C7[OSCSEL].
1178 * @retval kStatus_MCG_SourceUsed Because the external reference clock is used as a clock source,
1179 * the configuration should not be changed. Otherwise, a glitch occurs.
1180 * @retval kStatus_Success External reference clock set successfully.
1181 */
1182 status_t CLOCK_SetExternalRefClkConfig(mcg_oscsel_t oscsel);
1183
1184 /*!
1185 * @brief Set the FLL external reference clock divider value.
1186 *
1187 * Sets the FLL external reference clock divider value, the register MCG_C1[FRDIV].
1188 *
1189 * @param frdiv The FLL external reference clock divider value, MCG_C1[FRDIV].
1190 */
CLOCK_SetFllExtRefDiv(uint8_t frdiv)1191 static inline void CLOCK_SetFllExtRefDiv(uint8_t frdiv)
1192 {
1193 MCG->C1 = (uint8_t)((MCG->C1 & ~MCG_C1_FRDIV_MASK) | MCG_C1_FRDIV(frdiv));
1194 }
1195
1196 /*!
1197 * @brief Enables the PLL0 in FLL mode.
1198 *
1199 * This function sets us the PLL0 in FLL mode and reconfigures
1200 * the PLL0. Ensure that the PLL reference
1201 * clock is enabled before calling this function and that the PLL0 is not used as a clock source.
1202 * The function CLOCK_CalcPllDiv gets the correct PLL
1203 * divider values.
1204 *
1205 * @param config Pointer to the configuration structure.
1206 */
1207 void CLOCK_EnablePll0(mcg_pll_config_t const *config);
1208
1209 /*!
1210 * @brief Disables the PLL0 in FLL mode.
1211 *
1212 * This function disables the PLL0 in FLL mode. It should be used together with the
1213 * @ref CLOCK_EnablePll0.
1214 */
CLOCK_DisablePll0(void)1215 static inline void CLOCK_DisablePll0(void)
1216 {
1217 MCG->C5 &= (uint8_t)(~(MCG_C5_PLLCLKEN0_MASK | MCG_C5_PLLSTEN0_MASK));
1218 }
1219
1220 /*!
1221 * @brief Calculates the PLL divider setting for a desired output frequency.
1222 *
1223 * This function calculates the correct reference clock divider (\c PRDIV) and
1224 * VCO divider (\c VDIV) to generate a desired PLL output frequency. It returns the
1225 * closest frequency match with the corresponding \c PRDIV/VDIV
1226 * returned from parameters. If a desired frequency is not valid, this function
1227 * returns 0.
1228 *
1229 * @param refFreq PLL reference clock frequency.
1230 * @param desireFreq Desired PLL output frequency.
1231 * @param prdiv PRDIV value to generate desired PLL frequency.
1232 * @param vdiv VDIV value to generate desired PLL frequency.
1233 * @return Closest frequency match that the PLL was able generate.
1234 */
1235 uint32_t CLOCK_CalcPllDiv(uint32_t refFreq, uint32_t desireFreq, uint8_t *prdiv, uint8_t *vdiv);
1236
1237 /*!
1238 * @brief Set the PLL selection.
1239 *
1240 * This function sets the PLL selection between PLL0/PLL1/EXTPLL, and waits for
1241 * change finished.
1242 *
1243 * @param pllcs The PLL to select.
1244 */
1245 void CLOCK_SetPllClkSel(mcg_pll_clk_select_t pllcs);
1246
1247 /*@}*/
1248
1249 /*! @name MCG clock lock monitor functions. */
1250 /*@{*/
1251
1252 /*!
1253 * @brief Sets the OSC0 clock monitor mode.
1254 *
1255 * This function sets the OSC0 clock monitor mode. See @ref mcg_monitor_mode_t for details.
1256 *
1257 * @param mode Monitor mode to set.
1258 */
1259 void CLOCK_SetOsc0MonitorMode(mcg_monitor_mode_t mode);
1260
1261 /*!
1262 * @brief Sets the RTC OSC clock monitor mode.
1263 *
1264 * This function sets the RTC OSC clock monitor mode. See @ref mcg_monitor_mode_t for details.
1265 *
1266 * @param mode Monitor mode to set.
1267 */
1268 void CLOCK_SetRtcOscMonitorMode(mcg_monitor_mode_t mode);
1269
1270 /*!
1271 * @brief Sets the PLL0 clock monitor mode.
1272 *
1273 * This function sets the PLL0 clock monitor mode. See @ref mcg_monitor_mode_t for details.
1274 *
1275 * @param mode Monitor mode to set.
1276 */
1277 void CLOCK_SetPll0MonitorMode(mcg_monitor_mode_t mode);
1278
1279 /*!
1280 * @brief Sets the external PLL clock monitor mode.
1281 *
1282 * This function ets the external PLL clock monitor mode. See @ref mcg_monitor_mode_t
1283 * for details.
1284 *
1285 * @param mode Monitor mode to set.
1286 */
1287 void CLOCK_SetExtPllMonitorMode(mcg_monitor_mode_t mode);
1288
1289 /*!
1290 * @brief Gets the MCG status flags.
1291 *
1292 * This function gets the MCG clock status flags. All status flags are
1293 * returned as a logical OR of the enumeration refer to _mcg_status_flags_t. To
1294 * check a specific flag, compare the return value with the flag.
1295 *
1296 * Example:
1297 * @code
1298 * To check the clock lost lock status of OSC0 and PLL0.
1299 * uint32_t mcgFlags;
1300 *
1301 * mcgFlags = CLOCK_GetStatusFlags();
1302 *
1303 * if (mcgFlags & kMCG_Osc0LostFlag)
1304 * {
1305 * OSC0 clock lock lost. Do something.
1306 * }
1307 * if (mcgFlags & kMCG_Pll0LostFlag)
1308 * {
1309 * PLL0 clock lock lost. Do something.
1310 * }
1311 * @endcode
1312 *
1313 * @return Logical OR value of the enumeration _mcg_status_flags_t.
1314 */
1315 uint32_t CLOCK_GetStatusFlags(void);
1316
1317 /*!
1318 * @brief Clears the MCG status flags.
1319 *
1320 * This function clears the MCG clock lock lost status. The parameter is a logical
1321 * OR value of the flags to clear. See the enumeration _mcg_status_flags_t.
1322 *
1323 * Example:
1324 * @code
1325 * To clear the clock lost lock status flags of OSC0 and PLL0.
1326 *
1327 * CLOCK_ClearStatusFlags(kMCG_Osc0LostFlag | kMCG_Pll0LostFlag);
1328 * @endcode
1329 *
1330 * @param mask The status flags to clear. This is a logical OR of members of the
1331 * enumeration _mcg_status_flags_t.
1332 */
1333 void CLOCK_ClearStatusFlags(uint32_t mask);
1334
1335 /*@}*/
1336
1337 /*!
1338 * @name OSC configuration
1339 * @{
1340 */
1341
1342 /*!
1343 * @brief Configures the OSC external reference clock (OSCERCLK).
1344 *
1345 * This function configures the OSC external reference clock (OSCERCLK).
1346 * This is an example to enable the OSCERCLK in normal and stop modes and also set
1347 * the output divider to 1:
1348 *
1349 @code
1350 oscer_config_t config =
1351 {
1352 .enableMode = kOSC_ErClkEnable | kOSC_ErClkEnableInStop,
1353 .erclkDiv = 1U,
1354 };
1355
1356 OSC_SetExtRefClkConfig(OSC, &config);
1357 @endcode
1358 *
1359 * @param base OSC peripheral address.
1360 * @param config Pointer to the configuration structure.
1361 */
OSC_SetExtRefClkConfig(OSC_Type * base,oscer_config_t const * config)1362 static inline void OSC_SetExtRefClkConfig(OSC_Type *base, oscer_config_t const *config)
1363 {
1364 uint8_t reg = base->CR;
1365
1366 reg &= (uint8_t)(~(OSC_CR_ERCLKEN_MASK | OSC_CR_EREFSTEN_MASK));
1367 reg |= config->enableMode;
1368
1369 base->CR = reg;
1370
1371 base->DIV = OSC_DIV_ERPS(config->erclkDiv);
1372 }
1373
1374 /*!
1375 * @brief Sets the capacitor load configuration for the oscillator.
1376 *
1377 * This function sets the specified capacitors configuration for the oscillator.
1378 * This should be done in the early system level initialization function call
1379 * based on the system configuration.
1380 *
1381 * @param base OSC peripheral address.
1382 * @param capLoad OR'ed value for the capacitor load option, see \ref _osc_cap_load.
1383 *
1384 * Example:
1385 @code
1386 To enable only 2 pF and 8 pF capacitor load, please use like this.
1387 OSC_SetCapLoad(OSC, kOSC_Cap2P | kOSC_Cap8P);
1388 @endcode
1389 */
OSC_SetCapLoad(OSC_Type * base,uint8_t capLoad)1390 static inline void OSC_SetCapLoad(OSC_Type *base, uint8_t capLoad)
1391 {
1392 uint8_t reg = base->CR;
1393
1394 reg &= (uint8_t)(~(OSC_CR_SC2P_MASK | OSC_CR_SC4P_MASK | OSC_CR_SC8P_MASK | OSC_CR_SC16P_MASK));
1395 reg |= capLoad;
1396
1397 base->CR = reg;
1398 }
1399
1400 /*!
1401 * @brief Initializes the OSC0.
1402 *
1403 * This function initializes the OSC0 according to the board configuration.
1404 *
1405 * @param config Pointer to the OSC0 configuration structure.
1406 */
1407 void CLOCK_InitOsc0(osc_config_t const *config);
1408
1409 /*!
1410 * @brief Deinitializes the OSC0.
1411 *
1412 * This function deinitializes the OSC0.
1413 */
1414 void CLOCK_DeinitOsc0(void);
1415
1416 /* @} */
1417
1418 /*!
1419 * @name External clock frequency
1420 * @{
1421 */
1422
1423 /*!
1424 * @brief Sets the XTAL0 frequency based on board settings.
1425 *
1426 * @param freq The XTAL0/EXTAL0 input clock frequency in Hz.
1427 */
CLOCK_SetXtal0Freq(uint32_t freq)1428 static inline void CLOCK_SetXtal0Freq(uint32_t freq)
1429 {
1430 g_xtal0Freq = freq;
1431 }
1432
1433 /*!
1434 * @brief Sets the XTAL32/RTC_CLKIN frequency based on board settings.
1435 *
1436 * @param freq The XTAL32/EXTAL32/RTC_CLKIN input clock frequency in Hz.
1437 */
CLOCK_SetXtal32Freq(uint32_t freq)1438 static inline void CLOCK_SetXtal32Freq(uint32_t freq)
1439 {
1440 g_xtal32Freq = freq;
1441 }
1442 /* @} */
1443
1444 /*!
1445 * @name IRCs frequency
1446 * @{
1447 */
1448
1449 /*!
1450 * @brief Set the Slow IRC frequency based on the trimmed value
1451 *
1452 * @param freq The Slow IRC frequency input clock frequency in Hz.
1453 */
1454 void CLOCK_SetSlowIrcFreq(uint32_t freq);
1455
1456 /*!
1457 * @brief Set the Fast IRC frequency based on the trimmed value
1458 *
1459 * @param freq The Fast IRC frequency input clock frequency in Hz.
1460 */
1461 void CLOCK_SetFastIrcFreq(uint32_t freq);
1462 /* @} */
1463
1464 /*!
1465 * @name MCG auto-trim machine.
1466 * @{
1467 */
1468
1469 /*!
1470 * @brief Auto trims the internal reference clock.
1471 *
1472 * This function trims the internal reference clock by using the external clock. If
1473 * successful, it returns the kStatus_Success and the frequency after
1474 * trimming is received in the parameter @p actualFreq. If an error occurs,
1475 * the error code is returned.
1476 *
1477 * @param extFreq External clock frequency, which should be a bus clock.
1478 * @param desireFreq Frequency to trim to.
1479 * @param actualFreq Actual frequency after trimming.
1480 * @param atms Trim fast or slow internal reference clock.
1481 * @retval kStatus_Success ATM success.
1482 * @retval kStatus_MCG_AtmBusClockInvalid The bus clock is not in allowed range for the ATM.
1483 * @retval kStatus_MCG_AtmDesiredFreqInvalid MCGIRCLK could not be trimmed to the desired frequency.
1484 * @retval kStatus_MCG_AtmIrcUsed Could not trim because MCGIRCLK is used as a bus clock source.
1485 * @retval kStatus_MCG_AtmHardwareFail Hardware fails while trimming.
1486 */
1487 status_t CLOCK_TrimInternalRefClk(uint32_t extFreq, uint32_t desireFreq, uint32_t *actualFreq, mcg_atm_select_t atms);
1488 /* @} */
1489
1490 /*! @name MCG mode functions. */
1491 /*@{*/
1492
1493 /*!
1494 * @brief Gets the current MCG mode.
1495 *
1496 * This function checks the MCG registers and determines the current MCG mode.
1497 *
1498 * @return Current MCG mode or error code; See @ref mcg_mode_t.
1499 */
1500 mcg_mode_t CLOCK_GetMode(void);
1501
1502 /*!
1503 * @brief Sets the MCG to FEI mode.
1504 *
1505 * This function sets the MCG to FEI mode. If setting to FEI mode fails
1506 * from the current mode, this function returns an error.
1507 *
1508 * @param dmx32 DMX32 in FEI mode.
1509 * @param drs The DCO range selection.
1510 * @param fllStableDelay Delay function to ensure that the FLL is stable. Passing
1511 * NULL does not cause a delay.
1512 * @retval kStatus_MCG_ModeUnreachable Could not switch to the target mode.
1513 * @retval kStatus_Success Switched to the target mode successfully.
1514 * @note If @p dmx32 is set to kMCG_Dmx32Fine, the slow IRC must not be trimmed
1515 * to a frequency above 32768 Hz.
1516 */
1517 status_t CLOCK_SetFeiMode(mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDelay)(void));
1518
1519 /*!
1520 * @brief Sets the MCG to FEE mode.
1521 *
1522 * This function sets the MCG to FEE mode. If setting to FEE mode fails
1523 * from the current mode, this function returns an error.
1524 *
1525 * @param frdiv FLL reference clock divider setting, FRDIV.
1526 * @param dmx32 DMX32 in FEE mode.
1527 * @param drs The DCO range selection.
1528 * @param fllStableDelay Delay function to make sure FLL is stable. Passing
1529 * NULL does not cause a delay.
1530 *
1531 * @retval kStatus_MCG_ModeUnreachable Could not switch to the target mode.
1532 * @retval kStatus_Success Switched to the target mode successfully.
1533 */
1534 status_t CLOCK_SetFeeMode(uint8_t frdiv, mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDelay)(void));
1535
1536 /*!
1537 * @brief Sets the MCG to FBI mode.
1538 *
1539 * This function sets the MCG to FBI mode. If setting to FBI mode fails
1540 * from the current mode, this function returns an error.
1541 *
1542 * @param dmx32 DMX32 in FBI mode.
1543 * @param drs The DCO range selection.
1544 * @param fllStableDelay Delay function to make sure FLL is stable. If the FLL
1545 * is not used in FBI mode, this parameter can be NULL. Passing
1546 * NULL does not cause a delay.
1547 * @retval kStatus_MCG_ModeUnreachable Could not switch to the target mode.
1548 * @retval kStatus_Success Switched to the target mode successfully.
1549 * @note If @p dmx32 is set to kMCG_Dmx32Fine, the slow IRC must not be trimmed
1550 * to frequency above 32768 Hz.
1551 */
1552 status_t CLOCK_SetFbiMode(mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDelay)(void));
1553
1554 /*!
1555 * @brief Sets the MCG to FBE mode.
1556 *
1557 * This function sets the MCG to FBE mode. If setting to FBE mode fails
1558 * from the current mode, this function returns an error.
1559 *
1560 * @param frdiv FLL reference clock divider setting, FRDIV.
1561 * @param dmx32 DMX32 in FBE mode.
1562 * @param drs The DCO range selection.
1563 * @param fllStableDelay Delay function to make sure FLL is stable. If the FLL
1564 * is not used in FBE mode, this parameter can be NULL. Passing NULL
1565 * does not cause a delay.
1566 * @retval kStatus_MCG_ModeUnreachable Could not switch to the target mode.
1567 * @retval kStatus_Success Switched to the target mode successfully.
1568 */
1569 status_t CLOCK_SetFbeMode(uint8_t frdiv, mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDelay)(void));
1570
1571 /*!
1572 * @brief Sets the MCG to BLPI mode.
1573 *
1574 * This function sets the MCG to BLPI mode. If setting to BLPI mode fails
1575 * from the current mode, this function returns an error.
1576 *
1577 * @retval kStatus_MCG_ModeUnreachable Could not switch to the target mode.
1578 * @retval kStatus_Success Switched to the target mode successfully.
1579 */
1580 status_t CLOCK_SetBlpiMode(void);
1581
1582 /*!
1583 * @brief Sets the MCG to BLPE mode.
1584 *
1585 * This function sets the MCG to BLPE mode. If setting to BLPE mode fails
1586 * from the current mode, this function returns an error.
1587 *
1588 * @retval kStatus_MCG_ModeUnreachable Could not switch to the target mode.
1589 * @retval kStatus_Success Switched to the target mode successfully.
1590 */
1591 status_t CLOCK_SetBlpeMode(void);
1592
1593 /*!
1594 * @brief Sets the MCG to PBE mode.
1595 *
1596 * This function sets the MCG to PBE mode. If setting to PBE mode fails
1597 * from the current mode, this function returns an error.
1598 *
1599 * @param pllcs The PLL selection, PLLCS.
1600 * @param config Pointer to the PLL configuration.
1601 * @retval kStatus_MCG_ModeUnreachable Could not switch to the target mode.
1602 * @retval kStatus_Success Switched to the target mode successfully.
1603 *
1604 * @note
1605 * 1. The parameter \c pllcs selects the PLL. For platforms with
1606 * only one PLL, the parameter pllcs is kept for interface compatibility.
1607 * 2. The parameter \c config is the PLL configuration structure. On some
1608 * platforms, it is possible to choose the external PLL directly, which renders the
1609 * configuration structure not necessary. In this case, pass in NULL.
1610 * For example: CLOCK_SetPbeMode(kMCG_OscselOsc, kMCG_PllClkSelExtPll, NULL);
1611 */
1612 status_t CLOCK_SetPbeMode(mcg_pll_clk_select_t pllcs, mcg_pll_config_t const *config);
1613
1614 /*!
1615 * @brief Sets the MCG to PEE mode.
1616 *
1617 * This function sets the MCG to PEE mode.
1618 *
1619 * @retval kStatus_MCG_ModeUnreachable Could not switch to the target mode.
1620 * @retval kStatus_Success Switched to the target mode successfully.
1621 *
1622 * @note This function only changes the CLKS to use the PLL/FLL output. If the
1623 * PRDIV/VDIV are different than in the PBE mode, set them up
1624 * in PBE mode and wait. When the clock is stable, switch to PEE mode.
1625 */
1626 status_t CLOCK_SetPeeMode(void);
1627
1628 /*!
1629 * @brief Switches the MCG to FBE mode from the external mode.
1630 *
1631 * This function switches the MCG from external modes (PEE/PBE/BLPE/FEE) to the FBE mode quickly.
1632 * The external clock is used as the system clock source and PLL is disabled. However,
1633 * the FLL settings are not configured. This is a lite function with a small code size, which is useful
1634 * during the mode switch. For example, to switch from PEE mode to FEI mode:
1635 *
1636 * @code
1637 * CLOCK_ExternalModeToFbeModeQuick();
1638 * CLOCK_SetFeiMode(...);
1639 * @endcode
1640 *
1641 * @retval kStatus_Success Switched successfully.
1642 * @retval kStatus_MCG_ModeInvalid If the current mode is not an external mode, do not call this function.
1643 */
1644 status_t CLOCK_ExternalModeToFbeModeQuick(void);
1645
1646 /*!
1647 * @brief Switches the MCG to FBI mode from internal modes.
1648 *
1649 * This function switches the MCG from internal modes (PEI/PBI/BLPI/FEI) to the FBI mode quickly.
1650 * The MCGIRCLK is used as the system clock source and PLL is disabled. However,
1651 * FLL settings are not configured. This is a lite function with a small code size, which is useful
1652 * during the mode switch. For example, to switch from PEI mode to FEE mode:
1653 *
1654 * @code
1655 * CLOCK_InternalModeToFbiModeQuick();
1656 * CLOCK_SetFeeMode(...);
1657 * @endcode
1658 *
1659 * @retval kStatus_Success Switched successfully.
1660 * @retval kStatus_MCG_ModeInvalid If the current mode is not an internal mode, do not call this function.
1661 */
1662 status_t CLOCK_InternalModeToFbiModeQuick(void);
1663
1664 /*!
1665 * @brief Sets the MCG to FEI mode during system boot up.
1666 *
1667 * This function sets the MCG to FEI mode from the reset mode. It can also be used to
1668 * set up MCG during system boot up.
1669 *
1670 * @param dmx32 DMX32 in FEI mode.
1671 * @param drs The DCO range selection.
1672 * @param fllStableDelay Delay function to ensure that the FLL is stable.
1673 *
1674 * @retval kStatus_MCG_ModeUnreachable Could not switch to the target mode.
1675 * @retval kStatus_Success Switched to the target mode successfully.
1676 * @note If @p dmx32 is set to kMCG_Dmx32Fine, the slow IRC must not be trimmed
1677 * to frequency above 32768 Hz.
1678 */
1679 status_t CLOCK_BootToFeiMode(mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDelay)(void));
1680
1681 /*!
1682 * @brief Sets the MCG to FEE mode during system bootup.
1683 *
1684 * This function sets MCG to FEE mode from the reset mode. It can also be used to
1685 * set up the MCG during system boot up.
1686 *
1687 * @param oscsel OSC clock select, OSCSEL.
1688 * @param frdiv FLL reference clock divider setting, FRDIV.
1689 * @param dmx32 DMX32 in FEE mode.
1690 * @param drs The DCO range selection.
1691 * @param fllStableDelay Delay function to ensure that the FLL is stable.
1692 *
1693 * @retval kStatus_MCG_ModeUnreachable Could not switch to the target mode.
1694 * @retval kStatus_Success Switched to the target mode successfully.
1695 */
1696 status_t CLOCK_BootToFeeMode(
1697 mcg_oscsel_t oscsel, uint8_t frdiv, mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDelay)(void));
1698
1699 /*!
1700 * @brief Sets the MCG to BLPI mode during system boot up.
1701 *
1702 * This function sets the MCG to BLPI mode from the reset mode. It can also be used to
1703 * set up the MCG during system boot up.
1704 *
1705 * @param fcrdiv Fast IRC divider, FCRDIV.
1706 * @param ircs The internal reference clock to select, IRCS.
1707 * @param ircEnableMode The MCGIRCLK enable mode, OR'ed value of the enumeration _mcg_irclk_enable_mode.
1708 *
1709 * @retval kStatus_MCG_SourceUsed Could not change MCGIRCLK setting.
1710 * @retval kStatus_Success Switched to the target mode successfully.
1711 */
1712 status_t CLOCK_BootToBlpiMode(uint8_t fcrdiv, mcg_irc_mode_t ircs, uint8_t ircEnableMode);
1713
1714 /*!
1715 * @brief Sets the MCG to BLPE mode during system boot up.
1716 *
1717 * This function sets the MCG to BLPE mode from the reset mode. It can also be used to
1718 * set up the MCG during system boot up.
1719 *
1720 * @param oscsel OSC clock select, MCG_C7[OSCSEL].
1721 *
1722 * @retval kStatus_MCG_ModeUnreachable Could not switch to the target mode.
1723 * @retval kStatus_Success Switched to the target mode successfully.
1724 */
1725 status_t CLOCK_BootToBlpeMode(mcg_oscsel_t oscsel);
1726
1727 /*!
1728 * @brief Sets the MCG to PEE mode during system boot up.
1729 *
1730 * This function sets the MCG to PEE mode from reset mode. It can also be used to
1731 * set up the MCG during system boot up.
1732 *
1733 * @param oscsel OSC clock select, MCG_C7[OSCSEL].
1734 * @param pllcs The PLL selection, PLLCS.
1735 * @param config Pointer to the PLL configuration.
1736 *
1737 * @retval kStatus_MCG_ModeUnreachable Could not switch to the target mode.
1738 * @retval kStatus_Success Switched to the target mode successfully.
1739 */
1740 status_t CLOCK_BootToPeeMode(mcg_oscsel_t oscsel, mcg_pll_clk_select_t pllcs, mcg_pll_config_t const *config);
1741
1742 /*!
1743 * @brief Sets the MCG to a target mode.
1744 *
1745 * This function sets MCG to a target mode defined by the configuration
1746 * structure. If switching to the target mode fails, this function
1747 * chooses the correct path.
1748 *
1749 * @param config Pointer to the target MCG mode configuration structure.
1750 * @return Return kStatus_Success if switched successfully; Otherwise, it returns an error code _mcg_status.
1751 *
1752 * @note If the external clock is used in the target mode, ensure that it is
1753 * enabled. For example, if the OSC0 is used, set up OSC0 correctly before calling this
1754 * function.
1755 */
1756 status_t CLOCK_SetMcgConfig(mcg_config_t const *config);
1757
1758 /*@}*/
1759
1760 #if defined(__cplusplus)
1761 }
1762 #endif /* __cplusplus */
1763
1764 /*! @} */
1765
1766 #endif /* _FSL_CLOCK_H_ */
1767
