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Searched refs:MCG_C5_PLLSTEN0_MASK (Results 1 – 20 of 20) sorted by relevance

/hal_nxp-2.7.6/mcux/devices/MKL25Z4/
Dfsl_clock.h516 kMCG_PllEnableInStop = MCG_C5_PLLSTEN0_MASK /*!< MCGPLLCLK enable in STOP mode. */
896 MCG->C5 &= ~(MCG_C5_PLLCLKEN0_MASK | MCG_C5_PLLSTEN0_MASK); in CLOCK_DisablePll0()
DMKL25Z4.h2082 #define MCG_C5_PLLSTEN0_MASK (0x20U) macro
2084 … (((uint8_t)(((uint8_t)(x)) << MCG_C5_PLLSTEN0_SHIFT)) & MCG_C5_PLLSTEN0_MASK)
/hal_nxp-2.7.6/mcux/devices/MKW22D5/
Dfsl_clock.h546 kMCG_PllEnableInStop = MCG_C5_PLLSTEN0_MASK /*!< MCGPLLCLK enable in STOP mode. */
948 MCG->C5 &= ~(MCG_C5_PLLCLKEN0_MASK | MCG_C5_PLLSTEN0_MASK); in CLOCK_DisablePll0()
DMKW22D5.h4837 #define MCG_C5_PLLSTEN0_MASK (0x20U) macro
4839 … (((uint8_t)(((uint8_t)(x)) << MCG_C5_PLLSTEN0_SHIFT)) & MCG_C5_PLLSTEN0_MASK)
/hal_nxp-2.7.6/mcux/devices/MKW24D5/
Dfsl_clock.h546 kMCG_PllEnableInStop = MCG_C5_PLLSTEN0_MASK /*!< MCGPLLCLK enable in STOP mode. */
948 MCG->C5 &= ~(MCG_C5_PLLCLKEN0_MASK | MCG_C5_PLLSTEN0_MASK); in CLOCK_DisablePll0()
DMKW24D5.h4837 #define MCG_C5_PLLSTEN0_MASK (0x20U) macro
4839 … (((uint8_t)(((uint8_t)(x)) << MCG_C5_PLLSTEN0_SHIFT)) & MCG_C5_PLLSTEN0_MASK)
/hal_nxp-2.7.6/mcux/devices/MK22F51212/
Dfsl_clock.h558 kMCG_PllEnableInStop = MCG_C5_PLLSTEN0_MASK /*!< MCGPLLCLK enable in STOP mode. */
993 MCG->C5 &= (uint8_t)(~(MCG_C5_PLLCLKEN0_MASK | MCG_C5_PLLSTEN0_MASK)); in CLOCK_DisablePll0()
DMK22F51212.h8814 #define MCG_C5_PLLSTEN0_MASK (0x20U) macro
8820 … (((uint8_t)(((uint8_t)(x)) << MCG_C5_PLLSTEN0_SHIFT)) & MCG_C5_PLLSTEN0_MASK)
/hal_nxp-2.7.6/mcux/devices/MKV58F24/
Dfsl_clock.h604 kMCG_PllEnableInStop = MCG_C5_PLLSTEN0_MASK /*!< MCGPLLCLK enable in STOP mode. */
1013 MCG->C5 &= (uint8_t)(~(MCG_C5_PLLCLKEN0_MASK | MCG_C5_PLLSTEN0_MASK)); in CLOCK_DisablePll0()
DMKV58F24.h16656 #define MCG_C5_PLLSTEN0_MASK (MCG_C5_PLLSTEN_MASK) macro
/hal_nxp-2.7.6/mcux/devices/MKV56F24/
Dfsl_clock.h604 kMCG_PllEnableInStop = MCG_C5_PLLSTEN0_MASK /*!< MCGPLLCLK enable in STOP mode. */
1012 MCG->C5 &= (uint8_t)(~(MCG_C5_PLLCLKEN0_MASK | MCG_C5_PLLSTEN0_MASK)); in CLOCK_DisablePll0()
DMKV56F24.h15316 #define MCG_C5_PLLSTEN0_MASK (MCG_C5_PLLSTEN_MASK) macro
/hal_nxp-2.7.6/mcux/devices/MK64F12/
Dfsl_clock.h599 kMCG_PllEnableInStop = MCG_C5_PLLSTEN0_MASK /*!< MCGPLLCLK enable in STOP mode. */
1040 MCG->C5 &= (uint8_t)(~(MCG_C5_PLLCLKEN0_MASK | MCG_C5_PLLSTEN0_MASK)); in CLOCK_DisablePll0()
DMK64F12.h16703 #define MCG_C5_PLLSTEN0_MASK (0x20U) macro
16709 … (((uint8_t)(((uint8_t)(x)) << MCG_C5_PLLSTEN0_SHIFT)) & MCG_C5_PLLSTEN0_MASK)
/hal_nxp-2.7.6/mcux/devices/MK80F25615/
Dfsl_clock.h624 kMCG_PllEnableInStop = MCG_C5_PLLSTEN0_MASK /*!< MCGPLLCLK enable in STOP mode. */
1104 MCG->C5 &= (uint8_t)(~(MCG_C5_PLLCLKEN0_MASK | MCG_C5_PLLSTEN0_MASK)); in CLOCK_DisablePll0()
DMK80F25615.h16752 #define MCG_C5_PLLSTEN0_MASK (MCG_C5_PLLSTEN_MASK) macro
/hal_nxp-2.7.6/mcux/devices/MK82F25615/
Dfsl_clock.h631 kMCG_PllEnableInStop = MCG_C5_PLLSTEN0_MASK /*!< MCGPLLCLK enable in STOP mode. */
1111 MCG->C5 &= (uint8_t)(~(MCG_C5_PLLCLKEN0_MASK | MCG_C5_PLLSTEN0_MASK)); in CLOCK_DisablePll0()
DMK82F25615.h17499 #define MCG_C5_PLLSTEN0_MASK (MCG_C5_PLLSTEN_MASK) macro
/hal_nxp-2.7.6/mcux/devices/MK66F18/
Dfsl_clock.h654 kMCG_PllEnableInStop = MCG_C5_PLLSTEN0_MASK /*!< MCGPLLCLK enable in STOP mode. */
1217 MCG->C5 &= (uint8_t)(~(MCG_C5_PLLCLKEN0_MASK | MCG_C5_PLLSTEN0_MASK)); in CLOCK_DisablePll0()
DMK66F18.h17333 #define MCG_C5_PLLSTEN0_MASK (MCG_C5_PLLSTEN_MASK) macro