Home
last modified time | relevance | path

Searched refs:MCG_C5_PLLCLKEN0_MASK (Results 1 – 20 of 20) sorted by relevance

/hal_nxp-2.7.6/mcux/devices/MKL25Z4/
Dfsl_clock.h510 kMCG_PllEnableIndependent = MCG_C5_PLLCLKEN0_MASK, /*!< MCGPLLCLK enable independent of the
896 MCG->C5 &= ~(MCG_C5_PLLCLKEN0_MASK | MCG_C5_PLLSTEN0_MASK); in CLOCK_DisablePll0()
DMKL25Z4.h2085 #define MCG_C5_PLLCLKEN0_MASK (0x40U) macro
2087 … (((uint8_t)(((uint8_t)(x)) << MCG_C5_PLLCLKEN0_SHIFT)) & MCG_C5_PLLCLKEN0_MASK)
/hal_nxp-2.7.6/mcux/devices/MKW22D5/
Dfsl_clock.h540 kMCG_PllEnableIndependent = MCG_C5_PLLCLKEN0_MASK, /*!< MCGPLLCLK enable independent of the
948 MCG->C5 &= ~(MCG_C5_PLLCLKEN0_MASK | MCG_C5_PLLSTEN0_MASK); in CLOCK_DisablePll0()
DMKW22D5.h4840 #define MCG_C5_PLLCLKEN0_MASK (0x40U) macro
4842 … (((uint8_t)(((uint8_t)(x)) << MCG_C5_PLLCLKEN0_SHIFT)) & MCG_C5_PLLCLKEN0_MASK)
/hal_nxp-2.7.6/mcux/devices/MKW24D5/
Dfsl_clock.h540 kMCG_PllEnableIndependent = MCG_C5_PLLCLKEN0_MASK, /*!< MCGPLLCLK enable independent of the
948 MCG->C5 &= ~(MCG_C5_PLLCLKEN0_MASK | MCG_C5_PLLSTEN0_MASK); in CLOCK_DisablePll0()
DMKW24D5.h4840 #define MCG_C5_PLLCLKEN0_MASK (0x40U) macro
4842 … (((uint8_t)(((uint8_t)(x)) << MCG_C5_PLLCLKEN0_SHIFT)) & MCG_C5_PLLCLKEN0_MASK)
/hal_nxp-2.7.6/mcux/devices/MK22F51212/
Dfsl_clock.h552 kMCG_PllEnableIndependent = MCG_C5_PLLCLKEN0_MASK, /*!< MCGPLLCLK enable independent of the
993 MCG->C5 &= (uint8_t)(~(MCG_C5_PLLCLKEN0_MASK | MCG_C5_PLLSTEN0_MASK)); in CLOCK_DisablePll0()
DMK22F51212.h8821 #define MCG_C5_PLLCLKEN0_MASK (0x40U) macro
8827 … (((uint8_t)(((uint8_t)(x)) << MCG_C5_PLLCLKEN0_SHIFT)) & MCG_C5_PLLCLKEN0_MASK)
/hal_nxp-2.7.6/mcux/devices/MKV58F24/
Dfsl_clock.h598 kMCG_PllEnableIndependent = MCG_C5_PLLCLKEN0_MASK, /*!< MCGPLLCLK enable independent of the
1013 MCG->C5 &= (uint8_t)(~(MCG_C5_PLLCLKEN0_MASK | MCG_C5_PLLSTEN0_MASK)); in CLOCK_DisablePll0()
DMKV58F24.h16650 #define MCG_C5_PLLCLKEN0_MASK (MCG_C5_PLLCLKEN_MASK) macro
/hal_nxp-2.7.6/mcux/devices/MKV56F24/
Dfsl_clock.h598 kMCG_PllEnableIndependent = MCG_C5_PLLCLKEN0_MASK, /*!< MCGPLLCLK enable independent of the
1012 MCG->C5 &= (uint8_t)(~(MCG_C5_PLLCLKEN0_MASK | MCG_C5_PLLSTEN0_MASK)); in CLOCK_DisablePll0()
DMKV56F24.h15310 #define MCG_C5_PLLCLKEN0_MASK (MCG_C5_PLLCLKEN_MASK) macro
/hal_nxp-2.7.6/mcux/devices/MK64F12/
Dfsl_clock.h593 kMCG_PllEnableIndependent = MCG_C5_PLLCLKEN0_MASK, /*!< MCGPLLCLK enable independent of the
1040 MCG->C5 &= (uint8_t)(~(MCG_C5_PLLCLKEN0_MASK | MCG_C5_PLLSTEN0_MASK)); in CLOCK_DisablePll0()
DMK64F12.h16711 #define MCG_C5_PLLCLKEN0_MASK (0x40U) macro
16717 … (((uint8_t)(((uint8_t)(x)) << MCG_C5_PLLCLKEN0_SHIFT)) & MCG_C5_PLLCLKEN0_MASK)
/hal_nxp-2.7.6/mcux/devices/MK80F25615/
Dfsl_clock.h618 kMCG_PllEnableIndependent = MCG_C5_PLLCLKEN0_MASK, /*!< MCGPLLCLK enable independent of the
1104 MCG->C5 &= (uint8_t)(~(MCG_C5_PLLCLKEN0_MASK | MCG_C5_PLLSTEN0_MASK)); in CLOCK_DisablePll0()
DMK80F25615.h16746 #define MCG_C5_PLLCLKEN0_MASK (MCG_C5_PLLCLKEN_MASK) macro
/hal_nxp-2.7.6/mcux/devices/MK82F25615/
Dfsl_clock.h625 kMCG_PllEnableIndependent = MCG_C5_PLLCLKEN0_MASK, /*!< MCGPLLCLK enable independent of the
1111 MCG->C5 &= (uint8_t)(~(MCG_C5_PLLCLKEN0_MASK | MCG_C5_PLLSTEN0_MASK)); in CLOCK_DisablePll0()
DMK82F25615.h17493 #define MCG_C5_PLLCLKEN0_MASK (MCG_C5_PLLCLKEN_MASK) macro
/hal_nxp-2.7.6/mcux/devices/MK66F18/
Dfsl_clock.h648 kMCG_PllEnableIndependent = MCG_C5_PLLCLKEN0_MASK, /*!< MCGPLLCLK enable independent of the
1217 MCG->C5 &= (uint8_t)(~(MCG_C5_PLLCLKEN0_MASK | MCG_C5_PLLSTEN0_MASK)); in CLOCK_DisablePll0()
DMK66F18.h17327 #define MCG_C5_PLLCLKEN0_MASK (MCG_C5_PLLCLKEN_MASK) macro