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Searched refs:C5 (Results 1 – 25 of 50) sorted by relevance

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/hal_nxp-2.7.6/mcux/drivers/kinetis/
Dfsl_lpsci.h413 base->C5 |= UART0_C5_TDMAE_MASK; in LPSCI_EnableTxDMA()
418 base->C5 &= ~UART0_C5_TDMAE_MASK; in LPSCI_EnableTxDMA()
435 base->C5 |= UART0_C5_RDMAE_MASK; in LPSCI_EnableRxDMA()
440 base->C5 &= ~UART0_C5_RDMAE_MASK; in LPSCI_EnableRxDMA()
Dfsl_uart.h551 base->C5 |= (uint8_t)UART_C5_TDMAS_MASK; in UART_EnableTxDMA()
560 base->C5 &= ~(uint8_t)UART_C5_TDMAS_MASK; in UART_EnableTxDMA()
581 base->C5 |= (uint8_t)UART_C5_RDMAS_MASK; in UART_EnableRxDMA()
590 base->C5 &= ~(uint8_t)UART_C5_RDMAS_MASK; in UART_EnableRxDMA()
Dfsl_lpsci.c282 base->C5 |= UART0_C5_BOTHEDGE_MASK; in LPSCI_Init()
409 base->C5 |= UART0_C5_BOTHEDGE_MASK; in LPSCI_SetBaudRate()
/hal_nxp-2.7.6/mcux/devices/MKL25Z4/
Dfsl_clock.c80 #define MCG_C5_PLLREFSEL0_VAL ((MCG->C5 & MCG_C5_PLLREFSEL0_MASK) >> MCG_C5_PLLREFSEL0_SHIFT)
84 #define MCG_C5_PRDIV0_VAL ((MCG->C5 & MCG_C5_PRDIV0_MASK) >> MCG_C5_PRDIV0_SHIFT)
765 MCG->C5 = mcg_c5; /* Disable the PLL first. */ in CLOCK_EnablePll0()
770 MCG->C5 |= ((uint32_t)kMCG_PllEnableIndependent | (uint32_t)config->enableMode); in CLOCK_EnablePll0()
1673 MCG->C5 &= ~(uint32_t)kMCG_PllEnableIndependent; in CLOCK_SetMcgConfig()
Dsystem_MKL25Z4.c194 Divider = (((uint16_t)MCG->C5 & MCG_C5_PRDIV0_MASK) + 0x01U); in SystemCoreClockUpdate()
Dfsl_clock.h896 MCG->C5 &= ~(MCG_C5_PLLCLKEN0_MASK | MCG_C5_PLLSTEN0_MASK); in CLOCK_DisablePll0()
/hal_nxp-2.7.6/mcux/devices/MKW22D5/
Dfsl_clock.c80 #define MCG_C5_PLLREFSEL0_VAL ((MCG->C5 & MCG_C5_PLLREFSEL0_MASK) >> MCG_C5_PLLREFSEL0_SHIFT)
84 #define MCG_C5_PRDIV0_VAL ((MCG->C5 & MCG_C5_PRDIV0_MASK) >> MCG_C5_PRDIV0_SHIFT)
818 MCG->C5 = mcg_c5; /* Disable the PLL first. */ in CLOCK_EnablePll0()
823 MCG->C5 |= ((uint32_t)kMCG_PllEnableIndependent | (uint32_t)config->enableMode); in CLOCK_EnablePll0()
1772 MCG->C5 &= ~(uint32_t)kMCG_PllEnableIndependent; in CLOCK_SetMcgConfig()
Dsystem_MKW22D5.c207 Divider = (((uint16_t)MCG->C5 & MCG_C5_PRDIV0_MASK) + 0x01U); in SystemCoreClockUpdate()
/hal_nxp-2.7.6/mcux/devices/MKW24D5/
Dfsl_clock.c80 #define MCG_C5_PLLREFSEL0_VAL ((MCG->C5 & MCG_C5_PLLREFSEL0_MASK) >> MCG_C5_PLLREFSEL0_SHIFT)
84 #define MCG_C5_PRDIV0_VAL ((MCG->C5 & MCG_C5_PRDIV0_MASK) >> MCG_C5_PRDIV0_SHIFT)
818 MCG->C5 = mcg_c5; /* Disable the PLL first. */ in CLOCK_EnablePll0()
823 MCG->C5 |= ((uint32_t)kMCG_PllEnableIndependent | (uint32_t)config->enableMode); in CLOCK_EnablePll0()
1772 MCG->C5 &= ~(uint32_t)kMCG_PllEnableIndependent; in CLOCK_SetMcgConfig()
Dsystem_MKW24D5.c207 Divider = (((uint16_t)MCG->C5 & MCG_C5_PRDIV0_MASK) + 0x01U); in SystemCoreClockUpdate()
/hal_nxp-2.7.6/mcux/devices/MKV58F24/
Dfsl_clock.c62 #define MCG_C5_PLLREFSEL0_VAL ((MCG->C5 & MCG_C5_PLLREFSEL0_MASK) >> MCG_C5_PLLREFSEL0_SHIFT)
66 #define MCG_C5_PRDIV0_VAL ((uint8_t)(MCG->C5 & MCG_C5_PRDIV0_MASK) >> MCG_C5_PRDIV0_SHIFT)
950 MCG->C5 = mcg_c5; /* Disable the PLL first. */ in CLOCK_EnablePll0()
955 MCG->C5 |= ((uint8_t)kMCG_PllEnableIndependent | (uint8_t)config->enableMode); in CLOCK_EnablePll0()
2207 MCG->C5 &= ~(uint8_t)kMCG_PllEnableIndependent; in CLOCK_SetMcgConfig()
Dsystem_MKV58F24.c172 Divider = (1U + (MCG->C5 & MCG_C5_PRDIV_MASK)); in SystemCoreClockUpdate()
/hal_nxp-2.7.6/mcux/devices/MKV56F24/
Dfsl_clock.c62 #define MCG_C5_PLLREFSEL0_VAL ((MCG->C5 & MCG_C5_PLLREFSEL0_MASK) >> MCG_C5_PLLREFSEL0_SHIFT)
66 #define MCG_C5_PRDIV0_VAL ((uint8_t)(MCG->C5 & MCG_C5_PRDIV0_MASK) >> MCG_C5_PRDIV0_SHIFT)
950 MCG->C5 = mcg_c5; /* Disable the PLL first. */ in CLOCK_EnablePll0()
955 MCG->C5 |= ((uint8_t)kMCG_PllEnableIndependent | (uint8_t)config->enableMode); in CLOCK_EnablePll0()
2207 MCG->C5 &= ~(uint8_t)kMCG_PllEnableIndependent; in CLOCK_SetMcgConfig()
Dsystem_MKV56F24.c172 Divider = (1U + (MCG->C5 & MCG_C5_PRDIV_MASK)); in SystemCoreClockUpdate()
/hal_nxp-2.7.6/mcux/devices/MK22F51212/
Dfsl_clock.c62 #define MCG_C5_PLLREFSEL0_VAL ((MCG->C5 & MCG_C5_PLLREFSEL0_MASK) >> MCG_C5_PLLREFSEL0_SHIFT)
66 #define MCG_C5_PRDIV0_VAL ((uint8_t)(MCG->C5 & MCG_C5_PRDIV0_MASK) >> MCG_C5_PRDIV0_SHIFT)
1055 MCG->C5 = mcg_c5; /* Disable the PLL first. */ in CLOCK_EnablePll0()
1060 MCG->C5 |= ((uint8_t)kMCG_PllEnableIndependent | (uint8_t)config->enableMode); in CLOCK_EnablePll0()
2365 MCG->C5 &= ~(uint8_t)kMCG_PllEnableIndependent; in CLOCK_SetMcgConfig()
Dsystem_MK22F51212.c198 Divider = (((uint16_t)MCG->C5 & MCG_C5_PRDIV0_MASK) + 0x01U); in SystemCoreClockUpdate()
/hal_nxp-2.7.6/mcux/devices/MK64F12/
Dfsl_clock.c62 #define MCG_C5_PLLREFSEL0_VAL ((MCG->C5 & MCG_C5_PLLREFSEL0_MASK) >> MCG_C5_PLLREFSEL0_SHIFT)
66 #define MCG_C5_PRDIV0_VAL ((uint8_t)(MCG->C5 & MCG_C5_PRDIV0_MASK) >> MCG_C5_PRDIV0_SHIFT)
1022 MCG->C5 = mcg_c5; /* Disable the PLL first. */ in CLOCK_EnablePll0()
1027 MCG->C5 |= ((uint8_t)kMCG_PllEnableIndependent | (uint8_t)config->enableMode); in CLOCK_EnablePll0()
2332 MCG->C5 &= ~(uint8_t)kMCG_PllEnableIndependent; in CLOCK_SetMcgConfig()
Dsystem_MK64F12.c202 Divider = (((uint16_t)MCG->C5 & MCG_C5_PRDIV0_MASK) + 0x01U); in SystemCoreClockUpdate()
/hal_nxp-2.7.6/mcux/devices/MK80F25615/
Dfsl_clock.c62 #define MCG_C5_PLLREFSEL0_VAL ((MCG->C5 & MCG_C5_PLLREFSEL0_MASK) >> MCG_C5_PLLREFSEL0_SHIFT)
66 #define MCG_C5_PRDIV0_VAL ((uint8_t)(MCG->C5 & MCG_C5_PRDIV0_MASK) >> MCG_C5_PRDIV0_SHIFT)
1064 MCG->C5 = mcg_c5; /* Disable the PLL first. */ in CLOCK_EnablePll0()
1069 MCG->C5 |= ((uint8_t)kMCG_PllEnableIndependent | (uint8_t)config->enableMode); in CLOCK_EnablePll0()
2374 MCG->C5 &= ~(uint8_t)kMCG_PllEnableIndependent; in CLOCK_SetMcgConfig()
Dsystem_MK80F25615.c177 Divider = (((uint16_t)MCG->C5 & MCG_C5_PRDIV_MASK) + 0x01U); in SystemCoreClockUpdate()
/hal_nxp-2.7.6/mcux/devices/MK82F25615/
Dfsl_clock.c62 #define MCG_C5_PLLREFSEL0_VAL ((MCG->C5 & MCG_C5_PLLREFSEL0_MASK) >> MCG_C5_PLLREFSEL0_SHIFT)
66 #define MCG_C5_PRDIV0_VAL ((uint8_t)(MCG->C5 & MCG_C5_PRDIV0_MASK) >> MCG_C5_PRDIV0_SHIFT)
1064 MCG->C5 = mcg_c5; /* Disable the PLL first. */ in CLOCK_EnablePll0()
1069 MCG->C5 |= ((uint8_t)kMCG_PllEnableIndependent | (uint8_t)config->enableMode); in CLOCK_EnablePll0()
2374 MCG->C5 &= ~(uint8_t)kMCG_PllEnableIndependent; in CLOCK_SetMcgConfig()
Dsystem_MK82F25615.c171 Divider = (((uint16_t)MCG->C5 & MCG_C5_PRDIV_MASK) + 0x01U); in SystemCoreClockUpdate()
/hal_nxp-2.7.6/mcux/devices/MK66F18/
Dfsl_clock.c62 #define MCG_C5_PLLREFSEL0_VAL ((MCG->C5 & MCG_C5_PLLREFSEL0_MASK) >> MCG_C5_PLLREFSEL0_SHIFT)
66 #define MCG_C5_PRDIV0_VAL ((uint8_t)(MCG->C5 & MCG_C5_PRDIV0_MASK) >> MCG_C5_PRDIV0_SHIFT)
1282 MCG->C5 = mcg_c5; /* Disable the PLL first. */ in CLOCK_EnablePll0()
1287 MCG->C5 |= ((uint8_t)kMCG_PllEnableIndependent | (uint8_t)config->enableMode); in CLOCK_EnablePll0()
2665 MCG->C5 &= ~(uint8_t)kMCG_PllEnableIndependent; in CLOCK_SetMcgConfig()
Dsystem_MK66F18.c184 Divider = (((uint16_t)MCG->C5 & MCG_C5_PRDIV_MASK) + 0x01U); in SystemCoreClockUpdate()
/hal_nxp-2.7.6/mcux/devices/MKW41Z4/
Dfsl_clock.c108 #define MCG_C5_PLLREFSEL0_VAL ((MCG->C5 & MCG_C5_PLLREFSEL0_MASK) >> MCG_C5_PLLREFSEL0_SHIFT)
112 #define MCG_C5_PRDIV0_VAL ((MCG->C5 & MCG_C5_PRDIV0_MASK) >> MCG_C5_PRDIV0_SHIFT)

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