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/hal_nxp-2.7.6/mcux/devices/MKW41Z4/
Dfsl_clock.c105 #define MCG_C4_DMX32_VAL ((MCG->C4 & MCG_C4_DMX32_MASK) >> MCG_C4_DMX32_SHIFT)
106 #define MCG_C4_DRST_DRS_VAL ((MCG->C4 & MCG_C4_DRST_DRS_MASK) >> MCG_C4_DRST_DRS_SHIFT)
909 mcg_c4 = MCG->C4; in CLOCK_SetFeiMode()
921 MCG->C4 ^= (1U << MCG_C4_DRST_DRS_SHIFT); in CLOCK_SetFeiMode()
937 MCG->C4 = mcg_c4; in CLOCK_SetFeiMode()
941 …MCG->C4 = (mcg_c4 & ~(MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS_MASK)) | (MCG_C4_DMX32(dmx32) | MCG_C4_D… in CLOCK_SetFeiMode()
969 mcg_c4 = MCG->C4; in CLOCK_SetFeeMode()
981 MCG->C4 ^= (1U << MCG_C4_DRST_DRS_SHIFT); in CLOCK_SetFeeMode()
1009 MCG->C4 = mcg_c4; in CLOCK_SetFeeMode()
1014 MCG->C4 = mcg_c4; in CLOCK_SetFeeMode()
[all …]
Dsystem_MKW41Z4.c131 switch (MCG->C4 & (MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS_MASK)) { in SystemCoreClockUpdate()
/hal_nxp-2.7.6/mcux/devices/MKW30Z4/
Dsystem_MKW30Z4.c132 …MCG->C4 = (MCG->C4 & ~(MCG_C4_SCFTRIM_MASK)) | ((*((uint8_t*) SLOW_FINE_TRIM_ADDRESS)) & MCG_C4_SC… in SystemInit()
135 …MCG->C4 = (MCG->C4 & ~(MCG_C4_FCTRIM_MASK)) |((*((uint8_t*) FAST_TRIM_ADDRESS)) & MCG_C4_FCTRIM_MA… in SystemInit()
161 …MCG->C4 = ((SYSTEM_MCG_C4_VALUE) & (uint8_t)(~(MCG_C4_FCTRIM_MASK | MCG_C4_SCFTRIM_MASK))) | (MCG-… in SystemInit()
182 …MCG->C4 = ((SYSTEM_MCG_C4_VALUE) & (uint8_t)(~(MCG_C4_FCTRIM_MASK | MCG_C4_SCFTRIM_MASK))) | (MCG… in SystemInit()
247 switch (MCG->C4 & (MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS_MASK)) { in SystemCoreClockUpdate()
/hal_nxp-2.7.6/mcux/devices/MKW20Z4/
Dsystem_MKW20Z4.c132 …MCG->C4 = (MCG->C4 & ~(MCG_C4_SCFTRIM_MASK)) | ((*((uint8_t*) SLOW_FINE_TRIM_ADDRESS)) & MCG_C4_SC… in SystemInit()
135 …MCG->C4 = (MCG->C4 & ~(MCG_C4_FCTRIM_MASK)) |((*((uint8_t*) FAST_TRIM_ADDRESS)) & MCG_C4_FCTRIM_MA… in SystemInit()
161 …MCG->C4 = ((SYSTEM_MCG_C4_VALUE) & (uint8_t)(~(MCG_C4_FCTRIM_MASK | MCG_C4_SCFTRIM_MASK))) | (MCG-… in SystemInit()
182 …MCG->C4 = ((SYSTEM_MCG_C4_VALUE) & (uint8_t)(~(MCG_C4_FCTRIM_MASK | MCG_C4_SCFTRIM_MASK))) | (MCG… in SystemInit()
247 switch (MCG->C4 & (MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS_MASK)) { in SystemCoreClockUpdate()
/hal_nxp-2.7.6/mcux/devices/MKW40Z4/
Dsystem_MKW40Z4.c132 …MCG->C4 = (MCG->C4 & ~(MCG_C4_SCFTRIM_MASK)) | ((*((uint8_t*) SLOW_FINE_TRIM_ADDRESS)) & MCG_C4_SC… in SystemInit()
135 …MCG->C4 = (MCG->C4 & ~(MCG_C4_FCTRIM_MASK)) |((*((uint8_t*) FAST_TRIM_ADDRESS)) & MCG_C4_FCTRIM_MA… in SystemInit()
161 …MCG->C4 = ((SYSTEM_MCG_C4_VALUE) & (uint8_t)(~(MCG_C4_FCTRIM_MASK | MCG_C4_SCFTRIM_MASK))) | (MCG-… in SystemInit()
182 …MCG->C4 = ((SYSTEM_MCG_C4_VALUE) & (uint8_t)(~(MCG_C4_FCTRIM_MASK | MCG_C4_SCFTRIM_MASK))) | (MCG… in SystemInit()
247 switch (MCG->C4 & (MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS_MASK)) { in SystemCoreClockUpdate()
/hal_nxp-2.7.6/mcux/devices/MKL25Z4/
Dfsl_clock.c77 #define MCG_C4_DMX32_VAL ((MCG->C4 & MCG_C4_DMX32_MASK) >> MCG_C4_DMX32_SHIFT)
78 #define MCG_C4_DRST_DRS_VAL ((MCG->C4 & MCG_C4_DRST_DRS_MASK) >> MCG_C4_DRST_DRS_SHIFT)
1077 mcg_c4 = MCG->C4; in CLOCK_SetFeiMode()
1089 MCG->C4 ^= (1U << MCG_C4_DRST_DRS_SHIFT); in CLOCK_SetFeiMode()
1105 MCG->C4 = mcg_c4; in CLOCK_SetFeiMode()
1109 …MCG->C4 = (mcg_c4 & ~(MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS_MASK)) | (MCG_C4_DMX32(dmx32) | MCG_C4_D… in CLOCK_SetFeiMode()
1137 mcg_c4 = MCG->C4; in CLOCK_SetFeeMode()
1149 MCG->C4 ^= (1U << MCG_C4_DRST_DRS_SHIFT); in CLOCK_SetFeeMode()
1176 MCG->C4 = mcg_c4; in CLOCK_SetFeeMode()
1181 MCG->C4 = mcg_c4; in CLOCK_SetFeeMode()
[all …]
Dsystem_MKL25Z4.c164 switch (MCG->C4 & (MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS_MASK)) { in SystemCoreClockUpdate()
/hal_nxp-2.7.6/mcux/devices/MKW22D5/
Dfsl_clock.c77 #define MCG_C4_DMX32_VAL ((MCG->C4 & MCG_C4_DMX32_MASK) >> MCG_C4_DMX32_SHIFT)
78 #define MCG_C4_DRST_DRS_VAL ((MCG->C4 & MCG_C4_DRST_DRS_MASK) >> MCG_C4_DRST_DRS_SHIFT)
1160 mcg_c4 = MCG->C4; in CLOCK_SetFeiMode()
1172 MCG->C4 ^= (1U << MCG_C4_DRST_DRS_SHIFT); in CLOCK_SetFeiMode()
1188 MCG->C4 = mcg_c4; in CLOCK_SetFeiMode()
1192 …MCG->C4 = (mcg_c4 & ~(MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS_MASK)) | (MCG_C4_DMX32(dmx32) | MCG_C4_D… in CLOCK_SetFeiMode()
1220 mcg_c4 = MCG->C4; in CLOCK_SetFeeMode()
1232 MCG->C4 ^= (1U << MCG_C4_DRST_DRS_SHIFT); in CLOCK_SetFeeMode()
1260 MCG->C4 = mcg_c4; in CLOCK_SetFeeMode()
1265 MCG->C4 = mcg_c4; in CLOCK_SetFeeMode()
[all …]
/hal_nxp-2.7.6/mcux/devices/MKW24D5/
Dfsl_clock.c77 #define MCG_C4_DMX32_VAL ((MCG->C4 & MCG_C4_DMX32_MASK) >> MCG_C4_DMX32_SHIFT)
78 #define MCG_C4_DRST_DRS_VAL ((MCG->C4 & MCG_C4_DRST_DRS_MASK) >> MCG_C4_DRST_DRS_SHIFT)
1160 mcg_c4 = MCG->C4; in CLOCK_SetFeiMode()
1172 MCG->C4 ^= (1U << MCG_C4_DRST_DRS_SHIFT); in CLOCK_SetFeiMode()
1188 MCG->C4 = mcg_c4; in CLOCK_SetFeiMode()
1192 …MCG->C4 = (mcg_c4 & ~(MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS_MASK)) | (MCG_C4_DMX32(dmx32) | MCG_C4_D… in CLOCK_SetFeiMode()
1220 mcg_c4 = MCG->C4; in CLOCK_SetFeeMode()
1232 MCG->C4 ^= (1U << MCG_C4_DRST_DRS_SHIFT); in CLOCK_SetFeeMode()
1260 MCG->C4 = mcg_c4; in CLOCK_SetFeeMode()
1265 MCG->C4 = mcg_c4; in CLOCK_SetFeeMode()
[all …]
/hal_nxp-2.7.6/mcux/devices/MKV58F24/
Dfsl_clock.c59 #define MCG_C4_DMX32_VAL ((MCG->C4 & MCG_C4_DMX32_MASK) >> MCG_C4_DMX32_SHIFT)
60 #define MCG_C4_DRST_DRS_VAL ((MCG->C4 & MCG_C4_DRST_DRS_MASK) >> MCG_C4_DRST_DRS_SHIFT)
1396 mcg_c4 = MCG->C4; in CLOCK_SetFeiMode()
1408 MCG->C4 ^= (1U << MCG_C4_DRST_DRS_SHIFT); in CLOCK_SetFeiMode()
1424 MCG->C4 = mcg_c4; in CLOCK_SetFeiMode()
1428 MCG->C4 = (uint8_t)((mcg_c4 & ~(MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS_MASK)) | in CLOCK_SetFeiMode()
1472 mcg_c4 = MCG->C4; in CLOCK_SetFeeMode()
1484 MCG->C4 ^= (1U << MCG_C4_DRST_DRS_SHIFT); in CLOCK_SetFeeMode()
1511 MCG->C4 = mcg_c4; in CLOCK_SetFeeMode()
1517 MCG->C4 = mcg_c4; in CLOCK_SetFeeMode()
[all …]
Dsystem_MKV58F24.c141 switch (MCG->C4 & (MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS_MASK)) { in SystemCoreClockUpdate()
/hal_nxp-2.7.6/mcux/devices/MKV56F24/
Dfsl_clock.c59 #define MCG_C4_DMX32_VAL ((MCG->C4 & MCG_C4_DMX32_MASK) >> MCG_C4_DMX32_SHIFT)
60 #define MCG_C4_DRST_DRS_VAL ((MCG->C4 & MCG_C4_DRST_DRS_MASK) >> MCG_C4_DRST_DRS_SHIFT)
1396 mcg_c4 = MCG->C4; in CLOCK_SetFeiMode()
1408 MCG->C4 ^= (1U << MCG_C4_DRST_DRS_SHIFT); in CLOCK_SetFeiMode()
1424 MCG->C4 = mcg_c4; in CLOCK_SetFeiMode()
1428 MCG->C4 = (uint8_t)((mcg_c4 & ~(MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS_MASK)) | in CLOCK_SetFeiMode()
1472 mcg_c4 = MCG->C4; in CLOCK_SetFeeMode()
1484 MCG->C4 ^= (1U << MCG_C4_DRST_DRS_SHIFT); in CLOCK_SetFeeMode()
1511 MCG->C4 = mcg_c4; in CLOCK_SetFeeMode()
1517 MCG->C4 = mcg_c4; in CLOCK_SetFeeMode()
[all …]
Dsystem_MKV56F24.c141 switch (MCG->C4 & (MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS_MASK)) { in SystemCoreClockUpdate()
/hal_nxp-2.7.6/mcux/devices/MK22F51212/
Dfsl_clock.c59 #define MCG_C4_DMX32_VAL ((MCG->C4 & MCG_C4_DMX32_MASK) >> MCG_C4_DMX32_SHIFT)
60 #define MCG_C4_DRST_DRS_VAL ((MCG->C4 & MCG_C4_DRST_DRS_MASK) >> MCG_C4_DRST_DRS_SHIFT)
1538 mcg_c4 = MCG->C4; in CLOCK_SetFeiMode()
1550 MCG->C4 ^= (1U << MCG_C4_DRST_DRS_SHIFT); in CLOCK_SetFeiMode()
1566 MCG->C4 = mcg_c4; in CLOCK_SetFeiMode()
1570 MCG->C4 = (uint8_t)((mcg_c4 & ~(MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS_MASK)) | in CLOCK_SetFeiMode()
1614 mcg_c4 = MCG->C4; in CLOCK_SetFeeMode()
1626 MCG->C4 ^= (1U << MCG_C4_DRST_DRS_SHIFT); in CLOCK_SetFeeMode()
1654 MCG->C4 = mcg_c4; in CLOCK_SetFeeMode()
1660 MCG->C4 = mcg_c4; in CLOCK_SetFeeMode()
[all …]
Dsystem_MK22F51212.c167 switch (MCG->C4 & (MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS_MASK)) { in SystemCoreClockUpdate()
/hal_nxp-2.7.6/mcux/devices/MK64F12/
Dfsl_clock.c59 #define MCG_C4_DMX32_VAL ((MCG->C4 & MCG_C4_DMX32_MASK) >> MCG_C4_DMX32_SHIFT)
60 #define MCG_C4_DRST_DRS_VAL ((MCG->C4 & MCG_C4_DRST_DRS_MASK) >> MCG_C4_DRST_DRS_SHIFT)
1505 mcg_c4 = MCG->C4; in CLOCK_SetFeiMode()
1517 MCG->C4 ^= (1U << MCG_C4_DRST_DRS_SHIFT); in CLOCK_SetFeiMode()
1533 MCG->C4 = mcg_c4; in CLOCK_SetFeiMode()
1537 MCG->C4 = (uint8_t)((mcg_c4 & ~(MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS_MASK)) | in CLOCK_SetFeiMode()
1581 mcg_c4 = MCG->C4; in CLOCK_SetFeeMode()
1593 MCG->C4 ^= (1U << MCG_C4_DRST_DRS_SHIFT); in CLOCK_SetFeeMode()
1621 MCG->C4 = mcg_c4; in CLOCK_SetFeeMode()
1627 MCG->C4 = mcg_c4; in CLOCK_SetFeeMode()
[all …]
Dsystem_MK64F12.c171 switch (MCG->C4 & (MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS_MASK)) { in SystemCoreClockUpdate()
/hal_nxp-2.7.6/mcux/devices/MK80F25615/
Dfsl_clock.c59 #define MCG_C4_DMX32_VAL ((MCG->C4 & MCG_C4_DMX32_MASK) >> MCG_C4_DMX32_SHIFT)
60 #define MCG_C4_DRST_DRS_VAL ((MCG->C4 & MCG_C4_DRST_DRS_MASK) >> MCG_C4_DRST_DRS_SHIFT)
1547 mcg_c4 = MCG->C4; in CLOCK_SetFeiMode()
1559 MCG->C4 ^= (1U << MCG_C4_DRST_DRS_SHIFT); in CLOCK_SetFeiMode()
1575 MCG->C4 = mcg_c4; in CLOCK_SetFeiMode()
1579 MCG->C4 = (uint8_t)((mcg_c4 & ~(MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS_MASK)) | in CLOCK_SetFeiMode()
1623 mcg_c4 = MCG->C4; in CLOCK_SetFeeMode()
1635 MCG->C4 ^= (1U << MCG_C4_DRST_DRS_SHIFT); in CLOCK_SetFeeMode()
1663 MCG->C4 = mcg_c4; in CLOCK_SetFeeMode()
1669 MCG->C4 = mcg_c4; in CLOCK_SetFeeMode()
[all …]
/hal_nxp-2.7.6/mcux/devices/MK82F25615/
Dfsl_clock.c59 #define MCG_C4_DMX32_VAL ((MCG->C4 & MCG_C4_DMX32_MASK) >> MCG_C4_DMX32_SHIFT)
60 #define MCG_C4_DRST_DRS_VAL ((MCG->C4 & MCG_C4_DRST_DRS_MASK) >> MCG_C4_DRST_DRS_SHIFT)
1547 mcg_c4 = MCG->C4; in CLOCK_SetFeiMode()
1559 MCG->C4 ^= (1U << MCG_C4_DRST_DRS_SHIFT); in CLOCK_SetFeiMode()
1575 MCG->C4 = mcg_c4; in CLOCK_SetFeiMode()
1579 MCG->C4 = (uint8_t)((mcg_c4 & ~(MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS_MASK)) | in CLOCK_SetFeiMode()
1623 mcg_c4 = MCG->C4; in CLOCK_SetFeeMode()
1635 MCG->C4 ^= (1U << MCG_C4_DRST_DRS_SHIFT); in CLOCK_SetFeeMode()
1663 MCG->C4 = mcg_c4; in CLOCK_SetFeeMode()
1669 MCG->C4 = mcg_c4; in CLOCK_SetFeeMode()
[all …]
/hal_nxp-2.7.6/mcux/drivers/kinetis/
Dfsl_uart.h373 base->C4 |= (uint8_t)UART_C4_MAEN1_MASK; in UART_EnableMatchAddress()
377 base->C4 &= ~(uint8_t)UART_C4_MAEN1_MASK; in UART_EnableMatchAddress()
382 base->C4 |= (uint8_t)UART_C4_MAEN2_MASK; in UART_EnableMatchAddress()
386 base->C4 &= ~(uint8_t)UART_C4_MAEN2_MASK; in UART_EnableMatchAddress()
549 base->C4 |= (uint8_t)UART_C4_TDMAS_MASK; in UART_EnableTxDMA()
558 base->C4 &= ~(uint8_t)UART_C4_TDMAS_MASK; in UART_EnableTxDMA()
579 base->C4 |= (uint8_t)UART_C4_RDMAS_MASK; in UART_EnableRxDMA()
588 base->C4 &= ~(uint8_t)UART_C4_RDMAS_MASK; in UART_EnableRxDMA()
Dfsl_lpsci.c286 base->C4 = ((base->C4 & ~UART0_C4_OSR_MASK) | (osr - 1)); in LPSCI_Init()
289 base->BDH = ((base->C4 & ~UART0_BDH_SBR_MASK) | (uint8_t)(sbr >> 8)); in LPSCI_Init()
413 base->C4 = ((base->C4 & ~UART0_C4_OSR_MASK) | (osr - 1)); in LPSCI_SetBaudRate()
416 base->BDH = ((base->C4 & ~UART0_BDH_SBR_MASK) | (uint8_t)(sbr >> 8)); in LPSCI_SetBaudRate()
Dfsl_uart.c280 base->C4 = (base->C4 & ~(uint8_t)UART_C4_BRFA_MASK) | ((uint8_t)brfa & UART_C4_BRFA_MASK); in UART_Init()
491 …base->C4 = (base->C4 & ~(uint8_t)UART_C4_BRFA_MASK) | ((uint8_t)brfa & (uint8_t)UART_C4_BRFA_MASK); in UART_SetBaudRate()
/hal_nxp-2.7.6/mcux/devices/MK66F18/
Dfsl_clock.c59 #define MCG_C4_DMX32_VAL ((MCG->C4 & MCG_C4_DMX32_MASK) >> MCG_C4_DMX32_SHIFT)
60 #define MCG_C4_DRST_DRS_VAL ((MCG->C4 & MCG_C4_DRST_DRS_MASK) >> MCG_C4_DRST_DRS_SHIFT)
1815 mcg_c4 = MCG->C4; in CLOCK_SetFeiMode()
1827 MCG->C4 ^= (1U << MCG_C4_DRST_DRS_SHIFT); in CLOCK_SetFeiMode()
1843 MCG->C4 = mcg_c4; in CLOCK_SetFeiMode()
1847 MCG->C4 = (uint8_t)((mcg_c4 & ~(MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS_MASK)) | in CLOCK_SetFeiMode()
1891 mcg_c4 = MCG->C4; in CLOCK_SetFeeMode()
1903 MCG->C4 ^= (1U << MCG_C4_DRST_DRS_SHIFT); in CLOCK_SetFeeMode()
1931 MCG->C4 = mcg_c4; in CLOCK_SetFeeMode()
1937 MCG->C4 = mcg_c4; in CLOCK_SetFeeMode()
[all …]
/hal_nxp-2.7.6/mcux/devices/MKW21Z4/
Dsystem_MKW21Z4.c130 switch (MCG->C4 & (MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS_MASK)) { in SystemCoreClockUpdate()
/hal_nxp-2.7.6/mcux/devices/MKW31Z4/
Dsystem_MKW31Z4.c131 switch (MCG->C4 & (MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS_MASK)) { in SystemCoreClockUpdate()

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