Searched refs:SPI_FIFO_RXTO_INT_MASK (Results 1 – 6 of 6) sorted by relevance
683 if((u32Mask & SPI_FIFO_RXTO_INT_MASK) == SPI_FIFO_RXTO_INT_MASK) in SPI_EnableInt()766 if((u32Mask & SPI_FIFO_RXTO_INT_MASK) == SPI_FIFO_RXTO_INT_MASK) in SPI_DisableInt()861 if((u32Mask & SPI_FIFO_RXTO_INT_MASK) && (u32TmpVal)) in SPI_GetIntFlag()863 u32IntFlag |= SPI_FIFO_RXTO_INT_MASK; in SPI_GetIntFlag()924 if(u32Mask & SPI_FIFO_RXTO_INT_MASK) in SPI_ClearIntFlag()
684 if((u32Mask & SPI_FIFO_RXTO_INT_MASK) == SPI_FIFO_RXTO_INT_MASK) in SPI_EnableInt()767 if((u32Mask & SPI_FIFO_RXTO_INT_MASK) == SPI_FIFO_RXTO_INT_MASK) in SPI_DisableInt()862 if((u32Mask & SPI_FIFO_RXTO_INT_MASK) && (u32TmpVal)) in SPI_GetIntFlag()864 u32IntFlag |= SPI_FIFO_RXTO_INT_MASK; in SPI_GetIntFlag()925 if(u32Mask & SPI_FIFO_RXTO_INT_MASK) in SPI_ClearIntFlag()
1294 if((u32Mask & SPI_FIFO_RXTO_INT_MASK) == SPI_FIFO_RXTO_INT_MASK) in SPI_EnableInt()1377 if((u32Mask & SPI_FIFO_RXTO_INT_MASK) == SPI_FIFO_RXTO_INT_MASK) in SPI_DisableInt()1472 if((u32Mask & SPI_FIFO_RXTO_INT_MASK) && (u32TmpVal)) in SPI_GetIntFlag()1474 u32IntFlag |= SPI_FIFO_RXTO_INT_MASK; in SPI_GetIntFlag()1535 if(u32Mask & SPI_FIFO_RXTO_INT_MASK) in SPI_ClearIntFlag()
52 #define SPI_FIFO_RXTO_INT_MASK (0x400U) /*!< FIFO RX time-out in… macro
