1 /**************************************************************************//**
2 * @file spi.h
3 * @version V3.00
4 * @brief M480 series SPI driver header file
5 *
6 * SPDX-License-Identifier: Apache-2.0
7 * @copyright (C) 2016-2020 Nuvoton Technology Corp. All rights reserved.
8 *****************************************************************************/
9 #ifndef __SPI_H__
10 #define __SPI_H__
11
12 #ifdef __cplusplus
13 extern "C"
14 {
15 #endif
16
17
18 /** @addtogroup Standard_Driver Standard Driver
19 @{
20 */
21
22 /** @addtogroup SPI_Driver SPI Driver
23 @{
24 */
25
26 /** @addtogroup SPI_EXPORTED_CONSTANTS SPI Exported Constants
27 @{
28 */
29
30 #define SPI_MODE_0 (SPI_CTL_TXNEG_Msk) /*!< CLKPOL=0; RXNEG=0; TXNEG=1 \hideinitializer */
31 #define SPI_MODE_1 (SPI_CTL_RXNEG_Msk) /*!< CLKPOL=0; RXNEG=1; TXNEG=0 \hideinitializer */
32 #define SPI_MODE_2 (SPI_CTL_CLKPOL_Msk | SPI_CTL_RXNEG_Msk) /*!< CLKPOL=1; RXNEG=1; TXNEG=0 \hideinitializer */
33 #define SPI_MODE_3 (SPI_CTL_CLKPOL_Msk | SPI_CTL_TXNEG_Msk) /*!< CLKPOL=1; RXNEG=0; TXNEG=1 \hideinitializer */
34
35 #define SPI_SLAVE (SPI_CTL_SLAVE_Msk) /*!< Set as slave \hideinitializer */
36 #define SPI_MASTER (0x0U) /*!< Set as master \hideinitializer */
37
38 #define SPI_SS (SPI_SSCTL_SS_Msk) /*!< Set SS \hideinitializer */
39 #define SPI_SS_ACTIVE_HIGH (SPI_SSCTL_SSACTPOL_Msk) /*!< SS active high \hideinitializer */
40 #define SPI_SS_ACTIVE_LOW (0x0U) /*!< SS active low \hideinitializer */
41
42 /* SPI Interrupt Mask */
43 #define SPI_UNIT_INT_MASK (0x001U) /*!< Unit transfer interrupt mask \hideinitializer */
44 #define SPI_SSACT_INT_MASK (0x002U) /*!< Slave selection signal active interrupt mask \hideinitializer */
45 #define SPI_SSINACT_INT_MASK (0x004U) /*!< Slave selection signal inactive interrupt mask \hideinitializer */
46 #define SPI_SLVUR_INT_MASK (0x008U) /*!< Slave under run interrupt mask \hideinitializer */
47 #define SPI_SLVBE_INT_MASK (0x010U) /*!< Slave bit count error interrupt mask \hideinitializer */
48 #define SPI_TXUF_INT_MASK (0x040U) /*!< Slave TX underflow interrupt mask \hideinitializer */
49 #define SPI_FIFO_TXTH_INT_MASK (0x080U) /*!< FIFO TX threshold interrupt mask \hideinitializer */
50 #define SPI_FIFO_RXTH_INT_MASK (0x100U) /*!< FIFO RX threshold interrupt mask \hideinitializer */
51 #define SPI_FIFO_RXOV_INT_MASK (0x200U) /*!< FIFO RX overrun interrupt mask \hideinitializer */
52 #define SPI_FIFO_RXTO_INT_MASK (0x400U) /*!< FIFO RX time-out interrupt mask \hideinitializer */
53
54 /* SPI Status Mask */
55 #define SPI_BUSY_MASK (0x01U) /*!< Busy status mask \hideinitializer */
56 #define SPI_RX_EMPTY_MASK (0x02U) /*!< RX empty status mask \hideinitializer */
57 #define SPI_RX_FULL_MASK (0x04U) /*!< RX full status mask \hideinitializer */
58 #define SPI_TX_EMPTY_MASK (0x08U) /*!< TX empty status mask \hideinitializer */
59 #define SPI_TX_FULL_MASK (0x10U) /*!< TX full status mask \hideinitializer */
60 #define SPI_TXRX_RESET_MASK (0x20U) /*!< TX or RX reset status mask \hideinitializer */
61 #define SPI_SPIEN_STS_MASK (0x40U) /*!< SPIEN status mask \hideinitializer */
62 #define SPI_SSLINE_STS_MASK (0x80U) /*!< SPIx_SS line status mask \hideinitializer */
63
64
65 /* I2S Data Width */
66 #define SPII2S_DATABIT_8 (0U << SPI_I2SCTL_WDWIDTH_Pos) /*!< I2S data width is 8-bit \hideinitializer */
67 #define SPII2S_DATABIT_16 (1U << SPI_I2SCTL_WDWIDTH_Pos) /*!< I2S data width is 16-bit \hideinitializer */
68 #define SPII2S_DATABIT_24 (2U << SPI_I2SCTL_WDWIDTH_Pos) /*!< I2S data width is 24-bit \hideinitializer */
69 #define SPII2S_DATABIT_32 (3U << SPI_I2SCTL_WDWIDTH_Pos) /*!< I2S data width is 32-bit \hideinitializer */
70
71 /* I2S Audio Format */
72 #define SPII2S_MONO SPI_I2SCTL_MONO_Msk /*!< Monaural channel \hideinitializer */
73 #define SPII2S_STEREO (0U) /*!< Stereo channel \hideinitializer */
74
75 /* I2S Data Format */
76 #define SPII2S_FORMAT_I2S (0U<<SPI_I2SCTL_FORMAT_Pos) /*!< I2S data format \hideinitializer */
77 #define SPII2S_FORMAT_MSB (1U<<SPI_I2SCTL_FORMAT_Pos) /*!< MSB justified data format \hideinitializer */
78 #define SPII2S_FORMAT_PCMA (2U<<SPI_I2SCTL_FORMAT_Pos) /*!< PCM mode A data format \hideinitializer */
79 #define SPII2S_FORMAT_PCMB (3U<<SPI_I2SCTL_FORMAT_Pos) /*!< PCM mode B data format \hideinitializer */
80
81 /* I2S Operation mode */
82 #define SPII2S_MODE_SLAVE SPI_I2SCTL_SLAVE_Msk /*!< As slave mode \hideinitializer */
83 #define SPII2S_MODE_MASTER (0U) /*!< As master mode \hideinitializer */
84
85 /* I2S TX FIFO Threshold */
86 #define SPII2S_FIFO_TX_LEVEL_WORD_0 (0U) /*!< TX threshold is 0 word \hideinitializer */
87 #define SPII2S_FIFO_TX_LEVEL_WORD_1 (1U << SPI_FIFOCTL_TXTH_Pos) /*!< TX threshold is 1 word \hideinitializer */
88 #define SPII2S_FIFO_TX_LEVEL_WORD_2 (2U << SPI_FIFOCTL_TXTH_Pos) /*!< TX threshold is 2 words \hideinitializer */
89 #define SPII2S_FIFO_TX_LEVEL_WORD_3 (3U << SPI_FIFOCTL_TXTH_Pos) /*!< TX threshold is 3 words \hideinitializer */
90 /* I2S RX FIFO Threshold */
91 #define SPII2S_FIFO_RX_LEVEL_WORD_1 (0U) /*!< RX threshold is 1 word \hideinitializer */
92 #define SPII2S_FIFO_RX_LEVEL_WORD_2 (1U << SPI_FIFOCTL_RXTH_Pos) /*!< RX threshold is 2 words \hideinitializer */
93 #define SPII2S_FIFO_RX_LEVEL_WORD_3 (2U << SPI_FIFOCTL_RXTH_Pos) /*!< RX threshold is 3 words \hideinitializer */
94 #define SPII2S_FIFO_RX_LEVEL_WORD_4 (3U << SPI_FIFOCTL_RXTH_Pos) /*!< RX threshold is 4 words \hideinitializer */
95
96 /* I2S Record Channel */
97 #define SPII2S_MONO_RIGHT (0U) /*!< Record mono right channel \hideinitializer */
98 #define SPII2S_MONO_LEFT SPI_I2SCTL_RXLCH_Msk /*!< Record mono left channel \hideinitializer */
99
100 /* I2S Channel */
101 #define SPII2S_RIGHT (0U) /*!< Select right channel \hideinitializer */
102 #define SPII2S_LEFT (1U) /*!< Select left channel \hideinitializer */
103
104 /* I2S Interrupt Mask */
105 #define SPII2S_FIFO_TXTH_INT_MASK (0x01U) /*!< TX FIFO threshold interrupt mask \hideinitializer */
106 #define SPII2S_FIFO_RXTH_INT_MASK (0x02U) /*!< RX FIFO threshold interrupt mask \hideinitializer */
107 #define SPII2S_FIFO_RXOV_INT_MASK (0x04U) /*!< RX FIFO overrun interrupt mask \hideinitializer */
108 #define SPII2S_FIFO_RXTO_INT_MASK (0x08U) /*!< RX FIFO time-out interrupt mask \hideinitializer */
109 #define SPII2S_TXUF_INT_MASK (0x10U) /*!< TX FIFO underflow interrupt mask \hideinitializer */
110 #define SPII2S_RIGHT_ZC_INT_MASK (0x20U) /*!< Right channel zero cross interrupt mask \hideinitializer */
111 #define SPII2S_LEFT_ZC_INT_MASK (0x40U) /*!< Left channel zero cross interrupt mask \hideinitializer */
112
113 /*@}*/ /* end of group SPI_EXPORTED_CONSTANTS */
114
115
116 /** @addtogroup SPI_EXPORTED_FUNCTIONS SPI Exported Functions
117 @{
118 */
119
120 /**
121 * @brief Clear the unit transfer interrupt flag.
122 * @param[in] spi The pointer of the specified SPI module.
123 * @return None.
124 * @details Write 1 to UNITIF bit of SPI_STATUS register to clear the unit transfer interrupt flag.
125 * \hideinitializer
126 */
127 #define SPI_CLR_UNIT_TRANS_INT_FLAG(spi) ((spi)->STATUS = SPI_STATUS_UNITIF_Msk)
128
129 /**
130 * @brief Trigger RX PDMA function.
131 * @param[in] spi The pointer of the specified SPI module.
132 * @return None.
133 * @details Set RXPDMAEN bit of SPI_PDMACTL register to enable RX PDMA transfer function.
134 * \hideinitializer
135 */
136 #define SPI_TRIGGER_RX_PDMA(spi) ((spi)->PDMACTL |= SPI_PDMACTL_RXPDMAEN_Msk)
137
138 /**
139 * @brief Trigger TX PDMA function.
140 * @param[in] spi The pointer of the specified SPI module.
141 * @return None.
142 * @details Set TXPDMAEN bit of SPI_PDMACTL register to enable TX PDMA transfer function.
143 * \hideinitializer
144 */
145 #define SPI_TRIGGER_TX_PDMA(spi) ((spi)->PDMACTL |= SPI_PDMACTL_TXPDMAEN_Msk)
146
147 /**
148 * @brief Disable RX PDMA transfer.
149 * @param[in] spi The pointer of the specified SPI module.
150 * @return None.
151 * @details Clear RXPDMAEN bit of SPI_PDMACTL register to disable RX PDMA transfer function.
152 * \hideinitializer
153 */
154 #define SPI_DISABLE_RX_PDMA(spi) ( (spi)->PDMACTL &= ~SPI_PDMACTL_RXPDMAEN_Msk )
155
156 /**
157 * @brief Disable TX PDMA transfer.
158 * @param[in] spi The pointer of the specified SPI module.
159 * @return None.
160 * @details Clear TXPDMAEN bit of SPI_PDMACTL register to disable TX PDMA transfer function.
161 * \hideinitializer
162 */
163 #define SPI_DISABLE_TX_PDMA(spi) ( (spi)->PDMACTL &= ~SPI_PDMACTL_TXPDMAEN_Msk )
164
165 /**
166 * @brief Get the count of available data in RX FIFO.
167 * @param[in] spi The pointer of the specified SPI module.
168 * @return The count of available data in RX FIFO.
169 * @details Read RXCNT (SPI_STATUS[27:24]) to get the count of available data in RX FIFO.
170 * \hideinitializer
171 */
172 #define SPI_GET_RX_FIFO_COUNT(spi) (((spi)->STATUS & SPI_STATUS_RXCNT_Msk) >> SPI_STATUS_RXCNT_Pos)
173
174 /**
175 * @brief Get the RX FIFO empty flag.
176 * @param[in] spi The pointer of the specified SPI module.
177 * @retval 0 RX FIFO is not empty.
178 * @retval 1 RX FIFO is empty.
179 * @details Read RXEMPTY bit of SPI_STATUS register to get the RX FIFO empty flag.
180 * \hideinitializer
181 */
182 #define SPI_GET_RX_FIFO_EMPTY_FLAG(spi) (((spi)->STATUS & SPI_STATUS_RXEMPTY_Msk)>>SPI_STATUS_RXEMPTY_Pos)
183
184 /**
185 * @brief Get the TX FIFO empty flag.
186 * @param[in] spi The pointer of the specified SPI module.
187 * @retval 0 TX FIFO is not empty.
188 * @retval 1 TX FIFO is empty.
189 * @details Read TXEMPTY bit of SPI_STATUS register to get the TX FIFO empty flag.
190 * \hideinitializer
191 */
192 #define SPI_GET_TX_FIFO_EMPTY_FLAG(spi) (((spi)->STATUS & SPI_STATUS_TXEMPTY_Msk)>>SPI_STATUS_TXEMPTY_Pos)
193
194 /**
195 * @brief Get the TX FIFO full flag.
196 * @param[in] spi The pointer of the specified SPI module.
197 * @retval 0 TX FIFO is not full.
198 * @retval 1 TX FIFO is full.
199 * @details Read TXFULL bit of SPI_STATUS register to get the TX FIFO full flag.
200 * \hideinitializer
201 */
202 #define SPI_GET_TX_FIFO_FULL_FLAG(spi) (((spi)->STATUS & SPI_STATUS_TXFULL_Msk)>>SPI_STATUS_TXFULL_Pos)
203
204 /**
205 * @brief Get the datum read from RX register.
206 * @param[in] spi The pointer of the specified SPI module.
207 * @return Data in RX register.
208 * @details Read SPI_RX register to get the received datum.
209 * \hideinitializer
210 */
211 #define SPI_READ_RX(spi) ((spi)->RX)
212
213 /**
214 * @brief Write datum to TX register.
215 * @param[in] spi The pointer of the specified SPI module.
216 * @param[in] u32TxData The datum which user attempt to transfer through SPI bus.
217 * @return None.
218 * @details Write u32TxData to SPI_TX register.
219 * \hideinitializer
220 */
221 #define SPI_WRITE_TX(spi, u32TxData) ((spi)->TX = (u32TxData))
222
223 /**
224 * @brief Set SPIx_SS pin to high state.
225 * @param[in] spi The pointer of the specified SPI module.
226 * @return None.
227 * @details Disable automatic slave selection function and set SPIx_SS pin to high state.
228 * \hideinitializer
229 */
230 #define SPI_SET_SS_HIGH(spi) ((spi)->SSCTL = ((spi)->SSCTL & (~SPI_SSCTL_AUTOSS_Msk)) | (SPI_SSCTL_SSACTPOL_Msk | SPI_SSCTL_SS_Msk))
231
232 /**
233 * @brief Set SPIx_SS pin to low state.
234 * @param[in] spi The pointer of the specified SPI module.
235 * @return None.
236 * @details Disable automatic slave selection function and set SPIx_SS pin to low state.
237 * \hideinitializer
238 */
239 #define SPI_SET_SS_LOW(spi) ((spi)->SSCTL = ((spi)->SSCTL & (~(SPI_SSCTL_AUTOSS_Msk | SPI_SSCTL_SSACTPOL_Msk))) | SPI_SSCTL_SS_Msk)
240
241 /**
242 * @brief Enable Byte Reorder function.
243 * @param[in] spi The pointer of the specified SPI module.
244 * @return None.
245 * @details Enable Byte Reorder function. The suspend interval depends on the setting of SUSPITV (SPI_CTL[7:4]).
246 * \hideinitializer
247 */
248 #define SPI_ENABLE_BYTE_REORDER(spi) ((spi)->CTL |= SPI_CTL_REORDER_Msk)
249
250 /**
251 * @brief Disable Byte Reorder function.
252 * @param[in] spi The pointer of the specified SPI module.
253 * @return None.
254 * @details Clear REORDER bit field of SPI_CTL register to disable Byte Reorder function.
255 * \hideinitializer
256 */
257 #define SPI_DISABLE_BYTE_REORDER(spi) ((spi)->CTL &= ~SPI_CTL_REORDER_Msk)
258
259 /**
260 * @brief Set the length of suspend interval.
261 * @param[in] spi The pointer of the specified SPI module.
262 * @param[in] u32SuspCycle Decides the length of suspend interval. It could be 0 ~ 15.
263 * @return None.
264 * @details Set the length of suspend interval according to u32SuspCycle.
265 * The length of suspend interval is ((u32SuspCycle + 0.5) * the length of one SPI bus clock cycle).
266 * \hideinitializer
267 */
268 #define SPI_SET_SUSPEND_CYCLE(spi, u32SuspCycle) ((spi)->CTL = ((spi)->CTL & ~SPI_CTL_SUSPITV_Msk) | ((u32SuspCycle) << SPI_CTL_SUSPITV_Pos))
269
270 /**
271 * @brief Set the SPI transfer sequence with LSB first.
272 * @param[in] spi The pointer of the specified SPI module.
273 * @return None.
274 * @details Set LSB bit of SPI_CTL register to set the SPI transfer sequence with LSB first.
275 * \hideinitializer
276 */
277 #define SPI_SET_LSB_FIRST(spi) ((spi)->CTL |= SPI_CTL_LSB_Msk)
278
279 /**
280 * @brief Set the SPI transfer sequence with MSB first.
281 * @param[in] spi The pointer of the specified SPI module.
282 * @return None.
283 * @details Clear LSB bit of SPI_CTL register to set the SPI transfer sequence with MSB first.
284 * \hideinitializer
285 */
286 #define SPI_SET_MSB_FIRST(spi) ((spi)->CTL &= ~SPI_CTL_LSB_Msk)
287
288 /**
289 * @brief Set the data width of a SPI transaction.
290 * @param[in] spi The pointer of the specified SPI module.
291 * @param[in] u32Width The bit width of one transaction.
292 * @return None.
293 * @details The data width can be 8 ~ 32 bits.
294 * \hideinitializer
295 */
296 #define SPI_SET_DATA_WIDTH(spi, u32Width) ((spi)->CTL = ((spi)->CTL & ~SPI_CTL_DWIDTH_Msk) | (((u32Width)&0x1F) << SPI_CTL_DWIDTH_Pos))
297
298 /**
299 * @brief Get the SPI busy state.
300 * @param[in] spi The pointer of the specified SPI module.
301 * @retval 0 SPI controller is not busy.
302 * @retval 1 SPI controller is busy.
303 * @details This macro will return the busy state of SPI controller.
304 * \hideinitializer
305 */
306 #define SPI_IS_BUSY(spi) ( ((spi)->STATUS & SPI_STATUS_BUSY_Msk)>>SPI_STATUS_BUSY_Pos )
307
308 /**
309 * @brief Enable SPI controller.
310 * @param[in] spi The pointer of the specified SPI module.
311 * @return None.
312 * @details Set SPIEN (SPI_CTL[0]) to enable SPI controller.
313 * \hideinitializer
314 */
315 #define SPI_ENABLE(spi) ((spi)->CTL |= SPI_CTL_SPIEN_Msk)
316
317 /**
318 * @brief Disable SPI controller.
319 * @param[in] spi The pointer of the specified SPI module.
320 * @return None.
321 * @details Clear SPIEN (SPI_CTL[0]) to disable SPI controller.
322 * \hideinitializer
323 */
324 #define SPI_DISABLE(spi) ((spi)->CTL &= ~SPI_CTL_SPIEN_Msk)
325
326 /* Declare these inline functions here to avoid MISRA C 2004 rule 8.1 error */
327 __STATIC_INLINE void SPII2S_ENABLE_TX_ZCD(SPI_T *i2s, uint32_t u32ChMask);
328 __STATIC_INLINE void SPII2S_DISABLE_TX_ZCD(SPI_T *i2s, uint32_t u32ChMask);
329 __STATIC_INLINE void SPII2S_SET_MONO_RX_CHANNEL(SPI_T *i2s, uint32_t u32Ch);
330
331 /**
332 * @brief Enable zero cross detection function.
333 * @param[in] i2s The pointer of the specified I2S module.
334 * @param[in] u32ChMask The mask for left or right channel. Valid values are:
335 * - \ref SPII2S_RIGHT
336 * - \ref SPII2S_LEFT
337 * @return None
338 * @details This function will set RZCEN or LZCEN bit of SPI_I2SCTL register to enable zero cross detection function.
339 */
SPII2S_ENABLE_TX_ZCD(SPI_T * i2s,uint32_t u32ChMask)340 __STATIC_INLINE void SPII2S_ENABLE_TX_ZCD(SPI_T *i2s, uint32_t u32ChMask)
341 {
342 if(u32ChMask == SPII2S_RIGHT)
343 {
344 i2s->I2SCTL |= SPI_I2SCTL_RZCEN_Msk;
345 }
346 else
347 {
348 i2s->I2SCTL |= SPI_I2SCTL_LZCEN_Msk;
349 }
350 }
351
352 /**
353 * @brief Disable zero cross detection function.
354 * @param[in] i2s The pointer of the specified I2S module.
355 * @param[in] u32ChMask The mask for left or right channel. Valid values are:
356 * - \ref SPII2S_RIGHT
357 * - \ref SPII2S_LEFT
358 * @return None
359 * @details This function will clear RZCEN or LZCEN bit of SPI_I2SCTL register to disable zero cross detection function.
360 */
SPII2S_DISABLE_TX_ZCD(SPI_T * i2s,uint32_t u32ChMask)361 __STATIC_INLINE void SPII2S_DISABLE_TX_ZCD(SPI_T *i2s, uint32_t u32ChMask)
362 {
363 if(u32ChMask == SPII2S_RIGHT)
364 {
365 i2s->I2SCTL &= ~SPI_I2SCTL_RZCEN_Msk;
366 }
367 else
368 {
369 i2s->I2SCTL &= ~SPI_I2SCTL_LZCEN_Msk;
370 }
371 }
372
373 /**
374 * @brief Enable I2S TX DMA function.
375 * @param[in] i2s The pointer of the specified I2S module.
376 * @return None
377 * @details This macro will set TXPDMAEN bit of SPI_PDMACTL register to transmit data with PDMA.
378 * \hideinitializer
379 */
380 #define SPII2S_ENABLE_TXDMA(i2s) ( (i2s)->PDMACTL |= SPI_PDMACTL_TXPDMAEN_Msk )
381
382 /**
383 * @brief Disable I2S TX DMA function.
384 * @param[in] i2s The pointer of the specified I2S module.
385 * @return None
386 * @details This macro will clear TXPDMAEN bit of SPI_PDMACTL register to disable TX DMA function.
387 * \hideinitializer
388 */
389 #define SPII2S_DISABLE_TXDMA(i2s) ( (i2s)->PDMACTL &= ~SPI_PDMACTL_TXPDMAEN_Msk )
390
391 /**
392 * @brief Enable I2S RX DMA function.
393 * @param[in] i2s The pointer of the specified I2S module.
394 * @return None
395 * @details This macro will set RXPDMAEN bit of SPI_PDMACTL register to receive data with PDMA.
396 * \hideinitializer
397 */
398 #define SPII2S_ENABLE_RXDMA(i2s) ( (i2s)->PDMACTL |= SPI_PDMACTL_RXPDMAEN_Msk )
399
400 /**
401 * @brief Disable I2S RX DMA function.
402 * @param[in] i2s The pointer of the specified I2S module.
403 * @return None
404 * @details This macro will clear RXPDMAEN bit of SPI_PDMACTL register to disable RX DMA function.
405 * \hideinitializer
406 */
407 #define SPII2S_DISABLE_RXDMA(i2s) ( (i2s)->PDMACTL &= ~SPI_PDMACTL_RXPDMAEN_Msk )
408
409 /**
410 * @brief Enable I2S TX function.
411 * @param[in] i2s The pointer of the specified I2S module.
412 * @return None
413 * @details This macro will set TXEN bit of SPI_I2SCTL register to enable I2S TX function.
414 * \hideinitializer
415 */
416 #define SPII2S_ENABLE_TX(i2s) ( (i2s)->I2SCTL |= SPI_I2SCTL_TXEN_Msk )
417
418 /**
419 * @brief Disable I2S TX function.
420 * @param[in] i2s The pointer of the specified I2S module.
421 * @return None
422 * @details This macro will clear TXEN bit of SPI_I2SCTL register to disable I2S TX function.
423 * \hideinitializer
424 */
425 #define SPII2S_DISABLE_TX(i2s) ( (i2s)->I2SCTL &= ~SPI_I2SCTL_TXEN_Msk )
426
427 /**
428 * @brief Enable I2S RX function.
429 * @param[in] i2s The pointer of the specified I2S module.
430 * @return None
431 * @details This macro will set RXEN bit of SPI_I2SCTL register to enable I2S RX function.
432 * \hideinitializer
433 */
434 #define SPII2S_ENABLE_RX(i2s) ( (i2s)->I2SCTL |= SPI_I2SCTL_RXEN_Msk )
435
436 /**
437 * @brief Disable I2S RX function.
438 * @param[in] i2s The pointer of the specified I2S module.
439 * @return None
440 * @details This macro will clear RXEN bit of SPI_I2SCTL register to disable I2S RX function.
441 * \hideinitializer
442 */
443 #define SPII2S_DISABLE_RX(i2s) ( (i2s)->I2SCTL &= ~SPI_I2SCTL_RXEN_Msk )
444
445 /**
446 * @brief Enable TX Mute function.
447 * @param[in] i2s The pointer of the specified I2S module.
448 * @return None
449 * @details This macro will set MUTE bit of SPI_I2SCTL register to enable I2S TX mute function.
450 * \hideinitializer
451 */
452 #define SPII2S_ENABLE_TX_MUTE(i2s) ( (i2s)->I2SCTL |= SPI_I2SCTL_MUTE_Msk )
453
454 /**
455 * @brief Disable TX Mute function.
456 * @param[in] i2s The pointer of the specified I2S module.
457 * @return None
458 * @details This macro will clear MUTE bit of SPI_I2SCTL register to disable I2S TX mute function.
459 * \hideinitializer
460 */
461 #define SPII2S_DISABLE_TX_MUTE(i2s) ( (i2s)->I2SCTL &= ~SPI_I2SCTL_MUTE_Msk )
462
463 /**
464 * @brief Clear TX FIFO.
465 * @param[in] i2s The pointer of the specified I2S module.
466 * @return None
467 * @details This macro will clear TX FIFO. The internal TX FIFO pointer will be reset to FIFO start point.
468 * \hideinitializer
469 */
470 #define SPII2S_CLR_TX_FIFO(i2s) ( (i2s)->FIFOCTL |= SPI_FIFOCTL_TXFBCLR_Msk )
471
472 /**
473 * @brief Clear RX FIFO.
474 * @param[in] i2s The pointer of the specified I2S module.
475 * @return None
476 * @details This macro will clear RX FIFO. The internal RX FIFO pointer will be reset to FIFO start point.
477 * \hideinitializer
478 */
479 #define SPII2S_CLR_RX_FIFO(i2s) ( (i2s)->FIFOCTL |= SPI_FIFOCTL_RXFBCLR_Msk )
480
481 /**
482 * @brief This function sets the recording source channel when mono mode is used.
483 * @param[in] i2s The pointer of the specified I2S module.
484 * @param[in] u32Ch left or right channel. Valid values are:
485 * - \ref SPII2S_MONO_LEFT
486 * - \ref SPII2S_MONO_RIGHT
487 * @return None
488 * @details This function selects the recording source channel of monaural mode.
489 * \hideinitializer
490 */
SPII2S_SET_MONO_RX_CHANNEL(SPI_T * i2s,uint32_t u32Ch)491 __STATIC_INLINE void SPII2S_SET_MONO_RX_CHANNEL(SPI_T *i2s, uint32_t u32Ch)
492 {
493 u32Ch == SPII2S_MONO_LEFT ?
494 (i2s->I2SCTL |= SPI_I2SCTL_RXLCH_Msk) :
495 (i2s->I2SCTL &= ~SPI_I2SCTL_RXLCH_Msk);
496 }
497
498 /**
499 * @brief Write data to I2S TX FIFO.
500 * @param[in] i2s The pointer of the specified I2S module.
501 * @param[in] u32Data The value written to TX FIFO.
502 * @return None
503 * @details This macro will write a value to TX FIFO.
504 * \hideinitializer
505 */
506 #define SPII2S_WRITE_TX_FIFO(i2s, u32Data) ( (i2s)->TX = (u32Data) )
507
508 /**
509 * @brief Read RX FIFO.
510 * @param[in] i2s The pointer of the specified I2S module.
511 * @return The value read from RX FIFO.
512 * @details This function will return a value read from RX FIFO.
513 * \hideinitializer
514 */
515 #define SPII2S_READ_RX_FIFO(i2s) ( (i2s)->RX )
516
517 /**
518 * @brief Get the interrupt flag.
519 * @param[in] i2s The pointer of the specified I2S module.
520 * @param[in] u32Mask The mask value for all interrupt flags.
521 * @return The interrupt flags specified by the u32mask parameter.
522 * @details This macro will return the combination interrupt flags of SPI_I2SSTS register. The flags are specified by the u32mask parameter.
523 * \hideinitializer
524 */
525 #define SPII2S_GET_INT_FLAG(i2s, u32Mask) ( (i2s)->I2SSTS & (u32Mask) )
526
527 /**
528 * @brief Clear the interrupt flag.
529 * @param[in] i2s The pointer of the specified I2S module.
530 * @param[in] u32Mask The mask value for all interrupt flags.
531 * @return None
532 * @details This macro will clear the interrupt flags specified by the u32mask parameter.
533 * @note Except TX and RX FIFO threshold interrupt flags, the other interrupt flags can be cleared by writing 1 to itself.
534 * \hideinitializer
535 */
536 #define SPII2S_CLR_INT_FLAG(i2s, u32Mask) ( (i2s)->I2SSTS = (u32Mask) )
537
538 /**
539 * @brief Get transmit FIFO level
540 * @param[in] i2s The pointer of the specified I2S module.
541 * @return TX FIFO level
542 * @details This macro will return the number of available words in TX FIFO.
543 * \hideinitializer
544 */
545 #define SPII2S_GET_TX_FIFO_LEVEL(i2s) ( ((i2s)->I2SSTS & SPI_I2SSTS_TXCNT_Msk) >> SPI_I2SSTS_TXCNT_Pos )
546
547 /**
548 * @brief Get receive FIFO level
549 * @param[in] i2s The pointer of the specified I2S module.
550 * @return RX FIFO level
551 * @details This macro will return the number of available words in RX FIFO.
552 * \hideinitializer
553 */
554 #define SPII2S_GET_RX_FIFO_LEVEL(i2s) ( ((i2s)->I2SSTS & SPI_I2SSTS_RXCNT_Msk) >> SPI_I2SSTS_RXCNT_Pos )
555
556
557
558 /* Function prototype declaration */
559 uint32_t SPI_Open(SPI_T *spi, uint32_t u32MasterSlave, uint32_t u32SPIMode, uint32_t u32DataWidth, uint32_t u32BusClock);
560 void SPI_Close(SPI_T *spi);
561 void SPI_ClearRxFIFO(SPI_T *spi);
562 void SPI_ClearTxFIFO(SPI_T *spi);
563 void SPI_DisableAutoSS(SPI_T *spi);
564 void SPI_EnableAutoSS(SPI_T *spi, uint32_t u32SSPinMask, uint32_t u32ActiveLevel);
565 uint32_t SPI_SetBusClock(SPI_T *spi, uint32_t u32BusClock);
566 void SPI_SetFIFO(SPI_T *spi, uint32_t u32TxThreshold, uint32_t u32RxThreshold);
567 uint32_t SPI_GetBusClock(SPI_T *spi);
568 void SPI_EnableInt(SPI_T *spi, uint32_t u32Mask);
569 void SPI_DisableInt(SPI_T *spi, uint32_t u32Mask);
570 uint32_t SPI_GetIntFlag(SPI_T *spi, uint32_t u32Mask);
571 void SPI_ClearIntFlag(SPI_T *spi, uint32_t u32Mask);
572 uint32_t SPI_GetStatus(SPI_T *spi, uint32_t u32Mask);
573
574 uint32_t SPII2S_Open(SPI_T *i2s, uint32_t u32MasterSlave, uint32_t u32SampleRate, uint32_t u32WordWidth, uint32_t u32Channels, uint32_t u32DataFormat);
575 void SPII2S_Close(SPI_T *i2s);
576 void SPII2S_EnableInt(SPI_T *i2s, uint32_t u32Mask);
577 void SPII2S_DisableInt(SPI_T *i2s, uint32_t u32Mask);
578 uint32_t SPII2S_EnableMCLK(SPI_T *i2s, uint32_t u32BusClock);
579 void SPII2S_DisableMCLK(SPI_T *i2s);
580 void SPII2S_SetFIFO(SPI_T *i2s, uint32_t u32TxThreshold, uint32_t u32RxThreshold);
581
582
583 /*@}*/ /* end of group SPI_EXPORTED_FUNCTIONS */
584
585 /*@}*/ /* end of group SPI_Driver */
586
587 /*@}*/ /* end of group Standard_Driver */
588
589 #ifdef __cplusplus
590 }
591 #endif
592
593 #endif
594
595 /*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/
596
